From 047e58bc357c9dc3057e67931baae0ee94c28e8a Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jeremy@system76.com>
Date: Wed, 18 Nov 2020 21:13:15 -0700
Subject: [PATCH] Move CPU AER and PTM config to mainboard

Change-Id: Idd7908426e33a64afa34ea9e5d02ec7378a56271
---
 src/mainboard/system76/galp5/ramstage.c  | 4 ++++
 src/mainboard/system76/lemp10/ramstage.c | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/src/mainboard/system76/galp5/ramstage.c b/src/mainboard/system76/galp5/ramstage.c
index 9d436fc5f3..1f212147a8 100644
--- a/src/mainboard/system76/galp5/ramstage.c
+++ b/src/mainboard/system76/galp5/ramstage.c
@@ -4,5 +4,9 @@
 #include "gpio.h"
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *params) {
+	// CPU RP Config
+	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
+	params->CpuPcieRpPtmEnabled[0] = 0;
+
 	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 }
diff --git a/src/mainboard/system76/lemp10/ramstage.c b/src/mainboard/system76/lemp10/ramstage.c
index 9d436fc5f3..1f212147a8 100644
--- a/src/mainboard/system76/lemp10/ramstage.c
+++ b/src/mainboard/system76/lemp10/ramstage.c
@@ -4,5 +4,9 @@
 #include "gpio.h"
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *params) {
+	// CPU RP Config
+	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
+	params->CpuPcieRpPtmEnabled[0] = 0;
+
 	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 }