Inteltool: Add i830/Tolapai/Ich4 support
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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committed by
Stefan Reinauer
parent
881a553000
commit
04844816ac
@@ -1,7 +1,7 @@
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/*
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* inteltool - dump all registers on an Intel CPU + chipset based system.
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*
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* Copyright (C) 2008 by coresystems GmbH
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* Copyright (C) 2008-2010 by coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@@ -97,6 +97,67 @@ int print_intel_core_msrs(void)
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char *name;
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} msr_entry_t;
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static const msr_entry_t model6bx_global_msrs[] = {
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{ 0x0010, "IA32_TIME_STAMP_COUNTER" },
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{ 0x0017, "IA32_PLATFORM_ID" },
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{ 0x001b, "IA32_APIC_BASE" },
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{ 0x002a, "EBL_CR_POWERON" },
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{ 0x0033, "TEST_CTL" },
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{ 0x003f, "THERM_DIODE_OFFSET" },
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//{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
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{ 0x008b, "IA32_BIOS_SIGN_ID" },
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{ 0x00c1, "PERFCTR0" },
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{ 0x00c2, "PERFCTR1" },
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{ 0x011e, "BBL_CR_CTL3" },
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{ 0x0179, "IA32_MCG_CAP" },
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{ 0x017a, "IA32_MCG_STATUS" },
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{ 0x0198, "IA32_PERF_STATUS" },
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{ 0x0199, "IA32_PERF_CONTROL" },
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{ 0x019a, "IA32_CLOCK_MODULATION" },
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{ 0x01a0, "IA32_MISC_ENABLES" },
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{ 0x01d9, "IA32_DEBUGCTL" },
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{ 0x0200, "IA32_MTRR_PHYSBASE0" },
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{ 0x0201, "IA32_MTRR_PHYSMASK0" },
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{ 0x0202, "IA32_MTRR_PHYSBASE1" },
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{ 0x0203, "IA32_MTRR_PHYSMASK1" },
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{ 0x0204, "IA32_MTRR_PHYSBASE2" },
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{ 0x0205, "IA32_MTRR_PHYSMASK2" },
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{ 0x0206, "IA32_MTRR_PHYSBASE3" },
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{ 0x0207, "IA32_MTRR_PHYSMASK3" },
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{ 0x0208, "IA32_MTRR_PHYSBASE4" },
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{ 0x0209, "IA32_MTRR_PHYSMASK4" },
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{ 0x020a, "IA32_MTRR_PHYSBASE5" },
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{ 0x020b, "IA32_MTRR_PHYSMASK5" },
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{ 0x020c, "IA32_MTRR_PHYSBASE6" },
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{ 0x020d, "IA32_MTRR_PHYSMASK6" },
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{ 0x020e, "IA32_MTRR_PHYSBASE7" },
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{ 0x020f, "IA32_MTRR_PHYSMASK7" },
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{ 0x0250, "IA32_MTRR_FIX64K_00000" },
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{ 0x0258, "IA32_MTRR_FIX16K_80000" },
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{ 0x0259, "IA32_MTRR_FIX16K_A0000" },
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{ 0x0268, "IA32_MTRR_FIX4K_C0000" },
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{ 0x0269, "IA32_MTRR_FIX4K_C8000" },
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{ 0x026a, "IA32_MTRR_FIX4K_D0000" },
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{ 0x026b, "IA32_MTRR_FIX4K_D8000" },
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{ 0x026c, "IA32_MTRR_FIX4K_E0000" },
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{ 0x026d, "IA32_MTRR_FIX4K_E8000" },
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{ 0x026e, "IA32_MTRR_FIX4K_F0000" },
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{ 0x026f, "IA32_MTRR_FIX4K_F8000" },
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{ 0x02ff, "IA32_MTRR_DEF_TYPE" },
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{ 0x0400, "IA32_MC0_CTL" },
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{ 0x0401, "IA32_MC0_STATUS" },
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{ 0x0402, "IA32_MC0_ADDR" },
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//{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
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{ 0x040c, "IA32_MC4_CTL" },
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{ 0x040d, "IA32_MC4_STATUS" },
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{ 0x040e, "IA32_MC4_ADDR" },
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//{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
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};
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static const msr_entry_t model6bx_per_core_msrs[] = {
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// single core only
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};
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static const msr_entry_t model6ex_global_msrs[] = {
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{ 0x0017, "IA32_PLATFORM_ID" },
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{ 0x002a, "EBL_CR_POWERON" },
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@@ -259,6 +320,7 @@ int print_intel_core_msrs(void)
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} cpu_t;
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cpu_t cpulist[] = {
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{ 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 },
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{ 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) },
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{ 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) },
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};
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@@ -315,7 +377,8 @@ int print_intel_core_msrs(void)
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if (fd_msr < 0)
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break;
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#endif
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printf("\n====================== UNIQUE MSRs (core %d) ======================\n", core);
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if (cpu->num_per_core_msrs)
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printf("\n====================== UNIQUE MSRs (core %d) ======================\n", core);
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for (i = 0; i < cpu->num_per_core_msrs; i++) {
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msr = rdmsr(cpu->per_core_msrs[i].number);
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