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soc/intel/tigerlake: Update iDisp Link UPD settings

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Remove explicit setting of iDisp Link parameters. These settings are
related to configuration for the link between HD-Audio controller and
Display unit for purposes of HDMI/DP Audio playback. During PO,
observed that without setting these params display part was not
binding. With the latest code verified that we dont need to explicitly
set these parameters anymore. HDMI/DP audio playback works fine with
default settings.

BUG=b:151451125
BRANCH:none
TEST= build and boot volteer/ripto and verify HDMI/DP audio playback

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ie003d119918d363e2ff9172936b70416fd73c7f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40263
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jairaj Arava <jairaj.arava@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Srinidhi N Kaushik
2020-04-07 21:02:07 -07:00
committed by Patrick Georgi
parent 1b457f8517
commit 04a8cfbbc0
5 changed files with 0 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View File

@@ -121,12 +121,6 @@ chip soc/intel/tigerlake
register "PchHdaAudioLinkSspEnable[1]" = "0"
register "PchHdaAudioLinkSspEnable[2]" = "1"
register "PchHdaAudioLinkSndwEnable[0]" = "1"
# iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
register "PchHdaIDispLinkTmode" = "2"
# iDisp-Link Freq 4: 96MHz, 3: 48MHz.
register "PchHdaIDispLinkFrequency" = "4"
# Not disconnected/enumerable
register "PchHdaIDispCodecDisconnect" = "0"
# Intel Common SoC Config
register "common_soc_config" = "{

6
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@@ -117,12 +117,6 @@ chip soc/intel/tigerlake
register "PchHdaAudioLinkSspEnable[1]" = "0"
register "PchHdaAudioLinkSspEnable[2]" = "1"
register "PchHdaAudioLinkSndwEnable[0]" = "1"
# iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
register "PchHdaIDispLinkTmode" = "2"
# iDisp-Link Freq 4: 96MHz, 3: 48MHz.
register "PchHdaIDispLinkFrequency" = "4"
# Not disconnected/enumerable
register "PchHdaIDispCodecDisconnect" = "0"
# Intel Common SoC Config
register "common_soc_config" = "{