exynos5250: Fix PMU register address map
Patch 12b121f3fef61d introduced an off-by-one error in the offsets of the PMU register struct, which put both the newly added register and the PSHOLD that comes after it in the wrong place. This patch corrects the offsets (5420 had already been correct). Change-Id: I1d9d31a6a73ee91890824e94fbd247d5feb4f6ae Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179411 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 5fdc74bc18bcb1066a0ce3ba94829af1b175173b) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6892 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -58,8 +58,8 @@ struct exynos5_power {
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uint32_t inform0; /* 0x0800 */
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uint32_t inform0; /* 0x0800 */
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uint32_t inform1; /* 0x0804 */
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uint32_t inform1; /* 0x0804 */
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uint8_t reserved6[0x1f8];
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uint8_t reserved6[0x1f8];
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uint32_t pmu_debug; /* 0x0A00*/
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uint32_t pmu_debug; /* 0x0a00 */
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uint8_t reserved7[0x2728];
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uint8_t reserved7[0x2724];
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uint32_t padret_uart_opt; /* 0x3128 */
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uint32_t padret_uart_opt; /* 0x3128 */
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uint8_t reserved8[0x1e0];
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uint8_t reserved8[0x1e0];
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uint32_t ps_hold_ctrl; /* 0x330c */
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uint32_t ps_hold_ctrl; /* 0x330c */
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