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oryp6: Set M.2 and LAN power and reset lines to reset with RSMRST to avoid glitching during reboots

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This commit is contained in:
Jeremy Soller 2020-06-29 10:12:23 -06:00
parent 87a74eb767
commit 04c88e9113
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GPG Key ID: E988B49EE78A7FB1
1 changed files with 10 additions and 10 deletions
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20
src/mainboard/system76/oryp6/gpio.h
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@ -13,13 +13,13 @@
/* Pad configuration in romstage. */ /* Pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP), // M.2_PLT_RST_CNTRL1# PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, RSMRST), // M.2_PLT_RST_CNTRL1#
PAD_CFG_TERM_GPO(GPP_C15, 1, NONE, DEEP), // M.2_PLT_RST_CNTRL2# PAD_CFG_TERM_GPO(GPP_C15, 1, NONE, RSMRST), // M.2_PLT_RST_CNTRL2#
PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP), // DGPU_RST_N PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP), // DGPU_RST_N
PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // DGPU_PWR_EN PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // DGPU_PWR_EN
PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP), // SATA_M2_PWR_EN1 PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, RSMRST), // SATA_M2_PWR_EN1
PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, DEEP), // SATA_M2_PWR_EN2 PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, RSMRST), // SATA_M2_PWR_EN2
PAD_CFG_TERM_GPO(GPP_K11, 1, NONE, DEEP), // GPIO_LANRTD3 PAD_CFG_TERM_GPO(GPP_K11, 1, NONE, RSMRST), // GPIO_LANRTD3
}; };
/* Pad configuration in ramstage. */ /* Pad configuration in ramstage. */
@ -98,8 +98,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_C11, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_C11, UP_20K, DEEP), // NC
PAD_CFG_GPI(GPP_C12, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_C12, UP_20K, DEEP), // NC
PAD_CFG_GPI(GPP_C13, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_C13, UP_20K, DEEP), // NC
PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP), // M.2_PLT_RST_CNTRL1# PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, RSMRST), // M.2_PLT_RST_CNTRL1#
PAD_CFG_TERM_GPO(GPP_C15, 1, NONE, DEEP), // M.2_PLT_RST_CNTRL2# PAD_CFG_TERM_GPO(GPP_C15, 1, NONE, RSMRST), // M.2_PLT_RST_CNTRL2#
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // I2C_SDA_TP PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // I2C_SDA_TP
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // I2C_SCL_TP PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // I2C_SCL_TP
PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // I2C_SDA_Pantone PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // I2C_SDA_Pantone
@ -235,10 +235,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_K5, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_K5, UP_20K, DEEP), // NC
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI# _PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#
PAD_CFG_GPI(GPP_K7, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_K7, UP_20K, DEEP), // NC
PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP), // SATA_M2_PWR_EN1 PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, RSMRST), // SATA_M2_PWR_EN1
PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, DEEP), // SATA_M2_PWR_EN2 PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, RSMRST), // SATA_M2_PWR_EN2
PAD_CFG_TERM_GPO(GPP_K10, 1, NONE, DEEP), // LANRTD3_WAKE# PAD_CFG_TERM_GPO(GPP_K10, 1, NONE, DEEP), // LANRTD3_WAKE#
PAD_CFG_TERM_GPO(GPP_K11, 1, NONE, DEEP), // GPIO_LANRTD3 PAD_CFG_TERM_GPO(GPP_K11, 1, NONE, RSMRST), // GPIO_LANRTD3
PAD_CFG_GPI(GPP_K12, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_K12, UP_20K, DEEP), // NC
PAD_CFG_GPI(GPP_K13, UP_20K, DEEP), // NC PAD_CFG_GPI(GPP_K13, UP_20K, DEEP), // NC
PAD_CFG_GPI(GPP_K14, UP_20K, DEEP), // GPP_K_14_GSXDIN (test point) PAD_CFG_GPI(GPP_K14, UP_20K, DEEP), // GPP_K_14_GSXDIN (test point)