sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/zork,soc/amd/psp_verstage: Add verstage_mb_{tpm/espi}_init

Browse Source 
These functions can't be weak, because they actually need to configure
the GPIOs for eSPI and the TPM. With this change zork boots again.

I also noticed that zork doesn't use the early table in bootblock. This
means that zork will only boot if psp_verstage is enabled.

BUG=b:209465425
TEST=boot zork to ramstage

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I384fd578efe7da0a3d74829cccf38c3ed524f130
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
This commit is contained in:
Raul E Rangel
2021-12-06 12:15:45 -07:00
committed by Felix Held
parent 6ebcdf3872
commit 04cf42775c
5 changed files with 85 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
View File

@@ -311,25 +311,43 @@ const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp
return gpio_sleep_table;
}
static const struct soc_amd_gpio early_gpio_table[] = {
/* H1_FCH_INT_ODL */
PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS),
/* I2C3_SCL - H1 */
PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE),
/* I2C3_SDA - H1 */
PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
static const struct soc_amd_gpio espi_gpio_table[] = {
/* PCIE_RST0_L - Fixed timings */
PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
/* FCH_ESPI_EC_CS_L */
PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
/* ESPI_ALERT_L */
PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_NONE),
};
const __weak struct soc_amd_gpio *variant_espi_gpio_table(size_t *size)
{
*size = ARRAY_SIZE(espi_gpio_table);
return espi_gpio_table;
}
static const struct soc_amd_gpio tpm_gpio_table[] = {
/* H1_FCH_INT_ODL */
PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS),
/* I2C3_SCL - H1 */
PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE),
/* I2C3_SDA - H1 */
PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
/* EC_IN_RW_OD */
PAD_GPI(GPIO_11, PULL_NONE),
};
const __weak struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size)
{
*size = ARRAY_SIZE(tpm_gpio_table);
return tpm_gpio_table;
}
static const struct soc_amd_gpio early_gpio_table[] = {
/* UART0_RXD - DEBUG */
PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),
/* UART0_TXD - DEBUG */
PAD_NF(GPIO_138, UART0_TXD, PULL_NONE),
/* EC_IN_RW_OD */
PAD_GPI(GPIO_11, PULL_NONE),
};
const struct soc_amd_gpio *variant_early_gpio_table(size_t *size)

36
src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
View File

@@ -360,25 +360,43 @@ const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp
return gpio_sleep_table;
}
static const struct soc_amd_gpio early_gpio_table[] = {
/* H1_FCH_INT_ODL */
PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS),
/* I2C3_SCL - H1 */
PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE),
/* I2C3_SDA - H1 */
PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
static const struct soc_amd_gpio espi_gpio_table[] = {
/* PCIE_RST0_L - Fixed timings */
PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
/* FCH_ESPI_EC_CS_L */
PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
/* ESPI_ALERT_L */
PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_NONE),
};
const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size)
{
*size = ARRAY_SIZE(espi_gpio_table);
return espi_gpio_table;
}
static const struct soc_amd_gpio tpm_gpio_table[] = {
/* H1_FCH_INT_ODL */
PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS),
/* I2C3_SCL - H1 */
PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE),
/* I2C3_SDA - H1 */
PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
/* EC_IN_RW_OD */
PAD_GPI(GPIO_130, PULL_NONE),
};
const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size)
{
*size = ARRAY_SIZE(tpm_gpio_table);
return tpm_gpio_table;
}
static const struct soc_amd_gpio early_gpio_table[] = {
/* UART0_RXD - DEBUG */
PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),
/* UART0_TXD - DEBUG */
PAD_NF(GPIO_138, UART0_TXD, PULL_NONE),
/* EC_IN_RW_OD */
PAD_GPI(GPIO_130, PULL_NONE),
};
const struct soc_amd_gpio *variant_early_gpio_table(size_t *size)

6
src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
View File

@@ -33,6 +33,12 @@ const struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int slp_ty
*/
const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ);
/* This function provides GPIO settings for eSPI bus. */
const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size);
/* This function provides GPIO settings for TPM i2c bus. */
const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size);
void variant_updm_update(FSP_M_CONFIG *mcfg);
/* Program any required GPIOs at the finalize phase */

25
src/mainboard/google/zork/verstage.c
View File

@@ -2,6 +2,7 @@
#include <amdblocks/gpio.h>
#include <baseboard/variants.h>
#include <psp_verstage.h>
#include <security/vboot/vboot_common.h>
static void setup_gpio(void)
@@ -19,3 +20,27 @@ void verstage_mainboard_early_init(void)
{
setup_gpio();
}
void verstage_mainboard_espi_init(void)
{
const struct soc_amd_gpio *gpios;
size_t num_gpios;
if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))
return;
gpios = variant_espi_gpio_table(&num_gpios);
gpio_configure_pads(gpios, num_gpios);
}
void verstage_mainboard_tpm_init(void)
{
const struct soc_amd_gpio *gpios;
size_t num_gpios;
if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))
return;
gpios = variant_tpm_gpio_table(&num_gpios);
gpio_configure_pads(gpios, num_gpios);
}

3
src/soc/amd/common/psp_verstage/psp_verstage.c
View File

@@ -25,9 +25,6 @@
extern char _bss_start, _bss_end;
void __weak verstage_mainboard_early_init(void) {}
void __weak verstage_mainboard_espi_init(void) {}
void __weak verstage_mainboard_tpm_init(void) {}
void __weak verstage_mainboard_init(void) {}
uint32_t __weak get_max_workbuf_size(uint32_t *size)