drivers/aspeed: Add native text mode VGA support for the AST2050
Change-Id: I37763a59d2546cd0c0e57b31fdb7aa77c2c50bee Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11937 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
This commit is contained in:
Timothy Pearson
committed by
Peter Stuge
Peter Stuge
parent
c3fcdccb81
commit
04cf449e77
398
src/drivers/aspeed/common/ast_dp501.c
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398
src/drivers/aspeed/common/ast_dp501.c
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/*
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* This file is part of the coreboot project.
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*
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* File taken from the Linux ast driver (v3.18.5)
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* Coreboot-specific includes added at top and/or contents modified
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* as needed to function within the coreboot environment.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include "ast_drv.h"
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static void send_ack(struct ast_private *ast)
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{
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u8 sendack;
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sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff);
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sendack |= 0x80;
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
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}
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static void send_nack(struct ast_private *ast)
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{
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u8 sendack;
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sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff);
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sendack &= ~0x80;
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
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}
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static bool wait_ack(struct ast_private *ast)
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{
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u8 waitack;
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u32 retry = 0;
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do {
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waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
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waitack &= 0x80;
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udelay(100);
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} while ((!waitack) && (retry++ < 1000));
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if (retry < 1000)
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return true;
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else
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return false;
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}
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static bool wait_nack(struct ast_private *ast)
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{
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u8 waitack;
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u32 retry = 0;
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do {
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waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
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waitack &= 0x80;
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udelay(100);
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} while ((waitack) && (retry++ < 1000));
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if (retry < 1000)
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return true;
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else
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return false;
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}
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static void set_cmd_trigger(struct ast_private *ast)
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{
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x40);
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}
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static void clear_cmd_trigger(struct ast_private *ast)
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{
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x00);
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}
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static bool ast_write_cmd(struct drm_device *dev, u8 data)
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{
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struct ast_private *ast = dev->dev_private;
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int retry = 0;
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if (wait_nack(ast)) {
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send_nack(ast);
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
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send_ack(ast);
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set_cmd_trigger(ast);
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do {
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if (wait_ack(ast)) {
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clear_cmd_trigger(ast);
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send_nack(ast);
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return true;
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}
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} while (retry++ < 100);
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}
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clear_cmd_trigger(ast);
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send_nack(ast);
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return false;
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}
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static bool ast_write_data(struct drm_device *dev, u8 data)
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{
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struct ast_private *ast = dev->dev_private;
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if (wait_nack(ast)) {
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send_nack(ast);
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
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send_ack(ast);
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if (wait_ack(ast)) {
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send_nack(ast);
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return true;
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}
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}
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send_nack(ast);
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return false;
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}
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void ast_set_dp501_video_output(struct drm_device *dev, u8 mode)
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{
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ast_write_cmd(dev, 0x40);
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ast_write_data(dev, mode);
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msleep(10);
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}
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static u32 get_fw_base(struct ast_private *ast)
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{
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return ast_mindwm(ast, 0x1e6e2104) & 0x7fffffff;
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}
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bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size)
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{
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struct ast_private *ast = dev->dev_private;
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u32 i, data;
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u32 boot_address;
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data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
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if (data) {
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boot_address = get_fw_base(ast);
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for (i = 0; i < size; i += 4)
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*(u32 *)(addr + i) = ast_mindwm(ast, boot_address + i);
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return true;
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}
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return false;
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}
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bool ast_launch_m68k(struct drm_device *dev)
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{
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struct ast_private *ast = dev->dev_private;
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u32 i, data, len = 0;
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u32 boot_address;
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u8 *fw_addr = NULL;
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u8 jreg;
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data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
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if (!data) {
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if (ast->dp501_fw_addr) {
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fw_addr = ast->dp501_fw_addr;
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len = 32*1024;
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} else if (ast->dp501_fw) {
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fw_addr = (u8 *)ast->dp501_fw->data;
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len = ast->dp501_fw->size;
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}
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/* Get BootAddress */
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ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8);
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data = ast_mindwm(ast, 0x1e6e0004);
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switch (data & 0x03) {
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case 0:
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boot_address = 0x44000000;
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break;
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default:
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case 1:
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boot_address = 0x48000000;
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break;
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case 2:
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boot_address = 0x50000000;
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break;
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case 3:
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boot_address = 0x60000000;
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break;
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}
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boot_address -= 0x200000; /* -2MB */
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/* copy image to buffer */
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for (i = 0; i < len; i += 4) {
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data = *(u32 *)(fw_addr + i);
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ast_moutdwm(ast, boot_address + i, data);
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}
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/* Init SCU */
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ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8);
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/* Launch FW */
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ast_moutdwm(ast, 0x1e6e2104, 0x80000000 + boot_address);
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ast_moutdwm(ast, 0x1e6e2100, 1);
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/* Update Scratch */
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data = ast_mindwm(ast, 0x1e6e2040) & 0xfffff1ff; /* D[11:9] = 100b: UEFI handling */
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data |= 0x800;
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ast_moutdwm(ast, 0x1e6e2040, data);
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jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xfc); /* D[1:0]: Reserved Video Buffer */
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jreg |= 0x02;
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ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x99, jreg);
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}
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return true;
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}
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u8 ast_get_dp501_max_clk(struct drm_device *dev)
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{
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struct ast_private *ast = dev->dev_private;
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u32 boot_address, offset, data;
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u8 linkcap[4], linkrate, linklanes, maxclk = 0xff;
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boot_address = get_fw_base(ast);
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/* validate FW version */
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offset = 0xf000;
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data = ast_mindwm(ast, boot_address + offset);
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if ((data & 0xf0) != 0x10) /* version: 1x */
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return maxclk;
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/* Read Link Capability */
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offset = 0xf014;
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data = ast_mindwm(ast, boot_address + offset);
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linkcap[0] = (data & 0xff000000) >> 24;
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linkcap[1] = (data & 0x00ff0000) >> 16;
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linkcap[2] = (data & 0x0000ff00) >> 8;
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linkcap[3] = (data & 0x000000ff);
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if (linkcap[2] == 0) {
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linkrate = linkcap[0];
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linklanes = linkcap[1];
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data = (linkrate == 0x0a) ? (90 * linklanes) : (54 * linklanes);
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if (data > 0xff)
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data = 0xff;
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maxclk = (u8)data;
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}
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return maxclk;
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}
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bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata)
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{
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struct ast_private *ast = dev->dev_private;
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u32 i, boot_address, offset, data;
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boot_address = get_fw_base(ast);
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/* validate FW version */
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offset = 0xf000;
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data = ast_mindwm(ast, boot_address + offset);
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if ((data & 0xf0) != 0x10)
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return false;
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/* validate PnP Monitor */
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offset = 0xf010;
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data = ast_mindwm(ast, boot_address + offset);
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if (!(data & 0x01))
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return false;
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/* Read EDID */
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offset = 0xf020;
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for (i = 0; i < 128; i += 4) {
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data = ast_mindwm(ast, boot_address + offset + i);
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*(u32 *)(ediddata + i) = data;
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}
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return true;
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}
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static bool ast_init_dvo(struct drm_device *dev)
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{
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struct ast_private *ast = dev->dev_private;
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u8 jreg;
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u32 data;
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ast_write32(ast, 0xf004, 0x1e6e0000);
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ast_write32(ast, 0xf000, 0x1);
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ast_write32(ast, 0x12000, 0x1688a8a8);
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jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
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if (!(jreg & 0x80)) {
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/* Init SCU DVO Settings */
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data = ast_read32(ast, 0x12008);
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/* delay phase */
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data &= 0xfffff8ff;
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data |= 0x00000500;
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ast_write32(ast, 0x12008, data);
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if (ast->chip == AST2300) {
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data = ast_read32(ast, 0x12084);
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/* multi-pins for DVO single-edge */
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data |= 0xfffe0000;
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ast_write32(ast, 0x12084, data);
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data = ast_read32(ast, 0x12088);
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/* multi-pins for DVO single-edge */
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data |= 0x000fffff;
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ast_write32(ast, 0x12088, data);
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data = ast_read32(ast, 0x12090);
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/* multi-pins for DVO single-edge */
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data &= 0xffffffcf;
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data |= 0x00000020;
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ast_write32(ast, 0x12090, data);
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} else { /* AST2400 */
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data = ast_read32(ast, 0x12088);
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/* multi-pins for DVO single-edge */
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data |= 0x30000000;
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ast_write32(ast, 0x12088, data);
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data = ast_read32(ast, 0x1208c);
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/* multi-pins for DVO single-edge */
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data |= 0x000000cf;
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ast_write32(ast, 0x1208c, data);
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data = ast_read32(ast, 0x120a4);
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/* multi-pins for DVO single-edge */
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data |= 0xffff0000;
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ast_write32(ast, 0x120a4, data);
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data = ast_read32(ast, 0x120a8);
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/* multi-pins for DVO single-edge */
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data |= 0x0000000f;
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ast_write32(ast, 0x120a8, data);
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data = ast_read32(ast, 0x12094);
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/* multi-pins for DVO single-edge */
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data |= 0x00000002;
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ast_write32(ast, 0x12094, data);
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}
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}
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/* Force to DVO */
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data = ast_read32(ast, 0x1202c);
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data &= 0xfffbffff;
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ast_write32(ast, 0x1202c, data);
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/* Init VGA DVO Settings */
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80);
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return true;
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}
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static void ast_init_analog(struct drm_device *dev)
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{
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struct ast_private *ast = dev->dev_private;
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u32 data;
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/*
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* Set DAC source to VGA mode in SCU2C via the P2A
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* bridge. First configure the P2U to target the SCU
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* in case it isn't at this stage.
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*/
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ast_write32(ast, 0xf004, 0x1e6e0000);
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ast_write32(ast, 0xf000, 0x1);
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/* Then unlock the SCU with the magic password */
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ast_write32(ast, 0x12000, 0x1688a8a8);
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ast_write32(ast, 0x12000, 0x1688a8a8);
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ast_write32(ast, 0x12000, 0x1688a8a8);
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/* Finally, clear bits [17:16] of SCU2c */
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data = ast_read32(ast, 0x1202c);
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data &= 0xfffcffff;
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ast_write32(ast, 0, data);
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/* Disable DVO */
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x00);
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}
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void ast_init_3rdtx(struct drm_device *dev)
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{
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struct ast_private *ast = dev->dev_private;
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u8 jreg;
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if (ast->chip == AST2300 || ast->chip == AST2400) {
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jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
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switch (jreg & 0x0e) {
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case 0x04:
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ast_init_dvo(dev);
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break;
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case 0x08:
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ast_launch_m68k(dev);
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break;
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case 0x0c:
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ast_init_dvo(dev);
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break;
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default:
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if (ast->tx_chip_type == AST_TX_SIL164)
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ast_init_dvo(dev);
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else
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ast_init_analog(dev);
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}
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}
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}
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Block a user