drivers/aspeed: Add native text mode VGA support for the AST2050
Change-Id: I37763a59d2546cd0c0e57b31fdb7aa77c2c50bee Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11937 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
This commit is contained in:
Timothy Pearson
committed by
Peter Stuge
Peter Stuge
parent
c3fcdccb81
commit
04cf449e77
393
src/drivers/aspeed/common/ast_main.c
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393
src/drivers/aspeed/common/ast_main.c
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/*
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* Copyright 2012 Red Hat Inc.
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* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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/*
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* Authors: Dave Airlie <airlied@redhat.com>
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*/
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#include "ast_drv.h"
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#include "ast_dram_tables.h"
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void ast_set_index_reg_mask(struct ast_private *ast,
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uint32_t base, uint8_t index,
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uint8_t mask, uint8_t val)
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{
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u8 tmp;
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ast_io_write8(ast, base, index);
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tmp = (ast_io_read8(ast, base + 1) & mask) | val;
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ast_set_index_reg(ast, base, index, tmp);
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}
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uint8_t ast_get_index_reg(struct ast_private *ast,
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uint32_t base, uint8_t index)
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{
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uint8_t ret;
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ast_io_write8(ast, base, index);
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ret = ast_io_read8(ast, base + 1);
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return ret;
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}
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uint8_t ast_get_index_reg_mask(struct ast_private *ast,
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uint32_t base, uint8_t index, uint8_t mask)
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{
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uint8_t ret;
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ast_io_write8(ast, base, index);
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ret = ast_io_read8(ast, base + 1) & mask;
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return ret;
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}
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static int ast_detect_chip(struct drm_device *dev, bool *need_post)
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{
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struct ast_private *ast = dev->dev_private;
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uint32_t data, jreg;
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ast_open_key(ast);
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if (dev->pdev->device == PCI_CHIP_AST1180) {
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ast->chip = AST1100;
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DRM_INFO("AST 1180 detected\n");
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} else {
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pci_read_config_dword(ast->dev->pdev, 0x08, &data);
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uint8_t revision = data & 0xff;
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if (revision >= 0x30) {
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ast->chip = AST2400;
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DRM_INFO("AST 2400 detected\n");
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} else if (revision >= 0x20) {
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ast->chip = AST2300;
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DRM_INFO("AST 2300 detected\n");
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} else if (revision >= 0x10) {
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ast_write32(ast, 0xf004, 0x1e6e0000);
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ast_write32(ast, 0xf000, 0x1);
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data = ast_read32(ast, 0x1207c);
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switch (data & 0x0300) {
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case 0x0200:
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ast->chip = AST1100;
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DRM_INFO("AST 1100 detected\n");
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break;
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case 0x0100:
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ast->chip = AST2200;
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DRM_INFO("AST 2200 detected\n");
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break;
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case 0x0000:
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ast->chip = AST2150;
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DRM_INFO("AST 2150 detected\n");
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break;
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default:
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ast->chip = AST2100;
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DRM_INFO("AST 2100 detected\n");
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break;
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}
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ast->vga2_clone = false;
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} else {
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ast->chip = AST2000;
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DRM_INFO("AST 2000 detected\n");
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}
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}
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/*
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* If VGA isn't enabled, we need to enable now or subsequent
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* access to the scratch registers will fail. We also inform
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* our caller that it needs to POST the chip
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* (Assumption: VGA not enabled -> need to POST)
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*/
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if (!ast_is_vga_enabled(dev)) {
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ast_enable_vga(dev);
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ast_enable_mmio(dev);
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DRM_INFO("VGA not enabled on entry, requesting chip POST\n");
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*need_post = true;
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} else
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*need_post = false;
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/* Check if we support wide screen */
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switch (ast->chip) {
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case AST1180:
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ast->support_wide_screen = true;
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break;
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case AST2000:
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ast->support_wide_screen = false;
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break;
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default:
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jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
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if (!(jreg & 0x80))
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ast->support_wide_screen = true;
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else if (jreg & 0x01)
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ast->support_wide_screen = true;
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else {
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ast->support_wide_screen = false;
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/* Read SCU7c (silicon revision register) */
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ast_write32(ast, 0xf004, 0x1e6e0000);
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ast_write32(ast, 0xf000, 0x1);
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data = ast_read32(ast, 0x1207c);
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data &= 0x300;
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if (ast->chip == AST2300 && data == 0x0) /* ast1300 */
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ast->support_wide_screen = true;
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if (ast->chip == AST2400 && data == 0x100) /* ast1400 */
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ast->support_wide_screen = true;
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}
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break;
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}
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/* Check 3rd Tx option (digital output afaik) */
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ast->tx_chip_type = AST_TX_NONE;
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/*
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* VGACRA3 Enhanced Color Mode Register, check if DVO is already
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* enabled, in that case, assume we have a SIL164 TMDS transmitter
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*
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* Don't make that assumption if we the chip wasn't enabled and
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* is at power-on reset, otherwise we'll incorrectly "detect" a
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* SIL164 when there is none.
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*/
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if (!*need_post) {
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jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff);
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if (jreg & 0x80)
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ast->tx_chip_type = AST_TX_SIL164;
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}
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if ((ast->chip == AST2300) || (ast->chip == AST2400)) {
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/*
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* On AST2300 and 2400, look the configuration set by the SoC in
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* the SOC scratch register #1 bits 11:8 (interestingly marked
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* as "reserved" in the spec)
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*/
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jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
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switch (jreg) {
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case 0x04:
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ast->tx_chip_type = AST_TX_SIL164;
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break;
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case 0x08:
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ast->dp501_fw_addr = kzalloc(32*1024, GFP_KERNEL);
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if (ast->dp501_fw_addr) {
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/* backup firmware */
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if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
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kfree(ast->dp501_fw_addr);
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ast->dp501_fw_addr = NULL;
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}
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}
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/* fallthrough */
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case 0x0c:
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ast->tx_chip_type = AST_TX_DP501;
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}
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}
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/* Print stuff for diagnostic purposes */
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switch(ast->tx_chip_type) {
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case AST_TX_SIL164:
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DRM_INFO("Using Sil164 TMDS transmitter\n");
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break;
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case AST_TX_DP501:
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DRM_INFO("Using DP501 DisplayPort transmitter\n");
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break;
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default:
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DRM_INFO("Analog VGA only\n");
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}
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return 0;
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}
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static int ast_get_dram_info(struct drm_device *dev)
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{
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struct ast_private *ast = dev->dev_private;
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uint8_t i;
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uint32_t data, data2;
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uint32_t denum, num, div, ref_pll;
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ast_write32(ast, 0xf004, 0x1e6e0000);
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ast_write32(ast, 0xf000, 0x1);
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ast_write32(ast, 0x10000, 0xfc600309);
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/* Wait up to 2.5 seconds for device initialization / register unlock */
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for (i = 0; i < 250; i++) {
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if (ast_read32(ast, 0x10000) == 0x01)
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break;
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mdelay(10);
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}
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if (ast_read32(ast, 0x10000) != 0x01)
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dev_err(dev->pdev, "Unable to unlock SDRAM control registers\n");
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data = ast_read32(ast, 0x10004);
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if (data & 0x400)
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ast->dram_bus_width = 16;
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else
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ast->dram_bus_width = 32;
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if (ast->chip == AST2300 || ast->chip == AST2400) {
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switch (data & 0x03) {
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case 0:
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ast->dram_type = AST_DRAM_512Mx16;
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break;
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default:
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case 1:
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ast->dram_type = AST_DRAM_1Gx16;
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break;
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case 2:
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ast->dram_type = AST_DRAM_2Gx16;
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break;
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case 3:
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ast->dram_type = AST_DRAM_4Gx16;
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break;
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}
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} else {
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switch (data & 0x0c) {
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case 0:
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case 4:
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ast->dram_type = AST_DRAM_512Mx16;
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break;
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case 8:
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if (data & 0x40)
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ast->dram_type = AST_DRAM_1Gx16;
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else
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ast->dram_type = AST_DRAM_512Mx32;
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break;
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case 0xc:
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ast->dram_type = AST_DRAM_1Gx32;
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break;
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}
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}
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data = ast_read32(ast, 0x10120);
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data2 = ast_read32(ast, 0x10170);
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if (data2 & 0x2000)
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ref_pll = 14318;
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else
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ref_pll = 12000;
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denum = data & 0x1f;
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num = (data & 0x3fe0) >> 5;
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data = (data & 0xc000) >> 14;
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switch (data) {
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case 3:
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div = 0x4;
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break;
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case 2:
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case 1:
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div = 0x2;
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break;
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default:
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div = 0x1;
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break;
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}
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ast->mclk = ref_pll * (num + 2) / (denum + 2) * (div * 1000);
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return 0;
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}
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static u32 ast_get_vram_info(struct drm_device *dev)
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{
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struct ast_private *ast = dev->dev_private;
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u8 jreg;
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u32 vram_size;
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ast_open_key(ast);
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vram_size = AST_VIDMEM_DEFAULT_SIZE;
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jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xaa, 0xff);
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switch (jreg & 3) {
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case 0: vram_size = AST_VIDMEM_SIZE_8M; break;
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case 1: vram_size = AST_VIDMEM_SIZE_16M; break;
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case 2: vram_size = AST_VIDMEM_SIZE_32M; break;
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case 3: vram_size = AST_VIDMEM_SIZE_64M; break;
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}
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return vram_size;
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}
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int ast_driver_load(struct drm_device *dev, unsigned long flags)
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{
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struct ast_private *ast;
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bool need_post;
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int ret = 0;
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struct resource *res;
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ast = kzalloc(sizeof(struct ast_private), GFP_KERNEL);
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if (!ast)
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return -ENOMEM;
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dev->dev_private = ast;
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ast->dev = dev;
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/* PCI BAR 1 */
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res = find_resource(dev->pdev, 0x14);
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if (!res) {
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dev_err(dev->pdev, "BAR1 resource not found.\n");
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ret = -EIO;
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goto out_free;
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}
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ast->regs = res2mmio(res, 0, 0);
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if (!ast->regs) {
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ret = -EIO;
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goto out_free;
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}
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/* PCI BAR 2 */
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ast->io_space_uses_mmap = false;
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res = find_resource(dev->pdev, 0x18);
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if (!res) {
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dev_err(dev->pdev, "BAR2 resource not found.\n");
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ret = -EIO;
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goto out_free;
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}
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/*
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* If we don't have IO space at all, use MMIO now and
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* assume the chip has MMIO enabled by default (rev 0x20
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* and higher).
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*/
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if (!(res->flags & IORESOURCE_IO)) {
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DRM_INFO("platform has no IO space, trying MMIO\n");
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ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
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ast->io_space_uses_mmap = true;
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}
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/* "map" IO regs if the above hasn't done so already */
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if (!ast->ioregs) {
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ast->ioregs = res2mmio(res, 0, 0);
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if (!ast->ioregs) {
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ret = -EIO;
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goto out_free;
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}
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/* Adjust the I/O space location to match expectations (the code expects offset 0x0 to be I/O location 0x380) */
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ast->ioregs = (void *)AST_IO_MM_OFFSET;
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}
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ast_detect_chip(dev, &need_post);
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if (ast->chip != AST1180) {
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ast_get_dram_info(dev);
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ast->vram_size = ast_get_vram_info(dev);
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DRM_INFO("dram %d %d %d %08x\n", ast->mclk, ast->dram_type, ast->dram_bus_width, ast->vram_size);
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}
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if (need_post)
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ast_post_gpu(dev);
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return 0;
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out_free:
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kfree(ast);
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dev->dev_private = NULL;
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return ret;
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}
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