soc/intel/xeon_sp: Unshare UDK binding among Xeon-SP platforms

TEST=intel/archercity CRB

Change-Id: I285549daad87fe1ad6e8a94853e0a92cd5930e04
Signed-off-by: Li, Jincheng <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81041
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/xeon_sp/Kconfig

@@ -47,7 +47,6 @@ config MAINBOARD_USES_FSP2_0
 	  bool
 	  default y
 	  select PLATFORM_USES_FSP2_0
-	  select UDK_202005_BINDING
 	  select POSTCAR_STAGE
 
 config MAX_SOCKET

src/soc/intel/xeon_sp/cpx/Kconfig

@@ -8,6 +8,7 @@ config SOC_INTEL_COOPERLAKE_SP
 	select NO_FSP_TEMP_RAM_EXIT
 	select HAVE_INTEL_FSP_REPO
 	select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND
+	select UDK_202005_BINDING
 	help
 	  Intel Cooper Lake-SP support
 

src/soc/intel/xeon_sp/skx/Kconfig

@@ -5,6 +5,7 @@ config SOC_INTEL_SKYLAKE_SP
 	select XEON_SP_COMMON_BASE
 	select PLATFORM_USES_FSP2_0
 	select NO_FSP_TEMP_RAM_EXIT
+	select UDK_202005_BINDING
 	help
 	  Intel Skylake-SP support
 

src/soc/intel/xeon_sp/spr/Kconfig

@@ -14,6 +14,7 @@ config SOC_INTEL_SAPPHIRERAPIDS_SP
 	select XEON_SP_COMMON_BASE
 	select HAVE_IOAT_DOMAINS
 	select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND
+	select UDK_202005_BINDING
 	help
 	  Intel Sapphire Rapids-SP support