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soc/intel/xeon_sp: Unshare UDK binding among Xeon-SP platforms

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TEST=intel/archercity CRB

Change-Id: I285549daad87fe1ad6e8a94853e0a92cd5930e04
Signed-off-by: Li, Jincheng <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81041
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jincheng Li 2024-03-04 21:57:06 +08:00 committed by Lean Sheng Tan
parent a5bdf8e8df
commit 04fde7ed37
4 changed files with 3 additions and 1 deletions
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1
src/soc/intel/xeon_sp/Kconfig
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@ -47,7 +47,6 @@ config MAINBOARD_USES_FSP2_0
bool bool
default y default y
select PLATFORM_USES_FSP2_0 select PLATFORM_USES_FSP2_0
select UDK_202005_BINDING
select POSTCAR_STAGE select POSTCAR_STAGE
config MAX_SOCKET config MAX_SOCKET

1
src/soc/intel/xeon_sp/cpx/Kconfig
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@ -8,6 +8,7 @@ config SOC_INTEL_COOPERLAKE_SP
select NO_FSP_TEMP_RAM_EXIT select NO_FSP_TEMP_RAM_EXIT
select HAVE_INTEL_FSP_REPO select HAVE_INTEL_FSP_REPO
select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND
select UDK_202005_BINDING
help help
Intel Cooper Lake-SP support Intel Cooper Lake-SP support

1
src/soc/intel/xeon_sp/skx/Kconfig
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@ -5,6 +5,7 @@ config SOC_INTEL_SKYLAKE_SP
select XEON_SP_COMMON_BASE select XEON_SP_COMMON_BASE
select PLATFORM_USES_FSP2_0 select PLATFORM_USES_FSP2_0
select NO_FSP_TEMP_RAM_EXIT select NO_FSP_TEMP_RAM_EXIT
select UDK_202005_BINDING
help help
Intel Skylake-SP support Intel Skylake-SP support

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src/soc/intel/xeon_sp/spr/Kconfig
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@ -14,6 +14,7 @@ config SOC_INTEL_SAPPHIRERAPIDS_SP
select XEON_SP_COMMON_BASE select XEON_SP_COMMON_BASE
select HAVE_IOAT_DOMAINS select HAVE_IOAT_DOMAINS
select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND
select UDK_202005_BINDING
help help
Intel Sapphire Rapids-SP support Intel Sapphire Rapids-SP support