mb/prodrive/hermes: Remove overridetree
There's no need to have an overridetree with a single board variant. TEST=Compare static.c and observe only device order has changed. Change-Id: I2097e247c27d5d0c5479cb533b477cd490a4c827 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons
parent
57f09803bb
commit
0515aa1978
@ -51,9 +51,6 @@ config MAX_CPUS
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int
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int
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default 16
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default 16
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config CONSOLE_POST
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config CONSOLE_POST
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bool
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bool
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default y
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default y
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@ -1,4 +1,132 @@
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chip soc/intel/cannonlake
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chip soc/intel/cannonlake
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# FSP configuration
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register "SataMode" = "0" # AHCI
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register "SataSalpSupport" = "0"
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register "satapwroptimize" = "1"
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register "SataPortsDevSlp[1]" = "1" # PCH_M2_SATA_DEVSLP1
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register "SataPortsEnable[0]" = "1"
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register "SataPortsEnable[1]" = "1" # depends on SATAXPCIE1
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register "SataPortsEnable[2]" = "0" # Not used for SATA
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register "SataPortsEnable[3]" = "0" # Not used for SATA
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register "SataPortsEnable[4]" = "1"
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register "SataPortsEnable[5]" = "1"
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register "SataPortsEnable[6]" = "1"
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register "SataPortsEnable[7]" = "1"
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register "SataPortsHotPlug[0]" = "1"
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register "SataPortsHotPlug[1]" = "1"
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register "SataPortsHotPlug[2]" = "0"
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register "SataPortsHotPlug[3]" = "0"
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register "SataPortsHotPlug[4]" = "1"
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register "SataPortsHotPlug[5]" = "1"
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register "SataPortsHotPlug[6]" = "1"
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register "SataPortsHotPlug[7]" = "1"
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register "PchHdaDspEnable" = "0"
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register "PchHdaAudioLinkHda" = "1"
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# Controls the CLKREQ, not the output directly.
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# Depends on the CLKREQ to CLK gen mapping below
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register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" # BMC, PCIe Slot1, Slot2, Slot4, Slot6
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register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" # PHY3
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register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"
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register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
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register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" # RP9 M2 Slot M x4
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register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE" # RP16 M2 Slot E x1
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register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED"
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register "PcieClkSrcUsage[7]" = "PCIE_CLK_NOTUSED"
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register "PcieClkSrcUsage[8]" = "PCIE_CLK_NOTUSED"
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register "PcieClkSrcUsage[9]" = "PCIE_CLK_NOTUSED"
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register "PcieClkSrcUsage[10]" = "PCIE_CLK_NOTUSED"
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register "PcieClkSrcUsage[11]" = "PCIE_CLK_NOTUSED"
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register "PcieClkSrcUsage[12]" = "PCIE_CLK_NOTUSED"
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register "PcieClkSrcUsage[13]" = "PCIE_CLK_FREE" # PHY 0, PHY 1, PHY 2, PHY 4
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register "PcieClkSrcUsage[14]" = "PCIE_CLK_FREE" # PB
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register "PcieClkSrcUsage[15]" = "PCIE_CLK_FREE" # PCIe Slot3
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# Only map M2 CLKREQ to CLK gen
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register "PcieClkSrcClkReq[4]" = "4" # M2_M_CLK_REQ_n
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register "PcieClkSrcClkReq[5]" = "5" # M2_E_CLK_REQ_n
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# USB OC5-7: not connected
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register "usb2_ports" = "{
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#define HERMES_USB2_CONFIG(pin) { \
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.enable = 1, \
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.ocpin = (pin), \
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.tx_bias = USB2_BIAS_0MV, \
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.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \
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.pre_emp_bias = USB2_BIAS_28P15MV, \
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.pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \
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}
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[0] = HERMES_USB2_CONFIG(OC0), /* USB3 rear panel 1 */
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[1] = HERMES_USB2_CONFIG(OC0),
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[2] = HERMES_USB2_CONFIG(OC1), /* USB3 rear panel 2 */
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[3] = HERMES_USB2_CONFIG(OC1),
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[4] = HERMES_USB2_CONFIG(OC2), /* USB3 internal header CN_USB3_HDR */
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[5] = HERMES_USB2_CONFIG(OC2),
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[6] = HERMES_USB2_CONFIG(OC3), /* USB2 internal header USB2_HDR1 */
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[7] = HERMES_USB2_CONFIG(OC3),
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[8] = HERMES_USB2_CONFIG(OC4), /* USB2 internal header USB2_HDR1 */
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[9] = HERMES_USB2_CONFIG(OC4),
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[10] = HERMES_USB2_CONFIG(OC_SKIP), /* BMC */
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[11] = USB2_PORT_EMPTY,
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[12] = HERMES_USB2_CONFIG(OC_SKIP), /* piggy-back */
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[13] = HERMES_USB2_CONFIG(OC_SKIP), /* M.2 key E */
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}"
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# USB Config 2.0/3.0
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# Enumeration starts at 0
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# USB 3.0
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# USB OC0: RP1
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
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# USB OC1: RP2
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)"
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# USB OC2: Internal Header CN_USB3_HDR
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)"
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)"
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# Thermal
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register "tcc_offset" = "1" # TCC of 99C
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# Disable S0ix
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register "s0ix_enable" = "0"
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# Enable Turbo
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register "eist_enable" = "1"
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register "common_soc_config" = "{
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.gspi[0] = {
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.speed_mhz = 1,
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.early_init = 1,
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},
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}"
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# VR Power Delivery Design
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register "VrPowerDeliveryDesign" = "0x12"
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
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[PchSerialIoIndexSPI0] = PchSerialIoPci,
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[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART0] = PchSerialIoPci,
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[PchSerialIoIndexUART1] = PchSerialIoPci,
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[PchSerialIoIndexUART2] = PchSerialIoPci,
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}"
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register "DisableHeciRetry" = "1"
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device cpu_cluster 0 on
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device cpu_cluster 0 on
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device lapic 0 on end
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device lapic 0 on end
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end
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end
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@ -14,24 +142,86 @@ chip soc/intel/cannonlake
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device pci 01.2 on # PEG x4 or disabled / Slot 4
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device pci 01.2 on # PEG x4 or disabled / Slot 4
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smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT4" "SlotDataBusWidth4X"
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smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT4" "SlotDataBusWidth4X"
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end
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end
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device pci 02.0 on end # Integrated Graphics Device
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device pci 04.0 on end # SA Thermal device
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device pci 04.0 on end # SA Thermal device
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device pci 08.0 on end # Gaussian Mixture
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device pci 08.0 on end # Gaussian Mixture
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device pci 12.0 on end # Thermal Subsystem
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device pci 12.0 on end # Thermal Subsystem
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device pci 14.0 on end # USB xHCI
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device pci 14.0 on end # USB xHCI
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.2 on end # RAM controller
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device pci 14.2 on end # RAM controller
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device pci 14.3 on
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chip drivers/wifi/generic
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register "wake" = "PME_B0_EN_BIT"
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device generic 0 on end
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end
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end # CNVi wifi
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device pci 14.5 off end # SDCard
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device pci 14.5 off end # SDCard
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 on end # Management Engine Interface 2
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device pci 16.1 on end # Management Engine Interface 2
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device pci 16.4 off end # Management Engine Interface 3
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device pci 16.4 off end # Management Engine Interface 3
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device pci 17.0 on end # SATA
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device pci 17.0 on end # SATA
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device pci 1d.6 on # PCIe root port 15
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# This device does not have any function on CNP-H, but it needs
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# to be here so that the resource allocator is aware of UART 2.
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device pci 19.0 hidden end
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chip soc/intel/common/block/uart
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device pci 19.2 hidden
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register "devid" = "PCI_DEVICE_ID_INTEL_CNP_H_UART2"
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end # UART #2, in ACPI mode
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end
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device pci 1b.4 on # PCIe root port 21 (Slot 1)
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smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X"
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register "PcieRpEnable[20]" = "1"
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register "PcieRpLtrEnable[20]" = "1"
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register "PcieRpSlotImplemented[20]" = "1"
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register "PcieRpMaxPayload[20]" = "RpMaxPayload_256"
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register "PcieRpAdvancedErrorReporting[20]" = "1"
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register "PcieRpAspm[20]" = "AspmDisabled"
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end
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device pci 1c.0 on # PCIe root port 1 (Slot 3)
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smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X"
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register "PcieRpEnable[0]" = "1"
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register "PcieRpLtrEnable[0]" = "1"
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register "PcieRpSlotImplemented[0]" = "1"
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register "PcieRpMaxPayload[0]" = "RpMaxPayload_256"
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register "PcieRpAdvancedErrorReporting[0]" = "1"
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register "PcieRpAspm[0]" = "AspmDisabled"
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end
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device pci 1c.4 on # PCIe root port 5 (PHY 3)
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register "PcieRpEnable[4]" = "1"
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end
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device pci 1c.5 on # PCIe root port 6 (PHY 4)
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register "PcieRpEnable[5]" = "1"
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end
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device pci 1c.6 on # PCIe root port 7 (PHY 2)
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register "PcieRpEnable[6]" = "1"
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end
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device pci 1c.7 on # PCIe root port 8 (PHY 1)
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register "PcieRpEnable[7]" = "1"
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end
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device pci 1d.0 on # PCIe root port 9 (M2 M)
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smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X"
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register "PcieRpEnable[8]" = "1"
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register "PcieRpSlotImplemented[8]" = "1"
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end
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device pci 1d.5 on # PCIe root port 14 (PHY 0)
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register "PcieRpEnable[13]" = "1"
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end
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device pci 1d.6 on # PCIe root port 15 (BMC)
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device pci 00.0 on # Aspeed PCI Bridge
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device pci 00.0 on # Aspeed PCI Bridge
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device pci 00.0 on end # Aspeed 2500 VGA
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device pci 00.0 on end # Aspeed 2500 VGA
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end
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end
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register "PcieRpEnable[14]" = "1"
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register "PcieRpSlotImplemented[14]" = "1"
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register "PcieRpSlotImplemented[14]" = "1"
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end
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end
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device pci 1d.7 on # PCIe root port 16 (M.2 E/CNVi)
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# Disabled when CNVi is present
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register "PcieRpEnable[15]" = "1"
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register "PcieRpSlotImplemented[15]" = "1"
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end
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device pci 1e.0 on end # UART #0
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device pci 1e.1 on end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1f.0 on # LPC Interface
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device pci 1f.0 on # LPC Interface
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chip drivers/pc80/tpm
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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device pnp 0c31.0 on end
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@ -44,5 +234,4 @@ chip soc/intel/cannonlake
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device pci 1f.4 on end # SMBus
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # PCH SPI
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device pci 1f.5 on end # PCH SPI
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end
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end
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end
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end
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@ -1,204 +0,0 @@
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chip soc/intel/cannonlake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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# FSP configuration
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register "SataMode" = "0" # AHCI
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register "SataSalpSupport" = "0"
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register "satapwroptimize" = "1"
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register "SataPortsDevSlp[1]" = "1" # PCH_M2_SATA_DEVSLP1
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register "SataPortsEnable[0]" = "1"
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register "SataPortsEnable[1]" = "1" # depends on SATAXPCIE1
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register "SataPortsEnable[2]" = "0" # Not used for SATA
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register "SataPortsEnable[3]" = "0" # Not used for SATA
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register "SataPortsEnable[4]" = "1"
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register "SataPortsEnable[5]" = "1"
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register "SataPortsEnable[6]" = "1"
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register "SataPortsEnable[7]" = "1"
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register "SataPortsHotPlug[0]" = "1"
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register "SataPortsHotPlug[1]" = "1"
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register "SataPortsHotPlug[2]" = "0"
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register "SataPortsHotPlug[3]" = "0"
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register "SataPortsHotPlug[4]" = "1"
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register "SataPortsHotPlug[5]" = "1"
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register "SataPortsHotPlug[6]" = "1"
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register "SataPortsHotPlug[7]" = "1"
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register "PchHdaDspEnable" = "0"
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register "PchHdaAudioLinkHda" = "1"
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# Controls the CLKREQ, not the output directly.
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# Depends on the CLKREQ to CLK gen mapping below
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register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" # BMC, PCIe Slot1, Slot2, Slot4, Slot6
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register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" # PHY3
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register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"
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register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
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register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" # RP9 M2 Slot M x4
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register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE" # RP16 M2 Slot E x1
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register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED"
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register "PcieClkSrcUsage[7]" = "PCIE_CLK_NOTUSED"
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register "PcieClkSrcUsage[8]" = "PCIE_CLK_NOTUSED"
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register "PcieClkSrcUsage[9]" = "PCIE_CLK_NOTUSED"
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register "PcieClkSrcUsage[10]" = "PCIE_CLK_NOTUSED"
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register "PcieClkSrcUsage[11]" = "PCIE_CLK_NOTUSED"
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register "PcieClkSrcUsage[12]" = "PCIE_CLK_NOTUSED"
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register "PcieClkSrcUsage[13]" = "PCIE_CLK_FREE" # PHY 0, PHY 1, PHY 2, PHY 4
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register "PcieClkSrcUsage[14]" = "PCIE_CLK_FREE" # PB
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register "PcieClkSrcUsage[15]" = "PCIE_CLK_FREE" # PCIe Slot3
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|
||||||
# Only map M2 CLKREQ to CLK gen
|
|
||||||
register "PcieClkSrcClkReq[4]" = "4" # M2_M_CLK_REQ_n
|
|
||||||
register "PcieClkSrcClkReq[5]" = "5" # M2_E_CLK_REQ_n
|
|
||||||
|
|
||||||
# USB OC5-7: not connected
|
|
||||||
register "usb2_ports" = "{
|
|
||||||
|
|
||||||
#define HERMES_USB2_CONFIG(pin) { \
|
|
||||||
.enable = 1, \
|
|
||||||
.ocpin = (pin), \
|
|
||||||
.tx_bias = USB2_BIAS_0MV, \
|
|
||||||
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \
|
|
||||||
.pre_emp_bias = USB2_BIAS_28P15MV, \
|
|
||||||
.pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \
|
|
||||||
}
|
|
||||||
[0] = HERMES_USB2_CONFIG(OC0), /* USB3 rear panel 1 */
|
|
||||||
[1] = HERMES_USB2_CONFIG(OC0),
|
|
||||||
[2] = HERMES_USB2_CONFIG(OC1), /* USB3 rear panel 2 */
|
|
||||||
[3] = HERMES_USB2_CONFIG(OC1),
|
|
||||||
[4] = HERMES_USB2_CONFIG(OC2), /* USB3 internal header CN_USB3_HDR */
|
|
||||||
[5] = HERMES_USB2_CONFIG(OC2),
|
|
||||||
[6] = HERMES_USB2_CONFIG(OC3), /* USB2 internal header USB2_HDR1 */
|
|
||||||
[7] = HERMES_USB2_CONFIG(OC3),
|
|
||||||
[8] = HERMES_USB2_CONFIG(OC4), /* USB2 internal header USB2_HDR1 */
|
|
||||||
[9] = HERMES_USB2_CONFIG(OC4),
|
|
||||||
[10] = HERMES_USB2_CONFIG(OC_SKIP), /* BMC */
|
|
||||||
[11] = USB2_PORT_EMPTY,
|
|
||||||
[12] = HERMES_USB2_CONFIG(OC_SKIP), /* piggy-back */
|
|
||||||
[13] = HERMES_USB2_CONFIG(OC_SKIP), /* M.2 key E */
|
|
||||||
}"
|
|
||||||
|
|
||||||
# USB Config 2.0/3.0
|
|
||||||
# Enumeration starts at 0
|
|
||||||
# USB 3.0
|
|
||||||
# USB OC0: RP1
|
|
||||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
|
|
||||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
|
|
||||||
|
|
||||||
# USB OC1: RP2
|
|
||||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"
|
|
||||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)"
|
|
||||||
|
|
||||||
# USB OC2: Internal Header CN_USB3_HDR
|
|
||||||
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)"
|
|
||||||
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)"
|
|
||||||
|
|
||||||
# Thermal
|
|
||||||
register "tcc_offset" = "1" # TCC of 99C
|
|
||||||
|
|
||||||
|
|
||||||
# Disable S0ix
|
|
||||||
register "s0ix_enable" = "0"
|
|
||||||
|
|
||||||
# Enable Turbo
|
|
||||||
register "eist_enable" = "1"
|
|
||||||
|
|
||||||
register "common_soc_config" = "{
|
|
||||||
.gspi[0] = {
|
|
||||||
.speed_mhz = 1,
|
|
||||||
.early_init = 1,
|
|
||||||
},
|
|
||||||
}"
|
|
||||||
|
|
||||||
# VR Power Delivery Design
|
|
||||||
register "VrPowerDeliveryDesign" = "0x12"
|
|
||||||
|
|
||||||
register "SerialIoDevMode" = "{
|
|
||||||
[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
|
|
||||||
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
|
|
||||||
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
|
|
||||||
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
|
|
||||||
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
|
|
||||||
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
|
|
||||||
[PchSerialIoIndexSPI0] = PchSerialIoPci,
|
|
||||||
[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
|
|
||||||
[PchSerialIoIndexUART0] = PchSerialIoPci,
|
|
||||||
[PchSerialIoIndexUART1] = PchSerialIoPci,
|
|
||||||
[PchSerialIoIndexUART2] = PchSerialIoPci,
|
|
||||||
}"
|
|
||||||
|
|
||||||
register "DisableHeciRetry" = "1"
|
|
||||||
|
|
||||||
device domain 0 on
|
|
||||||
device pci 02.0 on end # Integrated Graphics Device
|
|
||||||
device pci 14.3 on
|
|
||||||
chip drivers/wifi/generic
|
|
||||||
register "wake" = "PME_B0_EN_BIT"
|
|
||||||
device generic 0 on end
|
|
||||||
end
|
|
||||||
end # CNVi wifi
|
|
||||||
|
|
||||||
# This device does not have any function on CNP-H, but it needs
|
|
||||||
# to be here so that the resource allocator is aware of UART 2.
|
|
||||||
device pci 19.0 hidden end
|
|
||||||
chip soc/intel/common/block/uart
|
|
||||||
device pci 19.2 hidden
|
|
||||||
register "devid" = "PCI_DEVICE_ID_INTEL_CNP_H_UART2"
|
|
||||||
end # UART #2, in ACPI mode
|
|
||||||
end
|
|
||||||
device pci 1b.4 on # PCIe root port 21 (Slot 1)
|
|
||||||
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X"
|
|
||||||
register "PcieRpEnable[20]" = "1"
|
|
||||||
register "PcieRpLtrEnable[20]" = "1"
|
|
||||||
register "PcieRpSlotImplemented[20]" = "1"
|
|
||||||
register "PcieRpMaxPayload[20]" = "RpMaxPayload_256"
|
|
||||||
register "PcieRpAdvancedErrorReporting[20]" = "1"
|
|
||||||
register "PcieRpAspm[20]" = "AspmDisabled"
|
|
||||||
end
|
|
||||||
device pci 1c.0 on # PCIe root port 1 (Slot 3)
|
|
||||||
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X"
|
|
||||||
register "PcieRpEnable[0]" = "1"
|
|
||||||
register "PcieRpLtrEnable[0]" = "1"
|
|
||||||
register "PcieRpSlotImplemented[0]" = "1"
|
|
||||||
register "PcieRpMaxPayload[0]" = "RpMaxPayload_256"
|
|
||||||
register "PcieRpAdvancedErrorReporting[0]" = "1"
|
|
||||||
register "PcieRpAspm[0]" = "AspmDisabled"
|
|
||||||
end
|
|
||||||
device pci 1c.4 on # PCIe root port 5 (PHY 3)
|
|
||||||
register "PcieRpEnable[4]" = "1"
|
|
||||||
end
|
|
||||||
device pci 1c.5 on # PCIe root port 6 (PHY 4)
|
|
||||||
register "PcieRpEnable[5]" = "1"
|
|
||||||
end
|
|
||||||
device pci 1c.6 on # PCIe root port 7 (PHY 2)
|
|
||||||
register "PcieRpEnable[6]" = "1"
|
|
||||||
end
|
|
||||||
device pci 1c.7 on # PCIe root port 8 (PHY 1)
|
|
||||||
register "PcieRpEnable[7]" = "1"
|
|
||||||
end
|
|
||||||
device pci 1d.0 on # PCIe root port 9 (M2 M)
|
|
||||||
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X"
|
|
||||||
register "PcieRpEnable[8]" = "1"
|
|
||||||
register "PcieRpSlotImplemented[8]" = "1"
|
|
||||||
end
|
|
||||||
device pci 1d.5 on # PCIe root port 14 (PHY 0)
|
|
||||||
register "PcieRpEnable[13]" = "1"
|
|
||||||
end
|
|
||||||
device pci 1d.6 on # PCIe root port 15 (BMC)
|
|
||||||
register "PcieRpEnable[14]" = "1"
|
|
||||||
end
|
|
||||||
device pci 1d.7 on # PCIe root port 16 (M.2 E/CNVi)
|
|
||||||
# Disabled when CNVi is present
|
|
||||||
register "PcieRpEnable[15]" = "1"
|
|
||||||
register "PcieRpSlotImplemented[15]" = "1"
|
|
||||||
end
|
|
||||||
device pci 1e.0 on end # UART #0
|
|
||||||
device pci 1e.1 on end # UART #1
|
|
||||||
device pci 1e.2 off end # GSPI #0
|
|
||||||
device pci 1e.3 off end # GSPI #1
|
|
||||||
end
|
|
||||||
end
|
|
||||||
Loading…
x
Reference in New Issue
Block a user