Kconfig!

Works on Kontron, qemu, and serengeti. 

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>

tested on abuild only. 

Acked-by: Ronald G. Minnich <rminnich@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/Kconfig

@@ -0,0 +1,275 @@
+##
+## This file is part of the coreboot repair project.
+##
+## Redistribution and use in source and binary forms, with or without
+## modification, are permitted provided that the following conditions
+## are met:
+## 1. Redistributions of source code must retain the above copyright
+##    notice, this list of conditions and the following disclaimer.
+## 2. Redistributions in binary form must reproduce the above copyright
+##    notice, this list of conditions and the following disclaimer in the
+##    documentation and/or other materials provided with the distribution.
+## 3. The name of the author may not be used to endorse or promote products
+##    derived from this software without specific prior written permission.
+##
+## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+## ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+## SUCH DAMAGE.
+##
+
+mainmenu "Coreboot Configuration"
+
+source src/mainboard/Kconfig
+source src/arch/i386/Kconfig
+source src/arch/ppc/Kconfig
+source src/devices/Kconfig
+source src/northbridge/Kconfig
+source src/southbridge/Kconfig
+source src/superio/Kconfig
+source src/cpu/Kconfig
+
+config CBFS
+	bool
+	default y
+
+config HAVE_HIGH_TABLES
+	bool
+	default y
+
+config PCI_BUS_SEGN_BITS
+	int
+	default 0
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+        hex
+        default 0
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+        hex
+        default 0
+
+config CPU_ADDR_BITS
+	int
+	default 36
+
+config XIP_ROM_BASE
+	hex
+	default 0xfffe0000
+
+config XIP_ROM_SIZE
+	hex
+	default 0x20000
+
+config LB_CKS_RANGE_START
+	int
+	default 49
+
+config LB_CKS_RANGE_END
+	int
+	default 125
+
+config LB_CKS_LOC
+	int
+	default 126
+
+config LOGICAL_CPUS
+	int
+	default 1
+
+config PCI_ROM_RUN
+	int
+	default 0
+
+config HT_CHAIN_UNITID_BASE
+	int
+	default 1
+
+config HT_CHAIN_END_UNITID_BASE
+	int
+	default 32
+
+config HEAP_SIZE
+	hex
+	default 0x2000
+
+config COREBOOT_V2
+	bool
+	default y
+
+config COREBOOT_V4
+	bool
+	default y
+
+config DEBUG
+	bool
+	default n
+
+config USE_PRINTK_IN_CAR
+	bool
+	default n
+
+config USE_OPTION_TABLE
+	bool
+	default n
+
+config MAX_CPUS
+	int
+	default 1
+
+config MMCONF_SUPPORT_DEFAULT
+	bool
+	default n
+
+config MMCONF_SUPPORT
+	bool
+	default n
+
+config LB_MEM_TOPK
+	int
+	default 2048
+
+config MULTIBOOT
+	bool
+	default n
+
+config COMPRESSED_PAYLOAD_LZMA
+	bool
+	default y
+
+config COMPRESSED_PAYLOAD_NRV2B
+	bool
+	default n
+
+source src/console/Kconfig
+
+config HAVE_ACPI_RESUME
+	bool
+	default n
+
+config ACPI_SSDTX_NUM
+	int
+	default 0
+
+config HAVE_ACPI_TABLES
+	bool
+	default n
+
+config HAVE_FALLBACK_BOOT
+	bool
+	default y
+
+config USE_FALLBACK_IMAGE
+	bool
+	default y
+
+config HAVE_HARD_RESET
+	bool
+	default n
+
+config HAVE_INIT_TIMER
+	bool
+	default n
+
+config HAVE_MAINBOARD_RESOURCES
+	bool
+	default n
+
+config HAVE_MOVNTI
+	bool
+	default y
+
+config HAVE_MP_TABLE
+	bool
+	default n
+
+config HAVE_OPTION_TABLE
+	bool
+	default y
+
+config HAVE_PIRQ_TABLE
+	bool
+	default n
+
+config PIRQ_ROUTE
+	bool
+	default n
+
+config HAVE_SMI_HANDLER
+	bool
+	default n
+
+config PCI_IO_CFG_EXT
+	bool
+	default n
+
+config IOAPIC
+	bool
+	default n
+
+menu "Drivers"
+
+endmenu
+
+menu "Payload"
+
+config COMPRESSED_PAYLOAD_LZMA
+	bool "Use LZMA compression for payloads"
+	default yes
+
+choice
+	prompt "Payload type"
+	default PAYLOAD_NONE
+
+config PAYLOAD_ELF
+	bool "An ELF executable payload file"
+	help
+	  Select this option if you have a payload image (an ELF file)
+	  which coreboot should run as soon as the basic hardware
+	  initialization is completed.
+
+	  You will be able to specify the location and file name of the
+	  payload image later.
+
+config PAYLOAD_NONE
+	bool "No payload"
+	help
+	  Select this option if you want to create an "empty" coreboot
+	  ROM image for a certain mainboard, i.e. a coreboot ROM image
+	  which does not yet contain a payload.
+
+	  For such an image to be useful, you have to use the 'lar' tool
+	  to add a payload to the ROM image later.
+
+endchoice
+
+config NORMAL_PAYLOAD_FILE
+	string "Normal payload path and filename"
+	depends on PAYLOAD_ELF
+	default "payload.elf"
+	help
+	  The path and filename of the ELF executable file to use as normal payload.
+
+config FALLBACK_PAYLOAD_FILE
+	string "Fallback payload path and filename"
+	depends on PAYLOAD_ELF
+	default "payload.elf"
+	help
+	  The path and filename of the ELF executable file to use as fallback payload.
+
+endmenu
+
+config GDB_STUB
+	bool "Enable GDB debugging support"
+	default y
+	help
+	  If this is set, then you will be able to set breakpoints for gdb debugging. 
+	  See: src/arch/i386/lib/c_start.S
+

src/arch/i386/Kconfig

@@ -0,0 +1,59 @@
+config ARCH_X86
+	boolean
+	help
+	  This option is used to set the architecture of a mainboard.
+	  It is usually set in mainboard/*/Kconfig.
+
+config ARCH
+	string
+	default i386
+	depends on ARCH_X86
+	help
+	  This is the name of the respective subdirectory in arch/.
+
+config ROMBASE
+	hex 
+	default 0xffe00000 if COREBOOT_ROMSIZE_KB_2048
+	default 0xfff00000 if COREBOOT_ROMSIZE_KB_1024
+	default 0xfff80000 if COREBOOT_ROMSIZE_KB_512
+	default 0xfffc0000 if COREBOOT_ROMSIZE_KB_256
+	default 0xfffe0000 if COREBOOT_ROMSIZE_KB_128
+
+config PAYLOAD_SIZE
+	hex
+	default 0
+
+config ROM_PAYLOAD_START
+	hex
+	default 0xffe00000 if COREBOOT_ROMSIZE_KB_2048
+	default 0xfff00000 if COREBOOT_ROMSIZE_KB_1024
+	default 0xfff80000 if COREBOOT_ROMSIZE_KB_512
+	default 0xfffc0000 if COREBOOT_ROMSIZE_KB_256
+	default 0xfffe0000 if COREBOOT_ROMSIZE_KB_128
+
+config ROM_IMAGE_SIZE
+	hex
+	default 0x200000 if COREBOOT_ROMSIZE_KB_2048
+	default 0x100000 if COREBOOT_ROMSIZE_KB_1024
+	default 0x80000 if COREBOOT_ROMSIZE_KB_512
+	default 0x40000 if COREBOOT_ROMSIZE_KB_256
+	default 0x20000 if COREBOOT_ROMSIZE_KB_128
+
+config RAMBASE
+	hex
+	default 0x100000
+
+config STACK_SIZE
+	hex
+	default 0x8000
+
+
+menu "Misc Options"
+
+config MAX_REBOOT_CNT
+	int "Maximum Reboot Count"
+	default 3
+
+endmenu
+
+

src/arch/i386/Makefile.inc

@@ -0,0 +1,98 @@
+#######################################################################
+# Take care of subdirectories
+subdirs-y += boot
+subdirs-y += init
+subdirs-y += lib
+subdirs-y += smp
+
+obj-y += ../../option_table.o
+
+ifdef POST_EVALUATION
+#######################################################################
+# Build the final rom image
+
+$(obj)/coreboot.rom: $(obj)/coreboot.bootblock $(obj)/coreboot_ram $(CBFSTOOL)
+	$(Q)rm -f $@
+	$(Q)$(CBFSTOOL) $@ create $(shell expr 1024 \* $(CONFIG_COREBOOT_ROMSIZE_KB)) 131072 $(obj)/coreboot.bootblock
+	$(Q)$(CBFSTOOL) $@ add-stage  $(obj)/coreboot_ram normal/coreboot_ram $(CBFS_COMPRESS_FLAG)
+	$(Q)if [ -f fallback/coreboot_apc ]; \
+	then \
+		$(CBFSTOOL) $@ add-stage fallback/coreboot_apc fallback/coreboot_apc $(CBFS_COMPRESS_FLAG); \
+	fi
+	$(Q)$(CBFSTOOL) $@ add-stage  $(obj)/coreboot_ram fallback/coreboot_ram $(CBFS_COMPRESS_FLAG)
+ifeq ($(CONFIG_PAYLOAD_NONE),y)
+	$(Q)printf "    PAYLOAD    none (as specified by user)\n"
+else
+	printf "    PAYLOAD    $(CONFIG_FALLBACK_PAYLOAD_FILE) $(COMPRESSFLAG)\n"
+	$(Q)$(CBFSTOOL) ./build/coreboot.rom add-payload $(CONFIG_FALLBACK_PAYLOAD_FILE)  fallback/payload $(CBFS_COMPRESS_FLAG)
+	printf "    PAYLOAD    $(CONFIG_NORMAL_PAYLOAD_FILE) $(COMPRESSFLAG)\n"
+	$(Q)$(CBFSTOOL) ./build/coreboot.rom add-payload $(CONFIG_NORMAL_PAYLOAD_FILE)  normal/payload $(CBFS_COMPRESS_FLAG)
+	$(CBFSTOOL) ./build/coreboot.rom print
+endif
+
+
+#######################################################################
+# Build the bootblock
+
+BOOTBLOCK_SIZE=65536
+
+$(obj)/coreboot.bootblock: $(obj)/coreboot.strip
+	$(Q)printf "    CREATE     $(subst $(obj)/,,$(@))\n"
+	$(Q)dd if=$< of=$(obj)/coreboot.bootblock.one obs=$(BOOTBLOCK_SIZE) conv=sync
+	$(Q)cat $(obj)/coreboot.bootblock.one $(obj)/coreboot.bootblock.one > $(obj)/coreboot.bootblock
+
+$(obj)/coreboot.strip: $(obj)/coreboot
+	$(Q)printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
+	$(Q)$(OBJCOPY) -O binary $< $@
+
+$(obj)/ldscript.ld: $(ldscripts) $(obj)/ldoptions
+	$(Q)printf 'INCLUDE "ldoptions"\n' > $@
+	$(Q)printf '$(foreach ldscript,$(ldscripts),INCLUDE "$(ldscript)"\n)' >> $@
+
+$(obj)/crt0_includes.h: $(crt0s)
+	$(Q)printf '$(foreach crt0,$(obj)/config.h $(crt0s),#include "$(crt0)"\n)' > $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/crt0.o: $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s
+	$(CC) -I$(obj) -Wa,-acdlns -c -o $@ $<  > $(dir $@)/crt0.disasm
+
+$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(src)/arch/i386/init/crt0.S.lb $(obj)/crt0_includes.h
+	$(CC) -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $< > $@.new && mv $@.new $@
+
+$(obj)/coreboot: $(initobjs) $(obj)/ldscript.ld
+	$(Q)printf "    LINK       $(subst $(obj)/,,$(@))\n"
+	$(Q)$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(obj)/ldscript.ld $(initobjs)
+	$(Q)$(NM) -n $(obj)/coreboot | sort > $(obj)/coreboot.map
+
+#######################################################################
+# i386 specific tools
+
+$(obj)/option_table.h $(obj)/option_table.c: $(obj)/build_opt_tbl $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout
+	$(Q)printf "    OPTION     $(subst $(obj)/,,$(@))\n"
+	$(Q)$(obj)/build_opt_tbl --config $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout --header $(obj)/option_table.h --option $(obj)/option_table.c
+
+$(obj)/build_opt_tbl: $(top)/util/options/build_opt_tbl.c $(top)/src/include/pc80/mc146818rtc.h $(top)/src/include/boot/coreboot_tables.h
+	$(Q)printf "    HOSTCC     $(subst $(obj)/,,$(@))\n"
+	$(Q)$(HOSTCC) $(HOSTCFLAGS) -include $(obj)/config.h $< -o $@
+
+#######################################################################
+# Build the coreboot_ram (stage 2)
+
+$(obj)/coreboot_ram: $(obj)/coreboot_ram.o $(src)/config/coreboot_ram.ld #ldoptions
+	$(Q)printf "    CC         $(subst $(obj)/,,$(@))\n"
+	$(Q)$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/config/coreboot_ram.ld $(obj)/coreboot_ram.o
+	$(Q)$(NM) -n $(obj)/coreboot_ram | sort > $(obj)/coreboot_ram.map
+
+$(obj)/coreboot_ram.o: $(obj)/arch/i386/lib/c_start.o $(drivers) $(obj)/coreboot.a $(LIBGCC_FILE_NAME)
+	$(Q)printf "    CC         $(subst $(obj)/,,$(@))\n"
+	$(Q)$(CC) -nostdlib -r -o $@ $(obj)/arch/i386/lib/c_start.o $(drivers) -Wl,-\( $(obj)/coreboot.a $(LIBGCC_FILE_NAME) -Wl,-\)
+
+$(obj)/coreboot.a: $(objs)
+	$(Q)printf "    AR         $(subst $(obj)/,,$(@))\n"
+	$(Q)rm -f $(obj)/coreboot.a
+	$(Q)$(AR) cr $(obj)/coreboot.a $(objs)
+
+
+#######################################################################
+# done
+
+endif

src/arch/i386/boot/Makefile.inc

@@ -0,0 +1,10 @@
+
+obj-y += boot.o
+obj-y += coreboot_table.o
+obj-$(CONFIG_MULTIBOOT) += multiboot.o
+obj-y += tables.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += pirq_routing.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += acpigen.o
+obj-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S
+

src/arch/i386/init/Makefile.inc

@@ -0,0 +1 @@
+#

src/arch/i386/lib/Makefile.inc

@@ -0,0 +1,15 @@
+obj-y += c_start.o
+obj-y += cpu.o
+obj-y += pci_ops_conf1.o
+obj-y += pci_ops_conf2.o
+obj-y += pci_ops_mmconf.o
+obj-y += pci_ops_auto.o
+obj-y += exception.o
+
+initobj-y += printk_init.o
+initobj-y += cbfs_and_run.o
+
+ifdef POST_EVALUATION
+$(obj)/arch/i386/lib/console.o :: $(obj)/build.h
+endif
+

src/arch/i386/smp/Makefile.inc

@@ -0,0 +1,5 @@
+obj-$(CONFIG_HAVE_MP_TABLE) += mpspec.o
+# what about this: how awkward.
+#object ioapic.o CONFIG_IOAPIC
+
+

src/arch/ppc/Kconfig

@@ -0,0 +1,13 @@
+config ARCH_POWERPC
+	boolean
+	help
+	  This option is used to set the architecture of a mainboard.
+	  It is usually set in mainboard/*/Kconfig.
+
+config ARCH
+	string
+	default ppc
+	depends on ARCH_POWERPC
+	help
+	  This is the name of the respective subdirectory in arch/.
+

src/boot/Makefile.inc

@@ -0,0 +1,2 @@
+obj-y += hardwaremain.o
+obj-y += selfboot.o

src/console/Kconfig

@@ -0,0 +1,40 @@
+menu "Console Options"
+
+config SERIAL_CONSOLE
+	bool "See output on the serial port console"
+	default y
+
+config TTYS0_BASE
+	hex "I/O base for the serial port (default 0x3f8)"
+	depends on SERIAL_CONSOLE
+	default 0x3f8
+
+config SERIAL_SET_SPEED
+	bool "Override the serial console baud rate"
+	default y
+	depends on SERIAL_CONSOLE
+
+config TTYS0_BAUD
+	int "Serial console baud rate (default 115200)"
+	depends on SERIAL_SET_SPEED
+	default 115200
+
+config USBDEBUG_DIRECT
+	bool "Support a USB debug dongle. Not supported on all chipsets. FIX DEPENDENCY HERE"
+	default n
+
+config CONSOLE_VGA
+	bool
+	default n
+
+config MAXIMUM_CONSOLE_LOGLEVEL
+	int
+	default 9
+
+config DEFAULT_CONSOLE_LOGLEVEL
+	int
+	default 9
+
+endmenu
+
+

src/console/Makefile.inc

@@ -0,0 +1,12 @@
+obj-y +=  printk.o
+obj-y +=  console.o
+obj-y +=  vtxprintf.o
+obj-y +=  vsprintf.o
+initobj-y +=  vtxprintf.o
+initobj-y +=  vsprintf.o
+driver-$(CONFIG_SERIAL_CONSOLE) +=  uart8250_console.o
+driver-$(CONFIG_USBDEBUG_DIRECT) +=  usbdebug_direct_console.o
+driver-$(CONFIG_CONSOLE_VGA) +=  vga_console.o
+driver-$(CONFIG_CONSOLE_BTEXT) +=  btext_console.o
+driver-$(CONFIG_CONSOLE_BTEXT) +=  font-8x16.o
+driver-$(CONFIG_CONSOLE_LOGBUF) +=  logbuf_console.o

src/console/console.c

@@ -8,8 +8,6 @@
 #include <pc80/mc146818rtc.h>
 
 
-static int initialized;
-
 /* initialize the console */
 void console_init(void)
 {
@@ -22,7 +20,6 @@ void console_init(void)
 			continue;
 		driver->init();
 	}
-	initialized = 1;
 }
 
 static void __console_tx_byte(unsigned char byte)
@@ -45,8 +42,6 @@ void console_tx_flush(void)
 
 void console_tx_byte(unsigned char byte)
 {
-	if (!initialized)
-		return;
 	if (byte == '\n')
 		__console_tx_byte('\r');
 	__console_tx_byte(byte);
@@ -55,8 +50,6 @@ void console_tx_byte(unsigned char byte)
 unsigned char console_rx_byte(void)
 {
 	struct console_driver *driver;
-	if (!initialized)
-		return 0;
 	for(driver = console_drivers; driver < econsole_drivers; driver++) {
 		if (driver->tst_byte)
 			break;
@@ -70,8 +63,6 @@ unsigned char console_rx_byte(void)
 int console_tst_byte(void)
 {
 	struct console_driver *driver;
-	if (!initialized)
-		return 0;
 	for(driver = console_drivers; driver < econsole_drivers; driver++)
 		if (driver->tst_byte)
 			return driver->tst_byte();

src/cpu/Kconfig

@@ -0,0 +1,18 @@
+#source src/cpu/amd/Kconfig
+source src/cpu/emulation/Kconfig
+source src/cpu/intel/Kconfig
+source src/cpu/via/Kconfig
+source src/cpu/x86/Kconfig
+source src/cpu/ppc/Kconfig
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xffdf8000 if CPU_INTEL_CORE
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x8000 if CPU_INTEL_CORE
+
+config SMP
+	bool
+	default n

src/cpu/Makefile.inc

@@ -0,0 +1,8 @@
+#input amd
+subdirs-y += intel
+subdirs-y += via
+subdirs-y += emulation
+#input ppc
+#input simple_init
+#input via
+#input x86

src/cpu/amd/Kconfig

@@ -0,0 +1,8 @@
+source src/cpu/amd/socket_754/Kconfig
+source src/cpu/amd/socket_939/Kconfig
+source src/cpu/amd/socket_940/Kconfig
+source src/cpu/amd/socket_AM2/Kconfig
+source src/cpu/amd/socket_AM2r2/Kconfig
+source src/cpu/amd/socket_F/Kconfig
+source src/cpu/amd/socket_F_1207/Kconfig
+source src/cpu/amd/socket_S1G1/Kconfig

src/cpu/amd/socket_F/Kconfig

@@ -0,0 +1,3 @@
+config CPU_AMD_SOCKET_F
+	bool
+	default false

src/cpu/emulation/Kconfig

@@ -0,0 +1,2 @@
+source src/cpu/emulation/qemu-x86/Kconfig
+

src/cpu/emulation/Makefile.inc

@@ -0,0 +1 @@
+subdirs-y += qemu-x86

src/cpu/emulation/qemu-x86/Kconfig

@@ -0,0 +1,4 @@
+config CPU_EMULATION_QEMU_X86
+        bool
+        default false
+

src/cpu/emulation/qemu-x86/Makefile.inc

@@ -0,0 +1 @@
+obj-$(CONFIG_CPU_EMULATION_QEMU_X86) += northbridge.o

src/cpu/intel/Kconfig

@@ -0,0 +1,4 @@
+source src/cpu/intel/model_6ex/Kconfig
+source src/cpu/intel/model_6fx/Kconfig
+source src/cpu/intel/socket_mFCPGA478/Kconfig
+source src/cpu/intel/socket_PGA370/Kconfig

src/cpu/intel/Makefile.inc

@@ -0,0 +1,14 @@
+# Note: from here on down, we are socket-centric. Socket choice determines what other cpu files are included. 
+# Therefore:
+# ONLY include Makefile.inc from socket directories!
+
+subdirs-y += speedstep
+subdirs-y += socket_mFCPGA478
+subdirs-y += socket_PGA370
+
+#socket_mPGA478
+#socket_mPGA479M
+#socket_mPGA603
+#socket_mPGA604
+#socket_mPGA604_533Mhz
+#socket_mPGA604_800Mhz

src/cpu/intel/hyperthreading/Makefile.inc

@@ -0,0 +1 @@
+obj-y += intel_sibling.o

src/cpu/intel/microcode/Makefile.inc

@@ -0,0 +1 @@
+obj-y += microcode.o

src/cpu/intel/model_69x/Makefile.inc

@@ -0,0 +1 @@
+driver-y += model_69x_init.o

src/cpu/intel/model_6dx/Makefile.inc

@@ -0,0 +1 @@
+driver-y += model_6dx_init.o

src/cpu/intel/model_6ex/Kconfig

@@ -0,0 +1,4 @@
+config CPU_INTEL_CORE
+	bool
+	default n
+	select SMP

src/cpu/intel/model_6ex/Makefile.inc

@@ -0,0 +1 @@
+driver-y += model_6ex_init.o

src/cpu/intel/model_6fx/Kconfig

@@ -0,0 +1 @@
+# select HAVE_MOVNTI

src/cpu/intel/model_6fx/Makefile.inc

@@ -0,0 +1 @@
+driver-y += model_6fx_init.o

src/cpu/intel/model_6xx/Makefile.inc

@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Ron Minnich <rminnich@gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+obj-y += model_6xx_init.o
+

src/cpu/intel/socket_PGA370/Kconfig

@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config CPU_INTEL_SOCKET_PGA370
+	bool
+	default false

src/cpu/intel/socket_PGA370/Makefile.inc

@@ -0,0 +1,34 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ifeq ($(CONFIG_CPU_INTEL_SOCKET_PGA370),y)
+	obj-y += socket_PGA370.o
+	subdirs-y += ../model_6xx
+	subdirs-y += ../../x86/tsc
+	subdirs-y += ../../x86/mtrr
+	subdirs-y += ../../x86/fpu
+	subdirs-y += ../../x86/mmx
+	subdirs-y += ../../x86/sse
+	subdirs-y += ../../x86/lapic
+	subdirs-y += ../../x86/cache
+	subdirs-y += ../../x86/smm
+	subdirs-y += ../microcode
+endif
+

src/cpu/intel/socket_mFCPGA478/Kconfig

@@ -0,0 +1,3 @@
+config CPU_INTEL_SOCKET_MFCPGA478
+	bool
+	default false

src/cpu/intel/socket_mFCPGA478/Makefile.inc

@@ -0,0 +1,17 @@
+ifeq ($(CONFIG_CPU_INTEL_SOCKET_MFCPGA478),y)
+	obj-y += socket_mFCPGA478.o
+	subdirs-y += ../model_69x
+	subdirs-y += ../model_6dx
+	subdirs-y += ../model_6ex
+	subdirs-y += ../model_6fx
+	subdirs-y += ../../x86/tsc
+	subdirs-y += ../../x86/mtrr
+	subdirs-y += ../../x86/fpu
+	subdirs-y += ../../x86/mmx
+	subdirs-y += ../../x86/sse
+	subdirs-y += ../../x86/lapic
+	subdirs-y += ../../x86/cache
+	subdirs-y += ../../x86/smm
+	subdirs-y += ../microcode
+	subdirs-y += ../hyperthreading
+endif

src/cpu/intel/speedstep/Makefile.inc

@@ -0,0 +1,5 @@
+ifeq ($(CONFIG_HAVE_ACPI_TABLES), y)
+ifeq ($(CONFIG_CPU_INTEL_SOCKET_MFCPGA478), y)
+	obj-y += acpi.o
+endif
+endif

src/cpu/ppc/Kconfig

@@ -0,0 +1 @@
+#

src/cpu/ppc/Makefile.inc

@@ -0,0 +1,6 @@
+#subdirs-y += ../simple_init
+#subdirs-y += mpc74xx
+#subdirs-y += ppc4xx
+#subdirs-y += ppc7xx
+#subdirs-y += ppc970
+

src/cpu/simple_init/Makefile.inc

@@ -0,0 +1 @@
+obj-y += simple_cpu_init.o

src/cpu/via/Kconfig

@@ -0,0 +1 @@
+source src/cpu/via/model_c7/Kconfig

src/cpu/via/Makefile.inc

@@ -0,0 +1,2 @@
+#subdirs-y += model_c7
+subdirs-y += model_c7

src/cpu/via/model_c7/Kconfig

@@ -0,0 +1,3 @@
+config CPU_VIA_C7
+	bool
+	default n

src/cpu/via/model_c7/Makefile.inc

@@ -0,0 +1,13 @@
+ifeq ($(CONFIG_CPU_VIA_C7),y)
+	subdirs-y += ../../x86/tsc
+	subdirs-y += ../../x86/mtrr
+	subdirs-y += ../../x86/fpu
+	subdirs-y += ../../x86/mmx
+	subdirs-y += ../../x86/sse
+	subdirs-y += ../../x86/lapic
+	subdirs-y += ../../x86/cache
+	subdirs-y += ../../x86/smm
+	subdirs-y += ../../intel/microcode
+endif
+
+obj-y += model_c7_init.o

src/cpu/x86/Kconfig

@@ -0,0 +1,11 @@
+config SERIAL_CPU_INIT
+	bool
+	default y
+
+config XIP_ROM_BASE
+	hex
+	default 0xfffe0000
+
+config XIP_ROM_BASE
+	hex
+	default 0x2000

src/cpu/x86/cache/Makefile.inc

@@ -0,0 +1 @@
+obj-y += cache.o

src/cpu/x86/fpu/Makefile.inc

@@ -0,0 +1 @@
+#

src/cpu/x86/lapic/Makefile.inc

@@ -0,0 +1,4 @@
+obj-y += lapic.o
+obj-y += lapic_cpu_init.o
+obj-y += secondary.o
+

src/cpu/x86/mmx/Makefile.inc

@@ -0,0 +1 @@
+#

src/cpu/x86/mtrr/Makefile.inc

@@ -0,0 +1 @@
+obj-y += mtrr.o

src/cpu/x86/smm/Makefile.inc

@@ -0,0 +1,45 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+##if CONFIG_HAVE_SMI_HANDLER
+##	object smmrelocate.S
+##
+##	smmobject smmhandler.S
+##	smmobject smihandler.o
+##
+##	makerule smm.o
+##		depends	"$(SMM-OBJECTS) $(TOP)/src/console/printk.o $(TOP)/src/console/vtxprintf.o $(LIBGCC_FILE_NAME)" 
+##		action	"$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ $^"
+##	end
+##
+##	makerule smm
+##		depends	"smm.o $(TOP)/src/cpu/x86/smm/smm.ld ldoptions" 
+##		action	"$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o smm.elf -T $(TOP)/src/cpu/x86/smm/smm.ld smm.o"
+##		action 	"$(CONFIG_CROSS_COMPILE)nm -n smm.elf | sort > smm.map"
+##		action  "$(OBJCOPY) -O binary smm.elf smm"
+##	end
+##
+##	makerule smm_bin.c
+##		depends "smm"
+##		action "(echo 'unsigned char smm[] = {'; od -vtx1 smm | sed -e 's,^[0-9]* *,,' -e 's:[0-9a-f][0-9a-f] :0x&,:g' -e 's:[0-9a-f][0-9a-f]$$:0x&,:'; echo '}; unsigned int smm_len = '; wc -c smm |awk '{print $$1;}' ; echo ';')  > smm_bin.c"
+##	end
+##
+##	object ./smm_bin.o
+##end

src/cpu/x86/sse/Makefile.inc

@@ -0,0 +1 @@
+#

src/cpu/x86/tsc/Makefile.inc

@@ -0,0 +1,7 @@
+obj-y += delay_tsc.o
+
+# default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0
+# if CONFIG_UDELAY_TSC 
+#	default CONFIG_HAVE_INIT_TIMER=1
+# 	object delay_tsc.o  
+# end

src/devices/Kconfig

@@ -0,0 +1,53 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 coresystems GmbH
+## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+menu "Devices"
+
+config VGA_ROM_RUN
+	bool
+	help
+	  Execute PCI/AGP option ROMs if available. This is required to
+	  enable PCI/AGP VGA plugin cards. 
+
+choice
+        prompt "Execute PCI Option ROMs"
+        default  PCI_OPTION_ROM_RUN_REALMODE
+        help
+          Execute PCI/AGP option ROMs if available. You can choose to
+          execute PCI option ROMs natively (32bit x86 system required),
+          in an emulator (x86emu), or ignore option ROM execution.
+
+	config PCI_OPTION_ROM_RUN_REALMODE
+		prompt "Run VGA ROMs"
+		bool
+		select VGA_ROM_RUN
+		help
+	  	Execute PCI/AGP option ROMs if available. This is required to
+	  	enable PCI/AGP VGA plugin cards. 
+
+	config NO_RUN
+		prompt "DO NOT Run VGA ROMs"
+		bool
+		help
+	  	Execute PCI/AGP option ROMs if available. This is required to
+	  	enable PCI/AGP VGA plugin cards. 
+
+endchoice
+endmenu

src/devices/Makefile.inc

@@ -0,0 +1,21 @@
+obj-y += device.o
+obj-y += root_device.o
+obj-y += device_util.o
+obj-y += pci_device.o
+obj-y += hypertransport.o
+obj-y += pcix_device.o
+obj-y += pciexp_device.o
+obj-y += agp_device.o
+obj-y += cardbus_device.o
+obj-y += pnp_device.o
+obj-y += pci_ops.o
+obj-y += smbus_ops.o
+
+ifeq ($(CONFIG_PCI_ROM_RUN),y)
+obj-$(CONFIG_PCI_ROM_RUN) += pci_rom.o
+subdirs-$(CONFIG_PCI_ROM_RUN) += ../../util/x86emu
+else
+obj-$(CONFIG_VGA_ROM_RUN) += pci_rom.o
+subdirs-$(CONFIG_VGA_ROM_RUN) += ../../util/x86emu
+endif
+

src/drivers/Makefile.inc

@@ -0,0 +1 @@
+subdirs-y += pci

src/drivers/pci/Makefile.inc

@@ -0,0 +1 @@
+subdirs-y += onboard

src/drivers/pci/onboard/Makefile.inc

@@ -0,0 +1 @@
+obj-y += onboard.o

src/lib/Makefile.inc

@@ -0,0 +1,29 @@
+obj-y +=  clog2.o
+obj-y +=  uart8250.o
+obj-y +=  memset.o
+obj-y +=  memcpy.o
+obj-y +=  memcmp.o
+obj-y +=  memmove.o
+obj-y +=  malloc.o
+obj-y +=  delay.o
+obj-y +=  fallback_boot.o
+obj-y +=  compute_ip_checksum.o
+obj-y +=  version.o
+obj-y +=  cbfs.o
+obj-y +=  lzma.o
+#obj-y +=  lzmadecode.o
+
+initobj-y  +=   uart8250.o
+initobj-y  +=   memset.o
+initobj-y  +=   memcpy.o
+initobj-y  +=   memcmp.o
+initobj-y  +=   cbfs.o
+initobj-y  +=   lzma.o
+#initobj-y  +=   lzmadecode.o
+
+obj-$(CONFIG_USBDEBUG_DIRECT)  +=  usbdebug_direct.o
+obj-$(CONFIG_COMPRESSED_PAYLOAD_LZMA)  +=  lzma.o
+
+ifdef POST_EVALUATION
+$(obj)/lib/version.o :: $(obj)/build.h
+endif

src/mainboard/Kconfig

@@ -0,0 +1,343 @@
+
+menu "Mainboard"
+
+choice
+	prompt "Mainboard vendor"
+	default VENDOR_EMULATION
+
+config VENDOR_ATREND
+	bool "A-Trend"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_ABIT
+	bool "ABIT"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_ADVANTECH
+	bool "Advantech"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_AGAMI
+	bool "Agami"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_AMD
+	bool "AMD"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_ARIMA
+	bool "Arima"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_ARTEC
+	bool "Artec Group"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_ASI
+	bool "ASI"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_ASUS
+	bool "ASUS"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_AXUS
+	bool "AXUS"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_AZZA
+	bool "Azza"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_BCOM
+	bool "BCOM"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_BIOSTAR
+	bool "Biostar"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_BROADCOM
+	bool "Broadcom"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_COMPAQ
+	bool "Compaq"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_DELL
+	bool "DELL"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_DIGITALLOGIC
+	bool "Digital Logic"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_EAGLELION
+	bool "Eagle Lion"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_EMBEDDEDPLANET
+	bool "Embedded Planet"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_EMULATION
+	bool "Emulation"
+	help
+	  Select this option for various system emulators, such as QEMU.
+
+config VENDOR_GIGABYTE
+	bool "Gigabyte"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_HP
+	bool "HP"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_IBM
+	bool "IBM"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_IEI
+	bool "IEI"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_INTEL
+	bool "Intel"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_IWILL
+	bool "Iwill"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_JETWAY
+	bool "Jetway"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_KONTRON
+	bool "Kontron"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_LIPPERT
+	bool "Lippert"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_MOTOROLA
+	bool "Motorola"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_MSI
+	bool "MSI"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_NEC
+	bool "NEC"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_NEWISYS
+	bool "Newisys"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_NVIDIA
+	bool "NVidia"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_OLPC
+	bool "OLPC"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_PCENGINES
+	bool "PC Engines"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_RCA
+	bool "RCA"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_SUNW
+	bool "SUN Microsystems"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_SUPERMICRO
+	bool "Supermicro"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_TECHNEXION
+	bool "Technexion"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_THOMSON
+	bool "Thomson"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_TOTALIMPACT
+	bool "Total Impact"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_TYAN
+	bool "Tyan"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_VIA
+	bool "VIA"
+	help
+	  Select this option for systems from the vendor.
+
+endchoice
+
+config MAINBOARD_VENDOR
+        string
+        default "EMULATION"
+        depends on VENDOR_EMULATION
+
+config MAINBOARD_VENDOR
+        string
+        default "KONTRON"
+        depends on VENDOR_KONTRON
+
+config MAINBOARD_VENDOR
+        string
+        default "VIA"
+        depends on VENDOR_VIA
+
+config MAINBOARD_VENDOR
+        string
+        default "AMD"
+        depends on VENDOR_AMD
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x1019
+        depends on VENDOR_VIA
+
+source "src/mainboard/a-trend/Kconfig"
+source "src/mainboard/abit/Kconfig"
+source "src/mainboard/advantech/Kconfig"
+source "src/mainboard/amd/Kconfig"
+source "src/mainboard/arima/Kconfig"
+source "src/mainboard/artecgroup/Kconfig"
+source "src/mainboard/asi/Kconfig"
+source "src/mainboard/asus/Kconfig"
+source "src/mainboard/axus/Kconfig"
+source "src/mainboard/azza/Kconfig"
+source "src/mainboard/bcom/Kconfig"
+source "src/mainboard/biostar/Kconfig"
+source "src/mainboard/broadcom/Kconfig"
+source "src/mainboard/compaq/Kconfig"
+source "src/mainboard/dell/Kconfig"
+source "src/mainboard/digitallogic/Kconfig"
+source "src/mainboard/eaglelion/Kconfig"
+source "src/mainboard/embeddedplanet/Kconfig"
+source "src/mainboard/emulation/Kconfig"
+source "src/mainboard/gigabyte/Kconfig"
+source "src/mainboard/hp/Kconfig"
+source "src/mainboard/ibm/Kconfig"
+source "src/mainboard/iei/Kconfig"
+source "src/mainboard/intel/Kconfig"
+source "src/mainboard/iwill/Kconfig"
+source "src/mainboard/jetway/Kconfig"
+source "src/mainboard/kontron/Kconfig"
+source "src/mainboard/lippert/Kconfig"
+source "src/mainboard/motorola/Kconfig"
+source "src/mainboard/msi/Kconfig"
+source "src/mainboard/nec/Kconfig"
+source "src/mainboard/newisys/Kconfig"
+source "src/mainboard/nvidia/Kconfig"
+source "src/mainboard/olpc/Kconfig"
+source "src/mainboard/pcengines/Kconfig"
+source "src/mainboard/rca/Kconfig"
+source "src/mainboard/sunw/Kconfig"
+source "src/mainboard/supermicro/Kconfig"
+source "src/mainboard/technexion/Kconfig"
+source "src/mainboard/technologic/Kconfig"
+source "src/mainboard/televideo/Kconfig"
+source "src/mainboard/thomson/Kconfig"
+source "src/mainboard/totalimpact/Kconfig"
+source "src/mainboard/tyan/Kconfig"
+source "src/mainboard/via/Kconfig"
+
+choice
+	prompt "ROM chip size"
+	default COREBOOT_ROMSIZE_KB_256
+
+config COREBOOT_ROMSIZE_KB_128
+	bool "128 KB"
+	help
+	  Choose this option if you have a 128 KB ROM chip.
+
+config COREBOOT_ROMSIZE_KB_256
+	bool "256 KB"
+	help
+	  Choose this option if you have a 256 KB ROM chip.
+
+config COREBOOT_ROMSIZE_KB_512
+	bool "512 KB"
+	help
+	  Choose this option if you have a 512 KB ROM chip.
+
+config COREBOOT_ROMSIZE_KB_1024
+	bool "1024 KB (1 MB)"
+	help
+	  Choose this option if you have a 1024 KB (1 MB) ROM chip.
+
+config COREBOOT_ROMSIZE_KB_2048
+	bool "2048 KB (2 MB)"
+	help
+	  Choose this option if you have a 2048 KB (2 MB) ROM chip.
+
+endchoice
+
+config COREBOOT_ROMSIZE_KB
+	int
+	default 128 if COREBOOT_ROMSIZE_KB_128
+	default 256 if COREBOOT_ROMSIZE_KB_256
+	default 512 if COREBOOT_ROMSIZE_KB_512
+	default 1024 if COREBOOT_ROMSIZE_KB_1024
+	default 2048 if COREBOOT_ROMSIZE_KB_2048
+	help
+	  Map the config names to an integer.
+
+endmenu
+

src/mainboard/a-trend/Kconfig

@@ -0,0 +1 @@
+#

src/mainboard/a-trend/atc-6220/devicetree.cb

@@ -0,0 +1,59 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 7.0 on			# ISA bridge
+        chip superio/winbond/w83977tf	# Super I/O (FIXME: It's W83977EF!)
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 3f0.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.3 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.6 on		# Consumer IR
+          end
+          device pnp 3f0.7 on		# GPIO 1
+          end
+          device pnp 3f0.8 on		# GPIO 2
+          end
+          device pnp 3f0.a on		# ACPI
+          end
+        end
+      end
+      device pci 7.1 on	end		# IDE
+      device pci 7.2 on	end		# USB
+      device pci 7.3 on end		# ACPI
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "0"
+      register "ide0_drive1_udma33_enable" = "0"
+      register "ide1_drive0_udma33_enable" = "0"
+      register "ide1_drive1_udma33_enable" = "0"
+    end
+  end
+end

src/mainboard/a-trend/atc-6240/devicetree.cb

@@ -0,0 +1,69 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 7.0 on			# ISA bridge
+        chip superio/winbond/w83627hf	# Super I/O
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+            drq 0x74 = 3
+          end
+          device pnp 3f0.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.3 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.6 on		# Consumer IR
+            io 0x60 = 0x00
+          end
+          device pnp 3f0.7 on		# Game port / MIDI / GPIO 1
+            io 0x60 = 0x201
+            io 0x62 = 0x330
+            irq 0x70 = 9
+          end
+          device pnp 3f0.8 off		# GPIO 2 / WDT
+          end
+          device pnp 3f0.9 off		# GPIO 3
+          end
+          device pnp 3f0.a off		# ACPI
+          end
+          device pnp 3f0.b off		# HWM (TODO)
+          end
+        end
+      end
+      device pci 7.1 on	end		# IDE
+      device pci 7.2 on	end		# USB
+      device pci 7.3 on end		# ACPI
+      device pci c.0 on end		# Onboard audio (ES1371)
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "0"
+      register "ide0_drive1_udma33_enable" = "0"
+      register "ide1_drive0_udma33_enable" = "0"
+      register "ide1_drive1_udma33_enable" = "0"
+    end
+  end
+end

src/mainboard/abit/Kconfig

@@ -0,0 +1 @@
+#

src/mainboard/abit/be6-ii_v2_0/devicetree.cb

@@ -0,0 +1,59 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 7.0 on			# ISA bridge
+        chip superio/winbond/w83977tf	# Super I/O (FIXME: It's W83977EF!)
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 3f0.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.3 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.6 on		# Consumer IR
+          end
+          device pnp 3f0.7 on		# GPIO 1
+          end
+          device pnp 3f0.8 on		# GPIO 2
+          end
+          device pnp 3f0.a on		# ACPI
+          end
+        end
+      end
+      device pci 7.1 on	end		# IDE, UDMA/33 (part of 82371EB)
+      device pci 7.2 on	end		# USB
+      device pci 7.3 on end		# ACPI
+      device pci 13.0 on end		# IDE, UDMA/66 (HPT366 controller)
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      register "ide0_drive0_udma33_enable" = "1"
+      register "ide0_drive1_udma33_enable" = "1"
+      register "ide1_drive0_udma33_enable" = "1"
+      register "ide1_drive1_udma33_enable" = "1"
+    end
+  end
+end

src/mainboard/advantech/Kconfig

@@ -0,0 +1 @@
+#

src/mainboard/advantech/pcm-5820/devicetree.cb

@@ -0,0 +1,56 @@
+chip northbridge/amd/gx1		# Northbridge
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    chip southbridge/amd/cs5530		# Southbridge
+      device pci 12.0 on		# ISA bridge
+        chip superio/winbond/w83977f	# SUper I/O
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 3f0.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.3 on		# COM2
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.4 on		# RTC / On-Now control
+            io 0x60 = 0x70
+            irq 0x70 = 8
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard / mouse
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.6 on		# IR
+            # TODO?
+          end
+          device pnp 3f0.7 on		# GPIO 1
+            # TODO?
+          end
+          device pnp 3f0.8 on		# GPIO 2
+            # TODO?
+          end
+        end
+      end
+      device pci 12.1 on end		# SMI
+      device pci 12.2 on end		# IDE
+      device pci 12.3 on end		# Audio (onboard)
+      device pci 12.4 on end		# VGA
+      device pci 13.0 on end		# USB
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+    end
+  end
+  chip cpu/amd/model_gx1		# CPU
+  end
+end

src/mainboard/amd/Kconfig

@@ -0,0 +1 @@
+source "src/mainboard/amd/serengeti_cheetah/Kconfig"

src/mainboard/amd/db800/devicetree.cb

@@ -0,0 +1,68 @@
+chip northbridge/amd/lx
+	device pci_domain 0 on
+		device pci 1.0 on end				# Northbridge
+		device pci 1.1 on end				# Graphics
+		chip southbridge/amd/cs5536
+			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
+			# SIRQ Mode = Active(Quiet) mode. Save power....
+			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
+			register "lpc_serirq_enable" = "0x0000105a"
+			register "lpc_serirq_polarity" = "0x0000EFA5"
+			register "lpc_serirq_mode" = "1"
+			register "enable_gpio_int_route" = "0x0D0C0700"
+			register "enable_ide_nand_flash" = "0"	# 0:ide mode, 1:flash
+			register "enable_USBP4_device" = "1"	# 0: host, 1:device
+			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+			register "com1_enable" = "0"
+			register "com1_address" = "0x3F8"
+			register "com1_irq" = "4"
+			register "com2_enable" = "0"
+			register "com2_address" = "0x2F8"
+			register "com2_irq" = "3"
+			register "unwanted_vpci[0]" = "0"	# End of list has a zero
+			device pci d.0 on end			# Ethernet
+			device pci e.0 on end			# Slot1
+			device pci f.0 on			# ISA Bridge
+				chip superio/winbond/w83627hf
+					device pnp 2e.0 off	# Floppy
+						io 0x60 = 0x3f0
+						irq 0x70 = 6
+						drq 0x74 = 2
+					end
+					device pnp 2e.1 off	# Parallel port
+						io 0x60 = 0x378
+						irq 0x70 = 7
+					end
+					device pnp 2e.2 on	# Com1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 off end	# Com2
+					device pnp 2e.5 on	# Keyboard
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1
+						irq 0x72 = 12
+					end
+					device pnp 2e.6 off end	# CIR
+					device pnp 2e.7 off end	# GAME_MIDI_GIPO1
+					device pnp 2e.8 off end	# GPIO2
+					device pnp 2e.9 off end	# GPIO3
+					device pnp 2e.a off end	# ACPI
+					device pnp 2e.b off end	# HW Monitor
+				end
+			end
+			device pci f.2 on end			# IDE Controller
+			device pci f.3 on end			# Audio
+			device pci f.4 on end			# OHCI
+			device pci f.5 on end			# EHCI
+		end
+	end
+	# APIC cluster is late CPU init.
+	device apic_cluster 0 on
+		chip cpu/amd/model_lx
+			device apic 0 on end
+		end
+	end
+end
+

src/mainboard/amd/dbm690t/devicetree.cb

@@ -0,0 +1,117 @@
+chip northbridge/amd/amdk8/root_complex
+	device apic_cluster 0 on
+		chip cpu/amd/socket_S1G1
+		device apic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on #  southbridge
+				chip southbridge/amd/rs690
+					device pci 0.0 on end # HT  	0x7910
+					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
+						chip drivers/pci/onboard
+							device pci 5.0 on end	# Internal Graphics 0x791F
+							register "rom_address" = "0xfff00000"
+						end
+					end
+					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
+					device pci 3.0 off end # PCIE P2P bridge	0x791b
+					device pci 4.0 on end # PCIE P2P bridge 0x7914
+					device pci 5.0 on end # PCIE P2P bridge 0x7915
+					device pci 6.0 on end # PCIE P2P bridge 0x7916
+					device pci 7.0 on end # PCIE P2P bridge 0x7917
+					device pci 8.0 off end # NB/SB Link P2P bridge
+					register "vga_rom_address" = "0xfff00000"
+					register "gpp_configuration" = "4"
+					register "port_enable" = "0xfc"
+					register "gfx_dev2_dev3" = "1"
+					register "gfx_dual_slot" = "0"
+					register "gfx_lane_reversal" = "0"
+					register "gfx_tmds" = "0"
+					register "gfx_compliance" = "0"
+					register "gfx_reconfiguration" = "1"
+					register "gfx_link_width" = "0"
+				end
+				chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
+					device pci 12.0 on end # SATA  0x4380
+					device pci 13.0 on end # USB   0x4387
+					device pci 13.1 on end # USB   0x4388
+					device pci 13.2 on end # USB   0x4389
+					device pci 13.3 on end # USB   0x438a
+					device pci 13.4 on end # USB   0x438b
+					device pci 13.5 on end # USB 2 0x4386
+	 				device pci 14.0 on # SM        0x4385
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-0
+							device i2c 52 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-1
+							device i2c 53 on end
+						end
+					end # SM
+					device pci 14.1 on end # IDE    0x438c
+					device pci 14.2 on end # HDA    0x4383
+					device pci 14.3 on # LPC	0x438d
+						chip superio/ite/it8712f
+							device pnp 2e.0 off #  Floppy
+								io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp 2e.1 on #  Com1
+								io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.2 off #  Com2
+								io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.3 off #  Parallel Port
+								io 0x60 = 0x378
+								irq 0x70 = 7
+							end
+							device pnp 2e.4 off end #  EC
+							device pnp 2e.5 on #  Keyboard
+								io 0x60 = 0x60
+								io 0x62 = 0x64
+								irq 0x70 = 1
+							end
+							device pnp 2e.6 on #  Mouse
+								irq 0x70 = 12
+							end
+							device pnp 2e.7 off #  GPIO, must be closed for unresolved reason.
+							end
+							device pnp 2e.8 off #  MIDI
+								io 0x60 = 0x300
+								irq 0x70 = 9
+							end
+							device pnp 2e.9 off #  GAME
+								io 0x60 = 0x220
+							end
+							device pnp 2e.a off end #  CIR
+						end	#superio/ite/it8712f
+					end		#LPC
+					device pci 14.4 on end # PCI 0x4384
+					device pci 14.5 on end # ACI 0x4382
+					device pci 14.6 on end # MCI 0x438e
+					register "ide0_enable" = "1"
+					register "sata0_enable" = "1"
+					register "hda_viddid" = "0x10ec0882"
+				end	#southbridge/amd/sb600
+			end #  device pci 18.0
+
+			device pci 18.0 on end
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end		#northbridge/amd/amdk8
+	end #pci_domain
+end		#northbridge/amd/amdk8/root_complex
+

src/mainboard/amd/norwich/devicetree.cb

@@ -0,0 +1,41 @@
+chip northbridge/amd/lx
+	device pci_domain 0 on
+		device pci 1.0 on end	# Northbridge
+		device pci 1.1 on end	# Graphics
+		chip southbridge/amd/cs5536
+			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
+			# SIRQ Mode = Active(Quiet) mode. Save power....
+			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
+			register "lpc_serirq_enable" = "0x00001002"
+			register "lpc_serirq_polarity" = "0x0000EFFD"
+			register "lpc_serirq_mode" = "1"
+			register "enable_gpio_int_route" = "0x0D0C0700"
+			register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+			register "enable_USBP4_device" = "0"	#0: host, 1:device
+			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+			register "com1_enable" = "1"
+			register "com1_address" = "0x3F8"
+			register "com1_irq" = "4"
+			register "com2_enable" = "0"
+			register "com2_address" = "0x2F8"
+			register "com2_irq" = "3"
+			register "unwanted_vpci[0]" = "0"	# End of list has a zero
+			device pci b.0 on end	# Slot 3
+			device pci c.0 on end	# Slot 4
+			device pci d.0 on end	# Slot 1
+			device pci e.0 on end	# Slot 2
+			device pci f.0 on end	# ISA Bridge
+			device pci f.2 on end	# IDE Controller
+			device pci f.3 on end	# Audio
+			device pci f.4 on end	# OHCI
+			device pci f.5 on end	# EHCI
+		end
+	end
+	# APIC cluster is late CPU init.
+	device apic_cluster 0 on
+		chip cpu/amd/model_lx
+			device apic 0 on end
+		end
+	end
+end
+

src/mainboard/amd/pistachio/devicetree.cb

@@ -0,0 +1,77 @@
+chip northbridge/amd/amdk8/root_complex
+	device apic_cluster 0 on
+		chip cpu/amd/socket_AM2
+		device apic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on #  southbridge, K8 HT Configuration
+				chip southbridge/amd/rs690
+					device pci 0.0 on end # HT  	0x7910
+				#	device pci 0.1 off end # CLK
+					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
+						chip drivers/pci/onboard
+							device pci 5.0 on end	# Internal Graphics 0x791F
+							register "rom_address" = "0xfff00000"
+						end
+					end
+					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
+					device pci 3.0 off end # PCIE P2P bridge	0x791b
+					device pci 4.0 on end # PCIE P2P bridge 0x7914
+					device pci 5.0 on end # PCIE P2P bridge 0x7915
+					device pci 6.0 on end # PCIE P2P bridge 0x7916
+					device pci 7.0 on end # PCIE P2P bridge 0x7917
+					device pci 8.0 off end # NB/SB Link P2P bridge
+					register "vga_rom_address" = "0xfff00000"
+					register "gpp_configuration" = "4"
+					register "port_enable" = "0xfc"
+					register "gfx_dev2_dev3" = "1"
+					register "gfx_dual_slot" = "0"
+					register "gfx_lane_reversal" = "0"
+					register "gfx_tmds" = "0"
+					register "gfx_compliance" = "0"
+					register "gfx_reconfiguration" = "1"
+					register "gfx_link_width" = "0"
+				end
+				chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
+					device pci 12.0 on end # SATA  0x4380
+					device pci 13.0 on end # USB   0x4387
+					device pci 13.1 on end # USB   0x4388
+					device pci 13.2 on end # USB   0x4389
+					device pci 13.3 on end # USB   0x438a
+					device pci 13.4 on end # USB   0x438b
+					device pci 13.5 on end # USB 2 0x4386
+	 				device pci 14.0 on # SM        0x4385
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 off end
+						end
+						chip drivers/generic/generic #dimm 0-1-0
+							device i2c 52 off end
+						end
+						chip drivers/generic/generic #dimm 0-1-1
+							device i2c 53 off end
+						end
+					end # SM
+				device pci 14.1 on end # IDE    0x438c
+				device pci 14.2 on end # HDA    0x4383
+				device pci 14.3 on end # LPC	0x438d
+				device pci 14.4 on end # PCI 0x4384
+				device pci 14.5 on end # ACI 0x4382
+				device pci 14.6 on end # MCI 0x438e
+					register "ide0_enable" = "1"
+					register "sata0_enable" = "1"
+					register "hda_viddid" = "0x10ec0882"
+				end	#southbridge/amd/sb600
+			end #  device pci 18.0
+
+			device pci 18.1 on end		# K8 Address Map
+			device pci 18.2 on end		# K8 DRAM Controller and HT Trace Mode
+			device pci 18.3 on end		# K8 Miscellaneous Control
+		end		#northbridge/amd/amdk8
+	end #pci_domain
+end		#northbridge/amd/amdk8/root_complex
+

src/mainboard/amd/rumba/devicetree.cb

@@ -0,0 +1,21 @@
+chip northbridge/amd/gx2
+	device apic_cluster 0 on
+		chip cpu/amd/model_gx2
+			device apic 0 on end
+		end
+	end
+  	device pci_domain 0 on 
+    		device pci 1.0 on end
+		device pci 1.1 on end
+      		chip southbridge/amd/cs5536
+			register "lpc_serirq_enable" = "0x80"  # enabled with default timing
+        		device pci d.0 on end	# Realtek 8139 LAN
+        		device pci f.0 on end	# ISA Bridge
+        		device pci f.2 on end	# IDE Controller
+        		device pci f.3 on end 	# Audio
+        		device pci f.4 on end	# OHCI
+			device pci f.4 on end	# UHCI
+      		end
+    	end
+end
+

src/mainboard/amd/serengeti_cheetah/Kconfig

@@ -0,0 +1,49 @@
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_AMD
+
+config BOARD_AMD_SERENGETI_CHEETAH
+	bool "SERENGETI_CHEETAH"
+	select ARCH_X86
+	select CPU_AMD_K8
+	select CPU_AMD_SOCKET_F
+	select NORTHBRIDGE_AMD_AMDK8
+	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+	select SOUTHBRIDGE_AMD_AMD8111
+	select SUPERIO_WINBOND_W83627THF
+	select PIRQ_TABLE
+	select MMCONF_SUPPORT
+	select USE_PRINTK_IN_CAR
+	help
+	AMD Serengeti Series mainboards
+endchoice
+
+config MAINBOARD_DIR
+	string
+	default amd/serengeti_cheetah
+	depends on BOARD_AMD_SERENGETI_CHEETAH
+
+#config DCACHE_RAM_BASE
+#	hex
+#	default 0xffdf8000
+#	depends on BOARD_AMD_SERENGETI_CHEETAH
+#	
+#config DCACHE_RAM_SIZE
+#	hex
+#	default 0x8000
+#	depends on BOARD_AMD_SERENGETI_CHEETAH
+
+config LB_CKS_RANGE_END
+	int
+	default 122
+	depends on BOARD_AMD_SERENGETI_CHEETAH
+
+config LB_CKS_LOC
+	int
+        default 123
+	depends on BOARD_AMD_SERENGETI_CHEETAH
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Serengeti-Cheetah"
+	depends on BOARD_AMD_SERENGETI_CHEETAH

src/mainboard/amd/serengeti_cheetah/Makefile.inc

@@ -0,0 +1,95 @@
+##
+## This file is part of the coreboot project.
+## 
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+##
+## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
+## 
+
+driver-y +=  mainboard.o
+
+#needed by irq_tables and mptable and acpi_tables
+obj-y += get_bus_conf.o
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  dsdt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  acpi_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  fadt.o
+
+#./ssdt.o is in northbridge/amd/amdk8/Config.lb
+obj-$(CONFIG_ACPI_SSDTX_NUM) +=  ssdt2.o
+obj-$(CONFIG_ACPI_SSDTX_NUM) +=  ssdt3.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  ssdt4.o
+
+# This is part of the conversion to init-obj and away from included code. 
+
+initobj-y += crt0.o
+# FIXME in $(top)/Makefile
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+ifdef POST_EVALUATION
+
+MAINBOARD_OPTIONS=\
+	-DCONFIG_AP_IN_SIPI_WAIT=1 \
+	-DCONFIG_USE_PRINTK_IN_CAR=1 \
+	-DCONFIG_HAVE_HIGH_TABLES=1 \
+	-DCONFIG_MMCONF_SUPPORT=1 \
+	-DCONFIG_MMCONF_BASE_ADDRESS=0xf0000000
+
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
+	iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
+	perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex
+	mv pci2.hex ssdt2.c
+
+$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
+	iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/
+	perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex
+	mv pci3.hex ssdt3.c
+           
+$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
+	iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
+	perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
+	mv pci4.hex ssdt4.c
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
+	perl -e 's/\.rodata/.rom.data/g' -pi $@
+	perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+

src/mainboard/amd/serengeti_cheetah/devicetree.cb

@@ -0,0 +1,159 @@
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_F
+                        device apic 0 on end
+                end
+        end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on #  northbridge 
+				#  devices on link 0, link 0 == LDT 0
+				chip southbridge/amd/amd8132
+					# the on/off keyword is mandatory
+					device pci 0.0 on end
+					device pci 0.1 on end
+					device pci 1.0 on end
+					device pci 1.1 on end
+				end
+				chip southbridge/amd/amd8111
+					# this "device pci 0.0" is the parent the next one
+					# PCI bridge
+					device pci 0.0 on
+						device pci 0.0 on end
+						device pci 0.1 on end
+						device pci 0.2 off end
+						device pci 1.0 off end
+					end
+					device pci 1.0 on
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 off #  Floppy
+                	                 			io 0x60 = 0x3f0
+                	                			irq 0x70 = 6
+                	                			drq 0x74 = 2
+							end
+                	        			device pnp 2e.1 off #  Parallel Port
+                	                 			io 0x60 = 0x378
+                	                			irq 0x70 = 7
+							end
+                	        			device pnp 2e.2 on #  Com1
+                	                 			io 0x60 = 0x3f8
+                	                			irq 0x70 = 4
+							end
+                	        			device pnp 2e.3 off #  Com2
+                	                 			io 0x60 = 0x2f8
+                	                			irq 0x70 = 3
+							end
+                	        			device pnp 2e.5 on #  Keyboard
+                	                 			io 0x60 = 0x60
+                	                 			io 0x62 = 0x64
+                	                			irq 0x70 = 1
+								irq 0x72 = 12
+							end
+                	        			device pnp 2e.6 off #  CIR
+								io 0x60 = 0x100
+							end
+                	        			device pnp 2e.7 off #  GAME_MIDI_GIPO1
+								io 0x60 = 0x220
+								io 0x62 = 0x300
+								irq 0x70 = 9
+							end						
+                	        			device pnp 2e.8 off end #  GPIO2
+                	        			device pnp 2e.9 off end #  GPIO3
+                	        			device pnp 2e.a off end #  ACPI
+                	        			device pnp 2e.b on #  HW Monitor
+ 					 			io 0x60 = 0x290
+								irq 0x70 = 5
+                					end
+						end
+					end
+					device pci 1.1 on end
+					device pci 1.2 on end
+					device pci 1.3 on
+                                                chip drivers/i2c/i2cmux # pca9556 smbus mux
+                                                        device i2c 18 on #0 pca9516 1
+                                                                chip drivers/generic/generic #dimm 0-0-0
+                                                                        device i2c 50 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-0-1
+                                                                        device i2c 51 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-0
+                                                                        device i2c 52 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-1
+                                                                        device i2c 53 on end
+                                                                end
+                                                        end
+                                                        device i2c 18 on #1 pca9516 2
+                                                                chip drivers/generic/generic #dimm 1-0-0
+                                                                        device i2c 50 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-0-1
+                                                                        device i2c 51 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-1-0
+                                                                        device i2c 52 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-1-1
+                                                                        device i2c 53 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-2-0
+                                                                        device i2c 54 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-2-1
+                                                                        device i2c 55 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-3-0
+                                                                        device i2c 56 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-3-1
+                                                                        device i2c 57 on end
+                                                                end
+                                                        end
+						end
+					end # acpi
+					device pci 1.5 off end
+					device pci 1.6 off end
+                	                register "ide0_enable" = "1"
+                	                register "ide1_enable" = "1"
+				end
+			end #  device pci 18.0
+
+                        device pci 18.0 on end
+                        device pci 18.0 on end  
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end
+                chip northbridge/amd/amdk8
+                        device pci 19.0 on #  northbridge
+                                chip southbridge/amd/amd8151
+                                        # the on/off keyword is mandatory
+                                        device pci 0.0 on end
+                                        device pci 1.0 on end
+                                end
+                        end #  device pci 19.0
+
+                        device pci 19.0 on end
+                        device pci 19.0 on end
+                        device pci 19.1 on end
+                        device pci 19.2 on end
+                        device pci 19.3 on end
+                end
+
+
+	end #pci_domain
+#        chip drivers/generic/debug
+#        	device pnp 0.0 off end # chip name
+#                device pnp 0.1 on end # pci_regs_all
+#                device pnp 0.2 off end # mem
+#                device pnp 0.3 off end # cpuid
+#                device pnp 0.4 off end # smbus_regs_all
+#                device pnp 0.5 off end # dual core msr
+#                device pnp 0.6 off end # cache size
+#                device pnp 0.7 off end # tsc
+#       end
+
+end
+
+

src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb

@@ -0,0 +1,152 @@
+chip northbridge/amd/amdfam10/root_complex
+	device apic_cluster 0 on
+		chip cpu/amd/socket_F_1207  #L1 and DDR2
+			 device apic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		chip northbridge/amd/amdfam10
+			device pci 18.0 on #  northbridge
+				#  devices on link 0, link 0 == LDT 0
+				chip southbridge/amd/amd8132
+					# the on/off keyword is mandatory
+					device pci 0.0 on end
+					device pci 0.1 on end
+					device pci 1.0 on end
+					device pci 1.1 on end
+				end
+				chip southbridge/amd/amd8111
+					# this "device pci 0.0" is the parent the next one
+					# PCI bridge
+					device pci 0.0 on
+						device pci 0.0 on end
+						device pci 0.1 on end
+						device pci 0.2 off end
+						device pci 1.0 off end
+					end
+					device pci 1.0 on
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 off #  Floppy
+								io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp 2e.1 off #  Parallel Port
+								io 0x60 = 0x378
+								irq 0x70 = 7
+							end
+							device pnp 2e.2 on #  Com1
+								io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.3 off #  Com2
+								io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.5 on #  Keyboard
+								io 0x60 = 0x60
+								io 0x62 = 0x64
+								irq 0x70 = 1
+								irq 0x72 = 12
+							end
+							device pnp 2e.6 off #  CIR
+								io 0x60 = 0x100
+							end
+							device pnp 2e.7 off #  GAME_MIDI_GIPO1
+								io 0x60 = 0x220
+								io 0x62 = 0x300
+								irq 0x70 = 9
+							end
+							device pnp 2e.8 off end #  GPIO2
+							device pnp 2e.9 off end #  GPIO3
+							device pnp 2e.a off end #  ACPI
+							device pnp 2e.b on #  HW Monitor
+								io 0x60 = 0x290
+								irq 0x70 = 5
+							end
+						end
+					end
+					device pci 1.1 on end
+					device pci 1.2 on end
+					device pci 1.3 on
+						chip drivers/i2c/i2cmux2 # pca9556 smbus mux
+						chip drivers/i2c/i2cmux2 # pca9556 smbus mux
+							device i2c 18 on #0 pca9516 1
+								chip drivers/generic/generic #dimm 0-0-0
+									device i2c 50 on end
+								end
+								chip drivers/generic/generic #dimm 0-0-1
+									device i2c 51 on end
+								end
+								chip drivers/generic/generic #dimm 0-1-0
+									device i2c 52 on end
+								end
+								chip drivers/generic/generic #dimm 0-1-1
+									device i2c 53 on end
+								end
+							end
+							device i2c 18 on #1 pca9516 2
+								chip drivers/generic/generic #dimm 1-0-0
+									device i2c 50 on end
+								end
+								chip drivers/generic/generic #dimm 1-0-1
+									device i2c 51 on end
+								end
+								chip drivers/generic/generic #dimm 1-1-0
+									device i2c 52 on end
+								end
+								chip drivers/generic/generic #dimm 1-1-1
+									device i2c 53 on end
+								end
+							end
+						end
+						end
+					end # acpi
+					device pci 1.5 off end
+					device pci 1.6 off end
+					register "ide0_enable" = "1"
+					register "ide1_enable" = "1"
+				end
+			end #  device pci 18.0
+
+			device pci 18.0 on end
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+			device pci 18.4 on end
+#			device pci 00.5 on end
+		end
+	end #pci_domain
+	#for node 32 to node 63
+#	device pci_domain 0 on
+#		chip northbridge/amd/amdfam10
+#			  device pci 00.0 on end#  northbridge
+#			  device pci 00.0 on end
+#			  device pci 00.0 on end
+#			  device pci 00.0 on end
+#			  device pci 00.1 on end
+#			  device pci 00.2 on end
+#			  device pci 00.3 on end
+#			  device pci 00.4 on end
+#			 device pci 00.5 on end
+#		end
+#	end #pci_domain
+
+#	  chip drivers/generic/debug
+#		 device pnp 0.0 off end # chip name
+#		  device pnp 0.1 on end # pci_regs_all
+#		  device pnp 0.2 off end # mem
+#		  device pnp 0.3 off end # cpuid
+#		  device pnp 0.4 off end # smbus_regs_all
+#		  device pnp 0.5 off end # dual core msr
+#		  device pnp 0.6 off end # cache size
+#		  device pnp 0.7 off end # tsc
+#		  device pnp 0.8 off end # hard reset
+#		  device pnp 0.9 off end # mcp55
+#		  device pnp 0.a on end # GH ext table
+#	 end
+
+end
+
+

src/mainboard/arima/Kconfig

@@ -0,0 +1 @@
+#

src/mainboard/arima/hdama/devicetree.cb

@@ -0,0 +1,196 @@
+chip northbridge/amd/amdk8/root_complex
+	device apic_cluster 0 on
+		chip cpu/amd/socket_940
+			device apic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on #  northbridge 
+				#  devices on link 0, link 0 == LDT 0 
+				chip southbridge/amd/amd8131
+					# the on/off keyword is mandatory
+					device pci 0.0 on	# PCIX bridge
+						## On board NIC A
+						#chip drivers/generic/generic
+						#	device pci 3.0 on	
+						#		irq 0 = 0x13
+						#	end
+						#end
+						## On board NIC B
+						#chip drivers/generic/generic
+						#	device pci 4.0 on
+						#		irq 0 = 0x13
+						#	end
+						#end
+						## PCI Slot 3
+						#chip drivers/generic/generic
+						#	device pci 1.0 on
+						#		irq 0 = 0x11
+						#		irq 1 = 0x12
+						#		irq 2 = 0x13
+						#		irq 3 = 0x10
+						#	end
+						#end 
+						## PCI Slot 4
+						#chip drivers/generic/generic
+						#	device pci 2.0 on
+						#		irq 0 = 0x12
+						#		irq 1 = 0x13
+						#		irq 2 = 0x10
+						#		irq 3 = 0x11
+						#	end
+						#end 
+					end
+					device pci 0.1 on end	# IOAPIC
+					device pci 1.0 on 	# PCIX bridge
+						## PCI Slot 1
+						#chip drivers/generic/generic
+						#	device pci 1.0 on
+						#		irq 0 = 0x11
+						#		irq 1 = 0x12
+						#		irq 2 = 0x13
+						#		irq 3 = 0x10
+						#	end
+						#end
+						## PCI Slot 2
+						#chip drivers/generic/generic
+						#	device pci 2.0 on
+						#		irq 0 = 0x12
+						#		irq 1 = 0x13
+						#		irq 2 = 0x10
+						#		irq 3 = 0x11
+						#	end
+						#end 
+					end
+					device pci 1.1 on end	# IOAPIC
+				end
+				chip southbridge/amd/amd8111
+					# this "device pci 0.0" is the parent of the next one
+					# PCI bridge
+					device pci 0.0 on
+						device pci 0.0 on  end	# USB0
+						device pci 0.1 on  end	# USB1
+						device pci 0.2 off end	# USB 2.0
+						device pci 1.0 off end	# LAN
+						chip drivers/pci/onboard
+							device pci 6.0 on end # ATI Rage XL
+							register "rom_address" = "0xfff80000"
+						end
+						## PCI Slot 5 (correct?)
+						#chip drivers/generic/generic
+						#	device pci 5.0 on
+						#		irq 0 = 0x11
+						#		irq 1 = 0x12
+						#		irq 2 = 0x13
+						#		irq 3 = 0x10
+						#	end
+						#end 
+						## PCI Slot 6 (correct?)
+						#chip drivers/generic/generic
+						#	device pci 4.0 on
+						#		irq 0 = 0x10
+						#		irq 1 = 0x11
+						#		irq 2 = 0x12
+						#		irq 3 = 0x13
+						#	end
+						#end 
+
+					end
+					# LPC bridge
+					device pci 1.0 on
+						chip superio/nsc/pc87360
+							device	pnp 2e.0 off  # Floppy 
+								 io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp 2e.1 off  # Parallel Port
+								 io 0x60 = 0x378
+								irq 0x70 = 7
+							end
+							device pnp 2e.2 off # Com 2
+								 io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.3 on  # Com 1
+								 io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.4 off end # SWC
+							device pnp 2e.5 off end # Mouse
+							device pnp 2e.6 on  # Keyboard
+								 io 0x60 = 0x60
+								 io 0x62 = 0x64
+								irq 0x70 = 1
+							end
+							device pnp 2e.7 off end # GPIO
+							device pnp 2e.8 off end # ACB
+							device pnp 2e.9 off end # FSCM
+							device pnp 2e.a off end # WDT  
+						end
+					end
+					device pci 1.1 on end	# IDE
+					device pci 1.2 on end	# SMBus 2.0
+					device pci 1.3 on 	# System Management
+						chip drivers/generic/generic
+							#phillips pca9545 smbus mux
+							device i2c 70 on 
+								# analog_devices adm1026	
+								chip drivers/generic/generic
+									device i2c 2c on end
+								end
+							end
+							device i2c 70 on end
+							device i2c 70 on end
+							device i2c 70 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 on end
+						end 
+						chip drivers/generic/generic #dimm 0-1-0
+							device i2c 52 on end
+						end 
+						chip drivers/generic/generic #dimm 0-1-1
+							device i2c 53 on end
+						end 
+						chip drivers/generic/generic #dimm 1-0-0
+							device i2c 54 on end 
+						end
+						chip drivers/generic/generic #dimm 1-0-1
+							device i2c 55 on end
+						end 
+						chip drivers/generic/generic #dimm 1-1-0
+							device i2c 56 on end
+						end 
+						chip drivers/generic/generic #dimm 1-1-1
+							device i2c 57 on end
+						end 
+					end
+					device pci 1.5 off end	# AC97 Audio
+					device pci 1.6 on  end	# AC97 Modem
+					register "ide0_enable" = "1"
+					register "ide1_enable" = "1"
+				end
+			end #  device pci 18.0 
+			
+			device pci 18.0 on end # LDT1
+			device pci 18.0 on end # LDT2
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end  # chip northbridge/amd/amdk8
+		chip northbridge/amd/amdk8
+			device pci 19.0 on end
+			device pci 19.0 on end
+			device pci 19.0 on end
+			device pci 19.1 on end
+			device pci 19.2 on end
+			device pci 19.3 on end
+		end
+	end 
+end
+

src/mainboard/artecgroup/Kconfig

@@ -0,0 +1 @@
+#

src/mainboard/artecgroup/dbe61/devicetree.cb

@@ -0,0 +1,42 @@
+chip northbridge/amd/lx
+	device pci_domain 0 on
+		device pci 1.0 on end	# Northbridge
+		device pci 1.1 on end	# Graphics
+		chip southbridge/amd/cs5536
+			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
+			# SIRQ Mode = Active(Quiet) mode. Save power....
+			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
+			register "lpc_serirq_enable" = "0x00001002"
+			register "lpc_serirq_polarity" = "0x0000EFFD"
+			register "lpc_serirq_mode" = "1"
+			register "enable_gpio_int_route" = "0x0D0C0700"
+			register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+			register "enable_USBP4_device" = "0"	#0: host, 1:device
+			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+			register "com1_enable" = "0"
+			register "com1_address" = "0x2F8"
+			register "com1_irq" = "3"
+			register "com2_enable" = "1"
+			register "com2_address" = "0x3F8"
+			register "com2_irq" = "4"
+			register "unwanted_vpci[0]" = "0"	# End of list has a zero
+			device pci b.0 on end	# Slot 3
+			device pci c.0 on end	# Slot 4
+			device pci d.0 on end	# Slot 1
+			device pci e.0 on end	# Slot 2
+			device pci f.0 on end	# ISA Bridge
+			device pci f.2 on end	# IDE Controller
+			device pci f.3 on end	# Audio
+			device pci f.4 on end	# OHCI
+			device pci f.5 on end	# EHCI
+		end
+	end
+	# APIC cluster is late CPU init.
+	device apic_cluster 0 on
+		chip cpu/amd/model_lx
+			device apic 0 on end
+		end
+	end
+
+end
+

src/mainboard/asi/Kconfig

@@ -0,0 +1 @@
+#

src/mainboard/asi/mb_5blgp/devicetree.cb

@@ -0,0 +1,55 @@
+chip northbridge/amd/gx1		# Northbridge
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    chip southbridge/amd/cs5530		# Southbridge
+      device pci 0f.0 on end		# Ethernet
+      device pci 12.0 on		# ISA bridge
+        chip superio/nsc/pc87351	# Super I/O
+          device pnp 2e.0 off		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 2e.2 on		# COM2
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.e on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.4 on		# System wake-up control (SWC)
+            irq 0x60 = 0x500
+          end
+          device pnp 2e.5 on		# PS/2 mouse
+            irq 0x70 = 12
+          end
+          device pnp 2e.6 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1
+          end
+          device pnp 2e.7 on		# GPIO
+            irq 0x60 = 0x800
+          end
+          device pnp 2e.8 on		# Fan speed control
+            irq 0x60 = 0x900
+          end
+        end
+      end
+      device pci 12.1 off end		# SMI
+      device pci 12.2 on end		# IDE
+      device pci 12.3 on end		# Audio
+      device pci 12.4 on end		# VGA
+      device pci 13.0 on end		# USB
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "0"	# No connector on this board
+    end
+  end
+  chip cpu/amd/model_gx1		# CPU
+  end
+end

src/mainboard/asi/mb_5blmp/devicetree.cb

@@ -0,0 +1,56 @@
+chip northbridge/amd/gx1		# Northbridge
+  device pci_domain 0 on
+    device pci 0.0 on end		# Host bridge
+    chip southbridge/amd/cs5530		# Southbridge
+      device pci 0f.0 off end		# Ethernet (Realtek RTL8139B)
+      device pci 12.0 on		# ISA bridge
+        chip superio/nsc/pc87351	# Super I/O
+          device pnp 2e.4 on		# PS/2 keyboard (+ mouse?)
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1
+            # irq 0x72 = 12
+          end
+          device pnp 2e.a on		# PS/2 mouse
+            irq 0x70 = 12
+          end
+          device pnp 2e.e on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.f off		# Floppy
+            io 0x60 = 0x3f2
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.10 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 2e.12 on		# COM2
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+        end
+      end
+      device pci 12.1 off end		# SMI
+      device pci 12.2 on  end		# IDE
+      device pci 12.3 on  end		# Audio
+      device pci 12.4 on  end		# VGA (onboard)
+      # device pci 12.4 on		# VGA (onboard)
+      #   chip drivers/pci/onboard
+      #     device pci 12.4 on end
+      #     register "rom_address" = "0xfffc0000" # 256 KB image
+      #     # register "rom_address" = "0xfff80000" # 512 KB image
+      #     # register "rom_address" = "0xfff00000" # 1 MB image
+      #   end
+      # end
+      device pci 13.0 on end		# USB
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+    end
+  end
+  chip cpu/amd/model_gx1		# CPU
+  end
+end
+

src/mainboard/asus/Kconfig

@@ -0,0 +1 @@
+#

src/mainboard/asus/a8n_e/devicetree.cb

@@ -0,0 +1,130 @@
+chip northbridge/amd/amdk8/root_complex		# Root complex
+  device apic_cluster 0 on			# APIC cluster
+    chip cpu/amd/socket_939			# Socket 939 CPU
+      device apic 0 on end			# APIC
+    end
+  end
+
+  device pci_domain 0 on			# PCI domain
+    chip northbridge/amd/amdk8			# mc0
+      device pci 18.0 on			# Northbridge
+        # Devices on link 0, link 0 == LDT 0
+        chip southbridge/nvidia/ck804		# Southbridge
+          device pci 0.0 on end			# HT
+          device pci 1.0 on			# LPC
+            chip superio/ite/it8712f		# Super I/O
+              device pnp 2e.0 on		# Floppy
+                io 0x60 = 0x3f0
+                irq 0x70 = 6
+                drq 0x74 = 2
+              end
+              device pnp 2e.1 on		# Com1
+                io 0x60 = 0x3f8
+                irq 0x70 = 4
+              end
+              device pnp 2e.2 off		# Com2 (N/A on this board)
+                io 0x60 = 0x2f8
+                irq 0x70 = 3
+              end
+              device pnp 2e.3 on		# Parallel port
+                io 0x60 = 0x378
+                irq 0x70 = 7
+                drq 0x74 = 3
+              end
+              device pnp 2e.4 on		# Environment controller
+                io 0x60 = 0x290
+                io 0x62 = 0x0000
+                irq 0x70 = 0x00
+              end
+              device pnp 2e.5 on		# PS/2 keyboard
+                io 0x60 = 0x60
+                io 0x62 = 0x64
+                irq 0x70 = 1
+                irq 0x71 = 2
+              end
+              device pnp 2e.6 on		# PS/2 mouse
+                irq 0x70 = 12
+                irq 0x71 = 2
+              end
+              device pnp 2e.7 on		# GPIO config
+                io 0x60 = 0x0800
+                # Set GPIO 1 & 2
+                io 0x25 = 0x0000
+                # Set GPIO 3 & 4
+                io 0x27 = 0x2540
+                # GPIO Polarity for Set 3
+                io 0xb2 = 0x2100
+                # GPIO Pin Internal Pull up for Set 3
+                io 0xba = 0x0100
+                # Simple I/O register config
+                io 0xc0 = 0x0000
+                io 0xc2 = 0x2540
+                io 0xc8 = 0x0000
+                io 0xca = 0x0500
+              end
+              device pnp 2e.8 on		# Midi port
+                io 0x60 = 0x300
+                irq 0x70 = 10
+              end
+              device pnp 2e.9 on		# Game port
+                io 0x60 = 0x201
+              end
+              device pnp 2e.a off		# IR (N/A on this board)
+                io 0x60 = 0x310
+                irq 0x70 = 11
+              end
+            end
+          end
+          device pci 1.1 on			# SM 0
+            # chip drivers/generic/generic #dimm 0-0-0
+            #   device i2c 50 on end
+            # end
+            # chip drivers/generic/generic #dimm 0-0-1
+            #   device i2c 51 on end
+            # end
+            # chip drivers/generic/generic #dimm 0-1-0
+            #   device i2c 52 on end
+            # end
+            # chip drivers/generic/generic #dimm 0-1-1
+            #   device i2c 53 on end
+            # end
+            # chip drivers/generic/generic #dimm 1-0-0
+            #   device i2c 54 on end
+            # end
+            # chip drivers/generic/generic #dimm 1-0-1
+            #   device i2c 55 on end
+            # end
+            # chip drivers/generic/generic #dimm 1-1-0
+            #   device i2c 56 on end
+            # end
+            # chip drivers/generic/generic #dimm 1-1-1
+            #   device i2c 57 on end
+            # end
+          end
+          device pci 2.0 on end			# USB 1.1
+          device pci 2.1 on end			# USB 2
+          device pci 4.0 on end			# Onboard audio (ACI)
+          device pci 4.1 off end		# Onboard modem (MCI), N/A
+          device pci 6.0 on end			# IDE
+          device pci 7.0 on end			# SATA 1
+          device pci 8.0 on end			# SATA 0
+          device pci 9.0 on end			# PCI
+          device pci a.0 on end			# NIC
+          device pci b.0 on end			# PCI E 3
+          device pci c.0 on end			# PCI E 2
+          device pci d.0 on end			# PCI E 1
+          device pci e.0 on end			# PCI E 0
+          register "ide0_enable" = "1"
+          register "ide1_enable" = "1"
+          register "sata0_enable" = "1"
+          register "sata1_enable" = "1"
+          # register "mac_eeprom_smbus" = "3"
+          # register "mac_eeprom_addr" = "0x51"
+        end
+      end
+      device pci 18.1 on end
+      device pci 18.2 on end
+      device pci 18.3 on end
+    end
+  end
+end

src/mainboard/asus/a8v-e_se/devicetree.cb

@@ -0,0 +1,96 @@
+chip northbridge/amd/amdk8/root_complex		# Root complex
+  device apic_cluster 0 on			# APIC cluster
+    chip cpu/amd/socket_939			# CPU
+      device apic 0 on end			# APIC
+    end
+  end
+  device pci_domain 0 on			# PCI domain
+    chip northbridge/amd/amdk8			# mc0
+      device pci 18.0 on			# Northbridge
+        # Devices on link 0, link 0 == LDT 0
+        chip southbridge/via/vt8237r		# Southbridge
+          register "ide0_enable" = "1"		# Enable IDE channel 0
+          register "ide1_enable" = "1"		# Enable IDE channel 1
+          register "ide0_80pin_cable" = "1"	# 80pin cable on IDE channel 0
+          register "ide1_80pin_cable" = "1"	# 80pin cable on IDE channel 1
+          register "fn_ctrl_lo" = "0"		# Enable SB functions
+          register "fn_ctrl_hi" = "0xad"	# Enable SB functions
+          device pci 0.0 on end			# HT
+          device pci f.1 on end			# IDE
+          device pci 11.0 on			# LPC
+            chip drivers/generic/generic	# DIMM 0-0-0
+              device i2c 50 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-0-1
+              device i2c 51 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-1-0
+              device i2c 52 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-1-1
+              device i2c 53 on end
+            end
+            chip superio/winbond/w83627ehg	# Super I/O
+              device pnp 2e.0 on		# Floppy
+                io 0x60 = 0x3f0
+                irq 0x70 = 6
+                drq 0x74 = 2
+              end
+              device pnp 2e.1 on		# Parallel port
+                io 0x60 = 0x378
+                irq 0x70 = 7
+                drq 0x74 = 3
+              end
+              device pnp 2e.2 on		# Com1
+                io 0x60 = 0x3f8
+                irq 0x70 = 4
+              end
+              device pnp 2e.3 off		# Com2 (N/A on this board)
+                io 0x60 = 0x2f8
+                irq 0x70 = 3
+              end
+              device pnp 2e.5 off		# PS/2 keyboard (off)
+              end
+              device pnp 2e.106 off		# Serial flash
+                io 0x60 = 0x100
+              end
+              device pnp 2e.007 off		# GPIO 1
+              end
+              device pnp 2e.107 on		# Game port
+                io 0x60 = 0x201
+              end
+              device pnp 2e.207 on		# MIDI
+                io 0x62 = 0x330
+                irq 0x70 = 0xa
+              end
+              device pnp 2e.307 off		# GPIO 6
+              end
+              device pnp 2e.8 off		# WDTO_PLED
+              end
+              device pnp 2e.009 on		# GPIO 2 on LDN 9 is in sio_setup
+              end
+              device pnp 2e.109 off		# GPIO 3
+              end
+              device pnp 2e.209 off		# GPIO 4
+              end
+              device pnp 2e.309 on		# GPIO5
+              end
+              device pnp 2e.a off		# ACPI
+              end
+              device pnp 2e.b on		# Hardware monitor
+                io 0x60 = 0x290
+                irq 0x70 = 0
+              end
+            end
+          end
+          device pci 12.0 off end		# VIA LAN (off, other chip used)
+        end
+        chip southbridge/via/k8t890		# "Southbridge" K8T890
+        end
+      end
+      device pci 18.1 on end
+      device pci 18.2 on end
+      device pci 18.3 on end
+    end
+  end
+end

src/mainboard/asus/m2v-mx_se/devicetree.cb

@@ -0,0 +1,76 @@
+chip northbridge/amd/amdk8/root_complex		# Root complex
+  device apic_cluster 0 on			# APIC cluster
+    chip cpu/amd/socket_AM2			# CPU
+      device apic 0 on end			# APIC
+    end
+  end
+  device pci_domain 0 on			# PCI domain
+    chip northbridge/amd/amdk8			# mc0
+      device pci 18.0 on			# Northbridge
+        # Devices on link 0, link 0 == LDT 0
+        chip southbridge/via/vt8237r		# Southbridge
+          register "ide0_enable" = "1"		# Enable IDE channel 0
+          register "ide1_enable" = "1"		# Enable IDE channel 1
+          register "ide0_80pin_cable" = "1"	# 80pin cable on IDE channel 0
+          register "ide1_80pin_cable" = "1"	# 80pin cable on IDE channel 1
+          register "fn_ctrl_lo" = "0xc0"	# Enable SB functions
+          register "fn_ctrl_hi" = "0x1d"	# Enable SB functions
+          device pci 0.0 on end			# HT
+          device pci f.1 on end			# IDE
+          device pci 11.0 on			# LPC
+            chip drivers/generic/generic	# DIMM 0-0-0
+              device i2c 50 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-0-1
+              device i2c 51 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-1-0
+              device i2c 52 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-1-1
+              device i2c 53 on end
+            end
+            chip superio/ite/it8712f		# Super I/O
+              device pnp 2e.0 on		# Floppy
+                io 0x60 = 0x3f0
+                irq 0x70 = 6
+                drq 0x74 = 2
+              end
+              device pnp 2e.1 on		# Com1
+                io 0x60 = 0x3f8
+                irq 0x70 = 4
+              end
+              device pnp 2e.2 off		# Com2
+                io 0x60 = 0x2f8
+                irq 0x70 = 3
+              end
+              device pnp 2e.3 on		# Parallel port
+                io 0x60 = 0x378
+                irq 0x70 = 7
+              end
+              device pnp 2e.4 on		# Environment controller
+                io 0x60 = 0x290
+                io 0x62 = 0x230
+                irq 0x70 = 0x00
+              end
+              device pnp 2e.5 off end		# PS/2 keyboard
+              device pnp 2e.6 off end		# PS/2 mouse
+              device pnp 2e.7 off end		# GPIO config
+              device pnp 2e.8 off end		# Midi port
+              device pnp 2e.9 off end		# Game port
+              device pnp 2e.a off end		# IR
+	     end
+	   end
+          device pci 12.0 on end		# VIA LAN
+          device pci 13.0 on end		# br
+          device pci 13.1 on end		# br2 need to have it here to discover it
+        end
+        chip southbridge/via/k8t890		# "Southbridge" K8M890
+        end
+      end
+      device pci 18.1 on end
+      device pci 18.2 on end
+      device pci 18.3 on end
+    end
+  end
+end

src/mainboard/asus/mew-am/devicetree.cb

@@ -0,0 +1,60 @@
+chip northbridge/intel/i82810		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/socket_PGA370	# CPU
+      device apic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Graphics Memory Controller Hub (GMCH)
+    device pci 1.0 on end		# Chipset Graphics Controller (CGC)
+    chip southbridge/intel/i82801xx	# Southbridge
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+
+      device pci 1e.0 on end		# PCI bridge
+      device pci 1f.0 on		# ISA bridge
+        chip superio/smsc/smscsuperio	# Super I/O
+          device pnp 2e.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.3 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+            drq 0x74 = 4
+          end
+          device pnp 2e.4 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.5 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.7 on		# PS/2 keyboard / mouse
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 2e.9 on		# Game port
+            io 0x60 = 0x201
+          end
+          device pnp 2e.a on		# Power-management events (PME)
+            io 0x60 = 0x600
+          end
+          device pnp 2e.b on		# MIDI port (MPU-401)
+            io 0x60 = 0x330
+            irq 0x70 = 5
+          end
+        end
+      end
+      device pci 1f.1 on end		# IDE
+      device pci 1f.2 on end		# USB
+      device pci 1f.3 on end		# SMbus
+      device pci 1f.5 off end		# AC'97 audio (N/A, uses CS4280 chip)
+      device pci 1f.6 off end		# AC'97 modem (N/A)
+    end
+  end
+end

src/mainboard/asus/mew-vm/devicetree.cb

@@ -0,0 +1,58 @@
+chip northbridge/intel/i82810
+	device pci_domain 0 on 
+		device pci 0.0 on end # Host bridge
+		device pci 1.0 on # Onboard Video
+			#chip drivers/pci/onboard
+			#	device pci 1.0 on end
+			#	register "rom_address" = "0xfff80000"
+		        #end
+		end
+		chip southbridge/intel/i82801xx # Southbridge
+      			register "ide0_enable" = "1"
+      			register "ide1_enable" = "1"
+
+			device pci 1e.0 on # PCI Bridge
+				#chip drivers/pci/onboard
+				#	device pci 1.0 on end
+				#	register "rom_address" = "0xfff80000"
+			        #end
+			end
+			device pci 1f.0 on  # ISA/LPC? Bridge
+				chip superio/smsc/lpc47b272
+					device pnp 2e.0 off # Floppy
+						io 0x60 = 0x3f0
+						irq 0x70 = 6
+						drq 0x74 = 2
+					end
+					device pnp 2e.3 off # Parallel Port
+						io 0x60 = 0x378
+						irq 0x70 = 7
+					end
+					device pnp 2e.4 on # Com1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.5 off # Com2
+						io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 2e.7 on # Keyboard
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1 # Keyboard interrupt
+						irq 0x72 = 12 # Mouse interrupt
+					end
+					device pnp 2e.a off end # ACPI
+				end
+			end
+			device pci 1f.1 on end # IDE
+			device pci 1f.2 on end # USB
+			device pci 1f.3 on end # SMBus
+			device pci 1f.5 off end # AC'97, no header on MEW-VM
+			device pci 1f.6 off end # AC'97 Modem (MC'97)
+		end
+	end
+	chip cpu/intel/socket_PGA370
+	end
+end
+

src/mainboard/asus/p2b-d/devicetree.cb

@@ -0,0 +1,62 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 1 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 4.0 on			# ISA bridge
+        chip superio/winbond/w83977tf	# Super I/O
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 3f0.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.3 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard / mouse
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.7 on		# GPIO 1
+          end
+          device pnp 3f0.8 on		# GPIO 2
+          end
+          device pnp 3f0.9 on		# GPIO 3
+          end
+          device pnp 3f0.a on		# ACPI
+          end
+        end
+      end
+      device pci 4.1 on	end		# IDE
+      device pci 4.2 on	end		# USB
+      device pci 4.3 on end		# ACPI
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "1"
+      register "ide0_drive1_udma33_enable" = "1"
+      register "ide1_drive0_udma33_enable" = "1"
+      register "ide1_drive1_udma33_enable" = "1"
+    end
+  end
+end

src/mainboard/asus/p2b-ds/devicetree.cb

@@ -0,0 +1,63 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 1 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 4.0 on			# ISA bridge
+        chip superio/winbond/w83977tf	# Super I/O
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 3f0.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.3 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard / mouse
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.7 on		# GPIO 1
+          end
+          device pnp 3f0.8 on		# GPIO 2
+          end
+          device pnp 3f0.9 on		# GPIO 3
+          end
+          device pnp 3f0.a on		# ACPI
+          end
+        end
+      end
+      device pci 4.1 on	end		# IDE
+      device pci 4.2 on	end		# USB
+      device pci 4.3 on end		# ACPI
+      device pci 6.0 on end		# Onboard SCSI
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "1"
+      register "ide0_drive1_udma33_enable" = "1"
+      register "ide1_drive0_udma33_enable" = "1"
+      register "ide1_drive1_udma33_enable" = "1"
+    end
+  end
+end

src/mainboard/asus/p2b-f/devicetree.cb

@@ -0,0 +1,59 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 4.0 on			# ISA bridge
+        chip superio/winbond/w83977tf	# Super I/O (FIXME: It's W83977EF!)
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 3f0.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.3 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.6 on		# Consumer IR
+          end
+          device pnp 3f0.7 on		# GPIO 1
+          end
+          device pnp 3f0.8 on		# GPIO 2
+          end
+          device pnp 3f0.a on		# ACPI
+          end
+        end
+      end
+      device pci 4.1 on	end		# IDE
+      device pci 4.2 on	end		# USB
+      device pci 4.3 on end		# ACPI
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "0"
+      register "ide0_drive1_udma33_enable" = "0"
+      register "ide1_drive0_udma33_enable" = "0"
+      register "ide1_drive1_udma33_enable" = "0"
+    end
+  end
+end

src/mainboard/asus/p2b/devicetree.cb

@@ -0,0 +1,59 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 4.0 on			# ISA bridge
+        chip superio/winbond/w83977tf	# Super I/O
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 3f0.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.3 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard / mouse
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.7 on		# GPIO 1
+          end
+          device pnp 3f0.8 on		# GPIO 2
+          end
+          device pnp 3f0.9 on		# GPIO 3
+          end
+          device pnp 3f0.a on		# ACPI
+          end
+        end
+      end
+      device pci 4.1 on	end		# IDE
+      device pci 4.2 on	end		# USB
+      device pci 4.3 on end		# ACPI
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "0"
+      register "ide0_drive1_udma33_enable" = "0"
+      register "ide1_drive0_udma33_enable" = "0"
+      register "ide1_drive1_udma33_enable" = "0"
+    end
+  end
+end

src/mainboard/asus/p3b-f/devicetree.cb

@@ -0,0 +1,59 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 4.0 on			# ISA bridge
+        chip superio/winbond/w83977tf	# Super I/O (FIXME: It's W83977EF!)
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 3f0.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.3 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.6 on		# Consumer IR
+          end
+          device pnp 3f0.7 on		# GPIO 1
+          end
+          device pnp 3f0.8 on		# GPIO 2
+          end
+          device pnp 3f0.a on		# ACPI
+          end
+        end
+      end
+      device pci 4.1 on	end		# IDE
+      device pci 4.2 on	end		# USB
+      device pci 4.3 on end		# ACPI
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "0"
+      register "ide0_drive1_udma33_enable" = "0"
+      register "ide1_drive0_udma33_enable" = "0"
+      register "ide1_drive1_udma33_enable" = "0"
+    end
+  end
+end

src/mainboard/axus/Kconfig

@@ -0,0 +1 @@
+#

src/mainboard/axus/tc320/devicetree.cb

@@ -0,0 +1,55 @@
+chip northbridge/amd/gx1		# Northbridge
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    chip southbridge/amd/cs5530		# Southbridge
+      device pci 12.0 on		# ISA bridge
+        chip superio/nsc/pc97317	# Super I/O
+          device pnp 2e.0 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1
+          end
+          device pnp 2e.1 on		# PS/2 mouse
+            irq 0x70 = 12
+          end
+          device pnp 2e.2 on		# RTC, advanced power control (APC)
+            io 0x60 = 0x70
+            irq 0x70 = 8
+          end
+          device pnp 2e.3 off		# Floppy (N/A on this board)
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.4 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 2e.5 off		# COM2
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.6 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.7 on		# GPIO
+            io 0x60 = 0xe0
+          end
+          device pnp 2e.8 on		# Power management
+            io 0x60 = 0xe800
+          end
+        end
+      end
+      device pci 12.1 off end		# SMI
+      device pci 12.2 off end		# IDE
+      device pci 12.3 on end		# Audio
+      device pci 12.4 on end		# VGA (onboard)
+      device pci 13.0 on end		# USB
+      # register "ide0_enable" = "1"
+      # register "ide1_enable" = "1"
+    end
+  end
+  chip cpu/amd/model_gx1		# CPU
+  end
+end

src/mainboard/azza/Kconfig

@@ -0,0 +1 @@
+#

src/mainboard/azza/pt-6ibd/devicetree.cb

@@ -0,0 +1,59 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 7.0 on			# ISA bridge
+        chip superio/winbond/w83977tf	# Super I/O (FIXME: It's W83977EF!)
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 3f0.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.3 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard / mouse
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.6 on		# Consumer IR
+          end
+          device pnp 3f0.7 on		# GPIO 1
+          end
+          device pnp 3f0.8 on		# GPIO 2
+          end
+          device pnp 3f0.a on		# ACPI
+          end
+        end
+      end
+      device pci 7.1 on	end		# IDE
+      device pci 7.2 on	end		# USB
+      device pci 7.3 on end		# ACPI
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "0"
+      register "ide0_drive1_udma33_enable" = "0"
+      register "ide1_drive0_udma33_enable" = "0"
+      register "ide1_drive1_udma33_enable" = "0"
+    end
+  end
+end

src/mainboard/bcom/Kconfig

@@ -0,0 +1 @@
+#

src/mainboard/bcom/winnet100/devicetree.cb

@@ -0,0 +1,56 @@
+chip northbridge/amd/gx1		# Northbridge
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    chip southbridge/amd/cs5530		# Southbridge
+      device pci 0f.0 on end		# Ethernet (onboard)
+      device pci 12.0 on		# ISA bridge
+        chip superio/nsc/pc97317	# Super I/O
+          device pnp 2e.0 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1
+          end
+          device pnp 2e.1 on		# PS/2 mouse
+            irq 0x70 = 12
+          end
+          device pnp 2e.2 on		# RTC, Advanced power control (APC)
+            io 0x60 = 0x70
+            irq 0x70 = 8
+          end
+          device pnp 2e.3 off		# Floppy (N/A on this board)
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.4 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 2e.5 on		# COM2 (used for smartcard reader)
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.6 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.7 on		# GPIO
+            io 0x60 = 0xe0
+          end
+          device pnp 2e.8 on		# Power management
+            io 0x60 = 0xe8
+          end
+        end
+      end
+      device pci 12.1 off end		# SMI
+      device pci 12.2 on end		# IDE
+      device pci 12.3 on end		# Audio
+      device pci 12.4 on end		# VGA (onboard)
+      device pci 13.0 on end		# USB
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "0"	# Not available/needed on this board
+    end
+  end
+  chip cpu/amd/model_gx1		# CPU
+  end
+end