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baytrail: Enable Turbo/Burst and set some magic MSRs

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As far as I can tell turbo enabling behaves like
it did on haswell so use the standard code.

There are also some magic values to set in some magic
MSRs related to turbo and package power so they report
correctly.

The L2 cache shrink is enabled and a threshold is set
that makes both dual and quad core happy.

C1E is disabled to match the reference code.

BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi

Change-Id: Ic6d4283d480a44d85a9b96571baf83928615665c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175743
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4952
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Duncan Laurie
2013-11-05 12:59:50 -08:00
committed by Kyösti Mälkki
parent fd461e396b
commit 05a3393a2c
3 changed files with 44 additions and 0 deletions
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1
src/soc/intel/baytrail/Makefile.inc
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@@ -6,6 +6,7 @@ subdirs-y += ../../../cpu/x86/mtrr
subdirs-y += ../../../cpu/x86/smm
subdirs-y += ../../../cpu/x86/tsc
subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo
ramstage-y += memmap.c
romstage-y += memmap.c