sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Replace cache control magic numbers with symbols

Browse Source 
Instead of opaque numbers like (1<<29), use
symbols like CR0_NoWriteThrough.

Change-Id: Id845e087fb472cfaf5f71beaf37fbf0d407880b5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/833
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Patrick Georgi
2012-03-31 12:52:21 +02:00
committed by Stefan Reinauer
parent 8919729307
commit 05e740fc40
11 changed files with 63 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
src/cpu/intel/model_106cx/cache_as_ram.inc
View File

@ -20,6 +20,7 @@
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
#define CPU_MAXPHYADDR 32
@ -84,7 +85,7 @@ clear_mtrrs:
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
movl %cr0, %eax
andl $(~((1 << 30) | (1 << 29))), %eax
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
invd
movl %eax, %cr0
@ -98,7 +99,7 @@ clear_mtrrs:
/* Enable Cache-as-RAM mode by disabling cache. */
movl %cr0, %eax
orl $(1 << 30), %eax
orl $CR0_CacheDisable, %eax
movl %eax, %cr0
#if CONFIG_XIP_ROM_SIZE
@ -122,7 +123,7 @@ clear_mtrrs:
/* Enable cache. */
movl %cr0, %eax
andl $(~((1 << 30) | (1 << 29))), %eax
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
movl %eax, %cr0
/* Set up the stack pointer. */
@ -150,7 +151,7 @@ clear_mtrrs:
/* Disable cache. */
movl %cr0, %eax
orl $(1 << 30), %eax
orl $CR0_CacheDisable, %eax
movl %eax, %cr0
post_code(0x31)
@ -181,14 +182,14 @@ clear_mtrrs:
/* Enable cache. */
movl %cr0, %eax
andl $~((1 << 30) | (1 << 29)), %eax
andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
movl %eax, %cr0
post_code(0x36)
/* Disable cache. */
movl %cr0, %eax
orl $(1 << 30), %eax
orl $CR0_CacheDisable, %eax
movl %eax, %cr0
post_code(0x38)
@ -207,7 +208,7 @@ clear_mtrrs:
/* And enable cache again after setting MTRRs. */
movl %cr0, %eax
andl $~((1 << 30) | (1 << 29)), %eax
andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
movl %eax, %cr0
post_code(0x3a)