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soc/intel/cannonlake: Add RP configuration settings

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Add RP configuration settings like Advanced Error Reporting(AER),
Latency Tolerence Reporting (LTR), Max Payload and Active State Power
Management (ASPM).

Tested on CFL platform

Change-Id: Ifaf0cc86ea412ce246723613f99908946d89ccb0
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41679
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Christian Walter
2020-05-23 15:54:43 +02:00
committed by Patrick Rudolph
parent 1f572b9276
commit 061cd78a1a
2 changed files with 36 additions and 1 deletions
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23
src/soc/intel/cannonlake/chip.h
View File

@@ -181,6 +181,29 @@ struct soc_intel_cannonlake_config {
/* Enable/Disable HotPlug support for Root Port */
uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
/*
* Enable/Disable AER (Advanced Error Reporting) for Root Port
* 0: Disable AER
* 1: Enable AER
*/
uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
/* PCIE RP ASPM, ASPM support for the root port */
enum {
AspmDefault,
AspmDisabled,
AspmL0s,
AspmL1,
AspmL0sL1,
AspmAutoConfig,
} PcieRpAspm[CONFIG_MAX_ROOT_PORTS];
/* PCIE RP Max Payload, Max Payload Size supported */
enum {
RpMaxPayload_128,
RpMaxPayload_256,
} PcieRpMaxPayload[CONFIG_MAX_ROOT_PORTS];
/* eMMC and SD */
uint8_t ScsEmmcHs400Enabled;
/* Need to update DLL setting to get Emmc running at HS400 speed */

14
src/soc/intel/cannonlake/fsp_params.c
View File

@@ -319,10 +319,22 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(config->PcieClkSrcUsage));
memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
sizeof(config->PcieClkSrcClkReq));
memcpy(params->PcieRpAdvancedErrorReporting,
config->PcieRpAdvancedErrorReporting,
sizeof(params->PcieRpAdvancedErrorReporting));
memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,
sizeof(config->PcieRpLtrEnable));
memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
sizeof(config->PcieRpHotPlug));
sizeof(params->PcieRpHotPlug));
for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i];
if (config->PcieRpAspm[i])
params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1;
};
/* eMMC and SD */
dev = pcidev_path_on_root(PCH_DEVFN_EMMC);