From 2f5183c7af57bdefc88999bba62896bbcfe606c6 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 9 May 2020 12:57:02 -0700 Subject: [PATCH 001/405] soc/amd/common/block: Add support for common config for AMD SoCs This change adds support for struct soc_amd_common_config that allows multiple AMD SoCs to share common configuration. This can then be used by common/block drivers to get the required configuration from device tree. It also provides function declaration for soc_get_common_config() that needs to be provided by SoCs making use of the common configuration structure. Signed-off-by: Furquan Shaikh Change-Id: Idb0d797525414c99894a8e4ede65469381db7794 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41246 Reviewed-by: Raul Rangel Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- .../amd/common/block/include/amdblocks/chip.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 src/soc/amd/common/block/include/amdblocks/chip.h diff --git a/src/soc/amd/common/block/include/amdblocks/chip.h b/src/soc/amd/common/block/include/amdblocks/chip.h new file mode 100644 index 0000000000..26ad26a6b1 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/chip.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __AMDBLOCKS_CHIP_H__ +#define __AMDBLOCKS_CHIP_H__ + +struct soc_amd_common_config { +}; + +/* + * SoC callback that returns pointer to soc_amd_common_config structure embedded within the chip + * soc config. + */ +const struct soc_amd_common_config *soc_get_common_config(void); + +#endif From d82c7d24ffc64e7caeaff6ccd7c79d3946142afc Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 9 May 2020 17:18:48 -0700 Subject: [PATCH 002/405] soc/amd/common/block/lpc: Split lpc_set_spibase() into two functions This change splits lpc_set_spibase() into two separate functions: lpc_set_spibase() - Sets MMIO base address for SPI controller and eSPI controller (if supported by platforms) lpc_enable_spi_rom() - Enables SPI ROM This split is done to allow setting of MMIO base independent of ROM enable bits. On platforms like Picasso, eSPI base is determined by the same register and hence eSPI can set the BAR without having to touch the enable bits. Signed-off-by: Furquan Shaikh Change-Id: I3f270ba1745b4bb8a403f00cd069a02e21d444be Reviewed-on: https://review.coreboot.org/c/coreboot/+/41247 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Aaron Durbin Reviewed-by: Felix Held --- .../amd/common/block/include/amdblocks/lpc.h | 11 ++++++++++- src/soc/amd/common/block/lpc/lpc_util.c | 18 ++++++++++++++---- src/soc/amd/picasso/southbridge.c | 4 +++- src/soc/amd/stoneyridge/southbridge.c | 4 +++- 4 files changed, 30 insertions(+), 7 deletions(-) diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index d7a455a681..00210a7fe1 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -179,6 +179,15 @@ int lpc_find_wideio_range(uint16_t start, uint16_t size); int lpc_set_wideio_range(uint16_t start, uint16_t size); uintptr_t lpc_get_spibase(void); -void lpc_set_spibase(uint32_t base, uint32_t enable); + +/* + * Sets MMIO base address for SPI controller and eSPI controller (if supported by platform). + * + * eSPI base = SPI base + 0x10000 + */ +void lpc_set_spibase(uint32_t base); + +/* Enable SPI ROM (SPI_ROM_ENABLE, SPI_ROM_ALT_ENABLE) */ +void lpc_enable_spi_rom(uint32_t enable); #endif /* __AMDBLOCKS_LPC_H__ */ diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index 97ef17c612..c9786e7aa2 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -322,19 +322,29 @@ uintptr_t lpc_get_spibase(void) return (uintptr_t)base; } -void lpc_set_spibase(u32 base, u32 enable) +void lpc_set_spibase(uint32_t base) { - u32 reg32; + uint32_t reg32; + + reg32 = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER); + + reg32 &= SPI_BASE_ALIGNMENT - 1; /* preserve only reserved, enables */ + reg32 |= ALIGN_DOWN(base, SPI_BASE_ALIGNMENT); + + pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, reg32); +} + +void lpc_enable_spi_rom(uint32_t enable) +{ + uint32_t reg32; /* only two types of CS# enables are allowed */ enable &= SPI_ROM_ENABLE | SPI_ROM_ALT_ENABLE; reg32 = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER); - reg32 &= SPI_BASE_ALIGNMENT - 1; /* preserve only reserved, enables */ reg32 &= ~(SPI_ROM_ENABLE | SPI_ROM_ALT_ENABLE); reg32 |= enable; - reg32 |= ALIGN_DOWN(base, SPI_BASE_ALIGNMENT); pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, reg32); } diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 73ab03b643..6308953fc6 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -207,7 +207,9 @@ static uintptr_t sb_init_spi_base(void) if (base) return base; - lpc_set_spibase(SPI_BASE_ADDRESS, SPI_ROM_ENABLE); + lpc_set_spibase(SPI_BASE_ADDRESS); + lpc_enable_spi_rom(SPI_ROM_ENABLE); + return SPI_BASE_ADDRESS; } diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index ccdedf4bbe..e90fe1b457 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -265,7 +265,9 @@ static uintptr_t sb_init_spi_base(void) if (base) return base; - lpc_set_spibase(SPI_BASE_ADDRESS, SPI_ROM_ENABLE); + lpc_set_spibase(SPI_BASE_ADDRESS); + lpc_enable_spi_rom(SPI_ROM_ENABLE); + return SPI_BASE_ADDRESS; } From edd9a4f9e74a2dca47aef286572f4742e516b47a Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Wed, 22 Apr 2020 17:21:52 -0400 Subject: [PATCH 003/405] nb/intel/i440bx: Drop mainboard_enable_serial() All boards using this northbridge now enable serial in bootblock, so this is no longer needed. Change-Id: I6baf2de81870dbba2a7f1abb3f1fdd6716d64511 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/41048 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/northbridge/intel/i440bx/raminit.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index 87c799ee5f..1bd5ab6e0f 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -9,7 +9,6 @@ void enable_spd(void); void disable_spd(void); void sdram_initialize(int s3resume); -void mainboard_enable_serial(void); /* Debug */ #if CONFIG(DEBUG_RAM_SETUP) From a3a71c64ab39f94e4cbc42567424027589a1d44b Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 10 May 2020 12:25:36 +0200 Subject: [PATCH 004/405] Revert "mb/{lenovo/x201,packardbell/ms2290}/acpi: Use GOS method" This reverts commit b3100775ae29caebd068db8f6209561abda2fb0c. This was part of a series that moved things to common code and causes regressions. Change-Id: I239906e498c8352e6880408744f176a8aeb13dc8 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/41191 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/lenovo/x201/acpi/platform.asl | 58 ++++++++++++++++++- .../packardbell/ms2290/acpi/platform.asl | 58 ++++++++++++++++++- 2 files changed, 114 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl index 1a3279d383..b03f45f8f0 100644 --- a/src/mainboard/lenovo/x201/acpi/platform.asl +++ b/src/mainboard/lenovo/x201/acpi/platform.asl @@ -42,6 +42,62 @@ Scope(\_SB) /* TRAP(71) */ /* TODO */ - \GOS() + /* Determine the Operating System and save the value in OSYS. + * We have to do this in order to be able to work around + * certain windows bugs. + * + * OSYS value | Operating System + * -----------+------------------ + * 2000 | Windows 2000 + * 2001 | Windows XP(+SP1) + * 2002 | Windows XP SP2 + * 2006 | Windows Vista + * ???? | Windows 7 + */ + + /* Let's assume we're running at least Windows 2000 */ + Store (2000, OSYS) + + If (CondRefOf(_OSI)) { + If (_OSI("Windows 2001")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP2")) { + Store (2002, OSYS) + } + + If (_OSI("Windows 2001.1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001.1 SP1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2006")) { + Store (2006, OSYS) + } + + If (_OSI("Windows 2006.1")) { + Store (2006, OSYS) + } + + If (_OSI("Windows 2006 SP1")) { + Store (2006, OSYS) + } + + If (_OSI("Windows 2009")) { + Store (2009, OSYS) + } + + If (_OSI("Windows 2012")) { + Store (2012, OSYS) + } + } } } diff --git a/src/mainboard/packardbell/ms2290/acpi/platform.asl b/src/mainboard/packardbell/ms2290/acpi/platform.asl index 5213ed192c..297eeb4f31 100644 --- a/src/mainboard/packardbell/ms2290/acpi/platform.asl +++ b/src/mainboard/packardbell/ms2290/acpi/platform.asl @@ -32,6 +32,62 @@ Scope(\_SB) /* TRAP(71) */ /* TODO */ - \GOS() + /* Determine the Operating System and save the value in OSYS. + * We have to do this in order to be able to work around + * certain windows bugs. + * + * OSYS value | Operating System + * -----------+------------------ + * 2000 | Windows 2000 + * 2001 | Windows XP(+SP1) + * 2002 | Windows XP SP2 + * 2006 | Windows Vista + * ???? | Windows 7 + */ + + /* Let's assume we're running at least Windows 2000 */ + Store (2000, OSYS) + + If (CondRefOf(_OSI)) { + If (_OSI("Windows 2001")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP2")) { + Store (2002, OSYS) + } + + If (_OSI("Windows 2001.1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001.1 SP1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2006")) { + Store (2006, OSYS) + } + + If (_OSI("Windows 2006.1")) { + Store (2006, OSYS) + } + + If (_OSI("Windows 2006 SP1")) { + Store (2006, OSYS) + } + + If (_OSI("Windows 2009")) { + Store (2009, OSYS) + } + + If (_OSI("Windows 2012")) { + Store (2012, OSYS) + } + } } } From c08bf025f7609d535e806787d9a1f12f4b33f17e Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 10 May 2020 12:27:32 +0200 Subject: [PATCH 005/405] Revert "sb/intel/common/acpi: Add more Windows versions" This reverts commit cc805d9dd64ca2d3c8de2b2de2ea7c53b387ff8f. Advertising certain Windows versions triggers different paths in the OS. As there may also be device specific quirks in the OS, such changes need to be tested thoroughly on all affected devices. There was at least one very subtle regression introduced by this. When Linux sees "Windows 2012" support advertised, it disables the `acpi_video` backlight controls, at least on devices with Intel IGD. Without user-space handling the ACPI events, keyboard backlight controls stop working. Moreover, the commit message didn't state any reason for this change. Why was it merged? Change-Id: I722075f8e8f836b039fb8b8277e665fb49dac8f4 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/41192 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- .../intel/common/acpi/platform.asl | 34 ++----------------- 1 file changed, 2 insertions(+), 32 deletions(-) diff --git a/src/southbridge/intel/common/acpi/platform.asl b/src/southbridge/intel/common/acpi/platform.asl index b92872920c..2786d93ec5 100644 --- a/src/southbridge/intel/common/acpi/platform.asl +++ b/src/southbridge/intel/common/acpi/platform.asl @@ -47,16 +47,10 @@ Method(GOS, 0) * OSYS value | Operating System * -----------+------------------ * 2000 | Windows 2000 - * 2001 | Windows XP - * 2001 | Windows XP SP1 - * 2001 | Windows Server 2003 - * 2001 | Windows Server 2003 SP1 + * 2001 | Windows XP(+SP1) * 2002 | Windows XP SP2 * 2006 | Windows Vista - * 2006 | Windows Vista SP1 - * 2006 | Windows Server 2008 - * 2009 | Windows 7 - * 2012 | Windows 8 + * ???? | Windows 7 */ /* Let's assume we're running at least Windows 2000 */ @@ -71,14 +65,6 @@ Method(GOS, 0) Store (2001, OSYS) } - If (_OSI("Windows 2001.1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001.1 SP1")) { - Store (2001, OSYS) - } - If (_OSI("Windows 2001 SP2")) { Store (2002, OSYS) } @@ -86,21 +72,5 @@ Method(GOS, 0) If (_OSI("Windows 2006")) { Store (2006, OSYS) } - - If (_OSI("Windows 2006 SP1")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006.1")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2009")) { - Store (2009, OSYS) - } - - If (_OSI("Windows 2012")) { - Store (2012, OSYS) - } } } From 5e64f01e791825a866a51919cd006de6512389df Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 7 May 2020 01:23:59 +0200 Subject: [PATCH 006/405] soc/intel/skl: Drop weak mainboard_memory_init_params MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We should not need that. Change-Id: Ic0181a300670ed7ee999dafedac79f3f89bfbee9 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41114 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Michael Niewöhner --- src/soc/intel/skylake/romstage/romstage.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index e2afdc59a3..99f444ad5e 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -323,8 +323,3 @@ void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, memory_cfg->MrcFastBoot = 0x00; memory_cfg->SaGv = 0x02; } - -__weak void mainboard_memory_init_params(FSPM_UPD *mupd) -{ - /* Do nothing */ -} From 3b3512941b557e1b8c0eb1922fa762f225848344 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sun, 10 May 2020 22:00:42 +0200 Subject: [PATCH 007/405] Documentation/getting_started: Fix typo Change-Id: I41571c45719dfade49a021b6bafe80afdcb7b581 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/41223 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- Documentation/getting_started/architecture.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/getting_started/architecture.md b/Documentation/getting_started/architecture.md index d037f752d9..8d63ac2c75 100644 --- a/Documentation/getting_started/architecture.md +++ b/Documentation/getting_started/architecture.md @@ -10,7 +10,7 @@ coreboot consists of multiple stages that are compiled as separate binaries and are inserted into the CBFS with custom compression. The bootblock usually doesn't have compression while the ramstage and payload are compressed with LZMA. -Each stage loads the next stage a given address (possibly decompressing it). +Each stage loads the next stage at given address (possibly decompressing it). Some stages are relocatable and can be placed anywhere in DRAM. Those stages are usually cached in CBMEM for faster loading times on ACPI S3 resume. From e6fb1344ed9188e19be4b54bdf1a76680b8c4523 Mon Sep 17 00:00:00 2001 From: Iru Cai Date: Wed, 8 Apr 2020 19:08:59 +0800 Subject: [PATCH 008/405] inteltool: fix dumping of Lynx Point LP and Wildcat Point PM registers Currently inteltool uses the addresses and names of the PCH of previous generations. It's wrong for Lynx Point LP and Wildcat Point. The addresses and names of the I/O registers can be found in "Mobile 4th Generation Intel Core Processor Family I/O Datasheet" (Document Number: 329003-003) for Lynx Point LP and "Mobile 5th Generation Intel Core Processor Family I/O, Intel Core M Processor Family I/O, Mobile Intel Pentium Processor Family I/O, and Mobile Intel Celeron Processor Family I/O Datasheet" (Document Number: 330837-004) for Wildcat Point. Change-Id: If6ba718ccff077aa89affec89018bd7923527466 Signed-off-by: Iru Cai Reviewed-on: https://review.coreboot.org/c/coreboot/+/40273 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- util/inteltool/powermgt.c | 52 +++++++++++++++++++++++++++++++++++---- 1 file changed, 47 insertions(+), 5 deletions(-) diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 2f44e1d28d..a21d002aac 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -28,6 +28,44 @@ static const io_register_t sunrise_pm_registers[] = { { 0x9c, 4, "GPE0_EN_127_96" }, }; +static const io_register_t lynxpoint_lp_pm_registers[] = { + { 0x00, 2, "PM1_STS" }, /* PM1 Status; ACPI pointer: PM1a_EVT_BLK */ + { 0x02, 2, "PM1_EN" }, /* PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2 */ + { 0x04, 4, "PM1_CNT" }, /* PM1 Control; ACPI pointer: PM1a_CNT_BLK */ + { 0x08, 4, "PM1_TMR" }, /* PM1 Timer; ACPI pointer: PMTMR_BLK */ + { 0x30, 4, "SMI_EN" }, + { 0x34, 4, "SMI_STS" }, + { 0x42, 1, "GPE_CNTL" }, + { 0x44, 2, "DEVACT_STS" }, /* Device Activity Status */ + { 0x50, 1, "PM2_CNT" }, /* PM2 Control; ACPI pointer: PM2a_CNT_BLK */ + /* The TCO registers start here. */ + { 0x60, 2, "TCO_RLD" }, + { 0x62, 1, "TCO_DAT_IN" }, + { 0x63, 1, "TCO_DAT_OUT" }, + { 0x64, 2, "TCO1_STS" }, + { 0x66, 2, "TCO2_STS" }, + { 0x68, 2, "TCO1_CNT" }, + { 0x6a, 2, "TCO2_CNT" }, + { 0x6c, 2, "TCO_MESSAGE" }, + { 0x6e, 1, "TCO_WDCNT" }, + { 0x6f, 1, "RESERVED" }, + { 0x70, 1, "SW_IRQ_GEN" }, + { 0x71, 1, "RESERVED" }, + { 0x72, 2, "TCO_TMR" }, + { 0x74, 4, "RESERVED" }, + { 0x78, 4, "RESERVED" }, + { 0x7c, 4, "RESERVED" }, + /* The TCO registers end here. */ + { 0x80, 4, "GPE0_STS_31_0" }, + { 0x84, 4, "GPE0_STS_63_32" }, + { 0x88, 4, "GPE0_STS_94_64" }, + { 0x8c, 4, "GPE0_STS_127_96" }, + { 0x90, 4, "GPE0_EN_31_0" }, + { 0x94, 4, "GPE0_EN_63_32" }, + { 0x98, 4, "GPE0_EN_94_64" }, + { 0x9c, 4, "GPE0_EN_127_96" }, +}; + static const io_register_t pch_pm_registers[] = { { 0x00, 2, "PM1_STS" }, // PM1 Status; ACPI pointer: PM1a_EVT_BLK { 0x02, 2, "PM1_EN" }, // PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2 @@ -712,11 +750,6 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) case PCI_DEVICE_ID_INTEL_HM76: case PCI_DEVICE_ID_INTEL_HM75: case PCI_DEVICE_ID_INTEL_HM70: - case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL: - case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM: - case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE: - case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM: - case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP: case PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC: case PCI_DEVICE_ID_INTEL_C8_MOBILE: case PCI_DEVICE_ID_INTEL_C8_DESKTOP: @@ -737,6 +770,15 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) pm_registers = pch_pm_registers; pm_registers_size = ARRAY_SIZE(pch_pm_registers); break; + case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL: + case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM: + case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE: + case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM: + case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP: + pmbase = pci_read_word(sb, 0x40) & 0xff80; + pm_registers = lynxpoint_lp_pm_registers; + pm_registers_size = ARRAY_SIZE(lynxpoint_lp_pm_registers); + break; case PCI_DEVICE_ID_INTEL_ICH10: case PCI_DEVICE_ID_INTEL_ICH10R: pmbase = pci_read_word(sb, 0x40) & 0xff80; From 3b02006afe8a85477dafa1bd149f1f0dba02afc7 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 27 Apr 2020 12:03:49 -0700 Subject: [PATCH 009/405] device: Enable resource allocator to use multiple ranges This change updates the resource allocator in coreboot to allow using multiple ranges for resource allocation rather than restricting available window to a single base/limit pair. This is done in preparation to allow 64-bit resource allocation. Following changes are made as part of this: a) Resource allocator still makes 2 passes at the entire tree. The first pass is to gather the resource requirements of each device under each domain. It walks recursively in DFS fashion to gather the requirements of the leaf devices and propagates this back up to the downstream bridges of the domain. Domain is special in the sense that it has fixed resource ranges. Hence, the resource requirements from the downstream devices have no effect on the domain resource windows. This results in domain resource limits being unmodified after the first pass. b) Once the requirements for all the devices under the domain are gathered, resource allocator walks a second time to allocate resources to downstream devices as per the requirements. Here, instead of maintaining a single window for allocating resources, it creates a list of memranges starting with the resource window at domain and then applying constraints to create holes for any fixed resources. This ensures that there is no overlap with fixed resources under the domain. c) Domain does not differentiate between mem and prefmem. Since they are allocated space from the same resource window at the domain level, it considers all resource requests from downstream devices of the domain independent of the prefetch type. d) Once resource allocation is done at the domain level, resource allocator walks down the downstream bridges and continues the same process until it reaches the leaves. Bridges have separate windows for mem and prefmem. Hence, unlike domain, the resource allocator at bridge level ensures that downstream requirements are satisfied by taking prefetch type into consideration. e) This whole 2-pass process is performed for every domain in the system under the assumption that domains do not have overlapping address spaces. Noticeable differences from previous resource allocator: a) Changes in print logs observed due to flows being slightly different. b) Base, limit and size of domain resources are no longer updated based on downstream requirements. c) Memranges are used instead of a single base/limit pair for determining resource allocation. d) Previously, if a resource request did not fit in the available base/limit window, then the resource would be allocated over DRAM or any other address space defeating the principle of "no overlap". With this change, any time a resource cannot fit in the available ranges, it complains and ensures that the resource is effectively disabled by setting base same as the limit. e) Resource allocator no longer looks at multiple links to determine the right bus for a resource. None of the current boards have multiple buses under any downstream device of the domain. The only device with multiple links seems to be the cpu cluster device for some AMD platforms. BUG=b:149186922 TEST=Verified that resource allocation looks correct based on addresses assigned on Volteer. Signed-off-by: Furquan Shaikh Change-Id: Ia1f089877c62e119c6a994a10809c9cc0050ec9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39486 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/device/device.c | 1025 +++++++++++++++++++++---------------------- 1 file changed, 511 insertions(+), 514 deletions(-) diff --git a/src/device/device.c b/src/device/device.c index e4b5f12023..3ed64da34a 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -154,14 +155,10 @@ struct device *alloc_find_dev(struct bus *parent, struct device_path *path) */ static resource_t round(resource_t val, unsigned long pow) { - resource_t mask; - mask = (1ULL << pow) - 1ULL; - val += mask; - val &= ~mask; - return val; + return ALIGN_UP(val, POWER_OF_2(pow)); } -static const char *resource2str(struct resource *res) +static const char *resource2str(const struct resource *res) { if (res->flags & IORESOURCE_IO) return "io"; @@ -266,466 +263,6 @@ static const struct device *largest_resource(struct bus *bus, return state.result_dev; } -/** - * This function is the guts of the resource allocator. - * - * The problem. - * - Allocate resource locations for every device. - * - Don't overlap, and follow the rules of bridges. - * - Don't overlap with resources in fixed locations. - * - Be efficient so we don't have ugly strategies. - * - * The strategy. - * - Devices that have fixed addresses are the minority so don't - * worry about them too much. Instead only use part of the address - * space for devices with programmable addresses. This easily handles - * everything except bridges. - * - * - PCI devices are required to have their sizes and their alignments - * equal. In this case an optimal solution to the packing problem - * exists. Allocate all devices from highest alignment to least - * alignment or vice versa. Use this. - * - * - So we can handle more than PCI run two allocation passes on bridges. The - * first to see how large the resources are behind the bridge, and what - * their alignment requirements are. The second to assign a safe address to - * the devices behind the bridge. This allows us to treat a bridge as just - * a device with a couple of resources, and not need to special case it in - * the allocator. Also this allows handling of other types of bridges. - * - * @param bus The bus we are traversing. - * @param bridge The bridge resource which must contain the bus' resources. - * @param type_mask This value gets ANDed with the resource type. - * @param type This value must match the result of the AND. - * @return TODO - */ -static void compute_resources(struct bus *bus, struct resource *bridge, - unsigned long type_mask, unsigned long type) -{ - const struct device *dev; - struct resource *resource; - resource_t base; - base = round(bridge->base, bridge->align); - - if (!bus) - return; - - printk(BIOS_SPEW, "%s %s: base: %llx size: %llx align: %d gran: %d" - " limit: %llx\n", dev_path(bus->dev), resource2str(bridge), - base, bridge->size, bridge->align, - bridge->gran, bridge->limit); - - /* For each child which is a bridge, compute the resource needs. */ - for (dev = bus->children; dev; dev = dev->sibling) { - struct resource *child_bridge; - - if (!dev->link_list) - continue; - - /* Find the resources with matching type flags. */ - for (child_bridge = dev->resource_list; child_bridge; - child_bridge = child_bridge->next) { - struct bus* link; - - if (!(child_bridge->flags & IORESOURCE_BRIDGE) - || (child_bridge->flags & type_mask) != type) - continue; - - /* - * Split prefetchable memory if combined. Many domains - * use the same address space for prefetchable memory - * and non-prefetchable memory. Bridges below them need - * it separated. Add the PREFETCH flag to the type_mask - * and type. - */ - link = dev->link_list; - while (link && link->link_num != - IOINDEX_LINK(child_bridge->index)) - link = link->next; - - if (link == NULL) { - printk(BIOS_ERR, "link %ld not found on %s\n", - IOINDEX_LINK(child_bridge->index), - dev_path(dev)); - } - - compute_resources(link, child_bridge, - type_mask | IORESOURCE_PREFETCH, - type | (child_bridge->flags & - IORESOURCE_PREFETCH)); - } - } - - /* Remember we haven't found anything yet. */ - resource = NULL; - - /* - * Walk through all the resources on the current bus and compute the - * amount of address space taken by them. Take granularity and - * alignment into account. - */ - while ((dev = largest_resource(bus, &resource, type_mask, type))) { - - /* Size 0 resources can be skipped. */ - if (!resource->size) - continue; - - /* Propagate the resource alignment to the bridge resource. */ - if (resource->align > bridge->align) - bridge->align = resource->align; - - /* Propagate the resource limit to the bridge register. */ - if (bridge->limit > resource->limit) - bridge->limit = resource->limit; - - /* Warn if it looks like APICs aren't declared. */ - if ((resource->limit == 0xffffffff) && - (resource->flags & IORESOURCE_ASSIGNED)) { - printk(BIOS_ERR, - "Resource limit looks wrong! (no APIC?)\n"); - printk(BIOS_ERR, "%s %02lx limit %08llx\n", - dev_path(dev), resource->index, resource->limit); - } - - if (resource->flags & IORESOURCE_IO) { - /* - * Don't allow potential aliases over the legacy PCI - * expansion card addresses. The legacy PCI decodes - * only 10 bits, uses 0x100 - 0x3ff. Therefore, only - * 0x00 - 0xff can be used out of each 0x400 block of - * I/O space. - */ - if ((base & 0x300) != 0) { - base = (base & ~0x3ff) + 0x400; - } - /* - * Don't allow allocations in the VGA I/O range. - * PCI has special cases for that. - */ - else if ((base >= 0x3b0) && (base <= 0x3df)) { - base = 0x3e0; - } - } - /* Base must be aligned. */ - base = round(base, resource->align); - resource->base = base; - base += resource->size; - - printk(BIOS_SPEW, "%s %02lx * [0x%llx - 0x%llx] %s\n", - dev_path(dev), resource->index, resource->base, - resource->base + resource->size - 1, - resource2str(resource)); - } - - /* - * A PCI bridge resource does not need to be a power of two size, but - * it does have a minimum granularity. Round the size up to that - * minimum granularity so we know not to place something else at an - * address positively decoded by the bridge. - */ - bridge->size = round(base, bridge->gran) - - round(bridge->base, bridge->align); - - printk(BIOS_SPEW, "%s %s: base: %llx size: %llx align: %d gran: %d" - " limit: %llx done\n", dev_path(bus->dev), - resource2str(bridge), - base, bridge->size, bridge->align, bridge->gran, bridge->limit); -} - -/** - * This function is the second part of the resource allocator. - * - * See the compute_resources function for a more detailed explanation. - * - * This function assigns the resources a value. - * - * @param bus The bus we are traversing. - * @param bridge The bridge resource which must contain the bus' resources. - * @param type_mask This value gets ANDed with the resource type. - * @param type This value must match the result of the AND. - * - * @see compute_resources - */ -static void allocate_resources(struct bus *bus, struct resource *bridge, - unsigned long type_mask, unsigned long type) -{ - const struct device *dev; - struct resource *resource; - resource_t base; - base = bridge->base; - - if (!bus) - return; - - printk(BIOS_SPEW, "%s %s: base:%llx size:%llx align:%d gran:%d " - "limit:%llx\n", dev_path(bus->dev), - resource2str(bridge), - base, bridge->size, bridge->align, bridge->gran, bridge->limit); - - /* Remember we haven't found anything yet. */ - resource = NULL; - - /* - * Walk through all the resources on the current bus and allocate them - * address space. - */ - while ((dev = largest_resource(bus, &resource, type_mask, type))) { - - /* Propagate the bridge limit to the resource register. */ - if (resource->limit > bridge->limit) - resource->limit = bridge->limit; - - /* Size 0 resources can be skipped. */ - if (!resource->size) { - /* Set the base to limit so it doesn't confuse tolm. */ - resource->base = resource->limit; - resource->flags |= IORESOURCE_ASSIGNED; - continue; - } - - if (resource->flags & IORESOURCE_IO) { - /* - * Don't allow potential aliases over the legacy PCI - * expansion card addresses. The legacy PCI decodes - * only 10 bits, uses 0x100 - 0x3ff. Therefore, only - * 0x00 - 0xff can be used out of each 0x400 block of - * I/O space. - */ - if ((base & 0x300) != 0) { - base = (base & ~0x3ff) + 0x400; - } - /* - * Don't allow allocations in the VGA I/O range. - * PCI has special cases for that. - */ - else if ((base >= 0x3b0) && (base <= 0x3df)) { - base = 0x3e0; - } - } - - if ((round(base, resource->align) + resource->size - 1) <= - resource->limit) { - /* Base must be aligned. */ - base = round(base, resource->align); - resource->base = base; - resource->limit = resource->base + resource->size - 1; - resource->flags |= IORESOURCE_ASSIGNED; - resource->flags &= ~IORESOURCE_STORED; - base += resource->size; - } else { - printk(BIOS_ERR, "!! Resource didn't fit !!\n"); - printk(BIOS_ERR, " aligned base %llx size %llx " - "limit %llx\n", round(base, resource->align), - resource->size, resource->limit); - printk(BIOS_ERR, " %llx needs to be <= %llx " - "(limit)\n", (round(base, resource->align) + - resource->size) - 1, resource->limit); - printk(BIOS_ERR, " %s%s %02lx * [0x%llx - 0x%llx]" - " %s\n", (resource->flags & IORESOURCE_ASSIGNED) - ? "Assigned: " : "", dev_path(dev), - resource->index, resource->base, - resource->base + resource->size - 1, - resource2str(resource)); - } - - printk(BIOS_SPEW, "%s %02lx * [0x%llx - 0x%llx] %s\n", - dev_path(dev), resource->index, resource->base, - resource->size ? resource->base + resource->size - 1 : - resource->base, resource2str(resource)); - } - - /* - * A PCI bridge resource does not need to be a power of two size, but - * it does have a minimum granularity. Round the size up to that - * minimum granularity so we know not to place something else at an - * address positively decoded by the bridge. - */ - - bridge->flags |= IORESOURCE_ASSIGNED; - - printk(BIOS_SPEW, "%s %s: next_base: %llx size: %llx align: %d " - "gran: %d done\n", dev_path(bus->dev), - resource2str(bridge), base, bridge->size, bridge->align, - bridge->gran); - - /* For each child which is a bridge, allocate_resources. */ - for (dev = bus->children; dev; dev = dev->sibling) { - struct resource *child_bridge; - - if (!dev->link_list) - continue; - - /* Find the resources with matching type flags. */ - for (child_bridge = dev->resource_list; child_bridge; - child_bridge = child_bridge->next) { - struct bus* link; - - if (!(child_bridge->flags & IORESOURCE_BRIDGE) || - (child_bridge->flags & type_mask) != type) - continue; - - /* - * Split prefetchable memory if combined. Many domains - * use the same address space for prefetchable memory - * and non-prefetchable memory. Bridges below them need - * it separated. Add the PREFETCH flag to the type_mask - * and type. - */ - link = dev->link_list; - while (link && link->link_num != - IOINDEX_LINK(child_bridge->index)) - link = link->next; - if (link == NULL) - printk(BIOS_ERR, "link %ld not found on %s\n", - IOINDEX_LINK(child_bridge->index), - dev_path(dev)); - - allocate_resources(link, child_bridge, - type_mask | IORESOURCE_PREFETCH, - type | (child_bridge->flags & - IORESOURCE_PREFETCH)); - } - } -} - -static int resource_is(struct resource *res, u32 type) -{ - return (res->flags & IORESOURCE_TYPE_MASK) == type; -} - -struct constraints { - struct resource io, mem; -}; - -static struct resource *resource_limit(struct constraints *limits, - struct resource *res) -{ - struct resource *lim = NULL; - - /* MEM, or I/O - skip any others. */ - if (resource_is(res, IORESOURCE_MEM)) - lim = &limits->mem; - else if (resource_is(res, IORESOURCE_IO)) - lim = &limits->io; - - return lim; -} - -static void constrain_resources(const struct device *dev, - struct constraints* limits) -{ - const struct device *child; - struct resource *res; - struct resource *lim; - struct bus *link; - - /* Constrain limits based on the fixed resources of this device. */ - for (res = dev->resource_list; res; res = res->next) { - if (!(res->flags & IORESOURCE_FIXED)) - continue; - if (!res->size) { - /* It makes no sense to have 0-sized, fixed resources.*/ - printk(BIOS_ERR, "skipping %s@%lx fixed resource, " - "size=0!\n", dev_path(dev), res->index); - continue; - } - - lim = resource_limit(limits, res); - if (!lim) - continue; - - /* - * Is it a fixed resource outside the current known region? - * If so, we don't have to consider it - it will be handled - * correctly and doesn't affect current region's limits. - */ - if (((res->base + res->size -1) < lim->base) - || (res->base > lim->limit)) - continue; - - printk(BIOS_SPEW, "%s: %s %02lx base %08llx limit %08llx %s (fixed)\n", - __func__, dev_path(dev), res->index, res->base, - res->base + res->size - 1, resource2str(res)); - - /* - * Choose to be above or below fixed resources. This check is - * signed so that "negative" amounts of space are handled - * correctly. - */ - if ((signed long long)(lim->limit - (res->base + res->size -1)) - > (signed long long)(res->base - lim->base)) - lim->base = res->base + res->size; - else - lim->limit = res->base -1; - } - - /* Descend into every enabled child and look for fixed resources. */ - for (link = dev->link_list; link; link = link->next) { - for (child = link->children; child; child = child->sibling) { - if (child->enabled) - constrain_resources(child, limits); - } - } -} - -static void avoid_fixed_resources(const struct device *dev) -{ - struct constraints limits; - struct resource *res; - struct resource *lim; - - printk(BIOS_SPEW, "%s: %s\n", __func__, dev_path(dev)); - - /* Initialize constraints to maximum size. */ - limits.io.base = 0; - limits.io.limit = 0xffffffffffffffffULL; - limits.mem.base = 0; - limits.mem.limit = 0xffffffffffffffffULL; - - /* Constrain the limits to dev's initial resources. */ - for (res = dev->resource_list; res; res = res->next) { - if ((res->flags & IORESOURCE_FIXED)) - continue; - printk(BIOS_SPEW, "%s:@%s %02lx limit %08llx\n", __func__, - dev_path(dev), res->index, res->limit); - - lim = resource_limit(&limits, res); - if (!lim) - continue; - - if (res->base > lim->base) - lim->base = res->base; - if (res->limit < lim->limit) - lim->limit = res->limit; - } - - /* Look through the tree for fixed resources and update the limits. */ - constrain_resources(dev, &limits); - - /* Update dev's resources with new limits. */ - for (res = dev->resource_list; res; res = res->next) { - if ((res->flags & IORESOURCE_FIXED)) - continue; - - lim = resource_limit(&limits, res); - if (!lim) - continue; - - /* Is the resource outside the limits? */ - if (lim->base > res->base) - res->base = lim->base; - if (res->limit > lim->limit) - res->limit = lim->limit; - - /* MEM resources need to start at the highest address manageable. */ - if (res->flags & IORESOURCE_MEM) - res->base = resource_max(res); - - printk(BIOS_SPEW, "%s:@%s %02lx base %08llx limit %08llx\n", - __func__, dev_path(dev), res->index, res->base, res->limit); - } -} - struct device *vga_pri = NULL; static void set_vga_bridge_bits(void) { @@ -981,6 +518,513 @@ void dev_enumerate(void) printk(BIOS_INFO, "done\n"); } +static bool dev_has_children(const struct device *dev) +{ + const struct bus *bus = dev->link_list; + return bus && bus->children; +} + +/* + * During pass 1, once all the requirements for downstream devices of a bridge are gathered, + * this function calculates the overall resource requirement for the bridge. It starts by + * picking the largest resource requirement downstream for the given resource type and works by + * adding requirements in descending order. + * + * Additionally, it takes alignment and limits of the downstream devices into consideration and + * ensures that they get propagated to the bridge resource. This is required to guarantee that + * the upstream bridge/domain honors the limit and alignment requirements for this bridge based + * on the tightest constraints downstream. + */ +static void update_bridge_resource(const struct device *bridge, struct resource *bridge_res, + unsigned long type_match) +{ + const struct device *child; + struct resource *child_res; + resource_t base; + bool first_child_res = true; + const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH; + struct bus *bus = bridge->link_list; + + child_res = NULL; + + /* + * `base` keeps track of where the next allocation for child resource can take place + * from within the bridge resource window. Since the bridge resource window allocation + * is not performed yet, it can start at 0. Base gets updated every time a resource + * requirement is accounted for in the loop below. After scanning all these resources, + * base will indicate the total size requirement for the current bridge resource + * window. + */ + base = 0; + + printk(BIOS_SPEW, "%s %s: size: %llx align: %d gran: %d limit: %llx\n", + dev_path(bridge), resource2str(bridge_res), bridge_res->size, + bridge_res->align, bridge_res->gran, bridge_res->limit); + + while ((child = largest_resource(bus, &child_res, type_mask, type_match))) { + + /* Size 0 resources can be skipped. */ + if (!child_res->size) + continue; + + /* + * Propagate the resource alignment to the bridge resource if this is the first + * child resource with non-zero size being considered. For all other children + * resources, alignment is taken care of by updating the base to round up as per + * the child resource alignment. It is guaranteed that pass 2 follows the exact + * same method of picking the resource for allocation using + * largest_resource(). Thus, as long as the alignment for first child resource + * is propagated up to the bridge resource, it can be guaranteed that the + * alignment for all resources is appropriately met. + */ + if (first_child_res && (child_res->align > bridge_res->align)) + bridge_res->align = child_res->align; + + first_child_res = false; + + /* + * Propagate the resource limit to the bridge resource only if child resource + * limit is non-zero. If a downstream device has stricter requirements + * w.r.t. limits for any resource, that constraint needs to be propagated back + * up to the downstream bridges of the domain. This guarantees that the resource + * allocation which starts at the domain level takes into account all these + * constraints thus working on a global view. + */ + if (child_res->limit && (child_res->limit < bridge_res->limit)) + bridge_res->limit = child_res->limit; + + /* + * Alignment value of 0 means that the child resource has no alignment + * requirements and so the base value remains unchanged here. + */ + base = round(base, child_res->align); + + printk(BIOS_SPEW, "%s %02lx * [0x%llx - 0x%llx] %s\n", + dev_path(child), child_res->index, base, base + child_res->size - 1, + resource2str(child_res)); + + base += child_res->size; + } + + /* + * After all downstream device resources are scanned, `base` represents the total size + * requirement for the current bridge resource window. This size needs to be rounded up + * to the granularity requirement of the bridge to ensure that the upstream + * bridge/domain allocates big enough window. + */ + bridge_res->size = round(base, bridge_res->gran); + + printk(BIOS_SPEW, "%s %s: size: %llx align: %d gran: %d limit: %llx done\n", + dev_path(bridge), resource2str(bridge_res), bridge_res->size, + bridge_res->align, bridge_res->gran, bridge_res->limit); +} + +/* + * During pass 1, resource allocator at bridge level gathers requirements from downstream + * devices and updates its own resource windows for the provided resource type. + */ +static void compute_bridge_resources(const struct device *bridge, unsigned long type_match) +{ + const struct device *child; + struct resource *res; + struct bus *bus = bridge->link_list; + const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH; + + for (res = bridge->resource_list; res; res = res->next) { + if (!(res->flags & IORESOURCE_BRIDGE)) + continue; + + if ((res->flags & type_mask) != type_match) + continue; + + /* + * Ensure that the resource requirements for all downstream bridges are + * gathered before updating the window for current bridge resource. + */ + for (child = bus->children; child; child = child->sibling) { + if (!dev_has_children(child)) + continue; + compute_bridge_resources(child, type_match); + } + + /* + * Update the window for current bridge resource now that all downstream + * requirements are gathered. + */ + update_bridge_resource(bridge, res, type_match); + } +} + +/* + * During pass 1, resource allocator walks down the entire sub-tree of a domain. It gathers + * resource requirements for every downstream bridge by looking at the resource requests of its + * children. Thus, the requirement gathering begins at the leaf devices and is propagated back + * up to the downstream bridges of the domain. + * + * At domain level, it identifies every downstream bridge and walks down that bridge to gather + * requirements for each resource type i.e. i/o, mem and prefmem. Since bridges have separate + * windows for mem and prefmem, requirements for each need to be collected separately. + * + * Domain resource windows are fixed ranges and hence requirement gathering does not result in + * any changes to these fixed ranges. + */ +static void compute_domain_resources(const struct device *domain) +{ + const struct device *child; + + if (domain->link_list == NULL) + return; + + for (child = domain->link_list->children; child; child = child->sibling) { + + /* Skip if this is not a bridge or has no children under it. */ + if (!dev_has_children(child)) + continue; + + compute_bridge_resources(child, IORESOURCE_IO); + compute_bridge_resources(child, IORESOURCE_MEM); + compute_bridge_resources(child, IORESOURCE_MEM | IORESOURCE_PREFETCH); + } +} + +static void initialize_memranges(struct memranges *ranges, const struct resource *res, + unsigned long memrange_type) +{ + resource_t res_base; + resource_t res_limit; + + memranges_init_empty(ranges, NULL, 0); + + if (res == NULL) + return; + + res_base = res->base; + res_limit = res->limit; + + if (res_base == res_limit) + return; + + memranges_insert(ranges, res_base, res_limit - res_base + 1, memrange_type); +} + +static void print_resource_ranges(const struct memranges *ranges) +{ + const struct range_entry *r; + + printk(BIOS_INFO, "Resource ranges:\n"); + + if (memranges_is_empty(ranges)) + printk(BIOS_INFO, "EMPTY!!\n"); + + memranges_each_entry(r, ranges) { + printk(BIOS_INFO, "Base: %llx, Size: %llx, Tag: %lx\n", + range_entry_base(r), range_entry_size(r), range_entry_tag(r)); + } +} + +static void mark_resource_invalid(struct resource *res) +{ + res->base = res->limit; + res->flags |= IORESOURCE_ASSIGNED; +} + +/* + * This is where the actual allocation of resources happens during pass 2. Given the list of + * memory ranges corresponding to the resource of given type, it finds the biggest unallocated + * resource using the type mask on the downstream bus. This continues in a descending + * order until all resources of given type are allocated address space within the current + * resource window. + * + * If a downstream resource cannot be allocated space for any reason, then its base is set to + * its limit and flags are updated to indicate that the resource assignment is complete. This is + * done to ensure that it does not confuse find_pci_tolm(). + */ +static void allocate_child_resources(struct bus *bus, struct memranges *ranges, + unsigned long type_mask, unsigned long type_match) +{ + struct resource *resource = NULL; + const struct device *dev; + + while ((dev = largest_resource(bus, &resource, type_mask, type_match))) { + + if (!resource->size) { + mark_resource_invalid(resource); + continue; + } + + if (memranges_steal(ranges, resource->limit, resource->size, resource->align, + type_match, &resource->base) == false) { + printk(BIOS_ERR, "ERROR: Resource didn't fit!!! "); + printk(BIOS_SPEW, "%s %02lx * size: 0x%llx limit: %llx %s\n", + dev_path(dev), resource->index, + resource->size, resource->limit, resource2str(resource)); + mark_resource_invalid(resource); + continue; + } + + resource->limit = resource->base + resource->size - 1; + resource->flags |= IORESOURCE_ASSIGNED; + + printk(BIOS_SPEW, "%s %02lx * [0x%llx - 0x%llx] limit: %llx %s\n", + dev_path(dev), resource->index, resource->base, + resource->size ? resource->base + resource->size - 1 : + resource->base, resource->limit, resource2str(resource)); + } +} + +static void update_constraints(void *gp, struct device *dev, struct resource *res) +{ + struct memranges *ranges = gp; + + if (!res->size) + return; + + printk(BIOS_SPEW, "%s: %s %02lx base %08llx limit %08llx %s (fixed)\n", + __func__, dev_path(dev), res->index, res->base, + res->base + res->size - 1, resource2str(res)); + + memranges_create_hole(ranges, res->base, res->size); +} + +static void constrain_domain_resources(struct bus *bus, struct memranges *ranges, + unsigned long type) +{ + /* + * Scan the entire tree to identify any fixed resources allocated by any device to + * ensure that the address map for domain resources are appropriately updated. + * + * Domains can typically provide memrange for entire address space. So, this function + * punches holes in the address space for all fixed resources that are already + * defined. Both IO and normal memory resources are added as fixed. Both need to be + * removed from address space where dynamic resource allocations are sourced. + */ + search_bus_resources(bus, type | IORESOURCE_FIXED, type | IORESOURCE_FIXED, + update_constraints, ranges); + + if (type == IORESOURCE_IO) { + /* + * Don't allow allocations in the VGA I/O range. PCI has special cases for + * that. + */ + memranges_create_hole(ranges, 0x3b0, 0x3df); + + /* + * Resource allocator no longer supports the legacy behavior where I/O resource + * allocation is guaranteed to avoid aliases over legacy PCI expansion card + * addresses. + */ + } +} + +/* + * This function creates a list of memranges of given type using the resource that is + * provided. If the given resource is NULL or if the resource window size is 0, then it creates + * an empty list. This results in resource allocation for that resource type failing for all + * downstream devices since there is nothing to allocate from. + * + * In case of domain, it applies additional constraints to ensure that the memranges do not + * overlap any of the fixed resources under that domain. Domain typically seems to provide + * memrange for entire address space. Thus, it is up to the chipset to add DRAM and all other + * windows which cannot be used for resource allocation as fixed resources. + */ +static void setup_resource_ranges(const struct device *dev, const struct resource *res, + unsigned long type, struct memranges *ranges) +{ + printk(BIOS_SPEW, "%s %s: base: %llx size: %llx align: %d gran: %d limit: %llx\n", + dev_path(dev), resource2str(res), res->base, res->size, res->align, + res->gran, res->limit); + + initialize_memranges(ranges, res, type); + + if (dev->path.type == DEVICE_PATH_DOMAIN) + constrain_domain_resources(dev->link_list, ranges, type); + + print_resource_ranges(ranges); +} + +static void cleanup_resource_ranges(const struct device *dev, struct memranges *ranges, + const struct resource *res) +{ + memranges_teardown(ranges); + printk(BIOS_SPEW, "%s %s: base: %llx size: %llx align: %d gran: %d limit: %llx done\n", + dev_path(dev), resource2str(res), res->base, res->size, res->align, + res->gran, res->limit); +} + +/* + * Pass 2 of resource allocator at the bridge level loops through all the resources for the + * bridge and generates a list of memory ranges similar to that at the domain level. However, + * there is no need to apply any additional constraints since the window allocated to the bridge + * is guaranteed to be non-overlapping by the allocator at domain level. + * + * Allocation at the bridge level works the same as at domain level (starts with the biggest + * resource requirement from downstream devices and continues in descending order). One major + * difference at the bridge level is that it considers prefmem resources separately from mem + * resources. + * + * Once allocation at the current bridge is complete, resource allocator continues walking down + * the downstream bridges until it hits the leaf devices. + */ +static void allocate_bridge_resources(const struct device *bridge) +{ + struct memranges ranges; + const struct resource *res; + struct bus *bus = bridge->link_list; + unsigned long type_match; + struct device *child; + const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH; + + for (res = bridge->resource_list; res; res = res->next) { + if (!res->size) + continue; + + if (!(res->flags & IORESOURCE_BRIDGE)) + continue; + + type_match = res->flags & type_mask; + + setup_resource_ranges(bridge, res, type_match, &ranges); + allocate_child_resources(bus, &ranges, type_mask, type_match); + cleanup_resource_ranges(bridge, &ranges, res); + } + + for (child = bus->children; child; child = child->sibling) { + if (!dev_has_children(child)) + continue; + + allocate_bridge_resources(child); + } +} + +static const struct resource *find_domain_resource(const struct device *domain, + unsigned long type) +{ + const struct resource *res; + + for (res = domain->resource_list; res; res = res->next) { + if (res->flags & IORESOURCE_FIXED) + continue; + + if ((res->flags & IORESOURCE_TYPE_MASK) == type) + return res; + } + + return NULL; +} + +/* + * Pass 2 of resource allocator begins at the domain level. Every domain has two types of + * resources - io and mem. For each of these resources, this function creates a list of memory + * ranges that can be used for downstream resource allocation. This list is constrained to + * remove any fixed resources in the domain sub-tree of the given resource type. It then uses + * the memory ranges to apply best fit on the resource requirements of the downstream devices. + * + * Once resources are allocated to all downstream devices of the domain, it walks down each + * downstream bridge to continue the same process until resources are allocated to all devices + * under the domain. + */ +static void allocate_domain_resources(const struct device *domain) +{ + struct memranges ranges; + struct device *child; + const struct resource *res; + + /* Resource type I/O */ + res = find_domain_resource(domain, IORESOURCE_IO); + if (res) { + setup_resource_ranges(domain, res, IORESOURCE_IO, &ranges); + allocate_child_resources(domain->link_list, &ranges, IORESOURCE_TYPE_MASK, + IORESOURCE_IO); + cleanup_resource_ranges(domain, &ranges, res); + } + + /* + * Resource type Mem: + * Domain does not distinguish between mem and prefmem resources. Thus, the resource + * allocation at domain level considers mem and prefmem together when finding the best + * fit based on the biggest resource requirement. + */ + res = find_domain_resource(domain, IORESOURCE_MEM); + if (res) { + setup_resource_ranges(domain, res, IORESOURCE_MEM, &ranges); + allocate_child_resources(domain->link_list, &ranges, IORESOURCE_TYPE_MASK, + IORESOURCE_MEM); + cleanup_resource_ranges(domain, &ranges, res); + } + + for (child = domain->link_list->children; child; child = child->sibling) { + if (!dev_has_children(child)) + continue; + + /* Continue allocation for all downstream bridges. */ + allocate_bridge_resources(child); + } +} + +/* + * This function forms the guts of the resource allocator. It walks through the entire device + * tree for each domain two times. + * + * Every domain has a fixed set of ranges. These ranges cannot be relaxed based on the + * requirements of the downstream devices. They represent the available windows from which + * resources can be allocated to the different devices under the domain. + * + * In order to identify the requirements of downstream devices, resource allocator walks in a + * DFS fashion. It gathers the requirements from leaf devices and propagates those back up + * to their upstream bridges until the requirements for all the downstream devices of the domain + * are gathered. This is referred to as pass 1 of resource allocator. + * + * Once the requirements for all the devices under the domain are gathered, resource allocator + * walks a second time to allocate resources to downstream devices as per the + * requirements. It always picks the biggest resource request as per the type (i/o and mem) to + * allocate space from its fixed window to the immediate downstream device of the domain. In + * order to accomplish best fit for the resources, a list of ranges is maintained by each + * resource type (i/o and mem). Domain does not differentiate between mem and prefmem. Since + * they are allocated space from the same window, the resource allocator at the domain level + * ensures that the biggest requirement is selected indepedent of the prefetch type. Once the + * resource allocation for all immediate downstream devices is complete at the domain level, + * resource allocator walks down the subtree for each downstream bridge to continue the + * allocation process at the bridge level. Since bridges have separate windows for i/o, mem and + * prefmem, best fit algorithm at bridge level looks for the biggest requirement considering + * prefmem resources separately from non-prefmem resources. This continues until resource + * allocation is performed for all downstream bridges in the domain sub-tree. This is referred + * to as pass 2 of resource allocator. + * + * Some rules that are followed by the resource allocator: + * - Allocate resource locations for every device as long as the requirements can be satisfied. + * - If a resource cannot be allocated any address space, then that resource needs to be + * properly updated to ensure that it does not incorrectly overlap some address space reserved + * for a different purpose. + * - Don't overlap with resources in fixed locations. + * - Don't overlap and follow the rules of bridges -- downstream devices of bridges should use + * parts of the address space allocated to the bridge. + */ +static void allocate_resources(const struct device *root) +{ + const struct device *child; + + if ((root == NULL) || (root->link_list == NULL)) + return; + + for (child = root->link_list->children; child; child = child->sibling) { + + if (child->path.type != DEVICE_PATH_DOMAIN) + continue; + + post_log_path(child); + + /* Pass 1 - Gather requirements. */ + printk(BIOS_INFO, "Resource allocator: %s - Pass 1 (gathering requirements)\n", + dev_path(child)); + compute_domain_resources(child); + + /* Pass 2 - Allocate resources as per gathered requirements. */ + printk(BIOS_INFO, "Resource allocator: %s - Pass 2 (allocating resources)\n", + dev_path(child)); + allocate_domain_resources(child); + } +} + /** * Configure devices on the devices tree. * @@ -996,9 +1040,7 @@ void dev_enumerate(void) */ void dev_configure(void) { - struct resource *res; const struct device *root; - const struct device *child; set_vga_bridge_bits(); @@ -1020,53 +1062,8 @@ void dev_configure(void) print_resource_tree(root, BIOS_SPEW, "After reading."); - /* Compute resources for all domains. */ - for (child = root->link_list->children; child; child = child->sibling) { - if (!(child->path.type == DEVICE_PATH_DOMAIN)) - continue; - post_log_path(child); - for (res = child->resource_list; res; res = res->next) { - if (res->flags & IORESOURCE_FIXED) - continue; - if (res->flags & IORESOURCE_MEM) { - compute_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_MEM); - continue; - } - if (res->flags & IORESOURCE_IO) { - compute_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_IO); - continue; - } - } - } + allocate_resources(root); - /* For all domains. */ - for (child = root->link_list->children; child; child=child->sibling) - if (child->path.type == DEVICE_PATH_DOMAIN) - avoid_fixed_resources(child); - - /* Store the computed resource allocations into device registers ... */ - printk(BIOS_INFO, "Setting resources...\n"); - for (child = root->link_list->children; child; child = child->sibling) { - if (!(child->path.type == DEVICE_PATH_DOMAIN)) - continue; - post_log_path(child); - for (res = child->resource_list; res; res = res->next) { - if (res->flags & IORESOURCE_FIXED) - continue; - if (res->flags & IORESOURCE_MEM) { - allocate_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_MEM); - continue; - } - if (res->flags & IORESOURCE_IO) { - allocate_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_IO); - continue; - } - } - } assign_resources(root->link_list); printk(BIOS_INFO, "Done setting resources.\n"); print_resource_tree(root, BIOS_SPEW, "After assigning values."); From 44ae0eacb82259243bf844a3fe5ad24a7821e997 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 31 Mar 2020 21:21:52 -0700 Subject: [PATCH 010/405] device: Enable resource allocation above 4G boundary This change adds support for allocating resources above the 4G boundary by making use of memranges for resource windows enabled in the previous CL. It adds a new resource flag IORESOURCE_ABOVE_4G which is used in the following ways: a) Downstream device resources can set this flag to indicate that they would like to have their resource allocation above the 4G boundary. These semantics will have to be enabled in the drivers managing the devices. It can also be extended to be enabled via devicetree. This flag is automatically propagated by the resource allocator from downstream devices to the upstream bridges in pass 1. It is done to ensure that the resource allocator has a global view of downstream requirements during pass 2 at domain level. b) Bridges have a single resource window for each of mem and prefmem resource types. Thus, if any downstream resource of the bridge requests allocation above 4G boundary, all the other downstream resources of the same type under the bridge will be allocated above 4G boundary. c) During pass 2, resource allocator at domain level splits IORESOURCE_MEM into two different memory ranges -- one for the window below 4G and other above 4G. Resource allocation happens separately for each of these windows. d) At the bridge level, there is no extra logic required since the resource will live entirely above or below the 4G boundary. Hence, all downstream devices of any bridge will fall within the window allocated to the bridge resource. To handle this case separately from that of domain, initializing of memranges for a bridge is done differently than the domain. Limitation: Resources of a given type at the bridge or downstream devices cannot live both above and below 4G boundary. Thus, if a bridge has some downstream resources requesting allocation for a given type above 4G boundary and other resources of the same type requesting allocation below 4G boundary, then all these resources of the same type get allocated above 4G boundary. BUG=b:149186922 TEST=Verified that resources get allocated above the 4G boundary correctly on volteer. Signed-off-by: Furquan Shaikh Change-Id: I7fb2a75cc280a307300d29ddabaebfc49175548f Reviewed-on: https://review.coreboot.org/c/coreboot/+/39487 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/device/device.c | 120 +++++++++++++++++++++++++++++++--- src/include/device/resource.h | 2 + 2 files changed, 113 insertions(+), 9 deletions(-) diff --git a/src/device/device.c b/src/device/device.c index 3ed64da34a..633346ede0 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -593,6 +593,19 @@ static void update_bridge_resource(const struct device *bridge, struct resource if (child_res->limit && (child_res->limit < bridge_res->limit)) bridge_res->limit = child_res->limit; + /* + * Propagate the downstream resource request to allocate above 4G boundary to + * upstream bridge resource. This ensures that during pass 2, the resource + * allocator at domain level has a global view of all the downstream device + * requirements and thus address space is allocated as per updated flags in the + * bridge resource. + * + * Since the bridge resource is a single window, all the downstream resources of + * this bridge resource will be allocated space above 4G boundary. + */ + if (child_res->flags & IORESOURCE_ABOVE_4G) + bridge_res->flags |= IORESOURCE_ABOVE_4G; + /* * Alignment value of 0 means that the child resource has no alignment * requirements and so the base value remains unchanged here. @@ -687,24 +700,98 @@ static void compute_domain_resources(const struct device *domain) } } -static void initialize_memranges(struct memranges *ranges, const struct resource *res, - unsigned long memrange_type) +/* + * If the resource base is set to the limit, then it means that the resource is invalid and + * hence cannot be used for allocation. + */ +static bool is_resource_invalid(const struct resource *res) +{ + return res->base == res->limit; +} + +/* + * This function initializes memranges for domain device. If the resource crosses 4G boundary, + * then this function splits it into two ranges -- one for the window below 4G and the other for + * the window above 4G. The latter range has IORESOURCE_ABOVE_4G flag set to satisfy resource + * requests from downstream devices for allocations above 4G. + */ +static void initialize_domain_memranges(struct memranges *ranges, const struct resource *res, + unsigned long memrange_type) { resource_t res_base; resource_t res_limit; + const resource_t limit_4g = 0xffffffff; memranges_init_empty(ranges, NULL, 0); - if (res == NULL) + if ((res == NULL) || is_resource_invalid(res)) return; res_base = res->base; res_limit = res->limit; - if (res_base == res_limit) + /* + * Split the resource into two separate ranges if it crosses the 4G boundary. Memrange + * type is set differently to ensure that memrange does not merge these two ranges. For + * the range above 4G boundary, given memrange type is ORed with IORESOURCE_ABOVE_4G. + */ + if (res_base <= limit_4g) { + + resource_t range_limit; + + /* Clip the resource limit at 4G boundary if necessary. */ + range_limit = MIN(res_limit, limit_4g); + memranges_insert(ranges, res_base, range_limit - res_base + 1, memrange_type); + + /* + * If the resource lies completely below the 4G boundary, nothing more needs to + * be done. + */ + if (res_limit <= limit_4g) + return; + + /* + * If the resource window crosses the 4G boundary, then update res_base to add + * another entry for the range above the boundary. + */ + res_base = limit_4g + 1; + } + + if (res_base > res_limit) return; - memranges_insert(ranges, res_base, res_limit - res_base + 1, memrange_type); + /* + * If resource lies completely above the 4G boundary or if the resource was clipped to + * add two separate ranges, the range above 4G boundary has the resource flag + * IORESOURCE_ABOVE_4G set. This allows domain to handle any downstream requests for + * resource allocation above 4G differently. + */ + memranges_insert(ranges, res_base, res_limit - res_base + 1, + memrange_type | IORESOURCE_ABOVE_4G); +} + +/* + * This function initializes memranges for bridge device. Unlike domain, bridge does not need to + * care about resource window crossing 4G boundary. This is handled by the resource allocator at + * domain level to ensure that all downstream bridges are allocated space either above or below + * 4G boundary as per the state of IORESOURCE_ABOVE_4G for the respective bridge resource. + * + * So, this function creates a single range of the entire resource window available for the + * bridge resource. Thus all downstream resources of the bridge for the given resource type get + * allocated space from the same window. If there is any downstream resource of the bridge which + * requests allocation above 4G, then all other downstream resources of the same type under the + * bridge get allocated above 4G. + */ +static void initialize_bridge_memranges(struct memranges *ranges, const struct resource *res, + unsigned long memrange_type) +{ + + memranges_init_empty(ranges, NULL, 0); + + if ((res == NULL) || is_resource_invalid(res)) + return; + + memranges_insert(ranges, res->base, res->limit - res->base + 1, memrange_type); } static void print_resource_ranges(const struct memranges *ranges) @@ -834,10 +921,12 @@ static void setup_resource_ranges(const struct device *dev, const struct resourc dev_path(dev), resource2str(res), res->base, res->size, res->align, res->gran, res->limit); - initialize_memranges(ranges, res, type); - - if (dev->path.type == DEVICE_PATH_DOMAIN) + if (dev->path.type == DEVICE_PATH_DOMAIN) { + initialize_domain_memranges(ranges, res, type); constrain_domain_resources(dev->link_list, ranges, type); + } else { + initialize_bridge_memranges(ranges, res, type); + } print_resource_ranges(ranges); } @@ -943,12 +1032,25 @@ static void allocate_domain_resources(const struct device *domain) * Domain does not distinguish between mem and prefmem resources. Thus, the resource * allocation at domain level considers mem and prefmem together when finding the best * fit based on the biggest resource requirement. + * + * However, resource requests for allocation above 4G boundary need to be handled + * separately if the domain resource window crosses this boundary. There is a single + * window for resource of type IORESOURCE_MEM. When creating memranges, this resource + * is split into two separate ranges -- one for the window below 4G boundary and other + * for the window above 4G boundary (with IORESOURCE_ABOVE_4G flag set). Thus, when + * allocating child resources, requests for below and above the 4G boundary are handled + * separately by setting the type_mask and type_match to allocate_child_resources() + * accordingly. */ res = find_domain_resource(domain, IORESOURCE_MEM); if (res) { setup_resource_ranges(domain, res, IORESOURCE_MEM, &ranges); - allocate_child_resources(domain->link_list, &ranges, IORESOURCE_TYPE_MASK, + allocate_child_resources(domain->link_list, &ranges, + IORESOURCE_TYPE_MASK | IORESOURCE_ABOVE_4G, IORESOURCE_MEM); + allocate_child_resources(domain->link_list, &ranges, + IORESOURCE_TYPE_MASK | IORESOURCE_ABOVE_4G, + IORESOURCE_MEM | IORESOURCE_ABOVE_4G); cleanup_resource_ranges(domain, &ranges, res); } diff --git a/src/include/device/resource.h b/src/include/device/resource.h index 1d04e9a1c8..4ebdfa3d47 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -24,6 +24,8 @@ #define IORESOURCE_SUBTRACTIVE 0x00040000 /* The IO resource has a bus below it. */ #define IORESOURCE_BRIDGE 0x00080000 +/* This is a request to allocate resource about 4G boundary. */ +#define IORESOURCE_ABOVE_4G 0x00100000 /* The resource needs to be reserved in the coreboot table */ #define IORESOURCE_RESERVE 0x10000000 /* The IO resource assignment has been stored in the device */ From 871baf2230dc1e0ed2becfd8526e00d5367618b3 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 12 Mar 2020 17:51:24 -0700 Subject: [PATCH 011/405] pci_device: Extend PCI domain limit to 64-bit This change updates the resource limit for PCI domain to allow resource allocation above 4G boundary. The resource limit is set to the highest physical address for the CPU. BUG=b:149186922 Signed-off-by: Furquan Shaikh Change-Id: Idfcc9a390d309886ee2b7880b29502c740e6578e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39488 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/device/pci_device.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 9036f53f3b..2c08ebc72e 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -433,7 +434,7 @@ void pci_domain_read_resources(struct device *dev) /* Initialize the system-wide memory resources constraints. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->limit = 0xffffffffULL; + res->limit = (1ULL << cpu_phys_address_size()) - 1; res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; } From dcbf6454b6d2d9b3627a14126ef20ed4b9c7d954 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 12 Mar 2020 17:58:13 -0700 Subject: [PATCH 012/405] pciexp_device: Add option to allocate prefetch memory above 4G boundary This change adds a Kconfig option to request allocation of prefetch memory for hotplug devices above the 4G boundary. In order to select this option by default and still allow users to disable this if required, another option is added to request allocation of prefetch memory below 4G boundary which defaults to n but can be overriden by mainboards. Without this change, if the number of pciexp bridges supporting hot-plug is more than 4 or if the reserved prefetch memory size for hot-plug cases was increased, then the resource allocator would fail to satisfy the resource requirement below 4G boundary. BUG=b:149186922 TEST=Enabled resource allocation above 4G for prefetch memory on volteer and verified that it gets allocated above 4G boundary. Signed-off-by: Furquan Shaikh Change-Id: I061d935eef9fcda352230b03b5cf14e467924e50 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39489 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/device/Kconfig | 15 +++++++++++++++ src/device/pciexp_device.c | 10 +++++++--- 2 files changed, 22 insertions(+), 3 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index 6096a38b6f..2976a61a8f 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -585,6 +585,21 @@ config PCIEXP_HOTPLUG_PREFETCH_MEM child devices. This size should be page-aligned. The default is 256 MiB. +config PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G + bool + default y if !PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G + default n + help + This enables prefetch memory allocation above 4G boundary for the + hotplug resources. + +config PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G + bool "PCI Express Hotplug Prefetch Memory Allocation below 4G boundary" + default n + help + This enables prefetch memory allocation below 4G boundary for the + hotplug resources. + config PCIEXP_HOTPLUG_IO hex "PCI Express Hotplug I/O Space" default 0x2000 diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 1189207539..f04d865152 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -512,7 +512,7 @@ static void pciexp_hotplug_dummy_read_resources(struct device *dev) { struct resource *resource; - // Add extra memory space + /* Add extra memory space */ resource = new_resource(dev, 0x10); resource->size = CONFIG_PCIEXP_HOTPLUG_MEM; resource->align = 12; @@ -520,7 +520,7 @@ static void pciexp_hotplug_dummy_read_resources(struct device *dev) resource->limit = 0xffffffff; resource->flags |= IORESOURCE_MEM; - // Add extra prefetchable memory space + /* Add extra prefetchable memory space */ resource = new_resource(dev, 0x14); resource->size = CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM; resource->align = 12; @@ -528,7 +528,11 @@ static void pciexp_hotplug_dummy_read_resources(struct device *dev) resource->limit = 0xffffffffffffffff; resource->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; - // Add extra I/O space + /* Set resource flag requesting allocation above 4G boundary. */ + if (CONFIG(PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G)) + resource->flags |= IORESOURCE_ABOVE_4G; + + /* Add extra I/O space */ resource = new_resource(dev, 0x18); resource->size = CONFIG_PCIEXP_HOTPLUG_IO; resource->align = 12; From 56875113b7472d806655c7871e013eecefba70c5 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 4 May 2020 00:23:41 +0200 Subject: [PATCH 013/405] Doc/mb/lenovo: Fix broken link Change-Id: Iafa7e0f3734042e35e8b4ea440baf1c3c3d147e9 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41017 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Rudolph --- Documentation/mainboard/lenovo/Sandy_Bridge_series.md | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/mainboard/lenovo/Sandy_Bridge_series.md b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md index 37a75b9799..0bf118ff35 100644 --- a/Documentation/mainboard/lenovo/Sandy_Bridge_series.md +++ b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md @@ -67,3 +67,4 @@ the remaining space for the `bios` partition. [me_cleaner]: ../../northbridge/intel/sandybridge/me_cleaner.md [external programmer]: ../../flash_tutorial/index.md +[flashing tutorial]: ../../flash_tutorial/index.md From 08c524c0b7266fd9f51e0d412bdac2b4d14c09e0 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 9 May 2020 13:10:30 -0700 Subject: [PATCH 014/405] soc/amd/common/block/spi: Add support for common SPI configuration This change adds support for following SPI configuration functions to common block SPI driver and exposes them to be used by SoC: 1. fch_spi_early_init(): Sets up SPI ROM base, enables SPI ROM, enables prefetching, disables 4dw burst mode and sets SPI speed and mode. 2. fch_spi_config_modes(): This allows SoC to configure SPI speed and mode. It uses SPI settings from soc_amd_common_config to configure the speed and mode. These functions expect SoC to include soc_amd_common_config in SoC chip config and mainboard to configure these settings in device tree. Signed-off-by: Furquan Shaikh Change-Id: Ia4f231bab69e8450005dd6abe7a8e014d5eb7261 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41248 Reviewed-by: Aaron Durbin Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- .../amd/common/block/include/amdblocks/chip.h | 12 +++ .../amd/common/block/include/amdblocks/spi.h | 97 +++++++++++++++++++ src/soc/amd/common/block/spi/Makefile.inc | 9 ++ src/soc/amd/common/block/spi/fch_spi.c | 86 ++++++++++++++++ src/soc/amd/common/block/spi/fch_spi_ctrl.c | 2 +- 5 files changed, 205 insertions(+), 1 deletion(-) create mode 100644 src/soc/amd/common/block/include/amdblocks/spi.h create mode 100644 src/soc/amd/common/block/spi/fch_spi.c diff --git a/src/soc/amd/common/block/include/amdblocks/chip.h b/src/soc/amd/common/block/include/amdblocks/chip.h index 26ad26a6b1..6e3c973c97 100644 --- a/src/soc/amd/common/block/include/amdblocks/chip.h +++ b/src/soc/amd/common/block/include/amdblocks/chip.h @@ -4,7 +4,19 @@ #ifndef __AMDBLOCKS_CHIP_H__ #define __AMDBLOCKS_CHIP_H__ +#include + struct soc_amd_common_config { + /* + * SPI configuration + * Default values if not overridden by mainboard: + * Read mode - Normal 33MHz + * Normal speed - 66MHz + * Fast speed - 66MHz + * Alt speed - 66MHz + * TPM speed - 66MHz + */ + struct spi_config spi_config; }; /* diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h new file mode 100644 index 0000000000..d901f7e020 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __AMDBLOCKS_SPI_H__ +#define __AMDBLOCKS_SPI_H__ + +#define SPI_CNTRL0 0x00 +#define SPI_BUSY BIT(31) + +enum spi_read_mode { + SPI_READ_MODE_NORMAL33M = 0, + /* 1 is reserved. */ + SPI_READ_MODE_DUAL112 = 2, + SPI_READ_MODE_QUAD114 = 3, + SPI_READ_MODE_DUAL122 = 4, + SPI_READ_MODE_QUAD144 = 5, + SPI_READ_MODE_NORMAL66M = 6, + SPI_READ_MODE_FAST_READ = 7, +}; +/* + * SPI read mode is split into bits 18, 29, 30 such that [30:29:18] correspond to bits [2:0] for + * SpiReadMode. + */ +#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) +#define SPI_READ_MODE_UPPER_BITS(x) ((((x) >> 1) & 0x3) << 29) +#define SPI_READ_MODE_LOWER_BITS(x) (((x) & 0x1) << 18) +#define SPI_READ_MODE(x) (SPI_READ_MODE_UPPER_BITS(x) | \ + SPI_READ_MODE_LOWER_BITS(x)) +#define SPI_ACCESS_MAC_ROM_EN BIT(22) + +#define SPI100_ENABLE 0x20 +#define SPI_USE_SPI100 BIT(0) + +/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */ +#define SPI100_SPEED_CONFIG 0x22 +enum spi100_speed { + SPI_SPEED_66M = 0, + SPI_SPEED_33M = 1, + SPI_SPEED_22M = 2, + SPI_SPEED_16M = 3, + SPI_SPEED_100M = 4, + SPI_SPEED_800K = 5, +}; + +#define SPI_SPEED_MASK 0xf +#define SPI_SPEED_MODE(x, shift) (((x) & SPI_SPEED_MASK) << shift) +#define SPI_NORM_SPEED(x) SPI_SPEED_MODE(x, 12) +#define SPI_FAST_SPEED(x) SPI_SPEED_MODE(x, 8) +#define SPI_ALT_SPEED(x) SPI_SPEED_MODE(x, 4) +#define SPI_TPM_SPEED(x) SPI_SPEED_MODE(x, 0) + +#define SPI_SPEED_CFG(n, f, a, t) (SPI_NORM_SPEED(n) | SPI_FAST_SPEED(f) | \ + SPI_ALT_SPEED(a) | SPI_TPM_SPEED(t)) + +#define SPI100_HOST_PREF_CONFIG 0x2c +#define SPI_RD4DW_EN_HOST BIT(15) + +#define SPI_FIFO 0x80 +#define SPI_FIFO_DEPTH (0xc7 - SPI_FIFO) + +struct spi_config { + /* + * Default values if not overridden by mainboard: + * Read mode - Normal 33MHz + * Normal speed - 66MHz + * Fast speed - 66MHz + * Alt speed - 66MHz + * TPM speed - 66MHz + */ + enum spi_read_mode read_mode; + enum spi100_speed normal_speed; + enum spi100_speed fast_speed; + enum spi100_speed altio_speed; + enum spi100_speed tpm_speed; +}; + +/* + * Perform early SPI initialization: + * 1. Sets SPI ROM base and enables SPI ROM + * 2. Enables SPI ROM prefetching + * 3. Disables 4dw burst + * 4. Configures SPI speed and read mode. + * + * This function expects SoC to include soc_amd_common_config in chip SoC config and uses + * settings from mainboard devicetree to configure speed and read mode. + */ +void fch_spi_early_init(void); + +/* + * Configure SPI speed and read mode. + * + * This function expects SoC to include soc_amd_common_config in chip SoC config and uses + * settings from mainboard devicetree to configure speed and read mode. + */ +void fch_spi_config_modes(void); + +#endif /* __AMDBLOCKS_SPI_H__ */ diff --git a/src/soc/amd/common/block/spi/Makefile.inc b/src/soc/amd/common/block/spi/Makefile.inc index 0e706ef3cb..3d541b7052 100644 --- a/src/soc/amd/common/block/spi/Makefile.inc +++ b/src/soc/amd/common/block/spi/Makefile.inc @@ -9,4 +9,13 @@ ifeq ($(CONFIG_SPI_FLASH_SMM),y) smm-y += fch_spi_ctrl.c endif +bootblock-y += fch_spi.c +romstage-y += fch_spi.c +postcar-y += fch_spi.c +ramstage-y += fch_spi.c +verstage-y += fch_spi.c +ifeq ($(CONFIG_SPI_FLASH_SMM),y) +smm-y += fch_spi.c +endif + endif diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c new file mode 100644 index 0000000000..950eee2947 --- /dev/null +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include +#include + +static uintptr_t fch_spi_base(void) +{ + uintptr_t base; + + base = lpc_get_spibase(); + + if (base) + return base; + + lpc_set_spibase(SPI_BASE_ADDRESS); + lpc_enable_spi_rom(SPI_ROM_ENABLE); + + return SPI_BASE_ADDRESS; +} + +static void fch_spi_set_spi100(int norm, int fast, int alt, int tpm) +{ + uintptr_t base = fch_spi_base(); + + write16((void *)(base + SPI100_SPEED_CONFIG), SPI_SPEED_CFG(norm, fast, alt, tpm)); + write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100); +} + +static void fch_spi_disable_4dw_burst(void) +{ + uintptr_t base = fch_spi_base(); + uint16_t val = read16((void *)(base + SPI100_HOST_PREF_CONFIG)); + + write16((void *)(base + SPI100_HOST_PREF_CONFIG), val & ~SPI_RD4DW_EN_HOST); +} + +static void fch_spi_set_read_mode(u32 mode) +{ + uintptr_t base = fch_spi_base(); + uint32_t val = read32((void *)(base + SPI_CNTRL0)) & ~SPI_READ_MODE_MASK; + + write32((void *)(base + SPI_CNTRL0), val | SPI_READ_MODE(mode)); +} + +static void fch_spi_config_mb_modes(void) +{ + const struct soc_amd_common_config *cfg = soc_get_common_config(); + + if (!cfg) + die("Common config structure is NULL!\n"); + + const struct spi_config *spi_cfg = &cfg->spi_config; + + fch_spi_set_read_mode(spi_cfg->read_mode); + fch_spi_set_spi100(spi_cfg->normal_speed, spi_cfg->fast_speed, + spi_cfg->altio_speed, spi_cfg->tpm_speed); +} + +static void fch_spi_config_em100_modes(void) +{ + fch_spi_set_read_mode(SPI_READ_MODE_NORMAL33M); + fch_spi_set_spi100(SPI_SPEED_16M, SPI_SPEED_16M, SPI_SPEED_16M, SPI_SPEED_16M); +} + +void fch_spi_config_modes(void) +{ + if (CONFIG(EM100)) + fch_spi_config_em100_modes(); + else + fch_spi_config_mb_modes(); +} + +void fch_spi_early_init(void) +{ + lpc_set_spibase(SPI_BASE_ADDRESS); + lpc_enable_spi_rom(SPI_ROM_ENABLE); + lpc_enable_spi_prefetch(); + fch_spi_disable_4dw_burst(); + fch_spi_config_modes(); +} diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index c0751a3f33..b048f1cbf7 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -2,9 +2,9 @@ #include #include -#include #include #include +#include #include #include #include From 033aa0dfc3e6c2478b6e21a75c751293ddeb6d35 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 9 May 2020 14:26:37 -0700 Subject: [PATCH 015/405] soc/amd/picasso: Add support for using common SoC configuration This change adds support for using common SoC configuration by adding soc_amd_common_config to soc_amd_picasso_config and helper function to return pointer to the structure to amd common block code. Change-Id: I8bd4eac3b19c9ded2d9a3e95ac077f014730f9d1 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41249 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Aaron Durbin --- src/soc/amd/picasso/Makefile.inc | 5 +++++ src/soc/amd/picasso/chip.h | 2 ++ src/soc/amd/picasso/config.c | 12 ++++++++++++ 3 files changed, 19 insertions(+) create mode 100644 src/soc/amd/picasso/config.c diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 0e5466161b..43bb32e7f0 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -18,6 +18,7 @@ bootblock-$(CONFIG_PICASSO_UART) += uart.c bootblock-y += tsc_freq.c bootblock-y += gpio.c bootblock-y += smi_util.c +bootblock-y += config.c romstage-y += i2c.c romstage-y += romstage.c @@ -31,10 +32,12 @@ romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c romstage-y += soc_util.c romstage-y += psp.c romstage-y += mtrr.c +romstage-y += config.c verstage-y += gpio.c verstage-y += i2c.c verstage-y += pmutil.c +verstage-y += config.c verstage-$(CONFIG_PICASSO_UART) += uart.c verstage-y += tsc_freq.c @@ -59,6 +62,7 @@ ramstage-y += finalize.c ramstage-y += soc_util.c ramstage-y += psp.c ramstage-y += fsp_params.c +ramstage-y += config.c all-y += reset.c @@ -68,6 +72,7 @@ smm-y += tsc_freq.c smm-$(CONFIG_DEBUG_SMI) += uart.c smm-y += gpio.c smm-y += psp.c +smm-y += config.c CPPFLAGS_common += -I$(src)/soc/amd/picasso CPPFLAGS_common += -I$(src)/soc/amd/picasso/include diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 9b77e84736..2b9ef3c37a 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -13,6 +14,7 @@ #include struct soc_amd_picasso_config { + struct soc_amd_common_config common_config; /* * If sb_reset_i2c_slaves() is called, this devicetree register * defines which I2C SCL will be toggled 9 times at 100 KHz. diff --git a/src/soc/amd/picasso/config.c b/src/soc/amd/picasso/config.c new file mode 100644 index 0000000000..5d52e7affa --- /dev/null +++ b/src/soc/amd/picasso/config.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include "chip.h" + +const struct soc_amd_common_config *soc_get_common_config() +{ + const struct soc_amd_picasso_config *cfg = config_of_soc(); + return &cfg->common_config; +} From 13b8158672d7a6509633d77e753e865db2fe09ef Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 9 May 2020 17:24:42 -0700 Subject: [PATCH 016/405] soc/amd/picasso: Use SPI configuration support from common block SPI driver This change switches to using the common block SPI driver for performing early SPI initialization and for re-configuring SPI speed and mode after FSP-S has run. Signed-off-by: Furquan Shaikh Change-Id: Ia3186ce59b66c2f44522a94fa52659b4942649b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41250 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Raul Rangel --- src/soc/amd/picasso/chip.h | 15 ---- src/soc/amd/picasso/include/soc/southbridge.h | 58 --------------- src/soc/amd/picasso/southbridge.c | 74 +------------------ 3 files changed, 2 insertions(+), 145 deletions(-) diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 2b9ef3c37a..8d4e0d3875 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -73,21 +73,6 @@ struct soc_amd_picasso_config { uint8_t min_soc_vid_offset; uint8_t aclk_dpm0_freq_400MHz; - /* - * SPI config - * Default values if not overridden by mainboard: - * Read mode - Normal 33MHz - * Normal speed - 66MHz - * Fast speed - 66MHz - * Alt speed - 66MHz - * TPM speed - 66MHz - */ - enum spi_read_mode spi_read_mode; - enum spi100_speed spi_normal_speed; - enum spi100_speed spi_fast_speed; - enum spi100_speed spi_altio_speed; - enum spi100_speed spi_tpm_speed; - enum { SD_EMMC_DISABLE, SD_EMMC_SD_LOW_SPEED, diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 602647660a..5bae754cf6 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -240,61 +240,6 @@ #define SATA_CAPABILITIES_REG 0xfc #define SATA_CAPABILITY_SPM BIT(12) -#define SPI_CNTRL0 0x00 -#define SPI_BUSY BIT(31) -enum spi_read_mode { - SPI_READ_MODE_NORMAL33M = 0, - /* 1 is reserved. */ - SPI_READ_MODE_DUAL112 = 2, - SPI_READ_MODE_QUAD114 = 3, - SPI_READ_MODE_DUAL122 = 4, - SPI_READ_MODE_QUAD144 = 5, - SPI_READ_MODE_NORMAL66M = 6, - SPI_READ_MODE_FAST_READ = 7, -}; -/* - * SPI read mode is split into bits 18, 29, 30 such that [30:29:18] correspond to bits [2:0] for - * SpiReadMode. - */ -#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) -#define SPI_READ_MODE_UPPER_BITS(x) ((((x) >> 1) & 0x3) << 29) -#define SPI_READ_MODE_LOWER_BITS(x) (((x) & 0x1) << 18) -#define SPI_READ_MODE(x) (SPI_READ_MODE_UPPER_BITS(x) | \ - SPI_READ_MODE_LOWER_BITS(x)) -#define SPI_ACCESS_MAC_ROM_EN BIT(22) -#define SPI_FIFO_PTR_CLR BIT(20) -#define SPI_ARB_ENABLE BIT(19) -#define EXEC_OPCODE BIT(16) -#define SPI_FIFO 0x80 -#define SPI_FIFO_DEPTH (0xc7 - SPI_FIFO) - -#define SPI100_ENABLE 0x20 -#define SPI_USE_SPI100 BIT(0) - -/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */ -#define SPI100_SPEED_CONFIG 0x22 -enum spi100_speed { - SPI_SPEED_66M = 0, - SPI_SPEED_33M = 1, - SPI_SPEED_22M = 2, - SPI_SPEED_16M = 3, - SPI_SPEED_100M = 4, - SPI_SPEED_800K = 5, -}; - -#define SPI_SPEED_MASK 0xf -#define SPI_SPEED_MODE(x, shift) (((x) & SPI_SPEED_MASK) << (shift)) -#define SPI_NORM_SPEED(x) SPI_SPEED_MODE(x, 12) -#define SPI_FAST_SPEED(x) SPI_SPEED_MODE(x, 8) -#define SPI_ALT_SPEED(x) SPI_SPEED_MODE(x, 4) -#define SPI_TPM_SPEED(x) SPI_SPEED_MODE(x, 0) - -#define SPI_SPEED_CFG(n, f, a, t) (SPI_NORM_SPEED(n) | SPI_FAST_SPEED(f) | \ - SPI_ALT_SPEED(a) | SPI_TPM_SPEED(t)) - -#define SPI100_HOST_PREF_CONFIG 0x2c -#define SPI_RD4DW_EN_HOST BIT(15) - /* IO 0xcf9 - Reset control port*/ #define FULL_RST BIT(3) #define RST_CMD BIT(2) @@ -329,12 +274,9 @@ struct soc_power_reg { void enable_aoac_devices(void); void sb_clk_output_48Mhz(void); -void sb_disable_4dw_burst(void); void sb_enable(struct device *dev); void southbridge_final(void *chip_info); void southbridge_init(void *chip_info); -void sb_read_mode(u32 mode); -void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); void fch_pre_init(void); void fch_early_init(void); void set_uart_config(int idx); diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 6308953fc6..c871ec9f58 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -197,77 +198,6 @@ void sb_clk_output_48Mhz(void) misc_write32(MISC_CLK_CNTL1, ctrl); } -static uintptr_t sb_init_spi_base(void) -{ - uintptr_t base; - - /* Make sure the base address is predictable */ - base = lpc_get_spibase(); - - if (base) - return base; - - lpc_set_spibase(SPI_BASE_ADDRESS); - lpc_enable_spi_rom(SPI_ROM_ENABLE); - - return SPI_BASE_ADDRESS; -} - -void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) -{ - uintptr_t base = sb_init_spi_base(); - - write16((void *)(base + SPI100_SPEED_CONFIG), SPI_SPEED_CFG(norm, fast, alt, tpm)); - write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100); -} - -void sb_disable_4dw_burst(void) -{ - uintptr_t base = sb_init_spi_base(); - write16((void *)(base + SPI100_HOST_PREF_CONFIG), - read16((void *)(base + SPI100_HOST_PREF_CONFIG)) - & ~SPI_RD4DW_EN_HOST); -} - -void sb_read_mode(u32 mode) -{ - uintptr_t base = sb_init_spi_base(); - uint32_t val = (read32((void *)(base + SPI_CNTRL0)) & ~SPI_READ_MODE_MASK); - - write32((void *)(base + SPI_CNTRL0), val | SPI_READ_MODE(mode)); -} - -static void sb_spi_config_mb_modes(void) -{ - const struct soc_amd_picasso_config *cfg = config_of_soc(); - - sb_read_mode(cfg->spi_read_mode); - sb_set_spi100(cfg->spi_normal_speed, cfg->spi_fast_speed, cfg->spi_altio_speed, - cfg->spi_tpm_speed); -} - -static void sb_spi_config_em100_modes(void) -{ - sb_read_mode(SPI_READ_MODE_NORMAL33M); - sb_set_spi100(SPI_SPEED_16M, SPI_SPEED_16M, SPI_SPEED_16M, SPI_SPEED_16M); -} - -static void sb_spi_config_modes(void) -{ - if (CONFIG(EM100)) - sb_spi_config_em100_modes(); - else - sb_spi_config_mb_modes(); -} - -static void sb_spi_init(void) -{ - lpc_enable_spi_prefetch(); - sb_init_spi_base(); - sb_disable_4dw_burst(); - sb_spi_config_modes(); -} - static void fch_smbus_init(void) { /* 400 kHz smbus speed. */ @@ -293,7 +223,7 @@ void fch_pre_init(void) if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80) && CONFIG(PICASSO_LPC_IOMUX)) lpc_enable_port80(); - sb_spi_init(); + fch_spi_early_init(); enable_acpimmio_decode_pm04(); fch_smbus_init(); sb_enable_cf9_io(); From ca892fe44b287df429215796f85e197f8bf0a968 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 9 May 2020 14:46:09 -0700 Subject: [PATCH 017/405] soc/amd/common/block/lpc: Set LPC_IO_PORT_DECODE_ENABLE to 0 when disabling decodes This change sets LPC_IO_PORT_DECODE_ENABLE to 0 as part of lpc_disable_decodes() to ensure that the I/O port decodes are also disabled. Signed-off-by: Furquan Shaikh Change-Id: I1474f561997f2ee1231bd0fcaab4d4d4e98ff923 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41251 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Aaron Durbin --- src/soc/amd/common/block/lpc/lpc_util.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index c9786e7aa2..2c47a8549a 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -182,6 +182,7 @@ void lpc_disable_decodes(void) reg = pci_read_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); reg &= LPC_SYNC_TIMEOUT_COUNT_MASK | LPC_SYNC_TIMEOUT_COUNT_ENABLE; pci_write_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, reg); + pci_write_config32(_LPCB_DEV, LPC_IO_PORT_DECODE_ENABLE, 0); /* D14F3x48 enables ranges configured in additional registers */ pci_write_config32(_LPCB_DEV, LPC_MEM_PORT1, 0); From 62d13437e25721016f991a7314386a1e6bbbe778 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 4 May 2020 22:50:57 -0700 Subject: [PATCH 018/405] espi: Add definitions for eSPI slave registers This change adds eSPI slave register definitions as per Enhanced Serial Peripheral Interface Base Specification (document # 327432-004 Revision 1.0) Chapter 7 "Slave Registers". BUG=b:153675913 Change-Id: Icee53817476b7d50ff26e64bbc2c3f5afb19a7cd Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41071 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Felix Held --- src/include/espi.h | 192 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 192 insertions(+) create mode 100644 src/include/espi.h diff --git a/src/include/espi.h b/src/include/espi.h new file mode 100644 index 0000000000..b1a51d9584 --- /dev/null +++ b/src/include/espi.h @@ -0,0 +1,192 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __ESPI_H__ +#define __ESPI_H__ + +/* ESPI Slave Registers (Document # 327432-004 Revision 1.0 Chapter 7) */ + +#define ESPI_SLAVE_DEVICE_ID 0x04 +#define ESPI_SLAVE_VERSION_ID_SHIFT 0 +#define ESPI_SLAVE_VERSION_ID_MASK 0xf + +#define ESPI_SLAVE_GENERAL_CFG 0x08 +#define ESPI_SLAVE_CRC_ENABLE (1 << 31) +#define ESPI_SLAVE_CRC_DISABLE (0 << 31) +#define ESPI_SLAVE_RESP_MOD_ENABLE (1 << 30) +#define ESPI_SLAVE_RESP_MOD_DISABLE (0 << 30) +#define ESPI_SLAVE_ALERT_MODE_PIN (1 << 28) +#define ESPI_SLAVE_ALERT_MODE_IO1 (0 << 28) +#define ESPI_SLAVE_IO_MODE_SEL_SHIFT 26 +#define ESPI_SLAVE_IO_MODE_SEL_MASK (0x3 << ESPI_SLAVE_IO_MODE_SEL_SHIFT) +#define ESPI_SLAVE_IO_MODE_SEL_VAL(x) ((x) << ESPI_SLAVE_IO_MODE_SEL_SHIFT) +#define ESPI_SLAVE_IO_MODE_SEL_SINGLE ESPI_SLAVE_IO_MODE_SEL_VAL(0) +#define ESPI_SLAVE_IO_MODE_SEL_DUAL ESPI_SLAVE_IO_MODE_SEL_VAL(1) +#define ESPI_SLAVE_IO_MODE_SEL_QUAD ESPI_SLAVE_IO_MODE_SEL_VAL(2) +#define ESPI_SLAVE_IO_MODE_SUPP_SHIFT 24 +#define ESPI_SLAVE_IO_MODE_SUPP_MASK (0x3 << ESPI_SLAVE_IO_MODE_SUPP_SHIFT) +#define ESPI_SLAVE_IO_MODE_SUPP_VAL(x) ((x) << ESPI_SLAVE_IO_MODE_SUPP_SHIFT) +#define ESPI_SLAVE_IO_MODE_SUPP_SINGLE_ONLY ESPI_SLAVE_IO_MODE_SUPP_VAL(0) +#define ESPI_SLAVE_IO_MODE_SUPP_SINGLE_DUAL ESPI_SLAVE_IO_MODE_SUPP_VAL(1) +#define ESPI_SLAVE_IO_MODE_SUPP_SINGLE_QUAD ESPI_SLAVE_IO_MODE_SUPP_VAL(2) +#define ESPI_SLAVE_IO_MODE_SUPP_SINGLE_DUAL_QUAD ESPI_SLAVE_IO_MODE_SUPP_VAL(3) +#define ESPI_SLAVE_OPEN_DRAIN_ALERT_SEL (1 << 23) +#define ESPI_SLAVE_PUSH_PULL_ALERT_SEL (0 << 23) +#define ESPI_SLAVE_OP_FREQ_SEL_SHIFT 20 +#define ESPI_SLAVE_OP_FREQ_SEL_MASK (0x7 << ESPI_SLAVE_OP_FREQ_SEL_SHIFT) +#define ESPI_SLAVE_OP_FREQ_SEL_VAL(x) ((x) << ESPI_SLAVE_OP_FREQ_SEL_SHIFT) +#define ESPI_SLAVE_OP_FREQ_SEL_20_MHZ ESPI_SLAVE_OP_FREQ_SEL_VAL(0) +#define ESPI_SLAVE_OP_FREQ_SEL_25_MHZ ESPI_SLAVE_OP_FREQ_SEL_VAL(1) +#define ESPI_SLAVE_OP_FREQ_SEL_33_MHZ ESPI_SLAVE_OP_FREQ_SEL_VAL(2) +#define ESPI_SLAVE_OP_FREQ_SEL_50_MHZ ESPI_SLAVE_OP_FREQ_SEL_VAL(3) +#define ESPI_SLAVE_OP_FREQ_SEL_66_MHZ ESPI_SLAVE_OP_FREQ_SEL_VAL(4) +#define ESPI_SLAVE_OPEN_DRAIN_ALERT_SUPP (1 << 19) +#define ESPI_SLAVE_OP_FREQ_SUPP_SHIFT 16 +#define ESPI_SLAVE_OP_FREQ_SUPP_MASK (0x7 << ESPI_SLAVE_OP_FREQ_SUPP_SHIFT) +#define ESPI_SLAVE_OP_FREQ_SUPP_VAL(x) ((x) << ESPI_SLAVE_OP_FREQ_SUPP_SHIFT) +#define ESPI_SLAVE_OP_FREQ_SUPP_20_MHZ ESPI_SLAVE_OP_FREQ_SUPP_VAL(0) +#define ESPI_SLAVE_OP_FREQ_SUPP_25_MHZ ESPI_SLAVE_OP_FREQ_SUPP_VAL(1) +#define ESPI_SLAVE_OP_FREQ_SUPP_33_MHZ ESPI_SLAVE_OP_FREQ_SUPP_VAL(2) +#define ESPI_SLAVE_OP_FREQ_SUPP_50_MHZ ESPI_SLAVE_OP_FREQ_SUPP_VAL(3) +#define ESPI_SLAVE_OP_FREQ_SUPP_66_MHZ ESPI_SLAVE_OP_FREQ_SUPP_VAL(4) +#define ESPI_SLAVE_MAX_WAIT_SHIFT 12 +#define ESPI_SLAVE_MAX_WAIT_MASK (0xf << ESPI_SLAVE_MAX_WAIT_SHIFT) +#define ESPI_SLAVE_MAX_WAIT_STATE(x) \ + (((x) << ESPI_SLAVE_MAX_WAIT_SHIFT) & ESPI_MAX_WAIT_MASK) +#define ESPI_SLAVE_FLASH_CH_SUPP (1 << 3) +#define ESPI_SLAVE_OOB_CH_SUPP (1 << 2) +#define ESPI_SLAVE_VW_CH_SUPP (1 << 1) +#define ESPI_SLAVE_PERIPH_CH_SUPP (1 << 0) + +#define ESPI_SLAVE_PERIPH_CFG 0x10 +#define ESPI_SLAVE_PERIPH_MAX_READ_SIZE_SHIFT 12 +#define ESPI_SLAVE_PERIPH_MAX_READ_SIZE_MASK \ + (0x7 << ESPI_SLAVE_PERIPH_MAX_READ_SIZE_SHIFT) +#define ESPI_SLAVE_PERIPH_MAX_READ_SIZE_VAL(x) \ + ((x) << ESPI_SLAVE_PERIPH_MAX_READ_SIZE_SHIFT) +#define ESPI_SLAVE_PERIPH_MAX_READ_64B ESPI_SLAVE_PERIPH_MAX_READ_SIZE_VAL(1) +#define ESPI_SLAVE_PERIPH_MAX_READ_128B ESPI_SLAVE_PERIPH_MAX_READ_SIZE_VAL(2) +#define ESPI_SLAVE_PERIPH_MAX_READ_256B ESPI_SLAVE_PERIPH_MAX_READ_SIZE_VAL(3) +#define ESPI_SLAVE_PERIPH_MAX_READ_512B ESPI_SLAVE_PERIPH_MAX_READ_SIZE_VAL(4) +#define ESPI_SLAVE_PERIPH_MAX_READ_1024B ESPI_SLAVE_PERIPH_MAX_READ_SIZE_VAL(5) +#define ESPI_SLAVE_PERIPH_MAX_READ_2048B ESPI_SLAVE_PERIPH_MAX_READ_SIZE_VAL(6) +#define ESPI_SLAVE_PERIPH_MAX_READ_4096B ESPI_SLAVE_PERIPH_MAX_READ_SIZE_VAL(7) +#define ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SEL_SHIFT 8 +#define ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SEL_MASK \ + (0x7 << ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SEL_SHIFT) +#define ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SEL_VAL(x) \ + ((x) << ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SEL_SHIFT) +#define ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SEL_64B \ + ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SEL_VAL(1) +#define ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SEL_128B \ + ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SEL_VAL(2) +#define ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SEL_256B \ + ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SEL_VAL(3) +#define ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SUPP_SHIFT 4 +#define ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SUPP_MASK \ + (0x7 << ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SUPP_SHIFT) +#define ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SUPP_VAL(x) \ + ((x) << ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SUPP_SHIFT) +#define ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SUPP_64B \ + ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SUPP_VAL(1) +#define ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SUPP_128B \ + ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SUPP_VAL(2) +#define ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SUPP_256B \ + ESPI_SLAVE_PERIPH_MAX_PAYLOAD_SIZE_SUPP_VAL(3) +#define ESPI_SLAVE_PERIPH_BUS_MASTER_ENABLE (1 << 2) + +#define ESPI_SLAVE_VW_CFG 0x20 +#define ESPI_SLAVE_VW_COUNT_SEL_SHIFT 16 +#define ESPI_SLAVE_VW_COUNT_SEL_MASK (0x3f << ESPI_SLAVE_VW_COUNT_SEL_SHIFT) +/* 0-based field. Value of 0 indicates 1 virtual wire selected. */ +#define ESPI_SLAVE_VW_COUNT_SEL_VAL(x) \ + ((x) << ESPI_SLAVE_VW_COUNT_SEL_SHIFT) +#define ESPI_SLAVE_VW_COUNT_SUPP_SHIFT 8 +#define ESPI_SLAVE_VW_COUNT_SUPP_MASK \ + (0x3f << ESPI_SLAVE_VW_COUNT_SUPP_SHIFT) + +#define ESPI_SLAVE_OOB_CFG 0x30 +#define ESPI_SLAVE_OOB_MAX_PAYLOAD_SIZE_SEL_SHIFT 8 +#define ESPI_SLAVE_OOB_MAX_PAYLOAD_SIZE_SEL_MASK \ + (0x7 << ESPI_SLAVE_OOB_MAX_PAYLOAD_SIZE_SEL_SHIFT) +#define ESPI_SLAVE_OOB_MAX_PAYLOAD_SIZE_SEL_VAL(x) \ + ((x) << ESPI_SLAVE_OOB_MAX_PAYLOAD_SIZE_SEL_SHIFT) +#define ESPI_SLAVE_OOB_MAX_PAYLOAD_SIZE_SEL_64B \ + ESPI_SLAVE_OOB_MAX_PAYLOAD_SIZE_SEL_VAL(1) +#define ESPI_SLAVE_OOB_MAX_PAYLOAD_SIZE_SEL_128B \ + ESPI_SLAVE_OOB_MAX_PAYLOAD_SIZE_SEL_VAL(2) +#define ESPI_SLAVE_OOB_MAX_PAYLOAD_SIZE_SEL_256B \ + ESPI_SLAVE_OOB_MAX_PAYLOAD_SIZE_SEL_VAL(3) +#define ESPI_SLAVE_OOB_MAX_PAYLOAD_SIZE_SUPP_SHIFT 4 +#define ESPI_SLAVE_OOB_MAX_PAYLOAD_SIZE_SUPP_MASK \ + (0x7 << ESPI_SLAVE_OOB_MAX_PAYLOAD_SIZE_SUPP_SHIFT) +#define ESPI_SLAVE_OOB_MAX_PAYLOAD_SIZE_SUPP_VAL(x) \ + ((x) << ESPI_SLAVE_OOB_MAX_PAYLOAD_SIZE_SUPP_SHIFT) +#define ESPI_SLAVE_OOB_MAX_PAYLOAD_SIZE_SUPP_64B \ + ESPI_SLAVE_OOB_MAX_PAYLOAD_SIZE_SUPP_VAL(1) +#define ESPI_SLAVE_OOB_MAX_PAYLOAD_SIZE_SUPP_128B \ + ESPI_SLAVE_OOB_MAX_PAYLOAD_SIZE_SUPP_VAL(2) +#define ESPI_SLAVE_OOB_MAX_PAYLOAD_SIZE_SUPP_256B \ + ESPI_SLAVE_OOB_MAX_PAYLOAD_SIZE_SUPP_VAL(3) + +#define ESPI_SLAVE_FLASH_CFG 0x40 +#define ESPI_SLAVE_FLASH_MAX_READ_SIZE_SHIFT 12 +#define ESPI_SLAVE_FLASH_MAX_READ_SIZE_MASK \ + (0x7 << ESPI_SLAVE_FLASH_MAX_READ_SIZE_SHIFT) +#define ESPI_SLAVE_FLASH_MAX_READ_SIZE_VAL(x) \ + ((x) << ESPI_SLAVE_FLASH_MAX_READ_SIZE_SHIFT) +#define ESPI_SLAVE_FLASH_MAX_READ_64B ESPI_SLAVE_FLASH_MAX_READ_SIZE_VAL(1) +#define ESPI_SLAVE_FLASH_MAX_READ_128B ESPI_SLAVE_FLASH_MAX_READ_SIZE_VAL(2) +#define ESPI_SLAVE_FLASH_MAX_READ_256B ESPI_SLAVE_FLASH_MAX_READ_SIZE_VAL(3) +#define ESPI_SLAVE_FLASH_MAX_READ_512B ESPI_SLAVE_FLASH_MAX_READ_SIZE_VAL(4) +#define ESPI_SLAVE_FLASH_MAX_READ_1024B ESPI_SLAVE_FLASH_MAX_READ_SIZE_VAL(5) +#define ESPI_SLAVE_FLASH_MAX_READ_2048B ESPI_SLAVE_FLASH_MAX_READ_SIZE_VAL(6) +#define ESPI_SLAVE_FLASH_MAX_READ_4096B ESPI_SLAVE_FLASH_MAX_READ_SIZE_VAL(7) +#define ESPI_SLAVE_FLASH_SHARING_MODE_MAF (1 << 11) +#define ESPI_SLAVE_FLASH_SHARING_MODE_SAF (0 << 11) +#define ESPI_SLAVE_FLASH_MAX_PAYLOAD_SIZE_SEL_SHIFT 8 +#define ESPI_SLAVE_FLASH_MAX_PAYLOAD_SIZE_SEL_MASK \ + (0x7 << ESPI_SLAVE_FLASH_MAX_PAYLOAD_SIZE_SEL_SHIFT) +#define ESPI_SLAVE_FLASH_MAX_PAYLOAD_SIZE_SEL_VAL(x) \ + ((x) << ESPI_SLAVE_FLASH_MAX_PAYLOAD_SIZE_SEL_SHIFT) +#define ESPI_SLAVE_FLASH_MAX_PAYLOAD_SIZE_SEL_64B \ + ESPI_SLAVE_FLASH_MAX_PAYLOAD_SIZE_SEL_VAL(1) +#define ESPI_SLAVE_FLASH_MAX_PAYLOAD_SIZE_SEL_128B \ + ESPI_SLAVE_FLASH_MAX_PAYLOAD_SIZE_SEL_VAL(2) +#define ESPI_SLAVE_FLASH_MAX_PAYLOAD_SIZE_SEL_256B \ + ESPI_SLAVE_FLASH_MAX_PAYLOAD_SIZE_SEL_VAL(3) +#define ESPI_SLAVE_FLASH_MAX_PAYLOAD_SIZE_SUPP_SHIFT 5 +#define ESPI_SLAVE_FLASH_MAX_PAYLOAD_SIZE_SUPP_MASK \ + (0x7 << ESPI_SLAVE_FLASH_MAX_PAYLOAD_SIZE_SUPP_SHIFT) +#define ESPI_SLAVE_FLASH_MAX_PAYLOAD_SIZE_SUPP_VAL(x) \ + ((x) << ESPI_SLAVE_FLASH_MAX_PAYLOAD_SIZE_SUPP_SHIFT) +#define ESPI_SLAVE_FLASH_MAX_PAYLOAD_SIZE_SUPP_64B \ + ESPI_SLAVE_FLASH_MAX_PAYLOAD_SIZE_SUPP_VAL(1) +#define ESPI_SLAVE_FLASH_MAX_PAYLOAD_SIZE_SUPP_128B \ + ESPI_SLAVE_FLASH_MAX_PAYLOAD_SIZE_SUPP_VAL(2) +#define ESPI_SLAVE_FLASH_MAX_PAYLOAD_SIZE_SUPP_256B \ + ESPI_SLAVE_FLASH_MAX_PAYLOAD_SIZE_SUPP_VAL(3) +#define ESPI_SLAVE_FLASH_BLOCK_ERASE_SIZE_SHIFT 2 +#define ESPI_SLAVE_FLASH_BLOCK_ERASE_SIZE_MASK \ + (0x7 << ESPI_SLAVE_FLASH_BLOCK_ERASE_SIZE_SHIFT) +#define ESPI_SLAVE_FLASH_BLOCK_ERASE_SIZE_VAL(x) \ + ((x) << ESPI_SLAVE_FLASH_BLOCK_ERASE_SIZE_SHIFT) +#define ESPI_SLAVE_FLASH_BLOCK_ERASE_SIZE_4K \ + ESPI_SLAVE_FLASH_BLOCK_ERASE_SIZE_VAL(1) +#define ESPI_SLAVE_FLASH_BLOCK_ERASE_SIZE_64K \ + ESPI_SLAVE_FLASH_BLOCK_ERASE_SIZE_VAL(2) +#define ESPI_SLAVE_FLASH_BLOCK_ERASE_SIZE_4K_64K \ + ESPI_SLAVE_FLASH_BLOCK_ERASE_SIZE_VAL(3) +#define ESPI_SLAVE_FLASH_BLOCK_ERASE_SIZE_128K \ + ESPI_SLAVE_FLASH_BLOCK_ERASE_SIZE_VAL(4) +#define ESPI_SLAVE_FLASH_BLOCK_ERASE_SIZE_256K \ + ESPI_SLAVE_FLASH_BLOCK_ERASE_SIZE_VAL(5) + +/* + * All channels -- peripheral, OOB, VW and flash use the same bits for channel ready and channel + * enable. + */ +#define ESPI_SLAVE_CHANNEL_READY (1 << 1) +#define ESPI_SLAVE_CHANNEL_ENABLE (1 << 0) + +#endif /* __ESPI_H__ */ From f3ac812e022f70d54dfcb94510eafa3d14462627 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 11 May 2020 12:06:25 -0700 Subject: [PATCH 019/405] espi: Add definitions for eSPI VW index messsages This change adds eSPI VW index message definitions as per per Enhanced Serial Peripheral Interface Base Specification (document # 327432-004 Revision 1.0) Chapter 5 "Transaction Layer". BUG=b:153675913 Signed-off-by: Furquan Shaikh Change-Id: I5c04d4de222e16d3b8e2a5fb2fc4107ea278a35b Reviewed-on: https://review.coreboot.org/c/coreboot/+/41252 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/include/espi.h | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/src/include/espi.h b/src/include/espi.h index b1a51d9584..171b1b8831 100644 --- a/src/include/espi.h +++ b/src/include/espi.h @@ -189,4 +189,41 @@ #define ESPI_SLAVE_CHANNEL_READY (1 << 1) #define ESPI_SLAVE_CHANNEL_ENABLE (1 << 0) +/* ESPI Slave Registers (Document # 327432-004 Revision 1.0 Chapter 5) */ +#define ESPI_VW_INDEX_INTERRUPT_EVENT_0 0 /* Interrupt lines 0 - 127 */ +#define ESPI_VW_INDEX_INTERRUPT_EVENT_1 1 /* Interrupt lines 128-255 */ +#define ESPI_VW_INTERRUPT_LEVEL_HIGH (1 << 7) +#define ESPI_VW_INTERRUPT_LEVEL_LOW (0 << 7) + +#define ESPI_VW_INDEX_SYSTEM_EVENT_2 2 +#define ESPI_VW_SLP_S5 2 +#define ESPI_VW_SLP_S4 1 +#define ESPI_VW_SLP_S3 0 +#define ESPI_VW_INDEX_SYSTEM_EVENT_3 3 +#define ESPI_VW_OOB_RST_WARN 2 +#define ESPI_VW_PLTRST 1 +#define ESPI_VW_SUS_STAT 0 +#define ESPI_VW_INDEX_SYSTEM_EVENT_4 4 +#define ESPI_VW_PME 3 +#define ESPI_VW_WAKE 2 +#define ESPI_VW_OOB_RST_ACK 0 +#define ESPI_VW_INDEX_SYSTEM_EVENT_5 5 +#define ESPI_VW_SLAVE_BOOT_LOAD_STATUS 3 +#define ESPI_VW_ERROR_NON_FATAL 2 +#define ESPI_VW_ERROR_FATAL 1 +#define ESPI_VW_SLV_BOOT_LOAD_DONE 0 +#define ESPI_VW_INDEX_SYSTEM_EVENT_6 6 +#define ESPI_VW_HOST_RST_ACK 3 +#define ESPI_VW_RCIN 2 +#define ESPI_VW_SMI 1 +#define ESPI_VW_SCI 0 +#define ESPI_VW_INDEX_SYSTEM_EVENT_7 7 +#define ESPI_VW_NMIOUT 2 +#define ESPI_VW_SMIOUT 1 +#define ESPI_VW_HOST_RST_WARN 0 + +#define ESPI_VW_VALID(x) (1 << ((x) + 4)) +#define ESPI_VW_VALUE(x, v) ((v) << (x)) +#define ESPI_VW_SIGNAL_HIGH(x) (ESPI_VW_VALID(x) | ESPI_VW_VALUE(1, x)) +#define ESPI_VW_SIGNAL_LOW(x) (ESPI_VW_VALID(x) | ESPI_VW_VALUE(0, x)) #endif /* __ESPI_H__ */ From 470f627c2bbfda9ff7e42801fa93b5205e0ba654 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 11 May 2020 16:43:37 -0700 Subject: [PATCH 020/405] espi: Add some helper functions for espi capability check This change adds helper functions that can be used to check support for different slave capabilities. BUG=b:153675913 Signed-off-by: Furquan Shaikh Change-Id: Ic66b06f9efcafd0eda4c6029fa67489de76bbed4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41253 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Paul Menzel --- src/include/espi.h | 92 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/src/include/espi.h b/src/include/espi.h index 171b1b8831..f0ae37383a 100644 --- a/src/include/espi.h +++ b/src/include/espi.h @@ -4,6 +4,8 @@ #ifndef __ESPI_H__ #define __ESPI_H__ +#include + /* ESPI Slave Registers (Document # 327432-004 Revision 1.0 Chapter 7) */ #define ESPI_SLAVE_DEVICE_ID 0x04 @@ -226,4 +228,94 @@ #define ESPI_VW_VALUE(x, v) ((v) << (x)) #define ESPI_VW_SIGNAL_HIGH(x) (ESPI_VW_VALID(x) | ESPI_VW_VALUE(1, x)) #define ESPI_VW_SIGNAL_LOW(x) (ESPI_VW_VALID(x) | ESPI_VW_VALUE(0, x)) + +static inline bool espi_slave_supports_quad_io(uint32_t gen_caps) +{ + uint32_t mode = gen_caps & ESPI_SLAVE_IO_MODE_SUPP_MASK; + return (mode == ESPI_SLAVE_IO_MODE_SUPP_SINGLE_QUAD) || + (mode == ESPI_SLAVE_IO_MODE_SUPP_SINGLE_DUAL_QUAD); +} + +static inline bool espi_slave_supports_dual_io(uint32_t gen_caps) +{ + uint32_t mode = gen_caps & ESPI_SLAVE_IO_MODE_SUPP_MASK; + return (mode == ESPI_SLAVE_IO_MODE_SUPP_SINGLE_DUAL) || + (mode == ESPI_SLAVE_IO_MODE_SUPP_SINGLE_DUAL_QUAD); +} + +static inline bool espi_slave_supports_66_mhz(uint32_t gen_caps) +{ + uint32_t freq = gen_caps & ESPI_SLAVE_OP_FREQ_SUPP_MASK; + return freq == ESPI_SLAVE_OP_FREQ_SUPP_66_MHZ; +} + +static inline bool espi_slave_supports_50_mhz(uint32_t gen_caps) +{ + uint32_t freq = gen_caps & ESPI_SLAVE_OP_FREQ_SUPP_MASK; + return freq == ESPI_SLAVE_OP_FREQ_SUPP_50_MHZ; +} + +static inline bool espi_slave_supports_33_mhz(uint32_t gen_caps) +{ + uint32_t freq = gen_caps & ESPI_SLAVE_OP_FREQ_SUPP_MASK; + return freq == ESPI_SLAVE_OP_FREQ_SUPP_33_MHZ; +} + +static inline bool espi_slave_supports_25_mhz(uint32_t gen_caps) +{ + uint32_t freq = gen_caps & ESPI_SLAVE_OP_FREQ_SUPP_MASK; + return freq == ESPI_SLAVE_OP_FREQ_SUPP_25_MHZ; +} + +static inline bool espi_slave_supports_20_mhz(uint32_t gen_caps) +{ + uint32_t freq = gen_caps & ESPI_SLAVE_OP_FREQ_SUPP_MASK; + return freq == ESPI_SLAVE_OP_FREQ_SUPP_20_MHZ; +} + +static inline int espi_slave_max_speed_mhz_supported(uint32_t gen_caps) +{ + if (espi_slave_supports_66_mhz(gen_caps)) + return 66; + else if (espi_slave_supports_50_mhz(gen_caps)) + return 50; + else if (espi_slave_supports_33_mhz(gen_caps)) + return 33; + else if (espi_slave_supports_25_mhz(gen_caps)) + return 25; + else if (espi_slave_supports_20_mhz(gen_caps)) + return 20; + return 0; +} + +static inline bool espi_slave_supports_vw_channel(uint32_t gen_caps) +{ + return !!(gen_caps & ESPI_SLAVE_VW_CH_SUPP); +} + +static inline bool espi_slave_supports_periph_channel(uint32_t gen_caps) +{ + return !!(gen_caps & ESPI_SLAVE_PERIPH_CH_SUPP); +} + +static inline bool espi_slave_supports_oob_channel(uint32_t gen_caps) +{ + return !!(gen_caps & ESPI_SLAVE_OOB_CH_SUPP); +} + +static inline bool espi_slave_supports_flash_channel(uint32_t gen_caps) +{ + return !!(gen_caps & ESPI_SLAVE_FLASH_CH_SUPP); +} + +static inline bool espi_slave_is_channel_ready(uint32_t config) +{ + return !!(config & ESPI_SLAVE_CHANNEL_READY); +} + +static inline uint32_t espi_slave_get_vw_count_supp(uint32_t vw_caps) +{ + return (vw_caps & ESPI_SLAVE_VW_COUNT_SUPP_MASK) >> ESPI_SLAVE_VW_COUNT_SUPP_SHIFT; +} + #endif /* __ESPI_H__ */ From 5cc41f2a6b6aeca1500fe9f55af5858d1c7e4e38 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 11 May 2020 12:11:27 -0700 Subject: [PATCH 021/405] espi: Add support for debug helper to print slave capabilities This change adds a Kconfig option to enable eSPI debugging that pulls in a helper function to print slave capabilities. BUG=b:153675913 Signed-off-by: Furquan Shaikh Change-Id: I8ff250fe85dfa9370bf93ce3c7e2de5c069bf9e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41254 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Aaron Durbin --- src/include/espi.h | 6 +++ src/lib/Kconfig | 6 +++ src/lib/Makefile.inc | 5 +++ src/lib/espi_debug.c | 94 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 111 insertions(+) create mode 100644 src/lib/espi_debug.c diff --git a/src/include/espi.h b/src/include/espi.h index f0ae37383a..7503af79ec 100644 --- a/src/include/espi.h +++ b/src/include/espi.h @@ -229,6 +229,12 @@ #define ESPI_VW_SIGNAL_HIGH(x) (ESPI_VW_VALID(x) | ESPI_VW_VALUE(1, x)) #define ESPI_VW_SIGNAL_LOW(x) (ESPI_VW_VALID(x) | ESPI_VW_VALUE(0, x)) +#if CONFIG(ESPI_DEBUG) +void espi_show_slave_general_configuration(uint32_t config); +#else +static void espi_show_slave_general_configuration(uint32_t config) {} +#endif + static inline bool espi_slave_supports_quad_io(uint32_t gen_caps) { uint32_t mode = gen_caps & ESPI_SLAVE_IO_MODE_SUPP_MASK; diff --git a/src/lib/Kconfig b/src/lib/Kconfig index dd9974a817..a6fb1f149e 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -75,3 +75,9 @@ config NO_FMAP_CACHE If your platform really doesn't want to use an FMAP cache (e.g. due to space constraints), you can select this to disable warnings and save a bit more code. + +config ESPI_DEBUG + bool + help + This option enables eSPI library helper functions for displaying debug + information. diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index f9bbebb35c..1fed543f70 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -162,6 +162,11 @@ romstage-y += hexdump.c verstage-y += hexdump.c smm-y += hexdump.c +bootblock-$(CONFIG_ESPI_DEBUG) += espi_debug.c +verstage-$(CONFIG_ESPI_DEBUG) += espi_debug.c +romstage-$(CONFIG_ESPI_DEBUG) += espi_debug.c +ramstage-$(CONFIG_ESPI_DEBUG) += espi_debug.c + bootblock-$(CONFIG_REG_SCRIPT) += reg_script.c verstage-$(CONFIG_REG_SCRIPT) += reg_script.c romstage-$(CONFIG_REG_SCRIPT) += reg_script.c diff --git a/src/lib/espi_debug.c b/src/lib/espi_debug.c new file mode 100644 index 0000000000..63e16f444b --- /dev/null +++ b/src/lib/espi_debug.c @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include + +void espi_show_slave_general_configuration(uint32_t config) +{ + uint32_t io_mode; + uint32_t op_freq; + + printk(BIOS_DEBUG, "eSPI Slave configuration:\n"); + + if (config & ESPI_SLAVE_CRC_ENABLE) + printk(BIOS_DEBUG, " CRC checking enabled\n"); + + if (config & ESPI_SLAVE_RESP_MOD_ENABLE) + printk(BIOS_DEBUG, " Response modifier enabled\n"); + + if (config & ESPI_SLAVE_ALERT_MODE_PIN) + printk(BIOS_DEBUG, " Dedicated Alert# used to signal alert event\n"); + else + printk(BIOS_DEBUG, " IO bit1 pin used to signal alert event\n"); + + io_mode = config & ESPI_SLAVE_IO_MODE_SEL_MASK; + if (io_mode == ESPI_SLAVE_IO_MODE_SEL_SINGLE) + printk(BIOS_DEBUG, " eSPI single IO mode selected\n"); + else if (io_mode == ESPI_SLAVE_IO_MODE_SEL_DUAL) + printk(BIOS_DEBUG, " eSPI dual IO mode selected\n"); + else if (io_mode == ESPI_SLAVE_IO_MODE_SEL_QUAD) + printk(BIOS_DEBUG, " eSPI quad IO mode selected\n"); + else + printk(BIOS_DEBUG, " Error: Invalid eSPI IO mode selected\n"); + + io_mode = config & ESPI_SLAVE_IO_MODE_SUPP_MASK; + if (io_mode == ESPI_SLAVE_IO_MODE_SUPP_SINGLE_QUAD) + printk(BIOS_DEBUG, " eSPI quad and single IO modes supported\n"); + else if (io_mode == ESPI_SLAVE_IO_MODE_SUPP_SINGLE_DUAL) + printk(BIOS_DEBUG, " eSPI dual and single IO mode supported\n"); + else if (io_mode == ESPI_SLAVE_IO_MODE_SUPP_SINGLE_DUAL_QUAD) + printk(BIOS_DEBUG, " eSPI quad, dual, and single IO modes supported\n"); + else + printk(BIOS_DEBUG, " Only eSPI single IO mode supported\n"); + + if (config & ESPI_SLAVE_OPEN_DRAIN_ALERT_SEL) + printk(BIOS_DEBUG, " Alert# pin is open-drain\n"); + else + printk(BIOS_DEBUG, " Alert# pin is driven\n"); + + op_freq = config & ESPI_SLAVE_OP_FREQ_SEL_MASK; + if (op_freq == ESPI_SLAVE_OP_FREQ_SEL_20_MHZ) + printk(BIOS_DEBUG, " eSPI 20MHz selected\n"); + else if (op_freq == ESPI_SLAVE_OP_FREQ_SEL_25_MHZ) + printk(BIOS_DEBUG, " eSPI 25MHz selected\n"); + else if (op_freq == ESPI_SLAVE_OP_FREQ_SEL_33_MHZ) + printk(BIOS_DEBUG, " eSPI 33MHz selected\n"); + else if (op_freq == ESPI_SLAVE_OP_FREQ_SEL_50_MHZ) + printk(BIOS_DEBUG, " eSPI 50MHz selected\n"); + else if (op_freq == ESPI_SLAVE_OP_FREQ_SEL_66_MHZ) + printk(BIOS_DEBUG, " eSPI 66MHz selected\n"); + else + printk(BIOS_DEBUG, " Error: Invalid eSPI frequency\n"); + + if (config & ESPI_SLAVE_OPEN_DRAIN_ALERT_SUPP) + printk(BIOS_DEBUG, " Open-drain Alert# pin supported\n"); + + op_freq = config & ESPI_SLAVE_OP_FREQ_SUPP_MASK; + if (op_freq == ESPI_SLAVE_OP_FREQ_SUPP_20_MHZ) + printk(BIOS_DEBUG, " eSPI 20MHz supported\n"); + else if (op_freq == ESPI_SLAVE_OP_FREQ_SUPP_25_MHZ) + printk(BIOS_DEBUG, " eSPI 25MHz supported\n"); + else if (op_freq == ESPI_SLAVE_OP_FREQ_SUPP_33_MHZ) + printk(BIOS_DEBUG, " eSPI 33MHz supported\n"); + else if (op_freq == ESPI_SLAVE_OP_FREQ_SUPP_50_MHZ) + printk(BIOS_DEBUG, " eSPI 50MHz supported\n"); + else if (op_freq == ESPI_SLAVE_OP_FREQ_SUPP_66_MHZ) + printk(BIOS_DEBUG, " eSPI 66MHz supported\n"); + else + printk(BIOS_DEBUG, " Error: Invalid eSPI frequency\n"); + + printk(BIOS_DEBUG, " Maximum Wait state: %d\n", + (config & ESPI_SLAVE_MAX_WAIT_MASK) >> ESPI_SLAVE_MAX_WAIT_SHIFT); + + if (config & ESPI_SLAVE_PERIPH_CH_SUPP) + printk(BIOS_DEBUG, " Peripheral Channel supported\n"); + if (config & ESPI_SLAVE_VW_CH_SUPP) + printk(BIOS_DEBUG, " Virtual Wire Channel supported\n"); + if (config & ESPI_SLAVE_OOB_CH_SUPP) + printk(BIOS_DEBUG, " OOB Channel supported\n"); + if (config & ESPI_SLAVE_FLASH_CH_SUPP) + printk(BIOS_DEBUG, " Flash Access Channel supported\n"); + printk(BIOS_DEBUG, "\n"); +} From dd5264612ae8145c8c8e38d2ff3fb7e47de8e4b2 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 4 May 2020 22:54:22 -0700 Subject: [PATCH 022/405] soc/amd/common/block: Add header file for eSPI register definitions This change adds eSPI register definitions for I/O and MMIO decode using eSPI on AMD SoCs. Additionally, it also adds a macro to define the offset of ESPI MMIO base from SPI MMIO base. BUG=b:153675913 Change-Id: Ifb70ae0c63cc823334a1d851faf4dda6d1c1fc1a Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41072 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Aaron Durbin --- .../amd/common/block/include/amdblocks/espi.h | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 src/soc/amd/common/block/include/amdblocks/espi.h diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h new file mode 100644 index 0000000000..82410e58d3 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __AMDBLOCKS_ESPI_H__ +#define __AMDBLOCKS_ESPI_H__ + +/* eSPI MMIO base lives at an offset of 0x10000 from the address in SPI BAR. */ +#define ESPI_OFFSET_FROM_BAR 0x10000 + +#define ESPI_DECODE 0x40 +#define ESPI_DECODE_MMIO_RANGE_EN(range) (1 << (((range) & 3) + 12)) +#define ESPI_DECODE_IO_RANGE_EN(range) (1 << (((range) & 3) + 8)) +#define ESPI_DECODE_IO_0x80_EN (1 << 2) +#define ESPI_DECODE_IO_0X60_0X64_EN (1 << 1) +#define ESPI_DECODE_IO_0X2E_0X2F_EN (1 << 0) + +#define ESPI_IO_RANGE_BASE(range) (0x44 + ((range) & 3) * 2) +#define ESPI_IO_RANGE_SIZE(range) (0x4c + ((range) & 3)) +#define ESPI_MMIO_RANGE_BASE(range) (0x50 + ((range) & 3) * 4) +#define ESPI_MMIO_RANGE_SIZE(range) (0x60 + ((range) & 3) * 2) + +#define ESPI_GENERIC_IO_WIN_COUNT 4 +#define ESPI_GENERIC_IO_MAX_WIN_SIZE 0x100 +#define ESPI_GENERIC_MMIO_WIN_COUNT 4 +#define ESPI_GENERIC_MMIO_MAX_WIN_SIZE 0x10000 + +#endif /* __AMDBLOCKS_ESPI_H__ */ From f318e03495e9a1d43d64516d77a6ae5f2c4d6999 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 4 May 2020 23:38:53 -0700 Subject: [PATCH 023/405] soc/amd/common/block/lpc: Add helpers for managing eSPI decode This change adds the following helper functions for eSPI decode: 1. espi_open_io_window() - Open generic IO window decoded by eSPI 2. espi_open_mmio_window() - Open generic MMIO window decoded by eSPI 3. espi_configure_decodes() - Configures standard and generic I/O windows using the espi configuration provided by mainboard in device tree. BUG=b:153675913,b:154445472 Change-Id: Idb49ef0477280eb46ecad65131d4cd7357618941 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41073 Reviewed-by: Aaron Durbin Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- .../amd/common/block/include/amdblocks/chip.h | 4 + .../amd/common/block/include/amdblocks/espi.h | 31 ++ src/soc/amd/common/block/lpc/Makefile.inc | 5 + src/soc/amd/common/block/lpc/espi_util.c | 291 ++++++++++++++++++ 4 files changed, 331 insertions(+) create mode 100644 src/soc/amd/common/block/lpc/espi_util.c diff --git a/src/soc/amd/common/block/include/amdblocks/chip.h b/src/soc/amd/common/block/include/amdblocks/chip.h index 6e3c973c97..b0348115e9 100644 --- a/src/soc/amd/common/block/include/amdblocks/chip.h +++ b/src/soc/amd/common/block/include/amdblocks/chip.h @@ -4,6 +4,7 @@ #ifndef __AMDBLOCKS_CHIP_H__ #define __AMDBLOCKS_CHIP_H__ +#include #include struct soc_amd_common_config { @@ -17,6 +18,9 @@ struct soc_amd_common_config { * TPM speed - 66MHz */ struct spi_config spi_config; + + /* eSPI configuration */ + struct espi_config espi_config; }; /* diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index 82410e58d3..53cc5f9f3f 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -4,6 +4,9 @@ #ifndef __AMDBLOCKS_ESPI_H__ #define __AMDBLOCKS_ESPI_H__ +#include +#include + /* eSPI MMIO base lives at an offset of 0x10000 from the address in SPI BAR. */ #define ESPI_OFFSET_FROM_BAR 0x10000 @@ -24,4 +27,32 @@ #define ESPI_GENERIC_MMIO_WIN_COUNT 4 #define ESPI_GENERIC_MMIO_MAX_WIN_SIZE 0x10000 +struct espi_config { + /* Bitmap for standard IO decodes. Use ESPI_DECODE_IO_* above. */ + uint32_t std_io_decode_bitmap; + + struct { + uint16_t base; + size_t size; + } generic_io_range[ESPI_GENERIC_IO_WIN_COUNT]; +}; + +/* + * Open I/O window using the provided base and size. + * Return value: 0 = success, -1 = error. + */ +int espi_open_io_window(uint16_t base, size_t size); + +/* + * Open MMIO window using the provided base and size. + * Return value: 0 = success, -1 = error. + */ +int espi_open_mmio_window(uint32_t base, size_t size); + +/* + * Configure generic and standard I/O decode windows using the espi_config structure settings + * provided by mainboard in device tree. + */ +void espi_configure_decodes(void); + #endif /* __AMDBLOCKS_ESPI_H__ */ diff --git a/src/soc/amd/common/block/lpc/Makefile.inc b/src/soc/amd/common/block/lpc/Makefile.inc index 72b1e42013..7db176b31d 100644 --- a/src/soc/amd/common/block/lpc/Makefile.inc +++ b/src/soc/amd/common/block/lpc/Makefile.inc @@ -6,3 +6,8 @@ romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c + +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_USE_ESPI) += espi_util.c +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_USE_ESPI) += espi_util.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_USE_ESPI) += espi_util.c +verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_USE_ESPI) += espi_util.c diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c new file mode 100644 index 0000000000..2585c46138 --- /dev/null +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -0,0 +1,291 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static uintptr_t espi_get_bar(void) +{ + uintptr_t espi_spi_base = lpc_get_spibase(); + return espi_spi_base + ESPI_OFFSET_FROM_BAR; +} + +static uint32_t espi_read32(int reg) +{ + return read32((void *)(espi_get_bar() + reg)); +} + +static void espi_write32(int reg, uint32_t val) +{ + write32((void *)(espi_get_bar() + reg), val); +} + +static uint16_t espi_read16(int reg) +{ + return read16((void *)(espi_get_bar() + reg)); +} + +static void espi_write16(int reg, uint16_t val) +{ + write16((void *)(espi_get_bar() + reg), val); +} + +static uint8_t espi_read8(int reg) +{ + return read8((void *)(espi_get_bar() + reg)); +} + +static void espi_write8(int reg, uint8_t val) +{ + write8((void *)(espi_get_bar() + reg), val); +} + +static void espi_enable_decode(int decode_en) +{ + uint32_t val; + + val = espi_read32(ESPI_DECODE); + val |= decode_en; + espi_write32(ESPI_DECODE, val); +} + +static bool espi_is_decode_enabled(int decode) +{ + uint32_t val; + + val = espi_read32(ESPI_DECODE); + return !!(val & decode); +} + +static int espi_find_io_window(uint16_t win_base) +{ + int i; + + for (i = 0; i < ESPI_GENERIC_IO_WIN_COUNT; i++) { + if (!espi_is_decode_enabled(ESPI_DECODE_IO_RANGE_EN(i))) + continue; + + if (espi_read16(ESPI_IO_RANGE_BASE(i)) == win_base) + return i; + } + + return -1; +} + +static int espi_get_unused_io_window(void) +{ + int i; + + for (i = 0; i < ESPI_GENERIC_IO_WIN_COUNT; i++) { + if (!espi_is_decode_enabled(ESPI_DECODE_IO_RANGE_EN(i))) + return i; + } + + return -1; +} + +/* + * Returns decode enable bits for standard IO port addresses. If port address is not supported + * by standard decode or if the size of window is not 1, then it returns -1. + */ +static int espi_std_io_decode(uint16_t base, size_t size) +{ + int ret = -1; + + if (size != 1) + return ret; + + switch (base) { + case 0x80: + ret = ESPI_DECODE_IO_0x80_EN; + break; + case 0x60: + case 0x64: + ret = ESPI_DECODE_IO_0X60_0X64_EN; + break; + case 0x2e: + case 0x2f: + ret = ESPI_DECODE_IO_0X2E_0X2F_EN; + break; + default: + ret = -1; + break; + } + + return ret; +} + +static size_t espi_get_io_window_size(int idx) +{ + return espi_read8(ESPI_IO_RANGE_SIZE(idx)) + 1; +} + +static void espi_write_io_window(int idx, uint16_t base, size_t size) +{ + espi_write16(ESPI_IO_RANGE_BASE(idx), base); + espi_write8(ESPI_IO_RANGE_SIZE(idx), size - 1); +} + +static int espi_open_generic_io_window(uint16_t base, size_t size) +{ + size_t win_size; + int idx; + + for (; size; size -= win_size, base += win_size) { + win_size = MIN(size, ESPI_GENERIC_IO_MAX_WIN_SIZE); + + idx = espi_find_io_window(base); + if (idx != -1) { + size_t curr_size = espi_get_io_window_size(idx); + + if (curr_size > win_size) { + printk(BIOS_INFO, "eSPI window already configured to be larger than requested! "); + printk(BIOS_INFO, "Base: 0x%x, Requested size: 0x%zx, Actual size: 0x%zx\n", + base, win_size, curr_size); + } else if (curr_size < win_size) { + espi_write_io_window(idx, base, win_size); + printk(BIOS_INFO, "eSPI window at base: 0x%x resized from 0x%zx to 0x%zx\n", + base, curr_size, win_size); + } + + continue; + } + + idx = espi_get_unused_io_window(); + if (idx == -1) { + printk(BIOS_ERR, "Cannot open IO window base %x size %zx\n", base, + size); + printk(BIOS_ERR, "ERROR: No more available IO windows!\n"); + return -1; + } + + espi_write_io_window(idx, base, win_size); + espi_enable_decode(ESPI_DECODE_IO_RANGE_EN(idx)); + } + + return 0; +} + +int espi_open_io_window(uint16_t base, size_t size) +{ + int std_io; + + std_io = espi_std_io_decode(base, size); + if (std_io != -1) { + espi_enable_decode(std_io); + return 0; + } + + return espi_open_generic_io_window(base, size); +} + +static int espi_find_mmio_window(uint32_t win_base) +{ + int i; + + for (i = 0; i < ESPI_GENERIC_MMIO_WIN_COUNT; i++) { + if (!espi_is_decode_enabled(ESPI_DECODE_MMIO_RANGE_EN(i))) + continue; + + if (espi_read32(ESPI_MMIO_RANGE_BASE(i)) == win_base) + return i; + } + + return -1; +} + +static int espi_get_unused_mmio_window(void) +{ + int i; + + for (i = 0; i < ESPI_GENERIC_MMIO_WIN_COUNT; i++) { + if (!espi_is_decode_enabled(ESPI_DECODE_MMIO_RANGE_EN(i))) + return i; + } + + return -1; + +} + +static size_t espi_get_mmio_window_size(int idx) +{ + return espi_read16(ESPI_MMIO_RANGE_SIZE(idx)) + 1; +} + +static void espi_write_mmio_window(int idx, uint32_t base, size_t size) +{ + espi_write32(ESPI_MMIO_RANGE_BASE(idx), base); + espi_write16(ESPI_MMIO_RANGE_SIZE(idx), size - 1); +} + +int espi_open_mmio_window(uint32_t base, size_t size) +{ + size_t win_size; + int idx; + + for (; size; size -= win_size, base += win_size) { + win_size = MIN(size, ESPI_GENERIC_MMIO_MAX_WIN_SIZE); + + idx = espi_find_mmio_window(base); + if (idx != -1) { + size_t curr_size = espi_get_mmio_window_size(idx); + + if (curr_size > win_size) { + printk(BIOS_INFO, "eSPI window already configured to be larger than requested! "); + printk(BIOS_INFO, "Base: 0x%x, Requested size: 0x%zx, Actual size: 0x%zx\n", + base, win_size, curr_size); + } else if (curr_size < win_size) { + espi_write_mmio_window(idx, base, win_size); + printk(BIOS_INFO, "eSPI window at base: 0x%x resized from 0x%zx to 0x%zx\n", + base, curr_size, win_size); + } + + continue; + } + + idx = espi_get_unused_mmio_window(); + if (idx == -1) { + printk(BIOS_ERR, "Cannot open IO window base %x size %zx\n", base, + size); + printk(BIOS_ERR, "ERROR: No more available MMIO windows!\n"); + return -1; + } + + espi_write_mmio_window(idx, base, win_size); + espi_enable_decode(ESPI_DECODE_MMIO_RANGE_EN(idx)); + } + + return 0; +} + +static const struct espi_config *espi_get_config(void) +{ + const struct soc_amd_common_config *soc_cfg = soc_get_common_config(); + + if (!soc_cfg) + die("Common config structure is NULL!\n"); + + return &soc_cfg->espi_config; +} + +void espi_configure_decodes(void) +{ + int i; + const struct espi_config *cfg = espi_get_config(); + + espi_enable_decode(cfg->std_io_decode_bitmap); + + for (i = 0; i < ESPI_GENERIC_IO_WIN_COUNT; i++) { + if (cfg->generic_io_range[i].size == 0) + continue; + espi_open_generic_io_window(cfg->generic_io_range[i].base, + cfg->generic_io_range[i].size); + } +} From 32b8a51153f7836b841cb2da832e9e78b32e1227 Mon Sep 17 00:00:00 2001 From: Shaunak Saha Date: Tue, 31 Mar 2020 22:56:13 -0700 Subject: [PATCH 024/405] soc/intel/tigerlake: Control SATA and DMI power optimization FSP provides the UPD's for SATA and DMI power optimization. In this patch we are adding the soc's config support to set those power optimization bits in FSP. By default those optimizations are enabled. To disable those we need to set the DmiPwrOptimizeDisable and SataPwrOptimizeDisable to 1 in devicetree. BUG=b:151162424 BRANCH=None TEST=Build and boot volteer and TGL RVP. Change-Id: Iefc5e7e48d69dccae43dc595dff2f824e53f5749 Signed-off-by: Shaunak Saha Reviewed-on: https://review.coreboot.org/c/coreboot/+/40005 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/tigerlake/chip.h | 12 ++++++++++++ src/soc/intel/tigerlake/fsp_params.c | 9 +++++++++ 2 files changed, 21 insertions(+) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index d9283e1652..e6e106df94 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -288,6 +288,18 @@ struct soc_intel_tigerlake_config { /* HyperThreadingDisable : Yes (1) / No (0) */ uint8_t HyperThreadingDisable; + + /* + * Enable(0)/Disable(1) DMI Power Optimizer on PCH side. + * Default 0. Setting this to 1 disables the DMI Power Optimizer. + */ + uint8_t DmiPwrOptimizeDisable; + + /* + * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. + * Default 0. Setting this to 1 disables the SATA Power Optimizer. + */ + uint8_t SataPwrOptimizeDisable; }; typedef struct soc_intel_tigerlake_config config_t; diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 11d79529ed..73c41c8519 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -184,6 +184,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(params->SataPortsDevSlp)); } + /* + * Power Optimizer for DMI and SATA. + * DmiPwrOptimizeDisable and SataPwrOptimizeDisable is default to 0. + * Boards not needing the optimizers explicitly disables them by setting + * these disable variables to 1 in devicetree overrides. + */ + params->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable); + params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable); + /* LAN */ dev = pcidev_path_on_root(PCH_DEVFN_GBE); if (!dev) From 98bc961ee365f9d71ee3844e522b659519a8f8a2 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 9 May 2020 19:31:55 -0700 Subject: [PATCH 025/405] soc/amd/common/block/lpc: Provide an option to use static eSPI BAR This change provides a helper function espi_update_static_bar() that informs the eSPI common driver about the static BAR to use for eSPI controller instead of reading the SPIBASE. This is required to support the case of verstage running on PSP. BUG=b:153675913 Signed-off-by: Furquan Shaikh Change-Id: I1f11bb2e29ea0acd71ba6984e42573cfe914e5d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41256 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Raul Rangel --- .../amd/common/block/include/amdblocks/espi.h | 6 ++++++ src/soc/amd/common/block/lpc/espi_util.c | 18 ++++++++++++++++-- 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index 53cc5f9f3f..69267f8cc3 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -55,4 +55,10 @@ int espi_open_mmio_window(uint32_t base, size_t size); */ void espi_configure_decodes(void); +/* + * In cases where eSPI BAR is statically provided by SoC, use that BAR instead of reading + * SPIBASE. This is required for cases where verstage runs on PSP. + */ +void espi_update_static_bar(uintptr_t bar); + #endif /* __AMDBLOCKS_ESPI_H__ */ diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 2585c46138..54a017ea0c 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -11,10 +11,24 @@ #include #include +static uintptr_t espi_bar; + +void espi_update_static_bar(uintptr_t bar) +{ + espi_bar = bar; +} + static uintptr_t espi_get_bar(void) { - uintptr_t espi_spi_base = lpc_get_spibase(); - return espi_spi_base + ESPI_OFFSET_FROM_BAR; + uintptr_t espi_spi_base; + + if (espi_bar) + return espi_bar; + + espi_spi_base = lpc_get_spibase(); + espi_update_static_bar(espi_spi_base + ESPI_OFFSET_FROM_BAR); + + return espi_bar; } static uint32_t espi_read32(int reg) From 511aa44ee68bba15f3aa87e0b6766852436a1c65 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 4 May 2020 23:42:46 -0700 Subject: [PATCH 026/405] soc/amd/common/block/lpc: Configure io/mmio windows differently for LPC and eSPI This change updates lpc_enable_children_resources() to configure IO and MMIO resources differently depending upon whether the mainboard wants to setup decode windows for LPC or eSPI. BUG=b:154445472,b:153675913 Change-Id: Ie8803e934f39388aeb6e3cbd7157664cb357ab23 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41074 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Raul Rangel --- src/soc/amd/common/block/lpc/lpc.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 1e57bc05e5..3ddedcebe8 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -278,6 +279,18 @@ static void configure_child_lpc_windows(struct device *dev, struct device *child pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, reg_x); } +static void configure_child_espi_windows(struct device *child) +{ + struct resource *res; + + for (res = child->resource_list; res; res = res->next) { + if (res->flags & IORESOURCE_IO) + espi_open_io_window(res->base, res->size); + else if (res->flags & IORESOURCE_MEM) + espi_open_mmio_window(res->base, res->size); + } +} + static void lpc_enable_children_resources(struct device *dev) { struct bus *link; @@ -289,7 +302,10 @@ static void lpc_enable_children_resources(struct device *dev) continue; if (child->path.type != DEVICE_PATH_PNP) continue; - configure_child_lpc_windows(dev, child); + if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) + configure_child_espi_windows(child); + else + configure_child_lpc_windows(dev, child); } } } From 727fe925649cadc2803e56b8d5ddb070ddc36a43 Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Mon, 11 May 2020 10:37:15 +0530 Subject: [PATCH 027/405] mb/intel/jasperlake_rvp: Remove SataEnable deviceetree config SataEnable UPD override will be filled using devicetree pci device status check. Change-Id: I957dfcf139acd4f4dd5723bc1b010ec45ec91651 Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/41227 Reviewed-by: Aamir Bohra Reviewed-by: V Sowmya Reviewed-by: Maulik V Vaghela Tested-by: build bot (Jenkins) --- .../intel/jasperlake_rvp/variants/jslrvp/devicetree.cb | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 61ce6cca2b..1e88c7ae62 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -86,8 +86,6 @@ chip soc/intel/jasperlake register "PcieClkSrcClkReq[4]" = "0x04" register "PcieClkSrcClkReq[5]" = "0x05" - register "SataEnable" = "0" - register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, From 7f9bca73286c393a919112133d50a767500cfa95 Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Mon, 4 May 2020 17:54:48 +0530 Subject: [PATCH 028/405] soc/intel/jasperlake: Add SATA related UPDs configuration This patch control SATA related UPDs based on the devicetree configuration as per each board's requirement. BUG=b:155595624 BRANCH=None TEST=Build, boot JSLRVP, Verified UPD values from FSP log Change-Id: I4f7e7508b8cd483508293ee3e7b760574d8f025f Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/41029 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Aamir Bohra Reviewed-by: V Sowmya Reviewed-by: Maulik V Vaghela --- src/soc/intel/jasperlake/chip.h | 1 - src/soc/intel/jasperlake/fsp_params.c | 20 ++++++++++++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 548d0ee2d1..7a6a7fd0dd 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -83,7 +83,6 @@ struct soc_intel_jasperlake_config { uint16_t usb3_wake_enable_bitmap; /* SATA related */ - uint8_t SataEnable; uint8_t SataMode; uint8_t SataSalpSupport; uint8_t SataPortsEnable[8]; diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index d9e8261de7..45162f91f2 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -148,6 +148,26 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } } + /* SATA */ + dev = pcidev_path_on_root(PCH_DEVFN_SATA); + if (dev) { + params->SataEnable = dev->enabled; + params->SataMode = config->SataMode; + params->SataSalpSupport = config->SataSalpSupport; + + _Static_assert(ARRAY_SIZE(params->SataPortsEnable) >= + ARRAY_SIZE(config->SataPortsEnable), "copy buffer overflow!"); + memcpy(params->SataPortsEnable, config->SataPortsEnable, + sizeof(params->SataPortsEnable)); + + _Static_assert(ARRAY_SIZE(params->SataPortsDevSlp) >= + ARRAY_SIZE(config->SataPortsDevSlp), "copy buffer overflow!"); + memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, + sizeof(params->SataPortsDevSlp)); + } else { + params->SataEnable = 0; + } + /* SDCard related configuration */ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); if (!dev) { From 194695fd953a2a8bd10eedc9aa7811c338988d3d Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Mon, 27 Apr 2020 20:48:09 +0530 Subject: [PATCH 029/405] soc/intel/jasperlake: Remove deprecated UPDs IedSize and EnableC6Dram are removed in JSL FSP v2114 so remove them from 'fsp_params.c'. BUG=155054804 BRANCH=None TEST=Build and boot JSLRVP Change-Id: I47bd3f87bdb59625098c0d734695f02d738f8bbd Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/41239 Reviewed-by: Maulik V Vaghela Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/intel/jasperlake/romstage/fsp_params.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index 1393c44eed..d9063b0b0c 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -26,7 +26,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, } m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; - m_cfg->IedSize = CONFIG_IED_REGION_SIZE; m_cfg->SaGv = config->SaGv; m_cfg->RMT = config->RMT; @@ -49,7 +48,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, sizeof(config->PcieClkSrcClkReq)); m_cfg->PrmrrSize = config->PrmrrSize; - m_cfg->EnableC6Dram = config->enable_c6dram; /* Disable BIOS Guard */ m_cfg->BiosGuard = 0; From 5cb34e2ea0034f3d3781006234a0c8b66f4efcfe Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Mon, 4 May 2020 16:41:22 -0600 Subject: [PATCH 030/405] device/pci_device: Extract pci_domain_set_resources from SOC pci_domain_set_resources is duplicated in all the SOCs. This change promotes the duplicated function. Picasso was adding it again in the northbridge patch. I decided to promote the function instead of duplicating it. BUG=b:147042464 TEST=Build and boot trembyle. Signed-off-by: Raul E Rangel Change-Id: Iba9661ac2c3a1803783d5aa32404143c9144aea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41041 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/device/pci_device.c | 5 +++++ src/include/device/device.h | 1 + src/northbridge/intel/haswell/northbridge.c | 5 ----- src/northbridge/intel/ironlake/northbridge.c | 5 ----- src/northbridge/intel/sandybridge/northbridge.c | 4 ++-- src/soc/amd/picasso/chip.c | 2 +- src/soc/intel/apollolake/chip.c | 5 ----- src/soc/intel/baytrail/chip.c | 5 ----- src/soc/intel/braswell/chip.c | 6 ------ src/soc/intel/broadwell/chip.c | 5 ----- src/soc/intel/cannonlake/chip.c | 5 ----- src/soc/intel/denverton_ns/chip.c | 5 ----- src/soc/intel/icelake/chip.c | 5 ----- src/soc/intel/jasperlake/chip.c | 5 ----- src/soc/intel/quark/chip.c | 5 ----- src/soc/intel/skylake/chip.c | 5 ----- src/soc/intel/tigerlake/chip.c | 5 ----- src/soc/intel/xeon_sp/cpx/chip.c | 5 ----- 18 files changed, 9 insertions(+), 74 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 2c08ebc72e..05848717e2 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -439,6 +439,11 @@ void pci_domain_read_resources(struct device *dev) IORESOURCE_ASSIGNED; } +void pci_domain_set_resources(struct device *dev) +{ + assign_resources(dev->link_list); +} + static void pci_set_resource(struct device *dev, struct resource *resource) { resource_t base, end; diff --git a/src/include/device/device.h b/src/include/device/device.h index 72df751054..46efbfe679 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -256,6 +256,7 @@ void show_all_devs_resources(int debug_level, const char *msg); extern struct device_operations default_dev_ops_root; void pci_domain_read_resources(struct device *dev); +void pci_domain_set_resources(struct device *dev); void pci_domain_scan_bus(struct device *dev); void fixed_io_resource(struct device *dev, unsigned long index, diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 458439ef32..a728e0e8cf 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -52,11 +52,6 @@ static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 * return 0; } -static void pci_domain_set_resources(struct device *dev) -{ - assign_resources(dev->link_list); -} - static const char *northbridge_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index 07b8f53e61..d98af9edc9 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -67,11 +67,6 @@ static void add_fixed_resources(struct device *dev, int index) #endif } -static void pci_domain_set_resources(struct device *dev) -{ - assign_resources(dev->link_list); -} - #if CONFIG(HAVE_ACPI_TABLES) static const char *northbridge_acpi_name(const struct device *dev) { diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index b3772189b2..7a6372c207 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -99,7 +99,7 @@ static void add_fixed_resources(struct device *dev, int index) } } -static void pci_domain_set_resources(struct device *dev) +static void pci_domain_set_resources_sandybridge(struct device *dev) { uint64_t tom, me_base, touud; uint32_t tseg_base, uma_size, tolud; @@ -243,7 +243,7 @@ static const char *northbridge_acpi_name(const struct device *dev) */ static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, + .set_resources = pci_domain_set_resources_sandybridge, .scan_bus = pci_domain_scan_bus, .write_acpi_tables = northbridge_write_acpi_tables, .acpi_name = northbridge_acpi_name, diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 2e0ba7eaf3..05106f569b 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -78,7 +78,7 @@ const char *soc_acpi_name(const struct device *dev) struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, - .set_resources = domain_set_resources, + .set_resources = pci_domain_set_resources, .scan_bus = pci_domain_scan_bus, .acpi_name = soc_acpi_name, }; diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 778132e7ad..058222ce39 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -197,11 +197,6 @@ const char *soc_acpi_name(const struct device *dev) return NULL; } -static void pci_domain_set_resources(struct device *dev) -{ - assign_resources(dev->link_list); -} - static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index 7bb294b935..b7e3250a84 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -8,11 +8,6 @@ #include #include "chip.h" -static void pci_domain_set_resources(struct device *dev) -{ - assign_resources(dev->link_list); -} - static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index 727982677f..c81d307f52 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -10,12 +10,6 @@ #include "chip.h" -static void pci_domain_set_resources(struct device *dev) -{ - printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); - assign_resources(dev->link_list); -} - static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c index 740e65ed20..16afcce60c 100644 --- a/src/soc/intel/broadwell/chip.c +++ b/src/soc/intel/broadwell/chip.c @@ -7,11 +7,6 @@ #include #include -static void pci_domain_set_resources(struct device *dev) -{ - assign_resources(dev->link_list); -} - static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index a137762ad6..51678add67 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -168,11 +168,6 @@ void soc_init_pre_device(void *chip_info) soc_gpio_pm_configuration(); } -static void pci_domain_set_resources(struct device *dev) -{ - assign_resources(dev->link_list); -} - static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index f24335cecf..3bade119e6 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -17,11 +17,6 @@ #include #include -static void pci_domain_set_resources(struct device *dev) -{ - assign_resources(dev->link_list); -} - static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 176a8e4ea2..a455bfce71 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -124,11 +124,6 @@ void soc_init_pre_device(void *chip_info) soc_fill_gpio_pm_configuration(); } -static void pci_domain_set_resources(struct device *dev) -{ - assign_resources(dev->link_list); -} - static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c index 95585d2b9b..6f4ee005c7 100644 --- a/src/soc/intel/jasperlake/chip.c +++ b/src/soc/intel/jasperlake/chip.c @@ -133,11 +133,6 @@ void soc_init_pre_device(void *chip_info) soc_fill_gpio_pm_configuration(); } -static void pci_domain_set_resources(struct device *dev) -{ - assign_resources(dev->link_list); -} - static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index 0852a1a58e..33033a98b6 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -106,11 +106,6 @@ static void chip_init(void *chip_info) fsp_silicon_init(romstage_handoff_is_resume()); } -static void pci_domain_set_resources(struct device *dev) -{ - assign_resources(dev->link_list); -} - static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 4f799763c1..4ad691cb2e 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -78,11 +78,6 @@ void soc_fsp_load(void) fsps_load(romstage_handoff_is_resume()); } -static void pci_domain_set_resources(struct device *dev) -{ - assign_resources(dev->link_list); -} - static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 68b5f8996f..c1764cde93 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -132,11 +132,6 @@ void soc_init_pre_device(void *chip_info) soc_fill_gpio_pm_configuration(); } -static void pci_domain_set_resources(struct device *dev) -{ - assign_resources(dev->link_list); -} - static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index d986471889..2125f0a891 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -14,11 +14,6 @@ /* C620 IOAPIC has 120 redirection entries */ #define C620_IOAPIC_REDIR_ENTRIES 120 -static void pci_domain_set_resources(struct device *dev) -{ - assign_resources(dev->link_list); -} - void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) { /* not implemented yet */ From 04953ebf5f343dcb37e1288705a160b4cf1b64cf Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Fri, 27 Mar 2020 11:59:43 +0100 Subject: [PATCH 031/405] southbridge/intel/common: Add Process Call Add functionality to use process call cycle. It can be used to write/read data to/from e.g. EEPROM attached to SMBus Controller via I2C. Tested on: * C246 Change-Id: Ifdac6cf70a4ce744601f5d152a83d2125ea88360 Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/39875 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/include/device/smbus_host.h | 1 + src/southbridge/intel/common/smbus.c | 37 ++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/src/include/device/smbus_host.h b/src/include/device/smbus_host.h index 6e6163f062..d9390eaf2d 100644 --- a/src/include/device/smbus_host.h +++ b/src/include/device/smbus_host.h @@ -17,6 +17,7 @@ int do_smbus_write_word(uintptr_t base, u8 device, u8 address, u16 data); int do_smbus_block_read(uintptr_t base, u8 device, u8 cmd, size_t max_bytes, u8 *buf); int do_smbus_block_write(uintptr_t base, u8 device, u8 cmd, size_t bytes, const u8 *buf); +int do_smbus_process_call(uintptr_t base, u8 device, u8 cmd, u16 data, u16 *buf); /* For Intel, implemented since ICH5. */ int do_i2c_eeprom_read(uintptr_t base, u8 device, u8 offset, size_t bytes, u8 *buf); diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index 95c2fd0957..8b19b7d900 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -33,6 +33,7 @@ #define I801_BYTE (1 << 2) #define I801_BYTE_DATA (2 << 2) #define I801_WORD_DATA (3 << 2) +#define I801_PROCESS_CALL (4 << 2) #define I801_BLOCK_DATA (5 << 2) #define I801_I2C_BLOCK_DATA (6 << 2) /* ICH5 and later */ @@ -391,6 +392,42 @@ int do_smbus_block_read(uintptr_t base, u8 device, u8 cmd, size_t max_bytes, u8 return ret; } +/* + * The caller is responsible of settings HOSTC I2C_EN bit prior to making this + * call! + */ +int do_smbus_process_call(uintptr_t base, u8 device, u8 cmd, u16 data, u16 *buf) +{ + int ret; + + /* Set up for process call */ + ret = setup_command(base, I801_PROCESS_CALL, XMIT_WRITE(device)); + if (ret < 0) + return ret; + + /* cmd will only be send if I2C_EN is zero */ + host_outb(base, SMBHSTCMD, cmd); + + host_outb(base, SMBHSTDAT0, data & 0x00ff); + host_outb(base, SMBHSTDAT1, (data & 0xff00) >> 8); + + /* Start the command */ + ret = execute_command(base); + if (ret < 0) + return ret; + + /* Poll for transaction completion */ + ret = complete_command(base); + if (ret < 0) + return ret; + + /* Read results of transaction */ + *buf = host_inb(base, SMBHSTDAT0); + *buf |= (host_inb(base, SMBHSTDAT1) << 8); + + return ret; +} + int do_smbus_block_write(uintptr_t base, u8 device, u8 cmd, const size_t bytes, const u8 *buf) { int ret; From 79412ed3649ab423fb2eee73f971a928108fd041 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Wed, 6 May 2020 20:48:32 -0700 Subject: [PATCH 032/405] soc/intel/tigerlake: Correct IRQ interrupt Current Interrupt setting use 2nd parameters as device function number. - Correct as interrupt pin number according to _PRT package format. {Address, pin, Source, Source index} - Use irq number directly rather than irq definition as its number is not for PCI device. The issue found while enabling GBE and GBE interrupt is not working without this change. Reference - ACPI spec 6.2.13 _PRT - FSP reference code: https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/TGL.3163.01/ ClientOneSiliconPkg/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/ PeiItssPolicyLibVer2.c - BIOS reference code: https://github.com/otcshare/CCG-TGL-Generic-Full/blob/master/ TigerLakeBoardPkg/Acpi/AcpiTables/Dsdt/PciTree.asl TEST=boot to OS with GBE enabled and check GBE interrupt Signed-off-by: Wonkyu Kim Change-Id: I8084b30c668c155ebabbee90b5f70054813b328e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41153 Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/acpi/pci_irqs.asl | 236 +++++++++++----------- src/soc/intel/tigerlake/include/soc/irq.h | 60 ------ 2 files changed, 121 insertions(+), 175 deletions(-) diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl index 536c75a950..6f5f4bc3fd 100644 --- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl +++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl @@ -1,146 +1,152 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include - Name (PICP, Package () { - /* D31:HDA, SMBUS, TraceHUB */ - Package(){0x001FFFFF, 3, 0, HDA_IRQ }, - Package(){0x001FFFFF, 4, 0, SMBUS_IRQ }, - Package(){0x001FFFFF, 6, 0, GBE_IRQ }, - Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ }, - /* D30: UART0, UART1, SPI0, SPI1 */ - Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, - Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, - Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, - Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, - /* D29: RP9 ~ RP12 */ - Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ }, - Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ }, - Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ }, - Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ }, - /* D28: RP1 ~ RP8 */ - Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, - Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, - Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, - Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, - Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ }, - Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ }, - Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ }, - Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ }, - /* D25: I2C4, I2C5, UART2 */ - Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, - Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, - Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, - /* D23: SATA */ - Package(){0x0017FFFF, 0, 0, SATA_IRQ }, - /* D22: CSME */ - Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, - Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, - Package(){0x0016FFFF, 4, 0, HECI_3_IRQ }, - Package(){0x0016FFFF, 5, 0, HECI_4_IRQ }, - /* D21: I2C0 ~ I2C3 */ - Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, - Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, - Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, - Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, - /* D20: xHCI, xDCI, SRAM, CNVI_WIFI */ - Package(){0x0014FFFF, 0, 0, xHCI_IRQ }, - Package(){0x0014FFFF, 1, 0, xDCI_IRQ }, - Package(){0x0014FFFF, 3, 0, CNVI_WIFI_IRQ }, - /* D19: SPI3 */ - Package(){0x0013FFFF, 0, 0, LPSS_SPI3_IRQ }, - /* D18: ISH, SPI2 */ - Package(){0x0012FFFF, 0, 0, ISH_IRQ }, - Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ }, - /* D16: TCH0, TCH1 */ - Package(){0x0010FFFF, 6, 0, THC0_IRQ }, - Package(){0x0010FFFF, 7, 0, THC1_IRQ }, - /* D13: xHCI, xDCI */ - Package(){0x000DFFFF, 0, 0, xHCI_IRQ }, - Package(){0x000DFFFF, 1, 0, xDCI_IRQ }, - /* D8: GNA */ - Package(){0x0008FFFF, 0, 0, GNA_IRQ }, - /* D7: TBT PCIe */ - Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ }, - Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ }, - Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ }, - Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ }, - /* D6: PEG60 */ - Package(){0x0006FFFF, 0, 0, PEG_IRQ }, - /* D5: IPU Device */ - Package(){0x0005FFFF, 0, 0, IPU_IRQ }, - /* D4: Thermal Device */ - Package(){0x0004FFFF, 0, 0, THERMAL_IRQ }, - /* D2: IGFX */ - Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, + /* D31 */ + Package(){0x001FFFFF, 0, 0, 16 }, + /* D30 */ + Package(){0x001EFFFF, 0, 0, 16 }, + Package(){0x001EFFFF, 1, 0, 17 }, + Package(){0x001EFFFF, 2, 0, 36 }, + Package(){0x001EFFFF, 3, 0, 37 }, + /* D29 */ + Package(){0x001DFFFF, 0, 0, 16 }, + Package(){0x001DFFFF, 1, 0, 17 }, + Package(){0x001DFFFF, 2, 0, 18 }, + Package(){0x001DFFFF, 3, 0, 19 }, + /* D28 */ + Package(){0x001CFFFF, 0, 0, 16 }, + Package(){0x001CFFFF, 1, 0, 17 }, + Package(){0x001CFFFF, 2, 0, 18 }, + Package(){0x001CFFFF, 3, 0, 19 }, + /* D25 */ + Package(){0x0019FFFF, 0, 0, 31 }, + Package(){0x0019FFFF, 1, 0, 32 }, + Package(){0x0019FFFF, 2, 0, 33 }, + /* D23 */ + Package(){0x0017FFFF, 0, 0, 16 }, + /* D22 */ + Package(){0x0016FFFF, 0, 0, 16 }, + Package(){0x0016FFFF, 1, 0, 17 }, + Package(){0x0016FFFF, 2, 0, 18 }, + Package(){0x0016FFFF, 3, 0, 19 }, + /* D21 */ + Package(){0x0015FFFF, 0, 0, 27 }, + Package(){0x0015FFFF, 1, 0, 40 }, + Package(){0x0015FFFF, 2, 0, 29 }, + Package(){0x0015FFFF, 3, 0, 30 }, + /* D20 */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + /* D19 */ + Package(){0x0013FFFF, 0, 0, 43 }, + Package(){0x0013FFFF, 1, 0, 24 }, + Package(){0x0013FFFF, 2, 0, 25 }, + Package(){0x0013FFFF, 3, 0, 38 }, + /* D18 */ + Package(){0x0012FFFF, 0, 0, 16 }, + Package(){0x0012FFFF, 1, 0, 34 }, + /* D17 */ + Package(){0x0011FFFF, 0, 0, 35 }, + Package(){0x0011FFFF, 1, 0, 20 }, + Package(){0x0011FFFF, 2, 0, 21 }, + Package(){0x0011FFFF, 3, 0, 42 }, + /* D16 */ + Package(){0x0010FFFF, 0, 0, 23 }, + Package(){0x0010FFFF, 1, 0, 22 }, + Package(){0x0010FFFF, 2, 0, 18 }, + Package(){0x0010FFFF, 3, 0, 19 }, + /* D13 */ + Package(){0x000DFFFF, 0, 0, 16 }, + Package(){0x000DFFFF, 1, 0, 17 }, + /* D8 */ + Package(){0x0008FFFF, 0, 0, 16 }, + /* D7 */ + Package(){0x0007FFFF, 0, 0, 16 }, + Package(){0x0007FFFF, 1, 0, 17 }, + Package(){0x0007FFFF, 2, 0, 18 }, + Package(){0x0007FFFF, 3, 0, 19 }, + /* D6 */ + Package(){0x0006FFFF, 0, 0, 16 }, + /* D5 */ + Package(){0x0005FFFF, 0, 0, 16 }, + /* D4 */ + Package(){0x0004FFFF, 0, 0, 16 }, + /* D2 */ + Package(){0x0002FFFF, 0, 0, 16 }, }) Name (PICN, Package () { - /* D31:HDA, SMBUS, TraceHUB*/ - Package () { 0x001FFFFF, 3, 0, 11 }, - Package () { 0x001FFFFF, 4, 0, 11 }, - Package () { 0x001FFFFF, 7, 0, 11 }, - /* D30: UART0, UART1, SPI0, SPI1 */ - Package () { 0x001EFFFF, 0, 0, 11 }, - Package () { 0x001EFFFF, 1, 0, 10 }, - Package () { 0x001EFFFF, 2, 0, 11 }, - Package () { 0x001EFFFF, 3, 0, 11 }, - /* D29: RP9 ~ RP12 */ - Package () { 0x001DFFFF, 0, 0, 11 }, - Package () { 0x001DFFFF, 1, 0, 10 }, - Package () { 0x001DFFFF, 2, 0, 11 }, - Package () { 0x001DFFFF, 3, 0, 11 }, - /* D28: RP1 ~ RP8 */ - Package () { 0x001CFFFF, 0, 0, 11 }, - Package () { 0x001CFFFF, 1, 0, 10 }, - Package () { 0x001CFFFF, 2, 0, 11 }, - Package () { 0x001CFFFF, 3, 0, 11 }, - Package () { 0x001CFFFF, 4, 0, 11 }, - Package () { 0x001CFFFF, 5, 0, 10 }, - Package () { 0x001CFFFF, 6, 0, 11 }, - Package () { 0x001CFFFF, 7, 0, 11 }, - /* D25: I2C4, I2C5, UART2 */ + /* D31 */ + Package(){0x001FFFFF, 0, 0, 11 }, + /* D30 */ + Package(){0x001EFFFF, 0, 0, 11 }, + Package(){0x001EFFFF, 1, 0, 10 }, + Package(){0x001EFFFF, 2, 0, 11 }, + Package(){0x001EFFFF, 3, 0, 11 }, + /* D29 */ + Package(){0x001DFFFF, 0, 0, 11 }, + Package(){0x001DFFFF, 1, 0, 10 }, + Package(){0x001DFFFF, 2, 0, 11 }, + Package(){0x001DFFFF, 3, 0, 11 }, + /* D28 */ + Package(){0x001CFFFF, 0, 0, 11 }, + Package(){0x001CFFFF, 1, 0, 10 }, + Package(){0x001CFFFF, 2, 0, 11 }, + Package(){0x001CFFFF, 3, 0, 11 }, + /* D25 */ Package(){0x0019FFFF, 0, 0, 11 }, Package(){0x0019FFFF, 1, 0, 10 }, Package(){0x0019FFFF, 2, 0, 11 }, - /* D23: SATA */ - Package () { 0x0017FFFF, 0, 0, 11 }, - /* D22: CSME */ + /* D23 */ + Package(){0x0017FFFF, 0, 0, 11 }, + /* D22 */ Package(){0x0016FFFF, 0, 0, 11 }, Package(){0x0016FFFF, 1, 0, 10 }, - Package(){0x0016FFFF, 4, 0, 11 }, - Package(){0x0016FFFF, 5, 0, 11 }, - /* D21: I2C0 ~ I2C3 */ + Package(){0x0016FFFF, 2, 0, 11 }, + Package(){0x0016FFFF, 3, 0, 11 }, + /* D21 */ Package(){0x0015FFFF, 0, 0, 11 }, Package(){0x0015FFFF, 1, 0, 10 }, Package(){0x0015FFFF, 2, 0, 11 }, Package(){0x0015FFFF, 3, 0, 11 }, - /* D19: SPI3 */ + /* D20 */ + Package(){0x0014FFFF, 0, 0, 11 }, + Package(){0x0014FFFF, 0, 0, 10 }, + /* D19 */ Package(){0x0013FFFF, 0, 0, 11 }, - /* D18: ISH, SPI2 */ + Package(){0x0013FFFF, 1, 0, 10 }, + Package(){0x0013FFFF, 2, 0, 11 }, + Package(){0x0013FFFF, 3, 0, 11 }, + /* D18 */ Package(){0x0012FFFF, 0, 0, 11 }, - Package(){0x0012FFFF, 6, 0, 11 },, - /* D16: CNVI_BT, TCH0, TCH1 */ + Package(){0x0012FFFF, 1, 0, 10 },, + /* D18 */ + Package(){0x0011FFFF, 0, 0, 11 }, + Package(){0x0011FFFF, 1, 0, 10 }, + Package(){0x0011FFFF, 2, 0, 11 }, + Package(){0x0011FFFF, 3, 0, 11 }, + /* D16 */ + Package(){0x0010FFFF, 0, 0, 11 }, + Package(){0x0010FFFF, 1, 0, 10 }, Package(){0x0010FFFF, 2, 0, 11 }, - Package(){0x0010FFFF, 6, 0, 11 }, - Package(){0x0010FFFF, 7, 0, 10 }, - /* D13: xHCI, xDCI */ + Package(){0x0010FFFF, 3, 0, 11 }, + /* D13 */ Package(){0x000DFFFF, 0, 0, 11 }, Package(){0x000DFFFF, 1, 0, 10 }, - /* D8: GNA */ + /* D8 */ Package(){0x0008FFFF, 0, 0, 11 }, - /* D7: TBT PCIe */ + /* D7 */ Package(){0x0007FFFF, 0, 0, 11 }, Package(){0x0007FFFF, 1, 0, 10 }, Package(){0x0007FFFF, 2, 0, 11 }, Package(){0x0007FFFF, 3, 0, 11 }, - /* D6: PEG60 */ + /* D6 */ Package(){0x0006FFFF, 0, 0, 11 }, - /* D5: IPU Device */ + /* D5 */ Package(){0x0005FFFF, 0, 0, 11 }, - /* D4: Thermal Device */ + /* D4 */ Package(){0x0004FFFF, 0, 0, 11 }, - /* D2: IGFX */ + /* D2 */ Package(){0x0002FFFF, 0, 0, 11 }, }) diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h index 68428d8ab0..ad70290148 100644 --- a/src/soc/intel/tigerlake/include/soc/irq.h +++ b/src/soc/intel/tigerlake/include/soc/irq.h @@ -9,64 +9,4 @@ #define PCH_IRQ10 10 #define PCH_IRQ11 11 -#define LPSS_I2C0_IRQ 27 -#define LPSS_I2C1_IRQ 40 -#define LPSS_I2C2_IRQ 29 -#define LPSS_I2C3_IRQ 30 -#define LPSS_I2C4_IRQ 31 -#define LPSS_I2C5_IRQ 32 -#define LPSS_SPI0_IRQ 36 -#define LPSS_SPI1_IRQ 37 -#define LPSS_SPI2_IRQ 34 -#define LPSS_SPI3_IRQ 43 -#define LPSS_UART0_IRQ 16 -#define LPSS_UART1_IRQ 17 -#define LPSS_UART2_IRQ 33 - -#define HDA_IRQ 16 -#define GBE_IRQ 16 -#define SMBUS_IRQ 16 -#define TRACEHUB_IRQ 16 - -#define PCIE_1_IRQ 16 -#define PCIE_2_IRQ 17 -#define PCIE_3_IRQ 18 -#define PCIE_4_IRQ 19 -#define PCIE_5_IRQ 16 -#define PCIE_6_IRQ 17 -#define PCIE_7_IRQ 18 -#define PCIE_8_IRQ 19 -#define PCIE_9_IRQ 16 -#define PCIE_10_IRQ 17 -#define PCIE_11_IRQ 18 -#define PCIE_12_IRQ 19 - -#define SATA_IRQ 16 - -#define xHCI_IRQ 16 -#define xDCI_IRQ 17 -#define CNVI_WIFI_IRQ 16 - -#define CNVI_BT_IRQ 18 - -#define THC0_IRQ 23 -#define THC1_IRQ 22 - -#define ISH_IRQ 16 - -#define TBT_PCIe0_IRQ 16 -#define TBT_PCIe1_IRQ 17 -#define TBT_PCIe2_IRQ 18 -#define TBT_PCIe3_IRQ 19 - -#define HECI_1_IRQ 16 -#define HECI_2_IRQ 17 -#define HECI_3_IRQ 16 -#define HECI_4_IRQ 19 - -#define PEG_IRQ 16 -#define IGFX_IRQ 16 -#define THERMAL_IRQ 16 -#define IPU_IRQ 16 -#define GNA_IRQ 16 #endif /* _SOC_IRQ_H_ */ From 5819eab5a660f915e0d18dd7d948d2af2a231aa0 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Thu, 7 May 2020 13:16:32 +0200 Subject: [PATCH 033/405] soc/intel/skylake: Add ability to set root port ASPM The default setting of the root port ASPM configuration can be overridden from the device tree by using a non zero value. BUG=N/A TEST=tested on facebook monolith Change-Id: I85c545d5eacb10f43b94228f1caf1163028645e0 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/41171 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/soc/intel/skylake/chip.c | 5 ++++- src/soc/intel/skylake/chip.h | 10 ++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 4ad691cb2e..ce566cf7b5 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -182,8 +182,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(params->PcieRpLtrEnable)); memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, sizeof(params->PcieRpHotPlug)); - for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) + for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i]; + if (config->PcieRpAspm[i]) + params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1; + } /* * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index e279d335bd..eb6cf9d7bc 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -289,6 +289,16 @@ struct soc_intel_skylake_config { RpMaxPayload_256, } PcieRpMaxPayload[CONFIG_MAX_ROOT_PORTS]; + /* PCIE RP ASPM, ASPM support for the root port */ + enum { + AspmDefault, + AspmDisabled, + AspmL0s, + AspmL1, + AspmL0sL1, + AspmAutoConfig, + } PcieRpAspm[CONFIG_MAX_ROOT_PORTS]; + /* USB related */ struct usb2_port_config usb2_ports[16]; struct usb3_port_config usb3_ports[10]; From 3f3f53cd5e05eead7a8b8616244a4665bd14b22b Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Wed, 6 May 2020 11:47:04 -0600 Subject: [PATCH 034/405] util/sconfig: Add LPC and ESPI buses Picasso has an LPC and eSPI bridge on the same PCI DEVFN. They can both be active at the same time. This adds a way to specify which devices belong on which bus. i.e., device pci 14.3 on # - D14F3 bridge device espi 0 on chip ec/google/chromeec device pnp 0c09.0 on end end end device lpc 0 on end end BUG=b:154445472 TEST=Built trembyle and saw static.c contained the espi bus. Signed-off-by: Raul E Rangel Change-Id: I0c2f40813c05680f72e5f30cbb13617e8f994841 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41099 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/device/device_const.c | 6 + src/device/device_util.c | 8 + src/include/device/path.h | 14 ++ util/sconfig/lex.yy.c_shipped | 269 +++++++++++++++-------------- util/sconfig/main.c | 8 + util/sconfig/sconfig.l | 2 + util/sconfig/sconfig.tab.c_shipped | 34 ++-- util/sconfig/sconfig.tab.h_shipped | 4 +- util/sconfig/sconfig.y | 2 +- 9 files changed, 200 insertions(+), 147 deletions(-) diff --git a/src/device/device_const.c b/src/device/device_const.c index 65ec15729a..3ad00f8838 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -156,6 +156,12 @@ static int path_eq(const struct device_path *path1, case DEVICE_PATH_MMIO: equal = (path1->mmio.addr == path2->mmio.addr); break; + case DEVICE_PATH_ESPI: + equal = (path1->espi.addr == path2->espi.addr); + break; + case DEVICE_PATH_LPC: + equal = (path1->lpc.addr == path2->lpc.addr); + break; default: printk(BIOS_ERR, "Unknown device type: %d\n", path1->type); break; diff --git a/src/device/device_util.c b/src/device/device_util.c index 5aa53c1daf..88608597f2 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -215,6 +215,14 @@ const char *dev_path(const struct device *dev) snprintf(buffer, sizeof(buffer), "MMIO: %08lx", dev->path.mmio.addr); break; + case DEVICE_PATH_ESPI: + snprintf(buffer, sizeof(buffer), "ESPI: %08lx", + dev->path.espi.addr); + break; + case DEVICE_PATH_LPC: + snprintf(buffer, sizeof(buffer), "LPC: %08lx", + dev->path.lpc.addr); + break; default: printk(BIOS_ERR, "Unknown device path type: %d\n", dev->path.type); diff --git a/src/include/device/path.h b/src/include/device/path.h index 6736bede69..964b4725fc 100644 --- a/src/include/device/path.h +++ b/src/include/device/path.h @@ -19,6 +19,8 @@ enum device_path_type { DEVICE_PATH_SPI, DEVICE_PATH_USB, DEVICE_PATH_MMIO, + DEVICE_PATH_ESPI, + DEVICE_PATH_LPC, /* * When adding path types to this table, please also update the @@ -42,6 +44,8 @@ enum device_path_type { "DEVICE_PATH_SPI", \ "DEVICE_PATH_USB", \ "DEVICE_PATH_MMIO", \ + "DEVICE_PATH_ESPI", \ + "DEVICE_PATH_LPC", \ } struct domain_path { @@ -104,6 +108,14 @@ struct mmio_path { uintptr_t addr; }; +struct espi_path { + uintptr_t addr; +}; + +struct lpc_path { + uintptr_t addr; +}; + struct device_path { enum device_path_type type; union { @@ -120,6 +132,8 @@ struct device_path { struct spi_path spi; struct usb_path usb; struct mmio_path mmio; + struct espi_path espi; + struct lpc_path lpc; }; }; diff --git a/util/sconfig/lex.yy.c_shipped b/util/sconfig/lex.yy.c_shipped index 63297732fa..61928e6397 100644 --- a/util/sconfig/lex.yy.c_shipped +++ b/util/sconfig/lex.yy.c_shipped @@ -159,8 +159,10 @@ extern FILE *yyin, *yyout; #define EOB_ACT_CONTINUE_SCAN 0 #define EOB_ACT_END_OF_FILE 1 #define EOB_ACT_LAST_MATCH 2 + #define YY_LESS_LINENO(n) #define YY_LINENO_REWIND_TO(ptr) + /* Return all but the first "n" matched characters back to the input stream. */ #define yyless(n) \ do \ @@ -347,8 +349,8 @@ static void yynoreturn yy_fatal_error ( const char* msg ); (yy_hold_char) = *yy_cp; \ *yy_cp = '\0'; \ (yy_c_buf_p) = yy_cp; -#define YY_NUM_RULES 39 -#define YY_END_OF_BUFFER 40 +#define YY_NUM_RULES 41 +#define YY_END_OF_BUFFER 42 /* This struct is not used in this scanner, but its presence is necessary. */ struct yy_trans_info @@ -356,26 +358,27 @@ struct yy_trans_info flex_int32_t yy_verify; flex_int32_t yy_nxt; }; -static const flex_int16_t yy_accept[168] = +static const flex_int16_t yy_accept[173] = { 0, - 0, 0, 40, 38, 1, 3, 38, 38, 38, 33, - 33, 31, 34, 38, 34, 34, 34, 38, 38, 38, - 38, 38, 38, 38, 38, 38, 38, 38, 1, 3, - 38, 0, 38, 38, 0, 2, 33, 34, 38, 38, - 38, 38, 34, 38, 38, 38, 38, 38, 38, 38, - 25, 38, 38, 38, 38, 38, 7, 38, 38, 38, - 38, 38, 38, 38, 37, 37, 38, 0, 32, 38, - 38, 17, 38, 38, 24, 29, 38, 38, 14, 38, - 38, 23, 38, 38, 38, 8, 11, 13, 38, 38, - 21, 38, 22, 38, 0, 35, 4, 38, 38, 38, + 0, 0, 42, 40, 1, 3, 40, 40, 40, 35, + 35, 33, 36, 40, 36, 36, 36, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 1, 3, + 40, 0, 40, 40, 0, 2, 35, 36, 40, 40, + 40, 40, 36, 40, 40, 40, 40, 40, 40, 40, + 40, 27, 40, 40, 40, 40, 40, 40, 7, 40, + 40, 40, 40, 40, 40, 40, 39, 39, 40, 0, + 34, 40, 40, 17, 40, 40, 26, 31, 40, 40, + 40, 14, 40, 40, 25, 40, 23, 40, 40, 8, + 11, 13, 40, 40, 21, 40, 22, 40, 0, 37, - 38, 38, 38, 38, 38, 38, 20, 38, 38, 38, - 36, 36, 38, 38, 38, 38, 38, 38, 38, 15, - 38, 38, 38, 38, 38, 5, 18, 38, 9, 38, - 12, 38, 38, 38, 38, 38, 19, 27, 38, 38, - 38, 38, 38, 38, 38, 38, 6, 38, 38, 38, - 38, 10, 38, 38, 38, 26, 38, 38, 16, 38, - 28, 38, 38, 38, 38, 30, 0 + 4, 40, 40, 40, 24, 40, 40, 40, 40, 40, + 40, 20, 40, 40, 40, 38, 38, 40, 40, 40, + 40, 40, 40, 40, 15, 40, 40, 40, 40, 40, + 5, 18, 40, 9, 40, 12, 40, 40, 40, 40, + 40, 19, 29, 40, 40, 40, 40, 40, 40, 40, + 40, 6, 40, 40, 40, 40, 10, 40, 40, 40, + 28, 40, 40, 16, 40, 30, 40, 40, 40, 40, + 32, 0 } ; static const YY_CHAR yy_ec[256] = @@ -418,118 +421,118 @@ static const YY_CHAR yy_meta[39] = 1, 1, 1, 1, 1, 1, 1, 1 } ; -static const flex_int16_t yy_base[175] = +static const flex_int16_t yy_base[180] = { 0, - 0, 0, 235, 0, 232, 236, 230, 37, 41, 38, - 195, 0, 44, 217, 54, 78, 60, 209, 204, 45, - 211, 48, 42, 52, 206, 62, 193, 0, 223, 236, - 88, 219, 93, 79, 220, 236, 0, 93, 104, 207, - 196, 185, 96, 192, 187, 197, 188, 195, 195, 189, - 195, 180, 180, 181, 183, 185, 0, 181, 175, 181, - 185, 177, 183, 182, 0, 236, 115, 194, 0, 187, - 167, 180, 170, 177, 0, 0, 172, 172, 0, 170, - 160, 0, 164, 168, 158, 0, 0, 0, 161, 160, - 0, 151, 0, 178, 177, 0, 0, 162, 161, 154, + 0, 0, 240, 0, 237, 241, 235, 37, 41, 38, + 200, 0, 44, 222, 54, 78, 60, 214, 209, 45, + 49, 48, 42, 52, 212, 62, 199, 0, 229, 241, + 93, 225, 98, 79, 226, 241, 0, 97, 104, 213, + 202, 191, 110, 198, 193, 203, 192, 193, 200, 200, + 194, 200, 185, 185, 195, 185, 187, 189, 0, 185, + 179, 185, 189, 181, 187, 186, 0, 241, 125, 198, + 0, 191, 171, 184, 174, 181, 0, 0, 172, 175, + 175, 0, 173, 163, 0, 167, 0, 171, 161, 0, + 0, 0, 164, 163, 0, 154, 0, 181, 180, 0, - 146, 156, 144, 150, 155, 156, 0, 139, 142, 132, - 0, 236, 143, 147, 139, 141, 137, 139, 144, 0, - 128, 127, 127, 126, 123, 0, 0, 138, 0, 122, - 139, 125, 132, 136, 117, 117, 0, 0, 124, 116, - 115, 113, 124, 97, 98, 91, 0, 102, 100, 98, - 83, 0, 80, 83, 74, 0, 60, 63, 0, 63, - 0, 56, 51, 33, 29, 0, 236, 40, 132, 134, - 136, 138, 140, 142 + 0, 165, 164, 157, 0, 149, 159, 147, 153, 158, + 159, 0, 142, 145, 135, 0, 241, 146, 150, 142, + 144, 140, 142, 147, 0, 131, 130, 130, 129, 126, + 0, 0, 141, 0, 125, 129, 115, 122, 126, 107, + 107, 0, 0, 114, 106, 105, 103, 114, 100, 101, + 94, 0, 105, 102, 99, 83, 0, 80, 83, 70, + 0, 60, 71, 0, 74, 0, 63, 55, 39, 29, + 0, 241, 40, 146, 148, 150, 152, 154, 156 } ; -static const flex_int16_t yy_def[175] = +static const flex_int16_t yy_def[180] = { 0, - 167, 1, 167, 168, 167, 167, 168, 169, 170, 168, - 10, 168, 10, 168, 10, 10, 10, 168, 168, 168, - 168, 168, 168, 168, 168, 168, 168, 168, 167, 167, - 169, 171, 172, 170, 173, 167, 10, 10, 10, 168, - 168, 168, 10, 168, 168, 168, 168, 168, 168, 168, - 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, - 168, 168, 168, 168, 168, 167, 172, 174, 39, 168, - 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, - 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, - 168, 168, 168, 168, 167, 168, 168, 168, 168, 168, + 172, 1, 172, 173, 172, 172, 173, 174, 175, 173, + 10, 173, 10, 173, 10, 10, 10, 173, 173, 173, + 173, 173, 173, 173, 173, 173, 173, 173, 172, 172, + 174, 176, 177, 175, 178, 172, 10, 10, 10, 173, + 173, 173, 10, 173, 173, 173, 173, 173, 173, 173, + 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, + 173, 173, 173, 173, 173, 173, 173, 172, 177, 179, + 39, 173, 173, 173, 173, 173, 173, 173, 173, 173, + 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, + 173, 173, 173, 173, 173, 173, 173, 173, 172, 173, - 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, - 168, 167, 168, 168, 168, 168, 168, 168, 168, 168, - 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, - 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, - 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, - 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, - 168, 168, 168, 168, 168, 168, 0, 167, 167, 167, - 167, 167, 167, 167 + 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, + 173, 173, 173, 173, 173, 173, 172, 173, 173, 173, + 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, + 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, + 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, + 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, + 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, + 173, 0, 172, 172, 172, 172, 172, 172, 172 } ; -static const flex_int16_t yy_nxt[275] = +static const flex_int16_t yy_nxt[280] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 10, 12, 13, 13, 14, 4, 4, 4, 13, 13, 15, 16, 17, 13, 18, 19, 20, 21, 22, 4, 23, 24, 4, 25, 26, 4, 27, 4, 4, 4, 32, 32, - 28, 33, 35, 36, 37, 37, 37, 166, 38, 38, - 38, 38, 38, 49, 38, 38, 38, 38, 38, 38, - 38, 38, 38, 56, 54, 165, 38, 38, 38, 57, - 58, 164, 50, 51, 55, 163, 52, 41, 162, 59, - 35, 36, 161, 42, 38, 38, 38, 46, 61, 32, - 32, 62, 65, 160, 68, 68, 63, 28, 43, 38, + 28, 33, 35, 36, 37, 37, 37, 171, 38, 38, + 38, 38, 38, 50, 38, 38, 38, 38, 38, 38, + 38, 38, 38, 58, 56, 54, 38, 38, 38, 59, + 60, 170, 51, 52, 57, 169, 53, 41, 55, 61, + 35, 36, 168, 42, 38, 38, 38, 46, 63, 167, + 166, 64, 47, 165, 32, 32, 65, 67, 43, 70, - 38, 38, 38, 38, 38, 159, 44, 158, 157, 45, - 69, 69, 69, 156, 69, 69, 68, 68, 155, 94, - 69, 69, 69, 69, 69, 69, 154, 153, 152, 151, - 150, 73, 31, 31, 34, 34, 32, 32, 67, 67, - 35, 35, 68, 68, 149, 148, 147, 146, 145, 144, - 143, 142, 141, 140, 139, 138, 137, 136, 135, 134, - 133, 132, 131, 130, 129, 128, 127, 126, 125, 124, - 123, 122, 121, 120, 119, 118, 117, 116, 115, 114, - 113, 112, 111, 110, 109, 108, 107, 106, 105, 104, - 103, 102, 101, 100, 99, 98, 97, 96, 95, 93, + 70, 164, 28, 38, 38, 38, 44, 163, 162, 45, + 71, 71, 71, 161, 71, 71, 38, 38, 38, 160, + 71, 71, 71, 71, 71, 71, 70, 70, 159, 98, + 158, 157, 156, 155, 154, 153, 152, 151, 150, 149, + 148, 147, 146, 145, 144, 75, 31, 31, 34, 34, + 32, 32, 69, 69, 35, 35, 70, 70, 143, 142, + 141, 140, 139, 138, 137, 136, 135, 134, 133, 132, + 131, 130, 129, 128, 127, 126, 125, 124, 123, 122, + 121, 120, 119, 118, 117, 116, 115, 114, 113, 112, + 111, 110, 109, 108, 107, 106, 105, 104, 103, 102, - 92, 91, 90, 89, 88, 87, 86, 85, 84, 83, - 82, 81, 80, 79, 78, 77, 76, 75, 74, 72, - 71, 70, 36, 66, 29, 64, 60, 53, 48, 47, - 40, 39, 30, 29, 167, 3, 167, 167, 167, 167, - 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, - 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, - 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, - 167, 167, 167, 167 + 101, 100, 99, 97, 96, 95, 94, 93, 92, 91, + 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, + 80, 79, 78, 77, 76, 74, 73, 72, 36, 68, + 29, 66, 62, 49, 48, 40, 39, 30, 29, 172, + 3, 172, 172, 172, 172, 172, 172, 172, 172, 172, + 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, + 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, + 172, 172, 172, 172, 172, 172, 172, 172, 172 } ; -static const flex_int16_t yy_chk[275] = +static const flex_int16_t yy_chk[280] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 8, 8, - 168, 8, 9, 9, 10, 10, 10, 165, 10, 10, + 173, 8, 9, 9, 10, 10, 10, 170, 10, 10, 13, 13, 13, 20, 10, 10, 10, 10, 10, 10, - 15, 15, 15, 23, 22, 164, 17, 17, 17, 23, - 24, 163, 20, 20, 22, 162, 20, 15, 160, 24, - 34, 34, 158, 15, 16, 16, 16, 17, 26, 31, - 31, 26, 31, 157, 33, 33, 26, 33, 16, 38, + 15, 15, 15, 23, 22, 21, 17, 17, 17, 23, + 24, 169, 20, 20, 22, 168, 20, 15, 21, 24, + 34, 34, 167, 15, 16, 16, 16, 17, 26, 165, + 163, 26, 17, 162, 31, 31, 26, 31, 16, 33, - 38, 38, 43, 43, 43, 155, 16, 154, 153, 16, - 39, 39, 39, 151, 39, 39, 67, 67, 150, 67, - 39, 39, 39, 39, 39, 39, 149, 148, 146, 145, - 144, 43, 169, 169, 170, 170, 171, 171, 172, 172, - 173, 173, 174, 174, 143, 142, 141, 140, 139, 136, - 135, 134, 133, 132, 131, 130, 128, 125, 124, 123, - 122, 121, 119, 118, 117, 116, 115, 114, 113, 110, - 109, 108, 106, 105, 104, 103, 102, 101, 100, 99, - 98, 95, 94, 92, 90, 89, 85, 84, 83, 81, - 80, 78, 77, 74, 73, 72, 71, 70, 68, 64, + 33, 160, 33, 38, 38, 38, 16, 159, 158, 16, + 39, 39, 39, 156, 39, 39, 43, 43, 43, 155, + 39, 39, 39, 39, 39, 39, 69, 69, 154, 69, + 153, 151, 150, 149, 148, 147, 146, 145, 144, 141, + 140, 139, 138, 137, 136, 43, 174, 174, 175, 175, + 176, 176, 177, 177, 178, 178, 179, 179, 135, 133, + 130, 129, 128, 127, 126, 124, 123, 122, 121, 120, + 119, 118, 115, 114, 113, 111, 110, 109, 108, 107, + 106, 104, 103, 102, 99, 98, 96, 94, 93, 89, + 88, 86, 84, 83, 81, 80, 79, 76, 75, 74, - 63, 62, 61, 60, 59, 58, 56, 55, 54, 53, - 52, 51, 50, 49, 48, 47, 46, 45, 44, 42, - 41, 40, 35, 32, 29, 27, 25, 21, 19, 18, - 14, 11, 7, 5, 3, 167, 167, 167, 167, 167, - 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, - 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, - 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, - 167, 167, 167, 167 + 73, 72, 70, 66, 65, 64, 63, 62, 61, 60, + 58, 57, 56, 55, 54, 53, 52, 51, 50, 49, + 48, 47, 46, 45, 44, 42, 41, 40, 35, 32, + 29, 27, 25, 19, 18, 14, 11, 7, 5, 3, + 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, + 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, + 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, + 172, 172, 172, 172, 172, 172, 172, 172, 172 } ; static yy_state_type yy_last_accepting_state; @@ -807,13 +810,13 @@ yy_match: while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 168 ) + if ( yy_current_state >= 173 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; ++yy_cp; } - while ( yy_base[yy_current_state] != 236 ); + while ( yy_base[yy_current_state] != 241 ); yy_find_action: yy_act = yy_accept[yy_current_state]; @@ -929,47 +932,47 @@ YY_RULE_SETUP YY_BREAK case 23: YY_RULE_SETUP -{yylval.number=IRQ; return(RESOURCE);} +{yylval.number=LPC; return(BUS);} YY_BREAK case 24: YY_RULE_SETUP -{yylval.number=DRQ; return(RESOURCE);} +{yylval.number=ESPI; return(BUS);} YY_BREAK case 25: YY_RULE_SETUP -{yylval.number=IO; return(RESOURCE);} +{yylval.number=IRQ; return(RESOURCE);} YY_BREAK case 26: YY_RULE_SETUP -{return(IOAPIC_IRQ);} +{yylval.number=DRQ; return(RESOURCE);} YY_BREAK case 27: YY_RULE_SETUP -{return(INHERIT);} +{yylval.number=IO; return(RESOURCE);} YY_BREAK case 28: YY_RULE_SETUP -{return(SUBSYSTEMID);} +{return(IOAPIC_IRQ);} YY_BREAK case 29: YY_RULE_SETUP -{return(END);} +{return(INHERIT);} YY_BREAK case 30: YY_RULE_SETUP -{return(SLOT_DESC);} +{return(SUBSYSTEMID);} YY_BREAK case 31: YY_RULE_SETUP -{return(EQUALS);} +{return(END);} YY_BREAK case 32: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +{return(SLOT_DESC);} YY_BREAK case 33: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +{return(EQUALS);} YY_BREAK case 34: YY_RULE_SETUP @@ -977,23 +980,31 @@ YY_RULE_SETUP YY_BREAK case 35: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} YY_BREAK case 36: -/* rule 36 can match eol */ YY_RULE_SETUP -{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} YY_BREAK case 37: -/* rule 37 can match eol */ +YY_RULE_SETUP +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} + YY_BREAK +case 38: +/* rule 38 can match eol */ YY_RULE_SETUP {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} YY_BREAK -case 38: +case 39: +/* rule 39 can match eol */ +YY_RULE_SETUP +{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} + YY_BREAK +case 40: YY_RULE_SETUP {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} YY_BREAK -case 39: +case 41: YY_RULE_SETUP ECHO; YY_BREAK @@ -1293,7 +1304,7 @@ static int yy_get_next_buffer (void) while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 168 ) + if ( yy_current_state >= 173 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; @@ -1321,11 +1332,11 @@ static int yy_get_next_buffer (void) while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 168 ) + if ( yy_current_state >= 173 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; - yy_is_jam = (yy_current_state == 167); + yy_is_jam = (yy_current_state == 172); return yy_is_jam ? 0 : yy_current_state; } diff --git a/util/sconfig/main.c b/util/sconfig/main.c index b0c53385c6..6676baea90 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -493,6 +493,14 @@ struct device *new_device(struct bus *parent, case MMIO: new_d->path = ".type=DEVICE_PATH_MMIO,{.mmio={ .addr = 0x%x }}"; break; + + case ESPI: + new_d->path = ".type=DEVICE_PATH_ESPI,{.espi={ .addr = 0x%x }}"; + break; + + case LPC: + new_d->path = ".type=DEVICE_PATH_LPC,{.lpc={ .addr = 0x%x }}"; + break; } return new_d; diff --git a/util/sconfig/sconfig.l b/util/sconfig/sconfig.l index 9fd0cec0e9..5ac5057e23 100755 --- a/util/sconfig/sconfig.l +++ b/util/sconfig/sconfig.l @@ -30,6 +30,8 @@ generic {yylval.number=GENERIC; return(BUS);} mmio {yylval.number=MMIO; return(BUS);} spi {yylval.number=SPI; return(BUS);} usb {yylval.number=USB; return(BUS);} +lpc {yylval.number=LPC; return(BUS);} +espi {yylval.number=ESPI; return(BUS);} irq {yylval.number=IRQ; return(RESOURCE);} drq {yylval.number=DRQ; return(RESOURCE);} io {yylval.number=IO; return(RESOURCE);} diff --git a/util/sconfig/sconfig.tab.c_shipped b/util/sconfig/sconfig.tab.c_shipped index fb7e3f710f..2bae43bc29 100644 --- a/util/sconfig/sconfig.tab.c_shipped +++ b/util/sconfig/sconfig.tab.c_shipped @@ -158,7 +158,9 @@ extern int yydebug; GENERIC = 287, SPI = 288, USB = 289, - MMIO = 290 + MMIO = 290, + LPC = 291, + ESPI = 292 }; #endif @@ -493,7 +495,7 @@ union yyalloc #define YYLAST 45 /* YYNTOKENS -- Number of terminals. */ -#define YYNTOKENS 36 +#define YYNTOKENS 38 /* YYNNTS -- Number of nonterminals. */ #define YYNNTS 15 /* YYNRULES -- Number of rules. */ @@ -502,7 +504,7 @@ union yyalloc #define YYNSTATES 50 #define YYUNDEFTOK 2 -#define YYMAXUTOK 290 +#define YYMAXUTOK 292 /* YYTRANSLATE(TOKEN-NUM) -- Symbol number corresponding to TOKEN-NUM @@ -543,7 +545,7 @@ static const yytype_int8 yytranslate[] = 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, - 35 + 35, 36, 37 }; #if YYDEBUG @@ -565,10 +567,10 @@ static const char *const yytname[] = "STATUS", "MANDATORY", "BUS", "RESOURCE", "END", "EQUALS", "HEX", "STRING", "PCI", "PNP", "I2C", "APIC", "CPU_CLUSTER", "CPU", "DOMAIN", "IRQ", "DRQ", "SLOT_DESC", "IO", "NUMBER", "SUBSYSTEMID", "INHERIT", - "IOAPIC_IRQ", "IOAPIC", "PCIINT", "GENERIC", "SPI", "USB", "MMIO", - "$accept", "devtree", "$@1", "chipchildren", "devicechildren", "chip", - "@2", "device", "@3", "status", "resource", "registers", "subsystemid", - "ioapic_irq", "smbios_slot_desc", YY_NULLPTR + "IOAPIC_IRQ", "IOAPIC", "PCIINT", "GENERIC", "SPI", "USB", "MMIO", "LPC", + "ESPI", "$accept", "devtree", "$@1", "chipchildren", "devicechildren", + "chip", "@2", "device", "@3", "status", "resource", "registers", + "subsystemid", "ioapic_irq", "smbios_slot_desc", YY_NULLPTR }; #endif @@ -580,7 +582,7 @@ static const yytype_int16 yytoknum[] = 0, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, - 285, 286, 287, 288, 289, 290 + 285, 286, 287, 288, 289, 290, 291, 292 }; # endif @@ -656,19 +658,19 @@ static const yytype_int8 yycheck[] = symbol of state STATE-NUM. */ static const yytype_int8 yystos[] = { - 0, 37, 38, 0, 3, 41, 14, 42, 39, 4, - 5, 11, 41, 43, 47, 9, 14, 26, 12, 6, - 7, 45, 14, 44, 40, 10, 11, 24, 27, 29, - 41, 43, 46, 47, 48, 49, 50, 26, 14, 26, + 0, 39, 40, 0, 3, 43, 14, 44, 41, 4, + 5, 11, 43, 45, 49, 9, 14, 26, 12, 6, + 7, 47, 14, 46, 42, 10, 11, 24, 27, 29, + 43, 45, 48, 49, 50, 51, 52, 26, 14, 26, 26, 12, 14, 26, 31, 26, 14, 28, 26, 14 }; /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ static const yytype_int8 yyr1[] = { - 0, 36, 38, 37, 39, 39, 39, 39, 40, 40, - 40, 40, 40, 40, 40, 40, 42, 41, 44, 43, - 45, 45, 46, 47, 48, 48, 49, 50, 50, 50 + 0, 38, 40, 39, 41, 41, 41, 41, 42, 42, + 42, 42, 42, 42, 42, 42, 44, 43, 46, 45, + 47, 47, 48, 49, 50, 50, 51, 52, 52, 52 }; /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */ diff --git a/util/sconfig/sconfig.tab.h_shipped b/util/sconfig/sconfig.tab.h_shipped index f93daea392..5fa9d19362 100644 --- a/util/sconfig/sconfig.tab.h_shipped +++ b/util/sconfig/sconfig.tab.h_shipped @@ -81,7 +81,9 @@ extern int yydebug; GENERIC = 287, SPI = 288, USB = 289, - MMIO = 290 + MMIO = 290, + LPC = 291, + ESPI = 292 }; #endif diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index 597e309a42..161cf81551 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -18,7 +18,7 @@ static struct chip_instance *cur_chip_instance; int number; } -%token CHIP DEVICE REGISTER BOOL STATUS MANDATORY BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESC IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO +%token CHIP DEVICE REGISTER BOOL STATUS MANDATORY BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESC IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO LPC ESPI %% devtree: { cur_parent = root_parent; } chip; From 6d28802d32c397650fadd556afe98da36e489473 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 11 May 2020 16:35:08 -0700 Subject: [PATCH 035/405] soc/amd/common/block/lpc: Add helper function lpc_early_init() This change adds a helper function lpc_early_init() which does the following things: 1. Enables LPC controller 2. Disables any LPC decodes (These can be set up later by SoC or mainboard as required). 3. Sets SPI base so that MMIO base for SPI and eSPI controllers is initialized. BUG=b:153675913 Signed-off-by: Furquan Shaikh Change-Id: I016f29339466c3fee92fe9b62a13d72297c29b8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41257 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Raul Rangel --- .../amd/common/block/include/amdblocks/lpc.h | 9 +++++++++ src/soc/amd/common/block/lpc/lpc_util.c | 18 ++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 00210a7fe1..11acc78228 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -180,6 +180,15 @@ int lpc_set_wideio_range(uint16_t start, uint16_t size); uintptr_t lpc_get_spibase(void); +/* + * Perform early initialization for LPC: + * 1. Enable LPC controller + * 2. Disable any LPC decodes + * 3. Set SPI Base which is the MMIO base for both SPI and eSPI controller (if supported by + * platform). + */ +void lpc_early_init(void); + /* * Sets MMIO base address for SPI controller and eSPI controller (if supported by platform). * diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index 2c47a8549a..d2a65c8c96 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -349,3 +350,20 @@ void lpc_enable_spi_rom(uint32_t enable) pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, reg32); } + +static void lpc_enable_controller(void) +{ + u8 byte; + + /* Enable LPC controller */ + byte = pm_io_read8(PM_LPC_GATING); + byte |= PM_LPC_ENABLE; + pm_io_write8(PM_LPC_GATING, byte); +} + +void lpc_early_init(void) +{ + lpc_enable_controller(); + lpc_disable_decodes(); + lpc_set_spibase(SPI_BASE_ADDRESS); +} From ad4fb6e569d276574ef641d36d8cf02e5e2984e9 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 9 May 2020 19:44:52 -0700 Subject: [PATCH 036/405] soc/amd/common/block/spi: Include mmio.h in fch_spi_ctrl.c fch_spi_ctrl.c uses read*()/write*() functions which are declared in arch/mmio.h. This change includes the file arch/mmio.h in fch_spi_ctrl.c. Signed-off-by: Furquan Shaikh Change-Id: I6540004512af1f59f5fb300a3a4818b87ad94bfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/41271 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Raul Rangel --- src/soc/amd/common/block/spi/fch_spi_ctrl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index b048f1cbf7..13ad0cd32d 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include From ca203f85a061d7c17a0b24a0c2f37eb3d44d7a0e Mon Sep 17 00:00:00 2001 From: Tommie Date: Thu, 30 Apr 2020 15:21:47 +0800 Subject: [PATCH 037/405] mb/google/octopus/variants/foob: Disable xHCI compliance mode When any USB image disk is connected to the DUT through HUAWEI/APPLE Dongle, press Ctrl + u on the dev screen, it cannot boot from USB. We found the SS hub cannot be enumerated. So disable xHCI compliance mode. BRANCH=octopus BUG=b:155347573 TEST=Confirm successful boot from USB Change-Id: Iea4a3df156da0627336f7d6c1e03837b6cf0e7f2 Signed-off-by: tong.lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/40905 Reviewed-by: Marco Chen Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/mainboard/google/octopus/variants/foob/overridetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/octopus/variants/foob/overridetree.cb b/src/mainboard/google/octopus/variants/foob/overridetree.cb index 004076d047..4ec6fee1c9 100644 --- a/src/mainboard/google/octopus/variants/foob/overridetree.cb +++ b/src/mainboard/google/octopus/variants/foob/overridetree.cb @@ -162,4 +162,7 @@ chip soc/intel/apollolake end end # - I2C 7 end + + # Disable xHCI compliance mode + register "DisableComplianceMode" = "1" end From 9647903dfc8e52110582ed910bde6950bf4bc00d Mon Sep 17 00:00:00 2001 From: Ian Feng Date: Tue, 12 May 2020 11:19:33 +0800 Subject: [PATCH 038/405] mb/google/dedede/variants/waddledoo: Modify ELAN touchscreen slave address Modify ELAN EKTH6918 USI touchscreen slave address to 0x10. BUG=b:152936745 TEST="emerge-dedede coreboot chromeos-bootimage", build successful. Signed-off-by: Ian Feng Change-Id: I999967b0f37c82ff7811e3b6117baab795a11195 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41277 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/dedede/variants/waddledoo/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb index b9346af1fa..4546c9f026 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -105,7 +105,7 @@ chip soc/intel/jasperlake register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 15 on end + device i2c 10 on end end end # I2C 2 device pci 1c.7 on From 2fc0cf66a4bd5a3baf46620eacba35bcd8e155a1 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 2 May 2020 16:51:39 +0200 Subject: [PATCH 039/405] mb/google/volteer: Enable keyboard backlight feature This enables the keyboard backlight feature in ACPI for volteer. BUG=b:156326050 TEST=Verified 'KBLT' shows up in the DSDT ACPI table. Change-Id: Id1b1bb059368b0cc36cb06e6cdb8b989060a1dde Signed-off-by: Caveh Jalali Reviewed-on: https://review.coreboot.org/c/coreboot/+/41281 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- .../google/volteer/variants/baseboard/include/baseboard/ec.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h index 981bfae07b..2d04380e6f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h @@ -73,4 +73,7 @@ /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + #endif /* __MAINBOARD_EC_H__ */ From 4bb9c5955843bba0491a18becc2a5a394264eaf9 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Thu, 7 May 2020 14:25:09 -0600 Subject: [PATCH 040/405] soc/amd/common/block/psp: Remove unused northbridge header BUG=b:147042464 TEST=Build trembyle Signed-off-by: Raul E Rangel Change-Id: I5df618f69a7dcca47b9733efb3699b37fd171e90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41261 Reviewed-by: Furquan Shaikh Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/psp/psp.c | 1 - src/soc/amd/common/block/psp/psp_gen2.c | 1 - src/soc/amd/common/block/psp/psp_smm.c | 1 - 3 files changed, 3 deletions(-) diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index 5cc35c0792..b1b8b0d1c8 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -7,7 +7,6 @@ #include #include #include -#include #include "psp_def.h" static const char *psp_status_nobase = "error: PSP BAR3 not assigned"; diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c index d9865786b6..cf9b532f88 100644 --- a/src/soc/amd/common/block/psp/psp_gen2.c +++ b/src/soc/amd/common/block/psp/psp_gen2.c @@ -5,7 +5,6 @@ #include #include #include -#include #include "psp_def.h" static u16 rd_mbox_sts(struct pspv2_mbox *mbox) diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c index aad8ac6850..4fd80fc052 100644 --- a/src/soc/amd/common/block/psp/psp_smm.c +++ b/src/soc/amd/common/block/psp/psp_smm.c @@ -11,7 +11,6 @@ #include #include #include -#include #include "psp_def.h" #define C2P_BUFFER_MAXSIZE 0xc00 /* Core-to-PSP buffer */ From 94acba86fa05a5994d8d81da89dee063ab6d34d8 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Thu, 7 May 2020 15:12:20 -0600 Subject: [PATCH 041/405] soc/amd/picasso: Move acpi_fill_mcfg Move this with the other acpi functions. BUG=b:147042464 TEST=build trembyle Signed-off-by: Raul E Rangel Change-Id: I24bd5c7d7c90968759ac745012e7bbc47f0ef6a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41262 Reviewed-by: Furquan Shaikh Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/acpi.c | 13 ++++++++++++- src/soc/amd/picasso/northbridge.c | 12 ------------ 2 files changed, 12 insertions(+), 13 deletions(-) diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index a02d8f37cb..ac23d0f1e9 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -20,11 +20,22 @@ #include #include #include -#include #include #include #include +unsigned long acpi_fill_mcfg(unsigned long current) +{ + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + CONFIG_MMCONF_BASE_ADDRESS, + 0, + 0, + CONFIG_MMCONF_BUS_NUMBER); + + return current; +} + unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index dbd6a73566..70ad8d102a 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -146,18 +146,6 @@ static void set_resources(struct device *dev) assign_resources(bus); } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, - 0, - 0, - CONFIG_MMCONF_BUS_NUMBER); - - return current; -} - static void northbridge_fill_ssdt_generator(const struct device *device) { msr_t msr; From 4c7e0d734f198d05f668d3a28fd8362f7382b02c Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Thu, 7 May 2020 15:14:09 -0600 Subject: [PATCH 042/405] soc/amd/picasso: Move ACP register to acp.h This is a device specific register, not a northbridge register. BUG=b:147042464 Signed-off-by: Raul E Rangel Change-Id: I97b63571e336f541dcb274e4c8c608f6fc59ff42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41263 Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/acp.c | 2 +- src/soc/amd/picasso/include/soc/acp.h | 10 ++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) create mode 100644 src/soc/amd/picasso/include/soc/acp.h diff --git a/src/soc/amd/picasso/acp.c b/src/soc/amd/picasso/acp.c index c2c1022f76..e0b369d65e 100644 --- a/src/soc/amd/picasso/acp.c +++ b/src/soc/amd/picasso/acp.c @@ -6,9 +6,9 @@ #include #include #include "chip.h" +#include #include #include -#include #include #include #include diff --git a/src/soc/amd/picasso/include/soc/acp.h b/src/soc/amd/picasso/include/soc/acp.h new file mode 100644 index 0000000000..e7ec17ca38 --- /dev/null +++ b/src/soc/amd/picasso/include/soc/acp.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __PI_PICASSO_ACP_H__ +#define __PI_PICASSO_ACP_H__ + +/* Bus A D0F5 - Audio Processor */ +#define ACP_I2S_PIN_CONFIG 0x1400 /* HDA, Soundwire, I2S */ + +#endif /* __PI_PICASSO_ACP_H__ */ From cd39a41278cbe895a1c34a264f5da20226537893 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Thu, 7 May 2020 15:16:15 -0600 Subject: [PATCH 043/405] soc/amd/picasso: Extract reset flags from northbridge.h These are not northbridge functions. BUG=b:147042464 Signed-off-by: Raul E Rangel Change-Id: Ia9e7d4c7554788a9fdbfdb90e6ead60060cc4c30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41264 Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/cpu.c | 2 +- src/soc/amd/picasso/include/soc/reset.h | 10 ++++++++++ src/soc/amd/picasso/mca.c | 2 +- src/soc/amd/picasso/reset.c | 2 +- 4 files changed, 13 insertions(+), 3 deletions(-) create mode 100644 src/soc/amd/picasso/include/soc/reset.h diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index f3332ac01c..88626971c5 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/amd/picasso/include/soc/reset.h b/src/soc/amd/picasso/include/soc/reset.h new file mode 100644 index 0000000000..5fc549f203 --- /dev/null +++ b/src/soc/amd/picasso/include/soc/reset.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __PI_PICASSO_RESET_H__ +#define __PI_PICASSO_RESET_H__ + +void set_warm_reset_flag(void); +int is_warm_reset(void); + +#endif /* __PI_PICASSO_RESET_H__ */ diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 35a953c492..cea1c51301 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -3,7 +3,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c index bf9345ed4c..b6aeb1fb54 100644 --- a/src/soc/amd/picasso/reset.c +++ b/src/soc/amd/picasso/reset.c @@ -2,8 +2,8 @@ #include #include -#include #include +#include #include #include #include From b1ffca30576770999199fc8b691cfdd1185a30d5 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Tue, 16 Jul 2019 15:46:35 -0600 Subject: [PATCH 044/405] soc/amd/picasso: Delete northbridge Family 17h devices are designed with a new internal architecture, frequently referred to as the data fabric. Although designed to behave somewhat like the older integrated northbridge designs, the D18Fx definitions are completely new. The previous northbridge.c was copied from stoneyridge which is completely different. Change-Id: Id70cbda99657249179fb8cf5e461dd6a37ec9153 Signed-off-by: Raul E Rangel Reviewed-on: https://review.coreboot.org/c/coreboot/+/41265 Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Makefile.inc | 1 - src/soc/amd/picasso/chip.c | 1 - src/soc/amd/picasso/include/soc/northbridge.h | 73 ----- src/soc/amd/picasso/include/soc/pci_devs.h | 42 --- src/soc/amd/picasso/northbridge.c | 284 ------------------ 5 files changed, 401 deletions(-) delete mode 100644 src/soc/amd/picasso/include/soc/northbridge.h delete mode 100644 src/soc/amd/picasso/northbridge.c diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 43bb32e7f0..0e5cdf54ce 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -48,7 +48,6 @@ ramstage-y += mca.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += gpio.c ramstage-y += southbridge.c -ramstage-y += northbridge.c ramstage-y += pmutil.c ramstage-y += acp.c ramstage-y += sata.c diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 05106f569b..afe4c396fe 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include "chip.h" diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h deleted file mode 100644 index da33b7e043..0000000000 --- a/src/soc/amd/picasso/include/soc/northbridge.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __PI_PICASSO_NORTHBRIDGE_H__ -#define __PI_PICASSO_NORTHBRIDGE_H__ - -#include -#include - -/* D1F1 - HDA Configuration Registers */ -#define HDA_DEV_CTRL_STATUS 0x60 -#define HDA_NO_SNOOP_EN BIT(11) - -/* D18F0 - HT Configuration Registers */ -#define D18F0_NODE_ID 0x60 -#define D18F0_CPU_CNT 0x62 /* BKDG defines as a field in DWORD 0x60 */ -# define CPU_CNT_MASK 0x1f /* CpuCnt + 1 = no. CPUs */ -#define HT_INIT_CONTROL 0x6c -# define HTIC_BIOSR_DETECT ((1 << 5) | (1 << 9) | (1 << 10)) -# define HTIC_COLD_RST_DET BIT(4) - -/* D18F1 - Address Map Registers */ - -/* MMIO base and limit */ -#define D18F1_MMIO_BASE0_LO 0x80 -# define MMIO_WE (1 << 1) -# define MMIO_RE (1 << 0) -#define D18F1_MMIO_LIMIT0_LO 0x84 -# define MMIO_NP (1 << 7) -#define D18F1_IO_BASE0_LO 0xc0 -#define D18F1_IO_BASE1_LO 0xc8 -#define D18F1_IO_BASE2_LO 0xd0 -#define D18F1_IO_BASE3_LO 0xd8 -#define D18F1_MMIO_BASE7_LO 0xb8 -#define D18F1_MMIO_BASELIM0_HI 0x180 -#define D18F1_MMIO_BASE8_LO 0x1a0 -#define D18F1_MMIO_LIMIT8_LO 0x1a4 -#define D18F1_MMIO_BASE11_LO 0x1b8 -#define D18F1_MMIO_BASELIM8_HI 0x1c0 -#define NB_MMIO_BASE_LO(reg) ((reg) * 2 * sizeof(uint32_t) + (((reg) < 8) \ - ? D18F1_MMIO_BASE0_LO \ - : D18F1_MMIO_BASE8_LO \ - - 8 * sizeof(uint64_t))) -#define NB_MMIO_LIMIT_LO(reg) (NB_MMIO_BASE_LO(reg) + sizeof(uint32_t)) -#define NB_MMIO_BASELIM_HI(reg) ((reg) * sizeof(uint32_t) + (((reg) < 8) \ - ? D18F1_MMIO_BASELIM0_HI \ - : D18F1_MMIO_BASELIM8_HI \ - - 8 * sizeof(uint32_t))) -/* I/O base and limit */ -#define D18F1_IO_BASE0 0xc0 -# define IO_WE (1 << 1) -# define IO_RE (1 << 0) -#define D18F1_IO_LIMIT0 0xc4 -#define NB_IO_BASE(reg) ((reg) * 2 * sizeof(uint32_t) + D18F1_IO_BASE0) -#define NB_IO_LIMIT(reg) (NB_IO_BASE(reg) + sizeof(uint32_t)) - -#define D18F1_DRAM_HOLE 0xf0 -# define DRAM_HOIST_VALID (1 << 1) -# define DRAM_HOLE_VALID (1 << 0) -#define D18F1_VGAEN 0xf4 -# define VGA_ADDR_ENABLE (1 << 0) - -/* Bus A D0F5 - Audio Processor */ -#define ACP_I2S_PIN_CONFIG 0x1400 /* HDA, Soundwire, I2S */ - -void amd_initcpuio(void); - -void domain_enable_resources(struct device *dev); -void domain_set_resources(struct device *dev); -void fam15_finalize(void *chip_info); -void set_warm_reset_flag(void); -int is_warm_reset(void); - -#endif /* __PI_PICASSO_NORTHBRIDGE_H__ */ diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index cfcc5503a2..a97391e86a 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -89,48 +89,6 @@ #define HDA1_DEVFN PCI_DEVFN(HDA1_DEV, HDA1_FUNC) #define SOC_HDA1_DEV _SOC_DEV(HDA1_DEV, HDA1_FUNC) -/* HT Configuration */ -#define HT_DEV 0x18 -#define HT_FUNC 0 -#define HT_DEVID 0x15b0 -#define HT_DEVFN PCI_DEVFN(HT_DEV, HT_FUNC) -#define SOC_HT_DEV _SOC_DEV(HT_DEV, HT_FUNC) - -/* Address Maps */ -#define ADDR_DEV 0x18 -#define ADDR_FUNC 1 -#define ADDR_DEVID 0x15b1 -#define ADDR_DEVFN PCI_DEVFN(ADDR_DEV, ADDR_FUNC) -#define SOC_ADDR_DEV _SOC_DEV(ADDR_DEV, ADDR_FUNC) - -/* DRAM Configuration */ -#define DCT_DEV 0x18 -#define DCT_FUNC 2 -#define DCT_DEVID 0x15b2 -#define DCT_DEVFN PCI_DEVFN(DCT_DEV, DCT_FUNC) -#define SOC_DCT_DEV _SOC_DEV(DCT_DEV, DCT_FUNC) - -/* Misc. Configuration */ -#define MISC_DEV 0x18 -#define MISC_FUNC 3 -#define MISC_DEVID 0x15b3 -#define MISC_DEVFN PCI_DEVFN(MISC_DEV, MISC_FUNC) -#define SOC_MISC_DEV _SOC_DEV(MISC_DEV, MISC_FUNC) - -/* PM Configuration */ -#define PM_DEV 0x18 -#define PM_FUNC 4 -#define PM_DEVID 0x15b4 -#define PM_DEVFN PCI_DEVFN(PM_DEV, PM_FUNC) -#define SOC_PM_DEV _SOC_DEV(PM_DEV, PM_FUNC) - -/* Northbridge Configuration */ -#define NB_DEV 0x18 -#define NB_FUNC 5 -#define NB_DEVID 0x15b5 -#define NB_DEVFN PCI_DEVFN(NB_DEV, NB_FUNC) -#define SOC_NB_DEV _SOC_DEV(NB_DEV, NB_FUNC) - /* USB 3.1 */ #define XHCI0_DEV 0x0 #define XHCI0_FUNC 3 diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c deleted file mode 100644 index 70ad8d102a..0000000000 --- a/src/soc/amd/picasso/northbridge.c +++ /dev/null @@ -1,284 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "chip.h" - -static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, - u32 io_min, u32 io_max) -{ - u32 tempreg; - - /* io range allocation. Limit */ - tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) - | ((io_max & 0xf0) << (12 - 4)); - pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg); - tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); /* base: ISA and VGA ? */ - pci_write_config32(SOC_ADDR_DEV, reg, tempreg); -} - -static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, - u32 mmio_min, u32 mmio_max) -{ - u32 tempreg; - - /* io range allocation. Limit */ - tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00); - pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg); - tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00); - pci_write_config32(SOC_ADDR_DEV, reg, tempreg); -} - -static void read_resources(struct device *dev) -{ - /* - * This MMCONF resource must be reserved in the PCI domain. - * It is not honored by the coreboot resource allocator if it is in - * the CPU_CLUSTER. - */ - mmconf_resource(dev, MMIO_CONF_BASE); -} - -static void set_resource(struct device *dev, struct resource *res, u32 nodeid) -{ - resource_t rbase, rend; - unsigned int reg, link_num; - char buf[50]; - - /* Make certain the resource has actually been set */ - if (!(res->flags & IORESOURCE_ASSIGNED)) - return; - - /* If I have already stored this resource don't worry about it */ - if (res->flags & IORESOURCE_STORED) - return; - - /* Only handle PCI memory and IO resources */ - if (!(res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) - return; - - /* Ensure I am actually looking at a resource of function 1 */ - if ((res->index & 0xffff) < 0x1000) - return; - - /* Get the base address */ - rbase = res->base; - - /* Get the limit (rounded up) */ - rend = resource_end(res); - - /* Get the register and link */ - reg = res->index & 0xfff; /* 4k */ - link_num = IOINDEX_LINK(res->index); - - if (res->flags & IORESOURCE_IO) - set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); - else if (res->flags & IORESOURCE_MEM) - set_mmio_addr_reg(nodeid, link_num, reg, - (res->index >> 24), rbase >> 8, rend >> 8); - - res->flags |= IORESOURCE_STORED; - snprintf(buf, sizeof(buf), " ", - nodeid, link_num); - report_resource_stored(dev, res, buf); -} - -/** - * I tried to reuse the resource allocation code in set_resource() - * but it is too difficult to deal with the resource allocation magic. - */ - -static void create_vga_resource(struct device *dev) -{ - struct bus *link; - - /* find out which link the VGA card is connected, - * we only deal with the 'first' vga card */ - for (link = dev->link_list ; link ; link = link->next) - if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) - break; - - /* no VGA card installed */ - if (link == NULL) - return; - - printk(BIOS_DEBUG, "VGA: %s has VGA device\n", dev_path(dev)); - /* Route A0000-BFFFF, IO 3B0-3BB 3C0-3DF */ - pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE); -} - -static void set_resources(struct device *dev) -{ - struct bus *bus; - struct resource *res; - - - /* do we need this? */ - create_vga_resource(dev); - - /* Set each resource we have found */ - for (res = dev->resource_list ; res ; res = res->next) - set_resource(dev, res, 0); - - for (bus = dev->link_list ; bus ; bus = bus->next) - if (bus->children) - assign_resources(bus); -} - -static void northbridge_fill_ssdt_generator(const struct device *device) -{ - msr_t msr; - char pscope[] = "\\_SB.PCI0"; - - acpigen_write_scope(pscope); - msr = rdmsr(TOP_MEM); - acpigen_write_name_dword("TOM1", msr.lo); - msr = rdmsr(TOP_MEM2); - /* - * Since XP only implements parts of ACPI 2.0, we can't use a qword - * here. - * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt - * slide 22ff. - * Shift value right by 20 bit to make it fit into 32bit, - * giving us 1MB granularity and a limit of almost 4Exabyte of memory. - */ - acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); - acpigen_pop_len(); -} - -static unsigned long agesa_write_acpi_tables(const struct device *device, - unsigned long current, - acpi_rsdp_t *rsdp) -{ - /* TODO - different mechanism to collect this info for Family 17h */ - return current; -} - -static struct device_operations northbridge_operations = { - .read_resources = read_resources, - .set_resources = set_resources, - .enable_resources = pci_dev_enable_resources, - .acpi_fill_ssdt = northbridge_fill_ssdt_generator, - .write_acpi_tables = agesa_write_acpi_tables, -}; - -static const struct pci_driver family15_northbridge __pci_driver = { - .ops = &northbridge_operations, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT, -}; - -/* - * Enable VGA cycles. Set memory ranges of the FCH legacy devices (TPM, HPET, - * BIOS RAM, Watchdog Timer, IOAPIC and ACPI) as non-posted. Set remaining - * MMIO to posted. Route all I/O to the southbridge. - */ -void amd_initcpuio(void) -{ - uintptr_t topmem = bsp_topmem(); - uintptr_t base, limit; - - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE); - - /* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */ - base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE; - limit = (ALIGN_DOWN(LOCAL_APIC_ADDR - 1, 64 * KiB) >> 8) | MMIO_NP; - pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(0), limit); - pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(0), base); - - /* Remaining PCI hole posted MMIO: TOM-HPET (TOM through 0xfed00000-1 */ - base = (topmem >> 8) | MMIO_WE | MMIO_RE; - limit = ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8; - pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(1), limit); - pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(1), base); - - /* Route all I/O downstream */ - base = 0 | IO_WE | IO_RE; - limit = ALIGN_DOWN(0xffff, 4 * KiB); - pci_write_config32(SOC_ADDR_DEV, NB_IO_LIMIT(0), limit); - pci_write_config32(SOC_ADDR_DEV, NB_IO_BASE(0), base); -} - -void fam15_finalize(void *chip_info) -{ - u32 value; - - /* disable No Snoop */ - value = pci_read_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS); - value &= ~HDA_NO_SNOOP_EN; - pci_write_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS, value); -} - -void domain_set_resources(struct device *dev) -{ - uint64_t uma_base = get_uma_base(); - uint32_t uma_size = get_uma_size(); - uint32_t mem_useable = (uintptr_t)cbmem_top(); - msr_t tom = rdmsr(TOP_MEM); - msr_t high_tom = rdmsr(TOP_MEM2); - uint64_t high_mem_useable; - int idx = 0x10; - - /* 0x0 -> 0x9ffff */ - ram_resource(dev, idx++, 0, 0xa0000 / KiB); - - /* 0xa0000 -> 0xbffff: legacy VGA */ - mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB); - - /* 0xc0000 -> 0xfffff: Option ROM */ - reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); - - /* - * 0x100000 (1MiB) -> low top useable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. - */ - ram_resource(dev, idx++, (1 * MiB) / KiB, - (mem_useable - (1 * MiB)) / KiB); - - /* Low top useable RAM -> Low top RAM (bottom pci mmio hole) */ - reserved_ram_resource(dev, idx++, mem_useable / KiB, - (tom.lo - mem_useable) / KiB); - - /* If there is memory above 4GiB */ - if (high_tom.hi) { - /* 4GiB -> high top useable */ - if (uma_base >= (4ull * GiB)) - high_mem_useable = uma_base; - else - high_mem_useable = ((uint64_t)high_tom.lo | - ((uint64_t)high_tom.hi << 32)); - - ram_resource(dev, idx++, (4ull * GiB) / KiB, - ((high_mem_useable - (4ull * GiB)) / KiB)); - - /* High top useable RAM -> high top RAM */ - if (uma_base >= (4ull * GiB)) { - reserved_ram_resource(dev, idx++, uma_base / KiB, - uma_size / KiB); - } - } - - assign_resources(dev->link_list); -} From e44651b496a2f88fd1212ab4228323a5eee1b80c Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Thu, 7 May 2020 15:19:53 -0600 Subject: [PATCH 045/405] soc/amd/picasso: Add data fabric register definitions These are used to setup the data fabric. Definitions came from 55570-B1 Rev 3.14 - PPR for AMD Family 17h Model 18h BUG=b:147042464 Signed-off-by: Raul E Rangel Change-Id: Ib51f6e2fd304da9948d6625608af71f25b974854 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41266 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/include/soc/data_fabric.h | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 src/soc/amd/picasso/include/soc/data_fabric.h diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h new file mode 100644 index 0000000000..af9c200ce2 --- /dev/null +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_PICASSO_DATAFABRIC_H__ +#define __SOC_PICASSO_DATAFABRIC_H__ + +#include + +/* D18F0 - Fabric Configuration registers */ +#define IOMS0_FABRIC_ID 9 + +#define D18F0_VGAEN 0x80 +#define VGA_ADDR_ENABLE BIT(0) + +#define D18F0_MMIO_BASE0 0x200 +#define D18F0_MMIO_LIMIT0 0x204 +#define D18F0_MMIO_SHIFT 16 +#define D18F0_MMIO_CTRL0 0x208 +#define MMIO_NP BIT(12) +#define MMIO_DST_FABRIC_ID_SHIFT 4 +#define MMIO_WE BIT(1) +#define MMIO_RE BIT(0) +#define NUM_NB_MMIO_REGS 8 +#define NB_MMIO_BASE(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_BASE0) +#define NB_MMIO_LIMIT(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_LIMIT0) +#define NB_MMIO_CONTROL(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_CTRL0) + +#endif /* __SOC_PICASSO_DATAFABRIC_H__ */ From 658a2913a5bbe9c638c0d069ea663ecb77b490b0 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Mon, 11 May 2020 15:47:39 -0600 Subject: [PATCH 046/405] soc/amd/picasso: Add data fabric pci_devs The device ids are already defined in include/device/pci_ids.h as PCI_DEVICE_ID_AMD_FAM17H_DF*. BUG=b:147042464 TEST=Build trembyle Signed-off-by: Raul E Rangel Change-Id: Ic68a1067e5976af972592d7352c40a5c66dbeb8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41267 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin --- src/soc/amd/picasso/include/soc/pci_devs.h | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index a97391e86a..282d86ce09 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -89,6 +89,30 @@ #define HDA1_DEVFN PCI_DEVFN(HDA1_DEV, HDA1_FUNC) #define SOC_HDA1_DEV _SOC_DEV(HDA1_DEV, HDA1_FUNC) +/* Data Fabric functions */ +#define DF_DEV 0x18 + +#define DF_F0_DEVFN PCI_DEVFN(DF_DEV, 0) +#define SOC_DF_F0_DEV _SOC_DEV(DF_DEV, 0) + +#define DF_F1_DEVFN PCI_DEVFN(DF_DEV, 1) +#define SOC_DF_F1_DEV _SOC_DEV(DF_DEV, 1) + +#define DF_F2_DEVFN PCI_DEVFN(DF_DEV, 2) +#define SOC_DF_F2_DEV _SOC_DEV(DF_DEV, 2) + +#define DF_F3_DEVFN PCI_DEVFN(DF_DEV, 3) +#define SOC_DF_F3_DEV _SOC_DEV(DF_DEV, 3) + +#define DF_F4_DEVFN PCI_DEVFN(DF_DEV, 4) +#define SOC_DF_F4_DEV _SOC_DEV(DF_DEV, 4) + +#define DF_F5_DEVFN PCI_DEVFN(DF_DEV, 5) +#define SOC_DF_F5_DEV _SOC_DEV(DF_DEV, 5) + +#define DF_F6_DEVFN PCI_DEVFN(DF_DEV, 6) +#define SOC_DF_F6_DEV _SOC_DEV(DF_DEV, 6) + /* USB 3.1 */ #define XHCI0_DEV 0x0 #define XHCI0_FUNC 3 From 789aefc2272c2ffb3ca2c9380ccdc1a2288f2534 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Mon, 11 May 2020 16:26:35 -0600 Subject: [PATCH 047/405] soc/amd/picasso: Mark FCH MMIO addresses as non-posted Immediately following FSP-S, update the data fabric routing registers to make the region between HPET and LAPIC as non-posted. If AGESA is modified to do this, we can delete data_fabric_util.c. If AGESA is modified to not program the registers, then we can simplify data_fabric_set_mmio_np(). BUG=b:147042464, b:156296146 TEST=boot trembyle Change-Id: Idbafaac158f5a4c533d2d88db79bb4d6244e5355 Signed-off-by: Marshall Dawson Signed-off-by: Raul E Rangel Reviewed-on: https://review.coreboot.org/c/coreboot/+/41268 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Makefile.inc | 1 + src/soc/amd/picasso/chip.c | 2 + src/soc/amd/picasso/data_fabric_util.c | 117 ++++++++++++++++++ src/soc/amd/picasso/include/soc/data_fabric.h | 2 + 4 files changed, 122 insertions(+) create mode 100644 src/soc/amd/picasso/data_fabric_util.c diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 0e5cdf54ce..e015fbe057 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -44,6 +44,7 @@ verstage-y += tsc_freq.c ramstage-y += i2c.c ramstage-y += chip.c ramstage-y += cpu.c +ramstage-y += data_fabric_util.c ramstage-y += mca.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += gpio.c diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index afe4c396fe..5c5b79d136 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include "chip.h" @@ -100,6 +101,7 @@ static void soc_init(void *chip_info) { fsp_silicon_init(acpi_is_wakeup_s3()); + data_fabric_set_mmio_np(); southbridge_init(chip_info); setup_bsp_ramtop(); } diff --git a/src/soc/amd/picasso/data_fabric_util.c b/src/soc/amd/picasso/data_fabric_util.c new file mode 100644 index 0000000000..a375b84477 --- /dev/null +++ b/src/soc/amd/picasso/data_fabric_util.c @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +static void disable_mmio_reg(int reg) +{ + pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_CONTROL(reg), + IOMS0_FABRIC_ID << MMIO_DST_FABRIC_ID_SHIFT); + pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_BASE(reg), 0); + pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(reg), 0); +} + +static bool is_mmio_reg_disabled(int reg) +{ + uint32_t val = pci_read_config32(SOC_DF_F0_DEV, NB_MMIO_CONTROL(reg)); + return !(val & ((MMIO_WE | MMIO_RE))); +} + +static int find_unused_mmio_reg(void) +{ + unsigned int i; + + for (i = 0; i < NUM_NB_MMIO_REGS; i++) { + if (is_mmio_reg_disabled(i)) + return i; + } + return -1; +} + +void data_fabric_set_mmio_np(void) +{ + /* + * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP. + * + * AGESA has already programmed the NB MMIO routing, however nothing + * is yet marked as non-posted. + * + * If there exists an overlapping routing base/limit pair, trim its + * base or limit to avoid the new NP region. If any pair exists + * completely within HPET-LAPIC range, remove it. If any pair surrounds + * HPET-LAPIC, it must be split into two regions. + * + * TODO(b/156296146): Remove the settings from AGESA and allow coreboot + * to own everything. If not practical, consider erasing all settings + * and have coreboot reprogram them. At that time, make the source + * below more flexible. + * * Note that the code relies on the granularity of the HPET and + * LAPIC addresses being sufficiently large that the shifted limits + * +/-1 are always equivalent to the non-shifted values +/-1. + */ + + unsigned int i; + int reg; + uint32_t base, limit, ctrl; + const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; + const uint32_t np_top = (LOCAL_APIC_ADDR - 1) >> D18F0_MMIO_SHIFT; + + for (i = 0; i < NUM_NB_MMIO_REGS; i++) { + /* Adjust all registers that overlap */ + ctrl = pci_read_config32(SOC_DF_F0_DEV, NB_MMIO_CONTROL(i)); + if (!(ctrl & (MMIO_WE | MMIO_RE))) + continue; /* not enabled */ + + base = pci_read_config32(SOC_DF_F0_DEV, NB_MMIO_BASE(i)); + limit = pci_read_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(i)); + + if (base > np_top || limit < np_bot) + continue; /* no overlap at all */ + + if (base >= np_bot && limit <= np_top) { + disable_mmio_reg(i); /* 100% within, so remove */ + continue; + } + + if (base < np_bot && limit > np_top) { + /* Split the configured region */ + pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(i), np_bot - 1); + reg = find_unused_mmio_reg(); + if (reg < 0) { + /* Although a pair could be freed later, this condition is + * very unusual and deserves analysis. Flag an error and + * leave the topmost part unconfigured. */ + printk(BIOS_ERR, + "Error: Not enough NB MMIO routing registers\n"); + continue; + } + pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_BASE(reg), np_top + 1); + pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(reg), limit); + pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_CONTROL(reg), ctrl); + continue; + } + + /* If still here, adjust only the base or limit */ + if (base <= np_bot) + pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(i), np_bot - 1); + else + pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_BASE(i), np_top + 1); + } + + reg = find_unused_mmio_reg(); + if (reg < 0) { + printk(BIOS_ERR, "Error: cannot configure region as NP\n"); + return; + } + + pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_BASE(reg), np_bot); + pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(reg), np_top); + pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_CONTROL(reg), + (IOMS0_FABRIC_ID << MMIO_DST_FABRIC_ID_SHIFT) | MMIO_NP | MMIO_WE + | MMIO_RE); +} diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index af9c200ce2..39906e8f95 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -24,4 +24,6 @@ #define NB_MMIO_LIMIT(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_LIMIT0) #define NB_MMIO_CONTROL(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_CTRL0) +void data_fabric_set_mmio_np(void); + #endif /* __SOC_PICASSO_DATAFABRIC_H__ */ From 5181ac15c849268ab0999e515abeb2d678c97d7b Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 12 May 2020 14:23:46 -0700 Subject: [PATCH 048/405] Remove new additions of "this file is part of" lines CB:41194 got rid of "this file is part of" lines. However, there are some changes that landed right around the same time including those lines. This change uses the following command to drop the lines from new files: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) Signed-off-by: Furquan Shaikh Change-Id: Ic3c1d717416f6b7e946f84748e2b260552c06a1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/41342 Reviewed-by: Patrick Georgi Reviewed-by: Raul Rangel Reviewed-by: Felix Held Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/drivers/i2c/max98390/chip.h | 1 - src/drivers/i2c/max98390/max98390.c | 1 - src/include/espi.h | 1 - src/lib/espi_debug.c | 1 - src/soc/amd/common/block/include/amdblocks/chip.h | 1 - src/soc/amd/common/block/include/amdblocks/espi.h | 1 - src/soc/amd/common/block/include/amdblocks/spi.h | 1 - src/soc/amd/common/block/lpc/espi_util.c | 1 - src/soc/amd/common/block/spi/fch_spi.c | 1 - src/soc/amd/picasso/config.c | 1 - 10 files changed, 10 deletions(-) diff --git a/src/drivers/i2c/max98390/chip.h b/src/drivers/i2c/max98390/chip.h index 26cad4c728..193a17412c 100644 --- a/src/drivers/i2c/max98390/chip.h +++ b/src/drivers/i2c/max98390/chip.h @@ -1,4 +1,3 @@ -/* This file is part of the coreboot project. */ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* diff --git a/src/drivers/i2c/max98390/max98390.c b/src/drivers/i2c/max98390/max98390.c index d2bb14fc8b..64c2e3ff2d 100644 --- a/src/drivers/i2c/max98390/max98390.c +++ b/src/drivers/i2c/max98390/max98390.c @@ -1,4 +1,3 @@ -/* This file is part of the coreboot project. */ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/include/espi.h b/src/include/espi.h index 7503af79ec..4be8543173 100644 --- a/src/include/espi.h +++ b/src/include/espi.h @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ #ifndef __ESPI_H__ #define __ESPI_H__ diff --git a/src/lib/espi_debug.c b/src/lib/espi_debug.c index 63e16f444b..5adb618182 100644 --- a/src/lib/espi_debug.c +++ b/src/lib/espi_debug.c @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/include/amdblocks/chip.h b/src/soc/amd/common/block/include/amdblocks/chip.h index b0348115e9..d15046463b 100644 --- a/src/soc/amd/common/block/include/amdblocks/chip.h +++ b/src/soc/amd/common/block/include/amdblocks/chip.h @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ #ifndef __AMDBLOCKS_CHIP_H__ #define __AMDBLOCKS_CHIP_H__ diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index 69267f8cc3..f47386bc5d 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ #ifndef __AMDBLOCKS_ESPI_H__ #define __AMDBLOCKS_ESPI_H__ diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index d901f7e020..fec099dc6a 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ #ifndef __AMDBLOCKS_SPI_H__ #define __AMDBLOCKS_SPI_H__ diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 54a017ea0c..83f36957bd 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c index 950eee2947..bf64c3f260 100644 --- a/src/soc/amd/common/block/spi/fch_spi.c +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/picasso/config.c b/src/soc/amd/picasso/config.c index 5d52e7affa..3d4bc7b1ed 100644 --- a/src/soc/amd/picasso/config.c +++ b/src/soc/amd/picasso/config.c @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ #include #include From 69d5bbf073ee45f18492a6204dc25c934c6d3c05 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 12 May 2020 15:46:16 -0700 Subject: [PATCH 049/405] espi_debug: Use switch case instead of if-else This change updates espi_debug.c to use switch case instead of if-else for operating frequency and i/o mode prints. This is done to address the review comments received on CB:41254. Signed-off-by: Furquan Shaikh Change-Id: I4f323b79f030818e2daa983d4f17ddf7a3192171 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41346 Reviewed-by: Felix Held Reviewed-by: Angel Pons Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/lib/espi_debug.c | 78 +++++++++++++++++++++++++++++--------------- 1 file changed, 51 insertions(+), 27 deletions(-) diff --git a/src/lib/espi_debug.c b/src/lib/espi_debug.c index 5adb618182..1ddcb40baa 100644 --- a/src/lib/espi_debug.c +++ b/src/lib/espi_debug.c @@ -23,24 +23,34 @@ void espi_show_slave_general_configuration(uint32_t config) printk(BIOS_DEBUG, " IO bit1 pin used to signal alert event\n"); io_mode = config & ESPI_SLAVE_IO_MODE_SEL_MASK; - if (io_mode == ESPI_SLAVE_IO_MODE_SEL_SINGLE) + switch (io_mode) { + case ESPI_SLAVE_IO_MODE_SEL_SINGLE: printk(BIOS_DEBUG, " eSPI single IO mode selected\n"); - else if (io_mode == ESPI_SLAVE_IO_MODE_SEL_DUAL) + break; + case ESPI_SLAVE_IO_MODE_SEL_DUAL: printk(BIOS_DEBUG, " eSPI dual IO mode selected\n"); - else if (io_mode == ESPI_SLAVE_IO_MODE_SEL_QUAD) + break; + case ESPI_SLAVE_IO_MODE_SEL_QUAD: printk(BIOS_DEBUG, " eSPI quad IO mode selected\n"); - else + break; + default: printk(BIOS_DEBUG, " Error: Invalid eSPI IO mode selected\n"); + } io_mode = config & ESPI_SLAVE_IO_MODE_SUPP_MASK; - if (io_mode == ESPI_SLAVE_IO_MODE_SUPP_SINGLE_QUAD) + switch (io_mode) { + case ESPI_SLAVE_IO_MODE_SUPP_SINGLE_QUAD: printk(BIOS_DEBUG, " eSPI quad and single IO modes supported\n"); - else if (io_mode == ESPI_SLAVE_IO_MODE_SUPP_SINGLE_DUAL) - printk(BIOS_DEBUG, " eSPI dual and single IO mode supported\n"); - else if (io_mode == ESPI_SLAVE_IO_MODE_SUPP_SINGLE_DUAL_QUAD) - printk(BIOS_DEBUG, " eSPI quad, dual, and single IO modes supported\n"); - else + break; + case ESPI_SLAVE_IO_MODE_SUPP_SINGLE_DUAL: + printk(BIOS_DEBUG, " eSPI dual and single IO modes supported\n"); + break; + case ESPI_SLAVE_IO_MODE_SUPP_SINGLE_DUAL_QUAD: + printk(BIOS_DEBUG, " eSPI quad, dual and single IO modes supported\n"); + break; + default: printk(BIOS_DEBUG, " Only eSPI single IO mode supported\n"); + } if (config & ESPI_SLAVE_OPEN_DRAIN_ALERT_SEL) printk(BIOS_DEBUG, " Alert# pin is open-drain\n"); @@ -48,35 +58,49 @@ void espi_show_slave_general_configuration(uint32_t config) printk(BIOS_DEBUG, " Alert# pin is driven\n"); op_freq = config & ESPI_SLAVE_OP_FREQ_SEL_MASK; - if (op_freq == ESPI_SLAVE_OP_FREQ_SEL_20_MHZ) + switch (op_freq) { + case ESPI_SLAVE_OP_FREQ_SEL_20_MHZ: printk(BIOS_DEBUG, " eSPI 20MHz selected\n"); - else if (op_freq == ESPI_SLAVE_OP_FREQ_SEL_25_MHZ) + break; + case ESPI_SLAVE_OP_FREQ_SEL_25_MHZ: printk(BIOS_DEBUG, " eSPI 25MHz selected\n"); - else if (op_freq == ESPI_SLAVE_OP_FREQ_SEL_33_MHZ) + break; + case ESPI_SLAVE_OP_FREQ_SEL_33_MHZ: printk(BIOS_DEBUG, " eSPI 33MHz selected\n"); - else if (op_freq == ESPI_SLAVE_OP_FREQ_SEL_50_MHZ) + break; + case ESPI_SLAVE_OP_FREQ_SEL_50_MHZ: printk(BIOS_DEBUG, " eSPI 50MHz selected\n"); - else if (op_freq == ESPI_SLAVE_OP_FREQ_SEL_66_MHZ) + break; + case ESPI_SLAVE_OP_FREQ_SEL_66_MHZ: printk(BIOS_DEBUG, " eSPI 66MHz selected\n"); - else + break; + default: printk(BIOS_DEBUG, " Error: Invalid eSPI frequency\n"); + } if (config & ESPI_SLAVE_OPEN_DRAIN_ALERT_SUPP) printk(BIOS_DEBUG, " Open-drain Alert# pin supported\n"); op_freq = config & ESPI_SLAVE_OP_FREQ_SUPP_MASK; - if (op_freq == ESPI_SLAVE_OP_FREQ_SUPP_20_MHZ) - printk(BIOS_DEBUG, " eSPI 20MHz supported\n"); - else if (op_freq == ESPI_SLAVE_OP_FREQ_SUPP_25_MHZ) - printk(BIOS_DEBUG, " eSPI 25MHz supported\n"); - else if (op_freq == ESPI_SLAVE_OP_FREQ_SUPP_33_MHZ) - printk(BIOS_DEBUG, " eSPI 33MHz supported\n"); - else if (op_freq == ESPI_SLAVE_OP_FREQ_SUPP_50_MHZ) - printk(BIOS_DEBUG, " eSPI 50MHz supported\n"); - else if (op_freq == ESPI_SLAVE_OP_FREQ_SUPP_66_MHZ) - printk(BIOS_DEBUG, " eSPI 66MHz supported\n"); - else + switch (op_freq) { + case ESPI_SLAVE_OP_FREQ_SUPP_20_MHZ: + printk(BIOS_DEBUG, " eSPI up to 20MHz supported\n"); + break; + case ESPI_SLAVE_OP_FREQ_SUPP_25_MHZ: + printk(BIOS_DEBUG, " eSPI up to 25MHz supported\n"); + break; + case ESPI_SLAVE_OP_FREQ_SUPP_33_MHZ: + printk(BIOS_DEBUG, " eSPI up to 33MHz supported\n"); + break; + case ESPI_SLAVE_OP_FREQ_SUPP_50_MHZ: + printk(BIOS_DEBUG, " eSPI up to 50MHz supported\n"); + break; + case ESPI_SLAVE_OP_FREQ_SUPP_66_MHZ: + printk(BIOS_DEBUG, " eSPI up to 66MHz supported\n"); + break; + default: printk(BIOS_DEBUG, " Error: Invalid eSPI frequency\n"); + } printk(BIOS_DEBUG, " Maximum Wait state: %d\n", (config & ESPI_SLAVE_MAX_WAIT_MASK) >> ESPI_SLAVE_MAX_WAIT_SHIFT); From 38779e6b8304cf4078bede5512ca07f609f3ea63 Mon Sep 17 00:00:00 2001 From: Weiyi Lu Date: Wed, 6 May 2020 11:05:15 +0800 Subject: [PATCH 050/405] soc/mediatek: improve ca53 frequency change procedure To change frequency, the SOC PLL team suggests procedure below: First, we need to enable the intermediate clock and switch the ca53 clock source to the intermediate clock. Second, disable the armpll_ll clock output. Third, raise armpll_ll frequency and enable the clock output. The last, switch the ca53 clock source back to armpll_ll and disable the intermediate clock. BUG=b:154451241 BRANCH=jacuzzi TEST=Boots correctly on Jacuzzi. Signed-off-by: Weiyi Lu Change-Id: Ib9556ba340da272fb62588f45851c93373cfa919 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41077 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8183/include/soc/pll.h | 1 + src/soc/mediatek/mt8183/pll.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/src/soc/mediatek/mt8183/include/soc/pll.h b/src/soc/mediatek/mt8183/include/soc/pll.h index 3fa7366942..3aa77c9f3b 100644 --- a/src/soc/mediatek/mt8183/include/soc/pll.h +++ b/src/soc/mediatek/mt8183/include/soc/pll.h @@ -217,6 +217,7 @@ enum { MUX_MASK = 0x3 << 9, MUX_SRC_ARMPLL = 0x1 << 9, + MUX_SRC_DIV_PLL1 = 0x2 << 9, }; enum { diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index 39dfa264e3..dedd59d4f2 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -365,5 +365,27 @@ void mt_pll_init(void) void mt_pll_raise_ca53_freq(u32 freq) { + /* enable [4] intermediate clock armpll_divider_pll1_ck */ + setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); + + /* switch ca53 clock source to intermediate clock */ + clrsetbits32(&mt8183_mcucfg->mp0_pll_divider_cfg, MUX_MASK, + MUX_SRC_DIV_PLL1); + + /* disable armpll_ll frequency output */ + clrbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN); + + /* raise armpll_ll frequency */ pll_set_rate(&plls[APMIXED_ARMPLL_LL], freq); + + /* enable armpll_ll frequency output */ + setbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN); + udelay(PLL_EN_DELAY); + + /* switch ca53 clock source back to armpll_ll */ + clrsetbits32(&mt8183_mcucfg->mp0_pll_divider_cfg, MUX_MASK, + MUX_SRC_ARMPLL); + + /* disable [4] intermediate clock armpll_divider_pll1_ck */ + clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); } From 785a3b4a6fa7c0d2597d3322e8c0394d51c9c41a Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Fri, 8 May 2020 16:16:36 -0700 Subject: [PATCH 051/405] mb/google/volteer: move SPD files to variant directories Memory SPD files for each variant are now stored in the variant's mb/google/volteer/variants//spd directory instead of storing them in mb/google/volteer/spd. This change moves SPDs to where they are needed and changes the makefile to look for them in their new locations. BUG=b:156126658 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot a proto2 SKU4 to the kernel. Change-Id: I759c979027477a2a4c5489a6b12278799488d6e7 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/41184 Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/Makefile.inc | 1 + src/mainboard/google/volteer/spd/Makefile.inc | 2 +- ...R4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex | 0 ...R4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex | 32 +++++++++++++++++++ ...R4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex | 32 +++++++++++++++++++ ...R4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex | 0 6 files changed, 66 insertions(+), 1 deletion(-) rename src/mainboard/google/volteer/{ => variants/malefor}/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex (100%) create mode 100644 src/mainboard/google/volteer/variants/ripto/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex create mode 100644 src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex rename src/mainboard/google/volteer/{ => variants/volteer}/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex (100%) diff --git a/src/mainboard/google/volteer/Makefile.inc b/src/mainboard/google/volteer/Makefile.inc index 4ef81c4912..75f8a58245 100644 --- a/src/mainboard/google/volteer/Makefile.inc +++ b/src/mainboard/google/volteer/Makefile.inc @@ -22,6 +22,7 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) subdirs-y += variants/$(VARIANT_DIR) +subdirs-y += variants/$(VARIANT_DIR)/spd CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include subdirs-y += spd diff --git a/src/mainboard/google/volteer/spd/Makefile.inc b/src/mainboard/google/volteer/spd/Makefile.inc index 00b7f939ca..eb53fc00a3 100644 --- a/src/mainboard/google/volteer/spd/Makefile.inc +++ b/src/mainboard/google/volteer/spd/Makefile.inc @@ -7,7 +7,7 @@ ifneq ($(SPD_SOURCES),) SPD_BIN = $(obj)/spd.bin -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) # Include spd ROM data $(SPD_BIN): $(SPD_DEPS) diff --git a/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex b/src/mainboard/google/volteer/variants/malefor/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex similarity index 100% rename from src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex rename to src/mainboard/google/volteer/variants/malefor/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex diff --git a/src/mainboard/google/volteer/variants/ripto/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex b/src/mainboard/google/volteer/variants/ripto/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex new file mode 100644 index 0000000000..94f258e1e9 --- /dev/null +++ b/src/mainboard/google/volteer/variants/ripto/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 95 08 00 00 00 00 02 01 00 00 +48 00 04 00 92 55 00 00 8C 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex b/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex new file mode 100644 index 0000000000..94f258e1e9 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 95 08 00 00 00 00 02 01 00 00 +48 00 04 00 92 55 00 00 8C 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex b/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex similarity index 100% rename from src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex rename to src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex From 70063ff565cbc9fafd54dc3efeb313d1789ce9eb Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 11 May 2020 14:28:13 -0700 Subject: [PATCH 052/405] soc/amd/common/block: Add support for configuring eSPI connection to slave This change adds a helper function espi_setup() which allows SoCs to configure connection to slave. Most of the configuration is dependent upon mainboard settings in espi_config done as part of the device tree. The general flow for setup involves the following steps: 1. Set initial configuration (lowest operating frequency and single mode). 2. Perform in-band reset and set initial configuration since the settings would be lost by the reset. 3. Read slave capabilities. 4. Set slave configuration based on mainboard settings. 5. Perform eSPI host controller configuration to match the slave configuration and set polarities for VW interrupts. 6. Perform VW channel setup and deassert PLTRST#. 7. Perform peripheral channel setup. 8. Perform OOB channel setup. 9. Perform flash channel setup. 10. Enable subtractive decoding if requested by mainboard. BUG=b:153675913 Signed-off-by: Furquan Shaikh Change-Id: I872ec09cd92e9bb53f22e38d2773f3491355279e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41272 Reviewed-by: Aaron Durbin Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- .../amd/common/block/include/amdblocks/espi.h | 61 ++ src/soc/amd/common/block/lpc/espi_util.c | 630 ++++++++++++++++++ 2 files changed, 691 insertions(+) diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index f47386bc5d..e882af0305 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -26,6 +26,46 @@ #define ESPI_GENERIC_MMIO_WIN_COUNT 4 #define ESPI_GENERIC_MMIO_MAX_WIN_SIZE 0x10000 +#define ESPI_SLAVE0_CONFIG 0x68 +#define ESPI_CRC_CHECKING_EN (1 << 31) +#define ESPI_ALERT_MODE (1 << 30) + +#define ESPI_IO_MODE_SHIFT 28 +#define ESPI_IO_MODE_MASK (0x3 << ESPI_IO_MODE_SHIFT) +#define ESPI_IO_MODE_VALUE(x) ((x) << ESPI_IO_MODE_SHIFT) + +#define ESPI_OP_FREQ_SHIFT 25 +#define ESPI_OP_FREQ_MASK (0x7 << ESPI_OP_FREQ_SHIFT) +#define ESPI_OP_FREQ_VALUE(x) ((x) << ESPI_OP_FREQ_SHIFT) + +#define ESPI_PERIPH_CH_EN (1 << 3) +#define ESPI_VW_CH_EN (1 << 2) +#define ESPI_OOB_CH_EN (1 << 1) +#define ESPI_FLASH_CH_EN (1 << 0) + +/* + * Virtual wire interrupt polarity. If the interrupt is active level high or active falling + * edge, then controller expects its bit to be cleared in ESPI_RXVW_POLARITY whereas if the + * interrupt is active level low or active rising edge, then its bit needs to be set in + * ESPI_RXVW_POLARITY. + */ +#define ESPI_VW_IRQ_LEVEL_HIGH(x) (0 << (x)) +#define ESPI_VW_IRQ_LEVEL_LOW(x) (1 << (x)) +#define ESPI_VW_IRQ_EDGE_HIGH(x) (1 << (x)) +#define ESPI_VW_IRQ_EDGE_LOW(x) (0 << (x)) + +enum espi_io_mode { + ESPI_IO_MODE_SINGLE = ESPI_IO_MODE_VALUE(0), + ESPI_IO_MODE_DUAL = ESPI_IO_MODE_VALUE(1), + ESPI_IO_MODE_QUAD = ESPI_IO_MODE_VALUE(2), +}; + +enum espi_op_freq { + ESPI_OP_FREQ_16_MHZ = ESPI_OP_FREQ_VALUE(0), + ESPI_OP_FREQ_33_MHZ = ESPI_OP_FREQ_VALUE(1), + ESPI_OP_FREQ_66_MHZ = ESPI_OP_FREQ_VALUE(2), +}; + struct espi_config { /* Bitmap for standard IO decodes. Use ESPI_DECODE_IO_* above. */ uint32_t std_io_decode_bitmap; @@ -34,6 +74,21 @@ struct espi_config { uint16_t base; size_t size; } generic_io_range[ESPI_GENERIC_IO_WIN_COUNT]; + + /* Slave configuration parameters */ + enum espi_io_mode io_mode; + enum espi_op_freq op_freq_mhz; + + uint32_t crc_check_enable:1; + uint32_t dedicated_alert_pin:1; + uint32_t periph_ch_en:1; + uint32_t vw_ch_en:1; + uint32_t oob_ch_en:1; + uint32_t flash_ch_en:1; + uint32_t subtractive_decode:1; + + /* Use ESPI_VW_IRQ_* above */ + uint32_t vw_irq_polarity; }; /* @@ -60,4 +115,10 @@ void espi_configure_decodes(void); */ void espi_update_static_bar(uintptr_t bar); +/* + * Perform eSPI connection setup to the slave. Currently, this supports slave0 only. + * Returns 0 on success and -1 on error. + */ +int espi_setup(void); + #endif /* __AMDBLOCKS_ESPI_H__ */ diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 83f36957bd..5ca0d2831a 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -5,9 +5,11 @@ #include #include #include +#include #include #include #include +#include #include static uintptr_t espi_bar; @@ -302,3 +304,631 @@ void espi_configure_decodes(void) cfg->generic_io_range[i].size); } } + +#define ESPI_DN_TX_HDR0 0x00 +enum espi_cmd_type { + CMD_TYPE_SET_CONFIGURATION = 0, + CMD_TYPE_GET_CONFIGURATION = 1, + CMD_TYPE_IN_BAND_RESET = 2, + CMD_TYPE_PERIPHERAL = 4, + CMD_TYPE_VW = 5, + CMD_TYPE_OOB = 6, + CMD_TYPE_FLASH = 7, +}; + +#define ESPI_DN_TX_HDR1 0x04 +#define ESPI_DN_TX_HDR2 0x08 +#define ESPI_DN_TX_DATA 0x0c + +#define ESPI_MASTER_CAP 0x2c +#define ESPI_VW_MAX_SIZE_SHIFT 13 +#define ESPI_VW_MAX_SIZE_MASK (0x3f << ESPI_VW_MAX_SIZE_SHIFT) + +#define ESPI_GLOBAL_CONTROL_1 0x34 +#define ESPI_SUB_DECODE_SLV_SHIFT 3 +#define ESPI_SUB_DECODE_SLV_MASK (0x3 << ESPI_SUB_DECODE_SLV_SHIFT) +#define ESPI_SUB_DECODE_EN (1 << 2) + +#define SLAVE0_INT_STS 0x70 +#define ESPI_STATUS_DNCMD_COMPLETE (1 << 28) +#define ESPI_STATUS_NON_FATAL_ERROR (1 << 6) +#define ESPI_STATUS_FATAL_ERROR (1 << 5) +#define ESPI_STATUS_NO_RESPONSE (1 << 4) +#define ESPI_STATUS_CRC_ERR (1 << 2) +#define ESPI_STATUS_WAIT_TIMEOUT (1 << 1) +#define ESPI_STATUS_BUS_ERROR (1 << 0) + +#define ESPI_RXVW_POLARITY 0xac + +#define ESPI_CMD_TIMEOUT_US 100 +#define ESPI_CH_READY_TIMEOUT_US 1000 + +union espi_txhdr0 { + uint32_t val; + struct { + uint32_t cmd_type:3; + uint32_t cmd_sts:1; + uint32_t slave_sel:2; + uint32_t rsvd:2; + uint32_t hdata0:8; + uint32_t hdata1:8; + uint32_t hdata2:8; + }; +} __packed; + +union espi_txhdr1 { + uint32_t val; + struct { + uint32_t hdata3:8; + uint32_t hdata4:8; + uint32_t hdata5:8; + uint32_t hdata6:8; + }; +} __packed; + +union espi_txhdr2 { + uint32_t val; + struct { + uint32_t hdata7:8; + uint32_t rsvd:24; + }; +} __packed; + +union espi_txdata { + uint32_t val; + struct { + uint32_t byte0:8; + uint32_t byte1:8; + uint32_t byte2:8; + uint32_t byte3:8; + }; +} __packed; + +struct espi_cmd { + union espi_txhdr0 hdr0; + union espi_txhdr1 hdr1; + union espi_txhdr2 hdr2; + union espi_txdata data; +} __packed; + +/* Wait up to ESPI_CMD_TIMEOUT_US for hardware to clear DNCMD_STATUS bit. */ +static int espi_wait_ready(void) +{ + struct stopwatch sw; + union espi_txhdr0 hdr0; + + stopwatch_init_usecs_expire(&sw, ESPI_CMD_TIMEOUT_US); + do { + hdr0.val = espi_read32(ESPI_DN_TX_HDR0); + if (!hdr0.cmd_sts) + return 0; + } while (!stopwatch_expired(&sw)); + + return -1; +} + +/* Clear interrupt status register */ +static void espi_clear_status(void) +{ + uint32_t status = espi_read32(SLAVE0_INT_STS); + if (status) + espi_write32(SLAVE0_INT_STS, status); +} + +/* + * Wait up to ESPI_CMD_TIMEOUT_US for interrupt status register to update after sending a + * command. + */ +static int espi_check_status(uint32_t *status) +{ + struct stopwatch sw; + + stopwatch_init_usecs_expire(&sw, ESPI_CMD_TIMEOUT_US); + do { + *status = espi_read32(SLAVE0_INT_STS); + if (*status) + return 0; + } while (!stopwatch_expired(&sw)); + + printk(BIOS_ERR, "Error: eSPI timed out waiting for status update.\n"); + + return -1; +} + +static void espi_show_failure(const struct espi_cmd *cmd, const char *str, uint32_t status) +{ + printk(BIOS_ERR, "eSPI cmd0-cmd2: %08x %08x %08x data: %08x.\n", + cmd->hdr0.val, cmd->hdr1.val, cmd->hdr2.val, cmd->data.val); + printk(BIOS_ERR, "%s (Status = 0x%x)\n", str, status); +} + +static int espi_send_command(const struct espi_cmd *cmd) +{ + uint32_t status; + + if (CONFIG(ESPI_DEBUG)) + printk(BIOS_ERR, "eSPI cmd0-cmd2: %08x %08x %08x data: %08x.\n", + cmd->hdr0.val, cmd->hdr1.val, cmd->hdr2.val, cmd->data.val); + + if (espi_wait_ready() == -1) { + espi_show_failure(cmd, "Error: eSPI was not ready to accept a command", 0); + return -1; + } + + espi_clear_status(); + + espi_write32(ESPI_DN_TX_HDR1, cmd->hdr1.val); + espi_write32(ESPI_DN_TX_HDR2, cmd->hdr2.val); + espi_write32(ESPI_DN_TX_DATA, cmd->data.val); + + /* Dword 0 must be last as this write triggers the transaction */ + espi_write32(ESPI_DN_TX_HDR0, cmd->hdr0.val); + + if (espi_wait_ready() == -1) { + espi_show_failure(cmd, + "Error: eSPI timed out waiting for command to complete", 0); + return -1; + } + + if (espi_check_status(&status) == -1) { + espi_show_failure(cmd, "Error: eSPI check status failed", 0); + return -1; + } + + /* If command did not complete downstream, return error. */ + if (!(status & ESPI_STATUS_DNCMD_COMPLETE)) { + espi_show_failure(cmd, "Error: eSPI downstream command completion failure", + status); + return -1; + } + + if (status & ~ESPI_STATUS_DNCMD_COMPLETE) { + espi_show_failure(cmd, "Error: eSPI status register bits set", status); + return -1; + } + + return 0; +} + +static int espi_send_reset(void) +{ + struct espi_cmd cmd = { + .hdr0 = { + .cmd_type = CMD_TYPE_IN_BAND_RESET, + .cmd_sts = 1, + }, + }; + + return espi_send_command(&cmd); +} + +static int espi_send_pltrst_deassert(const struct espi_config *mb_cfg) +{ + struct espi_cmd cmd = { + .hdr0 = { + .cmd_type = CMD_TYPE_VW, + .cmd_sts = 1, + .hdata0 = 0, /* 1 VW group */ + }, + .data = { + .byte0 = ESPI_VW_INDEX_SYSTEM_EVENT_3, + .byte1 = ESPI_VW_SIGNAL_HIGH(ESPI_VW_PLTRST), + }, + }; + + if (!mb_cfg->vw_ch_en) + return 0; + + return espi_send_command(&cmd); +} + +/* + * In case of get configuration command, hdata0 contains bits 15:8 of the slave register address + * and hdata1 contains bits 7:0 of the slave register address. + */ +#define ESPI_CONFIGURATION_HDATA0(a) (((a) >> 8) & 0xff) +#define ESPI_CONFIGURATION_HDATA1(a) ((a) & 0xff) + +static int espi_get_configuration(uint16_t slave_reg_addr, uint32_t *config) +{ + struct espi_cmd cmd = { + .hdr0 = { + .cmd_type = CMD_TYPE_GET_CONFIGURATION, + .cmd_sts = 1, + .hdata0 = ESPI_CONFIGURATION_HDATA0(slave_reg_addr), + .hdata1 = ESPI_CONFIGURATION_HDATA1(slave_reg_addr), + }, + }; + + *config = 0; + + if (espi_send_command(&cmd)) + return -1; + + *config = espi_read32(ESPI_DN_TX_HDR1); + + if (CONFIG(ESPI_DEBUG)) + printk(BIOS_DEBUG, "Get configuration for slave register(0x%x): 0x%x\n", + slave_reg_addr, *config); + + return 0; +} + +static int espi_set_configuration(uint16_t slave_reg_addr, uint32_t config) +{ + struct espi_cmd cmd = { + .hdr0 = { + .cmd_type = CMD_TYPE_SET_CONFIGURATION, + .cmd_sts = 1, + .hdata0 = ESPI_CONFIGURATION_HDATA0(slave_reg_addr), + .hdata1 = ESPI_CONFIGURATION_HDATA1(slave_reg_addr), + }, + .hdr1 = { + .val = config, + }, + }; + + return espi_send_command(&cmd); +} + +static int espi_get_general_configuration(uint32_t *config) +{ + int ret = espi_get_configuration(ESPI_SLAVE_GENERAL_CFG, config); + if (ret == -1) + return -1; + + espi_show_slave_general_configuration(*config); + return 0; +} + +static void espi_set_io_mode_config(enum espi_io_mode mb_io_mode, uint32_t slave_caps, + uint32_t *slave_config, uint32_t *ctrlr_config) +{ + switch (mb_io_mode) { + case ESPI_IO_MODE_QUAD: + if (espi_slave_supports_quad_io(slave_caps)) { + *slave_config |= ESPI_SLAVE_IO_MODE_SEL_QUAD; + *ctrlr_config |= ESPI_IO_MODE_QUAD; + break; + } + printk(BIOS_ERR, "Error: eSPI Quad I/O not supported. Dropping to dual mode.\n"); + /* Intentional fall-through */ + case ESPI_IO_MODE_DUAL: + if (espi_slave_supports_dual_io(slave_caps)) { + *slave_config |= ESPI_SLAVE_IO_MODE_SEL_DUAL; + *ctrlr_config |= ESPI_IO_MODE_DUAL; + break; + } + printk(BIOS_ERR, + "Error: eSPI Dual I/O not supported. Dropping to single mode.\n"); + /* Intentional fall-through */ + case ESPI_IO_MODE_SINGLE: + /* Single I/O mode is always supported. */ + *slave_config |= ESPI_SLAVE_IO_MODE_SEL_SINGLE; + *ctrlr_config |= ESPI_IO_MODE_SINGLE; + break; + default: + die("No supported eSPI I/O modes!\n"); + } +} + +static void espi_set_op_freq_config(enum espi_op_freq mb_op_freq, uint32_t slave_caps, + uint32_t *slave_config, uint32_t *ctrlr_config) +{ + int slave_max_speed_mhz = espi_slave_max_speed_mhz_supported(slave_caps); + + switch (mb_op_freq) { + case ESPI_OP_FREQ_66_MHZ: + if (slave_max_speed_mhz >= 66) { + *slave_config |= ESPI_SLAVE_OP_FREQ_SEL_66_MHZ; + *ctrlr_config |= ESPI_OP_FREQ_66_MHZ; + break; + } + printk(BIOS_ERR, "Error: eSPI 66MHz not supported. Dropping to 33MHz.\n"); + /* Intentional fall-through */ + case ESPI_OP_FREQ_33_MHZ: + if (slave_max_speed_mhz >= 33) { + *slave_config |= ESPI_SLAVE_OP_FREQ_SEL_33_MHZ; + *ctrlr_config |= ESPI_OP_FREQ_33_MHZ; + break; + } + printk(BIOS_ERR, "Error: eSPI 33MHz not supported. Dropping to 16MHz.\n"); + /* Intentional fall-through */ + case ESPI_OP_FREQ_16_MHZ: + /* + * eSPI spec says the minimum frequency is 20MHz, but AMD datasheets support + * 16.7 Mhz. + */ + if (slave_max_speed_mhz > 0) { + *slave_config |= ESPI_SLAVE_OP_FREQ_SEL_20_MHZ; + *ctrlr_config |= ESPI_OP_FREQ_16_MHZ; + break; + } + /* Intentional fall-through */ + default: + die("No supported eSPI Operating Frequency!\n"); + } +} + +static int espi_set_general_configuration(const struct espi_config *mb_cfg, uint32_t slave_caps) +{ + uint32_t slave_config = 0; + uint32_t ctrlr_config = 0; + + if (mb_cfg->crc_check_enable) { + slave_config |= ESPI_SLAVE_CRC_ENABLE; + ctrlr_config |= ESPI_CRC_CHECKING_EN; + } + + if (mb_cfg->dedicated_alert_pin) { + slave_config |= ESPI_SLAVE_ALERT_MODE_PIN; + ctrlr_config |= ESPI_ALERT_MODE; + } + + espi_set_io_mode_config(mb_cfg->io_mode, slave_caps, &slave_config, &ctrlr_config); + espi_set_op_freq_config(mb_cfg->op_freq_mhz, slave_caps, &slave_config, &ctrlr_config); + + if (CONFIG(ESPI_DEBUG)) + printk(BIOS_INFO, "Setting general configuration: slave: 0x%x controller: 0x%x\n", + slave_config, ctrlr_config); + + if (espi_set_configuration(ESPI_SLAVE_GENERAL_CFG, slave_config) == -1) + return -1; + + espi_write32(ESPI_SLAVE0_CONFIG, ctrlr_config); + return 0; +} + +static int espi_wait_channel_ready(uint16_t slave_reg_addr) +{ + struct stopwatch sw; + uint32_t config; + + stopwatch_init_usecs_expire(&sw, ESPI_CH_READY_TIMEOUT_US); + do { + espi_get_configuration(slave_reg_addr, &config); + if (espi_slave_is_channel_ready(config)) + return 0; + } while (!stopwatch_expired(&sw)); + + printk(BIOS_ERR, "Error: Channel is not ready after %d usec (slave addr: 0x%x)\n", + ESPI_CH_READY_TIMEOUT_US, slave_reg_addr); + return -1; + +} + +static void espi_enable_ctrlr_channel(uint32_t channel_en) +{ + uint32_t reg = espi_read32(ESPI_SLAVE0_CONFIG); + + reg |= channel_en; + + espi_write32(ESPI_SLAVE0_CONFIG, reg); +} + +static int espi_set_channel_configuration(uint32_t slave_config, uint32_t slave_reg_addr, + uint32_t ctrlr_enable) +{ + if (espi_set_configuration(slave_reg_addr, slave_config) == -1) + return -1; + + if (!(slave_config & ESPI_SLAVE_CHANNEL_ENABLE)) + return 0; + + if (espi_wait_channel_ready(slave_reg_addr) == -1) + return -1; + + espi_enable_ctrlr_channel(ctrlr_enable); + return 0; +} + +static int espi_setup_vw_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) +{ + uint32_t slave_vw_caps; + uint32_t ctrlr_vw_caps; + uint32_t slave_vw_count_supp; + uint32_t ctrlr_vw_count_supp; + uint32_t use_vw_count; + uint32_t slave_config; + + if (!mb_cfg->vw_ch_en) + return 0; + + if (!espi_slave_supports_vw_channel(slave_caps)) { + printk(BIOS_ERR, "Error: eSPI slave doesn't support VW channel!\n"); + return -1; + } + + if (espi_get_configuration(ESPI_SLAVE_VW_CFG, &slave_vw_caps) == -1) + return -1; + + ctrlr_vw_caps = espi_read32(ESPI_MASTER_CAP); + ctrlr_vw_count_supp = (ctrlr_vw_caps & ESPI_VW_MAX_SIZE_MASK) >> ESPI_VW_MAX_SIZE_SHIFT; + + slave_vw_count_supp = espi_slave_get_vw_count_supp(slave_vw_caps); + use_vw_count = MIN(ctrlr_vw_count_supp, slave_vw_count_supp); + + slave_config = ESPI_SLAVE_CHANNEL_ENABLE | ESPI_SLAVE_VW_COUNT_SEL_VAL(use_vw_count); + return espi_set_channel_configuration(slave_config, ESPI_SLAVE_VW_CFG, ESPI_VW_CH_EN); +} + +static int espi_setup_periph_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) +{ + uint32_t slave_config; + /* Peripheral channel requires BME bit to be set when enabling the channel. */ + const uint32_t slave_en_mask = ESPI_SLAVE_CHANNEL_READY | + ESPI_SLAVE_PERIPH_BUS_MASTER_ENABLE; + + if (espi_get_configuration(ESPI_SLAVE_PERIPH_CFG, &slave_config) == -1) + return -1; + + /* + * Peripheral channel is the only one which is enabled on reset. So, if the mainboard + * wants to disable it, set configuration to disable peripheral channel. It also + * requires that BME bit be cleared. + */ + if (mb_cfg->periph_ch_en) { + if (!espi_slave_supports_periph_channel(slave_caps)) { + printk(BIOS_ERR, "Error: eSPI slave doesn't support periph channel!\n"); + return -1; + } + slave_config |= slave_en_mask; + } else { + slave_config &= ~slave_en_mask; + } + + return espi_set_channel_configuration(slave_config, ESPI_SLAVE_PERIPH_CFG, + ESPI_PERIPH_CH_EN); +} + +static int espi_setup_oob_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) +{ + uint32_t slave_config; + + if (!mb_cfg->oob_ch_en) + return 0; + + if (!espi_slave_supports_oob_channel(slave_caps)) { + printk(BIOS_ERR, "Error: eSPI slave doesn't support OOB channel!\n"); + return -1; + } + + if (espi_get_configuration(ESPI_SLAVE_OOB_CFG, &slave_config) == -1) + return -1; + + slave_config |= ESPI_SLAVE_CHANNEL_ENABLE; + + return espi_set_channel_configuration(slave_config, ESPI_SLAVE_OOB_CFG, + ESPI_OOB_CH_EN); +} + +static int espi_setup_flash_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) +{ + uint32_t slave_config; + + if (!mb_cfg->flash_ch_en) + return 0; + + if (!espi_slave_supports_flash_channel(slave_caps)) { + printk(BIOS_ERR, "Error: eSPI slave doesn't support flash channel!\n"); + return -1; + } + + if (espi_get_configuration(ESPI_SLAVE_FLASH_CFG, &slave_config) == -1) + return -1; + + slave_config |= ESPI_SLAVE_CHANNEL_ENABLE; + + return espi_set_channel_configuration(slave_config, ESPI_SLAVE_FLASH_CFG, + ESPI_FLASH_CH_EN); +} + +static void espi_set_initial_config(const struct espi_config *mb_cfg) +{ + uint32_t espi_initial_mode = ESPI_OP_FREQ_16_MHZ | ESPI_IO_MODE_SINGLE; + + if (mb_cfg->dedicated_alert_pin) + espi_initial_mode |= ESPI_ALERT_MODE; + + espi_write32(ESPI_SLAVE0_CONFIG, espi_initial_mode); +} + +static void espi_setup_subtractive_decode(const struct espi_config *mb_cfg) +{ + uint32_t global_ctrl_reg; + global_ctrl_reg = espi_read32(ESPI_GLOBAL_CONTROL_1); + + if (mb_cfg->subtractive_decode) { + global_ctrl_reg &= ~ESPI_SUB_DECODE_SLV_MASK; + global_ctrl_reg |= ESPI_SUB_DECODE_EN; + + } else { + global_ctrl_reg &= ~ESPI_SUB_DECODE_EN; + } + espi_write32(ESPI_GLOBAL_CONTROL_1, global_ctrl_reg); +} + +int espi_setup(void) +{ + uint32_t slave_caps; + const struct espi_config *cfg = espi_get_config(); + + /* + * Boot sequence: Step 1 + * Set correct initial configuration to talk to the slave: + * Set clock frequency to 16.7MHz and single IO mode. + */ + espi_set_initial_config(cfg); + + /* + * Boot sequence: Step 2 + * Send in-band reset + * The resets affects both host and slave devices, so set initial config again. + */ + if (espi_send_reset() == -1) { + printk(BIOS_ERR, "Error: In-band reset failed!\n"); + return -1; + } + espi_set_initial_config(cfg); + + /* + * Boot sequence: Step 3 + * Get configuration of slave device. + */ + if (espi_get_general_configuration(&slave_caps) == -1) { + printk(BIOS_ERR, "Error: Slave GET_CONFIGURATION failed!\n"); + return -1; + } + + /* + * Boot sequence: + * Step 4: Write slave device general config + * Step 5: Set host slave config + */ + if (espi_set_general_configuration(cfg, slave_caps) == -1) { + printk(BIOS_ERR, "Error: Slave SET_CONFIGURATION failed!\n"); + return -1; + } + + /* + * Setup polarity before enabling the VW channel so any interrupts + * received will have the correct polarity. + */ + espi_write32(ESPI_RXVW_POLARITY, cfg->vw_irq_polarity); + + /* + * Boot Sequences: Steps 6 - 9 + * Channel setup + */ + /* Set up VW first so we can deassert PLTRST#. */ + if (espi_setup_vw_channel(cfg, slave_caps) == -1) { + printk(BIOS_ERR, "Error: Setup VW channel failed!\n"); + return -1; + } + + /* De-assert PLTRST# if VW channel is enabled by mainboard. */ + if (espi_send_pltrst_deassert(cfg) == -1) { + printk(BIOS_ERR, "Error: PLTRST deassertion failed!\n"); + return -1; + } + + if (espi_setup_periph_channel(cfg, slave_caps) == -1) { + printk(BIOS_ERR, "Error: Setup Periph channel failed!\n"); + return -1; + } + + if (espi_setup_oob_channel(cfg, slave_caps) == -1) { + printk(BIOS_ERR, "Error: Setup OOB channel failed!\n"); + return -1; + } + + if (espi_setup_flash_channel(cfg, slave_caps) == -1) { + printk(BIOS_ERR, "Error: Setup Flash channel failed!\n"); + return -1; + } + + /* Enable subtractive decode if configured */ + espi_setup_subtractive_decode(cfg); + + return 0; +} From ed8ceabf3e557bdaa104ebcab1cc98dc56b3536c Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 9 May 2020 17:35:02 -0700 Subject: [PATCH 053/405] soc/amd/picasso: Use lpc_early_init() from common lpc driver This change uses lpc_early_init() for enabling and configuring LPC using the common block LPC driver. Signed-off-by: Furquan Shaikh Change-Id: I65784b481ae598bf3a85392ae4fe281aac974097 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41273 Reviewed-by: Aaron Durbin Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/southbridge.c | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index c871ec9f58..2df193abbc 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -165,16 +165,6 @@ void enable_aoac_devices(void) } while (!status); } -static void sb_enable_lpc(void) -{ - u8 byte; - - /* Enable LPC controller */ - byte = pm_io_read8(PM_LPC_GATING); - byte |= PM_LPC_ENABLE; - pm_io_write8(PM_LPC_GATING, byte); -} - static void sb_enable_cf9_io(void) { uint32_t reg = pm_read32(PM_DECODE_EN); @@ -215,11 +205,7 @@ static void fch_smbus_init(void) /* Before console init */ void fch_pre_init(void) { - /* Turn on LPC in case the PSP didn't use it. However, ensure all - * decoding is cleared as the PSP may have enabled decode paths. */ - sb_enable_lpc(); - lpc_disable_decodes(); - + lpc_early_init(); if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80) && CONFIG(PICASSO_LPC_IOMUX)) lpc_enable_port80(); From 702cf30e987ef07533ef589035d7256c0be3d52c Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 9 May 2020 18:30:51 -0700 Subject: [PATCH 054/405] soc/amd/picasso: Enable eSPI capability for Picasso This change selects SOC_AMD_COMMON_BLOCK_HAS_ESPI which enables the capability for using eSPI on Picasso. Additionally, it also calls espi_setup() and espi_configure_decodes() if mainboard enables use of eSPI and skips LPC decodes in that case. BUG=b:153675913,b:154445472 Change-Id: I4876f1bff4305a23e8ccc48a2d0d3b64cdc9703d Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41075 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Raul Rangel --- src/soc/amd/picasso/Kconfig | 1 + src/soc/amd/picasso/southbridge.c | 19 ++++++++++++++++--- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index ba441460c5..b065e2fcfd 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -28,6 +28,7 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK + select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 2df193abbc..2261a30921 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -202,13 +203,20 @@ static void fch_smbus_init(void) asf_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); } +static void lpc_configure_decodes(void) +{ + if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80)) + lpc_enable_port80(); +} + /* Before console init */ void fch_pre_init(void) { lpc_early_init(); - if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80) - && CONFIG(PICASSO_LPC_IOMUX)) - lpc_enable_port80(); + + if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) + lpc_configure_decodes(); + fch_spi_early_init(); enable_acpimmio_decode_pm04(); fch_smbus_init(); @@ -280,6 +288,11 @@ void fch_early_init(void) if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) lpc_disable_spi_rom_sharing(); + + if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) { + espi_setup(); + espi_configure_decodes(); + } } void sb_enable(struct device *dev) From 4611ad8930f57aa0e394e476c613fae1a4931c13 Mon Sep 17 00:00:00 2001 From: Bill XIE Date: Sat, 21 Mar 2020 02:07:41 +0800 Subject: [PATCH 055/405] ec/lenovo/h8: Reintroduce h8_mb_init() for specific boards Mainboard specific dock-init mechanism introduced https://review.coreboot.org/c/coreboot/+/36093 works on most boards, but https://ticket.coreboot.org/issues/256 shows that some boards (e.g. x201 and t410) need communication with h8 EC to enable or disable dock, (in dock_connect() and dock_disconnect() respectively) so they must be done after the h8 EC is brought up, which is not garanteed in the above mainboard specific dock-init mechanism. This time, a hook function h8_mb_init() will be called at the end of h8_enable(). (in place of the ancient h8_mainboard_init_dock() removed in CB:36093) Its default implementation is a weak empty function, but could be overrided with a strong one for boards needing to perform actions which should be done after h8 EC is brought up. This should fix the regression detected in https://ticket.coreboot.org/issues/256 Change-Id: I3674fbfeab2ea2cd2a4453a8e77521157d553388 Signed-off-by: Bill XIE Reviewed-on: https://review.coreboot.org/c/coreboot/+/39708 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/ec/lenovo/h8/h8.c | 3 +++ src/ec/lenovo/h8/h8.h | 5 +++++ src/mainboard/lenovo/t410/dock.c | 5 +++-- src/mainboard/lenovo/t410/mainboard.c | 1 - src/mainboard/lenovo/x201/dock.c | 5 +++-- src/mainboard/lenovo/x201/mainboard.c | 2 -- 6 files changed, 14 insertions(+), 7 deletions(-) diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index c29364c9ef..aa1877eac6 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -221,6 +221,8 @@ struct device_operations h8_dev_ops = { .init = h8_init, }; +void __weak h8_mb_init(void){ /* NOOP */ } + static void h8_enable(struct device *dev) { struct ec_lenovo_h8_config *conf = dev->chip_info; @@ -340,6 +342,7 @@ static void h8_enable(struct device *dev) h8_charge_priority(val); h8_set_audio_mute(0); + h8_mb_init(); } struct chip_operations ec_lenovo_h8_ops = { diff --git a/src/ec/lenovo/h8/h8.h b/src/ec/lenovo/h8/h8.h index 6c2f86ab51..c5092c3a29 100644 --- a/src/ec/lenovo/h8/h8.h +++ b/src/ec/lenovo/h8/h8.h @@ -35,6 +35,11 @@ bool h8_wwan_nv_enable(void); bool h8_has_wwan(const struct device *dev); void h8_ssdt_generator(const struct device *dev); +/* + * boards needing specific h8-related inits could override it + */ +void h8_mb_init(void); + /* EC registers */ #define H8_CONFIG0 0x00 diff --git a/src/mainboard/lenovo/t410/dock.c b/src/mainboard/lenovo/t410/dock.c index 122376ac05..37a2908c1d 100644 --- a/src/mainboard/lenovo/t410/dock.c +++ b/src/mainboard/lenovo/t410/dock.c @@ -7,13 +7,14 @@ #include #include -void init_dock(void) +void h8_mb_init(void) { if (dock_present()) { printk(BIOS_DEBUG, "dock is connected\n"); dock_connect(); - } else + } else { printk(BIOS_DEBUG, "dock is not connected\n"); + } } void dock_connect(void) diff --git a/src/mainboard/lenovo/t410/mainboard.c b/src/mainboard/lenovo/t410/mainboard.c index c359173a4a..7953b2e575 100644 --- a/src/mainboard/lenovo/t410/mainboard.c +++ b/src/mainboard/lenovo/t410/mainboard.c @@ -10,7 +10,6 @@ static void mainboard_enable(struct device *dev) install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2); - init_dock(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lenovo/x201/dock.c b/src/mainboard/lenovo/x201/dock.c index 258d8f8eaa..7354eeeb41 100644 --- a/src/mainboard/lenovo/x201/dock.c +++ b/src/mainboard/lenovo/x201/dock.c @@ -7,13 +7,14 @@ #include #include -void init_dock(void) +void h8_mb_init(void) { if (dock_present()) { printk(BIOS_DEBUG, "dock is connected\n"); dock_connect(); - } else + } else { printk(BIOS_DEBUG, "dock is not connected\n"); + } } void dock_connect(void) diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index c35536df2d..beb99385f5 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -25,8 +25,6 @@ static void mainboard_enable(struct device *dev) install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2); - - init_dock(); } struct chip_operations mainboard_ops = { From f70bd99d2af3627b1dbdbea414941a12d6ecf6b3 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 7 May 2020 20:16:34 +0200 Subject: [PATCH 056/405] src: Remove unused '#include ' unused includes of found using following commande: diff <(git grep -l '#include ' -- src/) <(git grep -l 'int8_t\|uint8_t\|int16_t\|uint16_t\|int32_t\|uint32_t\|int64_t\| uint64_t\|intptr_t\|uintptr_t\|intmax_t\|uintmax_t\|s8\|u8\|s16\| u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|UINT8_MAX\|INT16_MIN\ |INT16_MAX\|UINT16_MAX\|INT32_MIN\|INT32_MAX\|UINT32_MAX\|INT64_MIN\ |INT64_MAX\|UINT64_MAX\|INTMAX_MIN\|INTMAX_MAX\|UINTMAX_MAX' -- src/) |grep '<' |grep -v vendor |grep -vF '.h' Change-Id: Icb9b54c6abfb18d1e263665981968a4d7cccabeb Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41148 Reviewed-by: Patrick Georgi Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/arch/arm/armv4/cache.c | 1 - src/arch/arm/armv7/cache_m.c | 1 - src/arch/riscv/virtual_memory.c | 1 - src/cpu/intel/haswell/finalize.c | 1 - src/cpu/intel/haswell/romstage.c | 1 - src/cpu/intel/model_2065x/finalize.c | 1 - src/cpu/intel/model_206ax/finalize.c | 1 - src/drivers/generic/adau7002/adau7002.c | 1 - src/drivers/generic/generic/generic.c | 1 - src/drivers/generic/max98357a/max98357a.c | 1 - src/drivers/gfx/generic/generic.c | 1 - src/drivers/i2c/da7219/da7219.c | 1 - src/drivers/i2c/generic/generic.c | 1 - src/drivers/i2c/hid/hid.c | 1 - src/drivers/i2c/max98373/max98373.c | 1 - src/drivers/i2c/max98927/max98927.c | 1 - src/drivers/i2c/rt5663/rt5663.c | 1 - src/drivers/i2c/sx9310/sx9310.c | 1 - src/drivers/i2c/tpm/chip.c | 1 - src/drivers/spi/acpi/acpi.c | 1 - src/drivers/usb/acpi/usb_acpi.c | 1 - src/mainboard/amd/thatcher/bootblock.c | 1 - src/mainboard/apple/macbook21/mptable.c | 1 - src/mainboard/apple/macbookair4_2/early_init.c | 1 - src/mainboard/asus/p2b/variants/p2b-d/mptable.c | 1 - src/mainboard/asus/p2b/variants/p2b-ds/mptable.c | 1 - src/mainboard/getac/p470/mptable.c | 1 - src/mainboard/google/auron/variants/auron_paine/pei_data.c | 1 - src/mainboard/google/auron/variants/auron_yuna/pei_data.c | 1 - src/mainboard/google/auron/variants/buddy/pei_data.c | 1 - src/mainboard/google/auron/variants/gandof/pei_data.c | 1 - src/mainboard/google/auron/variants/lulu/pei_data.c | 1 - src/mainboard/google/butterfly/acpi_tables.c | 1 - src/mainboard/google/jecht/variants/guado/pei_data.c | 1 - src/mainboard/google/jecht/variants/jecht/pei_data.c | 1 - src/mainboard/google/jecht/variants/rikku/pei_data.c | 1 - src/mainboard/google/jecht/variants/tidus/pei_data.c | 1 - src/mainboard/google/link/acpi_tables.c | 1 - src/mainboard/google/rambi/romstage.c | 1 - src/mainboard/hp/compaq_8200_elite_sff/early_init.c | 1 - src/mainboard/hp/z220_sff_workstation/early_init.c | 1 - src/mainboard/ibase/mb899/mptable.c | 1 - src/mainboard/intel/d945gclf/mptable.c | 1 - src/mainboard/intel/wtm2/pei_data.c | 1 - src/mainboard/intel/wtm2/romstage.c | 1 - src/mainboard/kontron/986lcd-m/mptable.c | 1 - src/mainboard/lenovo/t400/blc.c | 1 - src/mainboard/lenovo/t60/mptable.c | 1 - src/mainboard/lenovo/x230/early_init.c | 1 - src/mainboard/lenovo/x60/mptable.c | 1 - src/mainboard/roda/rk886ex/mptable.c | 1 - src/mainboard/roda/rk9/blc.c | 1 - src/mainboard/roda/rk9/mainboard.c | 1 - src/mainboard/sapphire/pureplatinumh61/early_init.c | 1 - src/northbridge/intel/e7505/northbridge.c | 1 - src/security/vboot/common.c | 1 - src/soc/intel/baytrail/dptf.c | 1 - src/soc/intel/baytrail/emmc.c | 1 - src/soc/intel/baytrail/perf_power.c | 1 - src/soc/intel/baytrail/tsc_freq.c | 1 - src/soc/intel/braswell/emmc.c | 1 - src/soc/intel/braswell/tsc_freq.c | 1 - src/soc/intel/braswell/xhci.c | 1 - src/soc/intel/broadwell/pei_data.c | 1 - src/soc/intel/broadwell/romstage/power_state.c | 1 - src/soc/intel/broadwell/tsc_freq.c | 1 - src/soc/intel/broadwell/usb_debug.c | 1 - src/soc/intel/denverton_ns/csme_ie_kt.c | 1 - src/soc/intel/skylake/me.c | 1 - src/southbridge/amd/cimx/sb800/early.c | 1 - src/southbridge/intel/bd82x6x/early_rcba.c | 1 - src/southbridge/intel/i82371eb/usb.c | 1 - src/southbridge/intel/ibexpeak/early_pch.c | 1 - 73 files changed, 73 deletions(-) diff --git a/src/arch/arm/armv4/cache.c b/src/arch/arm/armv4/cache.c index c667f6da3a..5f34c6049b 100644 --- a/src/arch/arm/armv4/cache.c +++ b/src/arch/arm/armv4/cache.c @@ -5,7 +5,6 @@ * Reference: ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition */ -#include #include diff --git a/src/arch/arm/armv7/cache_m.c b/src/arch/arm/armv7/cache_m.c index 88e94559f4..7267e83948 100644 --- a/src/arch/arm/armv7/cache_m.c +++ b/src/arch/arm/armv7/cache_m.c @@ -3,7 +3,6 @@ * cache.c: Cache maintenance routines for ARMv7-M */ -#include #include diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 467b93de16..43e3d70304 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -5,7 +5,6 @@ #include #include -#include #include /* Delegate controls which traps are delegated to the payload. If you diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c index 56571db127..a6d38ae6f7 100644 --- a/src/cpu/intel/haswell/finalize.c +++ b/src/cpu/intel/haswell/finalize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include "haswell.h" diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 921752ab5a..c682ef93f6 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index 53819be002..d530fba5e7 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 8b77bd1ac8..10a95a2ce5 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/drivers/generic/adau7002/adau7002.c b/src/drivers/generic/adau7002/adau7002.c index b61b1a0b78..88ee34da7b 100644 --- a/src/drivers/generic/adau7002/adau7002.c +++ b/src/drivers/generic/adau7002/adau7002.c @@ -5,7 +5,6 @@ #include #include #include -#include #include "chip.h" #if CONFIG(HAVE_ACPI_TABLES) diff --git a/src/drivers/generic/generic/generic.c b/src/drivers/generic/generic/generic.c index 0b6ae79420..a1f65995bf 100644 --- a/src/drivers/generic/generic/generic.c +++ b/src/drivers/generic/generic/generic.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include "chip.h" diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c index 6a0fcf5046..bd45296bcd 100644 --- a/src/drivers/generic/max98357a/max98357a.c +++ b/src/drivers/generic/max98357a/max98357a.c @@ -6,7 +6,6 @@ #include #include #include -#include #include "chip.h" #if CONFIG(HAVE_ACPI_TABLES) diff --git a/src/drivers/gfx/generic/generic.c b/src/drivers/gfx/generic/generic.c index 2c02106c35..546f30bead 100644 --- a/src/drivers/gfx/generic/generic.c +++ b/src/drivers/gfx/generic/generic.c @@ -5,7 +5,6 @@ #include #include #include -#include #include "chip.h" diff --git a/src/drivers/i2c/da7219/da7219.c b/src/drivers/i2c/da7219/da7219.c index 11a7adad0f..1d98023ff5 100644 --- a/src/drivers/i2c/da7219/da7219.c +++ b/src/drivers/i2c/da7219/da7219.c @@ -7,7 +7,6 @@ #include #include #include -#include #include "chip.h" diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 73b3aeae2f..5893a6fdad 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include "chip.h" diff --git a/src/drivers/i2c/hid/hid.c b/src/drivers/i2c/hid/hid.c index 9c49b750b0..0755852d94 100644 --- a/src/drivers/i2c/hid/hid.c +++ b/src/drivers/i2c/hid/hid.c @@ -2,7 +2,6 @@ #include #include -#include #include #include "chip.h" #include diff --git a/src/drivers/i2c/max98373/max98373.c b/src/drivers/i2c/max98373/max98373.c index bb8151829c..0557f421ca 100644 --- a/src/drivers/i2c/max98373/max98373.c +++ b/src/drivers/i2c/max98373/max98373.c @@ -7,7 +7,6 @@ #include #include #include -#include #include "chip.h" #define MAX98373_ACPI_NAME "MAXI" diff --git a/src/drivers/i2c/max98927/max98927.c b/src/drivers/i2c/max98927/max98927.c index ad6893f969..9429e4aa0d 100644 --- a/src/drivers/i2c/max98927/max98927.c +++ b/src/drivers/i2c/max98927/max98927.c @@ -7,7 +7,6 @@ #include #include #include -#include #include "chip.h" #define MAX98927_ACPI_NAME "MAXI" diff --git a/src/drivers/i2c/rt5663/rt5663.c b/src/drivers/i2c/rt5663/rt5663.c index e1f665246e..da12a4d761 100644 --- a/src/drivers/i2c/rt5663/rt5663.c +++ b/src/drivers/i2c/rt5663/rt5663.c @@ -7,7 +7,6 @@ #include #include #include -#include #include "chip.h" #define RT5663_ACPI_NAME "RT53" diff --git a/src/drivers/i2c/sx9310/sx9310.c b/src/drivers/i2c/sx9310/sx9310.c index 38dedc8c66..c12e4ea524 100644 --- a/src/drivers/i2c/sx9310/sx9310.c +++ b/src/drivers/i2c/sx9310/sx9310.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include "chip.h" diff --git a/src/drivers/i2c/tpm/chip.c b/src/drivers/i2c/tpm/chip.c index 4fd0f2bb3c..2baec423f1 100644 --- a/src/drivers/i2c/tpm/chip.c +++ b/src/drivers/i2c/tpm/chip.c @@ -6,7 +6,6 @@ #include #include #include -#include #include "tpm.h" #include "chip.h" diff --git a/src/drivers/spi/acpi/acpi.c b/src/drivers/spi/acpi/acpi.c index 8fb21d01f4..4127f9a93a 100644 --- a/src/drivers/spi/acpi/acpi.c +++ b/src/drivers/spi/acpi/acpi.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include "chip.h" diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index 4059db7f48..e136df0b38 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -6,7 +6,6 @@ #include #include #include -#include #include "chip.h" static bool usb_acpi_add_gpios_to_crs(struct drivers_usb_acpi_config *cfg) diff --git a/src/mainboard/amd/thatcher/bootblock.c b/src/mainboard/amd/thatcher/bootblock.c index 639c0c9d4c..468c938330 100644 --- a/src/mainboard/amd/thatcher/bootblock.c +++ b/src/mainboard/amd/thatcher/bootblock.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/apple/macbook21/mptable.c b/src/mainboard/apple/macbook21/mptable.c index f53ef2d27d..67827e2ab7 100644 --- a/src/mainboard/apple/macbook21/mptable.c +++ b/src/mainboard/apple/macbook21/mptable.c @@ -3,7 +3,6 @@ #include #include #include -#include static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/apple/macbookair4_2/early_init.c b/src/mainboard/apple/macbookair4_2/early_init.c index 153c53c415..63670e570d 100644 --- a/src/mainboard/apple/macbookair4_2/early_init.c +++ b/src/mainboard/apple/macbookair4_2/early_init.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/asus/p2b/variants/p2b-d/mptable.c b/src/mainboard/asus/p2b/variants/p2b-d/mptable.c index f2765758fe..590c8897f2 100644 --- a/src/mainboard/asus/p2b/variants/p2b-d/mptable.c +++ b/src/mainboard/asus/p2b/variants/p2b-d/mptable.c @@ -2,7 +2,6 @@ #include #include -#include static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/asus/p2b/variants/p2b-ds/mptable.c b/src/mainboard/asus/p2b/variants/p2b-ds/mptable.c index 03f5294d76..b8787c8756 100644 --- a/src/mainboard/asus/p2b/variants/p2b-ds/mptable.c +++ b/src/mainboard/asus/p2b/variants/p2b-ds/mptable.c @@ -2,7 +2,6 @@ #include #include -#include static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c index 6e3413cc03..603f1ba9b5 100644 --- a/src/mainboard/getac/p470/mptable.c +++ b/src/mainboard/getac/p470/mptable.c @@ -3,7 +3,6 @@ #include #include #include -#include static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/google/auron/variants/auron_paine/pei_data.c b/src/mainboard/google/auron/variants/auron_paine/pei_data.c index 3c0b03efa0..c2a22ae2a1 100644 --- a/src/mainboard/google/auron/variants/auron_paine/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_paine/pei_data.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c index 3c0b03efa0..c2a22ae2a1 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/auron/variants/buddy/pei_data.c b/src/mainboard/google/auron/variants/buddy/pei_data.c index ea6c6e9aec..026853ff25 100644 --- a/src/mainboard/google/auron/variants/buddy/pei_data.c +++ b/src/mainboard/google/auron/variants/buddy/pei_data.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/auron/variants/gandof/pei_data.c b/src/mainboard/google/auron/variants/gandof/pei_data.c index 3c0b03efa0..c2a22ae2a1 100644 --- a/src/mainboard/google/auron/variants/gandof/pei_data.c +++ b/src/mainboard/google/auron/variants/gandof/pei_data.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/auron/variants/lulu/pei_data.c b/src/mainboard/google/auron/variants/lulu/pei_data.c index 12bb8b8559..bbc7125330 100644 --- a/src/mainboard/google/auron/variants/lulu/pei_data.c +++ b/src/mainboard/google/auron/variants/lulu/pei_data.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c index db05e808f3..9680e8f489 100644 --- a/src/mainboard/google/butterfly/acpi_tables.c +++ b/src/mainboard/google/butterfly/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include "thermal.h" diff --git a/src/mainboard/google/jecht/variants/guado/pei_data.c b/src/mainboard/google/jecht/variants/guado/pei_data.c index d63013d5c4..ba950d6954 100644 --- a/src/mainboard/google/jecht/variants/guado/pei_data.c +++ b/src/mainboard/google/jecht/variants/guado/pei_data.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/jecht/variants/jecht/pei_data.c b/src/mainboard/google/jecht/variants/jecht/pei_data.c index d63013d5c4..ba950d6954 100644 --- a/src/mainboard/google/jecht/variants/jecht/pei_data.c +++ b/src/mainboard/google/jecht/variants/jecht/pei_data.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/jecht/variants/rikku/pei_data.c b/src/mainboard/google/jecht/variants/rikku/pei_data.c index d63013d5c4..ba950d6954 100644 --- a/src/mainboard/google/jecht/variants/rikku/pei_data.c +++ b/src/mainboard/google/jecht/variants/rikku/pei_data.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/jecht/variants/tidus/pei_data.c b/src/mainboard/google/jecht/variants/tidus/pei_data.c index 6fb2e50b6b..dc130224a4 100644 --- a/src/mainboard/google/jecht/variants/tidus/pei_data.c +++ b/src/mainboard/google/jecht/variants/tidus/pei_data.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c index e31b74011e..36b635e657 100644 --- a/src/mainboard/google/link/acpi_tables.c +++ b/src/mainboard/google/link/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index 854a9a6e0c..6487f43121 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/hp/compaq_8200_elite_sff/early_init.c b/src/mainboard/hp/compaq_8200_elite_sff/early_init.c index 49c1fa8dc3..873eeb3893 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/early_init.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/early_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/hp/z220_sff_workstation/early_init.c b/src/mainboard/hp/z220_sff_workstation/early_init.c index 149d480352..0a75614ecf 100644 --- a/src/mainboard/hp/z220_sff_workstation/early_init.c +++ b/src/mainboard/hp/z220_sff_workstation/early_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/ibase/mb899/mptable.c b/src/mainboard/ibase/mb899/mptable.c index e94a0cc473..7c632f572d 100644 --- a/src/mainboard/ibase/mb899/mptable.c +++ b/src/mainboard/ibase/mb899/mptable.c @@ -4,7 +4,6 @@ #include #include #include -#include static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c index a5d2c5e0cf..1b6a1b164d 100644 --- a/src/mainboard/intel/d945gclf/mptable.c +++ b/src/mainboard/intel/d945gclf/mptable.c @@ -3,7 +3,6 @@ #include #include #include -#include static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/intel/wtm2/pei_data.c b/src/mainboard/intel/wtm2/pei_data.c index 591fbe38e4..92101bdc51 100644 --- a/src/mainboard/intel/wtm2/pei_data.c +++ b/src/mainboard/intel/wtm2/pei_data.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index 3508f02a4e..9e22250935 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c index 4104f45a88..0c4ec67c7b 100644 --- a/src/mainboard/kontron/986lcd-m/mptable.c +++ b/src/mainboard/kontron/986lcd-m/mptable.c @@ -3,7 +3,6 @@ #include #include #include -#include static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/lenovo/t400/blc.c b/src/mainboard/lenovo/t400/blc.c index e1de97f5fa..823d9258e1 100644 --- a/src/mainboard/lenovo/t400/blc.c +++ b/src/mainboard/lenovo/t400/blc.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c index 96d2be7c50..2dc3a1aba0 100644 --- a/src/mainboard/lenovo/t60/mptable.c +++ b/src/mainboard/lenovo/t60/mptable.c @@ -3,7 +3,6 @@ #include #include #include -#include static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/lenovo/x230/early_init.c b/src/mainboard/lenovo/x230/early_init.c index 46b90cc070..2089ee6bb2 100644 --- a/src/mainboard/lenovo/x230/early_init.c +++ b/src/mainboard/lenovo/x230/early_init.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/lenovo/x60/mptable.c b/src/mainboard/lenovo/x60/mptable.c index 396dcbc84c..9e2cff101b 100644 --- a/src/mainboard/lenovo/x60/mptable.c +++ b/src/mainboard/lenovo/x60/mptable.c @@ -3,7 +3,6 @@ #include #include #include -#include static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c index bb5372c1aa..0ec750c82f 100644 --- a/src/mainboard/roda/rk886ex/mptable.c +++ b/src/mainboard/roda/rk886ex/mptable.c @@ -3,7 +3,6 @@ #include #include #include -#include static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/roda/rk9/blc.c b/src/mainboard/roda/rk9/blc.c index 1a054c819c..c3ee099ca5 100644 --- a/src/mainboard/roda/rk9/blc.c +++ b/src/mainboard/roda/rk9/blc.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include int get_blc_values(const struct blc_pwm_t **entries) diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c index ce5d0d21e1..8f157303e6 100644 --- a/src/mainboard/roda/rk9/mainboard.c +++ b/src/mainboard/roda/rk9/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/sapphire/pureplatinumh61/early_init.c b/src/mainboard/sapphire/pureplatinumh61/early_init.c index f04bb43791..3e652730cc 100644 --- a/src/mainboard/sapphire/pureplatinumh61/early_init.c +++ b/src/mainboard/sapphire/pureplatinumh61/early_init.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include #include #include diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index e6be17b53e..ee6ec5a0ec 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index e2b20b8bd4..97016907a7 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/baytrail/dptf.c b/src/soc/intel/baytrail/dptf.c index ee9cf169ba..d2658f92ca 100644 --- a/src/soc/intel/baytrail/dptf.c +++ b/src/soc/intel/baytrail/dptf.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c index 4cb558565b..623b149788 100644 --- a/src/soc/intel/baytrail/emmc.c +++ b/src/soc/intel/baytrail/emmc.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/intel/baytrail/perf_power.c b/src/soc/intel/baytrail/perf_power.c index d39178f8a6..563739277a 100644 --- a/src/soc/intel/baytrail/perf_power.c +++ b/src/soc/intel/baytrail/perf_power.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c index 033eb044a8..42ed584507 100644 --- a/src/soc/intel/baytrail/tsc_freq.c +++ b/src/soc/intel/baytrail/tsc_freq.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/intel/braswell/emmc.c b/src/soc/intel/braswell/emmc.c index 68a8ad3ec3..96f1f07036 100644 --- a/src/soc/intel/braswell/emmc.c +++ b/src/soc/intel/braswell/emmc.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index d171e9cc7f..ae0cce3cae 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -3,7 +3,6 @@ #include #include #include -#include static const unsigned int cpu_bus_clk_freq_table[] = { 83333, diff --git a/src/soc/intel/braswell/xhci.c b/src/soc/intel/braswell/xhci.c index 99db2c6d74..f84c204499 100644 --- a/src/soc/intel/braswell/xhci.c +++ b/src/soc/intel/braswell/xhci.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include diff --git a/src/soc/intel/broadwell/pei_data.c b/src/soc/intel/broadwell/pei_data.c index 6b51665da1..efc91fdfd6 100644 --- a/src/soc/intel/broadwell/pei_data.c +++ b/src/soc/intel/broadwell/pei_data.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c index 881315c584..8128458320 100644 --- a/src/soc/intel/broadwell/romstage/power_state.c +++ b/src/soc/intel/broadwell/romstage/power_state.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/broadwell/tsc_freq.c b/src/soc/intel/broadwell/tsc_freq.c index dfe325c882..4a8a34349f 100644 --- a/src/soc/intel/broadwell/tsc_freq.c +++ b/src/soc/intel/broadwell/tsc_freq.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/intel/broadwell/usb_debug.c b/src/soc/intel/broadwell/usb_debug.c index 954cbd29be..0fda336d14 100644 --- a/src/soc/intel/broadwell/usb_debug.c +++ b/src/soc/intel/broadwell/usb_debug.c @@ -3,7 +3,6 @@ // Use simple device model for this file even in ramstage #define __SIMPLE_DEVICE__ -#include #include #include diff --git a/src/soc/intel/denverton_ns/csme_ie_kt.c b/src/soc/intel/denverton_ns/csme_ie_kt.c index bf55009787..c104779182 100644 --- a/src/soc/intel/denverton_ns/csme_ie_kt.c +++ b/src/soc/intel/denverton_ns/csme_ie_kt.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index 873dcc16a2..0d6135fabd 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -9,7 +9,6 @@ #include #include #include -#include /* HFSTS1[3:0] Current Working State Values */ diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index d5c9916ff1..7ea179c94e 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include "SBPLATFORM.h" #include "sb_cimx.h" diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c index 1956cb6eac..29df6a38cb 100644 --- a/src/southbridge/intel/bd82x6x/early_rcba.c +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include "pch.h" diff --git a/src/southbridge/intel/i82371eb/usb.c b/src/southbridge/intel/i82371eb/usb.c index 0e530f4957..e3bcbebf82 100644 --- a/src/southbridge/intel/i82371eb/usb.c +++ b/src/southbridge/intel/i82371eb/usb.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include #include #include diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index 1732078b74..f1c7bb10e1 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include From e30c396ffabb3d3c966eecfcd291ca11b815ba7a Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 7 May 2020 21:08:49 +0200 Subject: [PATCH 057/405] src: Remove unused '#include ' Unused includes found using following commande: diff <(git grep -l '#include ' -- src/) <(git grep -l 'size_t\|ssize_t\|wchar_t\|wint_t\|NULL\|DEVTREE_EARLY\|DEVTREE_CONST\ |MAYBE_STATIC_NONZERO\|MAYBE_STATIC_BSS\|zeroptr' -- src/)|grep '<' |grep -v vendor |grep -vF '.h' Change-Id: Ic54b1db995fe7c61b416fa5e1c4022238e4a6ad5 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41150 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/cpu/ti/am335x/cbmem.c | 1 - src/cpu/ti/am335x/header.c | 1 - src/drivers/elog/boot_count.c | 1 - src/drivers/usb/pci_ehci.c | 1 - src/lib/edid.c | 1 - src/mainboard/google/eve/romstage.c | 1 - src/mainboard/google/kukui/boardid.c | 1 - src/mainboard/google/peach_pit/memory.c | 1 - src/mainboard/razer/blade_stealth_kbl/romstage.c | 1 - src/northbridge/intel/gm45/igd.c | 1 - src/northbridge/intel/gm45/pcie.c | 1 - src/northbridge/intel/gm45/pm.c | 1 - src/northbridge/intel/gm45/thermal.c | 1 - src/security/intel/stm/StmPlatformSmm.c | 1 - src/security/vboot/vboot_common.c | 1 - src/soc/intel/broadwell/romstage/romstage.c | 1 - src/soc/mediatek/common/cbmem.c | 1 - src/soc/mediatek/common/ddp.c | 1 - src/soc/mediatek/common/mtcmos.c | 1 - src/soc/mediatek/mt8173/ddp.c | 1 - src/soc/mediatek/mt8183/ddp.c | 1 - src/soc/mediatek/mt8183/pll.c | 1 - src/soc/rockchip/common/vop.c | 1 - src/soc/rockchip/rk3288/display.c | 1 - src/soc/rockchip/rk3288/soc.c | 1 - src/soc/rockchip/rk3399/soc.c | 1 - src/soc/samsung/exynos5250/cbmem.c | 1 - src/soc/samsung/exynos5250/cpu.c | 1 - src/soc/samsung/exynos5420/cbmem.c | 1 - src/soc/samsung/exynos5420/cpu.c | 1 - src/soc/samsung/exynos5420/i2c.c | 1 - src/soc/sifive/fu540/otp.c | 1 - src/soc/sifive/fu540/uart.c | 1 - 33 files changed, 33 deletions(-) diff --git a/src/cpu/ti/am335x/cbmem.c b/src/cpu/ti/am335x/cbmem.c index 0610d5991c..3765874ebe 100644 --- a/src/cpu/ti/am335x/cbmem.c +++ b/src/cpu/ti/am335x/cbmem.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include diff --git a/src/cpu/ti/am335x/header.c b/src/cpu/ti/am335x/header.c index 9ed99372a0..9edfdd062b 100644 --- a/src/cpu/ti/am335x/header.c +++ b/src/cpu/ti/am335x/header.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include #include diff --git a/src/drivers/elog/boot_count.c b/src/drivers/elog/boot_count.c index 72ed173503..9da62127dc 100644 --- a/src/drivers/elog/boot_count.c +++ b/src/drivers/elog/boot_count.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c index 993e6c64d6..d59ca32504 100644 --- a/src/drivers/usb/pci_ehci.c +++ b/src/drivers/usb/pci_ehci.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/lib/edid.c b/src/lib/edid.c index decc077042..78adf490fd 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -8,7 +8,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/google/eve/romstage.c b/src/mainboard/google/eve/romstage.c index 26c0361a8f..f3c0f1140b 100644 --- a/src/mainboard/google/eve/romstage.c +++ b/src/mainboard/google/eve/romstage.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c index f5955301e9..c6865d1a67 100644 --- a/src/mainboard/google/kukui/boardid.c +++ b/src/mainboard/google/kukui/boardid.c @@ -5,7 +5,6 @@ #include #include #include -#include /* For CBI un-provisioned/corrupted Flapjack board. */ #define FLAPJACK_UNDEF_SKU_ID 0 diff --git a/src/mainboard/google/peach_pit/memory.c b/src/mainboard/google/peach_pit/memory.c index 8630802d3e..4e82c90744 100644 --- a/src/mainboard/google/peach_pit/memory.c +++ b/src/mainboard/google/peach_pit/memory.c @@ -4,7 +4,6 @@ #include #include #include -#include const struct mem_timings mem_timings = { .mem_manuf = MEM_MANUF_SAMSUNG, diff --git a/src/mainboard/razer/blade_stealth_kbl/romstage.c b/src/mainboard/razer/blade_stealth_kbl/romstage.c index 94ca09a8f8..92ced2e613 100644 --- a/src/mainboard/razer/blade_stealth_kbl/romstage.c +++ b/src/mainboard/razer/blade_stealth_kbl/romstage.c @@ -7,7 +7,6 @@ #include "spd/spd.h" #include #include -#include #define SPD_4X_2GB 0 #define SPD_4X_4GB 1 diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index 10a6f84875..24633cf96e 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index 2cab42f4bb..e4d11e335c 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/northbridge/intel/gm45/pm.c b/src/northbridge/intel/gm45/pm.c index 6033c0aca2..680435baca 100644 --- a/src/northbridge/intel/gm45/pm.c +++ b/src/northbridge/intel/gm45/pm.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/northbridge/intel/gm45/thermal.c b/src/northbridge/intel/gm45/thermal.c index ed1ec959bd..a5d9820e71 100644 --- a/src/northbridge/intel/gm45/thermal.c +++ b/src/northbridge/intel/gm45/thermal.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c index de41f418bd..1f57b50f6d 100644 --- a/src/security/intel/stm/StmPlatformSmm.c +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -7,7 +7,6 @@ #include #include -#include #include #include #include diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index aeb6cefeb5..30a2c2f668 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 4b51bda6f0..54d6134b16 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/mediatek/common/cbmem.c b/src/soc/mediatek/common/cbmem.c index 871d7dd142..f9d11e91c5 100644 --- a/src/soc/mediatek/common/cbmem.c +++ b/src/soc/mediatek/common/cbmem.c @@ -2,7 +2,6 @@ #include #include -#include #include #include diff --git a/src/soc/mediatek/common/ddp.c b/src/soc/mediatek/common/ddp.c index 64e6e7a778..17a28494f7 100644 --- a/src/soc/mediatek/common/ddp.c +++ b/src/soc/mediatek/common/ddp.c @@ -2,7 +2,6 @@ #include #include -#include #include #include diff --git a/src/soc/mediatek/common/mtcmos.c b/src/soc/mediatek/common/mtcmos.c index e5d70b806d..71deb71c77 100644 --- a/src/soc/mediatek/common/mtcmos.c +++ b/src/soc/mediatek/common/mtcmos.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include diff --git a/src/soc/mediatek/mt8173/ddp.c b/src/soc/mediatek/mt8173/ddp.c index 93ef0b6544..ec53e12dee 100644 --- a/src/soc/mediatek/mt8173/ddp.c +++ b/src/soc/mediatek/mt8173/ddp.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c index d427dcb233..13918a07f4 100644 --- a/src/soc/mediatek/mt8183/ddp.c +++ b/src/soc/mediatek/mt8183/ddp.c @@ -2,7 +2,6 @@ #include #include -#include #include #include diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index dedd59d4f2..4570269421 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -2,7 +2,6 @@ #include #include -#include #include #include diff --git a/src/soc/rockchip/common/vop.c b/src/soc/rockchip/common/vop.c index 515395b7c3..5674339b04 100644 --- a/src/soc/rockchip/common/vop.c +++ b/src/soc/rockchip/common/vop.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index 2ad17b4f89..fd86b95d68 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index 4375f1bbc9..b23c803422 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include "chip.h" diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c index 92019a054e..89e33631bf 100644 --- a/src/soc/rockchip/rk3399/soc.c +++ b/src/soc/rockchip/rk3399/soc.c @@ -9,7 +9,6 @@ #include #include #include -#include #include void bootmem_platform_add_ranges(void) diff --git a/src/soc/samsung/exynos5250/cbmem.c b/src/soc/samsung/exynos5250/cbmem.c index 8aca86ad28..167bd80a3a 100644 --- a/src/soc/samsung/exynos5250/cbmem.c +++ b/src/soc/samsung/exynos5250/cbmem.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index b74b838bb7..514e451ede 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include "chip.h" diff --git a/src/soc/samsung/exynos5420/cbmem.c b/src/soc/samsung/exynos5420/cbmem.c index 5cee9be384..167bd80a3a 100644 --- a/src/soc/samsung/exynos5420/cbmem.c +++ b/src/soc/samsung/exynos5420/cbmem.c @@ -2,7 +2,6 @@ #include #include -#include void *cbmem_top_chipset(void) { diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index 4a294d55ad..8a07552cf6 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include "chip.h" diff --git a/src/soc/samsung/exynos5420/i2c.c b/src/soc/samsung/exynos5420/i2c.c index 416bb46f4c..45657f13cf 100644 --- a/src/soc/samsung/exynos5420/i2c.c +++ b/src/soc/samsung/exynos5420/i2c.c @@ -9,7 +9,6 @@ #include #include #include -#include #include struct __packed i2c_regs diff --git a/src/soc/sifive/fu540/otp.c b/src/soc/sifive/fu540/otp.c index ac74f82473..29f2c16271 100644 --- a/src/soc/sifive/fu540/otp.c +++ b/src/soc/sifive/fu540/otp.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/sifive/fu540/uart.c b/src/soc/sifive/fu540/uart.c index 6736a1694c..c35e0f6166 100644 --- a/src/soc/sifive/fu540/uart.c +++ b/src/soc/sifive/fu540/uart.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include From 6a197964d9f21305595d5f8dba3b7ad1f0547307 Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Wed, 6 May 2020 20:06:41 -0700 Subject: [PATCH 058/405] mb/google/volteer/variants/volteer: Add three generic SPD files - Add SPD_LPDDR4X_200b_1R_16Gb_16Row_DDP_4267.spd.hex, initially used for the SKhynix H9HCNNNBKMMLXR-NEE part with DRAM ID #2 - Add SPD_LPDDR4X_200b_2R_64Gb_ODP_4267.spd.hex, initially used for the SKhynix H9HCNNNFAMMLXR-NEE part with DRAM ID #3 - Add SPD_LPDDR4X_200b_2R_32Gb_QDP_4267.spd.hex, initially used for the Micron MT53E1G32D2NP-046 WT:A part with DRAM ID #4 BUG=b:147857288 TEST=none Change-Id: I60d8bb05a4d6d3608adc7de69efc8623d1ca610d Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/41126 Reviewed-by: Paul Menzel Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- .../volteer/variants/volteer/Makefile.inc | 9 ++++-- ...PDDR4X_200b_1R_16Gb_16Row_DDP_4267.spd.hex | 32 +++++++++++++++++++ .../SPD_LPDDR4X_200b_2R_32Gb_QDP_4267.spd.hex | 32 +++++++++++++++++++ .../SPD_LPDDR4X_200b_2R_64Gb_ODP_4267.spd.hex | 32 +++++++++++++++++++ 4 files changed, 102 insertions(+), 3 deletions(-) create mode 100644 src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_1R_16Gb_16Row_DDP_4267.spd.hex create mode 100644 src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_2R_32Gb_QDP_4267.spd.hex create mode 100644 src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_2R_64Gb_ODP_4267.spd.hex diff --git a/src/mainboard/google/volteer/variants/volteer/Makefile.inc b/src/mainboard/google/volteer/variants/volteer/Makefile.inc index 1bd6492c81..d075c1fe95 100644 --- a/src/mainboard/google/volteer/variants/volteer/Makefile.inc +++ b/src/mainboard/google/volteer/variants/volteer/Makefile.inc @@ -4,6 +4,9 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ## -## Memory Options -SPD_SOURCES = SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267 # 0b0000 -SPD_SOURCES += SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267 # 0b0001 +## Memory Options # DRAM ID # Part Num +SPD_SOURCES = SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267 # 0b0000 # K4U6E3S4AA-MGCL +SPD_SOURCES += SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267 # 0b0001 # K4UBE3D4AA-MGCL +SPD_SOURCES += SPD_LPDDR4X_200b_1R_16Gb_16Row_DDP_4267 # 0b0010 # H9HCNNNBKMMLXR-NEE +SPD_SOURCES += SPD_LPDDR4X_200b_2R_64Gb_ODP_4267 # 0b0011 # H9HCNNNFAMMLXR-NEE +SPD_SOURCES += SPD_LPDDR4X_200b_2R_32Gb_QDP_4267 # 0b0100 # MT53E1G32D2NP-046 WT:A diff --git a/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_1R_16Gb_16Row_DDP_4267.spd.hex b/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_1R_16Gb_16Row_DDP_4267.spd.hex new file mode 100644 index 0000000000..9ec70a9878 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_1R_16Gb_16Row_DDP_4267.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 95 08 00 00 00 00 02 01 00 00 +48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_2R_32Gb_QDP_4267.spd.hex b/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_2R_32Gb_QDP_4267.spd.hex new file mode 100644 index 0000000000..f2c52e2810 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_2R_32Gb_QDP_4267.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 B5 08 00 00 00 00 0A 01 00 00 +48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_2R_64Gb_ODP_4267.spd.hex b/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_2R_64Gb_ODP_4267.spd.hex new file mode 100644 index 0000000000..df96e70f06 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_2R_64Gb_ODP_4267.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 29 F9 08 00 00 00 00 09 01 00 00 +48 00 04 FF 92 55 00 00 8C 00 90 A8 90 E0 0B F0 +05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 From bc867d5b1d47e961b563431ec602934280fcbb96 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 11 May 2020 18:13:33 +0200 Subject: [PATCH 059/405] src/mainboard: Remove unused 'include ' Found using following commande: diff <(git grep -l '#include ' -- src/) <(git grep -l ' memalign\|malloc\|free' -- src/) |grep -v vendorcode |grep '<' Change-Id: Ib2ee840a10de5c10d57aa7a75b805ef69dc8da84 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41241 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/amd/inagua/BiosCallOuts.c | 1 - src/mainboard/amd/inagua/buildOpts.c | 1 - src/mainboard/amd/olivehill/BiosCallOuts.c | 1 - src/mainboard/amd/olivehill/buildOpts.c | 1 - src/mainboard/amd/parmer/BiosCallOuts.c | 1 - src/mainboard/amd/parmer/buildOpts.c | 1 - src/mainboard/amd/persimmon/BiosCallOuts.c | 1 - src/mainboard/amd/persimmon/buildOpts.c | 1 - src/mainboard/amd/south_station/BiosCallOuts.c | 1 - src/mainboard/amd/south_station/buildOpts.c | 1 - src/mainboard/amd/thatcher/BiosCallOuts.c | 1 - src/mainboard/amd/thatcher/buildOpts.c | 1 - src/mainboard/amd/union_station/BiosCallOuts.c | 1 - src/mainboard/amd/union_station/buildOpts.c | 1 - src/mainboard/asus/am1i-a/BiosCallOuts.c | 1 - src/mainboard/asus/am1i-a/buildOpts.c | 1 - src/mainboard/bap/ode_e20XX/BiosCallOuts.c | 1 - src/mainboard/bap/ode_e20XX/buildOpts.c | 1 - src/mainboard/bap/ode_e21XX/BiosCallOuts.c | 1 - src/mainboard/biostar/a68n_5200/BiosCallOuts.c | 1 - src/mainboard/biostar/a68n_5200/buildOpts.c | 1 - src/mainboard/elmex/pcm205400/BiosCallOuts.c | 1 - src/mainboard/elmex/pcm205400/buildOpts.c | 1 - src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c | 1 - src/mainboard/gizmosphere/gizmo2/buildOpts.c | 1 - src/mainboard/hp/abm/BiosCallOuts.c | 1 - src/mainboard/hp/abm/buildOpts.c | 1 - src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c | 1 - src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 1 - src/mainboard/lippert/frontrunner-af/BiosCallOuts.c | 1 - src/mainboard/lippert/frontrunner-af/buildOpts.c | 1 - src/mainboard/lippert/frontrunner-af/sema.c | 1 - src/mainboard/lippert/toucan-af/BiosCallOuts.c | 1 - src/mainboard/lippert/toucan-af/buildOpts.c | 1 - src/mainboard/lippert/toucan-af/mainboard.c | 1 - src/soc/intel/xeon_sp/skx/soc_util.c | 1 - src/soc/mediatek/mt8173/dramc_pi_calibration_api.c | 1 - src/soc/qualcomm/sc7180/usb.c | 1 - src/superio/nuvoton/nct5104d/superio.c | 1 - 39 files changed, 39 deletions(-) diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index d3336823c5..07b9ebd4c3 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -6,7 +6,6 @@ #include #include #include -#include static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index 18dcccd57c..b9d6a2cc3d 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -12,7 +12,6 @@ * */ -#include /* Select the CPU family. */ diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c index 8d4aa5de8c..d97f2b0a6a 100644 --- a/src/mainboard/amd/olivehill/BiosCallOuts.c +++ b/src/mainboard/amd/olivehill/BiosCallOuts.c @@ -4,7 +4,6 @@ #include #include #include -#include #include "imc.h" diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index 3fb482baf8..78a5596b93 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -12,7 +12,6 @@ * */ -#include #include #define INSTALL_FT3_SOCKET_SUPPORT TRUE diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index f68d46df7d..b553203abe 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -4,7 +4,6 @@ #include #include #include -#include #include "imc.h" diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 3b2910dfc3..bf610672ba 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -12,7 +12,6 @@ * */ -#include #include /* Select the CPU family. */ diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index 962e0899fc..4a6653e367 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -5,7 +5,6 @@ #include #include #include -#include static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index fdfa10156c..8432e7e88c 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -12,7 +12,6 @@ * */ -#include /* Select the CPU family. */ diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c index 2a7f373e9c..3e619be1a1 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.c +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -6,7 +6,6 @@ #include #include #include -#include static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index 06a6b5b4fc..4ad8a7ff68 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -12,7 +12,6 @@ * */ -#include /* Select the CPU family. */ diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index ef96bac8f9..1cba1a3cd9 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -4,7 +4,6 @@ #include #include #include -#include #include "imc.h" diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index c27e8fcd46..de1f89fb0a 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -12,7 +12,6 @@ * */ -#include #include /* Select the CPU family. */ diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c index 5be68ed432..a5634ecfd0 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.c +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -6,7 +6,6 @@ #include #include #include -#include static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index 06a6b5b4fc..4ad8a7ff68 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -12,7 +12,6 @@ * */ -#include /* Select the CPU family. */ diff --git a/src/mainboard/asus/am1i-a/BiosCallOuts.c b/src/mainboard/asus/am1i-a/BiosCallOuts.c index f9fa02b25c..bdaf7a730f 100644 --- a/src/mainboard/asus/am1i-a/BiosCallOuts.c +++ b/src/mainboard/asus/am1i-a/BiosCallOuts.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index d4300fa0ad..bbe16424f2 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -12,7 +12,6 @@ * */ -#include #include diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c index 4a678954a1..518bc9579c 100644 --- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include "imc.h" diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c index 317b55e125..f2956a12ad 100644 --- a/src/mainboard/bap/ode_e20XX/buildOpts.c +++ b/src/mainboard/bap/ode_e20XX/buildOpts.c @@ -12,7 +12,6 @@ * */ -#include #include #define INSTALL_FT3_SOCKET_SUPPORT TRUE diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c index 84bb9e571b..faf3b95f39 100644 --- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include "imc.h" diff --git a/src/mainboard/biostar/a68n_5200/BiosCallOuts.c b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c index ed03d5d19b..f1560c47e4 100644 --- a/src/mainboard/biostar/a68n_5200/BiosCallOuts.c +++ b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c @@ -4,7 +4,6 @@ #include #include #include -#include #include "imc.h" diff --git a/src/mainboard/biostar/a68n_5200/buildOpts.c b/src/mainboard/biostar/a68n_5200/buildOpts.c index 3fb482baf8..78a5596b93 100644 --- a/src/mainboard/biostar/a68n_5200/buildOpts.c +++ b/src/mainboard/biostar/a68n_5200/buildOpts.c @@ -12,7 +12,6 @@ * */ -#include #include #define INSTALL_FT3_SOCKET_SUPPORT TRUE diff --git a/src/mainboard/elmex/pcm205400/BiosCallOuts.c b/src/mainboard/elmex/pcm205400/BiosCallOuts.c index 38a1296b60..2242c0e988 100644 --- a/src/mainboard/elmex/pcm205400/BiosCallOuts.c +++ b/src/mainboard/elmex/pcm205400/BiosCallOuts.c @@ -5,7 +5,6 @@ #include #include #include -#include static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c index fa0d5b68f9..d39b25baf7 100644 --- a/src/mainboard/elmex/pcm205400/buildOpts.c +++ b/src/mainboard/elmex/pcm205400/buildOpts.c @@ -12,7 +12,6 @@ * */ -#include /* Select the cpu family. */ diff --git a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c index 5bb122a0df..46f4adbd97 100644 --- a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c +++ b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c @@ -4,7 +4,6 @@ #include #include #include -#include #include "imc.h" diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c index 317b55e125..f2956a12ad 100644 --- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c @@ -12,7 +12,6 @@ * */ -#include #include #define INSTALL_FT3_SOCKET_SUPPORT TRUE diff --git a/src/mainboard/hp/abm/BiosCallOuts.c b/src/mainboard/hp/abm/BiosCallOuts.c index c2d09d8c60..7610ec8784 100644 --- a/src/mainboard/hp/abm/BiosCallOuts.c +++ b/src/mainboard/hp/abm/BiosCallOuts.c @@ -4,7 +4,6 @@ #include #include #include -#include const BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index 061b66b049..337d35cf7a 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -16,7 +16,6 @@ * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ */ -#include #include #define INSTALL_FT3_SOCKET_SUPPORT TRUE diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index 17c5a9c595..6e0f1ad969 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -7,7 +7,6 @@ #include #include #include -#include static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index 4e9395756e..cdaecf0efc 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -12,7 +12,6 @@ * */ -#include #include diff --git a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c index c4555c9d7e..b2a96a236f 100644 --- a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c +++ b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c @@ -5,7 +5,6 @@ #include #include #include -#include /* Should AGESA_GNB_PCIE_SLOT_RESET use agesa_NoopSuccess? * diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c index c19f6bc8b0..b273428848 100644 --- a/src/mainboard/lippert/frontrunner-af/buildOpts.c +++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c @@ -12,7 +12,6 @@ * */ -#include diff --git a/src/mainboard/lippert/frontrunner-af/sema.c b/src/mainboard/lippert/frontrunner-af/sema.c index 51fe01fbcb..fb8e6ef877 100644 --- a/src/mainboard/lippert/frontrunner-af/sema.c +++ b/src/mainboard/lippert/frontrunner-af/sema.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/lippert/toucan-af/BiosCallOuts.c b/src/mainboard/lippert/toucan-af/BiosCallOuts.c index 51348bb451..9b8f3de5a7 100644 --- a/src/mainboard/lippert/toucan-af/BiosCallOuts.c +++ b/src/mainboard/lippert/toucan-af/BiosCallOuts.c @@ -5,7 +5,6 @@ #include #include #include -#include /* Should AGESA_GNB_PCIE_SLOT_RESET use agesa_NoopSuccess? * diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c index c19f6bc8b0..b273428848 100644 --- a/src/mainboard/lippert/toucan-af/buildOpts.c +++ b/src/mainboard/lippert/toucan-af/buildOpts.c @@ -12,7 +12,6 @@ * */ -#include diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index 504b736a79..901ee0208f 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 03c5fac7e9..aa965b6cce 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index 10c678a062..79d54aa784 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/qualcomm/sc7180/usb.c b/src/soc/qualcomm/sc7180/usb.c index 1c93e8009b..c4b65d6e4e 100644 --- a/src/soc/qualcomm/sc7180/usb.c +++ b/src/soc/qualcomm/sc7180/usb.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c index 09ec34b79a..3351ad980e 100644 --- a/src/superio/nuvoton/nct5104d/superio.c +++ b/src/superio/nuvoton/nct5104d/superio.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include #include #include From 7d1a4b2584ce61f89f8b4de52880f0a6db96aa94 Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Tue, 5 May 2020 18:23:43 -0700 Subject: [PATCH 060/405] mb/google/volteer/variants/halvor: add two SPD files Adds SPD_LPDDR4X_556b_1R_32Gb_8GbD_QDP_4267.spd.hex, which will be used initially for the "H9HKNNNCRMBVAR-NEH" SKhynix part as DRAM ID #0. Adds SPD_LPDDR4X_556b_1R_64Gb_16GbD_QDP_4267.spd.hex, which will be used initially for the "MT53E1G64D4SQ-046 WT:A" Micron part as DRAM ID #1. BUG=b:155423877 TEST=none Change-Id: I5580f602cd411e415dafcb36bd1ffa43c4f02f60 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/41076 Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- .../volteer/variants/halvor/Makefile.inc | 4 ++- ...LPDDR4X_556b_1R_32Gb_8GbD_QDP_4267.spd.hex | 32 +++++++++++++++++++ ...PDDR4X_556b_1R_64Gb_16GbD_QDP_4267.spd.hex | 32 +++++++++++++++++++ 3 files changed, 67 insertions(+), 1 deletion(-) create mode 100644 src/mainboard/google/volteer/variants/halvor/spd/SPD_LPDDR4X_556b_1R_32Gb_8GbD_QDP_4267.spd.hex create mode 100644 src/mainboard/google/volteer/variants/halvor/spd/SPD_LPDDR4X_556b_1R_64Gb_16GbD_QDP_4267.spd.hex diff --git a/src/mainboard/google/volteer/variants/halvor/Makefile.inc b/src/mainboard/google/volteer/variants/halvor/Makefile.inc index c9a128d72a..b1e4c9a37c 100644 --- a/src/mainboard/google/volteer/variants/halvor/Makefile.inc +++ b/src/mainboard/google/volteer/variants/halvor/Makefile.inc @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only -SPD_SOURCES = +## Memory Options # DRAM ID # Part Num +SPD_SOURCES = SPD_LPDDR4X_556b_1R_32Gb_8GbD_QDP_4267 # b0000 # H9HKNNNCRMBVAR-NEH +SPD_SOURCES += SPD_LPDDR4X_556b_1R_64Gb_16GbD_QDP_4267 # b0001 # MT53E1G64D4SQ-046 WT:A bootblock-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/halvor/spd/SPD_LPDDR4X_556b_1R_32Gb_8GbD_QDP_4267.spd.hex b/src/mainboard/google/volteer/variants/halvor/spd/SPD_LPDDR4X_556b_1R_32Gb_8GbD_QDP_4267.spd.hex new file mode 100644 index 0000000000..921ecf8a36 --- /dev/null +++ b/src/mainboard/google/volteer/variants/halvor/spd/SPD_LPDDR4X_556b_1R_32Gb_8GbD_QDP_4267.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 16 21 B9 08 00 00 00 00 02 01 00 00 +00 00 04 0F 92 54 05 00 87 00 90 A8 90 E0 0B F0 +05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 E5 00 E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/variants/halvor/spd/SPD_LPDDR4X_556b_1R_64Gb_16GbD_QDP_4267.spd.hex b/src/mainboard/google/volteer/variants/halvor/spd/SPD_LPDDR4X_556b_1R_64Gb_16GbD_QDP_4267.spd.hex new file mode 100644 index 0000000000..921ecf8a36 --- /dev/null +++ b/src/mainboard/google/volteer/variants/halvor/spd/SPD_LPDDR4X_556b_1R_64Gb_16GbD_QDP_4267.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 16 21 B9 08 00 00 00 00 02 01 00 00 +00 00 04 0F 92 54 05 00 87 00 90 A8 90 E0 0B F0 +05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 E5 00 E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 From 7adcfde079324b834c9a6370af38e56e34f1c45c Mon Sep 17 00:00:00 2001 From: Jamie Chen Date: Thu, 16 Apr 2020 01:20:29 +0800 Subject: [PATCH 061/405] lib/spd_bin: add get_spd_sn function This patch adds the get_spd_sn function. It's for reading SODIMM serial number. In spd_cache implementation it can use to get serial number before reading whole SPD by smbus. BUG=b:146457985 BRANCH=None TEST=Wrote sample code to get the serial number and ran on puff. It can get the serial number correctly. Change-Id: I406bba7cc56debbd9851d430f069e4fb96ec937c Signed-off-by: Jamie Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/40414 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/include/spd_bin.h | 10 +++++ src/soc/intel/common/block/smbus/smbuslib.c | 48 +++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index d1ee6f775c..11a0084c70 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -21,16 +21,19 @@ #define SPD_DRAM_LPDDR5 0x13 #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 +#define SPD_SN_LEN 4 #define DDR3_ORGANIZATION 7 #define DDR3_BUS_DEV_WIDTH 8 #define DDR4_ORGANIZATION 12 #define DDR4_BUS_DEV_WIDTH 13 #define DDR3_SPD_PART_OFF 128 #define DDR3_SPD_PART_LEN 18 +#define DDR3_SPD_SN_OFF 122 #define LPDDR3_SPD_PART_OFF 128 #define LPDDR3_SPD_PART_LEN 18 #define DDR4_SPD_PART_OFF 329 #define DDR4_SPD_PART_LEN 20 +#define DDR4_SPD_SN_OFF 325 struct spd_block { u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */ @@ -45,6 +48,13 @@ int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index); void dump_spd_info(struct spd_block *blk); void get_spd_smbus(struct spd_block *blk); +/* + * get_spd_sn returns the SODIMM serial number. It only supports DDR3 and DDR4. + * return CB_SUCCESS, sn is the serial number and sn=0xffffffff if the dimm is not present. + * return CB_ERR, if dram_type is not supported or addr is a zero. + */ +enum cb_err get_spd_sn(u8 addr, u32 *sn); + /* expects SPD size to be 128 bytes, reads from "spd.bin" in CBFS and verifies the checksum. Only available if CONFIG_DIMM_SPD_SIZE == 128. */ int read_ddr3_spd_from_cbfs(u8 *buf, int idx); diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c index f7192c85d4..5441b06219 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.c +++ b/src/soc/intel/common/block/smbus/smbuslib.c @@ -79,3 +79,51 @@ void get_spd_smbus(struct spd_block *blk) update_spd_len(blk); } + +/* + * get_spd_sn returns the SODIMM serial number. It only supports DDR3 and DDR4. + * return CB_SUCCESS, sn is the serial number and sn=0xffffffff if the dimm is not present. + * return CB_ERR, if dram_type is not supported or addr is a zero. + */ +enum cb_err get_spd_sn(u8 addr, u32 *sn) +{ + u8 i; + u8 dram_type; + int smbus_ret; + + /* addr is not a zero. */ + if (addr == 0x0) + return CB_ERR; + + /* If dimm is not present, set sn to 0xff. */ + smbus_ret = do_smbus_read_byte(SMBUS_IO_BASE, addr, SPD_DRAM_TYPE); + if (smbus_ret < 0) { + printk(BIOS_INFO, "No memory dimm at address %02X\n", addr); + *sn = 0xffffffff; + return CB_SUCCESS; + } + + dram_type = smbus_ret & 0xff; + + /* Check if module is DDR4, DDR4 spd is 512 byte. */ + if (dram_type == SPD_DRAM_DDR4 && CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) { + /* Switch to page 1 */ + do_smbus_write_byte(SMBUS_IO_BASE, SPD_PAGE_1, 0, 0); + + for (i = 0; i < SPD_SN_LEN; i++) + *((u8 *)sn + i) = do_smbus_read_byte(SMBUS_IO_BASE, addr, + i + DDR4_SPD_SN_OFF); + + /* Restore to page 0 */ + do_smbus_write_byte(SMBUS_IO_BASE, SPD_PAGE_0, 0, 0); + } else if (dram_type == SPD_DRAM_DDR3) { + for (i = 0; i < SPD_SN_LEN; i++) + *((u8 *)sn + i) = do_smbus_read_byte(SMBUS_IO_BASE, addr, + i + DDR3_SPD_SN_OFF); + } else { + printk(BIOS_ERR, "Unsupported dram_type\n"); + return CB_ERR; + } + + return CB_SUCCESS; +} From 92ba06fb3e6a5ba089305b6739b1b4344984ba37 Mon Sep 17 00:00:00 2001 From: Jamie Chen Date: Mon, 27 Apr 2020 15:49:09 +0800 Subject: [PATCH 062/405] lib/spd_cache: add spd_cache common code This patch adds some spd_cache functions. They are for implementing the spd_cache. It's for reducing the SPD fetch time when device uses SODIMMs. The MRC cache also includes SPD data, but there is no public header file available to decode the struct of MRC. So SPD cache is another solution. BUG=b:146457985 BRANCH=None TEST=Build puff successfully and verified below two items. one DIMM save the boot time : 158ms two DIMM save the boot time : 265ms Change-Id: Ia48aa022fabf8949960a50597185c9d821399522 Signed-off-by: Jamie Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/40797 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai Reviewed-by: Edward O'Callaghan --- src/include/spd_cache.h | 23 +++++ src/lib/Makefile.inc | 2 + src/lib/spd_cache.c | 221 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 246 insertions(+) create mode 100644 src/include/spd_cache.h create mode 100644 src/lib/spd_cache.c diff --git a/src/include/spd_cache.h b/src/include/spd_cache.h new file mode 100644 index 0000000000..3270defba8 --- /dev/null +++ b/src/include/spd_cache.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __SPD_CACHE_H +#define __SPD_CACHE_H + +#include + +#define SPD_CACHE_FMAP_NAME "RW_SPD_CACHE" +#define SC_SPD_NUMS (CONFIG_DIMM_MAX) +#define SC_SPD_OFFSET(n) (CONFIG_DIMM_SPD_SIZE * n) +#define SC_CRC_OFFSET (CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE) +#define SC_SPD_TOTAL_LEN (CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE) +#define SC_SPD_LEN (CONFIG_DIMM_SPD_SIZE) +#define SC_CRC_LEN (sizeof(uint16_t)) + +enum cb_err update_spd_cache(struct spd_block *blk); +enum cb_err load_spd_cache(uint8_t **spd_cache, size_t *spd_cache_sz); +bool spd_cache_is_valid(uint8_t *spd_cache, size_t spd_cache_sz); +bool check_if_dimm_changed(u8 *spd_cache, struct spd_block *blk); +enum cb_err spd_fill_from_cache(uint8_t *spd_cache, struct spd_block *blk); + +#endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1fed543f70..b6d318e7a3 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -345,3 +345,5 @@ spd.bin-type := spd endif ramstage-y += uuid.c + +romstage-$(CONFIG_ROMSTAGE_SPD_SMBUS) += spd_cache.c diff --git a/src/lib/spd_cache.c b/src/lib/spd_cache.c new file mode 100644 index 0000000000..71dfaf1024 --- /dev/null +++ b/src/lib/spd_cache.c @@ -0,0 +1,221 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * SPD_CACHE layout + * +==========+ offset 0x00 + * |DIMM 1 SPD| SPD data length is CONFIG_DIMM_SPD_SIZE. + * +----------+ offset CONFIG_DIMM_SPD_SIZE * 1 + * |DIMM 2 SPD| + * +----------+ offset CONFIG_DIMM_SPD_SIZE * 2 + * ... + * +----------+ offset CONFIG_DIMM_SPD_SIZE * (N -1) + * |DIMM N SPD| N = CONFIG_DIMM_MAX + * +----------+ offset CONFIG_DIMM_SPD_SIZE * CONFIG_DIMM_MAX + * | CRC 16 | Use to verify the data correctness. + * +==========+ + * + * The size of the RW_SPD_CACHE needs to be aligned with 4KiB. + */ + +/* + * Use to update SPD cache. + * *blk : the new SPD data will be stash into the cache. + * + * return CB_SUCCESS , update SPD cache successfully. + * return CB_ERR , update SPD cache unsuccessfully and the cache is invalid + */ +enum cb_err update_spd_cache(struct spd_block *blk) +{ + struct region_device rdev; + uint16_t data_crc = 0; + int i, j; + + assert(blk->len <= SC_SPD_LEN); + + if (fmap_locate_area_as_rdev_rw(SPD_CACHE_FMAP_NAME, &rdev)) { + printk(BIOS_ERR, "SPD_CACHE: Cannot access %s region\n", SPD_CACHE_FMAP_NAME); + return CB_ERR; + } + + /* Erase whole area, it's for align with 4KiB which is the size of SPI rom sector. */ + if (rdev_eraseat(&rdev, 0, region_device_sz(&rdev)) < 0) { + printk(BIOS_ERR, "SPD_CACHE: Cannot erase %s region\n", SPD_CACHE_FMAP_NAME); + return CB_ERR; + } + + /* Write SPD data */ + for (i = 0; i < SC_SPD_NUMS; i++) { + if (blk->spd_array[i] == NULL) { + /* If DIMM is not present, we calculate the CRC with 0xff. */ + for (j = 0; j < SC_SPD_LEN; j++) + data_crc = crc16_byte(data_crc, 0xff); + } else { + if (rdev_writeat(&rdev, blk->spd_array[i], SC_SPD_OFFSET(i), blk->len) + < 0) { + printk(BIOS_ERR, "SPD_CACHE: Cannot write SPD data at %d\n", + SC_SPD_OFFSET(i)); + return CB_ERR; + } + + for (j = 0; j < blk->len; j++) + data_crc = crc16_byte(data_crc, blk->spd_array[i][j]); + + /* If the blk->len < SC_SPD_LEN, we calculate the CRC with 0xff. */ + if (blk->len < SC_SPD_LEN) + for (j = 0; j < (SC_SPD_LEN - (blk->len)); j++) + data_crc = crc16_byte(data_crc, 0xff); + } + } + + /* Write the crc16 */ + /* It must be the last step to ensure that the data is written correctly */ + if (rdev_writeat(&rdev, &data_crc, SC_CRC_OFFSET, SC_CRC_LEN) < 0) { + printk(BIOS_ERR, "SPD_CACHE: Cannot write crc at 0x%04x\n", SC_CRC_OFFSET); + return CB_ERR; + } + return CB_SUCCESS; +} + +/* + * Locate the RW_SPD_CACHE area in the fmap and read SPD_CACHE data. + * return CB_SUCCESS ,if the SPD_CACHE data is ready and the pointer return at *spd_cache. + * return CB_ERR ,if it cannot locate RW_SPD_CACHE area in the fmap or data cannot be read. + */ +enum cb_err load_spd_cache(uint8_t **spd_cache, size_t *spd_cache_sz) +{ + struct region_device rdev; + + if (fmap_locate_area_as_rdev(SPD_CACHE_FMAP_NAME, &rdev) < 0) { + printk(BIOS_ERR, "SPD_CACHE: Cannot find %s region\n", SPD_CACHE_FMAP_NAME); + return CB_ERR; + } + + /* Assume boot device is memory mapped. */ + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + *spd_cache = rdev_mmap_full(&rdev); + + if (*spd_cache == NULL) + return CB_ERR; + + *spd_cache_sz = region_device_sz(&rdev); + + /* SPD cache found */ + printk(BIOS_INFO, "SPD_CACHE: cache found, size 0x%zx\n", *spd_cache_sz); + + return CB_SUCCESS; +} + +/* Use to verify the cache data is valid. */ +bool spd_cache_is_valid(uint8_t *spd_cache, size_t spd_cache_sz) +{ + uint16_t data_crc = 0; + int i; + + if (spd_cache_sz < SC_SPD_TOTAL_LEN + SC_CRC_LEN) + return false; + + /* Check the spd_cache crc */ + for (i = 0; i < SC_SPD_TOTAL_LEN; i++) + data_crc = crc16_byte(data_crc, *(spd_cache + i)); + + return *(uint16_t *)(spd_cache + SC_CRC_OFFSET) == data_crc; +} + +/* + * Check if the DIMM is preset in cache. + * return true , DIMM is present. + * return false, DIMM is not present. + */ +static bool get_cached_dimm_present(uint8_t *spd_cache, uint8_t idx) +{ + if (*(uint16_t *)(spd_cache + SC_SPD_OFFSET(idx)) == 0xffff) + return false; + else + return true; +} + +/* + * Use to check if the SODIMM is changed. + * spd_cache : it's a valid SPD cache. + * blk : it must include the smbus addresses of SODIMM. + */ +bool check_if_dimm_changed(u8 *spd_cache, struct spd_block *blk) +{ + int i; + u32 sn; + bool dimm_present_in_cache; + bool dimm_changed = false; + /* Check if the dimm is the same with last system boot. */ + for (i = 0; i < SC_SPD_NUMS && dimm_changed == false; i++) { + /* Return true if any error happened here. */ + if (get_spd_sn(blk->addr_map[i], &sn) == CB_ERR) + return true; + dimm_present_in_cache = get_cached_dimm_present(spd_cache, i); + /* Dimm is not present now. */ + if (sn == 0xffffffff) { + if (dimm_present_in_cache == false) + printk(BIOS_NOTICE, "SPD_CACHE: DIMM%d is not present\n", i); + else { + printk(BIOS_NOTICE, "SPD_CACHE: DIMM%d lost\n", i); + dimm_changed = true; + } + } else { /* Dimm is present now. */ + if (dimm_present_in_cache == true) { + if (memcmp(&sn, spd_cache + SC_SPD_OFFSET(i) + DDR4_SPD_SN_OFF, + SPD_SN_LEN) == 0) + printk(BIOS_NOTICE, "SPD_CACHE: DIMM%d is the same\n", + i); + else { + printk(BIOS_NOTICE, "SPD_CACHE: DIMM%d is new one\n", + i); + dimm_changed = true; + } + } else { + printk(BIOS_NOTICE, "SPD_CACHE: DIMM%d is new one\n", i); + dimm_changed = true; + } + } + } + return dimm_changed; +} + +/* Use to fill the struct spd_block with cache data.*/ +enum cb_err spd_fill_from_cache(uint8_t *spd_cache, struct spd_block *blk) +{ + int i; + u8 dram_type; + + /* Find the first present SPD */ + for (i = 0; i < SC_SPD_NUMS; i++) + if (get_cached_dimm_present(spd_cache, i) == true) + break; + + if (i == SC_SPD_NUMS) { + printk(BIOS_ERR, "SPD_CACHE: No DIMM is present.\n"); + return CB_ERR; + } + + dram_type = *(spd_cache + SC_SPD_OFFSET(i) + SPD_DRAM_TYPE); + + if (dram_type == SPD_DRAM_DDR4) + blk->len = SPD_PAGE_LEN_DDR4; + else + blk->len = SPD_PAGE_LEN; + + for (i = 0; i < SC_SPD_NUMS; i++) + if (get_cached_dimm_present(spd_cache, i) == true) + blk->spd_array[i] = spd_cache + SC_SPD_OFFSET(i); + else + blk->spd_array[i] = NULL; + + return CB_SUCCESS; +} From 741099239194b01ef153a7b41a9d8389b0b06f8e Mon Sep 17 00:00:00 2001 From: Jamie Chen Date: Thu, 16 Apr 2020 01:42:51 +0800 Subject: [PATCH 063/405] mb/google/puff: add a region to cache SPD data This patch adds a SPI rom region RW_SPD_CACHE on Puff and it can be used on spd_cache to reduce reading SPD data from SODIMM by smbus. It's for saving the boot time and it can be used to trigger MRC retraining when memory DIMM is changed. BUG=b:146457985 BRANCH=None TEST=Build puff successfully and verified below two items. 1. To change memory DIMM can trigger retraining. 2. one DIMM save the boot time : 158ms two DIMM save the boot time : 265ms Change-Id: I8d07fddf113a767d62394cb31e33b56f22f74351 Signed-off-by: Jamie Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/40415 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- src/mainboard/google/hatch/Kconfig | 9 ++++ .../google/hatch/chromeos-16MiB-spd.fmd | 44 +++++++++++++++++ src/mainboard/google/hatch/chromeos-spd.fmd | 48 +++++++++++++++++++ .../google/hatch/romstage_spd_smbus.c | 32 ++++++++++++- 4 files changed, 131 insertions(+), 2 deletions(-) create mode 100644 src/mainboard/google/hatch/chromeos-16MiB-spd.fmd create mode 100644 src/mainboard/google/hatch/chromeos-spd.fmd diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 6168e13140..8404eaa3f7 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -79,10 +79,19 @@ config DRIVER_TPM_SPI_BUS config UART_FOR_CONSOLE default 0 +if ROMSTAGE_SPD_CBFS config FMDFILE string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if BOARD_ROMSIZE_KB_32768 +endif + +if ROMSTAGE_SPD_SMBUS +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB-spd.fmd" if BOARD_ROMSIZE_KB_16384 + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-spd.fmd" if BOARD_ROMSIZE_KB_32768 +endif config MAINBOARD_DIR string diff --git a/src/mainboard/google/hatch/chromeos-16MiB-spd.fmd b/src/mainboard/google/hatch/chromeos-16MiB-spd.fmd new file mode 100644 index 0000000000..9f0981940d --- /dev/null +++ b/src/mainboard/google/hatch/chromeos-16MiB-spd.fmd @@ -0,0 +1,44 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL@0x0 0x400000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x3ff000 + } + SI_BIOS@0x400000 0xc00000 { + RW_SECTION_A@0x0 0x368000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x357fc0 + RW_FWID_A@0x367fc0 0x40 + } + RW_SECTION_B@0x368000 0x368000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x357fc0 + RW_FWID_B@0x367fc0 0x40 + } + RW_MISC@0x6D0000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x28000 0x2000 + RW_NVRAM(PRESERVE)@0x2a000 0x5000 + RW_SPD_CACHE(PRESERVE)@0x2f000 0x1000 + } + # RW_LEGACY needs to be minimum of 1MB + RW_LEGACY(CBFS)@0x700000 0x100000 + WP_RO@0x800000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } + } +} diff --git a/src/mainboard/google/hatch/chromeos-spd.fmd b/src/mainboard/google/hatch/chromeos-spd.fmd new file mode 100644 index 0000000000..37bc1bd832 --- /dev/null +++ b/src/mainboard/google/hatch/chromeos-spd.fmd @@ -0,0 +1,48 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x400000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x3ff000 + } + SI_BIOS@0x400000 0x1c00000 { + # Place RW_LEGACY at the start of BIOS region such that the rest + # of BIOS regions start at 16MiB boundary. Since this is a 32MiB + # SPI flash only the top 16MiB actually gets memory mapped. + RW_LEGACY(CBFS)@0x0 0x1000000 + RW_SECTION_A@0x1000000 0x3e0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x3cffc0 + RW_FWID_A@0x3dffc0 0x40 + } + RW_SECTION_B@0x13e0000 0x3e0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x3cffc0 + RW_FWID_B@0x3dffc0 0x40 + } + RW_MISC@0x17c0000 0x40000 { + UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x20000 + } + RW_ELOG(PRESERVE)@0x30000 0x4000 + RW_SHARED@0x34000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x38000 0x2000 + RW_NVRAM(PRESERVE)@0x3a000 0x5000 + RW_SPD_CACHE(PRESERVE)@0x3f000 0x1000 + } + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO@0x1800000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } + } +} diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c index 300cac009d..d21e86792d 100644 --- a/src/mainboard/google/hatch/romstage_spd_smbus.c +++ b/src/mainboard/google/hatch/romstage_spd_smbus.c @@ -4,6 +4,7 @@ #include #include #include +#include void mainboard_memory_init_params(FSPM_UPD *memupd) { @@ -15,8 +16,35 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) .addr_map = { 0x50, 0x52, }, }; - /* Access memory info through SMBUS. */ - get_spd_smbus(&blk); + uint8_t *spd_cache; + size_t spd_cache_sz; + bool need_update_cache = false; + bool dimm_changed = true; + + /* load spd cache from RW_SPD_CACHE */ + if (load_spd_cache(&spd_cache, &spd_cache_sz) == CB_SUCCESS) { + if (!spd_cache_is_valid(spd_cache, spd_cache_sz)) { + printk(BIOS_WARNING, "Invalid SPD cache\n"); + } else { + dimm_changed = check_if_dimm_changed(spd_cache, &blk); + if (dimm_changed && memupd->FspmArchUpd.NvsBufferPtr != NULL) { + /* Set mrc_cache as invalid */ + printk(BIOS_INFO, "Set mrc_cache as invalid\n"); + memupd->FspmArchUpd.NvsBufferPtr = NULL; + } + } + need_update_cache = true; + } + + if (!dimm_changed) { + spd_fill_from_cache(spd_cache, &blk); + } else { + /* Access memory info through SMBUS. */ + get_spd_smbus(&blk); + + if (need_update_cache && update_spd_cache(&blk) == CB_ERR) + printk(BIOS_WARNING, "update SPD cache failed\n"); + } if (blk.spd_array[0] == NULL) { memcfg.spd[0].read_type = NOT_EXISTING; From 6b95507ec5b087658178a325bdc68570bc48bb20 Mon Sep 17 00:00:00 2001 From: Bill XIE Date: Fri, 8 May 2020 16:40:48 +0800 Subject: [PATCH 064/405] mainboard/lenovo/x230: Add ThinkPad x230s as a variant The code is based on autoport and that for X230. Major differences are: - Only one DDR3 slot - HM77 PCH - M.2 socket instead of mini pci-e - no docking - no tpm Tested: - CPU i5-3337U - Slotted DIMM 8GiB - Camera - pci-e and usb2 on M.2 slot with A key for wlan - sata and usb2 (no superspeed components) on M.2 slot with B key for wwan - On board SDHCI connected to pci-e - USB3 ports - libgfxinit-based graphic init - NVRAM options for North and South bridges - Sound - Thinkpad EC - S3 - Linux 4.9 within Debian GNU/Linux stable, loaded from Seabios. Untested: - Touch screen, which is said to work under ubuntu but not debian. Change-Id: Ie537645d5ffaee799e79af2f821f80c3ebd2dfec Signed-off-by: Bill XIE Reviewed-on: https://review.coreboot.org/c/coreboot/+/41168 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi --- 3rdparty/libgfxinit | 2 +- Documentation/mainboard/index.md | 1 + .../mainboard/lenovo/Ivy_Bridge_series.md | 2 +- Documentation/mainboard/lenovo/x230s.md | 15 ++ .../mainboard/lenovo/x230s_bc_removed.jpg | Bin 0 -> 42564 bytes src/mainboard/lenovo/x230/Kconfig | 23 +- src/mainboard/lenovo/x230/Kconfig.name | 3 + src/mainboard/lenovo/x230/Makefile.inc | 12 +- src/mainboard/lenovo/x230/board_info.txt | 1 + src/mainboard/lenovo/x230/devicetree.cb | 8 +- src/mainboard/lenovo/x230/hda_verb.c | 83 +------ .../lenovo/x230/variants/x230/board_info.txt | 7 + .../lenovo/x230/{ => variants/x230}/data.vbt | Bin .../x230/{ => variants/x230}/early_init.c | 0 .../{ => variants/x230}/gma-mainboard.ads | 0 .../lenovo/x230/{ => variants/x230}/gpio.c | 0 .../lenovo/x230/variants/x230/hda_verb.c | 82 +++++++ .../lenovo/x230/variants/x230/overridetree.cb | 15 ++ .../lenovo/x230/variants/x230s/board_info.txt | 7 + .../lenovo/x230/variants/x230s/data.vbt | Bin 0 -> 4280 bytes .../lenovo/x230/variants/x230s/early_init.c | 49 ++++ .../x230/variants/x230s/gma-mainboard.ads | 22 ++ .../lenovo/x230/variants/x230s/gpio.c | 212 ++++++++++++++++++ .../lenovo/x230/variants/x230s/hda_verb.c | 33 +++ .../x230/variants/x230s/overridetree.cb | 36 +++ 25 files changed, 512 insertions(+), 101 deletions(-) create mode 100644 Documentation/mainboard/lenovo/x230s.md create mode 100644 Documentation/mainboard/lenovo/x230s_bc_removed.jpg create mode 100644 src/mainboard/lenovo/x230/variants/x230/board_info.txt rename src/mainboard/lenovo/x230/{ => variants/x230}/data.vbt (100%) rename src/mainboard/lenovo/x230/{ => variants/x230}/early_init.c (100%) rename src/mainboard/lenovo/x230/{ => variants/x230}/gma-mainboard.ads (100%) rename src/mainboard/lenovo/x230/{ => variants/x230}/gpio.c (100%) create mode 100644 src/mainboard/lenovo/x230/variants/x230/hda_verb.c create mode 100644 src/mainboard/lenovo/x230/variants/x230/overridetree.cb create mode 100644 src/mainboard/lenovo/x230/variants/x230s/board_info.txt create mode 100644 src/mainboard/lenovo/x230/variants/x230s/data.vbt create mode 100644 src/mainboard/lenovo/x230/variants/x230s/early_init.c create mode 100644 src/mainboard/lenovo/x230/variants/x230s/gma-mainboard.ads create mode 100644 src/mainboard/lenovo/x230/variants/x230s/gpio.c create mode 100644 src/mainboard/lenovo/x230/variants/x230s/hda_verb.c create mode 100644 src/mainboard/lenovo/x230/variants/x230s/overridetree.cb diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index 2e87c0d40a..cdbfce2757 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit 2e87c0d40a387c5b1f1afd3ce61ecdc7dad0e3e8 +Subproject commit cdbfce275777f2fd142e3a3c73469807a4c40207 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index e80ff0b512..33c60a4c97 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -98,6 +98,7 @@ The boards in this section are not real mainboards, but emulators. - [W530](lenovo/w530.md) - [T430 / T530 / X230 / W530 common](lenovo/Ivy_Bridge_series.md) - [T431s](lenovo/t431s.md) +- [X230s](lenovo/x230s.md) - [Internal flashing](lenovo/ivb_internal_flashing.md) ### Haswell series diff --git a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md index f4f0efff6c..5f151663c4 100644 --- a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md +++ b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md @@ -1,6 +1,6 @@ # Lenovo Ivy Bridge series -This information is valid for all supported models, except T430s and T431s. +This information is valid for all supported models, except T430s, [T431s](t431s.md) and [X230s](x230s.md). ## Flashing coreboot ```eval_rst diff --git a/Documentation/mainboard/lenovo/x230s.md b/Documentation/mainboard/lenovo/x230s.md new file mode 100644 index 0000000000..e42d75e974 --- /dev/null +++ b/Documentation/mainboard/lenovo/x230s.md @@ -0,0 +1,15 @@ +# Lenovo X230s + +## Disassembly Instructions + +You must remove the following parts to access the SPI flash chip: + +![x230s_bc_removed](x230s_bc_removed.jpg) + +* Base cover + +Its [Hardware Maintenance Manual](https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/x230s_hmm_en_0c10860_01.pdf) could be used as a guidance of disassembly. + +The SPI flash chip (W25Q128.V in thr form of SOIC-8 for mine) is located at the circled place. Unlike [most Ivy Bridge ThinkPads](Ivy_Bridge_series.md), X230s has a single 16MiB SPI flash chip. + +The general [flashing tutorial](../../flash_tutorial/index.md) has more details. diff --git a/Documentation/mainboard/lenovo/x230s_bc_removed.jpg b/Documentation/mainboard/lenovo/x230s_bc_removed.jpg new file mode 100644 index 0000000000000000000000000000000000000000..1735e8100b82acbaeb56a8b4428b106408bd4b47 GIT binary patch literal 42564 zcmbrlWmKIp*EV<#dT@7#;_hA?io3hR!Ci|L*Wz+;clQD<-s0}=QrwCU&nq+E{F)z= z>^sTIT3N};j$Hf7zTcPLR{;_L1f>6e;k^%l0Rs90|3L#N0YD4@6b9gZ06+`?0AYbZ zAmINFP|z^2KsW$A=zRqM`tSO?VARu|?a%7*Rpr%#Fq+OqTpQ(IHH5f5OQz=UoZ~d7 z9_XY8E~@QFp6+lc!ZNm_NSvOd7yM}K#Hj2++Bq*?X-H=Lu~UUTD=7HmN0W9k zOD%SXIOz^{(ii(V2F7!AMVc)-Hl;&IR>h{k(P956jz?-Hiwz^#3(@?mr}U)fkG=;=tp@2X@JSzZ{rEiSNys1(Mj6B7)S zNE6A+J|cM(#!hR+ns(0mN(|?C_qRYDJ6TbfO5qn(Dw6nSWd_*k-;+DpgljDe{;XXzK5%f}RcaPf{vB?^J3N&J=EK z@2{D2=MOUbYqS=s51Q|GgE(qhrkPZo6tnLpgo3jat5=f`VN_WPLz?AN+u1TR@%L6F zHMl%&MdTnR2b9p7WvQ1Xd+~TAC&&Z5m7PjJZj!w za~m;z$ms7HrYzjv?1LV@*lZJ4&=bk)+qpL^8ZLX_+(mhL85=$rb2{d(fPwK4XznAO zmV)j;?(CaTaHp442Dm_uO_m$h!*MkFZ&h?{bSzru=#Qvm)0N|mePV!^P})xMXvEl*?RifWqXZ7oSj z$Ar>WV?0sO$;}m=;PtwxB5!Z#8tDWrGd1dQk`^PwZD*;xM};^G!web4wBA9J&7IWd z^akRXwJC%x0RzqJ78A4yDYc&J(h)J9TJjl9`w{8?mxE_V<040<+nb(8mOg_3Pl;e| z06Ek>VcN(WWzT<KLMXGZg#=8+to;q3s_3XPfiWd zVVkY-T$#U=AvWiU_EWQQBn`2~m*=z@nJoW_x@z)i;vrH`JPDdmV&2cw$0@(W7`APt z+|j8ne62l)4uJ!(L6`CgY7}<^u zVb8dTK=TN;e*w7r7I|K1<)bk9@rkhy^o}OTaFd#gA zT3khkr_#0S54`)v7dMv*RWiu0Px|iw$s0btF7mmN?}O#H4wdr5FPEqG5DmS3^N4AK zcmV-bzAV|#nVIeDX0pfU!mVD;&y1*N1J(HSvA1N_H?fC4uXm|ND@r&o!nMTaNX2_;W;^yKr>t)4I;0O-;N0UR7PDuDBV0jM zti*2kq;6vs;e5Iv>n5?!T5h zf)1Li__&c7|34vIRpJPEtb1A00{7)7vS_?gS*|YVwZeG^^T~Vq>lj#X(@mCxELApp z29u+YoJ9vD@UN=M$B>JE_&wCzkpJ%Z0 zU9SciS9^B%FXtZ}$HZQaT9%pT*nE%D8bd?Fy^UWdv^`QYuKl*ghW7Q@^aFRt!c+*+ zx7Hp0hb3s*l2jy}CNotyay<`m)|xA}-$IWhCJ)aXX#WTtol+E5?IjxsptBygZ20H& zObtFRRz=cRA*&gL( z9>ZUn zjn>kCeAlHeuZ!#4s|H$qX0Tlhf}z)81>?;1W8I@|_ttN0r7_C;KicA68vZ6-Aw6vt zz8sVNnThdb`qSuez&x;?kEZ=Ky=`SuaD|DDsY*;y_LMGl8AHgoTv4t)bY}S88uuzg zYxGDtdkKNiiPitHmID@^o{XsN#IlGdDeJ6oT}uuhKap-TbTq|Y%8F-rA9fFjqC6!c zz;@1nNX-vbTgdVRYx53(irEm}{EH2&-0A$$q@b=+V<8iNQS@0Y+kU}I?95o0z43$) z*rJLfnQ~zRXC%~Xax3COAy=11Sj&xBY$LD|V)=C{P>4Uvh{133v#)H6M~EbGN!&~y zgRBM?Lgl1gPARl(X_ACNlIiemzb3ZePKoJfCl`(MazEoSwM6M3as@!Obfq=Q%rTyE zFD^v&$QmK1wYD;Aiby9!UhnMCJ$|H0iA5P5J6%D#_81n|EZgVuOq0bGlgWRU4FKkd;U+&gSe|&=Zg}FQL zetfHU{j&bm!oNYCrx&F~oEDaZ=oPL9J~2?gEi5-X)9wo(v9XL?-*4VXDHk#e868e= z28Q6{m$p4Hm6#`pL=f5lfWg^w#*LkIkbKCcYcvcOdp)H=E0jf2Ev7ikl1iP_|EHRu z{-dVeAY^<%FAAFtRuBM=%>+PhlF?S7TuaMOnD(6lz{M@7nW?wXx+CUFZ-QzqSKR}JRKTDtfJrtR`-Mz<4>-utv?AZeGaQcO zwp)a^_cnodX6G+@CNvZa8`fib=)8`P7+i?q}L#IXXf7 z52cAe1uN2+c@HMFIjR&^VSwsKKFzDe2_N&$_czU5lzprq{ zpL^^LHypEOP0n^~mgVY8C`d?5Oz&&>VhwZF<-ek0e@v_mW>>4!@6YRAp@7~`a3R`< z_>jJB?$=%!sZ&OxZfUc`aXzU9(eB8G4!WGkcY`B521BfBv*ggroU}VUnl#Cf8>Y zo^ga2SA*OGo;o%1WrEB{Y9Cv`~k!H(iUX7#w0+VwjiV`Ahs`5Xp@hL_&r;3{aT=d-L!-JtqF?W&qD77Nu|k=% z6ixOUhN>euKD|XbZXx4%G7s`Hr^QDWyAmayRJsptre6|f?r7uL=h8RQRP{rqp;6yj zPN%%hA;PlCx#=+~9x0xvUavvAl4DV;vD%xjD&wvj;H9n@NP>9>w0wSfzU)>VZ_kRf zm%;VmNXJUkJx55tvX1?CvU+5)nEyMnCx5n|So|gnEa%XDfW0*|8QC~v)5T}Uz62MK z!6$h~%<$wrJH)19xi<&TQNoUZN+rEoY&B2NBxkP<;W`*m3{8;IWs8$XG*w4TCj4GC zUWTC>x}Y=CC8*Ii&*!={Nl+GV{SmDOmQs#Z@}n8Kwa{+Y%jR1Wb)`z=;%jNMX5!4o zM%_WL5jtLkl)2Cj?U&Whi4sId_uKw&f} z7$KaNkZ4MrRKj5Z&!Vm*tRgGJW^1o}IQp~+D=eaS%ub5mxA}6Nl(ilFFvC$6)W3s? zQVygu5VMu~!RVJr9^8ATxq&ILVK;|2uTtZkm8Plh6rSm332c$A6<|-PWGBt&Uj-tAWg1TG~yOb)R|0wEJKU?GTXVQJI-f0 zJ@fcGl!PrU5YgmEgnLV_oGne`>_RJ4k?{FSV>Fl6gauL|(xrIKmwodAxUyQk2t;-M zr8j!Nu8`M8H>})$qP_#%2~_*(8J^lCdDz1e`crz+jzl_rFS9FUR7XB=`#14YbKD^< zz8F@-xsjc08Bj~uAP(2b&L%3=@k{c$O&hStuQPtzv1sc*t-5kG_8DuxATMHQa2u@? zWDJ;xr6pi_JdbOF=O?%WcXGVOEHjP={5~6euAX`aba+1a3%~SGJ(uMf;Uy36GknK3 zSU70DyZs$UW8uoApADbC&#R^7VOjrA$9GoiP$6RBaMyWbr`X>kYus|IBc0=hKBem& z@WuVm$H#@^V@vN3w5Owc*|ZDwmNK*3xF7syNWA%}mB?pImXj3M#GzbT2Z+$}|85Tx zlyYusUuo+C%97?faG%F8RVyX6}%QF6W%)>FSZ%Lo>OF+ke0pZ>6?f^L7JT|IR}5~= zs5^$q!y+!}J&LmP|D4l(uVVTHNgMoUI$`$Ib#BNi>`ZHO9LGfL#k&a68S;24bXp zDuL7VSsTKFkr7-<_bfo0t~+}<{W}h(L#q!puf(!i9WtJ#2+VE7nk4Ov-d1kPcpYjy zvX+6B#ts0?RUX~ia2GY=9H_^B?iif;wQ6u4!+ZJ}l_n}z3jaluoJ)A1fo2aiLLF*V z*49Q+xb$Xrs}qQIqIvQQL3tIyxJ$9*vo;PIc#XR`-JIRFwaVm<&eWV4Cj>z;=elw4 zFVNCHLqR0OuW;USDwo1j7ADEj*GPreBUW+CHXyxuqoh>4o8YH3w-n9JZ9+$wke_JV zCl-|Xi0UG7$P7#y;$}seCXMlgIvosd*xA$;MQpcRz&OCVzw_>*+V^^2hUQSXk#|~b;mEXJ7uT&+Ukwzz-S{ z@gQ^nbp2xG($BbKai=Y}GSuWtPF*LAQ-~o{7&Vy#mv%d`Vl7zYw!IMGYwDRv68@ro zI-NW)K3jI z;56AY`>K08=mQRb@?4dwJU(+I?-p*lEM-lES97xc58lf9g}h+AUH8k54Kq4V?6<@K z1PU*jHlwPY;f291riv-h<%kycFI$ckr4c8x9&bkpS!F%<#ayPgR*Bzjk!tyVocN)x z8`@rT$yZU2bDEDURcX0Q3a_gn3>o{Jl^gT=mH$`X1TK5h2-|kpH}`-s(aOrs0rDDu z-$qX4g&YpDj>(T6;BUtkOA2sNtRA?E?zFcojodrw9GxMGEf86rB!O}si1poIcOa@3 zGWltYf}Y(x43x2!j%e4Ashe#hPmF>|Q2F7{aatr*mxhr0R6G{;w-hZa)dQQr}kv-){^0(?~45H#Bp08#wCs}nv*SB?E*xW zF&JhtLm6-nzr>-w;keGAk_0W{w3JeQ?PgtN$K_pBN3^5QACR6+u35^A!Kcp*)#AgZ zt^4cLue!Ei$H5up8U`}N`LNipQZdA%OYaZ_eD{^m(Ik#VCZGWMeb|su^1~bs^&TFsVy; zXQfC)ifJLqPY!Lh^9KXifpJOJaXg^?=Dt}o?;Y>tfmC&ehE&`k71v4!*(Uix&X`x4 z_7xaq^#ZD0xu_~X&FyjO5y4t@>P&>Bu?0#4!%9FaC-(=IHD%;_kf?4JhZ+m*YL8N3 zG*Wl`^Mk=l!yG--WO&3c+rP5uPq{m{{yA=Dl;3EM<+nK8!!JD{>QLLIwm$920&W6s zF68AQh!wW~h0Xg_t#%X#1yJ@S%ykFl(s5p?MQpQqXCW~RyQ*nx9ggnp>6kmVeBhL+ z&zh&R?u`it1k$F6|_p0UFFJBzAPO>eg`b5LR+3QmkT$wB0(Wv2OsVg z6U!m&&E`tcEhQU^oZ4A=r4gant&hlYE)4>kLR((@zpRr}44z2&N zb^eo^u$I(~)}h$(3#qEhf^-#(7;aKou-BxQDa882_u02QF!}t51aO2!ne2HO#k;TufkRX+JUFf(73DN`}(x89SspID>x?-i^}xnXgRmJkkQS7`IU1tQ&~Q>E)^ zX2lqS7s27EZV`Cq_}L9|kIeZ86e`>iAgDxdC_5zT-~4KsYAIiLY$u3eYu|RABFck8 zTCqjBw4UvFk{mv*$TlfCFs;ZoH`!XvjJH7S*pOWL^6s}we9dvTzb>n*b)5y$iB>;yEUXE%-{$0|87eeB>BuvI#j@g4sKTsW|(KbDMvB8@z!YA4DaHZXlw z6`q2fH&{^jCn)WB!gvPcPFsV6eMFA8z!4#%W{tQ$AV*v&cj7{WYG$>limLu&wiA~e zODMxTj)@u(`%-O9io3L*5X7K?XiF_HuUNUt16_{WUHflWu(avJEHx}y`4BJpW`is< zsn|m^nR<706c`8Dqd@$*;Zms0qGw1Ql8R8tS<#uBfm`cOYBZbWro;FkZ}}pu4%pYo$heA;Vj&gk;ZNc$gkGh% z+=@bbxQhE&(N!9AiH5BKirWeiaLr&BK$2CfD}4|M2LL~+=h=32nmNoh2&1+CLf}D@ z{SKuW4VmPrw*I}IpAzr>J2e0j;E46QY|LEQw*9N4JYbnpW4l4yyHYnK+Mlni7;M@M zzKz2hQY+_@0cVR)Y>o!Vu7YeY2i%I7Wze{%?zNme?} zvbVwB=e@G@ul)nq2&;5+zcS(=8aBnyJ`xY zWjH;X?7X#2czvRmYk1dNckh?7=L(+VziA;)qQ$jX!^YxtacIjq!A-ush>6(DEyF() zY=>ZNmo87LU)K~r-RjXlpQ*-Ytk9YH*)FzU`1Y-6t}&-diaCs=syo-n>ZJ--+TwiP zDN-*{@k7)qgN&>Rg!$%RmXeyZB1 z4NW(!V5_mMz{mRH9&v#3#`_j#T&CtbqBUlCk(f0SV>K{tS>)c(t zB3CQEFRXk5%t`Y{Lp#@_Q5=`_<|Zn2KQ3L5_$Q1JZS)RA%)OGon%#sFm$ofl8ei2B zNisxz@Iwy#hqJl9%0kMI2#1i#N4Q)MS?%ZwO=l;g5_gWQ*}lWjC&rn@xmuoZ=U?bf znr!m^@%V4VVI|0j+3i2R*0=FA8=2WK5WNHH**S4Dnm?GZ)$z8E&9dUq{A-K` ziy(GDo~cp(Q=@X*=e1|IMg#d@p=;yqwySB(r}3@X930as>w={X;KpaYs@Cx94~uog z`h)L?a$%uSr%%jOIIyzhqMXeWL{t1Kc(|5xJ;|&_XCH2CrI&(344}~dl=*GE^}l;t zv2C`(f@b6VFR^XmsToBG?Q51@BH_p{h#DLx7WZ>P81JHF zm4T}1YnPt9vWhch$yUs%FlO4a;>c$jM{fX0hR6L|iHW6a!1&$qE4NrmIWuuj_C~ZR zkz*gW&Wmb^**vn=_Pm>~D156823>;EX0(OZ7fhhs7;fBx+#_EhvwolA>Y#cyNF22~ zJEU=$y*dl=R&v8O5;I6V0MHCLYfQ%+LM_Ubxzz-u@l8{_b&pLq_zH2Vle1pu=qNHKJ?9d zbY^2GFbt6;x`gZj_BLg0Mxm?A_B19MC-3Yjai#{GOo9 zLVuPCBCKe?2uC}e^EIvd`^`mH?V`EGcMPJ=oihWeKIca@*z*5=sibmtP)#GP3IY&P=%Gx@ zp}@E(;62g?G1-TZUyD<6a8qof2iG-dDA6=V^9jHv37DAi9hCpdVUz0U=%JAqkgMLN zq*EIIQG-cL0>W3&Dv(Mvm=l=Z$1&mDg1~8C5l*VvTN)?XlP}FGNlyCx;oP`ZdI3bnc2-RAl~TJV*v_5{mX=SI&<9kZ zF9ZO@9sw6h;L>GMBc;WoW-{oAzK5l!xJhBdxJ^vt4A66 zwk;IhRHnoZ>fj6A+uL(%Cg=LYT~Wj`Pc$(%>m&BM)AVDI%{dxutH7J@=Pa7L_MM8f zrkv*;@M-AbZSI!{m+$w{z2M(bj_y?GXphO)5;Xxu36z?NB`W0T-+#8*6d~MaO?UH$ z_V0jrC?l0?u$W2hXbAtf38u9L%pG&77hnNQ%#}j(46LsdQXQ9M~!2x(BFpLnu^&D@NpWaBLg- z)6j&zBV6{sE1k~pRV;j1`U{-?k(j%-=;Gs?IKmGUZ=b}Kwy(~WREKfj7!}Zojt;Cm zamS}tE+i*vY_6~us}^fEy^!sk^!?d0DwTZ_Z&BB~L*y@ba)ffZ{gIY~*vq2lCl>~~ zuOPtE#9t7Q9_6ph=B*NmmhUdi3Pe_6|eRl*R0e_WyAMVdV*AKC0crkBDRw9%5)@L1>y zTP?(G4SrR2>9*uvzkh~hdk3ihRq*or!@YZhW@&AFUw*$8rS!X{C=%hRX}})D8;T{4 zAEjl%QIx%N)Z3LF&c(CgIIYs6YFl?S$0kHbJC;n&0l}d8(_gNditjnoQb;IcfDx&u z;T|I>&W}gjE`C9c)HCObW=Z^QS<-VWvKxam01U6-TL=%va5T2XSiPZ2b$Zr5e^zLJTS!&(!v9D%O{tL# z%&3uo2QEM=A9zYny4TCmMqc9;Q4h1u%S&;uU2YVGWWMXQ+oA}Yj@}8hp^SDbPD8uy z_(GScm9zG?S6&L_GVA_Kk-Nix9Q%!^<KEUFMViZa5)^;T zQA`j`+YnNEfoPF`VD(}&%u`tKlb-zW^ zNF?cKt^h%bR*H{?_+D5vvk{1+zjefYR}d1KEf^QFl%^G3Y258{6h_3mS`y%9Sbo;D z4j`;IotS_Hsj~>ERCaD#)R(BQs8#_Pr+8`ku=s&Y<%iHkz@0p5Iwa~&M64+us^e*E z7|UTRQkpqGS*S0KwSi&!Q!|dB-1tfw^gCv`xpT#F^iYwISPikNNhq;tYPop#12mIt zk_nlXKV<=bp}_V^QFWlI13}(vEi7az#ridYC-&ddgG0GG3%t8R5y2;1mAicUqX7HI zpmpvZo&^Y{zR;(5?6E$W31>y}(f#Y~2I&fE|Gj*s!dg4tW_!(4Z7tkGkh3ZVx4C47 zl+UylCbpB<@J;_qyH0`z{NJgnjVubpDc+3j8{D=U{S`X+p-*mgT;Grw8_2Lj1-5KzF*LMz)F(1r z^QIqz2+UC#==WeAjB={CEQPU?RJsZ6Ya{fkFcA}=L;Ag$Ftq+poF}so zG))q-?FAzRHDBbV)YI5@$1;nrMtC->nPQSV7P8^@kB-FBQ=weom!v?2q*8dRqfl!> z#wsCivXjtftLD9HRsB?qq&M@S*l78|3H`3Q*jN3)5UyDV?2KcMY#$nFN=YSxp{xhJ zxEqq~gW$~+ANOVx{w&yiJ6(S-DLeg(XGQ~frn4A57S{z{mVtx)Q_!+xp^A_xaSozZ zY%^mgl>{_9)ghgjT9*NAR-QHiO4Exu9=!pKdwGVc}ydDK%ZJ+t;I6nt>!a?D&;tI98x1 zB|a|NTxN!Hh3y}A1g$8%K;{&dgko6Zk&b6&XF3?YwqKGyju=PZ0g6EGU;JAbK0w&O zr=m{cc*>rF@5=zj4ajCa0?Sy5SiL1DFBW;PIgwAhUDCobES7L|M7neUm`!VVZ{^&QOR$Tytt40;9P z6xG35%K%wtd4ShPN1zx}v+oWxiQY+dD2P2JTG44ayU=X2EVy-%w?9d-ZONS&h(UtM z;~O@e+bwu|lFOjN#X$O17&Jb)cRqsb`X&t}`{_g##Ti+K|)IA-%b=IRbrrSgon>i5`V{|PITOOByc=f=al2+2)hY!by`l--AG_Z#R0;?C*h9?= z0&*^NbMFUqFYKjyu9+W_e|pZHoN*U&lv8%z*9?O_mAT#lUgP-F+~B$@6caC;vI-*f zrs6FM1N9<4Dgxg7P*o`$lGVOg<~CSAzyooBgw|A;~<{QN&|F8PA*-f=6YgYN{?PERY>aDM0r0htgFrps|U{hgX zSWQLzaALqR?VmvOWooBs>%`JscO0V_g7>w-UJCkMrT$%rLF+N~28%@sK(Wn{grTUQ z*HTrwH1(~JA$&f^E6bFfyKO~*_rE@{>F*59SaQ7XcOoTyI`9x2i>9@*h~sURY$|9ewG2(BJwf~Wa&pnBTXIY4@`;j4gkZw z1KQA?o>h2X%Sj(rg1h_}cwa03M;_@m_rt(F&G6;tdV*?E=Lxo0>!dR@(p+Evl)zi) zJ_;9q*=`V|Sc=N5I#+G?(-G(QE(f(a65~+M6jp;ITu~Cs?G^D*=+HFv5TUk$+R0f! zNFo2P0y7DQBvbUili>VY*a%O;HbFMH1f-+z7@Iq0^*7z#ts%}#p|pxyGA!NdS_4yA zz4R4Mlb53r82o8H)baYXw4oPCxsOS7W$@KgukiFR4ky!`QxGk+9xQE--O!jRL_Wg6 z$5)a__0~#Yf>8lTv*9dQupCcMl{+3?A@#um%w=24)zk|~6hz@YQ5Qh(fK$ZAm=oP0 z?$faEr4zb%-F0Ebnk(`=Ng@|8a(Y-uVR>s@chSwvnt}YYMX95j7dg?mvr_*{MALD!Ro*Sfl5}cEbXdqN^hqo(O?c zo}{5cB}2i@HMR)=mK!4)e~D_{FfjpC^L0plxm+ciok-zpCRovS`W=A!lH9`G^>cgk zjHY$-h4Zy`N&&O%ZQ`uWqx#^8FkMr_PC4+_sEA-1VDqA8ToX_kzpSz_eRXm~67AU3 zT`8dpl9{g(yJ}>apIwb^B0=mEr@-)~yp=i%l{)Ub{aev@nY(eR?657|7JB~>QV7`4 zWE(2c3$1&~wLxYa@Xs8UrKGl+#h0rN)$RkT$Y|lP#;wjrw^V&*xNFe{?RWE#-JurB zw8$2{1HM0VeusW5SV6ZBeFt=%(xQkAexOy=<65|e8vh@f-vU)9QJo0}07Q(;M(NE$ z&=&R@3Rzn)7Lbgg`X9W4^JoJ$u~u1xF!?0eg6r_DzGQ!E?A*-p#pWKgn*H8J77_xN z^`<{AIvwE)OOb$q*W=@Tp|X^n1pG=y&`|J*w|w4}VI4!smB*{iQ059t8X3lB)VHOz z4fG)48tKi5$(G;$*2t$9e>)9D@D*6$GHo2`c2BR&N%d-?e$%_3z-Z*UoN82o75fs6 zZjMYYArrcYVeg;-eOZrh$Th=9Z0fAiPG^9Q2a6Oko)Jk7!q8z;aQ@CrQ3xM}5Z1N2 zm(N*_juGarq7o$lHI@SqP82HpjGsY#w5QIVU{)nMq~_))g|G~Fp(TMhImI@8LyGJ2 zJIlL=s5scPmYt;5;4%7%JLjLc2mYp70yMO*%fr`DN;?)>s8~)VkEUs6hPs-ZcL3|& z-4o<^rs?Oh_LKW42T%WEi8x_7=89YJnLnvF@v)adV7FMb&)@g=F@kaxh(gl1o>mlnu`XH@Nz37P%eW z(Bb6!EYbcCkc8kfd)z0SC%oL>pH3kp%^pCAZ(%AWQ> zQ*lcYt@C1t{E}8H#qn)dUEmUtrVM$u$YeRq1Q`S)y=gp9%;0K1x(1 zUZO1Wk{o=g`5ocdxJd9Y7y zoM3_9AyO!HSpuVB41M|rl&?OqD75{+ao?4h<9_}gn%*)lAln&d0eIufXDSOSc7+l^ zi(|NL-8`ag{S-5t6*%Mwpb4 zbZd8ggd@T`;5Ams{AcR4YGih@!D3&bST+^?khDq-_XW?FW)~LdenUERrATMu^n4X& zpMTN`k!2?3;-nbpu&T-#Y1PRmk@-j8gBv8Jwo5xQXuI=sEc|_X@+1p<7p;kx zl-NThZ*kLQ`OiHZ$)5}e?OQp9z6IPaTIkM}+VNc}MY#(J$6i+7MpwDFNdWj{VOPcf zDop6y((0VOs4{QoG<-fdqeB}PX`_VxCOt?AW6e?`HyM}t{d8!U3o?7>JU*7}(NM(0 zg~Z1^q4kEPeZy=%6g1f_{0^8UU2%H{lnOT+LZj>HfT)Bg$oR7V<`?P{{NU9-3B#b( zYsp%E15WNLFFMj)P9!O|HazP(hiQ>*56CbOD2YmfWw ziSWXQ{V*?!@RvSK5DdkOZ4Efyqe)o0rSj|U%1YJ|l3QjD@Hp3li{^BP`BmEGan_?O zx23*t6K{Y87*PDiY-h@2>D5JZHFslr3I?5LuGe?5wPfdVhcT14AJ| zQYxp57yf>eEhvW-fcB5ENk6Vt*bN6?+~^wElnGjGfk~Jqh;RBEhQ- zoE3tUUCe?#X;P?1OXXGn-2e6o@Jliam-fJGmS~+Oo*ccPuE%++E5lxr z?7q_T^7E~oMJ5?gh@BQ_`PP?mmti5WDvz8*)yYhYe2M9E?xJn#;;FH!`$!z?x^NrP z%VMHwzmff|eg_=e38$<(-R3oL>hq)x)CaR8%2feSGiX}>a-H*OFGM^U@&)1m^Htc~ z!!Q74s7J~V`VDp*yk-kTkOn(c#TcExF?!DnEw4K*ofFTkHC9bMXH`0HSIU9jXUbmQ zWdhex-NfAXw+Sg486yF>f5n<#sLaB8J<~A$Vr$r{7Bj5=EJ0qrX*Q)Vl1jw-6C_Ti zUSk-A0+r;au+}A-fB=Uem$7z`v_0XE;z#5L8^Nzd*V{b+DAD3 zk+z9t;C_E8mxccASouL|Zg>4gY7wPMgmUtC#`D{JmGEu@_&W8I#=>O;kPF1Q;o|D* zg6B~t=}eU3#K4={RdWd5(7Fi{1G+-(!TzR*-wHZ!GehrV9vFiy3$R2`2! zF0eLG@%WReQUZexf`x^JS=bjV=h=t2hK;&1(4`pq(%dSZ@TL-%)0DPy|B@+27bRyA zH3<5j)F7w>5G3&eBLApBmnivg)~5fD2QU;2-2dZP|M52@1-qE4>7`3>VgY(X@AmW+ zIh*MJI{u1Kh|?H>#wvJ!cIZyH_1qUNOvmmL4FCMOdDZMynYl%~UKU~?7h-_I)iRxY2=4(O}ih>)^9ZW=7^+ zRLU1!L8&C0ae{%UV8IP6w}9FmM?r{%>(}c$13taTz9yz!tpRNT%{TB>mDPX@XvZgc9ak zg1Zz{O@O%HC&GlT@(uW{XaQsjV{Vl-3(gY!+_)YeA6^m5ncZ{3#cqP^j_}2X4Az<6 zmAL984+X>?Q(`cWLy>N{>XWe$~BE}s{5_vaKUfY5cj5L z!yll~>XiZ?;~nIMfj%2`U{Y)cU*1r)URFE(8ihE7m@aShS*2Yke_1m6Zrw}>AYnbyMCx*|dZ2>BZ z`DU|)<7i;Xi=Ymcv&ceheh!xD6A5(zN)zqnDjEiG_N{S~{gDWZJjI4w%7Dj+CZ>hj za@c$cpVeV?xC5!ItQszW-v~n+_({0_z(}%3Qe$L*pMu2N^A;d*BAC33@ocDIWVODN zs$pnMMXVGasx1RdAGECP8%&*jCED^JbRIJj=phovhi@iOTBTo2BL`jk2jhb}En%{+ zs`;ALp^7a1%!fFyC3#Vx?=b*6>^K^`Ski2XvBYNMi`n@gfxo{{ouL|;1KaU|nSB$g zqH3)ANd_Ii`g(%~(g@oXg8=H>&(ctKvAD;XPvWHtO64gwbO_HuhF?CBEJ})MG5n>d z-ReibAPWWoB3Inh9?;F_X<+*OyNWT&n50>C%_k8wQ&kSJ9WlAH^YM+ywNjpn$fh%V zrk#NfHgJz(2l*ppyM1q&2n88TK`vaDaIECx=mqhwY?v8pI%O`!#iG35!9vW#=d>@Z zXvz1GM-EsWLij%t9fxd<11UfQUoUYjs9+7NsF4B-I8ki@V>wVUy$m$^`lB5xzNwII zZ=|Ek^#eQ9mFB{2&LpZqK5X=W@j$)JdN!i;7epq7<}g>gD;yZY5sI&Kjl$?dhA$)J z{3FirMtpqGjqtSb1JLM_gE+8TN|RquXK2;{8uxhljJw$S+_;p^;Y)TI`pPQhbX)+l zf$P7pX6?!R08j1H6asG6dTixl$1Y6_nIdd#c#gdE&Y`Cf#M+}PkoGPhxSOXc13^pw z>N%+W{wM9zF1 zWp5w5kAxzE&Y~!*HvAk`dfVw`NG@`2-R5r6}K7%GL@I+Tl`CBFepx zB}wwhp=d_GZ8TUy+e85r`HJSJ(2|&<{&)gU3R(v3SNP@$p!D!_tg(am(&EM|Q%wH- z!Uw_IBmuvo526oXlw(MDYlnQ%Wg1{HDJ|T(LC*yDur~nNI0puPpqZsyg%|8&G;+eDZDjow!^PGWVo@jX(nqTz9Vv!7=5?%`W z&~Fgk2gT;2Uoi$iToo5{O1sT}oXO&xK=Q!BYua_IpVe<;(BZ=%c7COt@7t;0-ze~Q zL8+9F0Rziqh3rVtbba-nL-yIRq7$jPXe%E_MF`C^vAGx%M@mT_VQ*G+kTi;jB7vWz{IGEkn(xOK=OjA`A{y=ExNz5p#%Uz z1k^xomEwwC0Kz8uWh!N%OQ!lc7^euhG23wG{mM%0sP$RvIyQ)$M-M2#=Zx9N)Owdu zwDBflzOne%S~q!)60Jk|BL6k|8Io6M_hqMTpOZZB>)ko;;y>?|oSet;p$WI=&GOC2 zo~_wY-PScLF`=bcC(}oUkT{mezX$A7xYi?Ok08jLFDiT}6qkWqYXRPfmOXPgpp}@~ zM$CDucLdcr4@pUx&z}bFcm7HVVT1%;kV>ZBs3SWOT(KdG%Jo7t@G-xpF$LK=xf;*L zAc@W&DW3iOrfUM*3R+W%Vk!ex2U`JCGt~3W?5$k#a{>Wv~@9 ziol$b{J(fQ^KhvC_y3<+jb)gz@5Vm%v1T`8C(9@bNn^=gS<7yQvF};3#n>g;A}VFg zQW6r9WXYOD5*6NGpX>Tvzw0{Z&vTtW&beN%`+hwi&*zQeL+g*jD+S@=YnHO~`hn>#Lm?fy1WAtj zyUhMO8S}PkfcG#b`@E_3qqx-l{LP+2xJT5y$=71J^lRZtHEJ@6epBXvK zWm>8C5P`4OWVHng-;7P!EF_VT>_J)wJxw<6x3 ziqj4L2Ut7@zq)5)KZbSm#Q0hWIElrJ=ZlvTibY6(yq{51MLVrG6!=$=C(DGd7T9%@ z4}ae$E-zS)93hV|Hqx5qwSNK#haPk;_+}*Fy5a(Lm zNr%cP^v2*{sO;w-KatKOZkL0dw!ddJNyc0hg?&xJ9E8y;_nMaP5 zZ)JqR0cXp*!@}3(SO3gW`PtC;k>m&sj#VY4w)pr_o^y(2}g%okrKv#&g%bm)fB?rn^elK z^jMzQ0%{-!-9n8`1_3dc!JYv1mCEOO0 zSLW}IJ{IZCp+VcuLGo78Bi|3Vp89jBfreiBiJQx>-VFs#F+5`o--`MEvU#ykFv0?1@ z*kuj{Ni2oWuney-kCWo0VI>ad;<1?93}c2suMMlvv?`t#SWZ+oZCzlz2m9v+?ODkC zVC^ns5hl#QApKye$yQTYZ0uL>mHu5-8$#Zw;!_S8{h)+_&eT_{A&RK}ER0@noD|)! z5JqKZ$w3f!x+mMpdevv+hIvY1Wi30VVw=gF%=7Vtn-8ZzpEY;B4*Hfd&r(bELq59Z# zzH?D~yd3#sCKiBQtz$+WtYNY*8pbZVnvT=gridA3{R<#qh`t}Z!nFda_%`Cl?%;L) zikhI*jB7VM5jiHyuB#vpm#nx@#Ya!glTBgz9_d$t=Zbr>jT%rQfX=f?cG4o z6xiqrGwrA`(y{c`lifT8^?R}?{`*(kVm~a}RqnK67cRMYDL=Xqe4Ih!>BHU|J!OCy z88Q^3sMZ6qxhy;biljex5shEopmS}~(-5KBI zUSYYRxC)WTt;8uBPjSG=j7l-r!;fnWu5IJY(berEr~b6@8uo~8TWlXBjlQVLK4y@KpB>Z&dwDCV|!fK2YmF3Cf z$(!(xa7HW`#1nAX48-xJWG!d$vsv14$L+!N(SmfQBF2NcDM$LlQ^D~(44fjBCg^rr zs%9lyKCeyB2$BlD2nD)|)6^?SX{H;mNxt|9MD~S3G>8%Ux#D}f*cE;o^s^8u%45GS zy6mfImf;PO6NcZ*l92P4g!t4`>46hWw#itWP?QOgQe`ecwCwm~FK~kLikJ9>xJtOu zPDXYCr3V3bk(pk8C!d$gQxsVU1#5ZQgOm%0oKouX-@YwmJ&BV$9%UwS<`ZQv^vFm4 z@PS<@;y0;;y?OH{w7|H&+>5~Sx6hgM?6+J0!AT#us!sqL_u~A?r}&lu!T8r;ZH7FF zq2D&DZe?|lQ5hnp1K~)}fjoTs-rn970Iw5ye2hsJH~R0oiW^~-zF~`ZyCPghfJF$W zQ@b7mV9Q~ZnUl~mCVG=Qcu@NA^U(qIZlsWV+wlpRMd-nGc*=vIYGAU#z|k-o4qkjS zI-p9D(n9}8Spc}TVcC;k_JT)YeExojM_*zWpRiecDVw} zFI~0AG*>1K2sl&q(V|k6CB=T!l0l(dr}XP~^baD=9-Qg3*I9s~^Jly~SwqSZ%d)V) z?zzF5b;~OmgR(cCK00ItNZ`_H5C9|7_`6V!7}s34hfgy*D*qw3$s`3~MJwXtn;08g zC-ri^$Ekm=PIZhgvrbR@T9icd}Rzi%Rz%6g3TnzW!Po(bg6X znyL(XdF3@H(1}R#$heK*45j=QyrB=fq^c-8>xfcefZzBsOto6AB=11FU;_z*ZVBx_ zao2CwqY65iQNub%inB|gKQPP9heu4pWAY8c^uZJW8F;*3g*L!> zq$k~{aK$GH_?*uUH z?X=3z=S<37eG&CDDaQ2|sA6=X$M#pE5@y74O9M>TKII2>R6rCa4f<=+g&y-NC7_bg z4DFmIA&C~Pe-sLR%wB(mV75irc)GO9CI+#&(W zcmx?=m*>!W|9Rgk#5O>)~z$P}0O;GWUBHjBg zSi#r0L+X=SnS08z#7YL1=Xb~fQWx@QAfl`aA7g>-MO>Yh6A56#_da!@XOB-KRMvei zKR}Q#QF!&u0Ol$dG1Eq~_w?@lzE_Jnv^hK$6P|j>S_-s*AJow?_e&p(?j|w0&-eaD z-H@OrVIPmCrDoG*7a6V6xI47}SkzSW*1z)nGnlZPm5`@6)j=L)-oE?#Qu|hhc54sI zxGb96rJ_FR?xSfhk;8eno3CmRHL{ktD!3P8!%)|SN!~ZgLxpo0hLG3KN~pg?c+*zy zS=qQ5tETg+TS;b7q`9S$@)8!Xup}?-Q6?H)Z{_O_efQiOw;}wxD{o;HI=cS>1@_P^ zX+lV1J3_+`|4VeySntC_5I9NlCo_%HCy7(GQBigQtX=JfFYR>GU5-_WaG@uyJ9k%r zE^Q1S4$2i!M)zOr&0uXR9h2%8e^{KnMf@_~a$ItLvV^R=5NBK1Q9j4Vvv=oQ6bm*N z=8=Ic?h-SceT1iA}101f8agC_H_XkjdU%Ms z0JVBxLBTZ5o~}Uwvs?r$r8JJ7uQF%E=jn&Q8oil=?=kqTrdSF0h<)V-cg@}@JZP_1 zpt4eH9<0uYX+X;gW7n=YXLIiIh$Y728FHH&>6upewgbq2JD-G5>>zRWYY~R>FKF{5 zOyChmBdYE)>a8EzxKpTXJFrnOYf+~4+#!^n)+2mvK3XCt#{k`)M|{3gkOmlp46h+O zFCutBXQF%0Fj)Gsm}nAK1hah2i-5u;_7AHqD&}(d>t%r+HuKrX6v)uZ!Cp-PG-ug49ZT6rj=YkJn zACX&<^)y&M<=QW@iwl^MgU&?4@S=wY0y6R(L$3wge2o7hm~%VQKpOS_$zOe|?-g`O zE_1xJX#l)J{)G`3j7{_ZahbnXNU=)dE?8ZX+b8J1M=6%Fuyajp^>O*zar72Mxro_&kx@+Ldk(ZM8 zPpb#Ff2ef~Xv7H;T@P+IOFUN0rPyT#{;T}R_#!YJZeOY(qVpCStf)b64u%_)xEMu+ zpktdR>Gl!fiet@BoH6YEgjljOCZrburp^7OxtzgNpBc3xISLEn_?v1q`z z@j?~QH+vsz_VwZt-R8l$=4|o~z^B8r&R(w16heldfu`W*v(8bL&JQ`C70 zp1%qTEeJSh}#@nEg&~d4pW`w^4d@ z*i38cF=EcjdY5?Nnl}m_h=b?G!e$#7xtwZlksFF$zFZPc?`Qxu%fQ|+Ib?a?Bg;eP zpOb8WAA3POn^*Uy(PDs8+^yXESR-2koyAgo54~y0Bi7V}Q#ZR8YQp_aGTniHFE;%~ z;rlv&{%g2;C$%UmNMUYhQP%v6%C|lNY{`4~jjlJsX8-Z=SYaBeG=4+Ad2D_%& zyAq_X9**B5R+SgRMxM##TjVZiOF4?O2+FgzuQ1)U}(JFMgl5C`TIECUiUs(?vlpwoO=m)AFYr zZ}-pifRHuNZJz37be3RM2bI~tC?PfM$Yn9_x-YO4P_nO(wtZ?Z;$`{*#3m>w7FzQGzu*9G5>L_61i z0j8#_%Mhgj0p?MMOeT3kbsA*Xm{24XxSd9_(qNg%b$TPjCpMkNW>|Iu;@=7qN&9*r zZF4E&)u->KDt2s(QH$nAeho}l=`^g?-s)CYU2@(d`UixFj9-1ak+2dHidMH(J7^Zm z{q#j^3@(y$x%Xm&sM$z>cmEv9)K-kJEcK{uFMqeREZ4x;JJRzIdKwtRqem^9N7c`W zZ8=~>l37cc!u|u2Rj#;24!sW> zycLs|`&h|Lr0KTZ)N4h~(1TfO25CI4xASwlKRMydXQF!7;fA#B>rv&-v@F|Y4&o)G zE^|gg>xP^We|4z!wo6RXMV<#z5(FQ&vJWC?X@DFM&@9Xigc$aXvr=qy66tSyoq3r> z8%~)BQe+(GFR}{tGU@tK&|%zXrw0EUAk4?~=187I!^u+dsXUFP4mX67MbVpKV)}P{ zz|-Eoplr#^H^*xwAJmwMGscx&vqHcr%;Vb*LS;S)aWL8|!pWO-1JcF{ismgrI1lvI zKeB%OkrF=P+%5h~+Y=w2f_TY{zU=lXN)m3;am4qT^zwAgqxcK<=+?efi+bJRakQ`Xw@1n*_+8zBODKoah2BYy>SvmUIcCZ(k7>k#4_^7cOzlDBKKx>pAUd`hb#Y;Q1H5Ef}NZSN)&NjP6{k zFWnVWnSCBrPR@Q-ysBZQ{}6mfzf%DpS96xr`k{zfO|)VCkAQ?|CCUk8Ei9e^;2k0` z!nO9qNjyVyC-wVRaajy^z868WI0eP8f0Hqhgh7V7jN}{GUX_+cO4H)GDbengQ{&EK z>V9~(E@|sWKraSXuJ-z8@i%pJE49ESXK=m^iu(qKN;q2rq$0a$W?Iqhw-J{ZB@5DG6t8oHnWlSf59Y-h| z6rPrSSp*?dN1&u#hCp}qW7F5H!>~(v6tal^jU|G@mcQ-BO=$uhMM#;hNr8)5IdTlK zLAs`*UsFkcdDeEq?uqDer>&g=aPXQ9X&5Gm8!?zh0*vFJy+LT09_Zwj6cx4tGj)pPIHGL0=m!W4 z%w=Ulv2dDFbM{sLmfM-6f?Amas!;;cKJFc%RPn(RkxnmpBfA}qoOXs1uf^sih<6J6 zU~`{bT{I{Q3DVO;DdVA-!Tv@LDmW@O5^u&RVcJPzvJt&*7P8t8qq2|7e@IFHnIPbn zJTDh$qar1**E#lm52YtILmGE{mzO+_s@l`L>ETovcabg_(|PiyGp` zzt;;_W4oknP#4C0KVG^O%btZas$o?JrJh{&vANE(G zbiR~zCSSVFy>j!YmqQ$!k4F5IDG4x>W-0{zGXe<^;*enh8)-;>QzK~G}N1KfpFhpOv66n6Oc&LyWLjB;XyNQNQn7X8$_ZCwPUUgLxI zgVtR>n!ZLSy%A)UKB+!Qf>Oce6gq~sto8*FwQ`#D8f|)cF+pVMawALNZoo-#6VvQo zVKo&zvZ2M$!+IXp++(*<%S}Sjk7)~vC7NEEi3-k3$rbiW61iro?dH=&yP%vRcxR=yA7a*Uj&82LQuG2Yv)ric0Fe zKfW9D;CAt~$#hppJ#0&8O z^A&aZ>pK?+E-B=6-2k#Vg(gaKagNrC`$0Z<$EGLDIc;}2Vui7)(Pn^iczWYo2W#n` z7h4ZLn4lXvdE}kov|O&$WEu1)uHx@ZOu*86Q}rL%nATb_jDb7}F@&qziLpO+*KGJ< z{mNEt7tG*p9<`s}3+hjT9L6~6KNhqY_)#Mw%X1W?uB((hZ|-nAcb4roTd1*Gwc*_R zCYy6%mW92`&kO^ut}Dbm{(>0w^zF6!Q0-lKrQKs&^wI98;Nm_-p}bS2Y1hAcb@;tY zhagdJ^Xz?_{f18uyK6Hx{w+uSj8i2YzL%7%3^AGp!{*~p6@*H0ty!Lv! zx4=0FH06goW{w5-d;W0|5?qSD<^_AKz4~L z45Y^U1Cl1IX-F3pdW0eB#pZ8OMPc67P#53#{Pde&-Q1iT`=$IxRQaR$w$r1Itl%#! z>zgZ!@!grT;@|vEJAKi6`!70qf0HDNXJGQI!4IF*or{NG{J5>I-*P{^SG8RfbX`O9 zb$HJ^(u-psPXKPQw3ebOD9f_cA9C~`kN^esDLLM3Dm?i$6M|!(WAlciq@UPA6D~+r zCsy~V-Wc~OT%po@Qv~cf*K_B>3ZzI=Gq2P;W2n@Qp<)~tC62Y^ZQu!cyHMC>_Um06KF{kTLA!Q)FEV&_Zr&HoU@tu@t(aOIf4zBHt+z@CDlUIXRi(+SyC8!D zY}h2Xz2GJ@a8|j2q2~_pwwf=--q4Wp3r)3@ECVwevM8ysyPmtU2~lO zJN7;AuPce)=~F4*EZGDvCd@s}0L=45G7m7v$Y`;lFg6q1CY*f1qFT6*3c8n`t4yl# z76Z9jsoI}^H0YaN*B6)OS1-Z^DiCS&0rwOKA4(;sUOh4QJbZCodBrrY`%M)mS#cs3 zPRH5)D(rz?D=px~xw()$a;i|v*54(;=YMluiyk!Ao(bNrObAx#-pHi#4L1gaEzY6q zdeD^Pmu=}G%^#+Y7a5s~(@{lxjz>3+{L-d^mH#E5cvAFg$n9H&XMdf;oS)DPRmG&l z_T6G(^r*N1Q~NE4WA9ttnb4`D%(}G?|CI6Hj*mF!kNW6>XvAJle8#`R{>?+Cv^i+| zO*Qf$?GI;K+$B#V{%0+{oquUn!v6Posgmem6n&lZ5B;ZD(32})L0szhbRN0-%6n;) zzkO^!ccAwYiTUwo4P{-*bJyz2{Zd!hfnJwBVtjJv;M1jZm$%>lKG`p< zrtE)GbS5#ioD@}7_=MA6HKUN#xqqIUE3RgRomQrWzopPoJHTb3UGg|ez9Lhi8Er!% zj#k#g_UBBsJ0+Ekvi=8@%N)}m_v#gtjaq-DKL)7?Kn;W^g|jwM!-h&p*HL?Ae}{(u z1A2gALe~Etj@y8q;uANZJj}7~0#LwR6VJo4dqyBjo)O4r2r?Xeh9I9siTp23OGU5Vdb3DPys7$X{CJ zSl8(p_-Tc9nH?PU?(6S4tq=13WQ|OYnKemb#=lhj6r+KUInYbDRxgz+D&pMQV!9wRRQf zHtp>F!R^#}5Rl-j>8o-ur%I%_I4sla4a2-kpZ9pyJPoYR%I}j|{`zkKH6Ll%y&H3# zToZkn4J%U%Vljvh6~eWhmZ6F7^%fU!H0;{za6zSpV2wAQv>RnvzuhQDR_Ms1ps={< zEVgMN{F@>-^UA|VZl6K(w{ntDgvm2vD^*QIMnAK0&gj8#u-UYLrFw`HDWT^Y;On2m ztrfKiK(p_BYga_+zYXAE)FwfURvtB?{O%mTO|87P?YO$Pr%+q~NgUu^{&Q^ykd|HM zSMQS_TA6}Hn%J?M>SgKq^FP-q)b7-WO_vC{F>(OYxI5pbm`ar%CSG0U@@yKSaw(Js z*-j`8G&=PtLN$I_7&Hw`WCl=ehJ+rs0sEyb8g_eMLT}U#;m^Yq@_r@G zJ|b9V7QA)k_1+uL+xOozX!&+y+0>(>8FbA3Ii@U5dG?z_#=txOM^RBG`8r7}pLIRP zd4)4)ytetD&3t`hC@Z+0d;P^=Al;hgsj=o(W#h3ZQ~JL$qPZt3gXjAgwvdtCKnHc$#>oty*sJ2{5EI-7d0`5c&`4d ze23rVW#dyq?Zf5D-tJ)ryFt2A=GNGRTM?UWT)O+t_X|@JtA(bFGlWL+5*rKSJiq@f z{2P-4(-Yd(8vV7y_xJ4NE-B7WZm5AdAf+_XSXR|aE{LPRi{upk9bqu2;uw&?$n@+6 zG(%UbZ>SlMQvFxVqfa#_njjk;uUQA|CpA3up^Dn+$;Lg>RcvzybOU)gsZ$Qe4E6{M6 z`w5qmVO2yh37h_`oQ+QrKr^IFQThOUw5ETcMlh|%^P}g>-G?tKk=jWY=$`BvyBP}n z)71wtH-|-zj@>GVy2aZa(4g>R3)0yA@z24j@zdIqGX#t0cacZeE4QYk4v$P@jO!bg zGIe&o^;)lKsSJEZmF6$n@chJ-eaCm;^vh~VKJ9E~!XnlNh7`d49ULYoi z>Gax}kx*ju+uss(&sude<1enKOP+p>jc&^;fZ@l%27gTi;HG};rH5k!e_#Id!-E(~ z8|fdaMsS8psPgG_>KlY=MejZKr7a~M!jcAGDV&Eh#Zw%C=!l+HTl|=DV=l z*Ji#**jND6VsNjF)ZY#2g2{v(K6$47LiO~il8{sAaVT}}AgyV}Nf$1o(Lm>N8P25e zuyns=!}nnM#jC-e#3(_&gaqZ4vt>70yyx1&5*~c6rIgLz)CRMWWI0UIGh~pe%1bB* zoeuquX~%50oj%3!w19?H!~r1mx9_ri?cNgIfh5Nk{N5zksOWM`*q)Czw)mkjMZ-$e z6FZXa-;juV%ZgOdOAz9yzKYN*GFL6BW$EM(wK4~-#Z7jhm4_CB(vo7F7sVfUVe>5m zv42y$lz`coE22Z>@27_a|KRt9izgT}%yq$*Ee@E!C515oN7=q9Wf#6Iq<4_J$xqfL zYn*mj;uA}8F&B{xnJld6zU@6v`uwUqHaWT6C0gVJ^{1JUKp_5npmo;Gu6Iw|xF_Fm z_R- z$%fo+wfcD}ct?pp{fsh1)@u2oPL9Qu?!Dt!Nqa*v#*w*yyLinhxn!2sv;v$mRr zw{A;RAE7Q|+}6jkG}bzj!|z(Q=l3xm`{^~kIkS)S*R@%c_3;*CZQcZ$ zHut;zJCB~LS_q{am+LAr(RozHr2caOKquiVjA9~kYGgc!#AXfMG6bHO^3B#6mXp>) zmTlL{wIU%jee74d%_^S${3I)sM63o%z3%h(ToD87UdBxwI-XQlvY$|M%3;QWcjURL1c1n1gvFXO2(TVfSEk;+W- z7lK`B1g@uX28-BVJ0P%txU!GD^$Q_iXo=~LMUj*XYArjB3n{?-ZvY(!UckG z007sjUf7RxPJF%$Y{fQqDPfhr6WKoRQwNKve&DS9J zqX=Dy$d8bXp;iOar+ zOmJk1@XYHCEq&rP0Dj624Ch-};XjwbFV$#$3}5TKpQ!Wm+Z4%;SDAW!{t`O+RYYUc~8ce2z^IS$)0{ees2?nLO|%^_U+L$r2=m5%(-TrE|tO z#>~4CD5>7D5%b&}#cz8S!Qg+X4$g57r1kaRCvsJElSBZlvs~`(iSMoH_qbF4`aOeC zdB6R)f2ZXEVmy-bU%x{y-o>5T_riyB2C`}UQ!7XyVAN}ZZ>m}ln7NayFB0N051NMk z=3>$%;wCpt;_UzEPBf@v&UV+jsavrwH4oZEzuxNOC~kUoko4wlP;5~|ejriuTxO&P zxNBWs{YKZTU$=?MPZ_%fC%Qhact!_+^i&ara%Kpgu!D?`x$%d*)#^sLZwv)nFf=;xmf^rIx{W;NkJIpU2QRk zAZF_U-oj^>{tU#V1XcO>5WUP^=eEtWD*wC-+zQn_T;mH4oo;^N~^qxFLj} zg5p;zIQ;kQvTppH1K`Grk0H_Rc+g5Zo_K7G~HGI;4fVEd#$Vt3>1)EnJl)-ye?@KA} zZ5Pr)m#s$=>A0&m=1)lzT0T?5lTmmQd6KaT%JrEEq@jOB_ADpM5A8E|+(%QrXl-NX zxX!37HOOxPp1DZMAB7&t3F)VVUUOzi2ULbUFKjYEz&fF9^wsy)62oV z`{sj(uPA`WXBP&IZ)s4vk5L_6f}7juM;e2}zWe)0eb2{(Cr{MVv>#tLBW5+P!Jeep`{n7-0j@zg%L9H@~5zYIADz`1PGq?mYLT%%9E-zIlkn}j!i z7qdx*MKeBq>Q(~d-Vi7i7{%()onw4_R`4Wp#okIi)bSWl*L2=DQ_;W&GCXwHH=L!K z0+X1J+ht!j3z(dR$wfR)GSs*ueKRaKA?nd$=EJk(L`J?bFJGV~cn{ z^nU>2o}=ri_jsS%2~mKuqr1h}QVaVc;&PY&ck_oB%;!Suy?b*(oBmhCnRgYqttYX? zTCBwp2qH8*gpnN6!RV7PD$7TwFTUzFW%6Yxk%`GYUj_v?TcXSp?yF{5zhc14uGnEw zKD|R=;)QxlBUTMfv7dzaCysTc@q7z=o`_fCth`vWYU6Pa$hQA}QqiS;vaM+IrNCHx zg=MxZzO|5Nj_mexqZi#;M`+TA3XXqaNaVJJbldGo;cspXwqUqz3=y&T>SMC8(3XfV zO`;~~B}akN1hh;T@1lQ}D8z45)(P;OBIr9&7R~r2NdkooMa zyG1}b5m14_tha?D>>JF7_4Ct6zE7~I%)8*NX>RStk@VgRrU!J3SlK$uD6k(8^tjO9 z|MN2KPQV^7dz_{TR89i|muTDsA2XvEekFw@c-5G86{{KZp5n4bkLdT#Cf-UJit1PQHR3760iVV3YfGjqF}YN4){5(gb>Dz3@q2Cl*CZx zAOQbK*c-TfsGe-UD){~55(C1d*jnI5`yOdnDR2mD&m6Dva8XfSUUCaM55gh9#E&=Qmm$7d^>Z!AYLq7pQzuzCA)Fa&NAZ63 zfVsxB+pv=^1+ORGt29WnrG%Ks0greQ$-$o4Z(gaH&wNr0@!t`2jD#B|iEZ|%bO`DH+snMuq#L7@i zbJQ`Hv8lL~_ZhTiQ20rS&U@ChTXELNik`oE zb@6Xj{ztc}@lz~QpMkxpiiiCXxP0XFu2Pzb?A<>(1tD2kj1nNo16IS-k6(TL2|nR6 z^KEw%Us%4&#;ai&dYa#=3XjGmK3|&$0{%cP6&A-$`eqiAcV{In~Jy{;yGXS_^eg?sPDI4Z5VhWmIP`gpl ziNp~TkR9`MFW@ffPAyvxL`}sSm3$Q3MaQuFa14!y^+z? zZ~tiRig7l#wrH@9DR~LWk-r+9e0um1OHljM)aWJRx3JfF_q{}T@B94zpHdqxljUcl z-BA89bZ)B#VA`l@mx@3u`P|35s+p~@H#4aR8k~WcOg!m=;;lz2>f)$*xWcR0uGTku z^|nMVEKek^j?sigAMV7+4poYUs%7lbL}&()$iy^ga9|YsD7vL-GM>r4gPeaHniCB1 zxOZvwY+QCt7sEZXXhJ$NQ}3f?z-7UVj=C>nLbPL1`NA=1t+a)kN;Ki;6%tyoj+jvz5;-(yeQ=df8)p zz|~Cx$6D$LVBm+dew^?&qs$pSm4yGgAsJMZ9^B$ceRZSHAw|+mw%QJO2EiZ< zhfbR=#gZY&J{kYy+qNVSseb(alD|+3hz{Lj#zay5=R!en+>iecXnhb>tzkiO2vf-Q^s9phG<(3JT@}1l-JUqXm zlx&V-_abSD@+MoN#!_C0RfY=eZ4}he;V*e_-RxgN7Uv@KidiD4dTT2nfg(b>SiGn| z%arGi$9n%;qB`LeaPa$a_@I?fy;r| z&r^i7z&gkfIu^*+2Og2(u^5^14enQAOGW|@#`pB+MAAmuyJXMkV{{fA%1{@{-Kok?N(&YrA#541N8#ZNPqmn?4Hlw zy(U`kM62Jt?VaSuZWLK?DM@pW<69pYkVT>1NE`x&NxR=fU4(ysSCV6bZo9-?f_H7v z(FDiS&oTNkiCVqoAi_27Vzzrtwgmg53||iK=`j@%>i(EL^(Thc;KQp$un|&X2pp_=&K4AF&;ZDObyc;VgZEN-3%=Nd ztPD8PS3X0R*UDvO-+N>s8Lp346ATr}=$aC5fBJ=-_-oTWQFgYk*#d!D8aUa#au|s<)#^2>xRr1 z5JAkZ6(@Fr$1r6c$lYK)Lu>T;hh_wE9DX--GX)*unD}hTv$;4MRq%KG4ZFasaSG@$BnLPdu`MZt4aZ$EH#(9ruOWa@&~Z;DD{p6yr~yF^_hX9D}f`eUf)HN*Qo zya45RJkRew>g(>n(}?b#MU{6|yy{_j`&$Coly6=3C6wO=v7!dzlo^D%>i~|=NR!-l zKA=vK*^PSnrkdFSzai^a*#y>N37d*2E1M-sqGgd=fY-Te1^R)k7e!zG#Uk9ey)NyJ zT2TegSt~tZyel}wZrtfkVDV>L65v;E^4!px$OQ}rQV)L8 zY6p1X*KFcEGM7OPrA^%+cFyq7bEh_(Vmem1Tc!}^)eEkHQ2|T+54mr3c0F(}QGnSX zm|1a$uRk{nBGRBmk5(-Om1C{MV_#ogS^)P+p&pZ}!jmi*tO(87UJy{YFe?qc9f$?V zSHJPObk0wM2+H|M^)aYb=grh%wo-|g(lO=V6_w`OPMT01g!M~CU;4FbA94CHL6X%{ z$N!Aa1>ZuH-DRYA8rNF_dc%wJpsRyc3InET*|>Yahw`)W89~vOrjf{@$XFvBL^Rv4 ze^H}}MWiH63i#-zG7!$j68xKnz~VV60%KR z6H)_u`!gY(6*w?T?*5NSE+&@If+nfNH}D5n92Q~4`&jZHZo)M{>H71WMRxKy>sY^> zNgl}PsdAG(M)jrtmA0Csgt$6Vx{yu3O8M^Xq|cz4!}6pSvbgPMA6`8AVl$MvO)a@T ztK!yNh$Ab|)K6!@K|q=5=soO)6qy!05s&OV51v=p7G)UMl}m)UD+*67N~1V%vZ)9r z>dO3Lr~17wiE0M2(d7KsP8Jj6yePM|B%9q{-i=-TTMTHV;H0O)p@0X+U6?UH(;p3K zIvE~#NtTLERe!Sb(7wi*s3;53N6K6YU7h~<>oA}i1uAdmm}U3>zW^sB*xL_&B+QjF zfg(AAYgh~cRISJZ5FogdU~GwF_8N7?2OKAo-De$qll} z-@TmWX9}o4+)_JqgN??`K%Ibq0T+TmF`I%|dD!F~v_|kA+%L&K@5U~$*=P@;=YoKV zO-g90Q~(-evTEdo;bO16ZoCKJDYHa?xDx^Zt8ttH@C_AbY4iGoATR^H@~NyDEnmbA zSZEsiPacd2g@(idvFj^|MagH z;s&bGtbZW5-VNB$VeL?9tKJo48w|S29LRm>d<>c)e;O9i5$|tC@N&egNMIVMNWmYH zzl(;f1wRwOl6l~iFLh3+4`@E&SDq7Vo)QGw1BGl2ApvwJq%~x?dw~FK8@OSP0VqOH z6jK2W3kZ2uO&luf3v}vH#|_2^vw1I@oDuJ=;CvR>x@(0d0GJKoq6t1PMr>(PYOH5K z3x{B&UDWl=W*{&T5CQ-o17HOK0}+V2xe|$E^^WBrkxpQ|#-hkD0_+s*6w(^vfKc_8 zE4>w55onEqe0Xk^Fon`a*0|&;v}^moE(jSQ0!Nx;mu@B_9ZwW~W(`TIY&;-HIHAf+ zcj1VF?vU&WsNea#>#OeNEVWDr_^N4=Y4<~5G;>3-do2AfjjO1Xbw&kaW!@=4> zgg81lLQ!yAGxSJsfXYcqUV~BM)A_vD%f$XJ#MBsaF(3wSADAL00K>S}8)rAF0tJNi zDjkb%fIXH?!hlrr=weq2SVoTO1TADiB8KJj2xynhH8}ndU@=G~xWj{C)B~y&>5laz&N549P6F*2D@Xk}ViPwI7bhZ7DPC!OEo9Jc_^KPO~j{{W4d81Rp=f|`%u1p~xT#0Vq;M!*a- z@a>NFI-VOLk>Ssx^HJjj9@o6bM*d*OQG7@%_bwcPVro=JLHB(G00(FU>1SXetbLDx zO+)sBpGE@As_h+&!H&y#=)i++LtpH+gaRC+tfAEb1wR*9OBiW`SaenQ^&UTlTIVi0>$9Sqvu0}{%-#OsT4+Ld~2t6;7jm)QK@Mf16gDM zh%B#UmNK|>JQzdCk+521Yl9)C<=oXArAxz-vG#i50#e5tbV=UwfbhV9-wo zr~oJfWuPA^0-b?HPoPUj7;Fo)^gMD@Vw_~KKk!jftPfd(=%z&C1a^D6ckqfm5CjnN zM{GzJ6leNE06!)WHva&T3pXomfEJ*K!sigg7cK?}!o(G}b^C>^&H=zt z1~ue?XYdXlsP4TAH#hV-TnDDwa7HUa3;TvjXkNbH%|#GF10j|D2vSG@3|m4~X@PQp z+@qnO%yIy&LH0C>*>hRzgO z?e!v@P!+Ohy%uf0)j{~O~*mA8ep^WSc9Yp3_bATFMmiGz({nBX>E3=lx?jBBhJM-4tN=lLI)s_-r6*FG_mtIAX3 z;@DK~dK!l{!cpP%rdt5278wAuAmu4)%W^2L2$N@E2NxS4bl{Z=xIh}64^fxN)2L~X zLV!Y8b=*HN!H-a0O3xe7#sp(r-khNb1B<*bhybhrn@-pWWWfXm(_mersLTMF28YBY zp_P#SPrRgTXocQl_UWI@47A22u+l18a$ELw^s`hd0egDC~n#Aqxvr z)r@~K93W=^kt6^D$N>hyuv_fTi;M#FBM^g~JwS7jS4(wvk-&2qKoE#f>v{~lcwHv8 zs;o(o`q-7LN&o=ReLmurwqi!2Zvp~?FyCW_lOPHR6Ahhi0C8juz_3Y9g4PngTECD; zwha&n0j2Br3@)gVFK`?NP$^ITz8so4mLU$%13B7a=gws!FftG#HFgp#cE>0QAOwIQ zgR;Vj(|{Bn8arAD52@nH#xUc~fPi29$Fk0cf0)%!20#`J>fPchRNsng z50rtq9NhRvaCqP3f71T|uaYWwV%P!|=naRn6!5JFJo}Oh$m@dm_z*a$iJc@t1wqCx zuBmYv?%XDTHS;=RzvG9SQRKs9zw{{Ys~PSE2EvWiggpa~opY8=o-B&ZNZ zTqQu_SvaRC7->boc2T1b0%;H!I*P~ukOxqC{!BduS3nXMARZGj$bCXlnnw*8{Od3| z>$Ct!3=7G?XC^0X?+V5k#t5(j6@fx9L+miI-6Q}A17q$u2m^8sra)wT0H^PSC6Z_| zXiyxd!b6ohGmSOn3ck@vs>>?}={OvD_FmogWi_Y^IIW_jnF1fhg(CTZ4!XD~AS3(S{d8~yk)X;p1cXadTEKz^MTn{c z^Q$EWKhri+b?w){ zD^S3NeseVlei?V31#!s;{5I6o9`*x%OD;sypIeGsQ0^GLmP_N1RKAtWj*a4^N$4%g z5<)-?AX7&MU(AD~uIdd7ja~Cu%xgWQYBVC^#COTj(}VhDlYg(jZR zePnzp%t)NXRw<#RQB*KNbrMC7)evLz&|upT(8vbSMC?t))=r?~>-7%UCsHAkW{nrz zAcEPNAou}x#?1bqGfe^{kU+#R5~!#_t>6(Tk*W@?46Yyu0AM&D-?(qe76Ty3;gU!N zrq;9|2?&zKg~=lG2+Cg_AY_tRVES2tART~7H46d8)z)tX#|VJj#CGDp4#qSheyzzy z1`5ES~N~>`5 zhXu0adKnnM@upD&!pf7urxURi__7|S`~m%hZ7=+HM2HmOz`S1yM5C3k(=?i1?8dej z4u=Va_Sz#L5&!`Z4=8c2@Pi>cUBFu?gZ<+k=W=5^pVTwh zhzJkM{{SQi0=1a~!O8<73>7M|1m#c~7Y&<`6rYj95Nd6pkvnfuv2+MU0wasyxD$#( zJw-4OhcF*fuyZE(g&+ZfbSZSa5f!Q+7(RuVf^-{(0Q&b00s&+REL{_1H+hKizkUf| z0s%*f2T{DULi4SiG_4@AwWKH-=LkWK5BLgD3N2kqnBv)B+8EKFk8kLY55*Ed@h2Ai zuIn7OC>s9fuLOy?B9@(>s0rPVwxkFW&)Jp>JMf#w31~3g_z#!~-)REIdh>*KqrlI^ zgMtIkR>_SZ01!HkR=@*Y1#wOQ1FkTin9LgMXajNZ>-qlR4-Jw&Pwosri8en}1|V4^ zEY}&=FpUxymqa{&9`{0EXt+i>AytJB!6Fa>TFFGTLI7G{#1KtDy=ay`2!%338|$p= z!W4W?kGwD&3}Ilym$f!-!OdZVES!o3OgB$L0F4gBZ~>KAI~|(8a6mf~cCSyB05bG9 zWuM9-8GE|g4QQj*(u5csrc4mgdkqKy5d>EQRSO{!^m*e^;m{C2$ZO)OQrWCFLTlkU zNG<~$LGsWNK%e0i0EP1N+AC4kC=sapSKKPHwom}c4?2DmV1Yct)j}T7t)v!l$oB?6 zvzO->Y3=(!3;j6c6{f9R@c2%pD)j>bcD5hPKx?Bd{{UZ@2SNfufRKp2mHLUlo_hPs zbws6iAQ+;o-lI@r-#@5Qm`FWefY}5Ep_F4&Lv;j;{-0+fluyh469f~}hdiImB!qw? zo?I1*f-0FL4VWTsatr)!Hg{H1DqhM{!z{*y&3Cz+d!}NUY#NT03}~gwNiT!8}og_5Fr3T1Y{k=B12;mR55d% z1A4;OECAH|7y*pym|(a=KsNy1Dh%#y?qdzzeZoKpC9_%qNpWxD0s{;rL{U1pfVjhu z6tYAK97nVS^^*uW0yB`YUO{XDt1N;66axp01AvFPc_PDjxH1AH?3p7tcIj z^FWnNePWXI#_mkm_{tmvCB}_D0l@fF^rOMa{{TY?v+4ei{9tc8@<|M5* zXKN(5U~yR$`9t9Y1(ZewmROLT0%5hBfMAi6f>mlF42GDxI?-H_5g{{9g|~tfCOR}{uJ9~N zFboZVox>*hK)Dr0Yk&ujVLKmKGMgp5x*r&f&9t@>tx(l)K-eGw(uh5wCBM(1DFuKK zBCIEwj0j|dptlRuASw-(nUgymB8_M=zcdb##|Typc`SV)5P!)qK`{Yx8iIk7m^Mlt zg$M~_&`cU}gtStM_^;!}So*!<7?#9Y<$Z}vS0@?Bl<@vB?j(-A`iRocqs~~YDOZ4F z9tr&U$wc)g7x2ggR4bOB;!4^{xAr&#&&`m{JEkrXg9d<459?f05lx={S$H1zfioAB-yRw(81^SOmBQo zxGboE5<3fzxH3hJ$7Pg+?OZ}boDhT)HKulgXj}u1kT3BdWI(Q))Hm_GM2_VW!N&FS zlnvqQsnDOPLF0UUA!k$S1_>sftF#@mSh``#9{&K-5Pvxb@B|wVLwGEvb`rxw z8wdbGhELo8Xozh98$bryn1xpH3dXSwnEXHj6|dkx1<=WYHX40E2GIwNzYu{`AORX0 zN@uNN4-pTz0J`Z-L|CYW*G>=~I&gr+3>bx0znB2J8fYbrfuP|O5dwzqRZDV*O?^*X z_j2=^B|f*Pr{EJ$FF*gp06`G|0RjUA1_lQP1P1^B000020RRya0}vq-A~I1i1VUnR zAW}h+VS+F-fugc;((n``!c+1EKw}j{bCaRL;{VzJ2mt{B0Y3n;AJ==FEr!b>)`wOe zq7EHNQ@zO5V-$_{K(*WXquO|tM@WC$V_g@C;yKmgJV%JI-1l_M3&`FDMoJ=lbXRt zBbvY^m|B3U%%U?Rg_Qb`{)F^cBB=^FFZ<t5kxAG+9jgVA)tP+E$Y%0fPtS*(ESaPoSrLM7PeCpm3nFOY2k!wcy%uf#C8H-4XsNdRuhu+q#$Q31o5gspcCHq7Y>Mk>DXZmT1IpwbR;8-dT*DPe!VDJiSG@aQNu#Q; zP#@c-IeJec!?9AudwP+~_PALFt7>SEM#Lzt%ez)5eXC{Nkz(p+5v$5LjS>r+!s9bb z5~Os6lo4{QQpL6|E-1bBL(a(DtyLDvb!QQMeioI%RiVt0My{136PTs2DN_oXKNCyD zY)}h9&cp!B72Y681l8t9`vHxE!rnWd9K&gQU@@LBJBumLG42$Urum_(gQV^k7h+b`O5 zX^j!eH!hRQgcZD6AqwH$-!MOf!I#Ar^?^2)OyQRgRGOU0ab#FqBBVE{%G1=~R^>nS`bu zDQq756Ti)tosn^|I*?BH4x%TMf@)-Nsp)kSMbP#^(SOAEnxRUW93rcfN3`l!ty47R z;&gZF^gp@!m>N{3Cku#NfC5MYB9fL-8EsWnaf7L(Hv7FweOl~rgdt&cY?*9Dxh`~9 z@`IxGqTdL;<9Dk{nBr9`$%sYK%gx%CqUzJd9WG`gmRGwZv;bGKFaF(K&ZrXMiBt|A z*M)}ZT>k*eBkxl{r6iQ%HSWY+LMG;MObAa7P5yVr)lE zCZs7I7fmD)6ulEJl*H62ni>*CDrsiy_Io~ysr>y(+|q%?lKf=6x_TnFxjyh zZAUa7@m#lb3#L+=;g{_^Q7z*gY3Kg{QP#e#PdbeB{eOE^f=5$@(TfF&N2OvV&X=+V zs}B{P_Z3GNwEDQBtR{7+1#}t6qB=5{N9?>U*(>0oRa%LghFux7olk0gYqhweidi2~ z4({tz&`@TZON5Y6+50H>UfIhj3O;oJ;LW#I^5@1h))ol z<*m+I+~uvzPAl4X$4H!<#c%(_074M}0RjU92nPlP1O@{D000020RR#a10o?1QWG*l zF$7|AQIcVTAfiDdvJ`>B1@iDSaX?ej24j)pFhfvtgOmT-00;pB0RcY%{{Wyz^2IOM zlm7sAc+bN>4BX#GW)^O;*9p))As3pYS``QX0A-e2xele-Luh)!^J3vni8wo42=jfe z2b+1efZ%zzn|ZbAdA9?Bz~OMXTnpfxu?=F;$?s(Mo>n8;>|iw%G)$gwHU9wmQ+c7Q zcofNXhg<&uAmwp2MMYGd>5c9O1A)n0)y>}LjrUngeP0@GTlhi|og$#Z(1ARzkX> z=Y--S{uFk#k|xRX!V7y z$u(Ic&IVBRoMY&-cksUc65=kgG#(eISASI z6tss#Z42H$_xEk;g-zPI2~(?PpysKGLL?=mBa|#cB9jnA5lPNp>i(ucEBJU}WkM3V z`!N$8<8w{U5BXt)h7!(aGNQ?JR3g>U$#NbUI0qzJfL^L1tq~BeO<0<<0fd$ps4Ool zR$WmMH9^_U6U~BZi$p}&lJKKMeJ^e@k|K0r>#^N3RNED&56F!CgmQGD zWJ@{Of-NgiI*2BMu#Z)O%ynHUaNaD@1r&uZOGG-P(OR**%dkX!;%bv{qeW(siivDi zG|*)zuGNXEsv^qu$zZ)XE<*EfHq|giOgeCvV^XU$OHzkRRn@IhnhOIZ0aaVnUr%le ztIhP5CZ5a96B=r2As1Jbg%YNHD5H{DPH3t7z1j#ZV=0WdVPilzno&%ulZr3YBD6fuSeRK-1E&53`0LhRvpnIpCMcud7|7`PIZW z4|R%Qzo>tmVq-$0-l9-t5ZP%=GQ6$?U4^pMt1PJ)%3@dA$`Tx*A+qG`lJn(tpEIUvk&=kSMP?z2 z5z@02n@*I}`ppq|nIfQ(L#j+G9EQ;jwv#pXLPj*kp%hk1nENsvA{e!vX)c{wa>}*t z!xxq2llheRbgg+_YUETZYr_;IJ!nU&>H#9bqE5J&1X^MGYK0l3%a~bHG`y2q9U*l6Ia;Kd=)K+>Q%!7YDIh9>O3O#();snk_XbQFWn-?+BZ@kSR@2p|jnG ztrMV!rwKy~N|f@X>eLu2Ae8cWoD7F}Q;Jt1S+%S9T&d-=+AtK-)J-C5QBf5LbBPQ( zu?|TIYQkO8(I>yrBpL@0kkpD8cz+XB%pf4^3`G<8gUKH=q-Rzw9WE#BKf`|8{3r1h zCn*n^)2mR-MNm-{)-{N!`XM?O$(GknI;E4%Wr3koP?VJ-^178qlA2`r*v$;-EP8#5w8@?Y39Z*ZYx@&tkpYa_eDggv-KQy;i%UcwR;@! zsED+c7to^mUD!*7_g{Ap&Wrs>-e=2!1aPTeAuh2CTO_GF(avsL9G%eUmo#5XrFkIA zaY8P=DwK#~URX<3FQuoWRJkxzVftO%C4`;+o(;Y;8fid^D^QU|oEXE!Vyy}+&VHHn=GfhI0ppSj-p#GW}8xJvD2+erB7!}X|8S^TUNMoT{DMm zrmOf}SrtMg$}f8gd&nrHYYBN;?-Y|-e62T_l4(k!rjL8wVNz%&i7C2Q(>#8DAD@LT z^?x>>yHOGeZJQcm6NMzzKhFf%jFwdidI~QysIid}q?K)CxQJnr${ihF#KV1(Bttdf z{{T~|yp=(a*`AhBH5>XBTI`dCZk05srF^9AB^=CFd2MM#>7=QTVEs;9GN?y1*ebv$6xLE0xwu$@B_Tygj3Q8xS&Nn3 zE0SIm!{+DPjmsxz3!U8#=QL - -const u32 cim_verb_data[] = { - /* --- Codec #0 --- */ - 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269VC */ - 0x17aa21fa, /* Subsystem ID */ - 19, /* Number of 4 dword sets */ - AZALIA_SUBVENDOR(0, 0x17aa21fa), - - /* Ext. Microphone Connector: External,Right; MicIn,3.5mm; Black,JD; DA,Seq */ - AZALIA_PIN_CFG(0, 0x0a, 0x04a11020), - - /* Headphones Connector: External,Right; HP,3.5mm; Black,JD; DA,Seq */ - AZALIA_PIN_CFG(0, 0x0b, 0x0421101f), - - /* Not connected: N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq */ - AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0), - - /* Internal Speakers Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq */ - AZALIA_PIN_CFG(0, 0x0d, 0x90170110), - - /* Not connected */ - AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0), - - /* Internal Microphone: Fixed,Int,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq */ - AZALIA_PIN_CFG(0, 0x11, 0xd5a30140), - AZALIA_PIN_CFG(0, 0x12, 0x90a60140), - AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x15, 0x03211020), - AZALIA_PIN_CFG(0, 0x18, 0x03a11830), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1d, 0x40138205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), - - /* Misc entries */ - 0x01970804, - 0x01870803, - 0x01470740, - 0x00970640, - - 0x00370680, - 0x00270680, - 0x01470c02, - 0x01570c02, - - /* ALC coefficients. */ - /* 08 */ - 0x02050008, - 0x02040700, - /* 18 */ - 0x02050018, - 0x02045184, - /* 1c */ - 0x0205001c, - 0x02042800, - - 0x01870724, /* Enable Vrefout for mic */ - 0x00170500, /* Set power state to D0 */ - - /* --- Codec #3 --- */ - 0x80862806, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - AZALIA_SUBVENDOR(3, 0x80860101), - AZALIA_PIN_CFG(3, 0x05, 0x18560010), - AZALIA_PIN_CFG(3, 0x06, 0x18560020), - AZALIA_PIN_CFG(3, 0x07, 0x18560030), -}; - -const u32 pc_beep_verbs[] = { - 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ -}; - -AZALIA_ARRAY_SIZES; +/* dummy */ diff --git a/src/mainboard/lenovo/x230/variants/x230/board_info.txt b/src/mainboard/lenovo/x230/variants/x230/board_info.txt new file mode 100644 index 0000000000..22281e6aa8 --- /dev/null +++ b/src/mainboard/lenovo/x230/variants/x230/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board name: ThinkPad X230 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2012 diff --git a/src/mainboard/lenovo/x230/data.vbt b/src/mainboard/lenovo/x230/variants/x230/data.vbt similarity index 100% rename from src/mainboard/lenovo/x230/data.vbt rename to src/mainboard/lenovo/x230/variants/x230/data.vbt diff --git a/src/mainboard/lenovo/x230/early_init.c b/src/mainboard/lenovo/x230/variants/x230/early_init.c similarity index 100% rename from src/mainboard/lenovo/x230/early_init.c rename to src/mainboard/lenovo/x230/variants/x230/early_init.c diff --git a/src/mainboard/lenovo/x230/gma-mainboard.ads b/src/mainboard/lenovo/x230/variants/x230/gma-mainboard.ads similarity index 100% rename from src/mainboard/lenovo/x230/gma-mainboard.ads rename to src/mainboard/lenovo/x230/variants/x230/gma-mainboard.ads diff --git a/src/mainboard/lenovo/x230/gpio.c b/src/mainboard/lenovo/x230/variants/x230/gpio.c similarity index 100% rename from src/mainboard/lenovo/x230/gpio.c rename to src/mainboard/lenovo/x230/variants/x230/gpio.c diff --git a/src/mainboard/lenovo/x230/variants/x230/hda_verb.c b/src/mainboard/lenovo/x230/variants/x230/hda_verb.c new file mode 100644 index 0000000000..05fb3fd775 --- /dev/null +++ b/src/mainboard/lenovo/x230/variants/x230/hda_verb.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Bits 31:28 - Codec Address */ +/* Bits 27:20 - NID */ +/* Bits 19:8 - Verb ID */ +/* Bits 7:0 - Payload */ + +#include + +const u32 cim_verb_data[] = { + /* --- Codec #0 --- */ + 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269VC */ + 0x17aa21fa, /* Subsystem ID */ + 19, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x17aa21fa), + + /* Ext. Microphone Connector: External,Right; MicIn,3.5mm; Black,JD; DA,Seq */ + AZALIA_PIN_CFG(0, 0x0a, 0x04a11020), + + /* Headphones Connector: External,Right; HP,3.5mm; Black,JD; DA,Seq */ + AZALIA_PIN_CFG(0, 0x0b, 0x0421101f), + + /* Not connected: N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq */ + AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0), + + /* Internal Speakers Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq */ + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + + /* Not connected */ + AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0), + + /* Internal Microphone: Fixed,Int,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq */ + AZALIA_PIN_CFG(0, 0x11, 0xd5a30140), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x03211020), + AZALIA_PIN_CFG(0, 0x18, 0x03a11830), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40138205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* Misc entries */ + 0x01970804, + 0x01870803, + 0x01470740, + 0x00970640, + + 0x00370680, + 0x00270680, + 0x01470c02, + 0x01570c02, + + /* ALC coefficients. */ + /* 08 */ + 0x02050008, + 0x02040700, + /* 18 */ + 0x02050018, + 0x02045184, + /* 1c */ + 0x0205001c, + 0x02042800, + + 0x01870724, /* Enable Vrefout for mic */ + 0x00170500, /* Set power state to D0 */ + + /* --- Codec #3 --- */ + 0x80862806, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[] = { + 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/x230/variants/x230/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb new file mode 100644 index 0000000000..8f1a97d9dd --- /dev/null +++ b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb @@ -0,0 +1,15 @@ +chip northbridge/intel/sandybridge + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "docking_supported" = "1" + device pci 1c.2 on + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" + end # PCIe Port #3 (expresscard) + device pci 1f.0 on # LPC bridge + chip ec/lenovo/h8 + register "eventa_enable" = "0x01" + end + end # LPC Controller + end + end +end diff --git a/src/mainboard/lenovo/x230/variants/x230s/board_info.txt b/src/mainboard/lenovo/x230/variants/x230s/board_info.txt new file mode 100644 index 0000000000..67b229455a --- /dev/null +++ b/src/mainboard/lenovo/x230/variants/x230s/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board name: ThinkPad X230s +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2013 diff --git a/src/mainboard/lenovo/x230/variants/x230s/data.vbt b/src/mainboard/lenovo/x230/variants/x230s/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..42b0394daa90ec9b812d11b61284b91e8f09ef73 GIT binary patch literal 4280 zcmdT`U2GIp6h3!mc4u~WW_LO*uq?E>AmA1$oi4RPt#P{ju?zj#{!kY}q=j9OSfG@j zKtg2HiX|Gdi3U-T?3;x6P-8-TQHc-Os3F7$G(;j29}GUo14d(z_1u}+rM6f$5+dH& zZ_c@A&i&@zbMHB`i~3`Iw6`->9q*4-b#%qz?JYC~27IJ_kN4><7Vqla*xcCHxG~n= z)wG7b2eV;JyLAm9MM#+%t$B1se8-;jP^71l_73hy9oRIoEwwdW9pC3_G|?2Njhi>8 zhtea1d(tV|+y7J}Wwfds+q-QjMLYLy-;^Gyr;KZ3&$_`KIE2>JE?-egsj;fsc&s{V z)I?FQtzWUKenp)sH@7r(btK~LjeYU1PTJK&o8!HWy}d0RvG#Q|(bLrykH!01npL@J z=kS4%ZCjt+LnBR`;3d&;zF=g9DK+Bh^sdzjB|+LPX$9@&>pEmvh#1~|)0 z0!D;*K;%v0`!fp7g6S1F9|4(@6hYz%=OKbh1V7)GC+}Dz%xC2AoPb zBv~NAx&3Z*DM0oz((|m(nLtqh2yk%#G>x1oV}|Ty5x~RjqDClTirvs*!gk0Tm?V@d zbkX6`9USa;6`a6*=On{al}RDyo`7g@xCO(8N^w{7l>~VKOlZa{E85LGL#_ZAr>R55vveQhz`Wl zh(W}2h`oqIh$D#C5$__rd*Nn|vjDddn?+n%;z-a0I9dtT3Drv^U73)yuBdr-9agZ)mV^tsbRDNEOA^|3-HS;Di6Q$69FHPh2Hh> zytfL1uL2(R`__DR0W6wc8wCwmeK7$f47~+Jz*PW|fS5q>hlz-f1dvciBLx$69AYwm zfq)=^VA{h8O9tl=B_N?E{v_sa+Jx+p!%W#z3XC5gAx{ayZMwo}3aykvkSp}=sFa-q zZ`gSvHr&wzjsNA7*=umwyj{hl!rF|{06=?dVq;=(M|!ApaC^GQ&YU(#%>}a&mKdS2 zI%mBhV<{Z(2E#OlOC3wasp|b#y2DG%0(FOYC*DfkArIJ* zMvY|bd_&F4P6L24Hv)6v54`3=hOo_J*92~#b1lR3kk`V&#`!3DYRbE+ZDNAp$8THs3IR%=qHMPL6I*h6jWVT<@qX&sd}F(Kcmu7RX?W6S(Tns z^>0=As!FAR9uCNh0(5mi-w=?u1n6r4{bWEs6``jvouEkL!PzAz{+3#v=63l?{U zSS5JW@jyu<3Lc6ir`Yla(NKDV594=tdL;1-Ivb-D_ z#tWO$?*ZOnFlLy;Sb6`|1k5&;%&vp7cQk+y%MB+F@NcES7#e0=#q=a(IpyTfeowe4 zhW)fVteILNjae?*C0!|wVS3s#2Cp3l(>q?o9Hy5ERt4 +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 3, 0 }, + { 1, 3, 1 }, + { 0, 1, 3 }, + { 1, 3, -1 }, + { 0, 1, 2 }, + { 0, 1, -1 }, + { 0, 1, -1 }, + { 0, 1, -1 }, + { 0, 1, -1 }, + { 0, 1, 5 }, + { 1, 1, -1 }, + { 0, 1, -1 }, + { 1, 3, -1 }, + { 1, 1, -1 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x52, id_only); + read_spd(&spd[2], 0x51, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/lenovo/x230/variants/x230s/gma-mainboard.ads b/src/mainboard/lenovo/x230/variants/x230s/gma-mainboard.ads new file mode 100644 index 0000000000..fb75293b81 --- /dev/null +++ b/src/mainboard/lenovo/x230/variants/x230s/gma-mainboard.ads @@ -0,0 +1,22 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + EDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/x230/variants/x230s/gpio.c b/src/mainboard/lenovo/x230/variants/x230s/gpio.c new file mode 100644 index 0000000000..a216c6bab0 --- /dev/null +++ b/src/mainboard/lenovo/x230/variants/x230s/gpio.c @@ -0,0 +1,212 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_LOW, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/lenovo/x230/variants/x230s/hda_verb.c b/src/mainboard/lenovo/x230/variants/x230s/hda_verb.c new file mode 100644 index 0000000000..77919041e5 --- /dev/null +++ b/src/mainboard/lenovo/x230/variants/x230s/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ + 0x17aa2209, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x17aa2209), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x03211020), + AZALIA_PIN_CFG(0, 0x17, 0x40008000), + AZALIA_PIN_CFG(0, 0x18, 0x03a11030), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40f38205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x58560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb new file mode 100644 index 0000000000..ed1dd3c3b4 --- /dev/null +++ b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb @@ -0,0 +1,36 @@ +chip northbridge/intel/sandybridge + # Enable DisplayPort Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + + # Enable Panel as eDP and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_backlight_off_delay" = "1" # 0.1ms + register "gpu_panel_power_backlight_on_delay" = "1" # 0.1ms + register "gpu_panel_power_down_delay" = "500" # 50ms + register "gpu_panel_power_up_delay" = "2000" # 200ms + + device domain 0x0 on + subsystemid 0x17aa 0x2209 inherit + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + # X230s does not support docking + register "docking_supported" = "0" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + # Enable SATA ports 0 (HDD bay) & 1 (WWAN M.2 SATA) + register "sata_port_map" = "0x3" + + device pci 1f.0 on # LPC bridge + chip ec/lenovo/h8 # + register "config1" = "0x05" + register "config3" = "0xc4" + register "event5_enable" = "0x3c" + register "evente_enable" = "0x1d" + # X230s only has BT on wlan card + register "has_bdc_detection" = "0" + end + end # LPC Controller + end + end +end From 1085fee761b381bbc2f9d18fb9cdc8a9e1c90884 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 7 May 2020 16:04:16 -0700 Subject: [PATCH 065/405] soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4G This change sets the base for MMIO above 4G to TOUDD. It matches what is used by resource allocator if MMIO resources are allocated above 4G and also matches the expectation in northbridge.asl. This change also gets rid of the macro ABOVE_4GB_MEM_BASE_ADDRESS since it is now unused. BUG=b:149186922 TEST=Verified that kernel does not complain about MMIO windows above 4G. Signed-off-by: Furquan Shaikh Change-Id: Ibbbfbdad867735a43cf57c256bf206a3f040f383 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41155 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/include/soc/iomap.h | 1 - src/soc/intel/cannonlake/include/soc/iomap.h | 1 - .../common/block/systemagent/systemagent.c | 59 ++++++++++--------- src/soc/intel/icelake/include/soc/iomap.h | 1 - src/soc/intel/jasperlake/include/soc/iomap.h | 1 - src/soc/intel/skylake/include/soc/iomap.h | 1 - src/soc/intel/tigerlake/include/soc/iomap.h | 1 - 7 files changed, 31 insertions(+), 34 deletions(-) diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 49cdaca7ac..e79331a3e8 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -45,7 +45,6 @@ #define EARLY_I2C_BASE_ADDRESS 0xfe020000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) -#define ABOVE_4GB_MEM_BASE_ADDRESS (128ULL * GiB) #define ABOVE_4GB_MEM_BASE_SIZE (64ULL * GiB) #endif /* _SOC_APOLLOLAKE_IOMAP_H_ */ diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h index ec60d0bb8a..9d13d84d3a 100644 --- a/src/soc/intel/cannonlake/include/soc/iomap.h +++ b/src/soc/intel/cannonlake/include/soc/iomap.h @@ -54,7 +54,6 @@ #define HECI1_BASE_ADDRESS 0xfeda2000 -#define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB) #define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB) /* PTT registers */ diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index e7230bcbf4..3da837c0af 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -40,34 +40,6 @@ __weak unsigned long sa_write_acpi_tables(const struct device *dev, return current; } -/* - * This function will get above 4GB mmio enable config specific to soc. - * - * Return values: - * 0 = Above 4GB memory is not enable - * 1 = Above 4GB memory is enable - */ -static int get_enable_above_4GB_mmio(void) -{ - const struct soc_intel_common_config *common_config; - common_config = chip_get_common_soc_structure(); - - return common_config->enable_above_4GB_mmio; -} - -/* Fill MMIO resource above 4GB into GNVS */ -void sa_fill_gnvs(global_nvs_t *gnvs) -{ - if (get_enable_above_4GB_mmio()) { - gnvs->e4gm = 1; - gnvs->a4gb = ABOVE_4GB_MEM_BASE_ADDRESS; - gnvs->a4gs = ABOVE_4GB_MEM_BASE_SIZE; - printk(BIOS_DEBUG, - "PCI space above 4GB MMIO is from 0x%llx to len = 0x%llx\n", - gnvs->a4gb, gnvs->a4gs); - } -} - /* * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. @@ -124,6 +96,37 @@ static void sa_read_map_entry(struct device *dev, *result = value; } +/* + * This function will get above 4GB mmio enable config specific to soc. + * + * Return values: + * 0 = Above 4GB memory is not enable + * 1 = Above 4GB memory is enable + */ +static int get_enable_above_4GB_mmio(void) +{ + const struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); + + return common_config->enable_above_4GB_mmio; +} + +/* Fill MMIO resource above 4GB into GNVS */ +void sa_fill_gnvs(global_nvs_t *gnvs) +{ + if (!get_enable_above_4GB_mmio()) + return; + + struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); + + gnvs->e4gm = 1; + sa_read_map_entry(sa_dev, &sa_memory_map[SA_TOUUD_REG], &gnvs->a4gb); + gnvs->a4gs = ABOVE_4GB_MEM_BASE_SIZE; + printk(BIOS_DEBUG, "PCI space above 4GB MMIO is from 0x%llx to len = 0x%llx\n", + gnvs->a4gb, gnvs->a4gs); +} + + static void sa_get_mem_map(struct device *dev, uint64_t *values) { int i; diff --git a/src/soc/intel/icelake/include/soc/iomap.h b/src/soc/intel/icelake/include/soc/iomap.h index 06f68f0d60..6971a3d564 100644 --- a/src/soc/intel/icelake/include/soc/iomap.h +++ b/src/soc/intel/icelake/include/soc/iomap.h @@ -48,7 +48,6 @@ #define VTD_BASE_ADDRESS 0xFED90000 #define VTD_BASE_SIZE 0x00004000 -#define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB) #define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB) /* diff --git a/src/soc/intel/jasperlake/include/soc/iomap.h b/src/soc/intel/jasperlake/include/soc/iomap.h index f2300a2ee8..3ee06a2d2f 100644 --- a/src/soc/intel/jasperlake/include/soc/iomap.h +++ b/src/soc/intel/jasperlake/include/soc/iomap.h @@ -70,7 +70,6 @@ #define VTD_BASE_ADDRESS 0xfed90000 #define VTD_BASE_SIZE 0x00004000 -#define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB) #define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB) #define MCH_BASE_ADDRESS 0xfea80000 diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index afded553f5..a3db5c033e 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -61,7 +61,6 @@ #define PTT_TXT_BASE_ADDRESS 0xfed30800 #define PTT_PRESENT 0x00070000 -#define ABOVE_4GB_MEM_BASE_ADDRESS (128ULL * GiB) #define ABOVE_4GB_MEM_BASE_SIZE (64ULL * GiB) /* diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index 13583d5257..70f908d57d 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -76,7 +76,6 @@ #define VTD_BASE_ADDRESS 0xfed90000 #define VTD_BASE_SIZE 0x00004000 -#define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB) #define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB) From abd4714ee059b075be5cb94d332602a4ce454bc9 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 11 May 2020 19:14:58 -0700 Subject: [PATCH 066/405] soc/intel: Always advertise MMIO window above 4G in ACPI tables There should be no harm in advertising the MMIO window above 4G in ACPI tables unconditionally. OS can decide whether or not to use the window. This change removes the config option enable_above_4GB_mmio and instead adds the correct MMIO window (above 4G) details to ACPI tables always. Change-Id: Ie728f6ee7f396918e61b29ade862b57dac36cb08 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41276 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/acpi/globalnvs.asl | 5 ++--- src/soc/intel/apollolake/include/soc/nvs.h | 7 +++---- .../common/block/acpi/acpi/globalnvs.asl | 5 ++--- .../common/block/include/intelblocks/cfg.h | 1 - .../common/block/include/intelblocks/nvs.h | 7 +++---- .../common/block/systemagent/systemagent.c | 19 ------------------- src/soc/intel/skylake/acpi/globalnvs.asl | 5 ++--- src/soc/intel/skylake/include/soc/nvs.h | 7 +++---- 8 files changed, 15 insertions(+), 41 deletions(-) diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index a512a488cd..82f41b3c64 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -30,9 +30,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) EPCS, 8, // 0x2C - SGX Enabled status EMNA, 64, // 0x2D - 0x34 EPC base address ELNG, 64, // 0x35 - 0x3C EPC Length - E4GM, 8, // 0x3D - Enable above 4GB MMIO Resource - A4GB, 64, // 0x3E - 0x45 Base of above 4GB MMIO Resource - A4GS, 64, // 0x46 - 0x4D Length of above 4GB MMIO Resource + A4GB, 64, // 0x3D - 0x44 Base of above 4GB MMIO Resource + A4GS, 64, // 0x45 - 0x4C Length of above 4GB MMIO Resource /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 6ed20a0277..4668e1a07f 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -32,10 +32,9 @@ typedef struct global_nvs_t { uint8_t ecps; /* 0x2C - SGX Enabled status */ uint64_t emna; /* 0x2D - 0x34 EPC base address */ uint64_t elng; /* 0x35 - 0x3C EPC Length */ - uint8_t e4gm; /* 0x3D - Enable above 4GB MMIO Resource */ - uint64_t a4gb; /* 0x3E - 0x45 Base of above 4GB MMIO Resource */ - uint64_t a4gs; /* 0x46 - 0x4D Length of above 4GB MMIO Resource */ - uint8_t unused[178]; + uint64_t a4gb; /* 0x3D - 0x44 Base of above 4GB MMIO Resource */ + uint64_t a4gs; /* 0x45 - 0x4C Length of above 4GB MMIO Resource */ + uint8_t unused[179]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl index bd248d338b..826e718da8 100644 --- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -34,9 +34,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) U2WE, 16, // 0x2b - 0x2c USB2 Wake Enable Bitmap U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap UIOR, 8, // 0x2f - UART debug controller init on S3 resume - E4GM, 8, // 0x30 - Enable above 4GB MMIO Resource - A4GB, 64, // 0x31 - 0x38 Base of above 4GB MMIO Resource - A4GS, 64, // 0x39 - 0x40 Length of above 4GB MMIO Resource + A4GB, 64, // 0x30 - 0x37 Base of above 4GB MMIO Resource + A4GS, 64, // 0x38 - 0x3f Length of above 4GB MMIO Resource /* ChromeOS specific */ Offset (0x100), diff --git a/src/soc/intel/common/block/include/intelblocks/cfg.h b/src/soc/intel/common/block/include/intelblocks/cfg.h index 621f0586cb..be2af4aeab 100644 --- a/src/soc/intel/common/block/include/intelblocks/cfg.h +++ b/src/soc/intel/common/block/include/intelblocks/cfg.h @@ -24,7 +24,6 @@ struct soc_intel_common_config { /* PCH Thermal Trip Temperature in deg C */ uint8_t pch_thermal_trip; struct mmc_dll_params emmc_dll; - int enable_above_4GB_mmio; }; /* This function to retrieve soc config structure required by common code */ diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h index 003a608f76..e1040eac3c 100644 --- a/src/soc/intel/common/block/include/intelblocks/nvs.h +++ b/src/soc/intel/common/block/include/intelblocks/nvs.h @@ -25,10 +25,9 @@ typedef struct global_nvs_t { u16 u2we; /* 0x2b - 0x2c USB2 Wake Enable Bitmap */ u16 u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */ u8 uior; /* 0x2f - UART debug controller init on S3 resume */ - u8 e4gm; /* 0x30 - Enable above 4GB MMIO Resource */ - u64 a4gb; /* 0x31 - 0x38 Base of above 4GB MMIO Resource */ - u64 a4gs; /* 0x39 - 0x40 Length of above 4GB MMIO Resource */ - u8 unused[191]; + u64 a4gb; /* 0x30 - 0x37 Base of above 4GB MMIO Resource */ + u64 a4gs; /* 0x38 - 0x3f Length of above 4GB MMIO Resource */ + u8 unused[192]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 3da837c0af..7355817ec2 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -96,30 +96,11 @@ static void sa_read_map_entry(struct device *dev, *result = value; } -/* - * This function will get above 4GB mmio enable config specific to soc. - * - * Return values: - * 0 = Above 4GB memory is not enable - * 1 = Above 4GB memory is enable - */ -static int get_enable_above_4GB_mmio(void) -{ - const struct soc_intel_common_config *common_config; - common_config = chip_get_common_soc_structure(); - - return common_config->enable_above_4GB_mmio; -} - /* Fill MMIO resource above 4GB into GNVS */ void sa_fill_gnvs(global_nvs_t *gnvs) { - if (!get_enable_above_4GB_mmio()) - return; - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - gnvs->e4gm = 1; sa_read_map_entry(sa_dev, &sa_memory_map[SA_TOUUD_REG], &gnvs->a4gb); gnvs->a4gs = ABOVE_4GB_MEM_BASE_SIZE; printk(BIOS_DEBUG, "PCI space above 4GB MMIO is from 0x%llx to len = 0x%llx\n", diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index 8eb0f8acd4..c2584db90b 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -55,9 +55,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) EPCS, 8, // 0x43 - SGX Enabled status EMNA, 64, // 0x44 - 0x4B EPC base address ELNG, 64, // 0x4C - 0x53 EPC Length - E4GM, 8, // 0x54 - Enable above 4GB MMIO Resource - A4GB, 64, // 0x55 - 0x5C Base of above 4GB MMIO Resource - A4GS, 64, // 0x5D - 0x64 Length of above 4GB MMIO Resource + A4GB, 64, // 0x54 - 0x5B Base of above 4GB MMIO Resource + A4GS, 64, // 0x5C - 0x63 Length of above 4GB MMIO Resource /* IGD OpRegion */ Offset (0xb4), diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index b4c669b169..630ceb7a78 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -45,10 +45,9 @@ typedef struct global_nvs_t { u8 ecps; /* 0x43 - SGX Enabled status */ u64 emna; /* 0x44 - 0x4B EPC base address */ u64 elng; /* 0x4C - 0x53 EPC Length */ - u8 e4gm; /* 0x54 - Enable above 4GB MMIO Resource */ - u64 a4gb; /* 0x55 - 0x5C Base of above 4GB MMIO Resource */ - u64 a4gs; /* 0x5D - 0x64 Length of above 4GB MMIO Resource */ - u8 rsvd[79]; + u64 a4gb; /* 0x54 - 0x5B Base of above 4GB MMIO Resource */ + u64 a4gs; /* 0x5C - 0x63 Length of above 4GB MMIO Resource */ + u8 rsvd[80]; /* IGD OpRegion */ u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ From cc35f723fdcc6999ace18eae18467b900a12c07f Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 12 May 2020 16:25:31 -0700 Subject: [PATCH 067/405] soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size() This change uses cpu_phys_address_size() to calculate the size of high MMIO region instead of a macro for each SoC. This ensures that the entire range above TOUUD that can be addressed by the CPU is used for MMIO above 4G boundary. Change-Id: I01a1a86c0c65856f9f35185c2f233c58f18f5dfe Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41347 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/include/soc/iomap.h | 2 -- src/soc/intel/cannonlake/include/soc/iomap.h | 2 -- src/soc/intel/common/block/systemagent/systemagent.c | 5 +++-- src/soc/intel/icelake/include/soc/iomap.h | 2 -- src/soc/intel/jasperlake/include/soc/iomap.h | 2 -- src/soc/intel/skylake/include/soc/iomap.h | 2 -- src/soc/intel/tigerlake/include/soc/iomap.h | 3 --- 7 files changed, 3 insertions(+), 15 deletions(-) diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index e79331a3e8..5e5b40e2e1 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -45,6 +45,4 @@ #define EARLY_I2C_BASE_ADDRESS 0xfe020000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) -#define ABOVE_4GB_MEM_BASE_SIZE (64ULL * GiB) - #endif /* _SOC_APOLLOLAKE_IOMAP_H_ */ diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h index 9d13d84d3a..dc070893c8 100644 --- a/src/soc/intel/cannonlake/include/soc/iomap.h +++ b/src/soc/intel/cannonlake/include/soc/iomap.h @@ -54,8 +54,6 @@ #define HECI1_BASE_ADDRESS 0xfeda2000 -#define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB) - /* PTT registers */ #define PTT_TXT_BASE_ADDRESS 0xfed30800 #define PTT_PRESENT 0x00070000 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 7355817ec2..269236ba32 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -102,8 +103,8 @@ void sa_fill_gnvs(global_nvs_t *gnvs) struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); sa_read_map_entry(sa_dev, &sa_memory_map[SA_TOUUD_REG], &gnvs->a4gb); - gnvs->a4gs = ABOVE_4GB_MEM_BASE_SIZE; - printk(BIOS_DEBUG, "PCI space above 4GB MMIO is from 0x%llx to len = 0x%llx\n", + gnvs->a4gs = POWER_OF_2(cpu_phys_address_size()) - gnvs->a4gb; + printk(BIOS_DEBUG, "PCI space above 4GB MMIO is at 0x%llx, len = 0x%llx\n", gnvs->a4gb, gnvs->a4gs); } diff --git a/src/soc/intel/icelake/include/soc/iomap.h b/src/soc/intel/icelake/include/soc/iomap.h index 6971a3d564..6b82c19ae2 100644 --- a/src/soc/intel/icelake/include/soc/iomap.h +++ b/src/soc/intel/icelake/include/soc/iomap.h @@ -48,8 +48,6 @@ #define VTD_BASE_ADDRESS 0xFED90000 #define VTD_BASE_SIZE 0x00004000 -#define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB) - /* * I/O port address space */ diff --git a/src/soc/intel/jasperlake/include/soc/iomap.h b/src/soc/intel/jasperlake/include/soc/iomap.h index 3ee06a2d2f..c45430a02e 100644 --- a/src/soc/intel/jasperlake/include/soc/iomap.h +++ b/src/soc/intel/jasperlake/include/soc/iomap.h @@ -70,8 +70,6 @@ #define VTD_BASE_ADDRESS 0xfed90000 #define VTD_BASE_SIZE 0x00004000 -#define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB) - #define MCH_BASE_ADDRESS 0xfea80000 #define MCH_BASE_SIZE 0x8000 diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index a3db5c033e..d3fb9579fd 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -61,8 +61,6 @@ #define PTT_TXT_BASE_ADDRESS 0xfed30800 #define PTT_PRESENT 0x00070000 -#define ABOVE_4GB_MEM_BASE_SIZE (64ULL * GiB) - /* * I/O port address space */ diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index 70f908d57d..282092fade 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -76,9 +76,6 @@ #define VTD_BASE_ADDRESS 0xfed90000 #define VTD_BASE_SIZE 0x00004000 -#define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB) - - #define MCH_BASE_ADDRESS 0xfedc0000 #define MCH_BASE_SIZE 0x20000 From 2412924bc7646fc22b2cb1b9108413fa3e849082 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 7 May 2020 14:29:13 -0700 Subject: [PATCH 068/405] mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports This change enables PCIEXP_HOTPLUG to support resource allocation for TCSS TBT/USB4 ports. BUG=b:149186922 Signed-off-by: Furquan Shaikh Change-Id: I4cb820e83da40434b00198b934453805e35ef1ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/41156 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/volteer/Kconfig | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index de77633153..68759636a0 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -15,6 +15,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 + select PCIEXP_HOTPLUG select SOC_INTEL_TIGERLAKE if BOARD_GOOGLE_BASEBOARD_VOLTEER @@ -66,6 +67,20 @@ config MAX_CPUS int default 8 +# Reserving resources for PCIe Hotplug as per TGL BIOS Spec (doc #611569) +# Revision 0.7.6 Section 7.2.5.1.5 +config PCIEXP_HOTPLUG_BUSES + int + default 42 + +config PCIEXP_HOTPLUG_MEM + hex + default 0xc200000 # 194 MiB + +config PCIEXP_HOTPLUG_PREFETCH_MEM + hex + default 0x1c000000 # 448 MiB + config TPM_TIS_ACPI_INTERRUPT int default 21 # GPE0_DW0_21 (GPP_C21) From 7ac6a987d03c3dc9e39c27fda76a2e8642376817 Mon Sep 17 00:00:00 2001 From: Anil Kumar Date: Wed, 13 May 2020 13:07:26 -0700 Subject: [PATCH 069/405] mb/google/deltaur: Configure GPIO B11 as PMCALERT GPIO B11 pin should be configured as PMCALERT function. This is required for the intergrated USB-C feature to work in the SOC BUG=b:154778458, b:156288164 TEST= build and boot coreboot image on deltan. Test Type-C port enumeration on Chrome OS Signed-off-by: Anil Kumar Change-Id: I8f995901b0a50d2c74f57aba96f86134c9d569e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41378 Reviewed-by: Tim Wawrzynczak Reviewed-by: Bora Guvendik Reviewed-by: EricR Lai Tested-by: build bot (Jenkins) --- src/mainboard/google/deltaur/variants/baseboard/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/deltaur/variants/baseboard/gpio.c b/src/mainboard/google/deltaur/variants/baseboard/gpio.c index aabfdc1239..432b9f88d8 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/gpio.c +++ b/src/mainboard/google/deltaur/variants/baseboard/gpio.c @@ -76,7 +76,7 @@ static const struct pad_config gpio_table[] = { /* B10 : GPP_B10 ===> NC */ PAD_NC(GPP_B10, NONE), /* B11 : GPP_B11 ==> TBT_I2C_INT# */ - PAD_CFG_GPI_APIC(GPP_B11, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* B12 : GPP_B12 ==> SIO_SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PCH_PLTRST# */ From 1ca24332c4ad8a9e466139d090500b0a523d56c8 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 13 May 2020 11:38:35 -0600 Subject: [PATCH 070/405] nb/intel/sandybridge: add resources during read_resources() The chipset code was incorrectly adding memory resources to the domain device after resource allocation occurred. It's not possible to get the correct view of the address space, and it's generally incorrect to not add resources during read_resources(). Fix the order by hanging the resources off of the host bridge device. Change-Id: I8a7081020be43da055b7de5a56dd97a7b5a9f09c Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/41364 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Angel Pons Reviewed-by: Furquan Shaikh Reviewed-by: Nico Huber --- .../intel/sandybridge/northbridge.c | 104 ++++++++---------- 1 file changed, 48 insertions(+), 56 deletions(-) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 7a6372c207..c1cdea5428 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -71,6 +71,34 @@ static int get_pcie_bar(u32 *base) return 0; } +static const char *northbridge_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + switch (dev->path.pci.devfn) { + case PCI_DEVFN(0, 0): + return "MCHC"; + } + + return NULL; +} + +/* + * TODO We could determine how many PCIe busses we need in the bar. + * For now, that number is hardcoded to a max of 64. + */ +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .scan_bus = pci_domain_scan_bus, + .write_acpi_tables = northbridge_write_acpi_tables, + .acpi_name = northbridge_acpi_name, +}; + static void add_fixed_resources(struct device *dev, int index) { mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10); @@ -99,13 +127,23 @@ static void add_fixed_resources(struct device *dev, int index) } } -static void pci_domain_set_resources_sandybridge(struct device *dev) +static void mc_read_resources(struct device *dev) { + u32 pcie_config_base; + int buses; uint64_t tom, me_base, touud; uint32_t tseg_base, uma_size, tolud; uint16_t ggc; unsigned long long tomk; + pci_dev_read_resources(dev); + + buses = get_pcie_bar(&pcie_config_base); + if (buses) { + struct resource *resource = new_resource(dev, PCIEXBAR); + mmconf_resource_init(resource, pcie_config_base, buses); + } + /* Total Memory 2GB example: * * 00000000 0000MB-1992MB 1992MB RAM (writeback) @@ -132,28 +170,26 @@ static void pci_domain_set_resources_sandybridge(struct device *dev) * 14fe00000 5368MB TOUUD */ - struct device *mch = pcidev_on_root(0, 0); - /* Top of Upper Usable DRAM, including remap */ - touud = pci_read_config32(mch, TOUUD + 4); + touud = pci_read_config32(dev, TOUUD + 4); touud <<= 32; - touud |= pci_read_config32(mch, TOUUD); + touud |= pci_read_config32(dev, TOUUD); /* Top of Lower Usable DRAM */ - tolud = pci_read_config32(mch, TOLUD); + tolud = pci_read_config32(dev, TOLUD); /* Top of Memory - does not account for any UMA */ - tom = pci_read_config32(mch, TOM + 4); + tom = pci_read_config32(dev, TOM + 4); tom <<= 32; - tom |= pci_read_config32(mch, TOM); + tom |= pci_read_config32(dev, TOM); printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", touud, tolud, tom); /* ME UMA needs excluding if total memory < 4GB */ - me_base = pci_read_config32(mch, MESEG_BASE + 4); + me_base = pci_read_config32(dev, MESEG_BASE + 4); me_base <<= 32; - me_base |= pci_read_config32(mch, MESEG_BASE); + me_base |= pci_read_config32(dev, MESEG_BASE); printk(BIOS_DEBUG, "MEBASE 0x%llx\n", me_base); @@ -172,7 +208,7 @@ static void pci_domain_set_resources_sandybridge(struct device *dev) } /* Graphics memory comes next */ - ggc = pci_read_config16(mch, GGC); + ggc = pci_read_config16(dev, GGC); if (!(ggc & 2)) { printk(BIOS_DEBUG, "IGD decoded, subtracting "); @@ -192,7 +228,7 @@ static void pci_domain_set_resources_sandybridge(struct device *dev) } /* Calculate TSEG size from its base which must be below GTT */ - tseg_base = pci_read_config32(mch, TSEGMB); + tseg_base = pci_read_config32(dev, TSEGMB); uma_size = (uma_memory_base - tseg_base) >> 10; tomk -= uma_size; uma_memory_base = tomk * 1024ULL; @@ -217,50 +253,6 @@ static void pci_domain_set_resources_sandybridge(struct device *dev) } add_fixed_resources(dev, 6); - - assign_resources(dev->link_list); -} - -static const char *northbridge_acpi_name(const struct device *dev) -{ - if (dev->path.type == DEVICE_PATH_DOMAIN) - return "PCI0"; - - if (dev->path.type != DEVICE_PATH_PCI) - return NULL; - - switch (dev->path.pci.devfn) { - case PCI_DEVFN(0, 0): - return "MCHC"; - } - - return NULL; -} - -/* - * TODO We could determine how many PCIe busses we need in the bar. - * For now, that number is hardcoded to a max of 64. - */ -static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources_sandybridge, - .scan_bus = pci_domain_scan_bus, - .write_acpi_tables = northbridge_write_acpi_tables, - .acpi_name = northbridge_acpi_name, -}; - -static void mc_read_resources(struct device *dev) -{ - u32 pcie_config_base; - int buses; - - pci_dev_read_resources(dev); - - buses = get_pcie_bar(&pcie_config_base); - if (buses) { - struct resource *resource = new_resource(dev, PCIEXBAR); - mmconf_resource_init(resource, pcie_config_base, buses); - } } static void northbridge_dmi_init(struct device *dev) From ffa5e8ddcfb099eff56eb8e6cd70ca4bd0b2545d Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 13 May 2020 13:00:49 -0700 Subject: [PATCH 071/405] nb/intel/i440bx: add resources during read_resources() The chipset code was incorrectly adding memory resources to the domain device after resource allocation occurred. It's not possible to get the correct view of the address space, and it's generally incorrect to not add resources during read_resources(). This change fixes the order by adding resources in read_resources(). Signed-off-by: Furquan Shaikh Change-Id: I84c1ba8645b548248a8bb8bf5bc4953d3be12475 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41368 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Reviewed-by: Keith Hui Reviewed-by: Aaron Durbin --- src/northbridge/intel/i440bx/northbridge.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index aefd026bfc..2659288070 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -27,11 +27,13 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x7190, }; -static void i440bx_domain_set_resources(struct device *dev) +static void i440bx_domain_read_resources(struct device *dev) { struct device *mc_dev; uint32_t pci_tolm; + pci_domain_read_resources(dev); + pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev->link_list->children; if (mc_dev) { @@ -62,12 +64,11 @@ static void i440bx_domain_set_resources(struct device *dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); } - assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = i440bx_domain_set_resources, + .read_resources = i440bx_domain_read_resources, + .set_resources = pci_domain_set_resources, .scan_bus = pci_domain_scan_bus, }; From fc752b69183e0c2b37fa50f03d89aeb59c876c4f Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 13 May 2020 12:14:11 -0700 Subject: [PATCH 072/405] soc/amd/stoneyridge: add resources during read_resources() The chipset code was incorrectly adding memory resources to the domain device after resource allocation occurred. It's not possible to get the correct view of the address space, and it's generally incorrect to not add resources during read_resources(). This change fixes the order by adding resources during read_resources(). Signed-off-by: Furquan Shaikh Change-Id: I532f508936d5ec154cbcb3538949316ae4851105 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41369 Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/amd/stoneyridge/chip.c | 4 ++-- src/soc/amd/stoneyridge/include/soc/northbridge.h | 2 +- src/soc/amd/stoneyridge/northbridge.c | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index f3c330c8a3..41fcafbab9 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -96,8 +96,8 @@ const char *soc_acpi_name(const struct device *dev) }; struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = domain_set_resources, + .read_resources = domain_read_resources, + .set_resources = pci_domain_set_resources, .enable_resources = domain_enable_resources, .scan_bus = pci_domain_scan_bus, .acpi_name = soc_acpi_name, diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 0e0b2c30f3..3b5fd22969 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -84,7 +84,7 @@ #define CMP_CAP_MASK 0xff void domain_enable_resources(struct device *dev); -void domain_set_resources(struct device *dev); +void domain_read_resources(struct device *dev); void fam15_finalize(void *chip_info); void set_warm_reset_flag(void); int is_warm_reset(void); diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 6c266232d8..c6fdc60073 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -414,7 +414,7 @@ void domain_enable_resources(struct device *dev) do_agesawrapper(AMD_INIT_MID, "amdinitmid"); } -void domain_set_resources(struct device *dev) +void domain_read_resources(struct device *dev) { uint64_t uma_base = get_uma_base(); uint32_t uma_size = get_uma_size(); @@ -424,6 +424,8 @@ void domain_set_resources(struct device *dev) uint64_t high_mem_useable; int idx = 0x10; + pci_domain_read_resources(dev); + /* 0x0 -> 0x9ffff */ ram_resource(dev, idx++, 0, 0xa0000 / KiB); @@ -462,8 +464,6 @@ void domain_set_resources(struct device *dev) uma_size / KiB); } } - - assign_resources(dev->link_list); } /********************************************************************* From 1dac6058723efa8b2a1ea3bfff8443e39e10fdf2 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 13 May 2020 10:46:17 -0700 Subject: [PATCH 073/405] aspeed/ast2050: Fix when resources are added This change moves adding of resources to read_resources() instead of set_resources(). Signed-off-by: Furquan Shaikh Change-Id: I7d5e4aa0fc28dd35f774957ef303d8854aa07913 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41370 Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/drivers/aspeed/ast2050/ast2050.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/drivers/aspeed/ast2050/ast2050.c b/src/drivers/aspeed/ast2050/ast2050.c index 5a1d92d6a3..5cb7198c29 100644 --- a/src/drivers/aspeed/ast2050/ast2050.c +++ b/src/drivers/aspeed/ast2050/ast2050.c @@ -11,13 +11,13 @@ #include "../common/aspeed_coreboot.h" #include "../common/ast_drv.h" -static void aspeed_ast2050_set_resources(struct device *dev) +static void aspeed_ast2050_read_resources(struct device *dev) { /* Reserve VGA regions */ mmio_resource(dev, 3, 0xa0000 >> 10, 0x1ffff >> 10); - /* Run standard resource set routine */ - pci_dev_set_resources(dev); + /* Run standard resource read routine */ + pci_dev_read_resources(dev); } static void aspeed_ast2050_init(struct device *dev) @@ -52,8 +52,8 @@ static void aspeed_ast2050_init(struct device *dev) } static struct device_operations aspeed_ast2050_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = aspeed_ast2050_set_resources, + .read_resources = aspeed_ast2050_read_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = aspeed_ast2050_init, }; From bcac1cbacd2613e02c865182f445a02e6cdf45e7 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 13 May 2020 12:19:15 -0700 Subject: [PATCH 074/405] soc/nvidia/tegra124: add resources during read_resources() The chipset code was incorrectly adding memory resources to the domain device after resource allocation occurred. It's not possible to get the correct view of the address space, and it's generally incorrect to not add resources during read_resources(). This change fixes the order by adding resources in read_resources(). Signed-off-by: Furquan Shaikh Change-Id: I16f0439679471366723a0084918a20cd95834831 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41372 Reviewed-by: Angel Pons Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/nvidia/tegra124/soc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index ffc8771d7d..00c7009e9a 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -14,7 +14,7 @@ * Will break if we get 2. Sigh. * We assume it's all multiples of MiB for MMUs sake. */ -static void soc_enable(struct device *dev) +static void soc_read_resources(struct device *dev) { u32 lcdbase = fb_base_mb(); unsigned long fb_size = FB_SIZE_MB; @@ -41,9 +41,8 @@ static void soc_init(struct device *dev) } static struct device_operations soc_ops = { - .read_resources = noop_read_resources, + .read_resources = soc_read_resources, .set_resources = noop_set_resources, - .enable_resources = soc_enable, .init = soc_init, }; From d6973e811b925901e045f3f229a45c16d8dcbcca Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 13 May 2020 12:21:06 -0700 Subject: [PATCH 075/405] soc/samsung/exynos5250: add resources during read_resources() The chipset code was incorrectly adding memory resources to the domain device after resource allocation occurred. It's not possible to get the correct view of the address space, and it's generally incorrect to not add resources during read_resources(). This change fixes the order by adding resources in read_resources(). Signed-off-by: Furquan Shaikh Change-Id: I419be7edf289636b24b9a7d6c390866ade638de3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41373 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/samsung/exynos5250/cpu.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index 514e451ede..6a0251d36f 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -95,14 +95,20 @@ static void cpu_enable(struct device *dev) unsigned long fb_size = FB_SIZE_KB * KiB; u32 lcdbase = get_fb_base_kb() * KiB; - ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB); - mmio_resource(dev, 1, lcdbase / KiB, DIV_ROUND_UP(fb_size, KiB)); - exynos_displayport_init(dev, lcdbase, fb_size); set_cpu_id(); } +static void cpu_read_resources(struct device *dev) +{ + unsigned long fb_size = FB_SIZE_KB * KiB; + u32 lcdbase = get_fb_base_kb() * KiB; + + ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB); + mmio_resource(dev, 1, lcdbase / KiB, DIV_ROUND_UP(fb_size, KiB)); +} + static void cpu_init(struct device *dev) { printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", @@ -110,7 +116,7 @@ static void cpu_init(struct device *dev) } static struct device_operations cpu_ops = { - .read_resources = noop_read_resources, + .read_resources = cpu_read_resources, .set_resources = noop_set_resources, .enable_resources = cpu_enable, .init = cpu_init, From cd6804cd16630ce672df7d8e52b7b4c628e4a3da Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 13 May 2020 12:22:53 -0700 Subject: [PATCH 076/405] samsung/exynos5420: add resources during read_resources() The chipset code was incorrectly adding memory resources to the domain device after resource allocation occurred. It's not possible to get the correct view of the address space, and it's generally incorrect to not add resources during read_resources(). This change fixes the order by adding resources in read_resources(). Signed-off-by: Furquan Shaikh Change-Id: I49ce6ac88c4cb7cd05ff9d78133593ce97304596 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41374 Reviewed-by: Angel Pons Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/samsung/exynos5420/cpu.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index 8a07552cf6..6d1418a545 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -97,8 +97,6 @@ static void exynos_displayport_init(struct device *dev, u32 lcdbase, dcache_clean_invalidate_by_mva((void *)lower, upper - lower); mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF); - - mmio_resource(dev, 1, lcdbase/KiB, DIV_ROUND_UP(fb_size, KiB)); } static void tps65090_thru_ec_fet_disable(int index) @@ -117,9 +115,6 @@ static void cpu_enable(struct device *dev) unsigned long fb_size = FB_SIZE_KB * KiB; u32 lcdbase = get_fb_base_kb() * KiB; - ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB); - mmio_resource(dev, 1, lcdbase / KiB, DIV_ROUND_UP(fb_size, KiB)); - /* * Disable LCD FETs before we do anything with the display. * FIXME(dhendrix): This is a gross hack and should be done @@ -133,6 +128,15 @@ static void cpu_enable(struct device *dev) set_cpu_id(); } +static void cpu_read_resources(struct device *dev) +{ + unsigned long fb_size = FB_SIZE_KB * KiB; + u32 lcdbase = get_fb_base_kb() * KiB; + + ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB); + mmio_resource(dev, 1, lcdbase / KiB, DIV_ROUND_UP(fb_size, KiB)); +} + static void cpu_init(struct device *dev) { printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", @@ -140,7 +144,7 @@ static void cpu_init(struct device *dev) } static struct device_operations cpu_ops = { - .read_resources = noop_read_resources, + .read_resources = cpu_read_resources, .set_resources = noop_set_resources, .enable_resources = cpu_enable, .init = cpu_init, From e8ee6f975b255c41102d1549ebdb69cfb2aa7850 Mon Sep 17 00:00:00 2001 From: vsujithk Date: Mon, 27 Jan 2020 17:47:31 +0530 Subject: [PATCH 077/405] sc7180: GPIO: Add I2S configuration for sc7180 Configuring GPIO Pins as I2S mode for Audio speaker. Change-Id: I681aa6d0d57671b0fd9b7bc88de6f2cc202a7af0 Signed-off-by: V Sujith Kumar Reddy Reviewed-on: https://review.coreboot.org/c/coreboot/+/38593 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/mainboard/google/trogdor/board.h | 4 +++- src/mainboard/google/trogdor/chromeos.c | 4 ++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/trogdor/board.h b/src/mainboard/google/trogdor/board.h index fa2fb9f5de..63d03db51c 100644 --- a/src/mainboard/google/trogdor/board.h +++ b/src/mainboard/google/trogdor/board.h @@ -11,7 +11,9 @@ #define GPIO_AP_EC_INT GPIO(94) #define GPIO_AP_SUSPEND GPIO(20) #define GPIO_WP_STATE GPIO(42) -#define GPIO_H1_AP_INT GPIO(21) +#define GPIO_H1_AP_INT (CONFIG(TROGDOR_REV0) ? GPIO(21) : GPIO(42)) +#define GPIO_SD_CD_L GPIO(69) +#define GPIO_AMP_ENABLE GPIO(23) void setup_chromeos_gpios(void); diff --git a/src/mainboard/google/trogdor/chromeos.c b/src/mainboard/google/trogdor/chromeos.c index 985ba0f85e..324d6ca8b9 100644 --- a/src/mainboard/google/trogdor/chromeos.c +++ b/src/mainboard/google/trogdor/chromeos.c @@ -28,6 +28,10 @@ void fill_lb_gpios(struct lb_gpios *gpios) "EC interrupt"}, {GPIO_H1_AP_INT.addr, ACTIVE_LOW, gpio_get(GPIO_H1_AP_INT), "TPM interrupt"}, + {GPIO_SD_CD_L.addr, ACTIVE_LOW, gpio_get(GPIO_SD_CD_L), + "SD card detect"}, + {GPIO_AMP_ENABLE.addr, ACTIVE_HIGH, gpio_get(GPIO_AMP_ENABLE), + "speaker enable"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); From 9a41af60c4f570e4621ce3c1a351e9316f2b3b93 Mon Sep 17 00:00:00 2001 From: Shaik Sajida Bhanu Date: Mon, 13 Apr 2020 18:55:52 +0530 Subject: [PATCH 078/405] trogdor: Update pull for Sd-card detect pin Configuring pull for SD-card detect pin. Without this SD-card detection is not working as expected Signed-off-by: Shaik Sajida Bhanu Change-Id: I77bf355a049224784a160defa6bee66d0f9ceb75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40534 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/mainboard/google/trogdor/chromeos.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/trogdor/chromeos.c b/src/mainboard/google/trogdor/chromeos.c index 324d6ca8b9..9360928a1e 100644 --- a/src/mainboard/google/trogdor/chromeos.c +++ b/src/mainboard/google/trogdor/chromeos.c @@ -16,7 +16,9 @@ void setup_chromeos_gpios(void) gpio_input_pullup(GPIO_AP_EC_INT); gpio_output(GPIO_AP_SUSPEND, 1); gpio_input(GPIO_WP_STATE); - gpio_input_pullup(GPIO_H1_AP_INT); + gpio_input_pullup(GPIO_SD_CD_L); + gpio_input_irq(GPIO_H1_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP); + gpio_output(GPIO_AMP_ENABLE, 0); } void fill_lb_gpios(struct lb_gpios *gpios) From ecc4c4e5f141543daa6c96826f3e6b5dcfa2a554 Mon Sep 17 00:00:00 2001 From: Rajat Jain Date: Wed, 13 May 2020 14:42:29 -0700 Subject: [PATCH 079/405] acpigen_ps2_keybd: Add keymap for Power key Power key is a special non-matrixed key. Chrome /powerd only listens to the keyboard device for this key, so add its keymap. BUG=b:155941390 TEST=Test that power key generates KEY_POWER in linux evtest Change-Id: I570602d9febcb5c17e58761f2004ee88be16c27f Signed-off-by: Rajat Jain Reviewed-on: https://review.coreboot.org/c/coreboot/+/41382 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/acpi/acpigen_ps2_keybd.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/acpi/acpigen_ps2_keybd.c b/src/acpi/acpigen_ps2_keybd.c index 78eb55ed47..1379a89c18 100644 --- a/src/acpi/acpigen_ps2_keybd.c +++ b/src/acpi/acpigen_ps2_keybd.c @@ -168,6 +168,8 @@ static uint32_t rest_of_keymaps[] = { KEYMAP(0xd0, KEY_DOWN), KEYMAP(0xcd, KEY_RIGHT), KEYMAP(0xc8, KEY_UP), + /* Power Key */ + KEYMAP(0xde, KEY_POWER), }; static void ssdt_generate_physmap(struct acpi_dp *dp, uint8_t num_top_row_keys, From 9e8dd06cd4adc8c5bae267251d3a5532737d05e4 Mon Sep 17 00:00:00 2001 From: Alex Levin Date: Tue, 12 May 2020 21:24:23 -0700 Subject: [PATCH 080/405] mb/google/volteer: Add delay to WWAN GPIO init sequence Based on Fibocom HW user manual RESET should be deasserted at least 20ms after the power on pin. The design for the reset pin is open drain connected to a pull up, so it is set to high-Z (configured as GPIO in) after 20ms. BUG=b:152013143 BRANCH=none TEST=traced the signals using a scope to verify timing is met. Signed-off-by: Alex Levin Change-Id: I7c947d1bc4cce1f97383a2f2c254986e182661c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41356 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- .../google/volteer/variants/baseboard/gpio.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index 2fbfced1a9..bff7e3c3ad 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -265,10 +265,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_F9, NONE), /* F10 : GPPF10_STRAP */ PAD_NC(GPP_F10, DN_20K), - /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ - PAD_CFG_GPO(GPP_F11, 1, DEEP), /* F12 : GSXDOUT ==> WWAN_RST_ODL */ - PAD_CFG_GPO(GPP_F12, 1, DEEP), + PAD_CFG_GPI(GPP_F12, NONE, DEEP), /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ PAD_CFG_GPO(GPP_F13, 1, DEEP), /* F14 : GSXDIN ==> SAR0_INT_L */ @@ -435,6 +433,14 @@ static const struct pad_config early_gpio_table[] = { /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ PAD_CFG_GPO(GPP_E12, 1, DEEP), + /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_F11, 1, DEEP), + + /* F12 : GSXDOUT ==> WWAN_RST_ODL + To meet timing constrains - drive reset low. + Deasserted in ramstage. */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H11, 1, DEEP), }; From 6ad701054230e25fa9b2afe414ca8da6d5a626ee Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Tue, 12 May 2020 21:28:53 +0530 Subject: [PATCH 081/405] soc/intel: Correct comment on HMRFPO_ENABLE HECI command Correct comment on HMRFPO_ENABLE flow for CSE Lite SKU. In order to place CSE into SECOVER_MEI_MSG mode, below procedure has to be followed. 1. Ensure CSE boots from RO(BP1). - Set CSE's next boot partition to RO - Issue GLOBAL_RESET HECI command to reset the system 2. Send HMRFPO_ENABLE command to CSE. Further, no reset is required. TEST=Verified on hatch Signed-off-by: Sridhar Siricilla Change-Id: I213e02ba3898194fa6c8fe38fab34b5c19f25aa1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41340 Reviewed-by: Furquan Shaikh Reviewed-by: Rizwan Qureshi Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/include/intelblocks/cse.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 103323b7cc..588d3eb79c 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -130,10 +130,10 @@ int cse_request_global_reset(enum rst_req_type rst_type); /* * Sends HMRFPO_ENABLE command. * HMRFPO - Host ME Region Flash Protection Override. - * For CSE Firmware SKU Custom, procedure to place CSE in HMRFPO (SECOVER_MEI_MSG) mode: - * 1. Ensure CSE boots from BP1(RO). - * - Send set_next_boot_partition(BP1) - * - Issue CSE Only Reset + * For CSE Lite SKU, procedure to place CSE in HMRFPO (SECOVER_MEI_MSG) mode: + * 1. Ensure CSE boots from RO(BP1). + * - Set CSE's next boot partition to RO + * - Issue GLOBAL_RESET command to reset the system * 2. Send HMRFPO_ENABLE command to CSE. Further, no reset is required. * * The HMRFPO mode prevents CSE to execute SPI I/O cycles to CSE region, and unlocks From 6191b85f8770ed807a5954339aef6c99609d7660 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Thu, 9 Apr 2020 11:37:05 -0600 Subject: [PATCH 082/405] drivers/i2c/designware: Check if the device is powered If the device doesn't return a valid component type, that means the device is non-functional. The dw_i2c_regs had invalid offsets for the version field. I got the correct value from the DesignWare DW_apb_i2c Databook v2.02a. It also matches what the Picasso PPR says. I also print out the version field of the controller. BUG=b:153001807 BRANCH=none TEST=Tested on PSP where I2C is non functional. Also tested on trembyle and verified i2c was initialized. Saw the following in the logs I2C bus 2 version 0x3132322a Signed-off-by: Raul E Rangel Change-Id: If5527972508e0f4b35cc9ecdb1491b1ce85ff3af Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2144540 Reviewed-by: Simon Glass Reviewed-by: Furquan Shaikh Tested-by: Simon Glass Reviewed-on: https://review.coreboot.org/c/coreboot/+/40870 Reviewed-by: Furquan Shaikh Reviewed-by: Angel Pons Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/drivers/i2c/designware/dw_i2c.c | 104 ++++++++++++++++------------ 1 file changed, 58 insertions(+), 46 deletions(-) diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index 21a68af24f..00865e3f6e 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -91,54 +91,58 @@ enum { /* I2C Controller MMIO register space */ struct dw_i2c_regs { - uint32_t control; - uint32_t target_addr; - uint32_t slave_addr; - uint32_t master_addr; - uint32_t cmd_data; - uint32_t ss_scl_hcnt; - uint32_t ss_scl_lcnt; - uint32_t fs_scl_hcnt; - uint32_t fs_scl_lcnt; - uint32_t hs_scl_hcnt; - uint32_t hs_scl_lcnt; - uint32_t intr_stat; - uint32_t intr_mask; - uint32_t raw_intr_stat; - uint32_t rx_thresh; - uint32_t tx_thresh; - uint32_t clear_intr; - uint32_t clear_rx_under_intr; - uint32_t clear_rx_over_intr; - uint32_t clear_tx_over_intr; - uint32_t clear_rd_req_intr; - uint32_t clear_tx_abrt_intr; - uint32_t clear_rx_done_intr; - uint32_t clear_activity_intr; - uint32_t clear_stop_det_intr; - uint32_t clear_start_det_intr; - uint32_t clear_gen_call_intr; - uint32_t enable; - uint32_t status; - uint32_t tx_level; - uint32_t rx_level; - uint32_t sda_hold; - uint32_t tx_abort_source; - uint32_t slv_data_nak_only; - uint32_t dma_cr; - uint32_t dma_tdlr; - uint32_t dma_rdlr; - uint32_t sda_setup; - uint32_t ack_general_call; - uint32_t enable_status; - uint32_t fs_spklen; - uint32_t hs_spklen; - uint32_t clr_restart_det; - uint32_t comp_param1; - uint32_t comp_version; - uint32_t comp_type; + uint32_t control; /* 0x0 */ + uint32_t target_addr; /* 0x4 */ + uint32_t slave_addr; /* 0x8 */ + uint32_t master_addr; /* 0xc */ + uint32_t cmd_data; /* 0x10 */ + uint32_t ss_scl_hcnt; /* 0x14 */ + uint32_t ss_scl_lcnt; /* 0x18 */ + uint32_t fs_scl_hcnt; /* 0x1c */ + uint32_t fs_scl_lcnt; /* 0x20 */ + uint32_t hs_scl_hcnt; /* 0x24 */ + uint32_t hs_scl_lcnt; /* 0x28 */ + uint32_t intr_stat; /* 0x2c */ + uint32_t intr_mask; /* 0x30 */ + uint32_t raw_intr_stat; /* 0x34 */ + uint32_t rx_thresh; /* 0x38 */ + uint32_t tx_thresh; /* 0x3c */ + uint32_t clear_intr; /* 0x40 */ + uint32_t clear_rx_under_intr; /* 0x44 */ + uint32_t clear_rx_over_intr; /* 0x48 */ + uint32_t clear_tx_over_intr; /* 0x4c */ + uint32_t clear_rd_req_intr; /* 0x50 */ + uint32_t clear_tx_abrt_intr; /* 0x54 */ + uint32_t clear_rx_done_intr; /* 0x58 */ + uint32_t clear_activity_intr; /* 0x5c */ + uint32_t clear_stop_det_intr; /* 0x60 */ + uint32_t clear_start_det_intr; /* 0x64 */ + uint32_t clear_gen_call_intr; /* 0x68 */ + uint32_t enable; /* 0x6c */ + uint32_t status; /* 0x70 */ + uint32_t tx_level; /* 0x74 */ + uint32_t rx_level; /* 0x78 */ + uint32_t sda_hold; /* 0x7c */ + uint32_t tx_abort_source; /* 0x80 */ + uint32_t slv_data_nak_only; /* 0x84 */ + uint32_t dma_cr; /* 0x88 */ + uint32_t dma_tdlr; /* 0x8c */ + uint32_t dma_rdlr; /* 0x90 */ + uint32_t sda_setup; /* 0x94 */ + uint32_t ack_general_call; /* 0x98 */ + uint32_t enable_status; /* 0x9c */ + uint32_t fs_spklen; /* 0xa0 */ + uint32_t hs_spklen; /* 0xa4 */ + uint32_t clr_restart_det; /* 0xa8 */ + uint32_t reserved[18]; /* 0xac - 0xf0 */ + uint32_t comp_param1; /* 0xf4 */ + uint32_t comp_version; /* 0xf8 */ + uint32_t comp_type; /* 0xfc */ } __packed; +/* Constant value defined in the DesignWare DW_apb_i2c Databook. */ +#define DW_I2C_COMP_TYPE 0x44570140 + static const struct i2c_descriptor { enum i2c_speed speed; struct freq freq; @@ -717,6 +721,14 @@ int dw_i2c_init(unsigned int bus, const struct dw_i2c_bus_config *bcfg) return -1; } + if (read32(®s->comp_type) != DW_I2C_COMP_TYPE) { + printk(BIOS_ERR, "I2C bus %u has unknown type 0x%x.\n", bus, + read32(®s->comp_type)); + return -1; + } + + printk(BIOS_DEBUG, "I2C bus %u version 0x%x\n", bus, read32(®s->comp_version)); + if (dw_i2c_disable(regs) < 0) { printk(BIOS_ERR, "I2C timeout disabling bus %u\n", bus); return -1; From fba08308f086d7b77f95554df094288fd55903d1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 13 Apr 2020 20:51:32 +0200 Subject: [PATCH 083/405] superio/smsc/sch5545: add support for SMSC SCH5545 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SMSC SCH5545 is very similar to the publicly available datasheet for the SCH5627. TEST=use PS2 keyboard and mouse, serial port, runtime registers and Embedded Memory Interface on Dell Optiplex 9010 Signed-off-by: Michał Żygowski Change-Id: If8a60d5802675f09b08014ed583d2d8afa29fc04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40350 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/superio/smsc/Makefile.inc | 1 + src/superio/smsc/sch5545/Kconfig | 4 + src/superio/smsc/sch5545/Makefile.inc | 10 + .../smsc/sch5545/acpi/resource_helpers.asl | 412 ++++++++++++ src/superio/smsc/sch5545/acpi/superio.asl | 589 ++++++++++++++++++ src/superio/smsc/sch5545/sch5545.h | 299 +++++++++ src/superio/smsc/sch5545/sch5545_early_init.c | 179 ++++++ src/superio/smsc/sch5545/sch5545_emi.c | 214 +++++++ src/superio/smsc/sch5545/sch5545_emi.h | 167 +++++ src/superio/smsc/sch5545/superio.c | 301 +++++++++ 10 files changed, 2176 insertions(+) create mode 100644 src/superio/smsc/sch5545/Kconfig create mode 100644 src/superio/smsc/sch5545/Makefile.inc create mode 100644 src/superio/smsc/sch5545/acpi/resource_helpers.asl create mode 100644 src/superio/smsc/sch5545/acpi/superio.asl create mode 100644 src/superio/smsc/sch5545/sch5545.h create mode 100644 src/superio/smsc/sch5545/sch5545_early_init.c create mode 100644 src/superio/smsc/sch5545/sch5545_emi.c create mode 100644 src/superio/smsc/sch5545/sch5545_emi.h create mode 100644 src/superio/smsc/sch5545/superio.c diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index 17bdaea6af..9442a9efde 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -16,3 +16,4 @@ subdirs-y += mec1308 subdirs-y += smscsuperio subdirs-y += sio1036 subdirs-y += sch4037 +subdirs-y += sch5545 diff --git a/src/superio/smsc/sch5545/Kconfig b/src/superio/smsc/sch5545/Kconfig new file mode 100644 index 0000000000..c6b9bae14a --- /dev/null +++ b/src/superio/smsc/sch5545/Kconfig @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config SUPERIO_SMSC_SCH5545 + bool diff --git a/src/superio/smsc/sch5545/Makefile.inc b/src/superio/smsc/sch5545/Makefile.inc new file mode 100644 index 0000000000..2a59f8f529 --- /dev/null +++ b/src/superio/smsc/sch5545/Makefile.inc @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-$(CONFIG_SUPERIO_SMSC_SCH5545) += sch5545_early_init.c +romstage-$(CONFIG_SUPERIO_SMSC_SCH5545) += sch5545_early_init.c + +bootblock-$(CONFIG_SUPERIO_SMSC_SCH5545) += sch5545_emi.c +romstage-$(CONFIG_SUPERIO_SMSC_SCH5545) += sch5545_emi.c +ramstage-$(CONFIG_SUPERIO_SMSC_SCH5545) += sch5545_emi.c + +ramstage-$(CONFIG_SUPERIO_SMSC_SCH5545) += superio.c diff --git a/src/superio/smsc/sch5545/acpi/resource_helpers.asl b/src/superio/smsc/sch5545/acpi/resource_helpers.asl new file mode 100644 index 0000000000..818f470534 --- /dev/null +++ b/src/superio/smsc/sch5545/acpi/resource_helpers.asl @@ -0,0 +1,412 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Helper package for determining IO, DMA, IRQ location according to LDN */ +Name (DCAT, Package (0x10) { + 0x07, /* UARTA */ + 0x08, /* UARTB */ + 0x11, /* LPT */ + 0x0B, /* Floppy */ + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + One, /* KBC */ + 0xFF, + 0xFF, + 0xFF, + One, /* KBC */ + 0xFF +}) + +Method (CGLD, 1, NotSerialized) +{ + Return (DerefOf (DCAT [Arg0])) +} + +/* Return Parallel port mode*/ +Method (LPTM, 1, NotSerialized) +{ + ENTER_CONFIG_MODE (CGLD (Arg0)) + Local0 = (OPT0 & 0x02) + EXIT_CONFIG_MODE () + Return (Local0) +} + +/* Device Status */ +Method (DSTA, 1, NotSerialized) +{ + ENTER_CONFIG_MODE (CGLD (Arg0)) + Local0 = PNP_DEVICE_ACTIVE + If (Local0 == 0xFF) + { + Return (Zero) + } + + Local0 &= One + If (Arg0 < 0x10) + { + IOST |= (Local0 << Arg0) + } + + If (Local0) + { + Return (DEVICE_PRESENT_ACTIVE) + } + ElseIf ((One << Arg0) & IOST) + { + Return (DEVICE_PRESENT_INACTIVE) + } + Else + { + Return (Zero) + } + + EXIT_CONFIG_MODE () +} + +Method (DCNT, 2, NotSerialized) +{ + ENTER_CONFIG_MODE (CGLD (Arg0)) + PNP_DEVICE_ACTIVE = Arg1 + EXIT_CONFIG_MODE () +} + +/* Resource templates for SIO LDNs */ +Name (CRS1, ResourceTemplate () +{ + IO (Decode16, + 0x0000, + 0x0000, + 0x01, + 0x00, + _Y16) + IRQ (Edge, ActiveHigh, Exclusive, _Y14) {} + DMA (Compatibility, NotBusMaster, Transfer8, _Y15) {} +}) + +CreateWordField (CRS1, \_SB.PCI0.LPCB.SIO1._Y14._INT, IRQM) +CreateByteField (CRS1, \_SB.PCI0.LPCB.SIO1._Y15._DMA, DMAM) +CreateWordField (CRS1, \_SB.PCI0.LPCB.SIO1._Y16._MIN, IO11) +CreateWordField (CRS1, \_SB.PCI0.LPCB.SIO1._Y16._MAX, IO12) +CreateByteField (CRS1, \_SB.PCI0.LPCB.SIO1._Y16._LEN, LEN1) + +Name (CRS2, ResourceTemplate () +{ + IO (Decode16, + 0x0000, + 0x0000, + 0x01, + 0x00, + _Y19) + IO (Decode16, + 0x0000, + 0x0000, + 0x01, + 0x00, + _Y1A) + IRQ (Edge, ActiveHigh, Exclusive, _Y17) {} + DMA (Compatibility, NotBusMaster, Transfer8, _Y18) {} +}) + +CreateWordField (CRS2, \_SB.PCI0.LPCB.SIO1._Y17._INT, IRQE) +CreateByteField (CRS2, \_SB.PCI0.LPCB.SIO1._Y18._DMA, DMAE) +CreateWordField (CRS2, \_SB.PCI0.LPCB.SIO1._Y19._MIN, IO21) +CreateWordField (CRS2, \_SB.PCI0.LPCB.SIO1._Y19._MAX, IO22) +CreateByteField (CRS2, \_SB.PCI0.LPCB.SIO1._Y19._LEN, LEN2) +CreateWordField (CRS2, \_SB.PCI0.LPCB.SIO1._Y1A._MIN, IO31) +CreateWordField (CRS2, \_SB.PCI0.LPCB.SIO1._Y1A._MAX, IO32) +CreateByteField (CRS2, \_SB.PCI0.LPCB.SIO1._Y1A._LEN, LEN3) + +/* Read IO resource */ +Method (GIOB, 1, NotSerialized) +{ + If (CGLD (Arg0) == 0x07) /* UARTA */ + { + SWITCH_LDN (SUPERIO_LPC_LDN) + Local0 = (CR6B << 0x08) + Local0 |= CR6A + Return (Local0) + } + + If (CGLD (Arg0) == 0x08) /* UARTB */ + { + SWITCH_LDN (SUPERIO_LPC_LDN) + Local0 = (CR6F << 0x08) + Local0 |= CR6E + Return (Local0) + } + + If (CGLD (Arg0) == 0x11) /* LPT */ + { + SWITCH_LDN (SUPERIO_LPC_LDN) + Local0 = (CR83 << 0x08) + Local0 |= CR82 + Return (Local0) + } + + If (CGLD (Arg0) == 0x0B) /* Floppy */ + { + SWITCH_LDN (SUPERIO_LPC_LDN) + Local0 = (CR7F << 0x08) + Local0 |= CR7E + Return (Local0) + } + + Return (Zero) +} + +/* Read IRQ resource */ +Method (GIRQ, 1, NotSerialized) +{ + SWITCH_LDN (SUPERIO_LPC_LDN) + Local0 = 0x0F /* 15 IRQ regs, 1 for each IRQ number */ + While (Local0) + { + Local1 = (0x40 + Local0) /* IRQ regs begin at offset 0x40 */ + PNP_ADDR_REG = Local1 + Local1 = PNP_DATA_REG + If (CGLD (Arg0) == Local1) + { + Local1 = One + Local0 = (Local1 << Local0) + Return (Local0) + } + + Local0-- + } + + Return (0xFF) +} + +/* Read DMA resource */ +Method (GDMA, 1, NotSerialized) +{ + SWITCH_LDN (SUPERIO_LPC_LDN) + Local0 = 0x03 /* Only DMA Channels 0-3 */ + While (Local0) + { + Local1 = (Local0 << One) + Local1 += 0x51 /* DMA regs begin at offset 0x50 */ + PNP_ADDR_REG = Local1 + Local1 = PNP_DATA_REG + If ((0x80 | CGLD (Arg0)) == Local1) + { + Local1 = One + Local0 = (Local1 << Local0) + Return (Local0) + } + + Local0-- + } + + Return (0xFF) +} + +/* Set IO resource */ +Method (STIO, 2, NotSerialized) +{ + SWITCH_LDN (SUPERIO_LPC_LDN) + Local0 = (Arg1 & 0xFF) + PNP_ADDR_REG = Arg0 + PNP_DATA_REG = Local0 + Local0 = (Arg1 >> 0x08) + Local1 = (Arg0 + One) + PNP_ADDR_REG = Local1 + PNP_DATA_REG = Local0 +} + +/* Set IRQ resource */ +Method (SIRQ, 2, NotSerialized) +{ + SWITCH_LDN (SUPERIO_LPC_LDN) + FindSetRightBit (Arg1, Local0) + Local0 -= One + Local1 = 0x0F + While (Local1) + { + Local2 = (0x40 + Local1) + PNP_ADDR_REG = Local2 + Local3 = PNP_DATA_REG + If (CGLD (Arg0) == Local3) + { + If (Local0 != Local1) + { + PNP_ADDR_REG = Local2 + PNP_DATA_REG = 0xFF + Break + } + Else + { + Return (Zero) + } + } + + Local1-- + } + + Local0 += 0x40 + PNP_ADDR_REG = Local0 + PNP_DATA_REG = CGLD (Arg0) + Return (0xFF) +} + +/* Set DMA resource */ +Method (SDMA, 2, NotSerialized) +{ + SWITCH_LDN (SUPERIO_LPC_LDN) + FindSetRightBit (Arg1, Local0) + Local0 -= One + Local1 = 0x03 + While (Local1) + { + Local2 = (Local1 << One) + Local3 = (0x51 + Local2) + PNP_ADDR_REG = Local3 + Local4 = PNP_DATA_REG + If ((0x80 | CGLD (Arg0)) == Local4) + { + If (Local0 != Local1) + { + PNP_ADDR_REG = Local3 + PNP_DATA_REG = Zero + Break + } + Else + { + Return (Zero) + } + } + + Local1-- + } + + Local0 <<= One + Local0 += 0x51 + PNP_ADDR_REG = Local0 + PNP_DATA_REG = (0x80 | CGLD (Arg0)) + Return (Zero) +} + +/* Device Current Resource Settings */ +Method (DCRS, 2, NotSerialized) +{ + If (CGLD (Arg0) == 0x07) /* UARTA resources */ + { + ENTER_CONFIG_MODE (SUPERIO_LPC_LDN) + IO11 = GIOB (Arg0) + IO12 = IO11 + LEN1 = 0x08 + IRQM = GIRQ (Arg0) + If ((GDMA (Arg0) > 0x03) || (Arg1 == Zero)) + { + DMAM = Zero + } + Else + { + DMAM = GDMA (Arg0) + } + + EXIT_CONFIG_MODE () + Return (CRS1) + } + + If (CGLD (Arg0) == 0x08) /* UARTB resources */ + { + ENTER_CONFIG_MODE (SUPERIO_LPC_LDN) + IO11 = GIOB (Arg0) + IO12 = IO11 + LEN1 = 0x08 + IRQM = GIRQ (Arg0) + If ((GDMA (Arg0) > 0x03) || (Arg1 == Zero)) + { + DMAM = Zero + } + Else + { + DMAM = GDMA (Arg0) + } + + EXIT_CONFIG_MODE () + Return (CRS1) + } + + If (CGLD (Arg0) == 0x11) /* LPT resources */ + { + If (LPTM (Arg0)) + { + ENTER_CONFIG_MODE (SUPERIO_LPC_LDN) + IO21 = GIOB (Arg0) + IO22 = IO21 + IO31 = (IO21 + 0x0400) + IO32 = IO31 + If ((IO21 & 0xFF) == 0xBC) + { + LEN2 = 0x04 + LEN3 = 0x04 + } + Else + { + LEN2 = 0x08 + LEN3 = 0x04 + } + + IRQE = GIRQ (Arg0) + If ((GDMA (Arg0) > 0x03) || (Arg1 == Zero)) + { + DMAM = Zero + } + Else + { + DMAE = GDMA (Arg0) + } + + EXIT_CONFIG_MODE () + Return (CRS2) /* \_SB_.PCI0.LPCB.SIO1.CRS2 */ + } + Else + { + ENTER_CONFIG_MODE (SUPERIO_LPC_LDN) + IO11 = GIOB (Arg0) + IO12 = IO11 /* \_SB_.PCI0.LPCB.SIO1.IO11 */ + If ((IO11 & 0xFF) == 0xBC) + { + LEN1 = 0x04 + } + Else + { + LEN1 = 0x08 + } + + IRQM = GIRQ (Arg0) + EXIT_CONFIG_MODE () + Return (CRS1) /* \_SB_.PCI0.LPCB.SIO1.CRS1 */ + } + } + + If (CGLD (Arg0) == 0x0B) /* Floppy resources */ + { + ENTER_CONFIG_MODE (SUPERIO_LPC_LDN) + IO21 = GIOB (Arg0) + IO22 = IO21 /* \_SB_.PCI0.LPCB.SIO1.IO21 */ + LEN2 = 0x06 + IO31 = (IO21 + 0x07) + IO32 = IO31 /* \_SB_.PCI0.LPCB.SIO1.IO31 */ + LEN3 = One + IRQE = GIRQ (Arg0) + If ((GDMA (Arg0) > 0x03) || (Arg1 == Zero)) + { + DMAM = Zero + } + Else + { + DMAE = GDMA (Arg0) + } + + EXIT_CONFIG_MODE () + Return (CRS2) /* \_SB_.PCI0.LPCB.SIO1.CRS2 */ + } + + Return (CRS1) /* \_SB_.PCI0.LPCB.SIO1.CRS1 */ +} diff --git a/src/superio/smsc/sch5545/acpi/superio.asl b/src/superio/smsc/sch5545/acpi/superio.asl new file mode 100644 index 0000000000..97303c29fa --- /dev/null +++ b/src/superio/smsc/sch5545/acpi/superio.asl @@ -0,0 +1,589 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the SCH5545 SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices and controlling power + * saving mode on logical devices or the whole chip. + * + * LDN State + * 0x0 FDC Not implemented + * 0x3 PP Not implemented + * 0x4 UARTA Implemented and tested + * 0x5 UARTB Implemented + * 0x7 KBC Implemented and tested + * + * Controllable through preprocessor defines: + * SUPERIO_PNP_BASE I/O address of the first PnP configuration register + * SCH5545_SHOW_UARTA If defined, UARTA will be exposed. + * SCH5545_SHOW_UARTB If defined, UARTB will be exposed. + * SCH5545_SHOW_KBC If defined, the KBC will be exposed. + * SCH5545_EMI_BASE If defined, the Embedded Memory Interface resource will be exposed. + * SCH5545_RUNTIME_BASE If defined, The Runtime Registers resource will be exposed. + */ + +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME SCH5545 +#include + +#undef PNP_DEFAULT_PSC +#define PNP_DEFAULT_PSC Return (0) /* no power management */ + +/* +* Common helpers will not work on this chip. IO, DMA and IRQ resources. +* These are accessed via LPC interface LDN 0xC. +*/ +#undef PNP_READ_IO +#undef PNP_READ_IRQ +#undef PNP_READ_DMA +#undef PNP_WRITE_IO +#undef PNP_WRITE_IRQ +#undef PNP_WRITE_DMA + +Device(SIO1) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("SMSC SCH5545 Super I/O")) + Name (_UID, SUPERIO_UID(SIO1,)) + +#ifdef SCH5545_EMI_BASE + Name (IO1B, SCH5545_EMI_BASE) +#endif +#ifdef SCH5545_RUNTIME_BASE + Name (IO2B, SCH5545_RUNTIME_BASE) +#endif + Name (IOST, 0x0001) /* IO decoding status */ + Name (MSFG, One) /* Mouse wake config */ + Name (KBFG, One) /* Keyboard wake config */ + Name (PMFG, Zero) /* Wake config */ + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8 + } + IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + + Offset (0x69), + CR69, 8, /* UART1 Base address Registers */ + CR6A, 8, + CR6B, 8, + Offset (0x6D), + CR6D, 8, /* UART2 Base address Registers */ + CR6E, 8, + CR6F, 8, + Offset (0x7D), + CR7D, 8, /* FD Base address Registers */ + CR7E, 8, + CR7F, 8, + Offset (0x81), + CR81, 8, /* LPT Base address Registers */ + CR82, 8, + CR83, 8, + Offset (0xF0), + OPT0, 8, /* MISC registers */ + OPT1, 8, + OPT2, 8, + OPT3, 8, + OPT4, 8, + OPT5, 8 + } + +#ifdef SCH5545_RUNTIME_BASE + /* Runtime registers */ + OperationRegion (RNTR, SystemIO, SCH5545_RUNTIME_BASE, 0x40) + Field (RNTR, ByteAcc, NoLock, Preserve) + { + PMES, 1, /* PME Global Status */ + Offset (0x01), + PMEN, 1, /* PME Global Enable */ + Offset (0x02), + PMS1, 8, /* PME Status 1 for KBD and PS2M */ + PMS2, 8, /* PME Status 2 for EC, WDT, Bat, Intruder */ + PMS3, 8, /* PME Status 3 for GPIOs */ + PME1, 8, /* PME Enable 1 for KBD and PS2M */ + PME2, 8, /* PME Enable 2 for EC, WDT, Bat, Intruder */ + PME3, 8, /* PME Enable 3 for GPIOs */ + Offset (0x10), + SOIS, 1, /* SMI Global Status*/ + Offset (0x11), + SOIE, 1, /* SMI Global Enable */ + Offset (0x12), + SST1, 8, /* SMI Status 1 for UARTs, LPT, FD, EC, Bat */ + SST2, 8, /* SMI Status 2 for KBD, PS2M, WDT, Intruder */ + SST3, 8, /* SMI Status 3 for GPIOs */ + Offset (0x16), + SEN1, 8, /* SMI Enable 1 for UARTs, LPT, FD, EC, Bat */ + SEN2, 8, /* SMI Enable 2 for KBD, PS2M, WDT, Intruder */ + SEN3, 8, /* SMI Enable 3 for GPIOs */ + Offset (0x25), + LED1, 8, /* LED control register */ + Offset (0x28), + GPSR, 8, /* GPIO Select Register */ + GPRR, 8 /* GPIO Read Register */ + } +#endif + Name (CRS, ResourceTemplate () + { + IO (Decode16, + 0x0000, + 0x0000, + 0x00, + 0x00, + _Y11) +#ifdef SCH5545_EMI_BASE + IO (Decode16, + 0x0000, + 0x0000, + 0x00, + 0x00, + _Y12) +#endif +#ifdef SCH5545_RUNTIME_BASE + IO (Decode16, + 0x0000, + 0x0000, + 0x00, + 0x00, + _Y13) +#endif + }) + Method (_CRS, 0, NotSerialized) + { + If (SUPERIO_PNP_BASE) + { + CreateWordField (CRS, \_SB.PCI0.LPCB.SIO1._Y11._MIN, GPI0) + CreateWordField (CRS, \_SB.PCI0.LPCB.SIO1._Y11._MAX, GPI1) + CreateByteField (CRS, \_SB.PCI0.LPCB.SIO1._Y11._LEN, GPIL) + GPI0 = SUPERIO_PNP_BASE + GPI1 = SUPERIO_PNP_BASE + GPIL = 0x02 + } +#ifdef SCH5545_EMI_BASE + If (IO1B) + { + CreateWordField (CRS, \_SB.PCI0.LPCB.SIO1._Y12._MIN, GP10) + CreateWordField (CRS, \_SB.PCI0.LPCB.SIO1._Y12._MAX, GP11) + CreateByteField (CRS, \_SB.PCI0.LPCB.SIO1._Y12._LEN, GPL1) + GP10 = SCH5545_EMI_BASE + GP11 = SCH5545_EMI_BASE + GPL1 = 0x10 + } +#endif +#ifdef SCH5545_RUNTIME_BASE + If (IO2B) + { + CreateWordField (CRS, \_SB.PCI0.LPCB.SIO1._Y13._MIN, GP20) + CreateWordField (CRS, \_SB.PCI0.LPCB.SIO1._Y13._MAX, GP21) + CreateByteField (CRS, \_SB.PCI0.LPCB.SIO1._Y13._LEN, GPL2) + GP20 = SCH5545_RUNTIME_BASE + GP21 = SCH5545_RUNTIME_BASE + GPL2 = 0x40 + } +#endif + Return (CRS) + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #undef PNP_EXIT_SPECIAL_REG + #undef PNP_EXIT_SPECIAL_VAL + #define PNP_ENTER_MAGIC_1ST 0x55 + #define PNP_EXIT_MAGIC_1ST 0xaa + #include + #define SUPERIO_LPC_LDN 0x0C + #include "resource_helpers.asl" + +#ifdef SCH5545_SHOW_KBC + Device (PS2K) + { + Name (_HID, EisaId ("PNP0303")) + Name (_CID, EisaId ("PNP030B")) + Method (_STA, 0, NotSerialized) + { + Return (DSTA (0xa)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, + 0x0060, + 0x0060, + 0x00, + 0x01, + ) + IO (Decode16, + 0x0064, + 0x0064, + 0x00, + 0x01, + ) + IRQ (Edge, ActiveHigh, Exclusive) {1} + }) + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0x00, 0x00) + { + FixedIO ( + 0x0060, // Address + 0x01, + ) + FixedIO ( + 0x0064, // Address + 0x01, + ) + IRQ (Edge, ActiveHigh, Exclusive) {1} + } + EndDependentFn () + }) + Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake + { + KBFG = Arg0 + } + Name (_PRW, Package() { 8, 3 }) + } + + Device (PS2M) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (DSTA (0xe)) + } + + Name (_CRS, ResourceTemplate () + { + IRQ (Edge, ActiveHigh, Exclusive) {12} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0x00, 0x00) + { + IRQ (Edge, ActiveHigh, Exclusive) {12} + } + EndDependentFn () + }) + + Method (_PSW, 1, NotSerialized) + { + MSFG = Arg0 + } + + Name (_PRW, Package() { 8, 3 }) + } + + OperationRegion (IOKP, SystemIO, 0x60, 0x05) + Field (IOKP, ByteAcc, NoLock, Preserve) + { + KP60, 8, + Offset (0x04), + KP64, 8 + } + + OperationRegion (KB64, SystemIO, 0x64, One) + Field (KB64, ByteAcc, NoLock, Preserve) + { + , 1, + KRDY, 1, + Offset (0x01) + } +#ifdef SCH5545_RUNTIME_BASE + /* SIO prepare to sleep */ + Method (SIOS, 1, NotSerialized) + { + If ((Arg0 == 0x03) | (Arg0 == One)) + { + ENTER_CONFIG_MODE (One) + Local0 = OPT0 + OPT0 = (Local0 | 0x60) + EXIT_CONFIG_MODE () + Local0 = PMS1 + PMS1 = (Local0 | 0x18) + Local0 = PMES + PMES = (Local0 | One) + + Local0 = PME1 + If (KBFG) + { + PME1 = (Local0 | 0x08) + } + Else + { + PME1 = (Local0 & 0xF7) + } + + Local0 = PME1 + If (MSFG) + { + PME1 = (Local0 | 0x10) + } + Else + { + PME1 = (Local0 & 0xEF) + } + + Local0 = PMEN + PMEN = (Local0 | One) + + While (KRDY) {} + KP60 = 0xED + While (KRDY) {} + KP60 = Zero + While (KRDY) {} + KP60 = 0xF4 + Sleep (One) + } + } + + Method (GPKM, 0, NotSerialized) + { + Local0 = PME1 + PME1 = (Local0 & 0xE7) + Local0 = PMEN + PMEN = (Local0 & 0xFE) + Local0 = PMS1 + PMS1 = (Local0 & 0x18) + Local0 = PMES + PMES = (Local0 & One) + } + + /* SIO wake method */ + Method (SIOW, 1, NotSerialized) + { + PMFG = PMS1 + If (Arg0 == One) + { + GPKM () + ENTER_CONFIG_MODE (One) + Local0 = OPT0 + OPT0 = (Local0 & 0x9F) + EXIT_CONFIG_MODE () + } + + If (Arg0 == 0x03) + { + GPKM () + ENTER_CONFIG_MODE (One) + Local0 = OPT0 + OPT0 = (Local0 & 0x9F) + OPT2 |= One + OPT2 &= 0xFE + EXIT_CONFIG_MODE () + } + } + + Method (SIOH, 0, NotSerialized) + { + If (PMFG & 0x08) + { + Notify (PS2K, 0x02) // Device Wake + } + + If (PMFG & 0x10) + { + Notify (PS2M, 0x02) // Device Wake + } + } +#endif // SCH5545_RUNTIME_BASE +#endif // SCH5545_SHOW_KBC + +#ifdef SCH5545_SHOW_UARTA +#define SUPERIO_UARTA_LDN 7 + Device (UAR1) + { + Name (_HID, EisaId ("PNP0501")) + Name (_UID, SUPERIO_UID(SER, SUPERIO_UARTA_LDN)) + Method (_STA, 0, NotSerialized) + { + Return (DSTA (Zero)) + } + + Method (_DIS, 0, NotSerialized) + { + DCNT (Zero, Zero) + } + + Method (_CRS, 0, NotSerialized) + { + Return (DCRS (Zero, Zero)) + } + + Method (_SRS, 1, NotSerialized) + { + CreateWordField (Arg0, 0x02, IO11) + CreateWordField (Arg0, 0x09, IRQM) + ENTER_CONFIG_MODE (SUPERIO_LPC_LDN) + STIO (0x6A, IO11) + SIRQ (Zero, IRQM) + EXIT_CONFIG_MODE () + DCNT (Zero, One) + } + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0x00, 0x00) + { + IO (Decode16, + 0x03F8, + 0x03F8, + 0x01, + 0x08, + ) + IRQNoFlags () + {4} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {} + } + StartDependentFn (0x00, 0x00) + { + IO (Decode16, + 0x02F8, + 0x02F8, + 0x01, + 0x08, + ) + IRQNoFlags () + {3} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {} + } + StartDependentFn (0x00, 0x00) + { + IO (Decode16, + 0x03E8, + 0x03E8, + 0x01, + 0x08, + ) + IRQNoFlags () + {4} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {} + } + StartDependentFn (0x00, 0x00) + { + IO (Decode16, + 0x02E8, + 0x02E8, + 0x01, + 0x08, + ) + IRQNoFlags () + {3} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {} + } + EndDependentFn () + }) + + Name (_PRW, Package() { 8, 3 }) + } +#endif + +#ifdef SCH5545_SHOW_UARTB +#define SUPERIO_UARTB_LDN 8 + Device (UAR1) + { + Name (_HID, EisaId ("PNP0501")) + Name (_UID, SUPERIO_UID(SER, SUPERIO_UARTB_LDN)) + Method (_STA, 0, NotSerialized) + { + Return (DSTA (One)) + } + + Method (_DIS, 0, NotSerialized) + { + DCNT (One, Zero) + } + + Method (_CRS, 0, NotSerialized) + { + Return (DCRS (One, Zero)) + } + + Method (_SRS, 1, NotSerialized) + { + CreateWordField (Arg0, 0x02, IO11) + CreateWordField (Arg0, 0x09, IRQM) + ENTER_CONFIG_MODE (SUPERIO_LPC_LDN) + STIO (0x6E, IO11) + SIRQ (One, IRQM) + EXIT_CONFIG_MODE () + DCNT (One, One) + } + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0x00, 0x00) + { + IO (Decode16, + 0x03F8, + 0x03F8, + 0x01, + 0x08, + ) + IRQNoFlags () + {4} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {} + } + StartDependentFn (0x00, 0x00) + { + IO (Decode16, + 0x02F8, + 0x02F8, + 0x01, + 0x08, + ) + IRQNoFlags () + {3} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {} + } + StartDependentFn (0x00, 0x00) + { + IO (Decode16, + 0x03E8, + 0x03E8, + 0x01, + 0x08, + ) + IRQNoFlags () + {4} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {} + } + StartDependentFn (0x00, 0x00) + { + IO (Decode16, + 0x02E8, + 0x02E8, + 0x01, + 0x08, + ) + IRQNoFlags () + {3} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {} + } + EndDependentFn () + }) + + Name (_PRW, Package() { 8, 3 }) + } + +#endif +} diff --git a/src/superio/smsc/sch5545/sch5545.h b/src/superio/smsc/sch5545/sch5545.h new file mode 100644 index 0000000000..464be1a106 --- /dev/null +++ b/src/superio/smsc/sch5545/sch5545.h @@ -0,0 +1,299 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Based on SMSC SCH5627 datahseet: + * http://pdf.datasheetcatalog.com/datasheets/microchip/00001996A.pdf + */ + +#ifndef SUPERIO_SCH_5545_H +#define SUPERIO_SCH_5545_H + +/* LPC I/O space */ +#define SCH5545_RUNTIME_REG_BASE 0x0a00 +#define SCH5545_EMI_BASE 0x0a40 + +/* logical devices */ +#define SCH5545_LDN_EMI 0x00 +#define SCH5545_LDN_KBC 0x01 +#define SCH5545_LDN_UART1 0x07 +#define SCH5545_LDN_UART2 0x08 +#define SCH5545_LDN_RR 0x0a /* Runtime Registers */ +#define SCH5545_LDN_FDC 0x0b +#define SCH5545_LDN_LPC 0x0c /* LPC Interface */ +#define SCH5545_LDN_PP 0x11 +#define SCH5545_LDN_GCONF 0x3f /* Global Config */ + +/* KBC config registers */ +#define SCH5545_KRST_GA20 0xf0 +#define SCH5545_PORT92_EN (1 << 2) +#define SCH5545_KBD_INT_LATCH (1 << 3) +#define SCH5545_MOUSE_INT_LATCH (1 << 4) +#define SCH5545_KBD_ISOLATION (1 << 5) +#define SCH5545_MOUSE_ISOLATION (1 << 6) +#define SCH5545_KEYBOARD_SELECT 0xf1 +#define SCH5545_KBD_MOUSE_SWAP (1 << 0) +#define SCH5545_8042_RESET 0xf2 +#define SCH5545_8042_IN_RESET (1 << 0) +#define SCH5545_8042_OUT_RESET (0 << 0) + +/* UART config registers */ +#define SCH5545_UART_CONFIG_SELECT 0xf0 +#define SCH5545_UART_CLK_64MHZ_RO (0 << 0) +#define SCH5545_UART_CLK_96MHZ_PLL (1 << 0) +#define SCH5545_UART_POWER_VTR (0 << 1) +#define SCH5545_UART_POWER_VCC (1 << 1) +#define SCH5545_UART_NO_POLARITY_INVERT (0 << 2) +#define SCH5545_UART_INVERT_POLARITY (1 << 2) + +/* RR config registers */ +#define SCH5545_SPEKEY 0xf0 +#define SCH5545_SPEKEY_WAKE_EN (0 << 1) +#define SCH5545_SPEKEY_WAKE_DIS (1 << 1) + +/* Floppy config registers */ +#define SCH5545_FDD_MODE 0xf0 +#define SCH5545_FDD_MODE_NORMAL (0 << 0) +#define SCH5545_FDD_MODE_ENHANCED (1 << 0) +#define SCH5545_FDC_DMA_MODE_BURST (0 << 1) +#define SCH5545_FDC_DMA_MODE_NON_BURST (1 << 1) +#define SCH5545_FDD_IF_MODE_AT (3 << 2) +#define SCH5545_FDD_IF_MODE_PS2 (1 << 2) +#define SCH5545_FDD_IF_MODE_MODEL30 (0 << 2) +#define SCH5545_FDC_OUTPUT_TYPE_OPEN_DRAIN (0 << 6) +#define SCH5545_FDC_OUTPUT_TYPE_PUSH_PULL (1 << 6) +#define SCH5545_FDC_OUTPUT_CTRL_ACTIVE (0 << 7) +#define SCH5545_FDC_OUTPUT_CTRL_TRISTATE (1 << 7) +#define SCH5545_FDD_OPTION 0xf1 +#define SCH5545_FDD_FORCED_WP_INACTIVE (0 << 0) +#define SCH5545_FDD_FORCED_WP_ACTIVE (1 << 0) +#define SCH5545_FDD_DENSITY_NORMAL (0 << 2) +#define SCH5545_FDD_DENSITY_NORMAL_USER (1 << 2) +#define SCH5545_FDD_DENSITY_LOGIC_ONE (2 << 2) +#define SCH5545_FDD_DENSITY_LOGIC_ZERO (3 << 2) +#define SCH5545_FDD_TYPE 0xf2 +#define SCH5545_FDD0 0xf4 +#define SCH5545_FDD0_TYPE_SEL_DT0 (1 << 0) +#define SCH5545_FDD0_TYPE_SEL_DT1 (1 << 1) +#define SCH5545_FDD0_DRT_SEL_DRT0 (1 << 3) +#define SCH5545_FDD0_USE_PRECOMPENSATION (0 << 6) +#define SCH5545_FDD0_NO_PRECOMPENSATION (1 << 6) + +/* Parallel Port config registers */ +#define SCH5545_PP_INT_SELECT 0x70 +#define SCH5545_PP_SERIRQ_CHANNEL_MASK 0xf +#define SCH5545_PP_DMA_SELECT 0x74 +#define SCH5545_PP_DMA_CHANNEL_MASK 0x7 +#define SCH5545_PP_MODE 0xf0 +#define SCH5545_PP_MODE_PRINTER (4 << 0) +#define SCH5545_PP_MODE_SPP (0 << 0) +#define SCH5545_PP_MODE_EPP19_SPP (1 << 0) +#define SCH5545_PP_MODE_EPP17_SPP (5 << 0) +#define SCH5545_PP_MODE_ECP (2 << 0) +#define SCH5545_PP_MODE_EPP17_ECP (3 << 0) +#define SCH5545_PP_MODE_EPP19_ECP (7 << 0) +#define SCH5545_PP_ECP_FIFO_TRESH_MASK (0xf << 3) +#define SCH5545_PP_INT_PULSED_LOW (1 << 7) +#define SCH5545_PP_INT_FOLLOWS_ACK (0 << 7) +#define SCH5545_PP_MODE2 0xf1 +#define SCH5545_PP_TMOUT_CLEARED_ON_WRITE (0 << 4) +#define SCH5545_PP_TMOUT_CLEARED_ON_READ (1 << 4) + +/* LPC IF config registers */ +#define SCH5545_IRQ_BASE 0x40 +#define SCH5545_DRQ_BASE 0x50 +/* + * BAR registers are 4 byte + * byte 0 0-6 mask, 7 reserved + * byte 1 0-5 frame, 6 device, 7 valid + * byte 2 LPC address least sig. + * byte 3 LPC address most sig. + */ +#define SCH5545_BAR_LPC_IF 0x60 +#define SCH5545_BAR_EM_IF 0x64 +#define SCH5545_BAR_UART1 0x68 +#define SCH5545_BAR_UART2 0x6c +#define SCH5545_BAR_RUNTIME_REG 0x70 +/* Certain SMSC parts have SPI controller LDN 0xf with BAR rgeister at 0x74 */ +#define SCH5545_BAR_KBC 0x78 +#define SCH5545_BAR_FLOPPY 0x7c +#define SCH5545_BAR_PARPORT 0x80 + +/* IRQ <> device mappings */ +#define SCH5545_IRQ_KBD 0x01 +#define SCH5545_IRQ_MOUSE 0x81 +#define SCH5545_IRQ_UART1 0x07 +#define SCH5545_IRQ_UART2 0x08 +#define SCH5545_IRQ_EMI_MAILBOX 0x00 +#define SCH5545_IRQ_EMI_IRQ_SOURCE 0x80 +#define SCH5545_IRQ_RUNTIME_REG 0x0a +#define SCH5545_IRQ_RUNTIME_REG_SMI 0x8a +#define SCH5545_IRQ_FLOPPY 0x0b +#define SCH5545_IRQ_PARPORT 0x11 +#define SCH5545_IRQ_DISABLED 0xff + + +/* runtime registers */ +#define SCH5545_RR_PME_STS 0x00 +#define SCH5545_GLOBAL_PME_STS 0x01 +#define SCH5545_RR_PME_EN 0x01 +#define SCH5545_GLOBAL_PME_EN 0x01 +#define SCH5545_RR_PME_STS1 0x02 +#define SCH5545_UART2_RI_PME_STS 0x2 +#define SCH5545_UART1_RI_PME_STS 0x4 +#define SCH5545_KBD_PME_STS 0x8 +#define SCH5545_MOUSE_PME_STS 0x10 +#define SCH5545_SPECIFIC_KEY_PME_STS 0x20 +#define SCH5545_RR_PME_STS2 0x03 +#define SCH5545_IO_SMI_EVT_STS 0x1 +#define SCH5545_WDT_TIMEOUT_EVT_STS 0x2 +#define SCH5545_EM_EVT1_STS 0x4 +#define SCH5545_EM_EVT2_STS 0x8 +#define SCH5545_FW_EVT_STS 0x10 +#define SCH5545_BAT_LOW_STS 0x20 +#define SCH5545_INTRUDER_STS 0x40 +#define SCH5545_RR_PME_STS3 0x04 +#define SCH5545_GPIO62_PME_STS 0x1 +#define SCH5545_GPIO54_PME_STS 0x2 +#define SCH5545_GPIO53_PME_STS 0x4 +#define SCH5545_GPIO35_PME_STS 0x8 +#define SCH5545_GPIO31_PME_STS 0x10 +#define SCH5545_GPIO25_PME_STS 0x20 +#define SCH5545_GPIO24_PME_STS 0x40 +#define SCH5545_GPIO21_PME_STS 0x80 +#define SCH5545_RR_PME_EN1 0x05 +#define SCH5545_UART2_RI_PME_EN 0x2 +#define SCH5545_UART1_RI_PME_EN 0x4 +#define SCH5545_KBD_PME_EN 0x8 +#define SCH5545_MOUSE_PME_EN 0x10 +#define SCH5545_SPECIFIC_KEY_PME_EN 0x20 +#define SCH5545_RR_PME_EN2 0x06 +#define SCH5545_IO_SMI_EVT_PME_EN 0x1 +#define SCH5545_WDT_EVT_PME_EN 0x2 +#define SCH5545_EM_EVT1_PME_EN 0x4 +#define SCH5545_EM_EVT2_PME_EN 0x8 +#define SCH5545_FW_EVT_PME_EN 0x10 +#define SCH5545_BAT_LOW_PME_EN 0x20 +#define SCH5545_INTRUDER_PME_EN 0x40 +#define SCH5545_RR_PME_EN3 0x07 +#define SCH5545_GPIO62_PME_EN 0x1 +#define SCH5545_GPIO54_PME_EN 0x2 +#define SCH5545_GPIO53_PME_EN 0x4 +#define SCH5545_GPIO35_PME_EN 0x8 +#define SCH5545_GPIO31_PME_EN 0x10 +#define SCH5545_GPIO25_PME_EN 0x20 +#define SCH5545_GPIO24_PME_EN 0x40 +#define SCH5545_GPIO21_PME_EN 0x80 +#define SCH5545_RR_SMI_STS 0x10 +#define SCH5545_SMI_GLOBAL_STS 0x1 +#define SCH5545_RR_SMI_EN 0x11 +#define SCH5545_SMI_GLOBAL_EN 0x1 +#define SCH5545_RR_SMI_STS1 0x12 +#define SCH5545_LOW_BAT_SMI_STS 0x1 +#define SCH5545_PAR_PORT_SMI_STS 0x2 +#define SCH5545_UART2_SMI_STS 0x4 +#define SCH5545_UART1_SMI_STS 0x8 +#define SCH5545_FLOPPY_SMI_STS 0x10 +#define SCH5545_EM_EVT1_SMI_STS 0x20 +#define SCH5545_EM_EVT2_SMI_STS 0x40 +#define SCH5545_FW_EVT_SMI_STS 0x80 +#define SCH5545_RR_SMI_STS2 0x13 +#define SCH5545_MOUSE_SMI_STS 0x1 +#define SCH5545_KBD_SMI_STS 0x2 +#define SCH5545_WATCHDOG_EVT_SMI_STS 0x8 +#define SCH5545_INTRUSION_SMI_STS 0x10 +#define SCH5545_RR_SMI_STS3 0x14 +#define SCH5545_GPIO62_SMI_STS 0x1 +#define SCH5545_GPIO54_SMI_STS 0x2 +#define SCH5545_GPIO53_SMI_STS 0x4 +#define SCH5545_GPIO35_SMI_STS 0x8 +#define SCH5545_GPIO31_SMI_STS 0x10 +#define SCH5545_GPIO25_SMI_STS 0x20 +#define SCH5545_GPIO24_SMI_STS 0x40 +#define SCH5545_GPIO21_SMI_STS 0x80 +#define SCH5545_RR_SMI_EN1 0x15 +#define SCH5545_LOW_BAT_SMI_EN 0x1 +#define SCH5545_PAR_PORT_SMI_EN 0x2 +#define SCH5545_UART2_SMI_EN 0x4 +#define SCH5545_UART1_SMI_EN 0x8 +#define SCH5545_FLOPPY_SMI_EN 0x10 +#define SCH5545_EM_EVT1_SMI_EN 0x20 +#define SCH5545_EM_EVT2_SMI_EN 0x40 +#define SCH5545_FW_EVT_SMI_EN 0x1 +#define SCH5545_RR_SMI_EN2 0x16 +#define SCH5545_MOUSE_SMI_EN 0x1 +#define SCH5545_KBD_SMI_EN 0x2 +#define SCH5545_WATCHDOG_EVT_SMI_EN 0x8 +#define SCH5545_INTRUSION_SMI_EN 0x10 +#define SCH5545_RR_SMI_EN3 0x17 +#define SCH5545_GPIO62_SMI_EN 0x1 +#define SCH5545_GPIO54_SMI_EN 0x2 +#define SCH5545_GPIO53_SMI_EN 0x4 +#define SCH5545_GPIO35_SMI_EN 0x8 +#define SCH5545_GPIO31_SMI_EN 0x10 +#define SCH5545_GPIO25_SMI_EN 0x20 +#define SCH5545_GPIO24_SMI_EN 0x40 +#define SCH5545_GPIO21_SMI_EN 0x80 +#define SCH5545_RR_FORCE_DISK_CH 0x20 +#define SCH5545_FLOPPY_DISK_CHANGE 0x1 +#define SCH5545_RR_FLOPPY_DR_SEL 0x21 +#define SCH5545_DR_SELECT0 0x1 +#define SCH5545_DR_SELECT1 0x2 +#define SCH5545_FLOPPY_PRECOMP0 0x4 +#define SCH5545_FLOPPY_PRECOMP1 0x8 +#define SCH5545_FLOPPY_PRECOMP2 0x10 +#define SCH5545_FLOPPY_PWR_DOWN 0x40 +#define SCH5545_FLOPPY_SOFT_RESET 0x80 +#define SCH5545_RR_UART1_FIFO_CTRL 0x22 +#define SCH5545_UART1_FIFO_FE 0x1 +#define SCH5545_UART1_FIFO_RFR 0x2 +#define SCH5545_UART1_FIFO_XFR 0x4 +#define SCH5545_UART1_FIFO_DMS 0x8 +#define SCH5545_UART1_FIFO_RTL 0x40 +#define SCH5545_UART1_FIFO_RTM 0x80 +#define SCH5545_RR_UART2_FIFO_CTRL 0x23 +#define SCH5545_UART2_FIFO_FE 0x1 +#define SCH5545_UART2_FIFO_RFR 0x2 +#define SCH5545_UART2_FIFO_XFR 0x4 +#define SCH5545_UART2_FIFO_DMS 0x8 +#define SCH5545_UART2_FIFO_RTL 0x40 +#define SCH5545_UART2_FIFO_RTM 0x80 +#define SCH5545_RR_DEV_DISABLE 0x24 +#define SCH5545_FLOPPY_WP 0x1 +#define SCH5545_FLOPPY_DIS 0x8 +#define SCH5545_UART2_DIS 0x20 +#define SCH5545_UART1_DIS 0x40 +#define SCH5545_PAR_PORT_DIS 0x80 +#define SCH5545_RR_LED 0x25 +#define SCH5545_LED_BLINK_OFF 0x0 +#define SCH5545_LED_BLINK_1HZ 0x1 +#define SCH5545_LED_BLINK_ON 0x3 +#define SCH5545_LED_BLINK_MASK 0x3 +#define SCH5545_LED_COLOR_YELLOW 0x0 +#define SCH5545_LED_COLOR_GREEN 0x4 +#define SCH5545_LED_CODE_FETCH 0x8 +#define SCH5545_RR_KB_SCAN 0x26 +#define SCH5545_RR_PWRGOOD 0x27 +#define SCH5545_PWRGOOD_DELAY 0x1 +#define SCH5545_PWRGOOD_LOCK 0x2 +#define SCH5545_PCIRST_OUT4_EN 0x10 +#define SCH5545_PCIRST_OUT3_EN 0x20 +#define SCH5545_PCIRST_OUT1_EN 0x40 +#define SCH5545_PCIRST_OUT2_EN 0x80 +#define SCH5545_RR_GPIO_SEL 0x28 +#define SCH5545_RR_GPIO_READ 0x29 +#define SCH5545_RR_GPIO_WRITE 0x2A +#define SCH5545_RR_FW_EVT_STS 0x30 +#define SCH5545_RR_FW_EVT_EN 0x31 +#define SCH5545_RR_PWR_REC_MODES 0x32 +#define SCH5545_PWR_SUPPLY_OFF 0x00 +#define SCH5545_PWR_SUPPLY_ON 0x80 +#define SCH5545_RR_INTRUDER 0x34 +#define SCH5545_INTRUSION_EDGE_STS 0x1 +#define SCH5545_INTRUDER_PIN_STS 0x2 + +void sch5545_early_init(unsigned int port); +void sch5545_enable_uart(unsigned int port, unsigned int uart_no); +void sch5545_set_led(unsigned int runtime_reg_base, unsigned int color, uint16_t blink); +int sch5545_get_gpio(uint8_t sio_port, uint8_t gpio); + +#endif /* SUPERIO_SCH_5545_H */ diff --git a/src/superio/smsc/sch5545/sch5545_early_init.c b/src/superio/smsc/sch5545/sch5545_early_init.c new file mode 100644 index 0000000000..4841571113 --- /dev/null +++ b/src/superio/smsc/sch5545/sch5545_early_init.c @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include "sch5545.h" + +static void pnp_enter_conf_state(pnp_devfn_t dev) +{ + unsigned int port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(pnp_devfn_t dev) +{ + unsigned int port = dev >> 8; + outb(0xaa, port); +} + +/* + * Set the BAR / iobase for a specific device. + * pnp_devfn_t dev must be in conf state. + * LDN LPC IF must be active. + */ +static void set_iobase(pnp_devfn_t dev, uint16_t device_addr, uint16_t bar_addr) +{ + uint16_t bar; + + /* + * Set the BAR. We have to flip the BAR due to different register layout: + * - LPC addr LSB on device_addr + 2 + * - LPC addr MSB on device_addr + 3 + */ + bar = ((bar_addr >> 8) & 0xff) | ((bar_addr & 0xff) << 8); + pnp_set_iobase(dev, device_addr + 2, bar); +} + +/* + * Set the IRQ for the specific device. + * pnp_devfn_t dev must be in conf state. + * LDN LPC IF must be active. + */ +static void set_irq(pnp_devfn_t dev, uint8_t irq_device, unsigned int irq) +{ + if (irq > 15) + return; + + pnp_write_config(dev, SCH5545_IRQ_BASE + irq, irq_device); +} + +/* + * sch5545 has 2 LEDs which are accessed via color (1 bit), 2 bits for a + * pattern blink and 1 bit for "code fetch" which means the cpu/mainboard is + * working (always set). + */ +void sch5545_set_led(unsigned int runtime_reg_base, unsigned int color, uint16_t blink) +{ + uint8_t val = blink & SCH5545_LED_BLINK_MASK; + val |= SCH5545_LED_CODE_FETCH; + if (color) + val |= SCH5545_LED_COLOR_GREEN; + outb(val, runtime_reg_base + SCH5545_RR_LED); +} + +void sch5545_early_init(unsigned int port) +{ + pnp_devfn_t dev; + + /* Enable SERIRQ */ + dev = PNP_DEV(port, SCH5545_LDN_GCONF); + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_write_config(dev, 0x24, pnp_read_config(dev, 0x24) | 0x04); + + /* Enable LPC interface */ + dev = PNP_DEV(port, SCH5545_LDN_LPC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); + /* Set LPC BAR mask */ + pnp_write_config(dev, SCH5545_BAR_LPC_IF, 0x01); + /* BAR valid, Frame/LDN = 0xc */ + pnp_write_config(dev, SCH5545_BAR_LPC_IF + 1, SCH5545_LDN_LPC | 0x80); + set_iobase(dev, SCH5545_BAR_LPC_IF, port); + + /* Enable Runtime Registers */ + + /* The Runtime Registers BAR is 0x40 long */ + pnp_write_config(dev, SCH5545_BAR_RUNTIME_REG, 0x3f); + /* BAR valid, Frame/LDN = 0xa */ + pnp_write_config(dev, SCH5545_BAR_RUNTIME_REG + 1, SCH5545_LDN_RR | 0x80); + + /* Map Runtime Registers */ + set_iobase(dev, SCH5545_BAR_RUNTIME_REG, SCH5545_RUNTIME_REG_BASE); + dev = PNP_DEV(port, SCH5545_LDN_RR); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); + + /* Set LED color and indicate BIOS has reached code fetch phase */ + sch5545_set_led(SCH5545_RUNTIME_REG_BASE, SCH5545_LED_COLOR_GREEN, + SCH5545_LED_BLINK_ON); + + /* Configure EMI */ + dev = PNP_DEV(port, SCH5545_LDN_LPC); + pnp_set_logical_device(dev); + /* EMI BAR has 11 registers, but vendor sets the mask to 0xf */ + pnp_write_config(dev, SCH5545_BAR_EM_IF, 0x0f); + /* BAR valid, Frame/LDN = 0x00 */ + pnp_write_config(dev, SCH5545_BAR_EM_IF + 1, SCH5545_LDN_EMI | 0x80); + set_iobase(dev, SCH5545_BAR_EM_IF, SCH5545_EMI_BASE); + + pnp_exit_conf_state(dev); +} + +void sch5545_enable_uart(unsigned int port, unsigned int uart_no) +{ + pnp_devfn_t dev; + + if (uart_no > 1) + return; + + /* Configure serial port */ + dev = PNP_DEV(port, SCH5545_LDN_LPC); + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + /* Set UART BAR mask to 0x07 (8 registers) */ + pnp_write_config(dev, SCH5545_BAR_UART1 + (4 * uart_no), 0x07); + /* Set BAR valid, Frame/LDN = UART1/2 LDN 0x07/0x08 */ + pnp_write_config(dev, SCH5545_BAR_UART1 + (4 * uart_no) + 1, + (SCH5545_LDN_UART1 + uart_no) | 0x80); + set_iobase(dev, SCH5545_BAR_UART1 + (4 * uart_no), (uart_no == 1) ? 0x2f8 : 0x3f8); + /* IRQ 3 for UART2, IRQ4 for UART1 */ + set_irq(dev, SCH5545_LDN_UART1 + uart_no, 4 - uart_no); + + dev = PNP_DEV(port, SCH5545_LDN_UART1 + uart_no); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); + pnp_write_config(dev, SCH5545_UART_CONFIG_SELECT, SCH5545_UART_POWER_VCC); + + pnp_exit_conf_state(dev); +} + +int sch5545_get_gpio(uint8_t sio_port, uint8_t gpio) +{ + pnp_devfn_t dev; + uint16_t runtime_reg_base; + uint8_t gpio_bank, gpio_num; + + gpio_bank = gpio / 10; + gpio_num = gpio % 10; + /* + * GPIOs are divided into banks of 8 GPIOs (kind of). Each group starts at decimal + * base, i.e. 8 GPIOs from GPIO000, 8 GPIOs from GPIO010, etc., up to GPIO071 and + * GPIO072 which are an exception (only two GPIOs in the bank 7). + */ + if (gpio_num > 7) + return -1; + else if (gpio_bank == 7 && gpio_num > 1) + return -1; + else if (gpio_bank > 7) + return -1; + + dev = PNP_DEV(sio_port, SCH5545_LDN_LPC); + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + + runtime_reg_base = pnp_read_config(dev, SCH5545_BAR_RUNTIME_REG + 2); + runtime_reg_base |= pnp_read_config(dev, SCH5545_BAR_RUNTIME_REG + 3) << 8; + + pnp_exit_conf_state(dev); + + if (runtime_reg_base == 0) + return -1; + + outb(gpio_bank * 8 + gpio_num, runtime_reg_base + SCH5545_RR_GPIO_SEL); + + return inb(runtime_reg_base + SCH5545_RR_GPIO_READ) & 1; +} diff --git a/src/superio/smsc/sch5545/sch5545_emi.c b/src/superio/smsc/sch5545/sch5545_emi.c new file mode 100644 index 0000000000..2bb150c69b --- /dev/null +++ b/src/superio/smsc/sch5545/sch5545_emi.c @@ -0,0 +1,214 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +#include "sch5545.h" +#include "sch5545_emi.h" + +static uint16_t emi_bar; + +#ifdef __SIMPLE_DEVICE__ +static void sch5545_enter_conf_state(pnp_devfn_t dev) +{ + unsigned int port = dev >> 8; + outb(0x55, port); +} + +static void sch5545_exit_conf_state(pnp_devfn_t dev) +{ + unsigned int port = dev >> 8; + outb(0xaa, port); +} +#endif + +uint16_t sch5545_read_emi_bar(uint8_t sio_port) +{ + uint16_t bar; + +#ifdef __SIMPLE_DEVICE__ + pnp_devfn_t lpcif = PNP_DEV(sio_port, SCH5545_LDN_LPC); + sch5545_enter_conf_state(lpcif); +#else + struct device *lpcif = dev_find_slot_pnp(sio_port, SCH5545_LDN_LPC); + if (!lpcif) + return 0; + pnp_enter_conf_mode_55(lpcif); +#endif + pnp_set_logical_device(lpcif); + + bar = pnp_read_config(lpcif, SCH5545_BAR_EM_IF + 2); + bar |= pnp_read_config(lpcif, SCH5545_BAR_EM_IF + 3) << 8; + +#ifdef __SIMPLE_DEVICE__ + sch5545_exit_conf_state(lpcif); +#else + pnp_exit_conf_mode_aa(lpcif); +#endif + return bar; +} + +void sch5545_emi_init(uint8_t sio_port) +{ + emi_bar = sch5545_read_emi_bar(sio_port); + assert(emi_bar != 0); +} + +void sch5545_emi_ec2h_mailbox_clear(void) +{ + sch5545_emi_ec2h_mbox_write(sch5545_emi_ec2h_mbox_read()); +} + +void sch5545_emi_disable_interrupts(void) +{ + sch5545_emi_set_int_mask(0); +} + +void sch5545_emi_h2ec_mbox_write(uint8_t mbox_message) +{ + outb(mbox_message, emi_bar + SCH5545_EMI_HOST_TO_EC_MAILBOX); +} + +uint8_t sch5545_emi_h2ec_mbox_read(void) +{ + return inb(emi_bar + SCH5545_EMI_HOST_TO_EC_MAILBOX); +} + +void sch5545_emi_ec2h_mbox_write(uint8_t mbox_message) +{ + outb(mbox_message, emi_bar + SCH5545_EMI_EC_TO_HOST_MAILBOX); +} + +uint8_t sch5545_emi_ec2h_mbox_read(void) +{ + return inb(emi_bar + SCH5545_EMI_EC_TO_HOST_MAILBOX); +} + +void sch5545_emi_set_int_mask(uint16_t mask) +{ + outw(mask, emi_bar + SCH5545_EMI_INT_MASK); +} + +void sch5545_emi_set_int_mask_low(uint8_t mask) +{ + outb(mask, emi_bar + SCH5545_EMI_INT_MASK); +} + +void sch5545_emi_set_int_mask_high(uint8_t mask) +{ + outb(mask, emi_bar + SCH5545_EMI_INT_MASK + 1); +} + +uint8_t sch5545_emi_get_int_mask_low(void) +{ + return inb(emi_bar + SCH5545_EMI_INT_MASK); +} + +uint8_t sch5545_emi_get_int_mask_high(void) +{ + return inb(emi_bar + SCH5545_EMI_INT_MASK + 1); +} + +uint16_t sch5545_emi_get_int_mask(void) +{ + return inw(emi_bar + SCH5545_EMI_INT_MASK); +} + +void sch5545_emi_set_int_src_low(uint8_t int_src) +{ + outb(int_src, emi_bar + SCH5545_EMI_INT_SOURCE); +} + +void sch5545_emi_set_int_src_high(uint8_t int_src) +{ + outb(int_src, emi_bar + SCH5545_EMI_INT_SOURCE + 1); +} + +uint8_t sch5545_emi_get_int_src_low(void) +{ + return inb(emi_bar + SCH5545_EMI_INT_SOURCE); +} + +uint8_t sch5545_emi_get_int_src_high(void) +{ + return inb(emi_bar + SCH5545_EMI_INT_SOURCE + 1); +} +uint16_t sch5545_emi_get_int_src(void) +{ + return inw(emi_bar + SCH5545_EMI_INT_SOURCE); +} + +void sch5545_emi_set_int_src(uint16_t int_src) +{ + outw(int_src, emi_bar + SCH5545_EMI_INT_SOURCE); +} + +void sch5545_emi_set_ec_addr(uint16_t addr) +{ + outw(addr, emi_bar + SCH5545_EMI_EC_ADDR); +} + +uint16_t sch5545_emi_read_ec_addr(void) +{ + return inw(emi_bar + SCH5545_EMI_EC_ADDR); +} + +void sch5545_emi_ec_write8(uint16_t addr, uint8_t data) +{ + sch5545_emi_set_ec_addr((addr & 0xfffc) | EMI_EC_8BIT_ACCESS); + outb(data, emi_bar + SCH5545_EMI_EC_DATA + (addr & 3)); +} + +void sch5545_emi_ec_write16(uint16_t addr, uint16_t data) +{ + sch5545_emi_set_ec_addr((addr & 0xfffc) | EMI_EC_16BIT_ACCESS); + outw(data, emi_bar + SCH5545_EMI_EC_DATA + (addr & 2)); +} + +void sch5545_emi_ec_write32(uint16_t addr, uint32_t data) +{ + sch5545_emi_set_ec_addr((addr & 0xfffc) | EMI_EC_32BIT_ACCESS); + outl(data, emi_bar + SCH5545_EMI_EC_DATA); +} + +void sch5545_emi_ec_write32_bulk(uint16_t addr, const uint32_t *buffer, size_t len) +{ + sch5545_emi_set_ec_addr((addr & 0xfffc) | EMI_EC_32BIT_AUTO_ACCESS); + + while (len > 0) { + outl(*(buffer++), emi_bar + SCH5545_EMI_EC_DATA); + len--; + } +} + +uint8_t sch5545_emi_ec_read8(uint16_t addr) +{ + sch5545_emi_set_ec_addr((addr & 0xfffc) | EMI_EC_8BIT_ACCESS); + return inb(emi_bar + SCH5545_EMI_EC_DATA + (addr & 3)); +} + +uint16_t sch5545_emi_ec_read16(uint16_t addr) +{ + sch5545_emi_set_ec_addr((addr & 0xfffc) | EMI_EC_16BIT_ACCESS); + return inw(emi_bar + SCH5545_EMI_EC_DATA + (addr & 2)); +} + +uint32_t sch5545_emi_ec_read32(uint16_t addr) +{ + sch5545_emi_set_ec_addr((addr & 0xfffc) | EMI_EC_32BIT_ACCESS); + return inb(emi_bar + SCH5545_EMI_EC_DATA); +} + +void sch5545_emi_ec_read32_bulk(uint16_t addr, uint32_t *buffer, size_t len) +{ + sch5545_emi_set_ec_addr((addr & 0xfffc) | EMI_EC_32BIT_AUTO_ACCESS); + + while (len > 0) { + *(buffer++) = inl(emi_bar + SCH5545_EMI_EC_DATA); + len--; + } +} diff --git a/src/superio/smsc/sch5545/sch5545_emi.h b/src/superio/smsc/sch5545/sch5545_emi.h new file mode 100644 index 0000000000..2bf3a769a5 --- /dev/null +++ b/src/superio/smsc/sch5545/sch5545_emi.h @@ -0,0 +1,167 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SUPERIO_SCH_5545_EMI_H +#define SUPERIO_SCH_5545_EMI_H + +#include +#include + +/* Embedded Memory Interface registers */ +#define SCH5545_EMI_HOST_TO_EC_MAILBOX 0x0 +#define SCH5545_EMI_EC_TO_HOST_MAILBOX 0x1 +#define SCH5545_EMI_EC_ADDR 0x2 +#define SCH5545_EMI_EC_DATA 0x4 +#define SCH5545_EMI_INT_SOURCE 0x8 +#define SCH5545_EMI_INT_MASK 0xa + +#define EMI_EC_8BIT_ACCESS 0 +#define EMI_EC_16BIT_ACCESS 1 +#define EMI_EC_32BIT_ACCESS 2 +#define EMI_EC_32BIT_AUTO_ACCESS 3 + +/** + * Reads and returns the base address of EMI from the SuperIO. + */ +uint16_t sch5545_read_emi_bar(uint8_t sio_port); +/** + * One must call this function at every stage before using any of the EMI + * functions. The base address of EMI interface must not be zero. + */ +void sch5545_emi_init(uint8_t sio_port); +/** + * Reads the EC to Host mailbox register and then writes the same content to + * clear it. + */ +void sch5545_emi_ec2h_mailbox_clear(void); +/** + * Writes the interrupt mask register with 0. + */ +void sch5545_emi_disable_interrupts(void); +/** + * Writes the Host to EC mailbox 8bit register with mbox_message. + */ +void sch5545_emi_h2ec_mbox_write(uint8_t mbox_message); +/** + * Reads and returns the Host to EC mailbox 8bit register. + */ +uint8_t sch5545_emi_h2ec_mbox_read(void); +/** + * Writes the EC to Host mailbox 8bit register with mbox_message. + */ +void sch5545_emi_ec2h_mbox_write(uint8_t mbox_message); +/** + * Reads and returns the EC to Host mailbox 8bit register. + */ +uint8_t sch5545_emi_ec2h_mbox_read(void); +/** + * Sets the mask for all EC interrupts. + */ +void sch5545_emi_set_int_mask(uint16_t mask); +/** + * Sets the EC interrupt mask for LSB in the Interrupt Mask register. + */ +void sch5545_emi_set_int_mask_low(uint8_t mask); +/** + * Sets the EC interrupt mask for MSB in the Interrupt Mask register. + */ +void sch5545_emi_set_int_mask_high(uint8_t mask); +/** + * Returns LSB of Interrupt mask register. + */ +uint8_t sch5545_emi_get_int_mask_low(void); +/** + * Returns MSB of Interrupt mask register. + */ +uint8_t sch5545_emi_get_int_mask_high(void); +/** + * Returns the content of interrupt mask register. + */ +uint16_t sch5545_emi_get_int_mask(void); +/** + * Clears the interrupt status bits. + */ +void sch5545_emi_clear_int_src(void); +/** + * Writes int_src bits to clear the desired interrupt source LSB. + */ +void sch5545_emi_set_int_src_low(uint8_t int_src); +/** + * Writes int_src bits to clear the desired interrupt source MSB. + */ +void sch5545_emi_set_int_src_high(uint8_t int_src); +/** + * Writes int_src bits to clear the desired interrupt source bits. + */ +void sch5545_emi_set_int_src(uint16_t int_src); +/** + * Returns LSB of interrupt source register. + */ +uint8_t sch5545_emi_get_int_src_low(void); +/** + * Returns MSB of interrupt source register. + */ +uint8_t sch5545_emi_get_int_src_high(void); +/** + * Returns the content of interrupt source register. + */ +uint16_t sch5545_emi_get_int_src(void); +/** + * Sets the EC address registers with given addr for indirect access to + * Embedded Memory. + */ +void sch5545_emi_set_ec_addr(uint16_t addr); +/** + * Return the current EC address used for indirect access to Embedded Memory. + */ +uint16_t sch5545_emi_read_ec_addr(void); +/** + * Writes any byte of 4 bytes from the 32bit dword indicated by addr. The + * function will automatically align to the matching 32bit dword. + */ +void sch5545_emi_ec_write8(uint16_t addr, uint8_t data); +/** + * Writes any word of 2 words from the 32bit dword indicated by addr. The addr + * must be aligned to 16bit access, because function programs the right access + * mode rounding the address to be written to 16 bit boundary. + */ +void sch5545_emi_ec_write16(uint16_t addr, uint16_t data); +/** + * Writes dword of data at the desired address indicated by addr. The addr must + * be aligned to 32bit access, because function programs the right access mode + * rounding the address to be written to 32 bit boundary. + */ +void sch5545_emi_ec_write32(uint16_t addr, uint32_t data); +/** + * Writes an array of dwords at the desired address indicated by addr. The addr + * must be aligned to 32bit access, because function programs the right access + * mode rounding the address to be written to 32 bit boundary. The address is + * autoincremented by each IO write operation automatically. + */ +void sch5545_emi_ec_write32_bulk(uint16_t addr, const uint32_t *buffer, size_t len); +/** + * Reads any byte of 4 bytes from the 32bit dword indicated by addr. The + * function will automatically align to the matching 32bit dword. + */ +uint8_t sch5545_emi_ec_read8(uint16_t addr); +/** + * Reads any word of 2 words from the 32bit dword indicated by addr. The addr + * must be aligned to 16bit access, because function programs the right access + * mode rounding the address to be read to 16 bit boundary. + */ +uint16_t sch5545_emi_ec_read16(uint16_t addr); +/** + * Reads dword of data at the desired address indicated by addr. The addr must + * be aligned to 32bit access, because function programs the right access mode + * rounding the address to be read to 32 bit boundary. + */ +uint32_t sch5545_emi_ec_read32(uint16_t addr); +/** + * Reads a stream of dwords of size len to an array of dwords from the desired + * address indicated by addr. The addr must be aligned to 32bit access, because + * function programs the right access mode rounding the start address to be + * read to 32 bit boundary. The address is autoincremented by each IO read + * operation automatically. + */ +void sch5545_emi_ec_read32_bulk(uint16_t addr, uint32_t *buffer, size_t len); + +#endif /* SUPERIO_SCH_5545_EMI_H */ diff --git a/src/superio/smsc/sch5545/superio.c b/src/superio/smsc/sch5545/superio.c new file mode 100644 index 0000000000..b6e5308f3c --- /dev/null +++ b/src/superio/smsc/sch5545/superio.c @@ -0,0 +1,301 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +#include "sch5545.h" + +int sch5545_get_gpio(uint8_t sio_port, uint8_t gpio) +{ + struct device *dev; + uint16_t runtime_reg_base; + uint8_t gpio_bank, gpio_num; + + gpio_bank = gpio / 10; + gpio_num = gpio % 10; + /* + * GPIOs are divided into banks of 8 GPIOs (kind of). Each group starts + * at decimal base, i.e. 8 GPIOs from GPIO000, 8 GPIOs from GPIO010, + * etc., up to GPIO071 and GPIO072 which are an exception (only two + * gpios in the bank 7). + */ + if (gpio_num > 7) + return -1; + else if (gpio_bank == 7 && gpio_num > 1) + return -1; + else if (gpio_bank > 7) + return -1; + + dev = dev_find_slot_pnp(sio_port, SCH5545_LDN_LPC); + + if (!dev) { + printk(BIOS_ERR, "%s: ERROR: LPC interface LDN not present." + "Check the devicetree!\n", __func__); + return -1; + } + + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + + runtime_reg_base = pnp_read_config(dev, SCH5545_BAR_RUNTIME_REG + 2); + runtime_reg_base |= pnp_read_config(dev, SCH5545_BAR_RUNTIME_REG + 3) << 8; + + pnp_exit_conf_mode(dev); + + if (runtime_reg_base == 0) + return -1; + + outb(gpio_bank * 8 + gpio_num, runtime_reg_base + SCH5545_RR_GPIO_SEL); + + return inb(runtime_reg_base + SCH5545_RR_GPIO_READ) & 1; +} + +static void sch5545_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case SCH5545_LDN_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + case SCH5545_LDN_LPC: + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + /* Enable SERIRQ */ + pnp_write_config(dev, 0x24, pnp_read_config(dev, 0x24) | 0x04); + pnp_exit_conf_mode(dev); + break; + } +} + +static void sch5545_set_iobase(struct device *dev, u8 index, u16 iobase) +{ + u8 val; + struct device *lpc_if; + u8 iobase_reg = 0; + + lpc_if = dev_find_slot_pnp(dev->path.pnp.port, SCH5545_LDN_LPC); + + if (!lpc_if) { + printk(BIOS_ERR, "ERROR: %s LPC interface LDN not present." + "Check the devicetree!\n", dev_path(dev)); + return; + } + + switch (dev->path.pnp.device) { + case SCH5545_LDN_EMI: + iobase_reg = SCH5545_BAR_EM_IF; + break; + case SCH5545_LDN_KBC: + iobase_reg = SCH5545_BAR_KBC; + break; + case SCH5545_LDN_UART1: + iobase_reg = SCH5545_BAR_UART1; + break; + case SCH5545_LDN_UART2: + iobase_reg = SCH5545_BAR_UART2; + break; + case SCH5545_LDN_RR: + iobase_reg = SCH5545_BAR_RUNTIME_REG; + break; + case SCH5545_LDN_FDC: + iobase_reg = SCH5545_BAR_FLOPPY; + break; + case SCH5545_LDN_LPC: + iobase_reg = SCH5545_BAR_LPC_IF; + break; + case SCH5545_LDN_PP: + iobase_reg = SCH5545_BAR_PARPORT; + break; + default: + return; + } + + pnp_set_logical_device(lpc_if); + + /* Flip the bytes in IO base, LSB goes first */ + pnp_write_config(lpc_if, iobase_reg + 2, iobase & 0xff); + pnp_write_config(lpc_if, iobase_reg + 3, (iobase >> 8) & 0xff); + + /* Set valid bit */ + val = pnp_read_config(lpc_if, iobase_reg + 1); + val |= 0x80; + pnp_write_config(lpc_if, iobase_reg + 1, val); + + pnp_set_logical_device(dev); +} + +static void sch5545_set_irq(struct device *dev, u8 index, u8 irq) +{ + u8 select_bit = 0; + struct device *lpc_if; + + /* In case it is not the IRQ, write misc register directly */ + if (index >= PNP_IDX_MSC0) { + pnp_write_config(dev, index, irq); + return; + } + + lpc_if = dev_find_slot_pnp(dev->path.pnp.port, SCH5545_LDN_LPC); + + if (!lpc_if) { + printk(BIOS_ERR, "ERROR: %s LPC interface LDN not present." + "Check the devicetree!\n", dev_path(dev)); + return; + } + + pnp_set_logical_device(lpc_if); + + /* + * Some LDNs can generate IRQs from two sources, i.e. + * - EMI may generate interrupts for Mailbox and INT source register + * - KBC may generate separate IRQ for mouse and keyboard, + * - RR LDN may generate IRQ for PME and SMI etc. + * SELECT bit allows to distinguish IRQ source for single LDN. + * Use the standard IRQs for devices. + */ + switch (dev->path.pnp.device) { + case SCH5545_LDN_EMI: + case SCH5545_LDN_KBC: + case SCH5545_LDN_RR: + if (index == 0x72) + select_bit = 0x80; + break; + default: + break; + } + + /* + * IRQs are set in a little different manner. Each IRQ number has its + * own register which is programmed with LDN number which should use + * the IRQ. Ignore the index offset and choose register based on IRQ + * number counting from IRQ base. + */ + pnp_write_config(lpc_if, SCH5545_IRQ_BASE + irq, dev->path.pnp.device | select_bit); + pnp_set_logical_device(dev); +} + +static void sch5545_set_drq(struct device *dev, u8 index, u8 drq) +{ + struct device *lpc_if; + + if (drq == 4) { + printk(BIOS_ERR, "ERROR: %s %02x: Trying to set reserved DMA channel 4!\n", + dev_path(dev), index); + printk(BIOS_ERR, "This configuration is untested. Trying to continue.\n"); + } + + /* DMA channel is programmed via LPC LDN */ + lpc_if = dev_find_slot_pnp(dev->path.pnp.port, SCH5545_LDN_LPC); + + if (!lpc_if) { + printk(BIOS_ERR, "ERROR: %s LPC interface LDN not present." + "Check the devicetree!\n", dev_path(dev)); + return; + } + + pnp_set_logical_device(lpc_if); + + /* + * There are 8 configurable DMA channels. DRQs are set in a little + * different manner. Each DMA channel has its own 16-bit register which + * is programmed with LDN number (in higher byte) which should use the + * IRQ. Ignore the index offset and choose register based on IRQ number + * counting from IRQ base. Set valid bit (bit 7) additionally. + */ + pnp_write_config(dev, SCH5545_DRQ_BASE + (drq * 2) + 1, dev->path.pnp.device | 0x80); + + pnp_set_logical_device(dev); +} + +static void sch5545_set_resource(struct device *dev, struct resource *resource) +{ + if (!(resource->flags & IORESOURCE_ASSIGNED)) { + /* + * The PNP_MSC super IO registers have the IRQ flag set. If no + * value is assigned in the devicetree, the corresponding + * PNP_MSC register doesn't get written, which should be printed + * as warning and not as error. + */ + if (resource->flags & IORESOURCE_IRQ && + (resource->index != PNP_IDX_IRQ0) && + (resource->index != PNP_IDX_IRQ1)) + printk(BIOS_WARNING, "WARNING: %s %02lx %s size: " + "0x%010llx not assigned\n", dev_path(dev), + resource->index, resource_type(resource), + resource->size); + else + printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx " + "not assigned\n", dev_path(dev), resource->index, + resource_type(resource), resource->size); + return; + } + + /* Now store the resource. */ + if (resource->flags & IORESOURCE_IO) { + sch5545_set_iobase(dev, resource->index, resource->base); + } else if (resource->flags & IORESOURCE_DRQ) { + sch5545_set_drq(dev, resource->index, resource->base); + } else if (resource->flags & IORESOURCE_IRQ) { + sch5545_set_irq(dev, resource->index, resource->base); + } else { + printk(BIOS_ERR, "ERROR: %s %02lx unknown resource type\n", + dev_path(dev), resource->index); + return; + } + resource->flags |= IORESOURCE_STORED; + + report_resource_stored(dev, resource, ""); +} + +static void sch5545_set_resources(struct device *dev) +{ + struct resource *res; + + pnp_enter_conf_mode(dev); + + /* Select the logical device (LDN). */ + pnp_set_logical_device(dev); + + for (res = dev->resource_list; res; res = res->next) + sch5545_set_resource(dev, res); + + pnp_exit_conf_mode(dev); +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = sch5545_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = sch5545_init, + .ops_pnp_mode = &pnp_conf_mode_55_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, SCH5545_LDN_EMI, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x0ff0 }, + { NULL, SCH5545_LDN_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1 | PNP_MSC0 | PNP_MSC1, 0x0fff }, + { NULL, SCH5545_LDN_UART1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8 }, + { NULL, SCH5545_LDN_UART2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8 }, + { NULL, SCH5545_LDN_RR, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1 | PNP_MSC0, 0x0fc0 }, + { NULL, SCH5545_LDN_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_MSC0 | PNP_MSC1 | + PNP_MSC2 | PNP_MSC3 | PNP_MSC4 | PNP_MSC5, 0x0ff8, }, + { NULL, SCH5545_LDN_LPC, PNP_IO0, 0x0ffe }, + { NULL, SCH5545_LDN_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_MSC0 | PNP_MSC1, 0x0ff8 }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_smsc_sch5545_ops = { + CHIP_NAME("SMSC SCH5545 Super I/O") + .enable_dev = enable_dev, +}; From 72f06ca554e6f7b155a6b4e2b8ce57942288ac2c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 13 Apr 2020 21:42:24 +0200 Subject: [PATCH 084/405] mb/dell/optiplex_9010: Add Dell OptiPlex 9010 SFF support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Based on the autoport. The OptiPlex 9010 comes in four different sizes: MT, DT, SFF and USFF. Tested on SFF only. The other PCBs are slightly different, but they are designed with intercompatibility in mind. With small devicetree overrides it should work on OptiPlex 7010 and other OptiPlex 9010 variants as well. Signed-off-by: Michał Żygowski Change-Id: I88d65cae30d08ca727d86d930707c2be25a527cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/40351 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- .../mainboard/dell/optiplex_9010.jpg | Bin 0 -> 80412 bytes Documentation/mainboard/dell/optiplex_9010.md | 147 ++++ Documentation/mainboard/index.md | 4 + configs/config.dell_optiplex_9010_sff | 9 + src/mainboard/dell/Kconfig | 16 + src/mainboard/dell/Kconfig.name | 2 + src/mainboard/dell/optiplex_9010/Kconfig | 69 ++ src/mainboard/dell/optiplex_9010/Kconfig.name | 2 + src/mainboard/dell/optiplex_9010/Makefile.inc | 22 + src/mainboard/dell/optiplex_9010/acpi/ec.asl | 0 .../dell/optiplex_9010/acpi/platform.asl | 54 ++ .../dell/optiplex_9010/acpi/superio.asl | 13 + .../dell/optiplex_9010/acpi_tables.c | 9 + .../dell/optiplex_9010/board_info.txt | 6 + src/mainboard/dell/optiplex_9010/cmos.default | 7 + src/mainboard/dell/optiplex_9010/cmos.layout | 95 +++ src/mainboard/dell/optiplex_9010/data.vbt | Bin 0 -> 4281 bytes .../dell/optiplex_9010/devicetree.cb | 99 +++ src/mainboard/dell/optiplex_9010/dsdt.asl | 32 + src/mainboard/dell/optiplex_9010/early_init.c | 47 ++ .../dell/optiplex_9010/gma-mainboard.ads | 19 + src/mainboard/dell/optiplex_9010/gpio.c | 208 +++++ src/mainboard/dell/optiplex_9010/hda_verb.c | 36 + src/mainboard/dell/optiplex_9010/mainboard.c | 191 +++++ src/mainboard/dell/optiplex_9010/romstage.c | 53 ++ src/mainboard/dell/optiplex_9010/sch5545_ec.c | 726 ++++++++++++++++++ src/mainboard/dell/optiplex_9010/sch5545_ec.h | 28 + .../dell/optiplex_9010/sch5545_ec_early.c | 116 +++ src/mainboard/dell/optiplex_9010/smihandler.c | 47 ++ 29 files changed, 2057 insertions(+) create mode 100644 Documentation/mainboard/dell/optiplex_9010.jpg create mode 100644 Documentation/mainboard/dell/optiplex_9010.md create mode 100644 configs/config.dell_optiplex_9010_sff create mode 100644 src/mainboard/dell/Kconfig create mode 100644 src/mainboard/dell/Kconfig.name create mode 100644 src/mainboard/dell/optiplex_9010/Kconfig create mode 100644 src/mainboard/dell/optiplex_9010/Kconfig.name create mode 100644 src/mainboard/dell/optiplex_9010/Makefile.inc create mode 100644 src/mainboard/dell/optiplex_9010/acpi/ec.asl create mode 100644 src/mainboard/dell/optiplex_9010/acpi/platform.asl create mode 100644 src/mainboard/dell/optiplex_9010/acpi/superio.asl create mode 100644 src/mainboard/dell/optiplex_9010/acpi_tables.c create mode 100644 src/mainboard/dell/optiplex_9010/board_info.txt create mode 100644 src/mainboard/dell/optiplex_9010/cmos.default create mode 100644 src/mainboard/dell/optiplex_9010/cmos.layout create mode 100644 src/mainboard/dell/optiplex_9010/data.vbt create mode 100644 src/mainboard/dell/optiplex_9010/devicetree.cb create mode 100644 src/mainboard/dell/optiplex_9010/dsdt.asl create mode 100644 src/mainboard/dell/optiplex_9010/early_init.c create mode 100644 src/mainboard/dell/optiplex_9010/gma-mainboard.ads create mode 100644 src/mainboard/dell/optiplex_9010/gpio.c create mode 100644 src/mainboard/dell/optiplex_9010/hda_verb.c create mode 100644 src/mainboard/dell/optiplex_9010/mainboard.c create mode 100644 src/mainboard/dell/optiplex_9010/romstage.c create mode 100644 src/mainboard/dell/optiplex_9010/sch5545_ec.c create mode 100644 src/mainboard/dell/optiplex_9010/sch5545_ec.h create mode 100644 src/mainboard/dell/optiplex_9010/sch5545_ec_early.c create mode 100644 src/mainboard/dell/optiplex_9010/smihandler.c diff --git a/Documentation/mainboard/dell/optiplex_9010.jpg b/Documentation/mainboard/dell/optiplex_9010.jpg new file mode 100644 index 0000000000000000000000000000000000000000..a5978acace499b10ced0559f05eb9489f0041d70 GIT binary patch literal 80412 zcmce-by!?M(=Rw!f+n~V2rdJ`H9&B87#JLe8Qk3?xCUp?;BGUxC3tWM?!lb|Pap|9 z$@|^C-^$%*_n+;NQ%_Y_{kp2{obEmkiw|D`gsO@viU2e;G=MVd19;d%uUCVW@c zx|s){ECB#B+<$HTFSGsM3kYnWo)7>4jR7To1#$E6LeZ8eTG-di?Ju2)qDdikRyHWQ z8bt#=Pz6NMi+}mn|DjL*(zgF-bQB37_0ZRqL-|IEq8V)e8*TmHXo#JMGb)cDDi5=b zvkS^Ty3v1Vo4<6>U)tHp8&$S{>92?QP!|I|)Rh_aqXj4dQ~(+PZ2$wn8sH7E2RH$| z0Nkjn3yR|j&_&5*{}=ky|May{TGl8ndjJHbArEi`I0LNy=>z`O0V)qF{mf-#q^CCr_S`5RtHwk+EtCaSLhve@+j*03vL(ujsEa(1-x&L}(a9Xb=4WR7GN-x)<8t zNc>mAz(hyGdW4cu{S~0n{}7*I6CVH|+@8^F zedqGu`Mm4^tiqE#N}xxrZS&TW=>6SB-OApC4vy@4ZVGv=fx#D?68jS7U4Ywa7lt71 zt0!R&?FCb;lNL`CXYRC=hEC94$-Kh++m-*NhUa$fV%Q0b^`%0ChInC~w;E+FK}QR0 zl+-riX=XBJbr6zB;^CTEJ049IEbu&ZqPPV|p(G((L97|LJlx5t((ai!es$0(0N%)* zKA;veCHC?nRdh1dcYgKPKALQ~IjwrHCY5{%ZWTwmU3Px=SvPy@{mJR&t*NL3i@g3w z-(vI(&Vfi{<~SAO$n#SVb1)BrRn=rR54zvkMX(G@;jEfi*V(%Z+7K5Srnx+l97}TY zKH3saZkv5;vf~#kL010HljjU`$(lOOKRiIX;5_U5wz#mE{cmM;vE$oUl28878lk=U zVke(6cIWGuk!)BcnJLK6jD+)>87Lm(WNE169KG^hc8E)>YTa43wGZ$wOj&L|44Qo^ z#|4s9eqF^ie2rc6&m(37)7_AurLgwpOHyP1pF<@z;{q!(FS~BMzn6Rz$wzdrKg&VS zoVA8}53F{@98%kCmLz!XZjV7S42=;fin>9TLft8u)Lt5m>NgvYouEFhf?+!b+)1#q zM7;r>Lp3#_)aAea(2|xfykLR|JM>fqzjVkEQ`Hz`70_Sn8{P1=c(l;Bdj;RvyP~KF z5+@P}b2QRktA(%c8^2}ch-V$*oD!^p`VEGAA2mb}?5S0m+Z;Z*%1JiL3-&R#N;}S% zEEAyTI$lctT!|Wi001zHr|GY?9dQXENf*|WE%j=loGn`eg;mq81@G^%PXf1G#(%yl zQTc!);xyJ|+z##HAG^xaPgTNV;SzV+j86Sr#gP?Rr^}f+4-={$t6-Z?QW;5^tQpO^ z;xE!-Y)N-G=^B1!X!jQin3qwjdpP@b*yiMP!4Ezf@GM7>^QlB)$L#5*?0I?6hH+lE z#;C6r4ou;bc(Y9|c}MNw+z>IBmjR{t8`>epfEw$Kplz??cdU9fIyqY(+SLv4zHmD6 zRF3owuefKnynrdqIs65}B~jjBe==A-TX8bC-n!;FI}aw%jGhb?Nc=dp5ovNUJbBns z_GaGNJ3GJV%jqU~aY>o;2sfb%|9zTV4KbIgAvSSV9I``u0xHrpP>&RmOa)IPpwRML zUn;J6=73@{P4iNB2*~&^77p8-!Y)|?brs35(n*@hH#2i zon(ZN-;76v)N?X5+r2n`1Q_l6G(rE>7(@D({gFDF>LO3p^yQB6+P)%^7Zw5;AL%-& z%}ZMY)5P^w_L&s-Rrk-X+J9YVB~`LFrmoMeBwpQ~uvH(k+Z7(Xz z^%`Og11r&C;hf?5fys?NmftV&RBPaNIQlU)ECJ-UB7J6*iWHvxAeWPz!z`COk1u>A zMiu-%IpUm#pqi8SNX$=Fh~Ww$>vl^-=lC#%hJz@-mI-A|o!mdy08fl zx41nA%GLdR2gk(&c(@)b#oBXlDxPD0ShfqJ>e8rq%^;u6(rEEX=i$6bka@ySldxE{1C>P%zfPE(ZW_22U;llk2~nYq$-Ioufh|^Qxd5d zE1NWGqwHCx`pVR)$a7feS<}3}Xt*K`#60s~+KLj*Ag-%w(iLZfEU+7>e86}rPPd-K zG4L;wyug52lbSRrJh4uEJ*UR%csng4B%$$N!0=cNqS!d(vxIXKvPkqf$8#}=`MlhW z-3bv?$rX9WAugvsQ_UWg`sWBQBBMp-Po2;AmJX=mj1T5=jcTs=UUpSZfLWQx;OfLE zFSNqu+6-({+r>)jug^zD>y%9XVPIh!5W^KoNa?8fiI956?RIUVnWpik_{Bwxp74Rd zWthUiycUZf$jr68JH%fe;aCbJOG=$i5&FFJ<+mPRvWIOMxBA$^-zeGp3K{I2b|Om= zHKLa~QfYx(8dGhASJg}O?EJ;SsaXL! z&TWIXnU}ZI{NI^g!4UQonk{p22$iwD@vG9#>MeyxV=vaqQG1@+ZED9CkbEwluK$AI z_u~^iDz_GcrN|MfrLJ}11o^UGBgR<`VxuL8E1_om4Vmf}2Q6j!Ri;TLYDe$)`Sz3+ zO6pe|Ih(Lxf?C>!)gGG2obh8du{f13|GSw@Z*xHjqp9vjXHY>uY=R@)ySigw%HGw&oL-p)CnaF2^7fi}ruus5Us@PYEKLbp#{89ZAK;b`2&I>;K;@?~z_+F^F8 zfP5((=gyGLozF8)3v~-JtH>MwZEUWHd2Y$jT){=mEYb7j!T43nf1omTYm4Q8y5mAZ z0iKe4tno2gzK1ub=iuT!F7`LomlH zc?+;noAiKy*0BlqoS|=J4nbRHjuXvM1}2%ym#3@NEzj1)x-Ikq|HcoC&{$D@9*qo} zR^v$vnYr6FwcImkw5B2VNvG;=vygX*8r_7WgKF^XCBgi;3(U956zSPtA$(^5{!}$n zs!}uWqDvqtDVB39s;S&aU3nNZP)G*a)yOmGh&!y-@)U)+*3DS{1xi*}dLwM*fwQ<2 zmTCQkUuDoZnhG3lXsH>e2g1Ek=8NP(KTZ*F4aoN19n58J-H$DH)HK~~KlLGZ8zYUm z_NIUjC+v+Cw8tzpnOoMfYw^tYUagz2iyI#d*jr$aCKo$KH5;p)K4+tbi^71l267vRTSR zioIo@mTIA%)iBt(XK0#gKQo^fld^!6z4{B2nPe+sgb`6Zb>Yu2=l83Jgc@FD5@Tbo z_j+!Q{MXJ1?$hFRv5JJiWCyv?SI*`JIGKG8>lL-M#Y1+HgWm+0c8^{15Xtj(o;PGe4L zzBukTAMT(G#;U27wU%IsAknqy5Fmz_2vyH8ulcNw_LbAt4wWZCa*lnPCj16qFMl6t zIJ9O}jLo|X-^`iiCc5UcHJyC>fWmqFlsnKYZXQC0nJ3OW^4p->re*c#HOvM&=t-QY zn^(c8P~E(({&|U`xtwfB;7wi&!K6U8%dg+gj~&(ecK}{oOiarap7E~5KlWG0=NY+= zxE#Qh)wXS8Yr?x`RC#-1|HC1wmvaOB>ML(GNZ|Xj!~>O!kn%f(LX95hq=e86XpaUQ zr!BAI_#B?yB5aHtcACUeAJ2(4zw4>mQCoin7H%ZhB%` zXw!V`O$#S+g*z)Lsebvj<@0iO)g|`rc2DsDl0z3cE;mo$&KaN`8=$Xa%P5A zD>Xy9_VG2smBiuQ0a9cxBpw@l%=7iT&e&vaV%Xu5UhdlkV zR8DkC0<|4=9ooqZw}d;FgOI1IT4fXdZ2#2)vDhyYMyX|RX6(PIy)%K&F7VFTERBa{ zn5kDY)MZwxgM=zr^LPeT4wbUYDqdg>_u+BGq%P~_98KfU(D8ee&m~)qAGsS<%@hvv z6wT)+J5G({zD(M=qYU<761x%lJD%dp3m2&mX|cR4CwSH~V}{)G$#Cyh;_|pRT1nQ} zq|PNTk3qg=b8vQOl20?i4dfT5wn^gz6TwcalNFhN=9V=92Qs{tV|JiaU0hU_#ir4w z#7Dz5;^bzT<1dfR@M@t~RDF6&3x5O0_?-OWU0Ez!yh;2*6+X+=CY{;E5}&D7Ck@o7<9OQLQ2` zR)g&t2wV9NW(`=u+EYMjDhDuE!|~GIs_137jTjt9jm0(c2jkPJbv4#I07O5Axf_$8t12dZjkNVW)_FlJd z$pL@f%|z}?)b6o}cnfh@H@{KPowm(4PB7%Z1D^nXxlo_Sib4-IQ%k*J>?_OX|Lkl~b9IvEG|*D&beiYl33AZ$S@2%eu)DOc ztiD|Ft`Y1K584%ATPTWb{m3^j6VAqU*kEYAbItt^<+)a>t%lSpD^qDj^Ji%t^NN%r zrZR}W;#&>1qPN?u6v~UGrgC3d+ibF%bB^N>j${c?0b%#pKZIf?4W3BXcG5r?cRcxZ5 z8Yf8`V8A_j^x?ya$GhYUv9=J~vIsuUia3qSIt#H}#nW`#H^##tm+SdjvCAu-lDVA$ zih#NAmuY?R+^MldX}DdI>S~-FRj>YnJmt}%-b)Yfbuia0Rsaq-LVHP(-UZ%8Z)AO9 zp5zp^+p!mlnU}H{b$+$3)}J^lwYs&-K<3SMn2V_uE)%Fg%&PZa9JU<&@ElcMS{?yXhiuozeb>Af<%|YR#&oN!AsI`M1?c7#;|HWYrSKSeQy=)KGkkD`O@@ zEoBy^Q5kQ*T+uc9$TQx|F)#s%t0$DrG7(I7y-DtGQ!t}KLNmr}18+BP?9qDxKE3kp zRLXFN(XAg&vZ)<>EBX2t>Ty0Z`N>6bm3Q)%0_Hd#R@Ph=N80;%aaOHY@usSR2bD}L zy1=bn4iSeVhY*kI&G|X66$5u3d~-&|(HYPg)b7+#?0s9exx#X{t(1}J0(9A7&e3RX z4@w!47uGSqW{!CM7e-Zq>g7F&dc^P>b;J?0cdyw&)TOaQvqzgOAugLVJMKw!74v0z zl{Y0@o_pzSd4 zvSo=c3`Wmz(ZUhXk+fmak{okZ^*2qH07b`$xE#^PO)C^oHriv8)!AkdQFF1P;1}~> z{M8B|JJ+C&p!=7<>ey9Yt4 zfqDW5ay(%kfg=Bc1wh9I&?Zdb43O~eq1I=(hWUX9Z1_|Oh6X831in>&Xn6^C>2J$5=>Wu58L*Uz@^zP{PHK9c?s`t#|#Vq|jSA2x$f zT!3-YtFk}CZ~<1EvCQ9l@svhL>!zA?s_cD%?X*IIl)!A+~0!LE<9s+1FC#d$xD*Egh$T*E?j0aMgyzR@J` ztuIjl@1D(A2tO-Ra=BR%5)Ln{W-qZ!`!RS1K&R0RG5I#%U%M6%+A*eCE>OUHESN

1|f#1AtO}Ob%=y^+B^-B7a*HAz>q6 zDUKL#^1XT+|A{NLv?V&!|2WMyCNSFvuj?Y+M;9#tkospn;S71k6IqD}Ug;0+>sfjh{?l* z&|IzD>>{mrR|w^iR@m0wCx+k)bV{;8p0y|^Bq+kI#(CBx?TM|%O#D;3TlD+t!ws86 z%f1bG5=Y3FVJ+81Z2qr)D_xqZ-MuzYAW0`^eqCWMQ1!AjzT)vKs**^}db-ULReklz z8EMsDk~&x8GO`g2;B9>iThr$EY!&x)B`V*PDIGeNz+w4 z*v@0|#q6z5XEyd;QyCgS-Rls&EYmNTiV_d20gqddNW$TS)*9=40mAkYIK zPPhxg$20>hI`{h1xNSc;6aTep4iV1$NF6pF)h7|N1i@s|mHo{_#bx1V%emc&wX(tTQs1JL@_<9xVxgHu}v6yzed&u#%Y|~>C6q{M zjTKhGM~6)_jxYvj#61!*%GlLE3 z`qFr-x=Rdy_9@=(x9bTc5W{ptrg~)i<5XbzKz6736&E@A zKE#@n>GffVZG}cj&M${%Vfu?04+dSN!Kjq#O>Wo&zk|}6YE6v7=DMzH1UGxtn zi74E5Wzfu)24cS5AR=R}y5Toz$(B~gUFZZsH13=@F&N+D1?Tr}kbZk{j@Ed+_sQHSCU?9Gms!vwZ@<_pQoZR*1W!+sES-Q+wC2>ktWnar1(1H z9mz|7g2yq~CJ38H+ztL0ph|o*dGo3GGE1TSp+@!hs9mbu$fnkDm9+MxLXfA4!%C5i zW!Nkv@R*kg$2NX_eA_kVUOGIV{)#>(k?f}EdQq9~g5uIUdWDY+T7)nf1f6GAf=pS^4$1|OGIwlI#X8TP^iQ{PT!GbLkGV|jcSLf2nGe-4V_rRY3iyOZs8 zJ~YA5Fo>$L?eK-ydsEBV($HXFyuYW+79<-q!asRVsP?$@8|=KLM-ml>MCsVO_E0FQ z1etv^Z_6rFyr~s5m$4~`4BP72wIJJu>2A%ejw|V$Ik}ap7h14t4}I|2r^8luQTfJLePN z;T2bdGNCn^-bu`xP&_HV^H76lj5^=$#yA&)D>8+-Dz+<_47h5Imp}OEY55q8C-53f zJwF_kF&iLIvMw^vw)zA^Vlog!E{z9&&y%Ptx7+J`tk=< zPFS9Wwp1_nq=ipx8tmHF6fo8H4j757aN^w%+Hi2v4k;K^D6ul8HaSfe1$pJn|jUM5b@~(-_UVT$5p0^izLz@-gC`Lf1=*_8f zqD|9uoFSDgM5JrW?K))tIW%G8S^mV}mGq$0i=(nd)t3(d$cw(pU$ZL^Z-hu) zbNJhpE8X{0rVeVE5|2u66Rslen`^kOR=E!@de-S6rT&!hD*V(owcjbZ8x-WLh>FJH zuW#CwsA=X$Xl1??`{nP%t&m)$051QdL=(Y)+d4!6_DNQWce<4kYkFmcf#i@FABGQNQoHIjZv6bbCon0IIdRY9J_57P;L ziE5gYnvd&J$#FN5wG6k{8TSe7^?Zu>2|iz;-)|DU0AY0aW7 z&2e*W_kbzfLScvPvHGy;eW6yeilvW94(P@9?d8IyTSwm~!LiX*&T$NKL;dR5gM|FL zLLn`9RrX{usqYbG(rQY+T4wJIhu<|W!)!EX&;gihsh(^3JTZv`9kv2gadC`4P0rV7 zQ1GQc#p6gr5dM-XqudN-A5<&`_y0dP3jM4 ztM_)Hg8ih)$s1k+4Elf05lBg6o$zz1H>B zd2oB^i^V-+m;jIx+LP_81c6qifgWuQok?#H4~i--OWU*@cHn$IH%%|!TJVH`LYXjL z+_qFWGUm*Ny>V2mx0IUB0L^ay&;{nmg1?3+Tne5L=xJ`3J)*|kqADhm&YYuY{&>#u zj*`DJ5aQA88^`kg7wE^-E8%uT%aCE@_0{)4uRj(IodxOdUw}?w))yWSTp4@qprnrT zW69pufqc5WA1Ag5!?Uu-65>Z%oz1noN-Qpg0+AVa+O2j#w2)1PBQ8Lzx02}@CUR)~ z0_LciYva%}O#T6Yn`nivZuGG?(d;-JL67Q%*&`2tN8hW4?hfL2XMXTEIewazu-=1<( z#&x`wX4B?v);dPD{M(N`ogC+n&#%tA?n0#(lAg9nZi==A8W+tTA*W z>cp=(UEVngemlf79O+KlAsNH{K zTD4p4VChQKP{@2u)km*j-q#!TNB>uT<>WKLOv1kFd7syu?~6cn?L4?Q&l3`;KGfj` z1T4GFjs!S-pXH!;s*IkA>XP92Bm--n_u!d5!WM!GahthGI@^6p=a1Gb45iI~Z}eO$ zTsr@LGV4B+#t7R{9_#!Jx0Wk6ga@d!+ zD;?zWb#k>8Cr(&!>%2|l6V#Jo z<(aC&V#kbO2{-PJNgaf;x?9z} z-%+pLRpzOpjRkz>oI2&Bv@JP@9z7GFENc^c<2JO7T>S+K)D@s~H1X3rkrEF{{q?ct z*y=??zli9&O1l>gu@;ulqiD_S3T^IIv5GcwklH#49!PlbJ3Cu-{H69X9lUAV z_QUC>Qo7-L*`lApRoU)uw&k8ig9ku(o~EQvU?^p8iSN<0E~t1^?j`nTu(6cq%#ZH= zy77qR^`o?Kx3c8BraI-`>^sXDJwC}t`RNUHuDCMStY###NA1z zVNOV{KE8pVEH5U1O}MZKsl|s=e4{@v&O*2(D-uuENqaU8za(Z{gf2uQQ$KYiBq%DBICZ`|6ax+w`9!|K^a z5Zo2r51JjR#LC6fYL5Q`!=-L^I3{vqnx@Aj1MA+&-ujXxwYJ_jBi-tk@;@YQ{n_6} zE|&*q_vTyurvRC&v1ns~l+pr|ZFb_Xl^E(q2w4pbMi*2Z7<){FBxl!Ghv%90__@2b6IIgzRkf6h|xc z+6Ke&m>xrc$|nV0eLtJ!CDT;+g2O^-UVf~dbb$12YBdKMp0fW81s@)dZ%9H>Qs9d4gTgwDBv~k~owom*1ooeK z|4_5MHQuGunpdv4FGIu5g`!byGH->fdu#DC_{Si34d~hT{tNCHM0*@)(%VPLiln@Z ztX%@E052`7e67V{+oXr5y<+TE71eySU%_hT2EBs+d_An2fmEGq^oH1L&sZ41m)-+M zqQf6E8ifg2Frib?y$fIfWeILu@xo{vA@ZN#SIcgt5fIV+a?4<9b#Ltl(C{Wle&!M1424LI`1qrCPrn z@!U(HjdFj^r-xK5OEk{O$o#XKMgslPuaC9EGyB5G%}$ORjA@HzU7d?R*~5fM(d)#o zj!j@zZ>{~?$=iN&`}l<>tv_{0z)1X!z;6wa#GJRL9cyeH_~!orVDT6WCA3yS4j5j% zXz{&c6j%%hC|fb$E^W+Zh_T2EeAOzPI6nJJ>~yijc-xIt$0D<4JkYeT7t%q}z(^?{ zYI`9?u9-2iFlKd7wix6+xtEx6O??t3C3c*1J$l{DpCp~td2HEN-a=qCPQTjvt_LP9 zfu`${^@4=_)%!9RUPF2Q&GtwAua=ngi*wS)Ze!yq8gIfDA8SrbUVYrIT<3N5Yc~13 zrbxuoBPmOCYoJDJ0_ng~Z*<5=N-B^UuqZ_g=k`3?ki-A4l1!FsGoi-Qmt1$KV03>7 zLEAX|Md$U$@e-&$2+P(nGw#2|_OzJzi9h zWrO}wE&2?pJ?E)iEYFWF%m=_T_~Gk!n6r-Mk0y>JEei!P7kGVYG)F2Sy7izjRio$X zTt4^$G#i*hr|jO3zBxX^vYm-z30WL2QAS>0)1$w88;Gw?r<|t0`I|+xj?7A40#+~5 zz-L`fobH<|G!GU9wN?H8wCGK?bBzr@B7YwcSrhHBf~Re1(EJN&nuVS^4cRR?=`&P) zt+a~G)9=_rcH7`yj?Ex3SP$=>URA}#{tPr8WIZZ_F>qy)&$=jrp8hxrj_St(M~%Tw zL9!=KT&xsuZ$ssnvZFw{E0oH zn)%)yI77s;@Msu^@PWZ?7L3Pef#BCcfaA(EY$}DIqS!ME+R+i7;t2<6JeaKHrMOqa z6GqG(E_fQ2Fy@!RLHj5fmc*^Y2u|nlIJfe5_~=F3LY0l>@3%Q-np$0aed?{X+v*ZR zw}Z<}EnUUbpTP%_@oaQ{ zLJOkF?!YbZkf43lxO0A9i2u+1{roK067rKztn&eTwvf%6%e1UnW9zj&%sr!iwTY&7SL=zLznq)#+A6$@7Lb~@Hl9B;T)?ZSFg zHUp7q_LzD$3L`svfe~VSI+tHj19__cr*0o_=EK0}k~h_vLj1@hi}d`Zxm&XYHG8SA z^Vf^c1j{DPjdAmVA~a<6xm?<@^E|a(+c^_(!s*#GgB6mGGdiW@4oK7I+96pXn(W6F z`Xh+1B~JUNCirp1ep9l@mYteZ)Fvka7-xW&7VUBPIfiE7>{sd9D50`xQ!{QV?-3WF zuXGQIW+sECPmCFvz3E01t`(y7E{aH zbI+Q~Vt)Syk)&|6BzXFAA0Nrf3=GaS0$+QFF_ymSOtVi4~+f^&*E?SKDfT_zNV6`$f* ze;<+4AAW?M-$vA)%HYk;wrW^AZQi9eWu=+@IEDzdki_0vo4Q*iBw%E}V+bOA-BiMo zWWOD*$ce^jzzuOp9$W^wTOoOqr)6V)O8W00y7RG81-<$lta+N88v$yO&anFGpBU|0h*nN$ElZcC8^ESC*qnK7YXkOo@{?i1 z8QFr%t|BDRY~T`XR2V#rXM50M*kAU=6e!LsXZ(68BCVeNlfoEBR6N|O{{vrs(krBA znTIcJ)(gg?mqsw5>p2XMSCugfvz8jMU3jEL0*u=VIeugbqFRBE10){+7JBbIn(2Rw zQX7EfT8HXHkU;W9ieFksk}!$YQj?iK1^{+XO#`_|G>HTvbbyEH8i<>eG&=A)|Oz>zPO#H+5xNT>I1 zkDYK5?r@5S76kZf6TOebL#R@O1<2o|hsSmOWYNe<0Jml0fi=`-Q|J&X0;RL_idE3; z@sJ#7ytfcbCCi2l7T()pGWwKCEFSYRv~O!%tp)cD+_2^D@~GcxMvgzE@$rtJRq6Ga zIMKiJtAE|(=28$T3jo2iMq_Wy^MYB57ne2yS z#*Toirp9}rg_HXyk%V3_X(h;Hy`4B4`Vn=x-)(Z0J$?xD- zTp^w!&MH_@p8?gHzhwfdTudmr-rwAnALfWo^2Zd z=W2}`vKC09Yzp2+5G^kaB`Z-W|ESmJFL>Rs$d@+TTsc(%Ec1s_vnZPsZPo)4>lGab zoSd7ey@8}1Z^$NB=1&3wPOK{+&Sr70YLuhLuf$(dyTcuhhI6ZzUUBoPz7cng3;I|y zZTjpzWq^RxblD16lsiXwpmKn_S;$XVC6k7PAx|5ZY`EW$(n=?;O5#%+XOYl(v?W$l zn5HmUJ8^Yo()9xFaT4%aH6b#nj<)A++JTYgD5pvDLqUO|B;!I_P2h9ZPY(e2TH_I2 z>JlXS^QkTv;&t7&RZ;KY`a8^8Bep5t$Y>zbC?}@LDqbOyC?*@+r~SIbjn^^sgzS-f z@wUo1lQDG%}=(p2Y1b!oBPWLSW->71}I|h%*%GOxZyvf3AN8WQc zg66=A&Ju$C{RX4dpW-leuS;(z*On7A9st!k_*=E^hN2FUrNxttg~25xCkOcu^?O{~ zMLns(iW?QFVYVgqd^_7^s+-c_ihKv#6|H80m`_q`1&1~KSqc^p0AJLOq7drcn7{jp z089*QG^~I7m}o@kgbWzOyqM4VUXd`$X!Gm1lQIbiTD_V6Zt0d(&~yH8TM_jZjWpT= zAaO=%w6#QU4N*y~%X3nv!A7`ne@DjdW+1EV#T;IuS8A_VLc^KpuE(irmtS6jITZdagU8 zMEfxEsjvoI`BFW{9FJOvbH-D}(6CB3`j#GJRO_eeM~ic3&h=c?V(-SFk*4dd@*+}M zPVh&hKC6oeF{7p&L?KJQ;SjZ>Mvd%Yda| z<7ytyK&rb8g>p$x7nv{FhXmWPOCv7(tGlc`qPiLJ!&3Nn2e0<5;L|T9Wu?~+LP8ET zqs{3}#@?#pYhv-LA)TJSsf4fYac6wERG4?gctBAMu^amispr-#*0`ndJ!eMy&6J`E)A#?4ETSC*WFP|ey&a(*mnY|JasPH1jY z;8IP|GML)MGf@JETq4O6!v64GiwBrBCK+g!y?FF>RSP|c#GZ}9xqoLM`MPjSF(16* z?4V?*#&0ms30h;;U(*EB@}(dVHj}smdCKhrHeHcNpXR38Dqj*mw?UZq6HQ{8JxQ)o zNass6TL!jKAlfo3Sr6mmlvf-)l2yKD^C+BD4Kt_25h$k>MHEQ+H{!*|&gMX{8Qx+u zn2v#as3f?mZOQeT z{*!)<;$)|WH~5-Ue8vSH5)FJ8{P_;fv@X+jM0y>F9pATN4i|d+bJ^pWZ8U6DD2_G5 zTO10S;E|xalUU`3WDl>;<-{XO&~YZ4IIyO)j{p8!z999tm|FN>*U~*S@vY^MGj2a$Fv3YNVb68J4B`DzAQYp8sHV6*l6} zu}IFB>SK1=u#uqvSsPUei$~E_FnDFlBeFlAGWp2%#QwEf#k{nX1brtvsKUIeVvs_m zA^LfkIax)7Sb6aI65b=AMUwyZa-*3p<71d6ksUb!4k0ibCGSjjVLl&kR7)4NNycV) zV?E494ups`63U><_A0@8_}|D=DLtsj0S0W`!D+3n>N#b7zaXs7*JCn%H$7ib%*XkdI;mO&lS5XMawn`!(Vq2Oy!v1w=O zkaTmKA?T)1oHCw)8NIgDz^~GyFLjgW!>BTxbSzQj$4Nw<#7Orc_Er6xLQ!hsJs)+O z?6A|;Y>hH(CNZ`I#Zy(rDLsGYWQBK)CJkJ3@9ZC;PJ+B8C?-lx@fjwQ^Oa9_Ayd5c zZ(Vg^z4{u>MwU$vajR6^QRz5w_Y*E8YNFA>q|u0&v8qQEEnAsEKE)nYx&Qf!JSpg? z;!jqg_(hB@oUKvXXWzKuNAdgbgvg1S5K%KCCi>quKL5Qi3qT_zLMLY6MNNk?7$l7R z+ByQ3vTpAGW$%LHTfQQKk&p{g>oMRJQMIaP>p#e92B~b{xy)3-CDdzZv&cvs~yGzMU1-T z*sgmJ<>|+{-E6-E_H4+}FQKOX3Hpc%yQCcjsZ z7*1O0#9z_^#}5F%)T!N3Qp2Z^0+U$|S)!BR zp@{vq`0zDA_Z<*m1<@3n;!R>GL?# z% z(;99mJ0o8>_XTlTN4|(f^X326fJ<6~D(Bt?Nmzlb90@JETeE2qO0a32523%1NNe6| zZZ(;H-H}*(-LW|Mg6>4e1T;I8e!o^cWk=4M3|CNOB9}X2*DW1*HW(;*F>SIwDE(-3 zaR59-b~*3>1Jc&(sXhzMd-B9+fY)o5bZd%LjJy$5*+=`C!l zbWM+m;qutjj^KOxG4?!fGR0v4DW{lj4@wmlR)N zLYa<(lm$_g^>Pk4ko*B)+Yo2YgI8?3Va@w_4q0&F*C<(T!mb^`VImo4&d3*xcVK(3 zmX@NlI1WSVogaHox~cw$bA{&2HC`W%Rc&3-jNuuJ?-tZ_n;7%I*dkF*VfC zN0*UkvgT+|(wjeCh`!zmR=(4@Dmqa563q5xvLs(kDm@r@2fy9{f9eInVkE_p5He~KX3Z`qw zPFzyc6qWX-%)DjRBHPS^;KF< zY{1)5Yz&UNCvu!tTS^KvDu^nmspKYShK-W45a9JSoS8U&LX69f`O8N3r}FiY2x;`X zzc2WSjo6HizgS=9a)~c@bc|hs_CnKz!Pdm|ngN>!Iwp=#rprDZCBG_XDGX>hWp=T0}>Al{fg@}^54fHr_#Mtz`3iAJr~;yCHj zk75$GP3;;Gqcj`P^#2XJKt#V;sMWC)P>T?pS!Sa89)!fpEXyQ>-3+laQDy9Z!>FRR zQAHX}B@|Ib3R4kypNaUNiTIz1_>`zvp<;?fA>f$Z4en8s{{W*=Mw3aT(osVH0N-E# z!~jDO009F60to>H1qTBI1Oos70RRFKAu$p`0}vuIQDJd`k)abXGm^0&LUMw^BT{0b z(c$m}G(Z$k@k3yPvT$?K|Jncu0RaF8KLY;%+xTP-sh~wr6ucs*+A-9yK%+Lv8j56y zbDBDpi<$obnGi`sWSLS}?uwv<2NVw!Nok_13wokZb!wmjPbDA|ScL=-d9BAs8h_5P zJyS!VfyFi~5mCuQur`r6kij(K;-Z~VJX9Vh{$%Y>5Si^UcAwD<827Wks&ic@7v5N& zDkzxfG?eHE!r909r}afUhDpTCITsLW`Ar}g98ma^`J?{EKN1AoQ2zkgL~j%^(B}nH z7k3l?06OSYg}!{1@d}xA^;9bBdc6_-pa2WP`0VhsZF9kslE5(SDR7Fd-$gqr%|*Cd zAy-DXP&j>4beJw;>OG(HD|)LdDr?VO{?_nY!^++sR`Bw-hn0V`w7sU5*?-uqJT00l z3MUbDTdoP!ynRvJvd~4;kZGC@?nQ;M^EshrdUk|PcL1PiFFNxG0=M+Lmx zJqn6MYIPCWD8@P?T_rfIQ}xWkN9d<-tHSQdp+|uM&xL%)%zVQQB(I zh^-2W8Bfs_Su>Qa!oC~57sGd=+;^gu(V~_JU;~^h`W<+<2-s*I9#Z)sf zl8X38Ro5Pqe1A~r&n$gXII6dyZEsBl+6O@^ZqqC&V) z&sEX)hNT=QYbAzm3M%@jP=PDy7g1Wv)5j~2j&oZ}y(YmK)I$B`yRLx;IeUa5j zw-j-w7YV93bYug|QA1W}6$&<|@f6q@4R4H`pcqtiR>+~RG%wu?tmOyALfr@+RzbPK zgzgLXhXsw)Xt32%wqmGZFfV6z)_G$ZU?`QLOO_ zj`dl1RfRlL=Y*iv`CS$!Sy|o|ei!yvLI}-N4$AacVnTq@I_fA4Cz`BxR#pKTN`s>w z7H#aOJ|$2zSAwK1m_QnZu>;E5?W$HB)ZtVL2)cm5$OZ6^kgZsGuVY2>nX`z@mJ_>k$U zt3C@z?qAV0+Bqn+!Zqfj8IZTi_=Rtkh{R0F!8r=uVz9_@LBh3EVZLD+XRB-VQb^V| zXIWhO61%C|KbZ#+hB8&va;~b2ziI64vR3|{{8Y|&N49Hs)fjK8siGotl;R4LWIn@x zMc$ubr<&PE-d|SZer527&b}A(Ey3kiMT7O#3Rx1q^(N<3kW&E?Dx(N&1oPYc@TQ%@ z#tUXGD3bYZK|9zBA_$y8gKC;%v>!lgt{aYg(6FOD(Jle zpdc!?doI6Yx(FbeiU?{Qbsu*{zT&ZRRA2*^sgS6B7exh39oazg<8_N`jnPL4&1lIN zP1*;?=&0bIBj~0H*~xoIb8%e@p6lVbakmAEtqAE0F;5gKYp6zMs4=*CgxS7mn)zK3 z;;BD0>!K`n>Gak8mM_smN%>(Mbtm{#w&RF|C1i$-y5)a#Lzh%`mhe<}pjY$?uzx69 zt?;VQtj`LetGWmvnu;37T}R$uP$1Ciuh_#)+|_h=S z!5mqmq%tKCNuC94@S3lNdn4_iY?bN3R>5xtvxL($*S83fRsEE^4Q(jwfO%3^-X0cf zYE={kbrvX0%E?d(RvN6Rj*|$)vz`kdD=unDbvR0=*ygOOZBxwz5KTn|eM7Im$zU}K zYY4TMTUdHIwOfrJmQ#tIRD?$WjR=e4Q&d1bR%faM6K901ZKov|S>1ls#FZQ%ClEGr zQJiF?w9Q2dE}HXPmfj&%Oh!0DsC`FN2Ms`TqTX>uh<=RcK6JN;!}nPg<%RJol1tbJgU!>BvYc8oHw6E40e&GKJqS~#IWrVZwb5xjEHLLcATmvwPDftK#N-!r5T>mi6mUaW>#MiDI-$|o7k=$l z5duOdX-73V#3PBIkS`TmLD%3)A);orMn`mPIm)I=MmbTnMT=6?!#9Pb(zIg2=>|~MRb741L!t?vWOdcs{s(Y`APFe! zyK83=&0vQ>JQHBN7#S_6y!C|`W&#ojM-zqfC>zrxC-qS`Gi4e_2P!#(^C~@%Z?w1c zenQ^S{ODnhqN75>9|qPu(RPbIog zZ#hQjM;fP&H>gqjwm@{vHL`q_c_)og_N^WfjU)-O#MmQm`?kTq?~ftq`fb zg<&|4H0L)FFfP?AJ1ZOTP+LqXkUdmo5vtj0{{SeyCN4|5ZmLyot9mWb;aGT9R@Iuu zD&8X{`ImG50M&QY24<&K7jze3f(E7rzdDCiUw-1@n%q7Dv5s(sLBpBJ3iYm`28pn8 zOhN}mEs4z;fj`2akzN83sHZg(6ZT?Y<*N-SKcW z3Z|O7pt}u22&^NESCw=+>h15p@T(pc7@@RLVzlH+d_+Xi957oV^gu{&HM}f@Rt88I zLBPR6ol&P%hDo6nLsbgi^ifN2O*|y}DJj%~8+0~^Owu%oZxw?GXybGw&2EVeE>c10 ztBRZo&YVOpw%UaxJGl$8xGnuuw3*<$pm`^Yn2@nzHQT~ zCs+B&HY+@GK=WPC(H&BA$#6k#kyICLK%)h{j;}hq{{X^iIW=9mQA=FQimmYlT&;&V z9Hr)~7S}>lJ*EMr6+2c@nZ9YzIG9$i**}E+5Ft&LkXM>C5lB+lo{Nv+Db;~AqBrb> ztRm{UD1!=tIO2*RX8Na^9S|+v7Fz+pW;kn%PU#d!_Jr~wI&_%FJeJ6$Y9HqX?8Ql; zWCt>w0j%4;tJj9NeigLn2nN(j+5PIRnY6^CS<>|&6bopuo+w8O1lPKp z5ya+^n3Wi3s`z0}6&}o#X+x5L&^jTj41qESg|;IR1M8^tQSAprN3?0=owmpR70xwB zBx2mGo7DYN`~3nvH3OQA&|iDH2=>%EYxAqRy!+d#D1+luorIAb6G1iLt1tjqv~KSz zrd+LsP?6E0V#Hk;MNlrO=7W8mGpZ!G$4Eu_I3uicUEvw4xF+>Pl0K=fk@QVa;%BKs zkyG?3tUM4kEl+7}Axeld(K>kkt9T|Hl`e!QCnrbm7}P?$BZg?s2u4E!t>J&1kRdl4 zsq|Vtr8}d)O@7b`1rP=vYU{cP_Etc0MtJJ;^#1^WT^1{SzEB`vR`K$#e5T>&bUmvk zzjP^)9NNAd{uNyt$B*iWV0Ch$E}gCsnlb<#6hpfy7AWl2Zz{^mby--T>qi{ab4}SI zXEbJz({>KfHs#%Ppl7KxTlaVQWb?5TLq81($NZ9P~lJ5P*!cTc8vnIv3^%-;DiG z{{T2BD4%3H=AAkqIfHa|J)Lq`obKgMv~Qk>?KKEmKBazFeu!!{b$BXIbR`TpZ;(MA z$RGy|esy=$J>=mY6~4(QvXb2MQ-lI@0dEp>M75|Fh#%+lMwy^Mnk+-P&D1nH)1id6`zI%bZUYIEnHUjU=F6=7&wnFz(Ux1!2 zQ2Cxn8FcqinG%a$N9GFpKgx$y$0{iEG+tJdx*v>vQT#{is+Z`bICv_K9tw;?ywCMj zg_rp%!3bJD=zbS{LLEZh{!+KUl&rf?^j8+0lhf`|zLw1%X?@i3)L3vd)}Q^+DP(aE2z@_oAdMK<{Lu5gegE z2&oEjwY0G*;?i+6^H>Zt9Mne4ssRCZO&8@))l0AHw*sGJ*+j*aDbZfJCW(~v-~Rw$ z`l;3abJzZI)&6tT)uTWFO$et{IPgRY#{jaXQ>wfUXh6*c*lLa;M&IU*UVg)U+$ft^ zsD72sZwf2@j4HS7Y=;@gTfviHcnj?Qv=y{=<6v!rR!L!1#dIAfve+|jsj_&dWJroikn3KGUs`Y>RZ+vr z0)JJ96@Ll_Q?zu%I4tExN!Vf=bj&x2QZ-=;xVJeB;Km( z^-$d-fa<<0m&HB;_@BxZaG%PzG)M9;gP{2rz|efEnjHxIsro`^jaG~BqtyV*lm`j= zpj0l!eq6R$f(= zk#0B!;V^Izpj?%JZ=K>blzJi61>;w5)g42>*l)Wu2dI@+;R4Wp$?f#ld>q&8pG@kZ z!mFYtuolQ{DSMk8NLX1@o_|#w5$c*6NL4a$-@4!QP~%BPJSocx5teJ?v%(_~A>0uS zp6eT%1C*nK4S1j_90)|#dLds#+DeJmA|VoV(mHC9;bV$&Dy@H_BShC?iK^OWj~C)0 zZR``2O8B43wp~4y53Z&W_nnbMH0_(79JS){sPrgxL3q{K9YgFl-565ob!Lx0MLx_l z{t@;ZXpXV~3Y)0BBZsJ1G>tO#?En$@l*@ClRA!ID1jSa{Wb+cSH0%z`6I~)Jw2lB9 z+7;R57>>#-PH>!K$v~QeWE;Y|srrBAd`BW~Rb^oTKvi6|2aqYB6l!B8jF32;`GTX{ z;Ze;zrt3cWCl(SYu{Nzu4mA>}?NuNSGQVXVU7BeQAi9PTmov&cAdaO#VDeS99)%95 zBim8voHcp+eTMt69x8JIe`Nv{nyePkJ&hMN5p-$0WMsfpB#%XC=7YDRiZ1)6`mLx6 z9*D^@?n;2b&K0IpfP>vQxO7g!KaJl* zGpO__y--KCuF2Ymf1-_J-U>uy6PndIDiu@cu7D&I`KH!LW}T1)U^6^WoT=4M1vp6U ztM@?kK$wmS8F8AxTKUz995zHn#Y)B5Vc}HcVF6c5J&x48jn`$i_?lFv*%Zzrn{6q+zl9xW*5R|&;5~h(3`{m0J5plc?q$c z-E4{>sxM^9K~8&t0RYkw#eA0DkhqZsLd3@sW^9{M&>f%WZPKc z#GGXghv>9gA*H}@46d}AH@gvTaD(J*$_EuAjTE`BCz6~F=t7TYr0}Q@6hU+?s+gxW zCglb;B}GZ(rQM3eD1d8b0$|`QLIJ^3G(<$Bw>=7=Av1OWs&H%zO(kM!YK%Kv0-AJ0 zGAVgP8-(ml8iV>|plKROwNw_0b4Nzd>v3MrU5+QB#6GG{kod{dH6KQN+=!&(Th=gx;uop#es#`m3fiJ6_1r? zeC2F|^Az;pcQtV+oXT}GMNvWEq#PuyJ5y^2Lk4|iaDs)qSj^jAI+dvXXKI)ae4N@?O&i>9K0;vog5ar?zX zkA)2`o`_;M)rh(W74ce$Z}0w#4n~Coh~gA7RA#3TG*Kt2sG@Yn*~J)fAlj@gCW{f- z{80*Ju54YuVC84SnxGX`^;t7l<{G;y4PJhlhh0tgkNhW9F26-wScak1Oq#3F zGz)}W<=H}D=HIH2q19VwBnjfAo`pAg%{$5i>BAB*XraUg-EdIt@2ZhiZ$-{Z zTskPyIvRM{Y`kBHKw|sT0NnswW-L&rDpgMv-BB6EIb9v175!HAWpDP7rxsGPye7>n znmC#!Viv<&PKdOy)T$HZ3z<&Ei)VtnhVWB|<0s*z}_ zBbtJ#tD>S3J>&W*997j+!o5=rQc#+v;F+5v?J3n*rsJScE!7-S2s9xW(mX+p=|>ZZ z3mmxzVKLbonkQoQPHTXK{6I%U;S<>tfDh43LfM|7ZxywP-H-*McrC{Ks0s8{{{ZMe zq5xs^O)+i?8pn8F3rX^=$NZ=Ws-`BJ30QF**o04xdW?!F3Jo1JK!a;1ZAqCZZ*4(X zi&X%Qs5%7^!c9~(?S3Gymk@5$ z&y{}3t!moi?;ftPJ9R^67E1|k=vk@^mh7*9)JbhPO_t&Eww!BaynHW+wqG%I@mIxa z_>Jpd0VgYto3&-=XhJ^!uW^fRMIbsJy*pZSH&MP-~MHBYADXgc~y4)A<@ANgdYnO>znM!bb(SL29Q76t@zL;R=puJPL=88q8$2 zq<2>;bFmoV!raDoTC{`_HNp;+B--zHMFFgryNe>lBOyl z_q!&X19}N93u4_9K%nG{V;GFed_Y0&&2GW#D`@JLs;$hqZiv#A{{T3k283cZs>O;NI4Gl~K)T5` z*9d*9pDTE+;z=W(og;pNcP|*46uMOh}yV_K63G;}}CKbvj z_I@g*zeQ%P(15{Z0g#3!_)(ICKFRkV^ijPLjsa{gmP}!E8TAF`JagbuxOR zi(p#nC(%&NRj4__84hI!O-jJ$Hi^QSAnA!2AWR%Jn5x(hJ(GQN6rLDG9_J2<<-z6w`q4WkDl zh8VKm!4{&SY3oIS!a6AXtXrfZOs&gN4jqbXS{4Y#Q6Z#uUeicmaN?i{?5X8e2RK)d zs9}6T;co?6lak$Ydr>x$v~mddn^SHp*?=j{R$DyOhdTTgCl?-ARTw1mg_Lze3BNTy z!STertQd5i#THn&YTZ^=^j6n>S*+E{-doD*>+Y|*w?f<}bwj0z$y~RVs}ATEIJ*rF5~Y$ls;N3Q`mM<5Rh{{6jJj)yW1*G35Vl`E5Nnt! zVzo{NI0a9z8go-~#bb)JprGi09NL40Csy*=O!t~jKq?bjt&mSCM9YHskv$a34Qqi0 z^;<3uKf_e>1WQd2+J7Ck!Y{)OzS0W8aQhYaLC%>fT1;!JPOx)9rzl1O+Gm3)v5-}7 zswa-3*qOSX3Txd6C0w8zC1W!gtXQgu{>no|6c*u3{6QD-RSRO8w^dfzSw{pjRMI)8 zsX{6^qkF6}E6q~0%`@I;{%k+MoG(X;|D0ZN@Leg*MI%D3C$ z0_g0GTBbEv_)&(-;rcDuM9K~tT^#jC0S?NEp75SJqL^%(dqs6@l-CoQbBP$UQ0Iuf z1yfz^3&wIGI}KzhH_28p#gN5xNSRKYMwAHb$docdroUyU4jNu=h~dQvk1KggZOuu< zuUjdt_$)8d(m!p;gXLJgr1n}O z(J)WdV#9aau}^T(yL4sEGYcFjZVv^chBy%F(P6@IlC+hBk{F#E12v*0#<{FgcdoRx zG%&Q4oGp|aijaoVc9OHzOJMX?QEx;OM6KiHWvSnZH?O>h1##g}g>bIbV7Glx{hg5> z%Sl?)57BNr!rVSJP^zQV3dAjv5NWdI&Q{L4v=r%RuO%(ly_W?{`Joi5I2{M7{h_W@ zQ3{d~H$)L}_D(Z~zq(h%^j{UI;nFmj$gKt@&GJv!*~TdxmXzq4Vh7c1IN=N=)o8Hk z9amPR0yK}rPZG3*Jc2o`_&7mYEx3^;%C5Vj!D#`A1}qkoVA0XJH3s0(id+O84X-5W zoBr~-l~REQ!l+5~UDirz3qIu#6JwA3nt-<(;chp=_-*jF0^Idmi+9z1<##RTDmbr+ z=)NbS_@0WcX;)&qR$f-;s@(Nko~z-N@ZI5jH+WwS-W6JWD=n`@MuiZtw@5$>;`#-? z4`ug!E!`i=tD?~Ss$Zhf5;-ls0}pgDf2RgHtUvVB{AkDea}K`LqDF!HSCc3_Xtb3S zRL0(@kVutve@#NFeWU!XljTu_^gy(ED9dV^2mRiy9v8!Jh490nPBg^!zR6t|$Kh&i?@a z!~iT10RRF50RjdB0|5a60RaI30RRypF+ovbae2mt{A z0Y4%C0QvO+!@K3$T@vi2#UZgLXzg?(92Kd_?-hq7!eCoH^|)vas{52rYOqcTpss`e z0I=!MT^vmk_!aqx04qip^Dtxt5#r#}s~V%gIb%gV7>N55@WW(U;FWP21g5cU;Q`SB zyYq*FE2vafXJhC80C0E((gR$o(2i9LaSbk{AAbpJPXp)a3!IMv3WqGO9LT2{ks6KI z?yvsAS_LaC3C1gKZqNrq42F=F>RWtEGyz*ZU%e+9fSl#uwCF?BKe?3@RD#%HZ-nmV z7-B&XzANz@5(eak8P; zue?S03K-lO41DlJC_0QxyL=hE97I836w_MXWr=$(Dhx3=ze!ii^~42Cfd2r0;|NjA z3gd>QD+0>&^iLWiKB8O=?o+I#UC$HJcm1dOAN*R*7g2Vezx;?^T?aDqq1UHLzx{s< z;v1LzI;`IIyQ9CrtV^w;)t$=%k5@^PlYNW0tw~D7L*1*}7VJ5k_3p;QlMk6K=K9d` z*4^iz?;^oClf9+ZP|{{UUQ zrvyKXg;M#28E>zI64cPv7K<#MW&K6SregGfjEPJp?3G>-e6zaaGPH|fU(~wOV6HLx zVqq<7U3}vuwJ+%|Y3yw?@aL0_b8f)_US}n`S~47E+#mvh9$< zy`rfM3J^9mo1{X76Qo2Xn$=Vda`9#>gKEqxuUG6k@-Om;0ENMPpv>w~Qp>bZL^)fQtmvuBL+Hw@8Fr^V_32#b`bB3z0 zR3xGgBJALC=>&KJIC^eore$iE;VR;(;f7(V0&;u!zy_#kfw-};1k}E#pqX%Ev|nml z&G^hNSvcsM#X`j>ZdQ}-05m%0X3@i^jLYlmnvOMPEo)FxG2gFZx@Li8FwVmf#d%5)W&sU3z{ zn`W4Sk=Kb6Ei~x}$#?S9!}|=a#y2btBTU}60H&hM;Eduq)I1aef5$2#gB(}!pj6V4 zz~4L?_hBp6+3Wmfh8|F~y}#(C5}e_eRG|#QjDp4~MyFB=?ZLackZ!4^o%J(RFwTjj zYNIeWyFfNoaf%?~3|WKoGF3gqCChF|ct?k?SOIKRMDUgCP_GGD+lV|%OFG6Ev>v)H zV@otL${NbmRsJQ8eVw%lp6snL=`0#A_&UCjT?MRRs>JE}5eHpgF7UuBHe?xmWr7yT zEhJ7m#YzVg-pt-mVc%1)@+#(9Li30YMs+7p z4x1o!?vj>DC<^_EqlNMd_?AQ*s%TneZ=4AURcVdSm+Znp<3nRsLW+)`p3l?#beh>NVfvcmwCeH|#XJo3UMhz17tP3Xh zX8ryVuSise)^V3vKzN+K_lQ(6QLK$o(oo@V7*XWpjkQ9W)C&PMO7oZjqc?)kb5JA_ zt2L(lK{{R?eq3IMG%Y7kEH*I5xEVnlht)lG*$bdP# zwHVx?g;P980`JaKlV&h4;#bDY=#@JI!JTY9OvgcWdAO7qX<40o&Vsrd#ZFW~PK<6- zK*c30~CLcAW`dA*WA){{WLW1?2?;LPz_DPzI^X&&;z{oUhUVTKTJ9z2fA|E);``oQAyWBUpJ* zX2C4W5KBI{5#&L3yZcg$2{Dogat-@N;HR9-pkU!r%Ya$G;xKtRGsikX-j`G_vbXd(du>Z{xMxG=A&j&$!f zV3d()^FWxq52UEa+6?DHQ3@8V$}%V|(rd4oShvI*#tzorlIYl%AA|mSykaW=N1e(a zf6{$N@jj9Gjf(T=m9jb-3iO$cuC?exB>-NA4qD%coUOKF7f^Ekq_H z5VHz%T=k7uDAhZ5ogY15-G=&1$;d$A-wR2iLCo-slq9Q=Iw#{Wnk6VeTyApj zmvphcT)tAa_sC1dw&PYu9J9L~7vZL6U>ok9ECpap!z*R&Y_`Xi%a2fWWkCTyC>gfX z-dX%Hw9>H^g08~4!*0P_Dt+c;I_klF81W;E*Do~HknaSrf!!&9igXh3;RIYW1qfGa zp9hFqstN;F?FT069$WMN<(0IKWaXpBEv*j%ejoXS6-Sa}qt{Eg0j*}DBY7Di*fRC$F+(w<3`H9}HHT$GR27+4Hgcbti~{2y zxQ_PXt3we^lLnz1%%*t7Bn0TaDlKkfdn$%j}zlzcS07wVA^#ZFQvmdAw zzeED~hH%b*5|u019|#G#MhvCQUiuIKKwPr$KyHtB`buKWFufh6qIqUq5HQ>&RvdY; zfKc5oy%Uu^VQdR!D86$Y#~9Z9M~k>@GRg*BE>zc9kQ9E0UbAw-+l0hi2DFF<(7Y)M zW2@719YAK@QCN*MRwiRIR8+3P)J99qs{25z7MyQV`-I`$S;{x^$Sa2X zK=~~9C-4n7vBk%`%JuITL--#T{Ke_0_S?!9c}Zf$R0f{+=Nlnao11oLi|Ym8+`Kx5 zRTjmn*c&9JQ|2?T>Quve#vH+`ucR^!cA&~(K57VqdcJptB{*6%FUfj$nw%B_x_EwO zVi*;SOR$Gjk_MnYR|oS%G2GeY_)MZD_3L z!tIA;=`~`SW%6km@OB0sr9LSagH6Q+d70f3yv88Yr#@PMlfj;g;VILH1w#u-(gZq~ z)UL#>k%x~7LnZQ=@yciK5JDajSpg7ysw%eN7mOQ*w1ycB`9upfSZSDl$zCM2^NaO@ zKI{9G>wqn@gJb|q(pZ{ifcT}ujP?ZL73E)v((%%KS@WW*^fSk<{{Y-k>mFVo^eSV0 z;t|N)uZL(f)aq&6OG-+8 za~U|Kctbp*U8p6~x^a7!+hBs5`o@pSW;DAUaUX-3TpNC1Is=r#o`p3G+DLRPfbA7~ zM>o$iD7rcHiA_U7hu#42XAKV$04A^|BdZU;P}~7gLn{QPP&1L4bxs)OBX^&Ht@nd0 zQP~q__?JPP#@7`cMN+U|%ne*a65cYpQ;z=tOu_=UVMj4B--q^?F^+5RNtft->o1Fr z@6@(?&(yTD%nX&~JBkjv@|NX*tnLmm-JWJ;4NCOFZQZ(SQAr(2A^@CD(azQ7!!<&? zQf_q#hvMqDV(AJ1E*sC;tN+b z-tq8>a1PP^rJTof%ON{cYL^vYw`{L=Vs5%sA47PZCe|5xc}3ibeCI4hLQrL<1vLfW zgi>cfDK8jb*j#2%EoMy3^~Ty%6*MfA))Op7@XayG-^>PAtkkZkwTYP=VFM-jN2~^O z!}l*Q&?HhITHmbLM~Y*XI|Y2d5|V8O+n*@p4P;}F+*M{553W4ZFX+Iin>-~HqkC2k zAlsJhUS@M0G`9)Gz7uh5WnVH;EP7iRd1-QdY)_vNHfibKlj8tG+ZcZ3A=pt)_Qwcw z3f20BU|qVJjeVM&ifq)gVYj>>;Q52$1<}(Jp*I`%{@F`<49bM>_lPogX1spxS&R5* z{eH6YFP^%I@^e}8KOgm0x)5+ZV>vvJ?SpA?M|o`37^g4-jk$ZU*SYH3ib{aMBr9sOzB#QRjO5; zGp>@63CaQ+3hi?K5r%+KqPO9AfTFyKVq!4S_PCpJCHYDYj-*USUIewW#8o2H1}5!m zF4fm&!wOLE@^7MWqo>PdjsgUrLkYQ$>I>nLXN>iQuOLLWFTgO|S=8h%ks`9CqZus$!di%}kh|cd5 zx!2yYa@I3n`@-)G$qLKOe8PHsTsU+Q!Jhk$5xdh3d3a3hRpDhbGlov$;JgOgvr)6P zDo}iyp$Vll)%P!LD~_tR1jw-8;HgIyo>auCH5tuco2hF99W7oDF{GBaO?t|M0UEmR zUx+gjIlAU8M)6B^QSI(_SCm&T19{c=hX?E)E75T!C5{T554BO2bq5y^C>`#1B2z2! zWmP^D%%>f6fn)$zJVmbl(wz?A!RRveF3!9E08!RIRS8|9I8K&*lS=^^9`8uSyT>V0 z)}NVY;aRR+=)VjL6g;dB9EV_HG*P{-ncZmAw(wXBs$Uo-6Ghh%hvy2bIN<9nVF{JZ zUJt~=F3j)F{{Sqre?%M=H*Ik7;~n0U#%Y`x&GS50UFMm_zQ6XLF)6_tN|;xud&E^V zc$fHRC(2y!%z-x>fd|qa49kDP7V^9;_>-{z08Kz8R10by04TWG*&rC|BtuvBBtrldo6-yOUGv6Qx4#fzyutpD2{D9hU-fmBWav(rn-Ol$ybc=c*RF{wg6% zNZIA>{AIPK1*WL{!$fd$RpuTGtmQP6<(u;?GaRF)o{=gO;Rn!-<{sn|1LlGBg=UV) z32O@%#59Z|gL2t9Va9wAdjcvI(fF3lm3TMjf4R%pl&2n0onewC>r=M$o;%CJKH@NTque!9fyULpKLGlHSx=`k%s&~(&u0yU$1 zojnIIFaWiCg$HsSr>-fuq2y|r;$+AUXyZrbH>2fh#tO|%U0eW%;^o)DDUDx9@QWY8 z#h~m;{{W(0ipyi9yf}IZmL0qqEB6tm@KY<2IdqNpj;DadN41!5Z9TXchG45$JZf*%pxOfu_R zgRu?k^Wo_OM{BJ&-@Is5cT0``0Bl9ImatCJp2N<8=N2ypB}7oDGWM9akL8^_NT^3- z@SbSjd69?`tu}KJTa{aIfY?{Yp~ZLM;Q#|5(%(t1l5#huevl!>d4G|QKpDJq4)1ic zAH~Idd9e-`?-sMenW}B@{{X5Cqn=2sP!hX6BjrYxGFzx`ShP^!Zag`wN-qBZ*;MFp zDOaxn2T8sG4d*+6yWzEZz^61eRUZx^Relox0LV5)3k3vr-4x~3-Wl`t&HuD^FO!9}n}&T(W+T%mNw?rg4@bUx8DYDZ{$M}mV{ zRI*+9Y8<0ts+JS5slD~@8ZGV#T1>YFl$6+f%@8e>=55{dCPgo2g}?ynpA)Pt=+CrN z^MvlwaU8t+#g*i&o{&O=`m_DV?4d`rX-ph~k4M}?BseQoQ=d3DuSjycNu$%p?@5=6 zk4*d#sl8-nmP+fq>((lgCl3rNhyYdI*2eWc1n|=uD#}N9#2TJc%LL9(5IJy7@g@{sQgDTtIWZi7W7RxuH*+}W4;JV zxM7~O>%vmz*6-ml=#K8(Kd2~U+xjN)hVvR-w;jsB`F5HY@BPjm4j`&44YT0?0G_99 z>l=4Tin|$9r=#fy0Rz!C6pq&G+A@L=EpGGuOJ!`gq4kIi$O(J;%3k5gR-W?EDD?hg z5MY(DLHmz_hfVlYrCc5GSEk`+V!@*@(E10S*U~HUK0k^g@vTIHz^nJ=cF1&hW}jqW z(`jbW8`P%g%gSKBH|WK-qm4N22&EWAtU$6Rk$LF=J6KxIzjKxZHF=$*d81Y9G87Za zBG_OUhOfyHL83jNT<*|OLhXeep_qW>IR^dj~ zb~y8uHkumMVrb1|`G@zM5!BtV%o_ZR_aRqa&%+aK>IYX^i#xxo)k(>u`+s7P16 zO!?V{!S=bUuRTb&CyrmrS0pvPKpA(6Tknh)#l=~Hpf=kpf_oTnUZQme)7gbiuBYB6 z0MkD(Fds#g%dg24yUI}JRVX@#<^%d)h*namy!MMEvf}AK2NNCI{t=`Xp!mmgMLL-| zzc}zad?lw##spbM>%R~D{zzH3){*EvKbEol87FP{DE!L66+y={39}^EjJ7E{u9<>Z zYd89gD_ge>(HSN3Fz|Ryn*s|*tYERRhQh@&aMG_Im=4BQbCWfRgaM(KXi;=n3h~1l z$ut-DnC)$8hM!kOB(f=Nwa4mlf|^rao0x(^tHI?Pxz6;aR*aX!7JDG$OqWSaWX+&=?sx4JyuQD(TQ68~@QwCIyQwyOT)sueVsv8`7GWql+gqULnv8V$;%fqV4GE zb>#`W0CJtCRB%?{6j!~~O_SWe5B$%7+`uDdlx{9B<|%?TQQWPgx3eD;H&6L83Mj$D z${|Thj2pP-g}s}AOA^)0Ey0rw@hFz@iJmKRMuc!Cq$CAho01Q}cgcbDK2+=3?f;O-0(2tK$=aMzs4d)EEm zv(AV6=>lsOwSHawVY<4zcI{oyBXOebVO62+4&5Xl@$i7_%VW3o%6XQ2V}BOi!ihYy zIM))>kY`5&XHtz#!4eTL#BSp2eR+oSc34+_`eztTvA<}ADVK@zFWX79EBkKH3G&TL zk+J_@xYpKX+yLP)rnnuE%-E!m4~DO(^?sK@x0+XJ@*VRas}0k*~gkx+z3gK}0e~rg5ERVho=%_*41b>4EmI z2;)HG3d3oWLTYB?bSS!3s2IS3%GMxW;{0eI#P;-C#psQ@0U>SjFfq(dG|pcSf8pFp z48Mu8t0z|)>11;$UU&+bpP79zvAbMp@d?iLJ^f2Zh8A&F!69Tgu34AJeY^%D^<`_~ zhrT=Vp2q38^3F*oJ<_!%{``$G!F(}6&#_AZDaYssO?KDYn9f~6E%iwe6t})&vM#^? z5G$JhO%g$UfYcrCz=n)NC&|leDSmct|CzRhcSwS0q!0xgQ{A%)N=h_D_;~X#+&8_< z*!HcT1=PiLT}29Gk0SL6D(e8*vc$h|gvvfkfN1&9${LmZ6+HTJ7qmg5ehaZ3r)w$#aqs24!U2+iNC)liN^f#kg6Hj`Z27ARmzsY#{ zl(=`wvxMNgSl~}YU%CMgMJ;z@_5+b`aV>%j@W02rrdAY8-`ZsDvJxpkh)E)l1kWd% z_PIjqv;v~PfBTgyL=YLpZSj3K8zwOLkg3p*B$?h(Mz!jm6JE#KybEBhbqKHZOPJDS zgz$OB=Pq#DM55u_Z}l<4FK1tR_Z11vDGQqh5#uFq<$|p@w%AD(_mE8w1`u$1`R(Zef($b(|%f*rATK3v010 z+@2mxpGaB+mQzmB@m$CObfq{EZ~2y}u6B#weNw^7ae1xVdK_4azvAv<&S_W^#eD|L zAOeTHT1o3av5nYpSdH1}r(+-7TOYtymSfiAs-Kmx7Eo=PAjXB`eHS6y)s1hw2SJXd z_%gAp{4Pd?#@M4*-27s;LEe3(3*s_c@M59vW?&>bncTOlt-Uk|Bpu2{{k<$C2b6pf zBqi!aT<*h_h#u9kB)Xsd!EXn!US%rI*mmF@`l2W{O}Iv!y~W-dS-%?X<1;86a+Y?n zdkD988p_GH{uqdDml0NL?Q(m}!ex6Y3`K_HO58ldK{pPpI3uV^o3S<<6FP^@*!;%2 zN+MZ;=VXCp(!SRrTqeh`FGI4qk=4AJtToz;=dn)s(WAlPAj>--aInuwVR%cUOoLM0 zb;|i!^zwszYX6K0RR*h?r&W|_fQq`Y`QSLFWN_6u{L$m1#AO6QP4@9I4pQmEV{OQ9 zENeb^9h$omq@r5Lw~885yLv!s2^O)}@R|lA&kiVDi$VE*C}AO-ax#Y(yg8%x&| ze}1PujZmjD^7?m`5@KD6fk`U27O( z4sP2v(`kw923t(iY^<_);kc|Ky5xDuPsqG+t=|-L%HqVh#rP`x^`pRu8W-!)rX25B zQ+rJfL6Ox^bOYAHqMPTtc4eE6wV$BdfY-95UF6?qTwQ9Mh#d2$}%KG zZ~HrtzKp3K9y67!XXG>%4}F&^-*ur!s2t!Ww;MD-shj7H!9cKo%tUfz+FecKD0Vcp z>Pt}W90lsMtBkkxnoZ^io7T?(<#MjL$#SwGO_5YwT)$aRCltAcNIsNc!2&}d+ZdI( zD(WJc!=^q>GjmXpYctKhty-#_EIOfBk>fMV^-!b3C2Y(}GBhNS&F`0yW zd$)|kIHlr!Z_%{OKAML|!}GyziYwhWWBWB)y{pH}o}EuX>~{A7((hq|PgE=ty@8vh zAC$e~_O6D{+A_0-9nMndJGo+2{B2rqnsFYQ`n+{6m2Ah2BNa;e%^Do6=I9w>TRT`k z7|w$U&x|xS#xqdLet=aE3o}6~d}m{zWxc6+&FLkBquIKGU-dWLv&fDW10Ng==6&%r zs@hrx5vH5xsddvM$PI__i2kfOtEoVo4M)fG>$QJi)2)6cvzTQ3&cXLZ6R( zx2paphZ=HJu`tECcJ&)iG3*42uKLWSDZbzFWx!SAvbp`x?jfMMFe3F>WRMMv}cA#G^>Q`I^x2NIZ^!0c;R=4 z+X!B+8L}|B6grC^0p#0adI#%uQK>2c9Kyx2dyLxOnQG9GR1r}Jq=J*@JoMw+-%MZL z1%rMz)*9N0g_6*jFh~^DATCWogXM9gGr7d$-|W)8GXm$O5uB(9vMp0J#8UVkq9JG_ zjCo6%ySGpbpMEh%4K|)GuzG30&EonTKy!xOncY0b__pp(IyYL6f9cBRkL1WR+nl0s z$KHojq*VM+3X#j2_rBJUdgH%v92l6@=3QiCA{M13Q`sxR6XJ?&)QT%m^beWpq_`w1 z9j!mQfe`)S&bZek!l|woc{sbQE;=3s-UL*Vw9|k7i;y7*C3|n4J@~TZTrNd!L}Hq_I?OKpoCwUFwIdwFWY)fK?k^OuM3k zwB|t^#b9XBJD4|l`3_!%<4L->dghDCSAInoTgGbgq%Nv{%%_&;$&PG&B?gdOL&hLP z1ET|(k0!`3L(ls%n0EQdhPp7tknw05(#c;jzv>;_Z_=II}6@t``@GqAScSiWS|gGeHlw-R+rIOxf>J z-KoBZe3U>gmB_M^g$H60|L%LCiwQ?n$+A=TJ3*VUKE_(N1tDUXG=oa?zGF1czYSfB zmaj2JPr7-O?(P32LQg@%^_H?`=50j4<8TI&imhOW?@Yf3@h83}ab!D9|#+7Scll^W&I(BwI`oM;KOaISjDqpsd@S0g1 zv{sL*@HV~`z*kxnHGokA$!O8dA98=J=->yH*R?OUW_2ZH&-Yl5AKIU`ACnjN#(ag$tDLNVH zRCjY@;B}-q$w`3Ou{(BQON;4s)2t!PW1=p6JI&iAw#ymbFu@d*qcz9UTI zaN>I#nJYc4_uDfN@oR{nN;b?ZiqrB+Wfr!Bc(lK*HriO(ylKuL`J%Z&0mO}f2g>_S zvYUUUG~|+kI_=oyZb&fo?Qe$~Ht($6ZyuYU0KC0vKJ97dMw!~f_CAV;5{Yot^2jW` z0t(xZ51~T^C1Vrb!>fu5KIta;y3RGNbX=w*&tquQag^hYiX90U_rV3=%omW%M~#rj z>u5mUDKl&rGVwuG}_hG^^kD1_Yy)D!Vt(gFVwMM-Ov%BDKhr?|akiy_lg_xa4*OuRvD6jOBub4ZEnzO(p#(_>3*I`f#eCBNCf_3 zsZJG9-_|hwXy~4UIWd?jfGP*^&Fnf*JjzX|Q&GWJ)5Bo#i1I{4wxjf93%U&wFcl{3 z5-2iK1@9St)3V-Zv^||BHuI{}5Z%$p@Ub}LNY5;t$}A)-3~r%Yl*UQ?wVP9I87GeXHfTR@C-KtAMR)`{Z@07X4Y5$vs^F=zHiGhQp5Fbv(N10KkRK z`RCsAX=$}oT4b)61Gt@04`PvSY;eCHw8ML zLis8l>olnbYjt>B53l!2n0!PvckDTh@}R&#Tf8xNAxI^DK(C z*0f|gY4E_M!W-YE<#VY0VwUN#j$i-S4Vm|BXZq8J8|!rqi|&h~7E*N185SeT{Al7>qqLs(}m`f?X{upYN@#$%X zk66n)dqGt}vMBYiAP26XR|5y8ppOqHB-y;N9!KE~AM}zBTFW zrt)|6-nmx0Qb9w`ejHd`B+{^)cW+o3#k7NOzwLHX`y(MzU4!{jY@}GwPvcw~W5Mlu zG7}%|YlQ|^02iNsVxh#me&3|2*QMTENHMYg5AFA2Bxvp-Jf@%Jna{IO@?6k93Y(*6 zDl1%^N7aN>50?~TxeE*^w)6n3#R}fB?GfwRMsArLKPxgH-#-epr0&EKbod3fNNcC< zy)s{ovs?!LR{7!Aqn|OALyyBV_V9Ivu#6@K zdUd|x9ldC2n*BUw^y{UU)2E-YJ9(UMStEd#u@q=!8I>GX?uc6w?s4&}_Zh!(bsy4g z_}?vqUa3AK`iS314l;cXXVDdec!Xocrn2y~9&;A_tRDDr-Yfm|_EWzQ1i^EgI$za| z&3?#r=-n~qFBdIkKkSXzh>!d4Jtg+8VA>ao>bnM-(tO6Z1DXl!lojf?)^F{XEk*$4 z8o5Dh=^A?pm34X6hF!I>HqtJ(hV?CYE!J8ocZ8J0ulX_!DC*g3eCe#MI_mQuI}lGx z(bHmZ1jZdN5)fN9ZS9j{)-<)1UMylTfbzw6aJI|+nCoWEZz)T?>8Lzi0a>0t@??US zAu+2;b4uzrtiB4bznKFbRvuH%DzXCxszO*-at&AWJ0R;PFH?2rFJkkGM%#xs^Sa&A zzFv97^Kec_-RgzNH-Z;w&OJ)@1mCJ}7CKt9RLO9<)OX8?RJ%ZQUMTt#kK<9X3&-PC z+&0v)+kHju$bwwR!K>v@y-i;-IN)7~BHs~b4ywdzARtGdAagSoY&Yta8f!5Z54@$l zv5n3gn!EJJ`-JK}doW4GXpLSWo7Pu3AO+el_Xx&S zy<)W)Ru*i?W9J9+-hlHU^$yb!RX5kH+(=Z)K7H2bQXVxo3W7!~r^Zt@bOYNglK?3m zGtjJoR?NC?-egGVZSZ-bRoXay6T5w!eBDSPaGT)1bj{$?g{Ar}h?ujbE;`f@PLi`? zRXEU1jG7?iRPUTOCj}r;zVfE?g9E-nw+=R4kLoeASPvJ3MfS{?>9rnov)yMs&sL?L z%FM5o__kqm8f)2bhG!O`q4FG5$Kmzp5 z|8|TK%w$|=SxS+-Of{pCK@e2+4N(ofM62*C@>JLe{WmHJZTm?QHs3|I?N(d)HzB;6 z+w7{}1Vz-&gSzhQmXJ+R;Jx+ zH_QeoVOFoSK-bcIgwyZ0 zts6b1eLkM(+$Nk!r!!S;WU)a z)rElH(3g4%+a50hTkv~E<@$J8^Uuuth`@0*RNS~WET8Y+9jNuIqOua3`)+SQp7)<>51*W~mpY`5{U0^N7U z)~bhGT+Yb*YSGOx1;2?p)T&U)*$94x%#WXHZT33SkGfW~A-#(=^$XaFG_4$;)hy;y z!fSvhs~2Q}ttYIeslII;Wi7pJwk#tvMA&tD9h;w)V_PWR&0NB1O`okB#n>>SO6dzUaxvk(^`%cMqREYfCXI&!gfO+zUg0T9SCNf4Hr(Rf%$KdR9y} zBC_&+?(acOqx%udlnW}AYoIUI0BokqjuxxedSE9azfJuj2EXhYe(rDkE>+7!3MHAh z|06v1@62}4Y)fqzT!H1EM2Q_mM1mQk25%Z_U^QkqBGo1n^e>$F0D>8*uY^9bwV}eB zxcKGbEWA>kJ0=$)>5D^BuYMX>^^(@5V2#T78#Tvci^;rl3Po^_k+!IN7Yi%!K4DIB zQ#~53{eDo-*ka&1Q-!kQ$q=VuUy!0)VuD&l=St*Fzf+O!`E&G5N*6Bmjg@Oad2#gC z%4)3UirCJ_k1?70XIgF~=N*8XiZX=MVr37E4;WUxzq{jVDhS!7tPHgY{O|SNK_Mi3(7k2PP1k1)-&@`!`06W$wn!rI^UxD zm0+Cw2Qr>pc>>$8rIgD@Oe)4)H1n?a!zw1K0@l{?-iGT3_D?nHJdGY1#ydab(QbTY z60jWncB8u@6r~5n`^(R%RLVaLm@z6ZwG>9ac_UQt;Wy9tY&EyiXP3GypD;(LG3O6l z(3QwEw>cL;J@2)C)kN2e!x>-(9l};W-4b@%l9dt|+9H3Z!;qbYBC~6m##wAxc`k(- zR8nt$Q}>T)R}o)D|lVKroH3T+q79dm}{eIpaReP zCmq`5m&YyR$~mw#uKu^~VhqNwsw&j;#}|MxkF_OJzq3rRh^mf_y7uydke^Ho|BXpb zL!^Q%>mUA_r6~G}xfXi$lNpXLoB++0y(Q}xN4uG(zi`S7jQ$Mp)qp5sizwix6|1H> z?EX;@Cm}k+Lk=S63!4rNMh({eyim6=uj@$bsXRQR2I2mRL&v2rSxUsERNG#~JsrJK zX?=%A(oUX)Q-0oCmAYq>_KNrcbD##}v~RAV#LoI&iN}S@`Qd%T563Se$#+PStkAez zph6#;-kB;#(dQp76tiuaKMqJM#Efl5i5chE*vL(5!M6!MJtTlS?7whWt!-|ZdJ>JX zL1J)5kg-MhZM??R^Oi2Fqxf$?-$`X(y-Y;mI18EJ$i}f1X_zDmS}6GuRbf{r?0#^M ziIb6{JP|z0zGKRG=yrW>ciu&ou9~G}%u`=gi=Cj-`a=3b*+Q4yfxANVv1y!6@zXrZ zGD`m)&$|*>imAx_fuNI^Z}KysoJy5LTy@AXqi;(x)a<;%9qu=ayul*_B5zFguZYa+ zI2Alv_;(w7n}OnbW?j=7i&bsuziho~7@c*h;*)0jryGUeyMD>P^T{79B0Id+tT-Chzlssr+(JqjFv>ph)-q)%pp9tlH9zF^vp0(mQ9b zZ+(XTpvrt)KF%A%du$J!!=Z9&Ds}K7%B~dNzlhOQ{#}KpKnAP(K;ia`E8?$b&58Oh zSV``}TZy{oiACBLLls2D0@OW?FvO3ge$MiT6>7wex;$pa$oS!Q-*Lx>eY_==ekzZQ zQSmxDk|?v;s9_upd3?Nk^L}V-X360qPX5V}tm^xBxzQ2-jTRz{Qk()2JauA@7*C^O z+>|+mNd3dC7*w08IzCY^SRL(wl6W9~_o~e!KCxHM(}3l;j)Vf&O*&FwW7Y_9Q&{C3 z2;U3ykMy7uP?52{Q7a@8w4%w(w;!9jAGDufF7D;1`}QdfV?Qe$FDru=(FqW&%HA7x zq&jt}r-3+fm4E}j{;Frm=A8^TgSy9!DZ}PjDw#O9z8zIHvRXgJ9OR-!no>}f&+k}L zEWV3g&g;@D%XcE$Wz|bg!586fp)(HQ4i2#R*(-y>G93H1;M24Y#HhIRnX&Dw{2}u2 zIGPy8d~AlZE&BqCB#XkljXY!--R(y%MT#H|3Uen_CZHPgW$dT)y@Q<__+=QQSd#he zZ(3U4kLbGYt(`^ncKYGt>ZCnC1K!hbByK2haR*&8J!I6MR)9;zDk&d56$bM67#^Yn z4<{m%qHmdQnRTAZd}mc|M_&&q7`EB&UWR^mySq%xR@`L0LXZpZC0~)A6k%B(Z~oWM z4Mlz$SR(9Ha9g*afHIVjuM2gz=b63X8SMD3A~kpXu0E|0W>oP&)xmb} zzi=<>Fm-#Zf7UN>|GZ!D{xd}T|NcPj=eZU8pFEq?#!rh z)&FV2{=pIZKU)a0|I;G%ze<==bdX2%Psg9&$$)EYphA%f5<~jm2T+dXI=?~DJY;*Q zI}o$}<=QL1u}>huoyMQ~kMk!(y-E(3VYOYZB{13SFwB7k&2j~KwyLSbf0*pl^NUx0 zeFz&oYQMZNvM?s2(W{0AH?ET(48jXRD8I*jI%BB!*AZHov&F9IKMTvJ!c!_2gHiMx z8+}yGDx?z*^1ZJ|(Oo_DKW!@d;zLY->%u7JMYH(m(r^Fqfo%tZu?*c==T-&oZ%&fG zX#Y{fNp6Dm(tJ*fvDZ%ZmCwp?mv0|}?`b9OIscs*XLDgX&{RJ7kyFCQBGw5`z(Iwl z7^6cT`%4Rqq7aJ_mndi}$`|0dAmETz0DrN)p_7b~Pg=8tQH-3aD@HW>XZ1v)p$Mf# zG;@6Kt-`G>%%+|d7=?Sb$VdB8g0*7pc?S4wk?GKn*rGHhCCtR~1qR`T0`hDCr@o)| zu-FJRiFNVKNxUIuznaRTn%1~)|ay=aQR`=*2taOg&=Feq07+DUsc_K)V(!)o}s zOJcaTW|+2x82?dLu!1~J2vlgrTzLa;{PzC+xGiP@{dzk4zk!QRK>FPfTUfM(74Il~ ziwodP74*;zA7k{!;=jRBFGyOWbDl@ut@!kgID3p%+%H&P%ya?Q*4c|6 z_6`LTvrkfAgsrQhNdZH#c<&Zr6r)kjYarX&+^Blp?8j(*QjcC=xQimELZ0`(`vLtN zJ_zpCs;ZfyedhfHvG7x3U6Kq*bwqKO=!wKSnlLK=Ci*Ir45Vc8v7!#H6;O=@!KbMb zc)M)bI1ZyyPCJ;PB{qBWki_D2+~A*PF}qn;%8T;3b^k6uc4Q)1RN0P9e;uQaZTPA3 zcGzI1N+MoRcccT1VosuwlnfB!k_KpWdXsR|9~R&%7a|%$E&m(tv_ut5OURC^xseP+ zWy^lK{u*89GeXs|bp)`h53fjNCQWjd;(mT@XS}69hGxG}ks91@^kH`82m4~sVOUWBO{s=7V!R2qPJS&?6y4J zM<_a5m3}Efty7Q8+DhRyjwSynKs+|>SxCmF2ZcnAh)3$+PHRE*)w(05;lEquQw`=R zkeI_`1hvKtV@7Jy&pdpugK32Q$Pd;PA&ZI)k-mjoip4gVG_WZZ*cd9Ex!%c3hjtC4 zn6n(c_F+yJ*tu_bc9y76xcr2+m+0J`u0_sa6kc0B_Xg?aj(U)sR-|^KddXkGG~lVp zbb9aK^9*Lmf(4%e&*%iPelejBAtnGj6)({lafBmF{iFZ)52S0oajhLL`@gRLH~jyt z{ZAJIAEt%@^9w~lMns1H?*$3d#lWNHpb}>n`=^aj*qc-bbBlq=V*I}zp?H7cwl_-H zyce2R4|Cup&+_{jDaBvwdZN7*=U`j>-uO!W9^JozIeOu)M3=WYJ_U&GAq{)=HXjmB ztq|{1N=B}~80EqR1O`XqkFTDIf?wyq%3gQpT)p?jZ1EQYqY2)fJv*HsP6v`chxM6o z!Ip|-q;R_*mq@AS&%goMJg6$oPeX`H>t%u4qJepmO)@8c;SSlfh=l@0GmpIag#e;e z&FzwI2QS1=%F-Nh~U1mQ5M+wI~@y+$L4y z#%c&?J(oTJRwk4}&qf_UxBm3!X1jBn`MPdc2lcCb??>-<8t8InxwRe;F?C>%F@orD z0eDR%1$lM-y%j{(gK!G%sqUM9S9ceKu}4-%WKFfi`AwFi$02L;+ zE3{90IXsBcV*sojm)G@a(Bl-`$o54JoI3I6q6mPMFEwzTUn-?55Vf<`pkI+OU?squ zD7`(0GX4x(ZFt9R)o-pR7e>+(y2bbJF?fmPzTONl5@riBKj(hr177-pKVU<;C7- zRHN=GSV=T*_=u-zy;6kYL3?#Q|6-nkX`W^Hya8wvx=cS6q&VD9fBBX8IH2yK+dv?L z&1#9uQ^qN<{&iV?5zel^hSID1_f#M-aWB>}TA(h)bW)lw)S@NZ2^Y{mn#F)Oj02w{ zu$e1$k=Gc4_snUr0-(O`mYpiGz6YzHU(5UTIO)tI!UNX3WxgJg6suG?c^#C()Kb zX9!J*6Xqm6eE{voFhGc-pDtnvD;oC~6o+kU`Fz|vrrRop((PrTU2n$aLARm9{tqY!Kasu!UXT^*VKs8woh}Hf_FC9gFxzr z<4_j_m9;wca}|sRF61OnY4p$X*tn7_v?Q1iz>Xe62jd7zy|?(KsDex0a-TV5M7uQL zov-bZ?mT?R??L!pb3?orlo!^JY#m6G?wUBxnYEFx3}NP)L^RxFSswDBXFrYyFPgs4 z=|@1?l}W7`3{|8dqnv(W*}w>pf|ZpJ7ZJ0*%$`X{dp}Y!s!l2Zn6783D7XdnM?542 zW<)sLv~l2bFpSl}vri%C)V8^tkb{3nhKu??Nc%KXuc3A!&VP#ZgSm(?l%OZT11@|o z=>t?jV3o=>5+@$Z`^c6|XbWxBHvK1m_|sdx#LJAJpGY zweM=Q+0f63?}W%@#T&m%RyS%xD%b}+T`Qd1r3j4>F`hwc0dCOE?e>lU!;@?fc*I%i zA@3^I{9?X7_w59DI=iXansmS*43l8j-w7kV$GFqp(yQa7lC(Qdo_} zlR@nj#iv9IJ73+IB#Dkhz2OlCbR2<+bP=-ke>Kxy`R75YD*)yQ>NcpGni5*kxB( zM{IaINi-in1O(~xOdyvj+r)VQsrh+A518xMcIinL)R}!U%@u@EGzf)wCT9q-nqo;e z=(!eHm0cxVgqvx2>e%EwL|zqnpg?|M(XfQxIL_dKOx_^pM6e1?iKFT;OK>e(MhL5i zd;*KJ9!q-<^^W(&*Fbs$G6x?{%r-2BNIBacBC1;a$ec}BL8~}C^%!AkhYe|7X`>!i z!Y42({U1_tnL?_}h6u}Np?Z2f8!S#Je>`s_O2VN7rVTb}AzuB`qWb#>`Gx*>y$K3x6bU8pcF7TpdQ;;=hJIr za;^i|%s~)7^o|zBQl#CF&PB8*X=<8}t?(DqC4#fosSq_t;1u$;& zLCra?gwUdoBT3QO9g83qX{ndaD#+n+&V6_)NWI+O61XCIZLnPRRxe1vy4&yZJ2~X#Z%dIlKM$> zDjN$MvurEml3^ONs6jebaItxwO^HzJ(Ei){*c6oW_zmF3wGePGfH%xp&s_F%Jrww3 zh51n&3h7zBfE`{eKSFC% zvq2E%hFlAW%uMFIAG#a2D;n#X#1Za{1V}9uxrzB`(WN9@{X?6@<;tI5-jrNDm4itHYGdX@z-_OX} zO=gu~%!S1vlIs9ow01%om;f(j@uS7`Y1b0Sr*j2$wPB9@7P%DAnZ6Mfysv)#Y-~wDPm1HNWlRb<(FzS*D z;R9}N@{yV~98K~-{T1u|^j3_uZBV(`8+i0Aow+u!qC$vOq7s8v<=}bCi0L)XW2dy+%(>8?FL+D5WQ#dC-W+vL?XVfib1O`+m zmBo^!jW7GqLu5fq0ra{zd^PaIh=`bkc5~oSRy3%roC;#k&`2n~jXj?>lq+foM5Twi zESJS^P_HjUCfV#+e>UzhIz;3Qp?w_V&HmBkIM?oZ@1CiYU_j!6r*^lV^YZ&{ic(kN zX!6Qm#+F|=@b+@j6~cVYGLf$ko`Mp1*9{9XKK>VCApUO;W_V;+^zuI;hMJj}OR#F; z^tq{XQt#&fjxhfDFT)~?;k6}(g0NO$g6{_~o69qt?Du_oG_jWJ$7K9`k2$320lUM@ zmK(F-0i_Y6*m+9~JfC))jvx1(;MU^uAVLbk{m+YBw1=qnmNqv*tGWHJ-OEY>>rXG+ zzh0n5rixaTQ}ch}y8prn$*p*LoerEmbYiF6b;A-mQ`e%DXTC7e=a#lxoN0|5NE>o=9QPVZ7a6ug zTW5;Nr;i+B!97c)*H0S@%mjW7B@8n`2(*2j_J=q;Hn)R5DXd;}5<9p7#AKyX$c2*X zHY~2l0MEV8=a7tWisjC%ZfM}RY%j;BdZ@z=%!tMuLT`ft?|~nf`Fb(*CpmeILi!GS zB|;gi~0i}0Pz^kG~qN*Rv5rv(A2Vk^+XklTM?A#}0sle9CM@1g42Wr_OLA@Z zrZA^3fxR((6LRR90zD1bFLU))JJ&2Z(TsPuht^8tI-O;|<#;M~CXoVcA8=4F`k$Cz zX}?|odl-U3ATQ0&F5m}`?h2ZSNjbhn!Mf!B$@5yJXAeK3__6WWDG6RH{W>zTsb=*0ovjNl`m(y)YV|-k$9@Kt z3-A{XjDyPG)88jK`HarjsZcskI#(Qm1%5`LTixBTnLE9nT1VYR1D}Q8itjdKhIkV} zK?qn6gk%)xCG7FQv?a@70HG%bzpta;5Y>B2t`%NK09FwYJY2VfC(uyt1?n_zA$j(7 zf@kpwI(d&YiE!0mdL0KvpSNsD0i1d%5z`x7ovOj3n~?yuAu(N|*xTY;35dteh(WV;bpt=T$5I55!KCZhk~tdvjU{KQ z5$h%{1N!0`CX02I$=VW+8TFBHr%ZB)?wXU!7-a@j-4D?%m|l&GITBHgnY5s{N6xlxOO^G;h%BOP80$$Ume-DyPhgvm9;P5Q+ z;d({clhbDX4t`M)j`T$}2t*D&f*#G^2-u0*OY3E0bvV>YzM@GKU~ygt58sm!$)14t&xThltn2*F!W-!(8@Rk*Uh${O>Li7jacoE@EF_VByml` zGy2BKj+edVKERSl0o(0PM6Wq{$Mp=|2A8G^>ToB7u^4eeZjkuL_u}L8QlB0$-A_@m zWYKlH9uM{!!>*0efQ~mu@3`#{LZ+fT2kzM8@bughb`~vtdp1a58+!=p^0C9Htzwy> zoKTQ~H?V`pMh70byGn0mu;V@|g6o8Eg#o)GYz$!K-`{)c6gYiS4?Q212be=$SMTX^ zaN%j4kK5#_pA;`RYz9va^YU;t1|&m9z{@eSX@9jek+`T+I`>_muXE$78%@Fhu-5%h_ggikDWp@ zdrs=}@Vkm7wts{NQk(C2!LCr&Gz9OawzSLPMt3+EHHY4w zC<~F{RhV8ys?f4`MF9Krtu49G3B1#BVW)4?uGnJU~UUUyI)QOK>4%02X)rr)8#3FR@tF`a*9uyY>+#Uvy zOZL#CzXw4L}Q9b-#D%g%+h$qAh?bY|7)n2fDrV&qD^J zk_sW_Zqq|ex6Nq*i0LCotGn9{fQ?Bcx@5&r$K*dr{lE^UPS+c&?x;GVi)1;Z0l~#5 zg?52_wsslFWPSzkhO#nH>IJV;+)2>kT&cq&+egg-ofo=a2-Bq^+aHo!*%-eeiF z^|p{rp*$1MJ6gQwYS{eWT-NgrICDA*fMO~zZ$I%xGuhgEStUcAPB{&1pzd8z<)1kS zXjG?@_F{&o%8kKz_-tYDu~YwPfj}- zPt8wzq`(*6i^b*k?6B+hGrE1Z=nh0&xYa@uJ_hW>)FmW+qKhRLrsufai4Lp!l1;(`Q}rtKG6YPA_zL{7j=>h?16bU290J7eK=?w`w@GeIsrAtAUIH3-)Rr~$!u-htRZ!T#CE%Ek$wTg@^_k^&-wu3Bde{618ZFUm?>6m$TaOcWauXR1amZQt! ztWre|i)CLmmWUFF8!O>X``+}?RmlyQ1g0jFIzTy>cCtNe`W?$y@^CmYnVIV$ov|sv zxP|m{fhlHKJYkJVHOfVAhCkQV6z3Sd{e>sl67w{WXBdzUOgU%1cY<4-(jI^U<6t)Q z%V-kg07r=MBA$bndz}N6Su0yJLtSg|x2cj~m~?6N7M_r3hPiCRPXKtIs-9+PhC4C@ zdh`T_f_ih%Lkz5duJunFd{`2?m@NA3O;~dYBYk5_!C1}&Ml6}%Hf{EHl&W>C^*PRw z}d1NBoLk~$A}WnSqa!dbQN*mK_OspwMiMH&w? zpnjU$uL7YgN#Ri;lbYu;gA_dU5Lv8{iOe{oLg_G|iNZ2i=c%#kDl zN&@OYaCkdyp!D74ByNPBRd_6pYBs5ko)h*IQ4JZ9KJVux8n%t*>kQcMb{fZ@mt$OT zzRjJ?Y2s>wseV6}a4#nqo%qE9_O1T=YuMfz9vD(!4?O-aCizbe904Bb|B(ZShsURe z`#=A4%1Mv97p;^FNY73L{E96n<{rb z8nN3iyLWRE`-V_$r>}xrF0sf&Zgcc6oIQ&3sdc0kKfGfUy|w3-uK7@<_&x6H7@`$6 zJzeVI{Rr|2+9*;3RWGAn16%(YjjYVTC_-P-&M?B8_l)Q|LtowK5Pks6xbDZktJkX( zbKJ$lholbg^fG3BH<26mQAJ+2Sm1NOBYETTAp&0d7jhC2;yzMA@0-Gw&y+b4?NX~) ziY72|@0KjTCY8+``FwQ*Yd8=+E{aZDPkfSY(LjO9cewHJXGLkCJ$_$>Fzfv&g{(7N zVns#FF;2Xz;33-5%C<07q&wd=-8HpH{_DulFN~jw`SolBNujo_f&@|*eCPzD^~=mY zNr~JFNKE*Qa7sy}=Nm-j1*x^?b&**JmqE1ruZsu~x0oBdCkfaU%oZnQLo_952u7K2 z%7ILXG_y4To}4lwGzsJ1RU=}1Oz^v_asdf7<>{cYlD=se#9Y)`I>lv-YtF z3r}W}izsCC1En=y5Eth&*4FMU9$bN1R{)tLGJy^&wNu^tkm63_dpx6IuEZo-HkF#I zuZu-U)kFIo(*!(T-v;PDZ+YL0sO!oP)}l_<-CG9p=QRaMN4*iZ|4KqtWgSKc<{(70 z+Ki%n=N=|^Jc&&wYGj&PxOYJ%j(YXHCB_n!Q1&o1K-WvT#=ygXvLsxatjAqB@?ZdS zb^Ev*91fS(pY{M6m=Dby*fYs^9JvETrJBFV@x*J-jS6<(>ZqD~k={w9iGH*`Ph^y^r5s^F<=Ugi*t_ zrE5%q{k3Rh90IIlsS($+i;H5a3itfBr83ia>S0()Q;8R8VOla-NY^YbS?w z3244*7CtgSftj#0g2NJXBJTyNAXL6QQR5uQZVV1ag9reUk_3>WchiL?+DjkVzKkLQ z2%@U)G<7*T9vfYy@hv~RhA}Jw33k(cSI$hrj0GTer&GjFw-N#rM^mBe-zDM|7&E#R zy3;sw#8fxSXQx;z695EcGepXq0h7J+7w9_48$f3hXK$CrGg6$` zt`84tFXFl0vud4)djpSbXu)Z`V4U=K>Ei)dD=MuXt#^s8UEOru`-L!^#Yz;JlXc{{WaEAk2URE0EU_iqJF>Qu}P1#8pt#;)m8O zs>ex?X)!4e;En=GI4Z=)as!2qcWPL>M~{5xZr%R?ml+tGpI;ahh+|bB%PgWNXXDEV zodQO7)GQ4)-~utoeC3?fOwjYCC%k6#-3TOeK~aT{WdvpbI9gMeBoz{XN(ePjc)~#h zFcv;%_`nkh6(9$Wtf|QW46>k$!Cr@1Bu2D_eQEa`+-Q{~H8Lg}CnJC&6xtGP48-Jk zn&mRdi`i4CIl_1mu27kVq^+31-iG?u27@ODL3d~WFQ8PVcL?WQm#d`f? zir_9nUnN=N?;;rq7!V<@xb9~J0!SuFA@0|G>M>4wR0?`O&JwA7$o#pgVTxzp`N)d9 z$N8E?03g_h*I6#DKwyLF@?4neWAHHrR15(izZRwt69%-xt;Wf39EX7;@BXInk~IGK z$6(uA05+apHRA~qM76>Eu{eu2^bq6>EXr>qL#6n$DdNm_Hj~LdnP^g&MX#>15(JYA z93-g)>srK#H~GAW0{3O!5_j zwjH=a38)U|S0p=gUP=E$1hjGnZ1z<8ZvLYrzc>@$2| z1DU_)0l*{!M~3%X>+K+k0*xPW_{Ruxkrq5%J-5foDKMA{JxRFtpE(mHoU*<@HCRYO z@j5DNqpXq+3JMe_oo_4W5EJB%H5&HFlF&$DnApX5a>iQK_E3_4-&F+ywmf6)!)BtdZ=LpmbEW9Z25k;pV0Tu&bW^0JPtX0Hk5M#Yka3F_Hz9j_opuj!6=J$U3^S zA9T}+4>Spq`oKIB1S%qv8cDb%%kW5MV9;4gc31wdCFJ8#<)12BL>DodHaY=%T)Gk$pSk0wkCA)-Pvs{CQ22mw@s#9lCEz(C6;1|Jkg5fB&z7%y?jSX>a$G7V zta)GM${>JiB~+pSZz3e-lN97i=?_^N!G|7VPt6!wJ_!C!aPf#m0$o|teq(q=5^x14 zpjlJ1TEV%ALNK?fmLh!&n~?yvLv4zVo;lVg0I47m;Lo(hYmapp~q$`p8jE)eGa($S<=!hHo-aVB>OsOWxH8@ncT=UY@b2UD=hD0MG1h?y6 z`ByXq#=z4>*ZBwhKm-M8x{vb`2w|xoL-U)8R~`tT=N<~CN4EM%Z0cDXOC~Ug< zeyPXS!+_L>Fvd(=q|`SPSWK$GDeVHuuqU-0 z(x1Fx5nfP`cyta;LpGG<@NtkLWwJFjxx8yj z7VJj8KRG+)oRljP>k^`97=8y1c!x1=C&#uGj!q>mnBFJ9Y2*CFl!O)}nZR>mOA2%2 z2J={27C$Wc#-Jrpaa9Iw>Hc5yQ2w8so|N!){x2XTQNscYumHKNutCuW@=wknaaM); z{9v?zm^OC6e_0|*TY~eXofC%|i!gcid!U%Pd4hT&}0iS-o{v5lInV-z>0A=ubRiF&6BHKPCq5 zgIiDiV6uRQW_>E(ePHZ{9Ka+g0f;bd**kB?eI0X9`!vKMxAp1ejz9vG9 z)Xx>qcisd_NhLH=OJx!|R0tNlz|+5T3$2QRhzv0dZj5CM8KrH>V|;nV1`|m{q6e%JAh(HQ;F5Nz%-#tO=ig9_^k2!x>#R>YR98-c~rxC}lKY}vw?oS6b!gdz0| z6Zyr3lR`3KIf?vU0RsjRNR5M^FvdGJ-6TM%2#_Ql9<5faGC%POGN_#sAB-wXP(2^tk2wQWV1qY? zZ%?eA(4|QslT{Vsy>eQ-1FRGhGG!Y#+UQ{ zfJy?0R0CX3fW@dtB?~4~;EAB}z+xu5$wdGusJ*0W_2V5=Mr23G2XU`C20i2YG1;Y( zBCYPKj(Ir7BRh~S(4y)v21;O5#6oY+?P6*}EDSCBm{zUe02%OPj15S?mh}^gFqSU^ z(a!G)qPl{@Hg9=02y7(>X8!;_a16mC2S@9IkXF=&cCX>ZMVL%0%X`3Zk^n{uxr_Ps z!;iKlAxdy8mUz}cWW)gruG$3p)*;-|B&r+jYaybfAk6ULnv8;p67f9D2z;}GlA;h_ zQY?($_PrElp_iULeBu+aB=Hq#F=wU%OSv+JWg)gaZ!8cY0Kw_p80=_33jWpk$27r; zQ15Vu@!kLiLkv6Y5KV+)2XGxahx*a5q2%yiBZL zJw^gp+f;`=vHX~AQIR>Lq3GA=1}ddMWC~S@FCu2BG3q2n#76H3ETK^fu0?{J8qKN2 zAi_RdG1$m~1X=Op^NmI_v0`oLU3}rZNkt^sdb{fPf+Q6}GRKUVqyZW?Q#0v7s>fll zUC8aIUqBot89|6ziIOkc;&B30bq@teHS4T23=+UZdcS?LdjyjI0PBjtfQcq}23O)Y zffS0gK@7d>F9S&_ah%X%Sjm7XCdz`cj*Pa3AOaK8b*$gw5Gajt>Fg7%4`PKxUoYky zX~rH{<4>k44F&>8P7O#)5vHy$-xoO15k!x%mjskpnDC?n_ZUJNjjEud_%+rZC&&nx zNd_^*S2*cYE|;M&%5S!?5-za#JlyD>JmN(ms`eHa2wnQ|miL>)L~W`K@5Ew*g`zgn zMVfUmZZV#s#8H{GuU~8@NJfC$zy|zer-CACjcVh^Y<-|)A=D)NhkQ@2B(n%GJ1oLP zkvBLZ8#xs-mz>SXjdr5FJq)3cj1vyt_w8PDtEQzthJHie6`V&D^(Bv9Kc+ZM>Y3j- z>-6XTV^Z`5Ua^yzH1R0lYwsNqB0@Oci6bhOg#!t_7ka`5C!2p6bUO7WEs`t&IoYr4 z5G&(iH8uNLQ7p;BcnT>Jk_njC>4cl-V4H|pv)6cJf)_23STo-YQraaTmbvqilQIgs zl>W0@GEd6L{WwtosWfU5*O9QvJ)Q*^MO zX0}*oahg!`wx{~YjRz@LrX(?jp`r))Mg&P)BupLpWR-V;D@z>?_@400C@lAC#3YgJ zyd||#B1m9lo*tu#tP}x;x?0f#zOqUZGKmmQx4dU$LkncmI3(i|u!2ku9nY@!#zC+W zjl`}CZM{6$a*3b^-2!}JIGHSzVwIbD=ObqF54;N&a0OfLVsJ$fK>@na2RQ_$a1A^p zB5JzF>a~g#G#_+MF(m-B1fgkRvZ7}b5r{;`Q4|7xa#CQ~4?B;#yids|O;4su%Ra<) zoageGr6f#<(;dX?1#8+;nDoh7=uyKghrsjL*+D<}Q0gB*nF^9@(={N)MgyjAHxpZS1D zorpu<9?wdoSiU9qj3SgWI3>%V@Dg*7g)%EmbHK4eo=spR5l~;bBNy&yK?}Jb+23w2 zktx18BQLADJmiF30|4NnW%mv6WG7M#vO@||B00O6F$lY4TB3pz%sjN>7-$%Ci_! zm<)dLhoXR#OkI%iHP#9hnN$mJ);3mIKnfyDG#BES&OopU3nYt~)MO@F&9NN1H{FzPC<;E4U1>AdBO>jp)#XH zk3$oC$>`Qxh)Za#o&Nx;jhV1W2Fn>3^~;CT3N)X{zd3rss}ZBmf;`3`BA$f)@d<`f zE5P+v-a^1t0GAXIZT0w5kpSR9@)v)D%nByCPNkKTRB7h9#a1?%D(t1K3$AeBg+X?N zBq|m5_fjnpqR`j=V-CU4msbZqvyv)cIbMSHH{9Sf!nGj&AA=?n#To-Cww>UDFzzQ! z%{}22A<{wJFK6EwJ$@nG8lKDsi7-M7)N^!yv4E;F2)4b+pYP!SNDnglZ(ZZb5u!`Q zQZZ-7F?P$WHGG5e;|DinFW4^-66FYkn7Em~s}hlxwu$&Nez-Eq8Js$aM*L)j2vBOE z#3_o2v4VU)e|F5!#3YP;_3P{z1O^4Te+RFg+ylyt5K+Ekey$P}Z4?<7(q zEUZsAFybme0+BumS5d2&z$QkBil>p==j#Fp$mApAIyNr<0NyECl)f;MDAXw!($O~5 z0WRJ9YXCJfSC|9}9K&jM&4^KumWT+7m?U-16!4)UK`B#R^;iLn01@ojCH&zyhOoj} zcYJZi6B5SaAyITN9Pd+si8IwiELj4`vn;t2@~&WY52o#Y7`l0iRu zoppdJK!xDln33gCwjl2z%>xi zkIZBMMh8QN;=G?!A?sHniYirT?kMgD6-3vcL%)aD z5L(KX8=EDse4;I$_WJSn;{s5CyvH|%z=WhB=xb8kZt`k_Jxu$38|%+5)II+I^Cjfm zz{%tD*mt8G9Xge|OB_0TBXAGS90YT;y%Il1;@0${_9l(T zd%-C^rI&9pe?HkeVwq*$Xkor%zuy=lfH4ya&h00B40no9l!KI1>QV4}=QSEi?qTd- zY3Chdqw6R;pZz0ogUO7cX$UNp(leJ^SOg1YA~~5ObC>EN5bZ%U4QhR|`Ku5rUec%7 z#=us!(E!Rz=N`&rj-7%P>iw~q^3f-h=s$Q08FoSn4n?vnQ@km~i(3>aoCR|DaR8J7 zB2Q=)!M~}b=p`e1)4xfaHn;#*WH`om-4j6}cW+a!a6nv$&{&8Nr?#>f8zfJLzOtyU zlZV5`vs1@85I`E^hqga8f+@DQX1R=l0U#tn)5K1k8r3_CazdwB44icA+uKkR?+vgw{P)iY}U{B6ilN?*`Z@dl! zB5$ylj$q&rZqc^;!NqcfGg^xG$uSIFzza3FPn;hhz(rT%_A=ENNU(9gI0{NbFpFAR zZ`k$8fdx?Lya_;LDxv3^#zvCRw0Sf{+MHYziBNYYfs;AQBl$3;_hsQSj3_eQ0G-4$ZBIBXHiSH)pRDgsF0?|4mBW_$aKt%&4k&+~Q zFA_h@?#pNjg7-aM3=EJmRZ}d)KK&8G&;+4NH6IKdMLLdodQJz7sv_bcUVjwAES{W;y4oYp9ijPoGbLk$Kl?s3e zeHvQCb&*A)gec6L=KALqsq>4gjY5t5WJb}A7BtG8MH|)}STMRoNFW2=q~{g509J^B zXfh{w5Pyyp0H11!)IMMY{^#ii8< z81PqrSe-~jRba47xYhNF=S^ICc>G`xisLoCJ~YNdf?^;sm8*EW$bd*e0)bt=zw6Kg z$U=q&c>)|$00~wm(1Z~tu`3Kn2*^PfVeP*>s|CubdXPsyi~~IN2j}_6Qm7DPxt4hO z#Gt7v096vCL=dJc2oh9)0VqlT09xKoG_;94LCY`Mj%hnB@S)d#j2rS$grp=(_HgY2 z=4=|d@js{vh!}{(uXs`cI)UHDBjKJ)_&ak+(*r4KSrj&I_K$*m=V(wYNl$n8&1EAoZBLwEZ{+^~uIibun#2$+6gB)~ zEQE(xaEJlvkRGJsW4IP5dz6o9YZOw>0E==IB!d&jsTo*NC=*I_D45?EqS)C0lB`6* zy2}k9q=JaOruz_?%E0(Af@$K;7uzO4fEflR32EPW?3P{xT`E339Eq_2ghM9dla1hH zk^%(+?yPQcZX^N{S+SBQ=ZnM~5DOqnuDK_iR0$A)1|cL8?w^VT2$l#<(nwu+aQWVe zrV#OMu6#yZGx9-GP~6Hcr<_PG#33?mAZLs$0ty7KIu;Un=OAiYmc)d{qFwRJf|DZ} z3JgMs*x1G*3>3f;f>1qo?~Q;fzbN&%)ZvkxR|ySDU0!nCO!iH|tMfa+qYz(lwp~6w zOpaC|%r}zJ6c$OMkb>`ixR8KW<@O>nPf3IdPzZUjmw1{aOc9k&i+=F<1oDT)II|#= zDvypn@-w@L4r2l$00{ycnF-%v=@@2`lmG%MB4$M>^N)FtMiH!V?jPKg*d{@MrD`2@G!t2^+{S;yD~)}Aw_p2o~-Ki zfrh4U0c> zfH4R{Nm1Fq;{_4_0HgZ-;KWGU#)>|EF5Q<0|x|6Q3Ws^{ohqTwhiU}l| zSXi#f=e(4b;g_4u&zI!?0IZlC$?{<=PX)rsK0Yv^2&Kswpwv;&ZTw&{pp=a}ka}Te zF7Ppu(5YACBbndZQ8g6??K0i^>i%dm&k=SKQy0ZM?sn~ly_=V_9wq65mXDcPl6*v35U?5UQ zQk!8$z4AN(js5fm|UNNNU3;$>IVOfe!y zHzF=SJISGTq^Eo0yka=Y4+2SUzmo?TgUF+_5e2-x;FGes>kZn2!+*@;B0(So7O=A@ zNTqHfd%T7nP9LS!WvN86`Ca<<<&%0{dtzjYmvg*h6>@pR|u zh-nF58KkiSW>(0)zx4>#WP!VYz1BH+&-7{@yP}o zOeltYg!~@-&V=R~B=QONJ~CX3Y(wEqpLu5v9yPBY&$dDV(Il1wsVCv~HRW2tAvtz#%gRxTremU|}~C~%BUCwiH+HL@%tt!5E(qP0mu!G%R_M$!hnKJkE2 z5JE`q8D6U813;cubY>+Uit&L2Q5k97CU|(}uxUt(B@D_QLAi+QZY)Ru z3XIZAsFra27Q~)4ax%R2SQW$QahHC#^~ymUlGqd3$%T&jy63!Nulxgcydn+~1tH>H z$9Qnn1jxfp8*bQ~GDr{tTPO;NYn0pi)q!)=UR08qeQP=9XwBX;N)6hJ4`m-7>QpghDMbd%4OYatYI%jVg=tK zN>I$*vG?f!loq*r%4@mxFujxrBE)}UzOD^5dsMlgvP)5G@wmi-AuWI$H3IyYIU!{~ z>y{va+E3qJdGNt7Kn|sUb+4?E5+(sR^7hBAV2WWLIgbyYyco7@9V=4pJ+aWX;?L>* z`&=RuXbo@h;L%V>WyoUZJU(*EyFF|A#YH0e*W_k1Kt`B`N7sAKV$5x9H-Kb8$BCEV zKb&I3h6Pyv0GK8sjoWy}iyCoTez#m@y z$M2w3y$oyL+nl6y43wQaD{<|N2w5$CwO%{M>I7RMi`2@V@#7nD7LJ21rTib#1VTd` zu=?IfkP`OmgFgQN@_*FWBrfq70dl)X6LFFrk}SKTCG$b;c=oa+r?8Mu>%0&eQ>HM{ z6^gCV;`X34~$5d^+6i>n0Fyl6E9 zGUT3IsvANAU%lq;qEKjsn@<{R5fm!|C>oco&*KUmIuRv0I(geBJYw%u5kAk+#Wr)- z?cr!TcY{gW&jxEcznow<2(L3k)YGb4X3~-^uSn~5i*G7OeFffR!}`O zwj;k>h!8n;;JR=k%x(6i`1i;!z>ec&i0f(TpYzn9SDaf0xZ zenXCj)xf*qP|0@!{z<||DGNv3Lxh2LMbWHCKxnE?{;l-)SR@Gm-`C6dHSkDC1ahLy zoI3OA)|Wx!Avc%g{{X3yE9=MikmqZ3Bj6ZZ8tj(E&LZLmAdTNM^?+PTs;nH4-|^lw z266$bq-}tGUGxD&10;q76-lSBY-*(F8#P2*&ZEtZ&ZdM86Kq=@{0Bfn(oFKBjN(5sDxPs8BLg+=(&XN;-n%Fq%quCVpGXSlkLpWjTdq--a>#J(pD$wKe?CmRV>g%Fm)WHinjDnO_DWSkm`Bm{%u?cM;A zm4<}~YABpmk|0OTO8Ur*m7)-I=pV-L>#!<9Fc1;z#vLe8K~Kt_BLy}=2%jMJzDy*W zHNXx6N4qQ+UX~3B1cY0lU78MK1UDCJ)}us z3T^a6-v@aF@FUSrJRzfeato=!pHfY%xEdl5U-Ac3`eOq~Vz$=S8|%w~H#(|>d0L-8 zJdi*wNdQaH>z3ByT}I`5^OHdxw{{S2R0M1<`CIV2~-JdZW za^*n5X2$rJ>?gMXPb%eS$UlCaMM*Wk&ExsMlm54XsVAo!1*bw1WN||;CObh=22*sw zH3YbtxYz`23Jff46v;%XM!#=$gNkEodZF`NGEVh&p5ofgYYC0$9yLUp(~haiHe7t_c2TOaS?yNdDa`gp|;vJY@JJMJBvNe_zf`aMpvO0^^TX zHCo7FS*Q}vKz(0);s#2x0UEbc-tstNl3dL5LY{x|nTo*4G;7cG{jdlV5lKDd{o=s} zhz_QBRD3?GQ8;0i?@=FkQ&qEHKhAxR>(hr$p+rtUKw?19Ktur{vH*(m!N?JzJc$)N`|AK3qf zSCCW*n-O#OgcEle6=Q`WYW+BB1q2e=B^~NwZv>D6$pTXg*$v6aKZ&rC`2kICz)Ah3OUDW zE4UPha(e+}S_e)s)--L8x90+wqSQnrQkGeR(?Vo+n%A!d8j;=-2ul!9Xk?Yr-a0WP zMaKsQu}n}F4*~dca5OekD7V1Yuje5pB}fL!$Amq)$ZLGkZzi98X01h<6#5Ixfv8L& z)d%mc1F$Y&Z4X!9Swq^2rI{ylh#U(9|m%9#mT-=Kal&=`WOt$ClA#Jq|vLF3f?K8Emy6@vt$d};7{ zS9xkwX#8*SacZ|#2guoUekChnf zYQ1M15*U;km1M#a0S}`RK!?9w<0Y5{1lTxQp0O%uJ2s>^)R*h57^oEL4^j=2pxe=+ zBBOH^f95M}P&^30lEUeo4_Rz3GOlu4B1?d3O@I_ zJIF(}-M#g%ro;m+tE9j9Zm`fSE zjej{T6DyRCKir67ETKUV^w-u3U~mX@L{B~X#t;j`5=eZO^^Tzyt9A0jq!Mu-$M9gV zwCoONqHXQ;>Iyg^RLZ&cN?AET;@`t18!8{5B zi=Hx7BX4Wz?SO1h2M!sMdWji)>LDnN1+zBuD_h8cKtd)!HtGSbdSg}QWLTS9B41r& zXzA~1;TL|6n1EI+o|u~GPICQGki;MK4Vxg zydq06q!eFlluH6#g#>4rDd!T*g0ljw?tgkQf!OKNjBaDvumC{}hf&YIO!_n(6MmT| z5+QF9$TV&bCLDS1>hOs|C+QEr9OPm`$||+O{{SBvDU8Tl*e)-PHHCB-0yhd4YVG&r z#;GAEj)M2d`d~)^CCSC1f?viGfJ9K-xv%K)IZStHXgRr+@#&3FsyhK)e^|?b9jonU zB_@cIPx1GFskMY1*Ykjg(4bN{(3pUn*2kode;5*7TM;M3BfN;Pz(jkv6QL6Pc6t6WfJ7;97ie{eC{hZWXl36|Q^p;}K?UEwxAl`n zK#6GAmOc+o*xKk_etOHQu$4OJ1cWLxve%|{dXCJ1MnHl%3dT6(qyAwKF&-GYw#xy1 z@MRQgmFZa+o3=NCm|{+F01(#(a&&mYBcZ2IAEWN#mqZ$cjwM*uy2lQzKvIzlqx8rj zEke+;#S7K9@B||@LDafebCN9yF$9ES82e=9#M&tbQ3RSS_ly%sq9nt<*yq;-3aSavG#J}x;cAVT$Xb?t^qOo=RZE|hg~k>?QUF)gI9H_*jl5;0~YapXAbydp{= z0->cLx_TmZO`xd?Mq;Ce25ZkRLTMB@#u=28$DBwcU^9-9GX_%%Wug?I81;SQi!COk z@PMoK)+#tCB=S4_`(n&XJ6cW=Ul=&h0L#{i{{V2T;!EpAO?%)5^&=q6*|HxR#knwr z#tk+xtSB%p4^L#lgqXMkwN(7kfii5Sa6pL|fR?Xiw!cP)QcQZEE)Rv-iwG$o5(}s* zzgx-mrlSdMsuJ3_HNw0ajIMZ?l>VBb0wwd5vJ%-Qj^i2*wiM;vn*E5U77m^QP% z+@2t547&1kJg-`hP_haMo?kepAhaFZ9KsSn_8K!Zd`IOG}gllobS4Oj1`OEkR7 z{WzE)#H$~nJ@AILB4XSG*S|NDXQo6_*FgUO?m?nmFg|2d_{fN|hO2+pDi#osk>hek zM-gHm7NStEjpGnlW=api_~Qxzuo6MyMEv1mgkUKyE*kH=sDs)Q9~ScB;ekZL%~E71 zIlB4&bK_0_06ORaQwsokV4VI@J_Zvb6~Pq# zSGR|snT%U#hCm499P#IjNMAt#nGrjCW$Jbv(@Lq@N}fCCB^;_$>UFxW*@prJghFu| zgW+%nM177xB{pug)(_Qyuv;i9U3MNVNeW5;Ap#&$;{I{302q|tC77wBG6<)dE9C~U zFoPf(Wo9}Vrto6yLK0mRNF|MT&PpaGfmBJt1ycolAVI-1F zK8z%fc%LMrEC3Uc(G)3Ih3?w@F^~ZY5MB!P#AUKlz%QIg=45ro20}UuQqG+x)A|rq zfD#pe?U!7W{H-mBAvhkoo+EzJP+43qSJ}VamBl1V2rsWg?tG}wfCy2pf!BZJvLj@R z&~ks8#Ig}G3U>>8eb1Rf2E$UGPs8>!RMSd9n6@y07^GZpCsQPeO~)Wp)mA7>l9?6L z*U5wwQ#3=+tYytE6H^IGO~xWx6L!=3V}-Op1{&179b%CnlFcoqyZ&%00TP0v;QV9> zq$E1Nn!7(d<6Q|XLo;}3;3OkxB3;P^N1Q_y6VY2-diRoSvYvmuu`QBYi29$q(G}b= z9Zc_!-xv`COn}tSK>gk;4V~@^&AI;ooB%W!NYj-0zd{;B=cf|0A{>JuB>oc=#ioTn zYb!&OtH>sfImIIbF{r>53TP@!PezzUVxTCOpLv{F+DVaV>LK;+Yn`B~A(&m%$lqvn zi!v;W1$d6KG99@t*7-x<50ddUgYmdarpghH-4r=cxkzk-|Lb$p&tb9UAeAa*y@7>_c zDUy*8M3dRq)*>d=6jhfuG3fAPW*}jbDKqoOe>oiHVwQu?Nr(r+2oJptPM$ETMj;h$ zMACgdIiC<6h&JWI;Shg+V+ghH!LatOSiA|dH#9aQQGXac$fVSy*)y-4j#D7^MWpnT0*vb_`DoB$*`FO?I#pQCQt+)R6S$u!*Wnd+^k@_=PE!e z<6hll859P{yh2mlZ&iq4=8%8CIUr7*hF!XEe}4foPOEQ!kJr4FO2SBk(EG`=Sum!) z4Pi?s&X>v$+#M5!{kxcu#X9e=o>4n_(0GhY1SLk|Av^z`S~D3w%$ zUbx@6?}C96Q|j(7=i`_mGL#It^sDss$tAt9kfG@R0Gx4PJffI{;DY;>a5KZVPT2_~ z!|#J591@S1IM?6gpKE>L5Z6Ng0B88Xo53QU!FA>`gwaAY{63i_r%d7Za>$m&Y{=f| z^e3DIIl)lO(k3bRfPVOr)K0s1|{LFK}1kJ}vCUpcSIRaMZM0KWr^uYmb zY*Mfy%!C~LWB>{QwmxNp-xTx}K(4d{;xTkf8ii^AIj!8;i;z}{mG`_D3y_vg+)>41 zo}5X6p(@FEn2C%zpjmJgOzDBw-VXJO8(A%o2B#fn!85QP8Zi3r#)i>@#U z1$H9KAj$@|;cf{4W?+!vnSx?b>T+q6NJ%nlmDUe&laTe0W6`^Nw?5~P`TuWjNnr8v^E?VTR;fCRTML=1lTGr2m?hN0qKQ=8^U5t z@|jYdxc5+ykPWNA2VBLwgaJ_z1cSQ0bL#?%1wcEUo-$0MHBgwYykNL?QE;>U{ke=o z5Qh}@!M`|#2#+B?xAOYqitu4Ai78R=pC#jgKKj33=Oj0(o}~2W*EH)#z2HLFBLYPI z6Z7xELM)k+2b@9do5VK*dltKo<@6^a!3Sfz$85wbIlLmzs-Zi7p z&OKv(r?ZVfQMjx7PxiI*gO-4!pJbT5ya>sye(i5?kExZ{#+zhst@ILq;SS0I{EwR_$QAz`OL>fwW zINV|kl$1ER*y-T)tH~=|l!zRaEY7N6zzIO4LTYJd>m@PFos-$nBX@ypiy}yS7e3fl z3d|Tc!+-0O7!eNOJKWxicg7S{3%U@{7>UW8(h5VfZEL((66Oz*6u0q+SdwKgiPV?) zz`~FN6{*3&AWRWEpSb$V{8me|)NAnKVGkt_fAMiE7`e7KMkwr?_k6}AP?VK0oo~$6 zK;iH$Ab@Ono^dH}4k=GCRO7KIAwfASW6brMmE=H&kUJ-QZtdu1P|D*=^Zm{UGa6zd zKWh|AV4#zz*}7qg`2@xya~BW=NzO{j%7O`(RTFmmWYxH&2Cs@RQoTrznAUcoucS?6 z);2XL!WwAttdWAR3--xa5bhtm=K4O$`^N>pP?OfA$u2n0*th!2P zbB${VDYd?VZ;96t)+tLX-mUz3U`Ug2@fNzMN*C%RlpQWX_zg9&(W^5P@2iz_7Cc zLgZWrs?7Mc>|^4wB!q$#_r^tt0ptC0TC~(&I?*FwX~fGxGHT3hblvNHCUUe0?RqIW zGIWIi30Fdw z;JmUy0;wIQxWUAtzyRst)-b`@l!~1jFPsso3{Z%PoqN6HgXU;Jk*VSQWn)&tA;BXF z?eByV00>S)Y*~IU(KQh?vXX9J7m8?!3`(i`53CBqg#aq_Gt9g-bwR-wkwPBsX%BfM ztphv~UCHj7kz~y35|8H~C>TUeoHu?kWT_zr5G^AlUr!jw2vC)isXiQXB+kZOAw+Kc z1}#t!nx$21vKVn3vXJ)Ca4g4VN8oy3X8{Dy)EJ(p#z^r1 z0HZ@3@wvWnYZ;Ax`ee1DOvFEj_AwLbT(;~(YHi9#jx>DWWD`pDK$(@01Hpw78VhI3 z4AuzxVjD;y!XvqbB-oxYu7Xm38m4w;qF=%*C45&f04Aa`p1(T88AKDQ-^td#cwiw7*W28lf2S&kQ+T-bcl?Q(f!OZ|Q6$WeBn3el z$O+}R2g@CABFS~_I86Tlc@-XUibSf4+;u;EVIV0Aas%*V83Yvsue9Wr=8!^rzXA2g zLNBNU@@$#e+;Y@rR8l_{Wa_kNn4+l~V5GVH7d`w6@;E*uu962 zb)?04#FW_q3PhM*2d*m)Lm5LkZ4ygEQ9U^UaS=8w@)5q=WG+}ks$X8$#y2`nb|_Ou z`HU`mDlM!6YSQ)8MnX;!6?&u!cb7vEsR-H}GV)kmQ@XJr99+|rh!=0AUOx+ zie_b1A|hfhjJymAQu&=7L0a!<;1oLrMZHN*yPZsuo+zv~flx3#jji#IMlnLcq1aA? zTGbVd{{S9EF#cM`;D8|;Zf*(v_g{n1tr%{Y-}#8d1cq1J(64`MXoeLsvF$h@Y6-a? z;BX6k>&__{&=hZj^7D(0${bQ`8A_5us{p_cyr}{mYOxA#LQ;QRVsKEeqeDAATgmr| z+&Y2z(nbfFa-(u=u$Y)kJ%O(Wz!1s%c)}owB`EFY4@@dW8>0O;i1Wn+7;3@xpHEPL z=5|Y-R2$ReV6Y9oB;EM?ZuY6>kM;j)xXwh`Hmq8>$Bt%%RcgLV~ zibMc&3j;c=h7|(f1C7o7&OAXzlG;LbC${*-0_lo9BblV+*O6$LY7VeO0|7_J+ZZAc z)TaXqgaaV)LpgsG6WBK}+mp{LGNMr$Pkm&V`11)_X5>i|KD`Q1Az>9EErAusGfV}5 zm|;9a&(F<-gOx%a1)lgwmJpdar7r&f&c{VOARft$)RP%FX&sRwfRq7}xTJ(s73`HR z^^8Rz1hG4MJUsQ0t4{!lR|!ogM_5Efw3kij;4Z%L$d-T+tK{GQ7!{4ChL@}8)!?fD zkcgrscSsRa=Kyni{r3C96Icj9kKde(EpNuRSU~3F_15x^62PK$kF(8|Gj=c{d z=_0l|QkObx4oT9Nq_7P!Cdn zj3Y5MCBjV;zbEWilXkBWju0UMPF&z2DgYk1FUBF0FtAVW=N_;{F{-UV)Vo4?xhGADRuP@-| z*Cq(9331YYhufIRO60$Z{xKs6K_nM_<2`ogul~pU;|#KvGE{7e*AbGH9HU@6@Ak2| zRzibXY4ebx43i-4rrFivLDMj!-Jz190|zH$nc$q#hd{dmLpfm3~wyqDEp^$b-Ywsh!WW?3>wV@DULh_%#QZ`F;~QUMoz z6UJ_R9za*tm@>ujup`403D4#+5-MBB#NS&NjxZsF87mw`L2W!|0!0iMb<&NV`1KS- zEHNGld9JWQs%$1*JlEvG8~gzkk{e)mF&?v!xDJR?zo6jJ=cwQOt?p=UU_hbE?Q?aJARPWRg=rvook5 z#Bo@|64v(nR{cN%LQuk8hUuTIFb2%K;jSb;FiMz3fJ__z0C&bgHpDw8Xs>TTj1>j(;Z56EAAU*)HnFe1K{yQ80! zltBu&vQLk0vZw%*5I^$>+z1V(uMVCx1j_ngv{}U&;>m}I^m1cY3uVJd{vS+`sA`HU zs3YSN0xrNMmD#;{&KPKj4&JK(w7{`4M}~gA@hoBLglwxHSL2jnBsgem&3$A68ze}N zK*!AEZ7z{6FpwB|{yn<*!EFPcDLiWEpS(Li^M^E$O+NGUk?bBYP7=U}ZOzLb#OWhZ z3ZJtA_FZdY9t7><&Pmv=2A_W$!9gNA)&9L^r1N*XmmG<^L; zT6KvEq)Q*-@T6vk13f9v{$Z`K49G|>lKM%b04W4)Bx*QPH{vb8rHX`rZQRQ(RC*aI zTO#xo^C{KaoLhaZ0 ziwX=u61iDvsozEd6jq!L;H6FP2;E@|hsi26?Ri_!Ucu=+2$V4*2e7}0!4vQ_1Je_e ztm(_$7=)>qVUpz#V*Ro=sV)bwfkyyh@M#pNPvHB-C-K^W?H9f>v5tThBeMFdxX zKC-YozBTS|oRZ?HYCOEl^OVej9Dr)z^B(;qLc!)i4tW1i5<5SFhU=SG@!C-qr zeV+L;akFvn))FMXMQ?RKgPc(Mp+w0$Mq=yVH7BFx{{SRlLmOx*fj+{k0ES7CF8+S84G7QO{6mX8IYa=PE@bnqPLm&n zru7=AZM=wZ7$h=s@R$H10uuxcdill&xqx~OeKT(knvzp<=Mrg!3Tlav`K(4@Tk)i% zYakLxVOUC*=10>5Ch%b-?17zIkcT}qQX~;sd0)ax^%xT)Y2C)KcS;e1bGUE$!*(ns z`*8Qhz`~>uh>Bla8xSRstTVzz9=Qo=onRsWHxh=})(DoiOge$t`M+eyP)ekT8-?7| zn=mT1B3Jo$b%KvjBu^K@Qf%I|xeygp^S_+bZsdVg8(E|-;};{g0K2Xo&nHGWr2rD> zG`5fL0pB==qB_2Ltb{NCQc;qUnLEWqBC!Upjqs67<$%#G8>=k$+in2OK!8SOOK0vd zsAD-XBuFpel84p?lZ~W2#DsB zhZqy2r*o)|WWL{GAf8%t}I< zbCIUWN1Z2+yi%Dfy?*YI+~srvi!L{?JRcZ^#2l$x=0oiE#wC!Yh|PGD_nb`;TAh29 zuDQT@vQ5p)<@x^rNi+sl6gv`nCLM_nZQjdF_Sab)Nj&e-s3RW856jl(GghT?eRQFSUaHdFAfxskS zq*`7mkdXk6+O3!m1fuFw`o^R}QS3$h;)zX%R!&nBCI%f1@o$W1=>*oGSixr%D3jZb z;lL#*EV!?Ic*8CgU@&ymy77#3@{&k-K)N{ZAb`fkAoCpm0Js8;pjjTXT0Ljv_nm1H zz9$iZD_$M`>xc5wR!NFYOdEZ;$OuuDPeVeQ;^!x#OAALfaX3NK0EBEIuUegZMTW-1 zwTM07%>3p zJTUlU0ZX*VLFunKA6bw@lDYo?ca~cTvTVVkHS#!`DA>e2?+BE*+C{!d`8`Z@O`Xcl zxm9)B>yfa#$Ehr+^vgUpk}Rj*z48;%EQuumn2U}V79I%65!5=!j3ErvPP`NIjX@fj ziJ5r(J@rUjTQ>o(HT=d!jHJN(=SP+&<0Q&+`9J1-f^C9dlaV3?Lr2zscY`sd{#+13 z71bwoVTp02j@wc?25VmUpC!4SQ{?{ua%DSvWFnA4SWB+*i$;u8iqq%&z_{2FoNw2I z*~Cg&BZ97`y2j$d&3ly5^9g<3Dd{r{p9}uDAc058nf>M zxdB2;sg1+TL}0cFg%RGE6l<|V(C6m|V>uL0ZQfkN!5n)zdG8NSp;4Q9`N6G;Brs2g z!(C+UOh}mtO>i=MV*#wn6;sX^4->zoVY3^Ay} zOt|N7EgF>=C?4Kx%iAvSbP?DBVoYUOokI?p2#Um5LN}0vni=0@9&+nQDp64)%LV$I z;%?v;sV#1s1C8~kq%}YpPZZH+W+Ce?=RhEER3oiA>l(O3gkt zW_Ny`xieYOByjRy-UN2Sf&3vKSW30JU3MebotiScSayP6-%Mhtm}P?X;#`>4;2?JL zPP%c#M2KLLea{<@ddQ+7eao(L@$kIodw-Gt07Se^atN`=ET~@Jd&*7&0EusD7yLMb z6Uzxlk4~}*VX`2v&i?>E5k%6+Rew0w_Fk~gG{kHR;QD~a#v1@lDfwk202-6ur}2W7 zi2#afBQAKXFcL~H^d|%Xoyf->RtmaO7)dXmPizpKiV}&a^OInr zVNy!_wf$h~b|frkR0OAO^*DSAFEFeknt?z0iBgy-u`mjoiFNAC5`f6S9;YSO-U_k? zsZNV#gQ+T`0H83EMG_RNb*w&sg3#jKbe-$a1<7(s`5PGQ`NhyIp(ETI#<)yT0nYor zF5KUsN0GZ0HI?5h7C`gvoNyQO=eyzVP-7+pc&rF;EH;gKFln*x*7;T_{F0#yILb zL}5!t(hbZ96$5=0SdwE|>vPc?x*G>kyi8ter4Z5sz9hV2<_o}>; z1FKLuhk`o6K(TTW(|-a!hJX@6iO+FK_@6j}8J__py*2ZQEE^Dy#MK;N+cy4hYiO0z)=Jv$^3uj z@>ax%AtcWIzVc@&SpanSIJ_@3ww@pQ4002`(LbDb3J}R=mw3icXfkuMxaSyFfw6h8 z#Ryq3zwZGo#FPm8-1x;Ij1&XPbvXfN3kbKqOROqb#zGc#6Dpn|)vC_HY`ASExGgFioiQ0B0JeP*ND8=@ehOfU6J6v(x0p7JaB%2yI5*Q9Un3FPjKtPgG_1jr4kceJyL zLJ`Of&ujykkosmI`No|x8jvf}YuUvRNKggIupV1|tAfR7lG>n>Sz=?w3NXmZ2-KBj z&oSo-EEW`mq0dNq9>6e8auf+%&5T?^)) zf(cI%wo(g+sOt>Wlty6{FsYf1{6aCQ6q2)WLoL2o1sP?5BTLv`KVU+dIkEeLBoT}W zv8En*!daRmBU>naa90IPSz9#|gWgyafKP>SvJvr{-w?yNsqv}6-t3x<{a^Ql0%c_q zehv5O&TjK|K-XQ7tT3?_?fT88p^j*gG#dzceNRbr&oSxXA5I`&dt!+5u zV=M;?8BZ}05vsG=^nAk9pF>0K-vU65Q4K^Oqq?VYHexH9wq{QY1(mq)u>R9kB&D=X?6Y%*9A7eK3T8NIFIS_mG8yhL4*}alRaan0TZ7JLd}EV~F&M z_A`8+ITi+(+5=!_~;PH~XRe#uGq6R=F1jn1eV_8Pf1&m~+mO&d=>VBvG zh$dV|!}`VPmcYHV68m|>A5Dlk-5S^a!L^}==Sb!}sCe;U(omHOXQA1H0J{Rg9EPmy z*}h0v2mxM+qsnU{cC}!fTo}9o4xyYwps}}@oP-4u&X4@Yw1E^01}~DubvdMkFb6z7 zpD!4?!G#9K{{R4e@=*{@FMnJW5<+87cj$ZwNeC|mNd2_qU=mgSb%7WdGqoPh_yuA` zi{GCwtN@A79PJOtG66LrRm>*8^kl8DEj~PY{owkW-*fms7#$LmU4Gslj75S+8#v^= z>66CKyWieI?soI?I(VP zN$-eknuBuk_dhtqRH|IEx<%n)N@+vFtZ2y90b)|zk;7ZbMw*HkLy2iZFL@RAXia)l z0QWud63Mz0Iu~NTrB$wAVVQY?uJ3bN!eVkDAX|s7e8x|LG_CW%&PEt81X3?Wal^(G zT1AA!`PMVCO7m}A{{UEtIiUmGd%!H1t2I}0tBE)*VcsM8Qw0W-xGDZ}NJy4a8z{fW zlOzOzI3O+K@zy*!UcFfzZJj23Sxhe#5lNYu<@Y#2s|K8JreER}{Vp~F>k-x_wY zw<8SM5>JFb>!R+`HosT#ki%C~FXPT23nbYPbG^^$fWj*V(_XlJpxoTrG*lYzCI)8< ze1BL$G85WQaw8D|84eK-i^md(B#L=lZbVpsby~fc4qgMf1ASgVK~wdc{{W-a$-ofY zs0c*{_iz?YOl@+InRQavddfd14i34NSW@%ubP|M^OeN+dCf)02hv5;5fvOf3S55Ry zC;%)40833o-#8v7h~^Rl3Q!qDClgu;(<(@&o#os_bWjH2o9aFtmnlHQuZ}l(xE!lv ztxR)CICvT1dIamqIT!?mOOf__av(}n45N4kFwDR`U3yLRg^AsZ8g%9-kBj^6yf zb9t@n*}m9C9YFxN{{S3@5(cDnb!}rJQ3RbbCnR$HGGLUd*1yqw7*M2?fn<+ z_W?%M!*4t4W~E4MKre?xf8vtG(o!CaWA(r(Hf121@8tK!YOD+1KRcM-G?9!%A_Ih< ze!XVJVqmBuYRp41gc=2-uD&r^OqdY!;zCajOMXfu704s+7&Zcn0n7QsW@%>`P8&_1P?Xq>bWXi15d(Fc%l_i`NsJ0<6vQFT-UOu(go6ZH>E|IBh86-Q;GOu^X^>#1 z-J5j1aqCizQUXKO(SN+;>a&Dv_9q6B5%0z*7w7#u!IZTc`>X;O$Qe}dutNLR9Rd;u z62_Ey+}g(Hr;Y8g76~ z(u4ky=OIL3NL^zSifNL}g@qQF@#hSb??!m!hCCjbO%NoAJ97+s7$lHTOHptVZurOv z$glxY5Fy(Qxe!){iZm=FDXEAzlZs_3D60Z4_lB4d1$FA~u#9huNjoj^?S??GQGtNn zfzZoYj^pD<69$}!ztESDpapYI?SB5WMsxdnCvb;*$cg>)4R@+u+^ zrfUo~PABGZ5Xkb6_mCJ~qY;US0@ZE4O1|(eqL+$P)I}Ty@iqf?2XZYa@p%{>+gxH* z;bw^MwP(=Lu~8%~<7ZqvZkGqGsDt4$2%%G_#+_av!zdx@Mu^$z-qz4WLd%#LQh6Yq zphD%&^nHFY8@sq+v zFi1|Jf11l!z(p7q1nDcs86xZ_<$x6&h<)|@@?-;f)ct?Zq6v>nLHzw;t3grVNlg{} z_PHz(VwA0f_`Tr>2?g3c!xMITWtB@+2Z(8eB|)#DFJU#PyXasE+@LZUJNFLms3VnHSogcNUj_r)g? z%1z3$Z;IAG*%}Qg0U=b%2@AOu6aob<7Cn26Ajw1$Pjh>ZOf;|%7?oiI7JH|}m>r)W zp#lO_f^K3kLI*0DOjJmGD-p`%iW1a?JqZcIt)Wg0F$Arh22@qx?yYqyQO9Qr^cfUC+3GvP|0k-Q0 zXrCl{U`&92dd>ltB#uCJ1P9DVITfzEUA^65U@cc)cuo{sC5TD&%QGU;+~k3Sx;fg8xxx!k3PCzabIS6#d4-jMKv1nMH9m67 zMEC_L`7zKi1ecHs1O6OO%E1%SWZxlj?sL6BU z+RRQMuoXbLVkZ$J5^V$2N9&0}xPTJDy+PV?V5dBj1howWePJUcPGc^@t(8aJa>`U7 zl*l&4zPMW$dJ2ujLgO0S#6D^=km7>@)o||dI0*vLcWr9A#3f>rI9ckz9-cBs21YHg zCy~B1;XC9AMLk)NyQGkF9j?ch+(^`wd2%%cd z@Wl=yp%XmMT{$TY*8)FdBoT5#y<+bNp?m)T%gd3p?xE9zIoQaCpPuo&tR2tOxxF3a zkybp&oNbqntYx*6fscUK_0bF}i)V@Ps{DAz()UXCK>2?2+j)SSpOv2Ph=fUJjy_)> zeugmIW06-|-jBZMo&yS@ufn;HIV&LU6V~FJV{!Q+8E45I{&nbL613G1hi_k;0Yxm* zdet<1y;{7TDE$w=&iO{fBv;8N{{UUsk!pGlHf3%689^n6$5|81iYqrTNx>xEM0^+T z28$ZvEGCon*NhY}Bmk+EeSGY~iJF2ElU$O+y1Y#Q5S^A;3S9N3o>01h4ND8-$5`cc z632X-_tqdB5?IM-g!24kveLwYTLfPk!W85@$EAnS-1_1PMv4~LVy_@#&4=UwoX*V} z=Z@CU!4wW`#f(a1E?7iBwrC2jqN&nEo?=Jhc;^}@0TsZvk4v$d%kqYTf?2NnJOh|`~o@WCzwxFlU5$lV@qHRN5Ea1Xmaz04Gt&2)dqW1ni z*fh4?WbCOM-_9?nHu-dF@o+7SEYlC4`W#%SOw(!|Eo&!|!3PMp$YAjmK$0rRrwnzF zHbj{_lBAW(RTr8~w2^&9M9b+T6sedCpeo>yjZNW1X+kAsHGw8A3zkim$QmITm)@c< zQ~-MlP6MTqlgzOFI7mc+94AFeLQ(`p-qhh41j5tUqgPm1(BZW$Lo;&`x$g2f3@N(0hX81m+7#19+1`#u!tZu=YlXDNYhopYe~nZ9U(w( zq~Q%uKQS0tbC5-Xj18j_8?vyXWJHDnCu{~}mOaH>K{3Kel=g6nIe;R6tZJx=fNrI@ zn1Tsm_EerB6tEqS8!GU|#6%sXixr#nGFW7cttAKB=OrQqkuk?OJ+cQC2%|pf9aaT_ z)}QG$T-4L7vEepo>J&nX@4Rl57$Yx$H;~;bnF&*L4_chl&m=~8v&8&j#rDJ{Kv*W( zr1rrsPXj>!bTP~3GEpE}BnPl-8ReY-=Wkvx7GXe1QR(T70!VKE0P;TYL87=d?%Yc_ zgs4V3h=qw|xo6V^#vm422ge*$;u)F|uyOgo9J48>ics~zspedE)pHoOro=2aA5HIB zRzV_6x4oY+$DD?f1_8Wqp+7hXZtymXU%~$XLLdYe1{e6q0l=;yut|ht1|iKr&|6@U zi@%1BhGd@-O2b4&hZixYrYs{SzdDHJURzc_6P zKq#cs>ybd18A#kLo4;tpAc<`WuUwE2Cuv`Ku4?j&89* zw*0xIn+g&L=NTl~+xx{CMmd*Xc;K)G09H_0k57D>-LQ(!BoEdB@(3gU05H=&$-lfb zkg0SxQ}6eLffTJH?-<-j!0Y21RfLH2`=6XZDH|ivgR*PJMG%lM!0TxTc@H*>ZBIc~ z<*D_-HCj;$+|tz7oSF%2EA~gZ-Wr&TEXTi$MIv2IRuiD{2(*jngz~vKtAm94j~F0L zG=VS1-^Md|Ex<_3kF4W5?CTp{-QF~tYeDfEyqwh~171eiaG4biYiNbPe-+hKfNC;5 zEMLlUpxIS?bH4qs%n(fX=ihE9mM0HG_{b@@ssKFroC~U{5#o^jV0mB$qa0Ov{xL|a z!e3*b{lLP7VQwD=EVTqB3DrI~lAuBoA=3ngY4P^7BuEjF*gm72Y3l$MVit?W!{ICf zH_Opj#{~icQ?i@<-%Mnp4u_^;(h{h||Z%wh2R60-SSt@qunH7D5tPFXp)3O&(Batsi)} zje6rv*m@i3F~-dvX@S5)v~J z?9=3NClDBz$Vdg1m!k;M7KoTXe`^#oAdJW#&+&jvk&^St?|9{8Oaz$sX9W}id-%p; z&tad=HUtLB2`Lda`%lIbL(ykLym*cBcPH#*K)M8(<8eF62b6-&OD|rT3W5S)%6LmEdV63>p}k+2qKkDl20Ceb3>~n z8t99ROcm23@*I_tMA~1k*vk?O%0m{(H{SygGr7wN#2~BrWEr(q5xEeJ@iaYSr9@07 zJSLdP0>lPnBk_JQ8I&PvjYqyJD8^3#qJ@HWaN!pK26cwdLLB^mcxjOXxcAj@8Ed!-1%yxo5c8=faENjmA__*julg(yQVpY#Ksr^p$QxL4 zl}ubrYxu?{1cH8@#_^GenwtLraod}8m(Ga~IAqH~0daG=j=u1KgqJufiw|sc(6Yej zF%VOc8IkL|no6rDJRY>X;)KE78ounDE+J_FgJwzME@N2K(kO(LNEt0K{{R^hEo49t+h3L= z4KdCHq7{`|3$@3A+khS;Ai3yuC zN6meV7;@x2^=de9fbc10_Ywh@eW2Z^?w{n1EOPec?`7f^F`M_&03BH2-ih4q|P z&I;}y>&_sCU#P}N$yrD6dG8d*3X_Hu$~@~Kl)Fq5RIl^rEZtB76Z04Ek`e(91_`2) zJG=3Znp8n^H|YNWo-$J6i9J~ih?~P<;y5BT&lC5Awyue^_0`G0=q4yfn8*YfpumPr z6F=qTCRIK9&-!{i6J`Yfc!M85#sUTOqDRE%mw!$&5+#o>>mwedIc&pUrQ|V6514wL z`t#NyVszlEN}JZ4zW08Wk{e?pEO~>xP8l+Q9~fdziRAp`uc|gHPQ5ZKqE&9HqbZbX zz{*Hi$;7xUDGBGVO>=`H!8( zGK7~Cnl)l31Xtq#6I_8FhUOhwc*N|$N)lOkd_k1@>SOxDYRM~K)=2yIu2gG8rI3WOoP=pZ0I>UrWmn7;s z4Nkeqrg{uSjt-x!5Q8-&BbrIyKb(mX5TzUI1i)mqAio$SM3mj)LPP5my;hCxkP5Z9*>w`y1g$qW>QsdX0 z-Oxs35iM5Uu%vWGh>sF=Ly*K{>%?S>HQfVsQtB&Xn$_9G(FrC{l&JQToZ4n z`@rg$h+`+tv5*SFs{OoW)Dye@nMVHrVt%j-IOM;qS0CHXC|LHzKi&Djek6Yh$4B4F zJ-x6}Nl3b}au;X^$&x%YD2&PR5PIjloI#=lTDLy2>6M8Rim~N9UPGcrn>RH2_gDaG z1!2d6^R!bEiShk1hV%82fe~litN2U+8OpKp3^Yt6WP7|rKOXQ>%3c5g1d5aDuuwuT zA>)C84hgb3lMp=4>mA#kI>Q7c2m?*A<0gwpV`>`z0J!B+5HaG(#GTrgDlRuh1{95m zXCcCAkpBSIBGt!w`@}X1P>AbV@iQ z{pU!ZPxpW`7x(86^ceUa*bS?-U+A(Bv-ZqRkw4OuCdU*@kfK9j);(B5#aa# I0RHd)*<{#ALI3~& literal 0 HcmV?d00001 diff --git a/Documentation/mainboard/dell/optiplex_9010.md b/Documentation/mainboard/dell/optiplex_9010.md new file mode 100644 index 0000000000..f22623d9d7 --- /dev/null +++ b/Documentation/mainboard/dell/optiplex_9010.md @@ -0,0 +1,147 @@ +# Dell OptiPlex 9010 + +This page describes how to run coreboot on Dell OptiPlex 9010 SFF. + +![](optiplex_9010.jpg) + +## Technology + +```eval_rst ++------------+---------------------------------------------------------------+ +| CPU | Intel Core 2nd Gen (Sandybridge) or 3rd Gen (Ivybridge) | ++------------+---------------------------------------------------------------+ +| DRAM | Up to 4 DIMM slots, up to 32GB 1600MHz non-ECC DDR3 SDRAM | ++------------+---------------------------------------------------------------+ +| Chipset | Intel Q77 Express | ++------------+---------------------------------------------------------------+ +| Super I/O | SMSC SCH5545 (or SCH5544) with Environmental Controller | ++------------+---------------------------------------------------------------+ +| TPM | ST Microelectronics ST33ZP24 | ++------------+---------------------------------------------------------------+ +| Boot | From USB, SATA, NVMe (using PCIe x4 expansion card) | ++------------+---------------------------------------------------------------+ +| Power | 200W-275W PSU | ++------------+---------------------------------------------------------------+ +``` + +More specifications on [Dell OptiPlex 9010 specifications]. + +## Required proprietary blobs + +```eval_rst ++------------------+---------------------------------+---------------------+ +| Binary file | Apply | Required / Optional | ++==================+=================================+=====================+ +| smsc_sch5545.bin | SMSC SCH5545 EC | Optional | ++------------------+---------------------------------+---------------------+ +| microcode | CPU microcode | Required | ++------------------+---------------------------------+---------------------+ +``` + +Microcode updates are automatically included into the coreboot image by build +system from the `3rdparty/intel-microcode` submodule. + +SMSC SC5545 EC firmware is optional, however lack of the binary will result in +EC malfunction after power failure and fans running at full speed. The blob can +be extracted from original firmware. It should be located under a file with +GUID D386BEB8-4B54-4E69-94F5-06091F67E0D3, raw section. The file begins with a +signature `SMSCUBIM`. The easiest way to do this is to use [UEFITool] and +`Extract body` option on the raw section of the file. + +## Flashing coreboot + +```eval_rst ++---------------------+--------------------------+ +| Type | Value | ++=====================+==========================+ +| Socketed flash | no | ++---------------------+--------------------------+ +| Model | MX25L6406E/MX25L3206E | ++---------------------+--------------------------+ +| Size | 8 + 4 MiB | ++---------------------+--------------------------+ +| Package | SOIC-16 + SOIC-8 | ++---------------------+--------------------------+ +| Write protection | chipset PRR | ++---------------------+--------------------------+ +| Dual BIOS feature | no | ++---------------------+--------------------------+ +| Internal flashing | yes | ++---------------------+--------------------------+ +``` + +### Internal programming + +The SPI flash can be accessed using [flashrom]. + + flashrom -p internal -w coreboot.rom --ifd -i bios + +Internal programming will not work when migrating from original UEFI firmware. +One will have to short the SERVICE_MODE jumper to enable HMRFPO and then boot +the machine to flash it. + +### External programming + +The external access to flash chip is available through standard SOP-8 clip +and/or SOP-16 clip on the right side of the CPU fan (marked on the board +image). The voltage of SPI flash is 3.3V. + +There are no restrictions as to the programmer device. It is only recommended +to flash firmware without supplying power. There are no diodes connected to the +flash chips. External programming can be performed, for example using OrangePi +and Armbian. You can use linux_spi driver which provides communication with SPI +devices. Example command to program SPI flash with OrangePi using linux_spi: + + flashrom -w coreboot.rom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000 + +## Schematics + +There are no schematics for SFF, but if one looks for MT/DT schematics, they +can be found publicly. Most of the schematics should match the SFF (although +MT/DT has additional PCIe and PCI slot). + +## Known issues + +- There seems to be a problem with DRAM clearing on reboot. The SSKPD register + still contains 0xCAFE which leads to reset loop. + +## Untested + +Not all mainboard's peripherals and functions were tested because of lack of +the cables or not being populated on the board case. + +- Internal USB 2.0 header +- Wake from S3 using serial port +- Wake-on-Lan from ACPI S4/S5 + +## Working + +- USB 3.0 and 2.0 rear and front ports (SeaBIOS and Linux 4.19) +- Gigabit Ethernet +- VGA and 2x DP port using libgfxinit +- flashrom +- PCIe x1 WiFi in PCIe x4 slot +- NVMe PCIe x4 using PCIe x4 expansion card +- PCIe x16 PEG port using Dell Radeon HD 7570 +- SATA ports (SATA disks and DVD) +- Super I/O serial port 0 (RS232 DB9 connector on the rear side) +- SMBus (reading SPD from DIMMs) +- CPU initialization using Intel i7-3770 +- Sandy Bridge/Ivy Bridge native RAM initialization +- SeaBIOS payload (version rel-1.13.0) +- PS/2 keyboard and mouse (including wake support) +- LPC debug header (requires soldering of the pin header and shorting RF24 for + LPC clock) +- USB debug dongle (the most bottom USB 2.0 port under RJ45 on the read side) +- SMSC SCH5545 Super I/O initialization +- SMSC SCH5545 EC initialization and firmware update +- SMSC SCH5545 EC automatic fan control +- TPM 1.2 +- Booting Debian 10, Ubuntu 18.04, QubesOS R4.01 +- Boot with cleaned ME +- Intruder detection +- Wake-on-Lan from ACPI S3 + +[flashrom]: https://flashrom.org/Flashrom +[Dell OptiPlex 9010 specifications]: https://www.dell.com/downloads/global/products/optix/en/dell_optiplex_9010_spec_sheet.pdf +[UEFITool]: https://github.com/LongSoft/UEFITool diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 33c60a4c97..b9fc68d052 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -26,6 +26,10 @@ This section contains documentation about coreboot on specific mainboards. - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md) +## Dell + +- [OptiPlex 9010 SFF](dell/optiplex_9010.md) + ## Emulation The boards in this section are not real mainboards, but emulators. diff --git a/configs/config.dell_optiplex_9010_sff b/configs/config.dell_optiplex_9010_sff new file mode 100644 index 0000000000..e25653e148 --- /dev/null +++ b/configs/config.dell_optiplex_9010_sff @@ -0,0 +1,9 @@ +CONFIG_USE_OPTION_TABLE=y +CONFIG_USE_BLOBS=y +CONFIG_VENDOR_DELL=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_PCIEXP_CLK_PM=y +CONFIG_SEABIOS_PS2_TIMEOUT=3000 +CONFIG_POST_DEVICE_LPC=y +CONFIG_HAVE_EM100_SUPPORT=y diff --git a/src/mainboard/dell/Kconfig b/src/mainboard/dell/Kconfig new file mode 100644 index 0000000000..298c62b52b --- /dev/null +++ b/src/mainboard/dell/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_DELL + +choice + prompt "Mainboard model" + +source "src/mainboard/dell/*/Kconfig.name" + +endchoice + +source "src/mainboard/dell/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Dell Inc." + +endif # VENDOR_DELL diff --git a/src/mainboard/dell/Kconfig.name b/src/mainboard/dell/Kconfig.name new file mode 100644 index 0000000000..3d2fefd11d --- /dev/null +++ b/src/mainboard/dell/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_DELL + bool "Dell Inc." diff --git a/src/mainboard/dell/optiplex_9010/Kconfig b/src/mainboard/dell/optiplex_9010/Kconfig new file mode 100644 index 0000000000..6a3feb3751 --- /dev/null +++ b/src/mainboard/dell/optiplex_9010/Kconfig @@ -0,0 +1,69 @@ +if BOARD_DELL_OPTIPLEX_9010 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_12288 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select MAINBOARD_USES_IFD_GBE_REGION + select SUPERIO_SMSC_SCH5545 + select MAINBOARD_HAS_LIBGFXINIT + select INTEL_GMA_HAVE_VBT + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select PCIEXP_L1_SUB_STATE + +config MAINBOARD_DIR + string + default dell/optiplex_9010 + +config MAINBOARD_PART_NUMBER + string + default "OptiPlex 9010" + +config VGA_BIOS_FILE + string + default "pci8086,0162.rom" + +config VGA_BIOS_ID + string + default "8086,0162" + +config DRAM_RESET_GATE_GPIO + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config CBFS_SIZE + hex + default 0x600000 + +config INCLUDE_SMSC_SCH5545_EC_FW + bool "Include SMSC SCH5545 EC firmware binary" + default n + help + This option allows to add the SMSC SCH5545 Environmental Controller + firmware binary. The firmware must be loaded after each power failure + in order to properly initialize the fan control, because EC loses its + configuration when power is cut off. Otherwise the fans will keep + running at full speed after power failure. + +config SMSC_SCH5545_EC_FW_FILE + string "File path to the SMSC SCH5545 EC firmware binary" + depends on INCLUDE_SMSC_SCH5545_EC_FW + +endif diff --git a/src/mainboard/dell/optiplex_9010/Kconfig.name b/src/mainboard/dell/optiplex_9010/Kconfig.name new file mode 100644 index 0000000000..96707c2890 --- /dev/null +++ b/src/mainboard/dell/optiplex_9010/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_DELL_OPTIPLEX_9010 + bool "OptiPlex 9010 SFF" diff --git a/src/mainboard/dell/optiplex_9010/Makefile.inc b/src/mainboard/dell/optiplex_9010/Makefile.inc new file mode 100644 index 0000000000..7a8a68423a --- /dev/null +++ b/src/mainboard/dell/optiplex_9010/Makefile.inc @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-only + +smm-y += smihandler.c + +bootblock-y += gpio.c +romstage-y += gpio.c + +bootblock-y += early_init.c +romstage-y += early_init.c + +bootblock-y += sch5545_ec_early.c + +romstage-y += sch5545_ec.c + +ramstage-y += sch5545_ec.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +ifeq ($(CONFIG_INCLUDE_SMSC_SCH5545_EC_FW),y) +cbfs-files-y += sch5545_ecfw.bin +sch5545_ecfw.bin-file := $(call strip_quotes,$(CONFIG_SMSC_SCH5545_EC_FW_FILE)) +sch5545_ecfw.bin-type := raw +endif diff --git a/src/mainboard/dell/optiplex_9010/acpi/ec.asl b/src/mainboard/dell/optiplex_9010/acpi/ec.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/dell/optiplex_9010/acpi/platform.asl b/src/mainboard/dell/optiplex_9010/acpi/platform.asl new file mode 100644 index 0000000000..f890b5af54 --- /dev/null +++ b/src/mainboard/dell/optiplex_9010/acpi/platform.asl @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK,1) +{ + \_SB.PCI0.LPCB.SIO1.SIOW (Arg0) + + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.SIO1.SIOS (Arg0) +} + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (_UID, 0xAA) + Name (_STA, 0x0B) + + Name (_PRW, Package() { 8, 3}) + } +} + +Scope (\_GPE) +{ + Method (_L08, 0, NotSerialized) + { + \_SB.PCI0.LPCB.SIO1.SIOH () + Notify (\_SB.PWRB, 0x02) + } + + Method (_L0D, 0, NotSerialized) + { + Notify (\_SB.PCI0.EHC1, 0x02) + Notify (\_SB.PCI0.EHC2, 0x02) + Notify (\_SB.PCI0.GLAN, 0x02) + } + + Method (_L09, 0, NotSerialized) + { + Notify (\_SB.PCI0.RP01, 0x02) + Notify (\_SB.PCI0.RP02, 0x02) + Notify (\_SB.PCI0.RP03, 0x02) + Notify (\_SB.PCI0.RP04, 0x02) + Notify (\_SB.PCI0.RP05, 0x02) + Notify (\_SB.PCI0.RP06, 0x02) + Notify (\_SB.PCI0.RP07, 0x02) + Notify (\_SB.PCI0.RP08, 0x02) + Notify (\_SB.PCI0.PEGP, 0x02) + } +} diff --git a/src/mainboard/dell/optiplex_9010/acpi/superio.asl b/src/mainboard/dell/optiplex_9010/acpi/superio.asl new file mode 100644 index 0000000000..fa1dfcf726 --- /dev/null +++ b/src/mainboard/dell/optiplex_9010/acpi/superio.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#define SUPERIO_DEV SIO1 +#define SUPERIO_PNP_BASE 0x2e + +#define SCH5545_RUNTIME_BASE 0xa00 +#define SCH5545_EMI_BASE 0xa40 +#define SCH5545_SHOW_UARTA +#define SCH5545_SHOW_KBC + +#include diff --git a/src/mainboard/dell/optiplex_9010/acpi_tables.c b/src/mainboard/dell/optiplex_9010/acpi_tables.c new file mode 100644 index 0000000000..33feed2a98 --- /dev/null +++ b/src/mainboard/dell/optiplex_9010/acpi_tables.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/dell/optiplex_9010/board_info.txt b/src/mainboard/dell/optiplex_9010/board_info.txt new file mode 100644 index 0000000000..f49f3ba416 --- /dev/null +++ b/src/mainboard/dell/optiplex_9010/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +ROM protocol: SPI +ROM package: SOIC-8, SOIC-16 +ROM socketed: n +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/dell/optiplex_9010/cmos.default b/src/mainboard/dell/optiplex_9010/cmos.default new file mode 100644 index 0000000000..ccc7e64625 --- /dev/null +++ b/src/mainboard/dell/optiplex_9010/cmos.default @@ -0,0 +1,7 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +sata_mode=AHCI +gfx_uma_size=128M +fan_full_speed=Disable diff --git a/src/mainboard/dell/optiplex_9010/cmos.layout b/src/mainboard/dell/optiplex_9010/cmos.layout new file mode 100644 index 0000000000..dcf9639d3f --- /dev/null +++ b/src/mainboard/dell/optiplex_9010/cmos.layout @@ -0,0 +1,95 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 1 e 8 sata_mode + +# coreboot config options: EC +412 1 e 1 fan_full_speed + +# coreboot config options: northbridge +432 3 e 9 gfx_uma_size + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 AHCI +8 1 Compatible +9 0 32M +9 1 64M +9 2 96M +9 3 128M +9 4 160M +9 5 192M +9 6 224M + + +# ----------------------------------------------------------------- +checksums + +checksum 392 447 984 diff --git a/src/mainboard/dell/optiplex_9010/data.vbt b/src/mainboard/dell/optiplex_9010/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..d1a95e86329ad61642591a87cdd8ee551061713c GIT binary patch literal 4281 zcmdT{Z){uD75`noXZz*(J==N7ij%g{p?^ZsHqEo^dR>-j&woe0JPo|G&ieuS(=p}5yh3FSofLS3rO`EB3dZ9AcH{MSZGpA=CKT$n3`%q=D@TjLz zDO;fQgAZ2bD%F{V$}CMx-JK>0YwDSEr{-p9^xVTID%By9SnN&lOdEm`G1dj2z7r@1xTASiX=cOpfGC-Caud z%>3ikQxBb7puTKBCHMmaE}%PQ%ATpt@2B+K9F0q#vou~gTd6);ncZ*d65uj4RRF?| z$deG_p9!=9hKjs{K7wB$4crOj023JDhyVqkA1DI5fPFv|K2!KqcGK|YV_tMgN=8zo z^w}UOq2j%1M5AgzZy17rU)qCFK|(4H-fX7b|RTNG&JmFa)Ggc)@OzY5s+I1odfxjPtxrAM(_*I+Y$oq4;aVMeoXmidRw z&oTd8)A1VfW#&IHzt8+<=D#xkjXBt+qn&vx^KRxr=C3hlnU6Ami+P6myUgd97nz@8 z{webd%z<Oh`zfrGqvkyWYX)uWs(JHnOSQh|sjJ$^YKL=s=ba7lnq;tEdHE zRfmOA|Bl8I;IPg^9EckDs8=I; zzYOB`zu9sRuUT_V!67PI%@ z;xX8cJ>Su=^t?Ry*y^$FUZ;GqX~}=nu}{33aGc9cORNv6MWqpMBem$4`_H#^YEdk^ z^~PENoDFR2>O&VkzyF0M*CnaFAvS62^=&D<*H&Am)$LJjdPl>xrxnZgBv+9TZJN)o8f%~6LTZ|B zuJ*JevX&~|u)Y{82i7pISNflYVuUCWvT`APG(-y_>wHLG4$*5NYbB(=6QX~FEZxvM z4H`16qM=V2^gY9R#?UVs^jpJv+t5EW2&QG3`Zkj?rZs8m-!^HslmrQ!ov_3HP zk4)0SR(Dw66{aI$>w&QToiIHewq6YDFNf)^u(cZ2uY@TYv35lCeGzldRkh|@6}5Iw zbxtU)YVfv~eTFMP6;YP{$X$GmZHy%6pqH1Vlzq2GxD+A8%iE~0*4YS5PioNznTaqs zg_T<)Y%D5S8;v^PpOvaa7~XUh8;elZRHJ^T{Eazmj$mz_I$45c6CK3vm-zVYwm<&F zT?9H?MmSu;PP=zY3I~575dyy)?vh~;9jzhsZk=L;UYlY`lz-Pi_++O-|oe|Hr(#38k)F7wsFyV=?*IFh%F!{#};As;xS6ol5z;Xgre zPXVK~NZx!7{Le{dwVztpi!0r@RH8d`^Embo4op%y&kX7%Q)@D0^sj~p6s z$^+hI%l3j#?Li^MdEl;-$CFEq>tCX)4}L`5Ys}liW$) zJLdM{2e0pZwduAOD9tQX&v>Ka@g$WGk9(u?xwxE3gYr4~+ufslZZEC9TQ`F*@9cd9 sfzcKIPw>jd_Q(qK@+)5Z7v-AXwDYKSKCXQuPW=Yj_Z9r4Ip=lqUoXj?9{>OV literal 0 HcmV?d00001 diff --git a/src/mainboard/dell/optiplex_9010/devicetree.cb b/src/mainboard/dell/optiplex_9010/devicetree.cb new file mode 100644 index 0000000000..6a21d20b74 --- /dev/null +++ b/src/mainboard/dell/optiplex_9010/devicetree.cb @@ -0,0 +1,99 @@ +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + register "tcc_offset" = "5" # TCC of 95C + device lapic 0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + subsystemid 0x1028 0x052c inherit + + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 on # PEG1 (blue slot1) + smbios_slot_desc "0xB6" "4" "SLOT1" "0x0D" + end + device pci 02.0 on end # Internal graphics VGA controller + device pci 06.0 off end # PEG2 + + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "gpe0_en" = "0x00000146" + register "alt_gp_smi_en" = "0x0004" + register "gpi2_routing" = "1" + register "gpi12_routing" = "2" + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x007c0a01" + register "gen2_dec" = "0x007c0901" + register "gen3_dec" = "0x003c07e1" + register "gen4_dec" = "0x001c0901" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x7" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x08040201" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on end # USB 3.0 Controller + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio controller + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on # PCIe Port #5 + smbios_slot_desc "0xB6" "4" "SLOT2" "0x0A" + end + device pci 1c.5 on end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7 + device pci 1c.7 on end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip superio/smsc/sch5545 + device pnp 2e.c on # LPC + io 0x60 = 0x2e + end + device pnp 2e.0 on # EMI + io 0x60 = 0xa40 + end + device pnp 2e.1 on # KBC/PS2M + io 0x60 = 0x60 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.7 on # UART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + irq 0xf0 = 0x02 + end + device pnp 2e.8 off end # UART2 + device pnp 2e.a on # Runtime registers + io 0x60 = 0xa00 + irq 0x70 = 9 # PME + end + device pnp 2e.b off end # Floppy + device pnp 2e.11 off end # PP + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 on end # Thermal + end + end +end diff --git a/src/mainboard/dell/optiplex_9010/dsdt.asl b/src/mainboard/dell/optiplex_9010/dsdt.asl new file mode 100644 index 0000000000..6a6dcb4c36 --- /dev/null +++ b/src/mainboard/dell/optiplex_9010/dsdt.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include + #include + #include + #include + + Scope (\_SB) + { + Device (PCI0) + { + #include + #include + Device (GLAN) + { + Name (_ADR, 0x00190000) + Name (_PRW, Package() { 13, 4 }) + } + } + } +} diff --git a/src/mainboard/dell/optiplex_9010/early_init.c b/src/mainboard/dell/optiplex_9010/early_init.c new file mode 100644 index 0000000000..5469c94f15 --- /dev/null +++ b/src/mainboard/dell/optiplex_9010/early_init.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +#include "sch5545_ec.h" + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 6, 0 }, + { 1, 6, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 1, 1, 2 }, + { 1, 6, 3 }, + { 1, 6, 3 }, + { 1, 6, 4 }, + { 1, 6, 4 }, + { 1, 6, 5 }, + { 1, 1, 5 }, + { 1, 1, 6 }, + { 1, 6, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + /* + * FIXME: the board gets stuck in reset loop in + * mainboard_romstage_entry. Avoid that by clearing SSKPD + */ + pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + (uintptr_t)DEFAULT_MCHBAR) >> 32); + MCHBAR16(SSKPD_HI) = 0; + + sch5545_early_init(0x2e); + /* Bare EC and SIO GPIO initialization which allows to enable serial port */ + sch5545_emi_init(0x2e); + sch5545_emi_disable_interrupts(); + sch5545_ec_early_init(); + + if (CONFIG(CONSOLE_SERIAL)) + sch5545_enable_uart(0x2e, 0); +} diff --git a/src/mainboard/dell/optiplex_9010/gma-mainboard.ads b/src/mainboard/dell/optiplex_9010/gma-mainboard.ads new file mode 100644 index 0000000000..74b50645e6 --- /dev/null +++ b/src/mainboard/dell/optiplex_9010/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + HDMI1, + HDMI2, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/dell/optiplex_9010/gpio.c b/src/mainboard/dell/optiplex_9010/gpio.c new file mode 100644 index 0000000000..d01e6221a6 --- /dev/null +++ b/src/mainboard/dell/optiplex_9010/gpio.c @@ -0,0 +1,208 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NATIVE, + .gpio1 = GPIO_MODE_GPIO, /* CHASSIS_ID0 */ + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, /* VGA_CBL_DET# */ + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, /* PCH_HS_DET# (unused?) */ + .gpio7 = GPIO_MODE_GPIO, /* SKU2 */ + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, /* PCIE_X4_WAKE*/ + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, /* PCIE_X1_WAKE (MT/DT only)*/ + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, /* CHASSIS_ID1 */ + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_GPIO, /* FLEXBAY_HDR_CBL_DET# */ + .gpio21 = GPIO_MODE_GPIO, /* BOARD_REV0 */ + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, /* Password Clear Jumper */ +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_OUTPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio2 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, /* SKU0 */ + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, /* SKU1 */ + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, /* CHASSIS_ID2 */ + .gpio39 = GPIO_MODE_GPIO, /* FP_PRESENCE# */ + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, /* INTRUD_CBL_DET# */ + .gpio45 = GPIO_MODE_GPIO, /* COM_SER2_DET# (unused?) */ + .gpio46 = GPIO_MODE_GPIO, /* BOARD_REV1 */ + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, /* BOARD_REV2 */ + .gpio69 = GPIO_MODE_GPIO, /* USB_HDR_DET# */ + .gpio70 = GPIO_MODE_GPIO, /* FP_CHAS_DET# */ + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, /* ME_MFG_MODE */ + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { + .gpio74 = GPIO_RESET_RSMRST, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/optiplex_9010/hda_verb.c b/src/mainboard/dell/optiplex_9010/hda_verb.c new file mode 100644 index 0000000000..eab4ba9053 --- /dev/null +++ b/src/mainboard/dell/optiplex_9010/hda_verb.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ + 0x1028052c, /* Subsystem ID */ + + 11, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(0, 0x1028052c), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x99130110), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x02a19830), + AZALIA_PIN_CFG(0, 0x19, 0x01a19840), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x01014020), + AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x0221402f), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 4, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x58560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/optiplex_9010/mainboard.c b/src/mainboard/dell/optiplex_9010/mainboard.c new file mode 100644 index 0000000000..4490c14a0d --- /dev/null +++ b/src/mainboard/dell/optiplex_9010/mainboard.c @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sch5545_ec.h" + +#define SIO_PORT 0x2e + +#define GPIO_CHASSIS_ID0 1 +#define GPIO_VGA_CABLE_DET_L 4 +#define GPIO_SKU2 7 +#define GPIO_CHASSIS_ID1 17 +/* Internal USB header on mainboard */ +#define FLEXBAY_HEADER_CABLE_DET_L 20 +#define GPIO_BOARD_REV0 21 +/* Password clear jumper */ +#define GPIO_PSWD_CLR 31 +#define GPIO_SKU0 32 +#define GPIO_SKU1 35 +#define GPIO_CHASSIS_ID2 37 +/* Front panel presence */ +#define GPIO_FRONT_PANEL_PRESENT_L 39 +#define GPIO_INTRUDER_CABLE_DET_L 44 +#define GPIO_BOARD_REV1 46 +#define GPIO_BOARD_REV2 68 +/* Front USB 3.0 ports */ +#define GPIO_USB_HEADER_DET_L 69 +/* Differentiate between MT/DT on the Medium Tower and Desktop variants */ +#define GPIO_FRONT_PANEL_CHASSIS_DET_L 70 +/* + * This GPIO is connected to the transistor gate. If high, it will pull the + * HDA_SDO high. When strapped at PCH_PWROK it will enable the Flash Descriptor + * Security Override and disable ME after chipset bringup. Alternative method + * is to use the service jumper on the mainboard. + */ +#define GPIO_ME_MFG_MODE 74 + +/* These GPIOs are on SCH5545 */ + +/* Detect if the power switch cable is connected */ +#define SIO_GPIO_FP_CBL_DET_L 25 +/* Detect internal speaker connected to front cover */ +#define SIO_GPIO_PCSPKR_DET_L 31 + +static void mainboard_enable(struct device *dev) +{ + int pin_sts; + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); + + pin_sts = get_gpio(GPIO_CHASSIS_ID0); + pin_sts |= get_gpio(GPIO_CHASSIS_ID1) << 1; + pin_sts |= get_gpio(GPIO_CHASSIS_ID2) << 2; + pin_sts |= get_gpio(GPIO_FRONT_PANEL_CHASSIS_DET_L) << 3; + + printk(BIOS_DEBUG, "Chassis type:"); + switch (pin_sts) { + case 0: + printk(BIOS_DEBUG, "MT\n"); + break; + case 3: + case 11: + printk(BIOS_DEBUG, "USFF\n"); + break; + case 4: + /* As per table in schematics, but don't know what this is */ + printk(BIOS_DEBUG, "Comoros\n"); + break; + case 1: + case 9: + case 5: + case 13: + printk(BIOS_DEBUG, "SFF\n"); + break; + case 8: + printk(BIOS_DEBUG, "DT\n"); + break; + default: + printk(BIOS_DEBUG, "Unknown chassis type %u\n", pin_sts); + break; + } + + pin_sts = get_gpio(GPIO_BOARD_REV0); + pin_sts |= get_gpio(GPIO_BOARD_REV1) << 1; + pin_sts |= get_gpio(GPIO_BOARD_REV2) << 2; + + printk(BIOS_DEBUG, "Board revision: %d\n", pin_sts); + + pin_sts = get_gpio(GPIO_SKU0); + pin_sts |= get_gpio(GPIO_SKU1) << 1; + pin_sts |= get_gpio(GPIO_SKU2) << 2; + + printk(BIOS_DEBUG, "SKU ID is %d:", pin_sts); + switch (pin_sts) { + case 0: + printk(BIOS_DEBUG, "TPM\n"); + break; + case 1: + printk(BIOS_DEBUG, "TCM\n"); + break; + case 2: + printk(BIOS_DEBUG, "Non TPM/TCM\n"); + break; + default: + printk(BIOS_DEBUG, "Unknown/reserved\n"); + break; + } + + printk(BIOS_DEBUG, "VGA cable %sconnected\n", + get_gpio(GPIO_VGA_CABLE_DET_L) ? "dis" : ""); + + printk(BIOS_DEBUG, "Flexbay %sattached to internal USB 2.0 header\n", + get_gpio(FLEXBAY_HEADER_CABLE_DET_L) ? "not " : ""); + + printk(BIOS_DEBUG, "Password clear jumper %sactive\n", + get_gpio(GPIO_PSWD_CLR) ? "in" : ""); + + if (!get_gpio(GPIO_FRONT_PANEL_PRESENT_L)) { + printk(BIOS_DEBUG, "Front panel cable connected\n"); + } else { + printk(BIOS_WARNING, "Front panel cable not connected!\n"); + printk(BIOS_WARNING, "Front USB 2.0 ports, SATA LED, microphone" + " and speaker jacks will not work!\n"); + printk(BIOS_WARNING, "Check the front panel cable!\n"); + } + + if (!get_gpio(GPIO_INTRUDER_CABLE_DET_L)) { + printk(BIOS_DEBUG, "Intruder cable connected\n"); + } else { + printk(BIOS_WARNING, "Intruder cable not connected!\n"); + printk(BIOS_WARNING, "Intrusion detection will not work!\n"); + printk(BIOS_WARNING, "Check the intruder cable!\n"); + } + + if (!get_gpio(GPIO_USB_HEADER_DET_L)) { + printk(BIOS_DEBUG, "Front USB 3.0 cable connected\n"); + } else { + printk(BIOS_WARNING, "Front USB 3.0 cable not connected!\n"); + printk(BIOS_WARNING, "Front USB 3.0 ports will not work!\n"); + printk(BIOS_WARNING, "Check the front USB 3.0 cable!\n"); + } +} + +static void mainboard_final(void *chip_info) +{ + int pin_sts; + struct device *dev = pcidev_on_root(0x1f, 0); + const u8 pirq_routing = 11; + + pci_write_config8(dev, PIRQA_ROUT, pirq_routing); + pci_write_config8(dev, PIRQB_ROUT, pirq_routing); + pci_write_config8(dev, PIRQC_ROUT, pirq_routing); + pci_write_config8(dev, PIRQD_ROUT, pirq_routing); + + pci_write_config8(dev, PIRQE_ROUT, pirq_routing); + pci_write_config8(dev, PIRQF_ROUT, pirq_routing); + pci_write_config8(dev, PIRQG_ROUT, pirq_routing); + pci_write_config8(dev, PIRQH_ROUT, pirq_routing); + + pin_sts = sch5545_get_gpio(SIO_PORT, SIO_GPIO_FP_CBL_DET_L); + + if (pin_sts != -1) { + if (pin_sts) { + printk(BIOS_WARNING, "Power switch cable not connected!\n"); + printk(BIOS_WARNING, "Check power switch cable!\n"); + } else { + printk(BIOS_DEBUG, "Power switch cable connected\n"); + } + } + + pin_sts = sch5545_get_gpio(SIO_PORT, SIO_GPIO_PCSPKR_DET_L); + + if (pin_sts != -1) + printk(BIOS_DEBUG, "Internal chassis PC speaker %sconnected\n", + pin_sts ? "not " : ""); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .final = mainboard_final, +}; + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5545_ec_hwm_init, NULL); diff --git a/src/mainboard/dell/optiplex_9010/romstage.c b/src/mainboard/dell/optiplex_9010/romstage.c new file mode 100644 index 0000000000..36af6e49c0 --- /dev/null +++ b/src/mainboard/dell/optiplex_9010/romstage.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sch5545_ec.h" + +void mainboard_early_init(int s3resume) +{ + uint16_t ec_fw_version; + + /* + * We do EC initialization in romstage, because it makes no sense to + * bloat the bootblock any more. Secondly, the EC expects to receive + * correct initialization sequence from the host in the time window of + * about 3-5 seconds since system reset. If it doesn't receive the + * initialization sequence, it enters an error path which results in + * fans spinned up to high speed. In this state EC doesn't respond to + * further messages sent over EMI. The issue appears after power + * failure, where EC loses its configuration. For this particular + * reasons we do the initialization in romstage instead of ramstage. + */ + sch5545_emi_init(0x2e); + if (sch5545_emi_get_int_mask_high()) + printk(BIOS_SPEW, "EC interrupt mask MSB is not 0\n"); + + sch5545_ec_hwm_early_init(); + + if (!s3resume) { + ec_fw_version = sch5545_get_ec_fw_version(); + printk(BIOS_DEBUG, "SCH5545 EC firmware version %04x\n", ec_fw_version); + sch5545_update_ec_firmware(ec_fw_version); + } + printk(BIOS_DEBUG, "EC early init complete.\n"); + + /* Disable SMIs and clear SMI status */ + outb(0, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_SMI_EN); + outb(SCH5545_SMI_GLOBAL_STS, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_SMI_STS); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/dell/optiplex_9010/sch5545_ec.c b/src/mainboard/dell/optiplex_9010/sch5545_ec.c new file mode 100644 index 0000000000..401345254d --- /dev/null +++ b/src/mainboard/dell/optiplex_9010/sch5545_ec.c @@ -0,0 +1,726 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sch5545_ec.h" + +#define GPIO_CHASSIS_ID0 1 +#define GPIO_CHASSIS_ID1 17 +#define GPIO_CHASSIS_ID2 37 +#define GPIO_FRONT_PANEL_CHASSIS_DET_L 70 + +enum { + TDP_16 = 0x10, + TDP_32 = 0x20, + TDP_COMMON = 0xff, +}; + +typedef struct ec_val_reg_tdp { + uint8_t val; + uint16_t reg; + uint8_t tdp; +} ec_chassis_tdp_t; + +static const struct ec_val_reg ec_hwm_init_seq[] = { + { 0xa0, 0x02fc }, + { 0x32, 0x02fd }, + { 0x77, 0x0005 }, + { 0x0f, 0x0018 }, + { 0x2f, 0x0019 }, + { 0x2f, 0x001a }, + { 0x33, 0x008a }, + { 0x33, 0x008b }, + { 0x33, 0x008c }, + { 0x10, 0x00ba }, + { 0xff, 0x00d1 }, + { 0xff, 0x00d6 }, + { 0xff, 0x00db }, + { 0x00, 0x0048 }, + { 0x00, 0x0049 }, + { 0x00, 0x007a }, + { 0x00, 0x007b }, + { 0x00, 0x007c }, + { 0x00, 0x0080 }, + { 0x00, 0x0081 }, + { 0x00, 0x0082 }, + { 0xbb, 0x0083 }, + { 0xb0, 0x0084 }, + { 0x88, 0x01a1 }, + { 0x80, 0x01a4 }, + { 0x00, 0x0088 }, + { 0x00, 0x0089 }, + { 0x02, 0x00a0 }, + { 0x02, 0x00a1 }, + { 0x02, 0x00a2 }, + { 0x04, 0x00a4 }, + { 0x04, 0x00a5 }, + { 0x04, 0x00a6 }, + { 0x00, 0x00ab }, + { 0x3f, 0x00ad }, + { 0x07, 0x00b7 }, + { 0x50, 0x0062 }, + { 0x46, 0x0063 }, + { 0x50, 0x0064 }, + { 0x46, 0x0065 }, + { 0x50, 0x0066 }, + { 0x46, 0x0067 }, + { 0x98, 0x0057 }, + { 0x98, 0x0059 }, + { 0x7c, 0x0061 }, + { 0x00, 0x01bc }, + { 0x00, 0x01bd }, + { 0x00, 0x01bb }, + { 0xdd, 0x0085 }, + { 0xdd, 0x0086 }, + { 0x07, 0x0087 }, + { 0x5e, 0x0090 }, + { 0x5e, 0x0091 }, + { 0x5d, 0x0095 }, + { 0x00, 0x0096 }, + { 0x00, 0x0097 }, + { 0x00, 0x009b }, + { 0x86, 0x00ae }, + { 0x86, 0x00af }, + { 0x67, 0x00b3 }, + { 0xff, 0x00c4 }, + { 0xff, 0x00c5 }, + { 0xff, 0x00c9 }, + { 0x01, 0x0040 }, + { 0x00, 0x02fc }, + { 0x9a, 0x02b3 }, + { 0x05, 0x02b4 }, + { 0x01, 0x02cc }, + { 0x4c, 0x02d0 }, + { 0x01, 0x02d2 }, + { 0x01, 0x006f }, + { 0x02, 0x0070 }, + { 0x03, 0x0071 }, +}; + + +static const ec_chassis_tdp_t ec_hwm_chassis3[] = { + { 0x33, 0x0005, TDP_COMMON }, + { 0x2f, 0x0018, TDP_COMMON }, + { 0x2f, 0x0019, TDP_COMMON }, + { 0x2f, 0x001a, TDP_COMMON }, + { 0x00, 0x0080, TDP_COMMON }, + { 0x00, 0x0081, TDP_COMMON }, + { 0xbb, 0x0083, TDP_COMMON }, + { 0x8a, 0x0085, TDP_16 }, + { 0x2c, 0x0086, TDP_16 }, + { 0x66, 0x008a, TDP_16 }, + { 0x5b, 0x008b, TDP_16 }, + { 0x65, 0x0090, TDP_COMMON }, + { 0x70, 0x0091, TDP_COMMON }, + { 0x86, 0x0092, TDP_COMMON }, + { 0xa4, 0x0096, TDP_COMMON }, + { 0xa4, 0x0097, TDP_COMMON }, + { 0xa4, 0x0098, TDP_COMMON }, + { 0xa4, 0x009b, TDP_COMMON }, + { 0x0e, 0x00a0, TDP_COMMON }, + { 0x0e, 0x00a1, TDP_COMMON }, + { 0x7c, 0x00ae, TDP_COMMON }, + { 0x86, 0x00af, TDP_COMMON }, + { 0x95, 0x00b0, TDP_COMMON }, + { 0x9a, 0x00b3, TDP_COMMON }, + { 0x08, 0x00b6, TDP_COMMON }, + { 0x08, 0x00b7, TDP_COMMON }, + { 0x64, 0x00ea, TDP_COMMON }, + { 0xff, 0x00ef, TDP_COMMON }, + { 0x15, 0x00f8, TDP_COMMON }, + { 0x00, 0x00f9, TDP_COMMON }, + { 0x30, 0x00f0, TDP_COMMON }, + { 0x01, 0x00fd, TDP_COMMON }, + { 0x88, 0x01a1, TDP_COMMON }, + { 0x08, 0x01a2, TDP_COMMON }, + { 0x08, 0x01b1, TDP_COMMON }, + { 0x94, 0x01be, TDP_COMMON }, + { 0x94, 0x0280, TDP_16 }, + { 0x11, 0x0281, TDP_16 }, + { 0x03, 0x0282, TDP_COMMON }, + { 0x0a, 0x0283, TDP_COMMON }, + { 0x80, 0x0284, TDP_COMMON }, + { 0x03, 0x0285, TDP_COMMON }, + { 0x68, 0x0288, TDP_16 }, + { 0x10, 0x0289, TDP_16 }, + { 0x03, 0x028a, TDP_COMMON }, + { 0x0a, 0x028b, TDP_COMMON }, + { 0x80, 0x028c, TDP_COMMON }, + { 0x03, 0x028d, TDP_COMMON }, +}; + +static const ec_chassis_tdp_t ec_hwm_chassis4[] = { + { 0x33, 0x0005, TDP_COMMON }, + { 0x2f, 0x0018, TDP_COMMON }, + { 0x2f, 0x0019, TDP_COMMON }, + { 0x2f, 0x001a, TDP_COMMON }, + { 0x00, 0x0080, TDP_COMMON }, + { 0x00, 0x0081, TDP_COMMON }, + { 0xbb, 0x0083, TDP_COMMON }, + { 0x99, 0x0085, TDP_32 }, + { 0x98, 0x0085, TDP_16 }, + { 0xbc, 0x0086, TDP_32 }, + { 0x1c, 0x0086, TDP_16 }, + { 0x39, 0x008a, TDP_32 }, + { 0x3d, 0x008a, TDP_16 }, + { 0x40, 0x008b, TDP_32 }, + { 0x43, 0x008b, TDP_16 }, + { 0x68, 0x0090, TDP_COMMON }, + { 0x5e, 0x0091, TDP_COMMON }, + { 0x86, 0x0092, TDP_COMMON }, + { 0xa4, 0x0096, TDP_COMMON }, + { 0xa4, 0x0097, TDP_COMMON }, + { 0xa4, 0x0098, TDP_COMMON }, + { 0xa4, 0x009b, TDP_COMMON }, + { 0x0c, 0x00a0, TDP_COMMON }, + { 0x0c, 0x00a1, TDP_COMMON }, + { 0x72, 0x00ae, TDP_COMMON }, + { 0x7c, 0x00af, TDP_COMMON }, + { 0x9a, 0x00b0, TDP_COMMON }, + { 0x7c, 0x00b3, TDP_COMMON }, + { 0x08, 0x00b6, TDP_COMMON }, + { 0x08, 0x00b7, TDP_COMMON }, + { 0x64, 0x00ea, TDP_COMMON }, + { 0xff, 0x00ef, TDP_COMMON }, + { 0x15, 0x00f8, TDP_COMMON }, + { 0x00, 0x00f9, TDP_COMMON }, + { 0x30, 0x00f0, TDP_COMMON }, + { 0x01, 0x00fd, TDP_COMMON }, + { 0x88, 0x01a1, TDP_COMMON }, + { 0x08, 0x01a2, TDP_COMMON }, + { 0x08, 0x01b1, TDP_COMMON }, + { 0x90, 0x01be, TDP_COMMON }, + { 0x94, 0x0280, TDP_32 }, + { 0x11, 0x0281, TDP_32 }, + { 0x68, 0x0280, TDP_16 }, + { 0x10, 0x0281, TDP_16 }, + { 0x03, 0x0282, TDP_COMMON }, + { 0x0a, 0x0283, TDP_COMMON }, + { 0x80, 0x0284, TDP_COMMON }, + { 0x03, 0x0285, TDP_COMMON }, + { 0xa0, 0x0288, TDP_32 }, + { 0x0f, 0x0289, TDP_32 }, + { 0xd8, 0x0288, TDP_16 }, + { 0x0e, 0x0289, TDP_16 }, + { 0x03, 0x028a, TDP_COMMON }, + { 0x0a, 0x028b, TDP_COMMON }, + { 0x80, 0x028c, TDP_COMMON }, + { 0x03, 0x028d, TDP_COMMON }, +}; + +static const ec_chassis_tdp_t ec_hwm_chassis5[] = { + { 0x33, 0x0005, TDP_COMMON }, + { 0x2f, 0x0018, TDP_COMMON }, + { 0x2f, 0x0019, TDP_COMMON }, + { 0x2f, 0x001a, TDP_COMMON }, + { 0x00, 0x0080, TDP_COMMON }, + { 0x00, 0x0081, TDP_COMMON }, + { 0xbb, 0x0083, TDP_COMMON }, + { 0x89, 0x0085, TDP_32 }, + { 0x99, 0x0085, TDP_16 }, + { 0x9c, 0x0086, TDP_COMMON }, + { 0x39, 0x008a, TDP_32 }, + { 0x42, 0x008a, TDP_16 }, + { 0x6b, 0x008b, TDP_32 }, + { 0x74, 0x008b, TDP_16 }, + { 0x5e, 0x0091, TDP_COMMON }, + { 0x86, 0x0092, TDP_COMMON }, + { 0xa4, 0x0096, TDP_COMMON }, + { 0xa4, 0x0097, TDP_COMMON }, + { 0xa4, 0x0098, TDP_COMMON }, + { 0xa4, 0x009b, TDP_COMMON }, + { 0x0c, 0x00a0, TDP_COMMON }, + { 0x0c, 0x00a1, TDP_COMMON }, + { 0x7c, 0x00ae, TDP_COMMON }, + { 0x7c, 0x00af, TDP_COMMON }, + { 0x9a, 0x00b0, TDP_COMMON }, + { 0x7c, 0x00b3, TDP_COMMON }, + { 0x08, 0x00b6, TDP_COMMON }, + { 0x08, 0x00b7, TDP_COMMON }, + { 0x64, 0x00ea, TDP_COMMON }, + { 0xff, 0x00ef, TDP_COMMON }, + { 0x15, 0x00f8, TDP_COMMON }, + { 0x00, 0x00f9, TDP_COMMON }, + { 0x30, 0x00f0, TDP_COMMON }, + { 0x01, 0x00fd, TDP_COMMON }, + { 0x88, 0x01a1, TDP_COMMON }, + { 0x08, 0x01a2, TDP_COMMON }, + { 0x08, 0x01b1, TDP_COMMON }, + { 0x90, 0x01be, TDP_COMMON }, + { 0x94, 0x0280, TDP_32 }, + { 0x11, 0x0281, TDP_32 }, + { 0x3c, 0x0280, TDP_16 }, + { 0x0f, 0x0281, TDP_16 }, + { 0x03, 0x0282, TDP_COMMON }, + { 0x0a, 0x0283, TDP_COMMON }, + { 0x80, 0x0284, TDP_COMMON }, + { 0x03, 0x0285, TDP_COMMON }, + { 0x60, 0x0288, TDP_32 }, + { 0x09, 0x0289, TDP_32 }, + { 0x98, 0x0288, TDP_16 }, + { 0x08, 0x0289, TDP_16 }, + { 0x03, 0x028a, TDP_COMMON }, + { 0x0a, 0x028b, TDP_COMMON }, + { 0x80, 0x028c, TDP_COMMON }, + { 0x03, 0x028d, TDP_COMMON }, +}; + +static const ec_chassis_tdp_t ec_hwm_chassis6[] = { + { 0x33, 0x0005, TDP_COMMON }, + { 0x2f, 0x0018, TDP_COMMON }, + { 0x2f, 0x0019, TDP_COMMON }, + { 0x2f, 0x001a, TDP_COMMON }, + { 0x00, 0x0080, TDP_COMMON }, + { 0x00, 0x0081, TDP_COMMON }, + { 0xbb, 0x0083, TDP_COMMON }, + { 0x99, 0x0085, TDP_32 }, + { 0x98, 0x0085, TDP_16 }, + { 0xdc, 0x0086, TDP_32 }, + { 0x9c, 0x0086, TDP_16 }, + { 0x3d, 0x008a, TDP_32 }, + { 0x43, 0x008a, TDP_16 }, + { 0x4e, 0x008b, TDP_32 }, + { 0x47, 0x008b, TDP_16 }, + { 0x6d, 0x0090, TDP_COMMON }, + { 0x5f, 0x0091, TDP_32 }, + { 0x61, 0x0091, TDP_16 }, + { 0x86, 0x0092, TDP_COMMON }, + { 0xa4, 0x0096, TDP_COMMON }, + { 0xa4, 0x0097, TDP_COMMON }, + { 0xa4, 0x0098, TDP_COMMON }, + { 0xa4, 0x009b, TDP_COMMON }, + { 0x0e, 0x00a0, TDP_COMMON }, + { 0x0e, 0x00a1, TDP_COMMON }, + { 0x7c, 0x00ae, TDP_COMMON }, + { 0x7c, 0x00af, TDP_COMMON }, + { 0x98, 0x00b0, TDP_32 }, + { 0x9a, 0x00b0, TDP_16 }, + { 0x9a, 0x00b3, TDP_COMMON }, + { 0x08, 0x00b6, TDP_COMMON }, + { 0x08, 0x00b7, TDP_COMMON }, + { 0x64, 0x00ea, TDP_COMMON }, + { 0xff, 0x00ef, TDP_COMMON }, + { 0x15, 0x00f8, TDP_COMMON }, + { 0x00, 0x00f9, TDP_COMMON }, + { 0x30, 0x00f0, TDP_COMMON }, + { 0x01, 0x00fd, TDP_COMMON }, + { 0x88, 0x01a1, TDP_COMMON }, + { 0x08, 0x01a2, TDP_COMMON }, + { 0x08, 0x01b1, TDP_COMMON }, + { 0x97, 0x01be, TDP_32 }, + { 0x95, 0x01be, TDP_16 }, + { 0x68, 0x0280, TDP_32 }, + { 0x10, 0x0281, TDP_32 }, + { 0xd8, 0x0280, TDP_16 }, + { 0x0e, 0x0281, TDP_16 }, + { 0x03, 0x0282, TDP_COMMON }, + { 0x0a, 0x0283, TDP_COMMON }, + { 0x80, 0x0284, TDP_COMMON }, + { 0x03, 0x0285, TDP_COMMON }, + { 0xe4, 0x0288, TDP_32 }, + { 0x0c, 0x0289, TDP_32 }, + { 0x10, 0x0288, TDP_16 }, + { 0x0e, 0x0289, TDP_16 }, + { 0x03, 0x028a, TDP_COMMON }, + { 0x0a, 0x028b, TDP_COMMON }, + { 0x80, 0x028c, TDP_COMMON }, + { 0x03, 0x028d, TDP_COMMON }, +}; + + + +static uint8_t send_mbox_msg_with_int(uint8_t mbox_message) +{ + uint8_t int_sts, int_cond; + + sch5545_emi_h2ec_mbox_write(mbox_message); + + do { + int_sts = sch5545_emi_get_int_src_low(); + int_cond = int_sts & 0x71; + } while (int_cond == 0); + + sch5545_emi_set_int_src_low(int_cond); + + if ((int_sts & 1) == 0) + return 0; + + if (sch5545_emi_ec2h_mbox_read() == mbox_message) + return 1; + + return 0; +} + +static uint8_t send_mbox_msg_simple(uint8_t mbox_message) +{ + uint8_t int_sts; + + sch5545_emi_h2ec_mbox_write(mbox_message); + + do { + int_sts = sch5545_emi_get_int_src_low(); + if ((int_sts & 70) != 0) + return 0; + } while ((int_sts & 1) == 0); + + if (sch5545_emi_ec2h_mbox_read() == mbox_message) + return 1; + + return 0; +} + +static void ec_check_mbox_and_int_status(uint8_t int_src, uint8_t mbox_msg) +{ + uint8_t val; + + val = sch5545_emi_ec2h_mbox_read(); + if (val != mbox_msg) + printk(BIOS_SPEW, "EC2H mailbox should be %02x, is %02x\n", mbox_msg, val); + + val = sch5545_emi_get_int_src_low(); + if (val != int_src) + printk(BIOS_SPEW, "EC INT SRC should be %02x, is %02x\n", int_src, val); + + sch5545_emi_set_int_src_low(val); +} + +static uint8_t ec_read_write_reg(uint8_t ldn, uint16_t reg, uint8_t *value, uint8_t rw_bit) +{ + uint8_t int_mask_bckup, ret = 0; + rw_bit &= 1; + + int_mask_bckup = sch5545_emi_get_int_mask_low(); + sch5545_emi_set_int_mask_low(0); + + sch5545_emi_ec_write16(0x8000, (ldn << 1) | 0x100 | rw_bit); + if (rw_bit) + sch5545_emi_ec_write32(0x8004, (reg << 16) | *value); + else + sch5545_emi_ec_write32(0x8004, reg << 16); + + ret = send_mbox_msg_with_int(1); + if (ret && !rw_bit) + *value = sch5545_emi_ec_read8(0x8004); + else if (ret != 1 && rw_bit) + printk(BIOS_WARNING, "EC mailbox returned unexpected value " + "when writing %02x to %04x\n", *value, reg); + else if (ret != 1 && !rw_bit) + printk(BIOS_WARNING, "EC mailbox returned unexpected value " + "when reading %04x\n", reg); + + sch5545_emi_set_int_mask_low(int_mask_bckup); + + return ret; +} + +uint16_t sch5545_get_ec_fw_version(void) +{ + uint8_t val; + uint16_t ec_fw_version; + + /* Read the FW version currently loaded used by EC */ + ec_read_write_reg(EC_HWM_LDN, 0x2ad, &val, READ_OP); + ec_fw_version = (val << 8); + ec_read_write_reg(EC_HWM_LDN, 0x2ae, &val, READ_OP); + ec_fw_version |= val; + ec_read_write_reg(EC_HWM_LDN, 0x2ac, &val, READ_OP); + ec_read_write_reg(EC_HWM_LDN, 0x2fd, &val, READ_OP); + ec_read_write_reg(EC_HWM_LDN, 0x2b0, &val, READ_OP); + + return ec_fw_version; +} + +void sch5545_update_ec_firmware(uint16_t ec_version) +{ + uint8_t status; + uint16_t ec_fw_version; + uint32_t *ec_fw_file; + size_t ec_fw_file_size; + + ec_fw_file = cbfs_boot_map_with_leak("sch5545_ecfw.bin", CBFS_TYPE_RAW, + &ec_fw_file_size); + + if (!ec_fw_file || ec_fw_file_size != 0x1750) { + printk(BIOS_ERR, "EC firmware file not found in CBFS!\n"); + printk(BIOS_ERR, "The fans will keep running at maximum speed.\n"); + return; + } + + ec_fw_version = ec_fw_file[3] & 0xffff; + + /* + * After power failure EC loses its configuration. The currently used firmware version + * by EC will be reported as 0x0000. In such case EC firmware needs to be uploaded. + */ + if (ec_version != ec_fw_version) { + printk(BIOS_INFO, "SCH5545 EC is not functional, probably due to power " + "failure\n"); + printk(BIOS_INFO, "Uploading EC firmware (version %04x) to SCH5545\n", + ec_fw_version); + + if (!send_mbox_msg_simple(0x03)) { + printk(BIOS_WARNING, "EC didn't accept FW upload start signal\n"); + printk(BIOS_WARNING, "EC firmware update failed!\n"); + return; + } + + sch5545_emi_ec_write32_bulk(0x8100, ec_fw_file, ec_fw_file_size); + + status = send_mbox_msg_simple(0x04); + status += send_mbox_msg_simple(0x06); + + if (status != 2) + printk(BIOS_WARNING, "EC firmware update failed!\n"); + + if (ec_fw_version != sch5545_get_ec_fw_version()) { + printk(BIOS_ERR, "EC firmware update failed!\n"); + printk(BIOS_ERR, "The fans will keep running at maximum speed\n"); + } else { + printk(BIOS_INFO, "EC firmware update success\n"); + /* + * The vendor BIOS does a full reset after EC firmware update. Most + * likely because the fans are adapting very slowly after automatic fan + * control is enabled. This makes huge noise. To avoid it, also do the + * full reset. On next boot, it will not be necessary. + */ + full_reset(); + } + } else { + printk(BIOS_INFO, "SCH5545 EC firmware up to date (version %04x)\n", + ec_version); + } +} + +void sch5545_ec_hwm_early_init(void) +{ + uint8_t val; + int i; + + printk(BIOS_DEBUG, "%s\n", __func__); + + ec_check_mbox_and_int_status(0x20, 0x01); + + ec_read_write_reg(2, 0xcb, &val, READ_OP); + ec_read_write_reg(2, 0xb8, &val, READ_OP); + + for (i = 0; i < ARRAY_SIZE(ec_hwm_init_seq); i++) { + val = ec_hwm_init_seq[i].val; + ec_read_write_reg(EC_HWM_LDN, ec_hwm_init_seq[i].reg, &val, + WRITE_OP); + } + + ec_check_mbox_and_int_status(0x01, 0x01); +} + +static uint8_t get_sku_tdp_config(void) +{ + msr_t msr; + uint32_t power_unit, tdp; + /* Get units */ + msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = msr.lo & 0xf; + + /* Get power defaults for this SKU */ + msr = rdmsr(MSR_PKG_POWER_SKU); + tdp = msr.lo & 0x7fff; + + /* These numbers will determine which settings to use to init EC */ + if ((tdp >> power_unit) < 66) + return 16; + else + return 32; +} + +static uint8_t get_chassis_type(void) +{ + uint8_t chassis_id; + + chassis_id = get_gpio(GPIO_CHASSIS_ID0); + chassis_id |= get_gpio(GPIO_CHASSIS_ID1) << 1; + chassis_id |= get_gpio(GPIO_CHASSIS_ID2) << 2; + chassis_id |= get_gpio(GPIO_FRONT_PANEL_CHASSIS_DET_L) << 3; + + /* This mapping will determine which EC init sequence to use */ + switch (chassis_id) { + case 0x0: + return 5; + case 0x8: + return 4; + case 0x3: + case 0xb: + return 3; + case 0x1: + case 0x9: + case 0x5: + case 0xd: + return 6; + default: + printk(BIOS_DEBUG, "Unknown chassis ID %x\n", chassis_id); + break; + } + + return 0xff; +} + +static void ec_hwm_init_late(const ec_chassis_tdp_t *ec_hwm_sequence, size_t size) +{ + unsigned int i; + uint8_t val; + uint8_t tdp_config = get_sku_tdp_config(); + + for (i = 0; i < size; i++) { + if (ec_hwm_sequence[i].tdp == tdp_config || + ec_hwm_sequence[i].tdp == TDP_COMMON) { + val = ec_hwm_sequence[i].val; + ec_read_write_reg(EC_HWM_LDN, ec_hwm_sequence[i].reg, &val, WRITE_OP); + } + } +} + +static void prepare_for_hwm_ec_sequence(uint8_t write_only, uint8_t *value) +{ + uint16_t reg; + uint8_t val; + + if (write_only == 1) { + val = *value; + reg = 0x02fc; + } else { + if (value != NULL) + ec_read_write_reg(EC_HWM_LDN, 0x02fc, value, READ_OP); + val = 0xa0; + ec_read_write_reg(EC_HWM_LDN, 0x2fc, &val, WRITE_OP); + val = 0x32; + reg = 0x02fd; + } + + ec_read_write_reg(1, reg, &val, WRITE_OP); +} + +void sch5545_ec_hwm_init(void *unused) +{ + uint8_t val, val_2fc, chassis_type, fan_speed_full = 0; + + printk(BIOS_DEBUG, "%s\n", __func__); + sch5545_emi_init(0x2e); + + chassis_type = get_chassis_type(); + + ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP); + ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP); + ec_read_write_reg(EC_HWM_LDN, 0x0042, &val, READ_OP); + ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP); + val |= 0x02; + ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP); + ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP); + ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP); + ec_read_write_reg(EC_HWM_LDN, 0x0042, &val, READ_OP); + ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP); + val |= 0x04; + ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP); + ec_read_write_reg(EC_HWM_LDN, 0x0081, &val, READ_OP); + ec_read_write_reg(EC_HWM_LDN, 0x0027, &val, READ_OP); + + ec_check_mbox_and_int_status(0x00, 0x01); + + prepare_for_hwm_ec_sequence(0, &val_2fc); + + if (chassis_type != 0xff) { + printk(BIOS_DEBUG, "Performing HWM init for chassis %d\n", chassis_type); + switch (chassis_type) { + case 3: + ec_hwm_init_late(ec_hwm_chassis3, ARRAY_SIZE(ec_hwm_chassis3)); + break; + case 4: + ec_hwm_init_late(ec_hwm_chassis4, ARRAY_SIZE(ec_hwm_chassis4)); + break; + case 5: + ec_hwm_init_late(ec_hwm_chassis6, ARRAY_SIZE(ec_hwm_chassis5)); + break; + case 6: + ec_hwm_init_late(ec_hwm_chassis6, ARRAY_SIZE(ec_hwm_chassis6)); + break; + } + } + + if (CONFIG_MAX_CPUS > 2) { + val = 0x30; + ec_read_write_reg(EC_HWM_LDN, 0x009e, &val, WRITE_OP); + ec_read_write_reg(EC_HWM_LDN, 0x00ea, &val, READ_OP); + ec_read_write_reg(EC_HWM_LDN, 0x00eb, &val, WRITE_OP); + } + + ec_read_write_reg(EC_HWM_LDN, 0x02fc, &val_2fc, WRITE_OP); + + if (get_option(&fan_speed_full, "fan_full_speed") != CB_SUCCESS) + printk(BIOS_INFO, "fan_full_speed CMOS option not found. " + "Fans will be set up for automatic control\n"); + + if (fan_speed_full) { + ec_read_write_reg(EC_HWM_LDN, 0x0080, &val, READ_OP); + val |= 0x60; + ec_read_write_reg(EC_HWM_LDN, 0x0080, &val, WRITE_OP); + ec_read_write_reg(EC_HWM_LDN, 0x0081, &val, READ_OP); + val |= 0x60; + ec_read_write_reg(EC_HWM_LDN, 0x0081, &val, WRITE_OP); + } + + ec_read_write_reg(EC_HWM_LDN, 0x00b8, &val, READ_OP); + + if (chassis_type == 4 || chassis_type == 5) { + ec_read_write_reg(EC_HWM_LDN, 0x00a0, &val, READ_OP); + val &= 0xfb; + ec_read_write_reg(EC_HWM_LDN, 0x00a0, &val, WRITE_OP); + ec_read_write_reg(EC_HWM_LDN, 0x00a1, &val, READ_OP); + val &= 0xfb; + ec_read_write_reg(EC_HWM_LDN, 0x00a1, &val, WRITE_OP); + ec_read_write_reg(EC_HWM_LDN, 0x00a2, &val, READ_OP); + val &= 0xfb; + ec_read_write_reg(EC_HWM_LDN, 0x00a2, &val, WRITE_OP); + val = 0x99; + ec_read_write_reg(EC_HWM_LDN, 0x008a, &val, WRITE_OP); + val = 0x47; + ec_read_write_reg(EC_HWM_LDN, 0x008b, &val, WRITE_OP); + val = 0x91; + ec_read_write_reg(EC_HWM_LDN, 0x008c, &val, WRITE_OP); + } + + ec_read_write_reg(EC_HWM_LDN, 0x0049, &val, READ_OP); + val &= 0xf7; + ec_read_write_reg(EC_HWM_LDN, 0x0049, &val, WRITE_OP); + + val = 0x6a; + if (chassis_type != 3) + ec_read_write_reg(EC_HWM_LDN, 0x0059, &val, WRITE_OP); + else + ec_read_write_reg(EC_HWM_LDN, 0x0057, &val, WRITE_OP); + + ec_read_write_reg(EC_HWM_LDN, 0x0041, &val, READ_OP); + val |= 0x40; + ec_read_write_reg(EC_HWM_LDN, 0x0041, &val, WRITE_OP); + + if (chassis_type == 3) { + ec_read_write_reg(EC_HWM_LDN, 0x0049, &val, READ_OP); + val |= 0x04; + } else { + ec_read_write_reg(EC_HWM_LDN, 0x0049, &val, READ_OP); + val |= 0x08; + } + ec_read_write_reg(EC_HWM_LDN, 0x0049, &val, WRITE_OP); + + val = 0x0e; + ec_read_write_reg(EC_HWM_LDN, 0x007b, &val, WRITE_OP); + ec_read_write_reg(EC_HWM_LDN, 0x007c, &val, WRITE_OP); + val = 0x01; + ec_read_write_reg(EC_HWM_LDN, 0x007a, &val, WRITE_OP); +} diff --git a/src/mainboard/dell/optiplex_9010/sch5545_ec.h b/src/mainboard/dell/optiplex_9010/sch5545_ec.h new file mode 100644 index 0000000000..0ca589f9eb --- /dev/null +++ b/src/mainboard/dell/optiplex_9010/sch5545_ec.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#define READ_OP 0 +#define WRITE_OP 1 + +#define EC_HWM_LDN 1 +#define EC_GPIO_LDN 2 + +/* EC GPIO configuration */ +#define EC_GPIO_PP (0 << 0) +#define EC_GPIO_OD (1 << 0) +#define EC_GPIO_FUNC0 (0 << 4) +#define EC_GPIO_FUNC1 (1 << 4) +#define EC_GPIO_FUNC2 (2 << 4) +#define EC_GPIO_FUNC3 (3 << 4) + +struct ec_val_reg { + uint8_t val; + uint16_t reg; +}; + +uint16_t sch5545_get_ec_fw_version(void); +void sch5545_update_ec_firmware(uint16_t ec_version); +void sch5545_ec_early_init(void); +void sch5545_ec_hwm_early_init(void); +void sch5545_ec_hwm_init(void *unused); diff --git a/src/mainboard/dell/optiplex_9010/sch5545_ec_early.c b/src/mainboard/dell/optiplex_9010/sch5545_ec_early.c new file mode 100644 index 0000000000..70b7de6064 --- /dev/null +++ b/src/mainboard/dell/optiplex_9010/sch5545_ec_early.c @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#include "sch5545_ec.h" + +static uint16_t emi_bar; + +static const struct ec_val_reg ec_gpio_init_table[] = { + /* + * Probably some early GPIO initialization, setting GPIO functions. + * The LSBs in third column match the GPIO config registers offsets for + * non-default GPIOs. + */ + { EC_GPIO_PP | EC_GPIO_FUNC1, 0x08cc }, /* GP063 (def) / KBDRST# */ + { EC_GPIO_PP | EC_GPIO_FUNC1, 0x08d0 }, /* GP064 (def) / A20M */ + { EC_GPIO_PP | EC_GPIO_FUNC1, 0x089c }, /* GP047 / TXD1 (def) */ + { EC_GPIO_PP | EC_GPIO_FUNC1, 0x0878 }, /* GP036 (def) / SMBCLK1 */ + { EC_GPIO_PP | EC_GPIO_FUNC1, 0x0880 }, /* GP040 (def) / SMBDAT1 */ + { EC_GPIO_OD | EC_GPIO_FUNC1, 0x0884 }, /* GP041 (def) / IO_PME# */ + { EC_GPIO_PP | EC_GPIO_FUNC1, 0x08e4 }, /* GP071 (def) / IO_SMI# */ + { EC_GPIO_PP | EC_GPIO_FUNC1, 0x08e0 }, /* GP070 (def) / SPEAKER */ + { EC_GPIO_PP | EC_GPIO_FUNC1, 0x0848 }, /* GP022 (def) / PWM1 */ + { EC_GPIO_PP | EC_GPIO_FUNC1, 0x084c }, /* GP023 (def) / PWM2 */ + { EC_GPIO_PP | EC_GPIO_FUNC1, 0x0850 }, /* GP024 (def) / PWM3 */ + { EC_GPIO_PP | EC_GPIO_FUNC1, 0x083c }, /* GP017 / TACH1 (def) */ + { EC_GPIO_PP | EC_GPIO_FUNC1, 0x0840 }, /* GP020 / TACH2 (def) */ + { EC_GPIO_PP | EC_GPIO_FUNC1, 0x0844 }, /* GP021 / TACH3 (def) */ + { EC_GPIO_PP | EC_GPIO_FUNC1, 0x0814 }, /* GP005 (def) / PECI_REQ# */ +}; + +static const struct ec_val_reg ec_hwm_early_init_table[] = { + /* Probably some early hardware monitor initialization */ + { 0xff, 0x0005 }, + { 0x30, 0x00f0 }, + { 0x10, 0x00f8 }, + { 0x00, 0x00f9 }, + { 0x00, 0x00fa }, + { 0x00, 0x00fb }, + { 0x00, 0x00ea }, + { 0x00, 0x00eb }, + { 0x7c, 0x00ef }, + { 0x03, 0x006e }, + { 0x51, 0x02d0 }, + { 0x01, 0x02d2 }, + { 0x12, 0x059a }, + { 0x11, 0x059e }, + { 0x14, 0x05a2 }, + { 0x55, 0x05a3 }, + { 0x01, 0x02db }, + { 0x01, 0x0040 }, +}; + +static void ec_read_write_reg_timeout(uint16_t ldn, uint8_t *val, uint16_t reg, + uint8_t rw_bit) +{ + uint16_t timeout = 0; + rw_bit &= 1; + sch5545_emi_ec2h_mailbox_clear(); + sch5545_emi_ec_write16(0x8000, (ldn << 1) | 0x100 | rw_bit); + + sch5545_emi_set_ec_addr(0x8004); + + if (rw_bit) + outb(*val, emi_bar + SCH5545_EMI_EC_DATA); + + outb(reg & 0xff, emi_bar + SCH5545_EMI_EC_DATA + 2); + outb((reg >> 8) & 0xff, emi_bar + SCH5545_EMI_EC_DATA + 3); + sch5545_emi_h2ec_mbox_write(1); + + do { + timeout++; + if ((sch5545_emi_ec2h_mbox_read() & 1) != 0) + break; + } while (timeout < 0xfff); + + sch5545_emi_set_int_src(0x11); + sch5545_emi_h2ec_mbox_write(0xc0); + + if (!rw_bit) + *val = inb(emi_bar + SCH5545_EMI_EC_DATA); +} + +static void ec_init_gpios(void) +{ + unsigned int i; + uint8_t val; + + for (i = 0; i < ARRAY_SIZE(ec_gpio_init_table); i++) { + val = ec_gpio_init_table[i].val; + ec_read_write_reg_timeout(EC_GPIO_LDN, &val, ec_gpio_init_table[i].reg, + WRITE_OP); + } +} + +static void ec_early_hwm_init(void) +{ + unsigned int i; + uint8_t val; + + for (i = 0; i < ARRAY_SIZE(ec_hwm_early_init_table); i++) { + val = ec_hwm_early_init_table[i].val; + ec_read_write_reg_timeout(EC_HWM_LDN, &val, ec_hwm_early_init_table[i].reg, + WRITE_OP); + } +} + +void sch5545_ec_early_init(void) +{ + emi_bar = sch5545_read_emi_bar(0x2e); + + ec_init_gpios(); + ec_early_hwm_init(); +} diff --git a/src/mainboard/dell/optiplex_9010/smihandler.c b/src/mainboard/dell/optiplex_9010/smihandler.c new file mode 100644 index 0000000000..d3c83ef5e7 --- /dev/null +++ b/src/mainboard/dell/optiplex_9010/smihandler.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +void mainboard_smi_gpi(u32 gpi_sts) +{ + printk(BIOS_SPEW, "%s: gpi_sts: %08x\n", __func__, gpi_sts); +} + +int mainboard_smi_apmc(u8 data) +{ + u8 val; + switch (data) { + case APM_CNT_ACPI_ENABLE: + printk(BIOS_SPEW, "%s: APM CNT EN: %02x\n", __func__, data); + /* Enable wake on PS2 */ + val = inb(SCH5545_RUNTIME_REG_BASE + SCH5545_RR_PME_EN1); + val |= (SCH5545_KBD_PME_EN | SCH5545_MOUSE_PME_EN); + outb(val, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_PME_EN1); + /* Clear pending and enable PMEs */ + outb(SCH5545_GLOBAL_PME_STS, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_PME_STS); + outb(SCH5545_GLOBAL_PME_EN, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_PME_EN); + break; + case APM_CNT_ACPI_DISABLE: + printk(BIOS_SPEW, "%s: APM CNT DIS: %02x\n", __func__, data); + /* Disable wake on PS2 */ + val = inb(SCH5545_RUNTIME_REG_BASE + SCH5545_RR_PME_EN1); + val &= ~(SCH5545_KBD_PME_EN | SCH5545_MOUSE_PME_EN); + outb(val, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_PME_EN1); + /* Clear pending and disable PMEs */ + outb(SCH5545_GLOBAL_PME_STS, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_PME_STS); + outb(0, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_PME_EN); + break; + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + printk(BIOS_SPEW, "%s: SMI sleep: %02x\n", __func__, slp_typ); +} From 563424e986edc1027d49c0efd151118a2e687c86 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 14 May 2020 14:52:14 -0700 Subject: [PATCH 085/405] Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports" This reverts commit 2412924bc7646fc22b2cb1b9108413fa3e849082. Reason for revert: Resource allocator patches need to be reverted until the AMD chipsets can be fixed to handle the resource allocation flow correctly. BUG=b:149186922 Change-Id: Iea6db8cc0cb5a0e81d176ed3199c91dcd02d1859 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41411 Reviewed-by: Angel Pons Reviewed-by: Mike Banon Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/Kconfig | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 68759636a0..de77633153 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -15,7 +15,6 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 - select PCIEXP_HOTPLUG select SOC_INTEL_TIGERLAKE if BOARD_GOOGLE_BASEBOARD_VOLTEER @@ -67,20 +66,6 @@ config MAX_CPUS int default 8 -# Reserving resources for PCIe Hotplug as per TGL BIOS Spec (doc #611569) -# Revision 0.7.6 Section 7.2.5.1.5 -config PCIEXP_HOTPLUG_BUSES - int - default 42 - -config PCIEXP_HOTPLUG_MEM - hex - default 0xc200000 # 194 MiB - -config PCIEXP_HOTPLUG_PREFETCH_MEM - hex - default 0x1c000000 # 448 MiB - config TPM_TIS_ACPI_INTERRUPT int default 21 # GPE0_DW0_21 (GPP_C21) From 196d8559d90ff1ac1ebf52fc23b5a6a2493b386c Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 15 May 2020 23:34:27 -0700 Subject: [PATCH 086/405] Revert "pciexp_device: Add option to allocate prefetch memory above 4G boundary" This reverts commit dcbf6454b6d2d9b3627a14126ef20ed4b9c7d954. Reason for revert: Resource allocator patches need to be reverted until the AMD chipsets can be fixed to handle the resource allocation flow correctly. Change-Id: I58c9fff1a18ea1c9941e29c2c6e60e338c517c30 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41465 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Mike Banon --- src/device/Kconfig | 15 --------------- src/device/pciexp_device.c | 10 +++------- 2 files changed, 3 insertions(+), 22 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index 2976a61a8f..6096a38b6f 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -585,21 +585,6 @@ config PCIEXP_HOTPLUG_PREFETCH_MEM child devices. This size should be page-aligned. The default is 256 MiB. -config PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G - bool - default y if !PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G - default n - help - This enables prefetch memory allocation above 4G boundary for the - hotplug resources. - -config PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G - bool "PCI Express Hotplug Prefetch Memory Allocation below 4G boundary" - default n - help - This enables prefetch memory allocation below 4G boundary for the - hotplug resources. - config PCIEXP_HOTPLUG_IO hex "PCI Express Hotplug I/O Space" default 0x2000 diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index f04d865152..1189207539 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -512,7 +512,7 @@ static void pciexp_hotplug_dummy_read_resources(struct device *dev) { struct resource *resource; - /* Add extra memory space */ + // Add extra memory space resource = new_resource(dev, 0x10); resource->size = CONFIG_PCIEXP_HOTPLUG_MEM; resource->align = 12; @@ -520,7 +520,7 @@ static void pciexp_hotplug_dummy_read_resources(struct device *dev) resource->limit = 0xffffffff; resource->flags |= IORESOURCE_MEM; - /* Add extra prefetchable memory space */ + // Add extra prefetchable memory space resource = new_resource(dev, 0x14); resource->size = CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM; resource->align = 12; @@ -528,11 +528,7 @@ static void pciexp_hotplug_dummy_read_resources(struct device *dev) resource->limit = 0xffffffffffffffff; resource->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; - /* Set resource flag requesting allocation above 4G boundary. */ - if (CONFIG(PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G)) - resource->flags |= IORESOURCE_ABOVE_4G; - - /* Add extra I/O space */ + // Add extra I/O space resource = new_resource(dev, 0x18); resource->size = CONFIG_PCIEXP_HOTPLUG_IO; resource->align = 12; From bca71f643cfbef5d931d237ed778d278d16a00f7 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 14 May 2020 14:56:58 -0700 Subject: [PATCH 087/405] Revert "device: Enable resource allocation above 4G boundary" This reverts commit 44ae0eacb82259243bf844a3fe5ad24a7821e997. Reason for revert: Resource allocator patches need to be reverted until the AMD chipsets can be fixed to handle the resource allocation flow correctly. BUG=b:149186922 Change-Id: I90f3eac2d23b5f59ab356ae48ed94d14c7405774 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41412 Reviewed-by: Angel Pons Reviewed-by: Mike Banon Reviewed-by: HAOUAS Elyes Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/device/device.c | 120 +++------------------------------- src/include/device/resource.h | 2 - 2 files changed, 9 insertions(+), 113 deletions(-) diff --git a/src/device/device.c b/src/device/device.c index 633346ede0..3ed64da34a 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -593,19 +593,6 @@ static void update_bridge_resource(const struct device *bridge, struct resource if (child_res->limit && (child_res->limit < bridge_res->limit)) bridge_res->limit = child_res->limit; - /* - * Propagate the downstream resource request to allocate above 4G boundary to - * upstream bridge resource. This ensures that during pass 2, the resource - * allocator at domain level has a global view of all the downstream device - * requirements and thus address space is allocated as per updated flags in the - * bridge resource. - * - * Since the bridge resource is a single window, all the downstream resources of - * this bridge resource will be allocated space above 4G boundary. - */ - if (child_res->flags & IORESOURCE_ABOVE_4G) - bridge_res->flags |= IORESOURCE_ABOVE_4G; - /* * Alignment value of 0 means that the child resource has no alignment * requirements and so the base value remains unchanged here. @@ -700,98 +687,24 @@ static void compute_domain_resources(const struct device *domain) } } -/* - * If the resource base is set to the limit, then it means that the resource is invalid and - * hence cannot be used for allocation. - */ -static bool is_resource_invalid(const struct resource *res) -{ - return res->base == res->limit; -} - -/* - * This function initializes memranges for domain device. If the resource crosses 4G boundary, - * then this function splits it into two ranges -- one for the window below 4G and the other for - * the window above 4G. The latter range has IORESOURCE_ABOVE_4G flag set to satisfy resource - * requests from downstream devices for allocations above 4G. - */ -static void initialize_domain_memranges(struct memranges *ranges, const struct resource *res, - unsigned long memrange_type) +static void initialize_memranges(struct memranges *ranges, const struct resource *res, + unsigned long memrange_type) { resource_t res_base; resource_t res_limit; - const resource_t limit_4g = 0xffffffff; memranges_init_empty(ranges, NULL, 0); - if ((res == NULL) || is_resource_invalid(res)) + if (res == NULL) return; res_base = res->base; res_limit = res->limit; - /* - * Split the resource into two separate ranges if it crosses the 4G boundary. Memrange - * type is set differently to ensure that memrange does not merge these two ranges. For - * the range above 4G boundary, given memrange type is ORed with IORESOURCE_ABOVE_4G. - */ - if (res_base <= limit_4g) { - - resource_t range_limit; - - /* Clip the resource limit at 4G boundary if necessary. */ - range_limit = MIN(res_limit, limit_4g); - memranges_insert(ranges, res_base, range_limit - res_base + 1, memrange_type); - - /* - * If the resource lies completely below the 4G boundary, nothing more needs to - * be done. - */ - if (res_limit <= limit_4g) - return; - - /* - * If the resource window crosses the 4G boundary, then update res_base to add - * another entry for the range above the boundary. - */ - res_base = limit_4g + 1; - } - - if (res_base > res_limit) + if (res_base == res_limit) return; - /* - * If resource lies completely above the 4G boundary or if the resource was clipped to - * add two separate ranges, the range above 4G boundary has the resource flag - * IORESOURCE_ABOVE_4G set. This allows domain to handle any downstream requests for - * resource allocation above 4G differently. - */ - memranges_insert(ranges, res_base, res_limit - res_base + 1, - memrange_type | IORESOURCE_ABOVE_4G); -} - -/* - * This function initializes memranges for bridge device. Unlike domain, bridge does not need to - * care about resource window crossing 4G boundary. This is handled by the resource allocator at - * domain level to ensure that all downstream bridges are allocated space either above or below - * 4G boundary as per the state of IORESOURCE_ABOVE_4G for the respective bridge resource. - * - * So, this function creates a single range of the entire resource window available for the - * bridge resource. Thus all downstream resources of the bridge for the given resource type get - * allocated space from the same window. If there is any downstream resource of the bridge which - * requests allocation above 4G, then all other downstream resources of the same type under the - * bridge get allocated above 4G. - */ -static void initialize_bridge_memranges(struct memranges *ranges, const struct resource *res, - unsigned long memrange_type) -{ - - memranges_init_empty(ranges, NULL, 0); - - if ((res == NULL) || is_resource_invalid(res)) - return; - - memranges_insert(ranges, res->base, res->limit - res->base + 1, memrange_type); + memranges_insert(ranges, res_base, res_limit - res_base + 1, memrange_type); } static void print_resource_ranges(const struct memranges *ranges) @@ -921,12 +834,10 @@ static void setup_resource_ranges(const struct device *dev, const struct resourc dev_path(dev), resource2str(res), res->base, res->size, res->align, res->gran, res->limit); - if (dev->path.type == DEVICE_PATH_DOMAIN) { - initialize_domain_memranges(ranges, res, type); + initialize_memranges(ranges, res, type); + + if (dev->path.type == DEVICE_PATH_DOMAIN) constrain_domain_resources(dev->link_list, ranges, type); - } else { - initialize_bridge_memranges(ranges, res, type); - } print_resource_ranges(ranges); } @@ -1032,25 +943,12 @@ static void allocate_domain_resources(const struct device *domain) * Domain does not distinguish between mem and prefmem resources. Thus, the resource * allocation at domain level considers mem and prefmem together when finding the best * fit based on the biggest resource requirement. - * - * However, resource requests for allocation above 4G boundary need to be handled - * separately if the domain resource window crosses this boundary. There is a single - * window for resource of type IORESOURCE_MEM. When creating memranges, this resource - * is split into two separate ranges -- one for the window below 4G boundary and other - * for the window above 4G boundary (with IORESOURCE_ABOVE_4G flag set). Thus, when - * allocating child resources, requests for below and above the 4G boundary are handled - * separately by setting the type_mask and type_match to allocate_child_resources() - * accordingly. */ res = find_domain_resource(domain, IORESOURCE_MEM); if (res) { setup_resource_ranges(domain, res, IORESOURCE_MEM, &ranges); - allocate_child_resources(domain->link_list, &ranges, - IORESOURCE_TYPE_MASK | IORESOURCE_ABOVE_4G, + allocate_child_resources(domain->link_list, &ranges, IORESOURCE_TYPE_MASK, IORESOURCE_MEM); - allocate_child_resources(domain->link_list, &ranges, - IORESOURCE_TYPE_MASK | IORESOURCE_ABOVE_4G, - IORESOURCE_MEM | IORESOURCE_ABOVE_4G); cleanup_resource_ranges(domain, &ranges, res); } diff --git a/src/include/device/resource.h b/src/include/device/resource.h index 4ebdfa3d47..1d04e9a1c8 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -24,8 +24,6 @@ #define IORESOURCE_SUBTRACTIVE 0x00040000 /* The IO resource has a bus below it. */ #define IORESOURCE_BRIDGE 0x00080000 -/* This is a request to allocate resource about 4G boundary. */ -#define IORESOURCE_ABOVE_4G 0x00100000 /* The resource needs to be reserved in the coreboot table */ #define IORESOURCE_RESERVE 0x10000000 /* The IO resource assignment has been stored in the device */ From 6186cbcdc7c51362d139548da0acb5dc2af6a7e4 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 14 May 2020 14:57:21 -0700 Subject: [PATCH 088/405] Revert "device: Enable resource allocator to use multiple ranges" This reverts commit 3b02006afe8a85477dafa1bd149f1f0dba02afc7. Reason for revert: Resource allocator patches need to be reverted until the AMD chipsets can be fixed to handle the resource allocation flow correctly. BUG=b:149186922 Change-Id: Id9872b90482319748b4f3ba2e0de2185d5c50667 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41413 Reviewed-by: Angel Pons Reviewed-by: Mike Banon Reviewed-by: Aaron Durbin Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/device/device.c | 1025 ++++++++++++++++++++++--------------------- 1 file changed, 514 insertions(+), 511 deletions(-) diff --git a/src/device/device.c b/src/device/device.c index 3ed64da34a..e4b5f12023 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -155,10 +154,14 @@ struct device *alloc_find_dev(struct bus *parent, struct device_path *path) */ static resource_t round(resource_t val, unsigned long pow) { - return ALIGN_UP(val, POWER_OF_2(pow)); + resource_t mask; + mask = (1ULL << pow) - 1ULL; + val += mask; + val &= ~mask; + return val; } -static const char *resource2str(const struct resource *res) +static const char *resource2str(struct resource *res) { if (res->flags & IORESOURCE_IO) return "io"; @@ -263,6 +266,466 @@ static const struct device *largest_resource(struct bus *bus, return state.result_dev; } +/** + * This function is the guts of the resource allocator. + * + * The problem. + * - Allocate resource locations for every device. + * - Don't overlap, and follow the rules of bridges. + * - Don't overlap with resources in fixed locations. + * - Be efficient so we don't have ugly strategies. + * + * The strategy. + * - Devices that have fixed addresses are the minority so don't + * worry about them too much. Instead only use part of the address + * space for devices with programmable addresses. This easily handles + * everything except bridges. + * + * - PCI devices are required to have their sizes and their alignments + * equal. In this case an optimal solution to the packing problem + * exists. Allocate all devices from highest alignment to least + * alignment or vice versa. Use this. + * + * - So we can handle more than PCI run two allocation passes on bridges. The + * first to see how large the resources are behind the bridge, and what + * their alignment requirements are. The second to assign a safe address to + * the devices behind the bridge. This allows us to treat a bridge as just + * a device with a couple of resources, and not need to special case it in + * the allocator. Also this allows handling of other types of bridges. + * + * @param bus The bus we are traversing. + * @param bridge The bridge resource which must contain the bus' resources. + * @param type_mask This value gets ANDed with the resource type. + * @param type This value must match the result of the AND. + * @return TODO + */ +static void compute_resources(struct bus *bus, struct resource *bridge, + unsigned long type_mask, unsigned long type) +{ + const struct device *dev; + struct resource *resource; + resource_t base; + base = round(bridge->base, bridge->align); + + if (!bus) + return; + + printk(BIOS_SPEW, "%s %s: base: %llx size: %llx align: %d gran: %d" + " limit: %llx\n", dev_path(bus->dev), resource2str(bridge), + base, bridge->size, bridge->align, + bridge->gran, bridge->limit); + + /* For each child which is a bridge, compute the resource needs. */ + for (dev = bus->children; dev; dev = dev->sibling) { + struct resource *child_bridge; + + if (!dev->link_list) + continue; + + /* Find the resources with matching type flags. */ + for (child_bridge = dev->resource_list; child_bridge; + child_bridge = child_bridge->next) { + struct bus* link; + + if (!(child_bridge->flags & IORESOURCE_BRIDGE) + || (child_bridge->flags & type_mask) != type) + continue; + + /* + * Split prefetchable memory if combined. Many domains + * use the same address space for prefetchable memory + * and non-prefetchable memory. Bridges below them need + * it separated. Add the PREFETCH flag to the type_mask + * and type. + */ + link = dev->link_list; + while (link && link->link_num != + IOINDEX_LINK(child_bridge->index)) + link = link->next; + + if (link == NULL) { + printk(BIOS_ERR, "link %ld not found on %s\n", + IOINDEX_LINK(child_bridge->index), + dev_path(dev)); + } + + compute_resources(link, child_bridge, + type_mask | IORESOURCE_PREFETCH, + type | (child_bridge->flags & + IORESOURCE_PREFETCH)); + } + } + + /* Remember we haven't found anything yet. */ + resource = NULL; + + /* + * Walk through all the resources on the current bus and compute the + * amount of address space taken by them. Take granularity and + * alignment into account. + */ + while ((dev = largest_resource(bus, &resource, type_mask, type))) { + + /* Size 0 resources can be skipped. */ + if (!resource->size) + continue; + + /* Propagate the resource alignment to the bridge resource. */ + if (resource->align > bridge->align) + bridge->align = resource->align; + + /* Propagate the resource limit to the bridge register. */ + if (bridge->limit > resource->limit) + bridge->limit = resource->limit; + + /* Warn if it looks like APICs aren't declared. */ + if ((resource->limit == 0xffffffff) && + (resource->flags & IORESOURCE_ASSIGNED)) { + printk(BIOS_ERR, + "Resource limit looks wrong! (no APIC?)\n"); + printk(BIOS_ERR, "%s %02lx limit %08llx\n", + dev_path(dev), resource->index, resource->limit); + } + + if (resource->flags & IORESOURCE_IO) { + /* + * Don't allow potential aliases over the legacy PCI + * expansion card addresses. The legacy PCI decodes + * only 10 bits, uses 0x100 - 0x3ff. Therefore, only + * 0x00 - 0xff can be used out of each 0x400 block of + * I/O space. + */ + if ((base & 0x300) != 0) { + base = (base & ~0x3ff) + 0x400; + } + /* + * Don't allow allocations in the VGA I/O range. + * PCI has special cases for that. + */ + else if ((base >= 0x3b0) && (base <= 0x3df)) { + base = 0x3e0; + } + } + /* Base must be aligned. */ + base = round(base, resource->align); + resource->base = base; + base += resource->size; + + printk(BIOS_SPEW, "%s %02lx * [0x%llx - 0x%llx] %s\n", + dev_path(dev), resource->index, resource->base, + resource->base + resource->size - 1, + resource2str(resource)); + } + + /* + * A PCI bridge resource does not need to be a power of two size, but + * it does have a minimum granularity. Round the size up to that + * minimum granularity so we know not to place something else at an + * address positively decoded by the bridge. + */ + bridge->size = round(base, bridge->gran) - + round(bridge->base, bridge->align); + + printk(BIOS_SPEW, "%s %s: base: %llx size: %llx align: %d gran: %d" + " limit: %llx done\n", dev_path(bus->dev), + resource2str(bridge), + base, bridge->size, bridge->align, bridge->gran, bridge->limit); +} + +/** + * This function is the second part of the resource allocator. + * + * See the compute_resources function for a more detailed explanation. + * + * This function assigns the resources a value. + * + * @param bus The bus we are traversing. + * @param bridge The bridge resource which must contain the bus' resources. + * @param type_mask This value gets ANDed with the resource type. + * @param type This value must match the result of the AND. + * + * @see compute_resources + */ +static void allocate_resources(struct bus *bus, struct resource *bridge, + unsigned long type_mask, unsigned long type) +{ + const struct device *dev; + struct resource *resource; + resource_t base; + base = bridge->base; + + if (!bus) + return; + + printk(BIOS_SPEW, "%s %s: base:%llx size:%llx align:%d gran:%d " + "limit:%llx\n", dev_path(bus->dev), + resource2str(bridge), + base, bridge->size, bridge->align, bridge->gran, bridge->limit); + + /* Remember we haven't found anything yet. */ + resource = NULL; + + /* + * Walk through all the resources on the current bus and allocate them + * address space. + */ + while ((dev = largest_resource(bus, &resource, type_mask, type))) { + + /* Propagate the bridge limit to the resource register. */ + if (resource->limit > bridge->limit) + resource->limit = bridge->limit; + + /* Size 0 resources can be skipped. */ + if (!resource->size) { + /* Set the base to limit so it doesn't confuse tolm. */ + resource->base = resource->limit; + resource->flags |= IORESOURCE_ASSIGNED; + continue; + } + + if (resource->flags & IORESOURCE_IO) { + /* + * Don't allow potential aliases over the legacy PCI + * expansion card addresses. The legacy PCI decodes + * only 10 bits, uses 0x100 - 0x3ff. Therefore, only + * 0x00 - 0xff can be used out of each 0x400 block of + * I/O space. + */ + if ((base & 0x300) != 0) { + base = (base & ~0x3ff) + 0x400; + } + /* + * Don't allow allocations in the VGA I/O range. + * PCI has special cases for that. + */ + else if ((base >= 0x3b0) && (base <= 0x3df)) { + base = 0x3e0; + } + } + + if ((round(base, resource->align) + resource->size - 1) <= + resource->limit) { + /* Base must be aligned. */ + base = round(base, resource->align); + resource->base = base; + resource->limit = resource->base + resource->size - 1; + resource->flags |= IORESOURCE_ASSIGNED; + resource->flags &= ~IORESOURCE_STORED; + base += resource->size; + } else { + printk(BIOS_ERR, "!! Resource didn't fit !!\n"); + printk(BIOS_ERR, " aligned base %llx size %llx " + "limit %llx\n", round(base, resource->align), + resource->size, resource->limit); + printk(BIOS_ERR, " %llx needs to be <= %llx " + "(limit)\n", (round(base, resource->align) + + resource->size) - 1, resource->limit); + printk(BIOS_ERR, " %s%s %02lx * [0x%llx - 0x%llx]" + " %s\n", (resource->flags & IORESOURCE_ASSIGNED) + ? "Assigned: " : "", dev_path(dev), + resource->index, resource->base, + resource->base + resource->size - 1, + resource2str(resource)); + } + + printk(BIOS_SPEW, "%s %02lx * [0x%llx - 0x%llx] %s\n", + dev_path(dev), resource->index, resource->base, + resource->size ? resource->base + resource->size - 1 : + resource->base, resource2str(resource)); + } + + /* + * A PCI bridge resource does not need to be a power of two size, but + * it does have a minimum granularity. Round the size up to that + * minimum granularity so we know not to place something else at an + * address positively decoded by the bridge. + */ + + bridge->flags |= IORESOURCE_ASSIGNED; + + printk(BIOS_SPEW, "%s %s: next_base: %llx size: %llx align: %d " + "gran: %d done\n", dev_path(bus->dev), + resource2str(bridge), base, bridge->size, bridge->align, + bridge->gran); + + /* For each child which is a bridge, allocate_resources. */ + for (dev = bus->children; dev; dev = dev->sibling) { + struct resource *child_bridge; + + if (!dev->link_list) + continue; + + /* Find the resources with matching type flags. */ + for (child_bridge = dev->resource_list; child_bridge; + child_bridge = child_bridge->next) { + struct bus* link; + + if (!(child_bridge->flags & IORESOURCE_BRIDGE) || + (child_bridge->flags & type_mask) != type) + continue; + + /* + * Split prefetchable memory if combined. Many domains + * use the same address space for prefetchable memory + * and non-prefetchable memory. Bridges below them need + * it separated. Add the PREFETCH flag to the type_mask + * and type. + */ + link = dev->link_list; + while (link && link->link_num != + IOINDEX_LINK(child_bridge->index)) + link = link->next; + if (link == NULL) + printk(BIOS_ERR, "link %ld not found on %s\n", + IOINDEX_LINK(child_bridge->index), + dev_path(dev)); + + allocate_resources(link, child_bridge, + type_mask | IORESOURCE_PREFETCH, + type | (child_bridge->flags & + IORESOURCE_PREFETCH)); + } + } +} + +static int resource_is(struct resource *res, u32 type) +{ + return (res->flags & IORESOURCE_TYPE_MASK) == type; +} + +struct constraints { + struct resource io, mem; +}; + +static struct resource *resource_limit(struct constraints *limits, + struct resource *res) +{ + struct resource *lim = NULL; + + /* MEM, or I/O - skip any others. */ + if (resource_is(res, IORESOURCE_MEM)) + lim = &limits->mem; + else if (resource_is(res, IORESOURCE_IO)) + lim = &limits->io; + + return lim; +} + +static void constrain_resources(const struct device *dev, + struct constraints* limits) +{ + const struct device *child; + struct resource *res; + struct resource *lim; + struct bus *link; + + /* Constrain limits based on the fixed resources of this device. */ + for (res = dev->resource_list; res; res = res->next) { + if (!(res->flags & IORESOURCE_FIXED)) + continue; + if (!res->size) { + /* It makes no sense to have 0-sized, fixed resources.*/ + printk(BIOS_ERR, "skipping %s@%lx fixed resource, " + "size=0!\n", dev_path(dev), res->index); + continue; + } + + lim = resource_limit(limits, res); + if (!lim) + continue; + + /* + * Is it a fixed resource outside the current known region? + * If so, we don't have to consider it - it will be handled + * correctly and doesn't affect current region's limits. + */ + if (((res->base + res->size -1) < lim->base) + || (res->base > lim->limit)) + continue; + + printk(BIOS_SPEW, "%s: %s %02lx base %08llx limit %08llx %s (fixed)\n", + __func__, dev_path(dev), res->index, res->base, + res->base + res->size - 1, resource2str(res)); + + /* + * Choose to be above or below fixed resources. This check is + * signed so that "negative" amounts of space are handled + * correctly. + */ + if ((signed long long)(lim->limit - (res->base + res->size -1)) + > (signed long long)(res->base - lim->base)) + lim->base = res->base + res->size; + else + lim->limit = res->base -1; + } + + /* Descend into every enabled child and look for fixed resources. */ + for (link = dev->link_list; link; link = link->next) { + for (child = link->children; child; child = child->sibling) { + if (child->enabled) + constrain_resources(child, limits); + } + } +} + +static void avoid_fixed_resources(const struct device *dev) +{ + struct constraints limits; + struct resource *res; + struct resource *lim; + + printk(BIOS_SPEW, "%s: %s\n", __func__, dev_path(dev)); + + /* Initialize constraints to maximum size. */ + limits.io.base = 0; + limits.io.limit = 0xffffffffffffffffULL; + limits.mem.base = 0; + limits.mem.limit = 0xffffffffffffffffULL; + + /* Constrain the limits to dev's initial resources. */ + for (res = dev->resource_list; res; res = res->next) { + if ((res->flags & IORESOURCE_FIXED)) + continue; + printk(BIOS_SPEW, "%s:@%s %02lx limit %08llx\n", __func__, + dev_path(dev), res->index, res->limit); + + lim = resource_limit(&limits, res); + if (!lim) + continue; + + if (res->base > lim->base) + lim->base = res->base; + if (res->limit < lim->limit) + lim->limit = res->limit; + } + + /* Look through the tree for fixed resources and update the limits. */ + constrain_resources(dev, &limits); + + /* Update dev's resources with new limits. */ + for (res = dev->resource_list; res; res = res->next) { + if ((res->flags & IORESOURCE_FIXED)) + continue; + + lim = resource_limit(&limits, res); + if (!lim) + continue; + + /* Is the resource outside the limits? */ + if (lim->base > res->base) + res->base = lim->base; + if (res->limit > lim->limit) + res->limit = lim->limit; + + /* MEM resources need to start at the highest address manageable. */ + if (res->flags & IORESOURCE_MEM) + res->base = resource_max(res); + + printk(BIOS_SPEW, "%s:@%s %02lx base %08llx limit %08llx\n", + __func__, dev_path(dev), res->index, res->base, res->limit); + } +} + struct device *vga_pri = NULL; static void set_vga_bridge_bits(void) { @@ -518,513 +981,6 @@ void dev_enumerate(void) printk(BIOS_INFO, "done\n"); } -static bool dev_has_children(const struct device *dev) -{ - const struct bus *bus = dev->link_list; - return bus && bus->children; -} - -/* - * During pass 1, once all the requirements for downstream devices of a bridge are gathered, - * this function calculates the overall resource requirement for the bridge. It starts by - * picking the largest resource requirement downstream for the given resource type and works by - * adding requirements in descending order. - * - * Additionally, it takes alignment and limits of the downstream devices into consideration and - * ensures that they get propagated to the bridge resource. This is required to guarantee that - * the upstream bridge/domain honors the limit and alignment requirements for this bridge based - * on the tightest constraints downstream. - */ -static void update_bridge_resource(const struct device *bridge, struct resource *bridge_res, - unsigned long type_match) -{ - const struct device *child; - struct resource *child_res; - resource_t base; - bool first_child_res = true; - const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH; - struct bus *bus = bridge->link_list; - - child_res = NULL; - - /* - * `base` keeps track of where the next allocation for child resource can take place - * from within the bridge resource window. Since the bridge resource window allocation - * is not performed yet, it can start at 0. Base gets updated every time a resource - * requirement is accounted for in the loop below. After scanning all these resources, - * base will indicate the total size requirement for the current bridge resource - * window. - */ - base = 0; - - printk(BIOS_SPEW, "%s %s: size: %llx align: %d gran: %d limit: %llx\n", - dev_path(bridge), resource2str(bridge_res), bridge_res->size, - bridge_res->align, bridge_res->gran, bridge_res->limit); - - while ((child = largest_resource(bus, &child_res, type_mask, type_match))) { - - /* Size 0 resources can be skipped. */ - if (!child_res->size) - continue; - - /* - * Propagate the resource alignment to the bridge resource if this is the first - * child resource with non-zero size being considered. For all other children - * resources, alignment is taken care of by updating the base to round up as per - * the child resource alignment. It is guaranteed that pass 2 follows the exact - * same method of picking the resource for allocation using - * largest_resource(). Thus, as long as the alignment for first child resource - * is propagated up to the bridge resource, it can be guaranteed that the - * alignment for all resources is appropriately met. - */ - if (first_child_res && (child_res->align > bridge_res->align)) - bridge_res->align = child_res->align; - - first_child_res = false; - - /* - * Propagate the resource limit to the bridge resource only if child resource - * limit is non-zero. If a downstream device has stricter requirements - * w.r.t. limits for any resource, that constraint needs to be propagated back - * up to the downstream bridges of the domain. This guarantees that the resource - * allocation which starts at the domain level takes into account all these - * constraints thus working on a global view. - */ - if (child_res->limit && (child_res->limit < bridge_res->limit)) - bridge_res->limit = child_res->limit; - - /* - * Alignment value of 0 means that the child resource has no alignment - * requirements and so the base value remains unchanged here. - */ - base = round(base, child_res->align); - - printk(BIOS_SPEW, "%s %02lx * [0x%llx - 0x%llx] %s\n", - dev_path(child), child_res->index, base, base + child_res->size - 1, - resource2str(child_res)); - - base += child_res->size; - } - - /* - * After all downstream device resources are scanned, `base` represents the total size - * requirement for the current bridge resource window. This size needs to be rounded up - * to the granularity requirement of the bridge to ensure that the upstream - * bridge/domain allocates big enough window. - */ - bridge_res->size = round(base, bridge_res->gran); - - printk(BIOS_SPEW, "%s %s: size: %llx align: %d gran: %d limit: %llx done\n", - dev_path(bridge), resource2str(bridge_res), bridge_res->size, - bridge_res->align, bridge_res->gran, bridge_res->limit); -} - -/* - * During pass 1, resource allocator at bridge level gathers requirements from downstream - * devices and updates its own resource windows for the provided resource type. - */ -static void compute_bridge_resources(const struct device *bridge, unsigned long type_match) -{ - const struct device *child; - struct resource *res; - struct bus *bus = bridge->link_list; - const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH; - - for (res = bridge->resource_list; res; res = res->next) { - if (!(res->flags & IORESOURCE_BRIDGE)) - continue; - - if ((res->flags & type_mask) != type_match) - continue; - - /* - * Ensure that the resource requirements for all downstream bridges are - * gathered before updating the window for current bridge resource. - */ - for (child = bus->children; child; child = child->sibling) { - if (!dev_has_children(child)) - continue; - compute_bridge_resources(child, type_match); - } - - /* - * Update the window for current bridge resource now that all downstream - * requirements are gathered. - */ - update_bridge_resource(bridge, res, type_match); - } -} - -/* - * During pass 1, resource allocator walks down the entire sub-tree of a domain. It gathers - * resource requirements for every downstream bridge by looking at the resource requests of its - * children. Thus, the requirement gathering begins at the leaf devices and is propagated back - * up to the downstream bridges of the domain. - * - * At domain level, it identifies every downstream bridge and walks down that bridge to gather - * requirements for each resource type i.e. i/o, mem and prefmem. Since bridges have separate - * windows for mem and prefmem, requirements for each need to be collected separately. - * - * Domain resource windows are fixed ranges and hence requirement gathering does not result in - * any changes to these fixed ranges. - */ -static void compute_domain_resources(const struct device *domain) -{ - const struct device *child; - - if (domain->link_list == NULL) - return; - - for (child = domain->link_list->children; child; child = child->sibling) { - - /* Skip if this is not a bridge or has no children under it. */ - if (!dev_has_children(child)) - continue; - - compute_bridge_resources(child, IORESOURCE_IO); - compute_bridge_resources(child, IORESOURCE_MEM); - compute_bridge_resources(child, IORESOURCE_MEM | IORESOURCE_PREFETCH); - } -} - -static void initialize_memranges(struct memranges *ranges, const struct resource *res, - unsigned long memrange_type) -{ - resource_t res_base; - resource_t res_limit; - - memranges_init_empty(ranges, NULL, 0); - - if (res == NULL) - return; - - res_base = res->base; - res_limit = res->limit; - - if (res_base == res_limit) - return; - - memranges_insert(ranges, res_base, res_limit - res_base + 1, memrange_type); -} - -static void print_resource_ranges(const struct memranges *ranges) -{ - const struct range_entry *r; - - printk(BIOS_INFO, "Resource ranges:\n"); - - if (memranges_is_empty(ranges)) - printk(BIOS_INFO, "EMPTY!!\n"); - - memranges_each_entry(r, ranges) { - printk(BIOS_INFO, "Base: %llx, Size: %llx, Tag: %lx\n", - range_entry_base(r), range_entry_size(r), range_entry_tag(r)); - } -} - -static void mark_resource_invalid(struct resource *res) -{ - res->base = res->limit; - res->flags |= IORESOURCE_ASSIGNED; -} - -/* - * This is where the actual allocation of resources happens during pass 2. Given the list of - * memory ranges corresponding to the resource of given type, it finds the biggest unallocated - * resource using the type mask on the downstream bus. This continues in a descending - * order until all resources of given type are allocated address space within the current - * resource window. - * - * If a downstream resource cannot be allocated space for any reason, then its base is set to - * its limit and flags are updated to indicate that the resource assignment is complete. This is - * done to ensure that it does not confuse find_pci_tolm(). - */ -static void allocate_child_resources(struct bus *bus, struct memranges *ranges, - unsigned long type_mask, unsigned long type_match) -{ - struct resource *resource = NULL; - const struct device *dev; - - while ((dev = largest_resource(bus, &resource, type_mask, type_match))) { - - if (!resource->size) { - mark_resource_invalid(resource); - continue; - } - - if (memranges_steal(ranges, resource->limit, resource->size, resource->align, - type_match, &resource->base) == false) { - printk(BIOS_ERR, "ERROR: Resource didn't fit!!! "); - printk(BIOS_SPEW, "%s %02lx * size: 0x%llx limit: %llx %s\n", - dev_path(dev), resource->index, - resource->size, resource->limit, resource2str(resource)); - mark_resource_invalid(resource); - continue; - } - - resource->limit = resource->base + resource->size - 1; - resource->flags |= IORESOURCE_ASSIGNED; - - printk(BIOS_SPEW, "%s %02lx * [0x%llx - 0x%llx] limit: %llx %s\n", - dev_path(dev), resource->index, resource->base, - resource->size ? resource->base + resource->size - 1 : - resource->base, resource->limit, resource2str(resource)); - } -} - -static void update_constraints(void *gp, struct device *dev, struct resource *res) -{ - struct memranges *ranges = gp; - - if (!res->size) - return; - - printk(BIOS_SPEW, "%s: %s %02lx base %08llx limit %08llx %s (fixed)\n", - __func__, dev_path(dev), res->index, res->base, - res->base + res->size - 1, resource2str(res)); - - memranges_create_hole(ranges, res->base, res->size); -} - -static void constrain_domain_resources(struct bus *bus, struct memranges *ranges, - unsigned long type) -{ - /* - * Scan the entire tree to identify any fixed resources allocated by any device to - * ensure that the address map for domain resources are appropriately updated. - * - * Domains can typically provide memrange for entire address space. So, this function - * punches holes in the address space for all fixed resources that are already - * defined. Both IO and normal memory resources are added as fixed. Both need to be - * removed from address space where dynamic resource allocations are sourced. - */ - search_bus_resources(bus, type | IORESOURCE_FIXED, type | IORESOURCE_FIXED, - update_constraints, ranges); - - if (type == IORESOURCE_IO) { - /* - * Don't allow allocations in the VGA I/O range. PCI has special cases for - * that. - */ - memranges_create_hole(ranges, 0x3b0, 0x3df); - - /* - * Resource allocator no longer supports the legacy behavior where I/O resource - * allocation is guaranteed to avoid aliases over legacy PCI expansion card - * addresses. - */ - } -} - -/* - * This function creates a list of memranges of given type using the resource that is - * provided. If the given resource is NULL or if the resource window size is 0, then it creates - * an empty list. This results in resource allocation for that resource type failing for all - * downstream devices since there is nothing to allocate from. - * - * In case of domain, it applies additional constraints to ensure that the memranges do not - * overlap any of the fixed resources under that domain. Domain typically seems to provide - * memrange for entire address space. Thus, it is up to the chipset to add DRAM and all other - * windows which cannot be used for resource allocation as fixed resources. - */ -static void setup_resource_ranges(const struct device *dev, const struct resource *res, - unsigned long type, struct memranges *ranges) -{ - printk(BIOS_SPEW, "%s %s: base: %llx size: %llx align: %d gran: %d limit: %llx\n", - dev_path(dev), resource2str(res), res->base, res->size, res->align, - res->gran, res->limit); - - initialize_memranges(ranges, res, type); - - if (dev->path.type == DEVICE_PATH_DOMAIN) - constrain_domain_resources(dev->link_list, ranges, type); - - print_resource_ranges(ranges); -} - -static void cleanup_resource_ranges(const struct device *dev, struct memranges *ranges, - const struct resource *res) -{ - memranges_teardown(ranges); - printk(BIOS_SPEW, "%s %s: base: %llx size: %llx align: %d gran: %d limit: %llx done\n", - dev_path(dev), resource2str(res), res->base, res->size, res->align, - res->gran, res->limit); -} - -/* - * Pass 2 of resource allocator at the bridge level loops through all the resources for the - * bridge and generates a list of memory ranges similar to that at the domain level. However, - * there is no need to apply any additional constraints since the window allocated to the bridge - * is guaranteed to be non-overlapping by the allocator at domain level. - * - * Allocation at the bridge level works the same as at domain level (starts with the biggest - * resource requirement from downstream devices and continues in descending order). One major - * difference at the bridge level is that it considers prefmem resources separately from mem - * resources. - * - * Once allocation at the current bridge is complete, resource allocator continues walking down - * the downstream bridges until it hits the leaf devices. - */ -static void allocate_bridge_resources(const struct device *bridge) -{ - struct memranges ranges; - const struct resource *res; - struct bus *bus = bridge->link_list; - unsigned long type_match; - struct device *child; - const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH; - - for (res = bridge->resource_list; res; res = res->next) { - if (!res->size) - continue; - - if (!(res->flags & IORESOURCE_BRIDGE)) - continue; - - type_match = res->flags & type_mask; - - setup_resource_ranges(bridge, res, type_match, &ranges); - allocate_child_resources(bus, &ranges, type_mask, type_match); - cleanup_resource_ranges(bridge, &ranges, res); - } - - for (child = bus->children; child; child = child->sibling) { - if (!dev_has_children(child)) - continue; - - allocate_bridge_resources(child); - } -} - -static const struct resource *find_domain_resource(const struct device *domain, - unsigned long type) -{ - const struct resource *res; - - for (res = domain->resource_list; res; res = res->next) { - if (res->flags & IORESOURCE_FIXED) - continue; - - if ((res->flags & IORESOURCE_TYPE_MASK) == type) - return res; - } - - return NULL; -} - -/* - * Pass 2 of resource allocator begins at the domain level. Every domain has two types of - * resources - io and mem. For each of these resources, this function creates a list of memory - * ranges that can be used for downstream resource allocation. This list is constrained to - * remove any fixed resources in the domain sub-tree of the given resource type. It then uses - * the memory ranges to apply best fit on the resource requirements of the downstream devices. - * - * Once resources are allocated to all downstream devices of the domain, it walks down each - * downstream bridge to continue the same process until resources are allocated to all devices - * under the domain. - */ -static void allocate_domain_resources(const struct device *domain) -{ - struct memranges ranges; - struct device *child; - const struct resource *res; - - /* Resource type I/O */ - res = find_domain_resource(domain, IORESOURCE_IO); - if (res) { - setup_resource_ranges(domain, res, IORESOURCE_IO, &ranges); - allocate_child_resources(domain->link_list, &ranges, IORESOURCE_TYPE_MASK, - IORESOURCE_IO); - cleanup_resource_ranges(domain, &ranges, res); - } - - /* - * Resource type Mem: - * Domain does not distinguish between mem and prefmem resources. Thus, the resource - * allocation at domain level considers mem and prefmem together when finding the best - * fit based on the biggest resource requirement. - */ - res = find_domain_resource(domain, IORESOURCE_MEM); - if (res) { - setup_resource_ranges(domain, res, IORESOURCE_MEM, &ranges); - allocate_child_resources(domain->link_list, &ranges, IORESOURCE_TYPE_MASK, - IORESOURCE_MEM); - cleanup_resource_ranges(domain, &ranges, res); - } - - for (child = domain->link_list->children; child; child = child->sibling) { - if (!dev_has_children(child)) - continue; - - /* Continue allocation for all downstream bridges. */ - allocate_bridge_resources(child); - } -} - -/* - * This function forms the guts of the resource allocator. It walks through the entire device - * tree for each domain two times. - * - * Every domain has a fixed set of ranges. These ranges cannot be relaxed based on the - * requirements of the downstream devices. They represent the available windows from which - * resources can be allocated to the different devices under the domain. - * - * In order to identify the requirements of downstream devices, resource allocator walks in a - * DFS fashion. It gathers the requirements from leaf devices and propagates those back up - * to their upstream bridges until the requirements for all the downstream devices of the domain - * are gathered. This is referred to as pass 1 of resource allocator. - * - * Once the requirements for all the devices under the domain are gathered, resource allocator - * walks a second time to allocate resources to downstream devices as per the - * requirements. It always picks the biggest resource request as per the type (i/o and mem) to - * allocate space from its fixed window to the immediate downstream device of the domain. In - * order to accomplish best fit for the resources, a list of ranges is maintained by each - * resource type (i/o and mem). Domain does not differentiate between mem and prefmem. Since - * they are allocated space from the same window, the resource allocator at the domain level - * ensures that the biggest requirement is selected indepedent of the prefetch type. Once the - * resource allocation for all immediate downstream devices is complete at the domain level, - * resource allocator walks down the subtree for each downstream bridge to continue the - * allocation process at the bridge level. Since bridges have separate windows for i/o, mem and - * prefmem, best fit algorithm at bridge level looks for the biggest requirement considering - * prefmem resources separately from non-prefmem resources. This continues until resource - * allocation is performed for all downstream bridges in the domain sub-tree. This is referred - * to as pass 2 of resource allocator. - * - * Some rules that are followed by the resource allocator: - * - Allocate resource locations for every device as long as the requirements can be satisfied. - * - If a resource cannot be allocated any address space, then that resource needs to be - * properly updated to ensure that it does not incorrectly overlap some address space reserved - * for a different purpose. - * - Don't overlap with resources in fixed locations. - * - Don't overlap and follow the rules of bridges -- downstream devices of bridges should use - * parts of the address space allocated to the bridge. - */ -static void allocate_resources(const struct device *root) -{ - const struct device *child; - - if ((root == NULL) || (root->link_list == NULL)) - return; - - for (child = root->link_list->children; child; child = child->sibling) { - - if (child->path.type != DEVICE_PATH_DOMAIN) - continue; - - post_log_path(child); - - /* Pass 1 - Gather requirements. */ - printk(BIOS_INFO, "Resource allocator: %s - Pass 1 (gathering requirements)\n", - dev_path(child)); - compute_domain_resources(child); - - /* Pass 2 - Allocate resources as per gathered requirements. */ - printk(BIOS_INFO, "Resource allocator: %s - Pass 2 (allocating resources)\n", - dev_path(child)); - allocate_domain_resources(child); - } -} - /** * Configure devices on the devices tree. * @@ -1040,7 +996,9 @@ static void allocate_resources(const struct device *root) */ void dev_configure(void) { + struct resource *res; const struct device *root; + const struct device *child; set_vga_bridge_bits(); @@ -1062,8 +1020,53 @@ void dev_configure(void) print_resource_tree(root, BIOS_SPEW, "After reading."); - allocate_resources(root); + /* Compute resources for all domains. */ + for (child = root->link_list->children; child; child = child->sibling) { + if (!(child->path.type == DEVICE_PATH_DOMAIN)) + continue; + post_log_path(child); + for (res = child->resource_list; res; res = res->next) { + if (res->flags & IORESOURCE_FIXED) + continue; + if (res->flags & IORESOURCE_MEM) { + compute_resources(child->link_list, + res, IORESOURCE_TYPE_MASK, IORESOURCE_MEM); + continue; + } + if (res->flags & IORESOURCE_IO) { + compute_resources(child->link_list, + res, IORESOURCE_TYPE_MASK, IORESOURCE_IO); + continue; + } + } + } + /* For all domains. */ + for (child = root->link_list->children; child; child=child->sibling) + if (child->path.type == DEVICE_PATH_DOMAIN) + avoid_fixed_resources(child); + + /* Store the computed resource allocations into device registers ... */ + printk(BIOS_INFO, "Setting resources...\n"); + for (child = root->link_list->children; child; child = child->sibling) { + if (!(child->path.type == DEVICE_PATH_DOMAIN)) + continue; + post_log_path(child); + for (res = child->resource_list; res; res = res->next) { + if (res->flags & IORESOURCE_FIXED) + continue; + if (res->flags & IORESOURCE_MEM) { + allocate_resources(child->link_list, + res, IORESOURCE_TYPE_MASK, IORESOURCE_MEM); + continue; + } + if (res->flags & IORESOURCE_IO) { + allocate_resources(child->link_list, + res, IORESOURCE_TYPE_MASK, IORESOURCE_IO); + continue; + } + } + } assign_resources(root->link_list); printk(BIOS_INFO, "Done setting resources.\n"); print_resource_tree(root, BIOS_SPEW, "After assigning values."); From edf2c8eb557c8ee16e72a2177985463e66e194c9 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 15 May 2020 18:50:09 -0700 Subject: [PATCH 089/405] soc/intel/common/block/acpi: Update northbridge.asl to ASL2.0 syntax This change updates northbridge.asl to use ASL2.0 syntax. This increases the readability of the ASL code. Signed-off-by: Furquan Shaikh Change-Id: If8eabb6b934b74e69cdf4e18981082028399244d Reviewed-on: https://review.coreboot.org/c/coreboot/+/41454 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Subrata Banik Reviewed-by: Angel Pons --- .../common/block/acpi/acpi/northbridge.asl | 36 +++++++++---------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index 33900273fb..1f58dfe720 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -183,21 +183,21 @@ Method (_CRS, 0, Serialized) * Fix up PCI memory region * Start with Top of Lower Usable DRAM */ - Store (\_SB.PCI0.MCHC.TLUD, PMIN) - Add (Subtract (PMAX, PMIN), 1, PLEN) + PMIN = \_SB.PCI0.MCHC.TLUD + PLEN = PMAX - PMIN + 1 /* Patch PM02 range based on Memory Size */ - If (LEqual (A4GS, 0)) { + If (A4GS == 0) { CreateQwordField (MCRS, PM02._LEN, MSEN) - Store (0, MSEN) + MSEN = 0 } Else { CreateQwordField (MCRS, PM02._MIN, MMIN) CreateQwordField (MCRS, PM02._MAX, MMAX) CreateQwordField (MCRS, PM02._LEN, MLEN) /* Set 64bit MMIO resource base and length */ - Store (A4GS, MLEN) - Store (A4GB, MMIN) - Subtract (Add (MMIN, MLEN), 1, MMAX) + MLEN = A4GS + MMIN = A4GB + MMAX = MMIN + MLEN - 1 } Return (MCRS) @@ -206,35 +206,35 @@ Method (_CRS, 0, Serialized) /* Get MCH BAR */ Method (GMHB, 0, Serialized) { - ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, Local0) + Local0 = \_SB.PCI0.MCHC.MHBR << 15 Return (Local0) } /* Get EP BAR */ Method (GEPB, 0, Serialized) { - ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, Local0) + Local0 = \_SB.PCI0.MCHC.EPBR << 12 Return (Local0) } /* Get PCIe BAR */ Method (GPCB, 0, Serialized) { - ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, Local0) + Local0 = \_SB.PCI0.MCHC.PXBR << 26 Return (Local0) } /* Get PCIe Length */ Method (GPCL, 0, Serialized) { - ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, Local0) + Local0 = 0x10000000 << \_SB.PCI0.MCHC.PXSZ Return (Local0) } /* Get DMI BAR */ Method (GDMB, 0, Serialized) { - ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, Local0) + Local0 = \_SB.PCI0.MCHC.DIBR << 12 Return (Local0) } @@ -282,22 +282,22 @@ Device (PDRC) }) CreateDwordField (BUF0, MCHB._BAS, MBR0) - Store (\_SB.PCI0.GMHB (), MBR0) + MBR0 = \_SB.PCI0.GMHB () CreateDwordField (BUF0, DMIB._BAS, DBR0) - Store (\_SB.PCI0.GDMB (), DBR0) + DBR0 = \_SB.PCI0.GDMB () CreateDwordField (BUF0, EGPB._BAS, EBR0) - Store (\_SB.PCI0.GEPB (), EBR0) + EBR0 = \_SB.PCI0.GEPB () CreateDwordField (BUF0, PCIX._BAS, XBR0) - Store (\_SB.PCI0.GPCB (), XBR0) + XBR0 = \_SB.PCI0.GPCB () CreateDwordField (BUF0, PCIX._LEN, XSZ0) - Store (\_SB.PCI0.GPCL (), XSZ0) + XSZ0 = \_SB.PCI0.GPCL () CreateDwordField (BUF0, FIOH._BAS, FBR0) - Subtract(0x100000000, CONFIG_ROM_SIZE, FBR0) + FBR0 = 0x100000000 - CONFIG_ROM_SIZE Return (BUF0) } From 17b48033819976405ce0acd8a8a371f166e576b5 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 15 May 2020 18:52:35 -0700 Subject: [PATCH 090/405] soc/intel/common/block/acpi: Mask lower 20 bits of TOLUD Lower 20bits of TOLUD register include 19 reserved bits and 1 lock bit. If lock bit is set, then northbridge.asl was reporting the base address of low MMIO incorrectly i.e. off by 1. This resulted in Linux kernel complaining that the MMIO window allocated to the device at the base of low MMIO is incorrect: pci 0000:00:1c.0: can't claim BAR 8 [mem 0x7fc00000-0x7fcfffff]: no compatible brw pci 0000:00:1c.0: [mem 0x7fc00000-0x7fcfffff] clipped to [mem 0x7fc00001-0x7fcfff] pci 0000:00:1c.0: bridge window [mem 0x7fc00001-0x7fcfffff] This change masks the lower 20 bits of TOLUD register when exposing it in the ACPI tables to ensure that the base address of low MMIO region is reported correctly. TEST=Verified that kernel dmesg no longer complains about the BAR at base of low MMIO. Signed-off-by: Furquan Shaikh Change-Id: I4849367d5fa03d70c50dc97c7e84454a65d1887a Reviewed-on: https://review.coreboot.org/c/coreboot/+/41455 Reviewed-by: Duncan Laurie Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/acpi/acpi/northbridge.asl | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index 1f58dfe720..53b21881ae 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -182,8 +182,10 @@ Method (_CRS, 0, Serialized) /* * Fix up PCI memory region * Start with Top of Lower Usable DRAM + * Lower 20 bits of TOLUD register need to be masked since they contain lock and + * reserved bits. */ - PMIN = \_SB.PCI0.MCHC.TLUD + PMIN = \_SB.PCI0.MCHC.TLUD & (0xfff << 20) PLEN = PMAX - PMIN + 1 /* Patch PM02 range based on Memory Size */ From 99dbca381b10a25dabdeb7dd0a03c1a45449b472 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Tue, 12 May 2020 21:05:04 +0530 Subject: [PATCH 091/405] soc/intel/common: Rename cse_is_hfs3_fw_sku_custom() Rename cse_is_hfs3_fw_sku_custom() to cse_is_hfs3_fw_sku_lite() and rename custom_bp.c to cse_lite.c. Also, rename all CSE Custom SKU references to CSE Lite SKU. TEST=Verified on hatch Signed-off-by: Sridhar Siricilla Change-Id: I20654bc14f0da8d21e31a4183df7a2e34394f34e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41341 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Rizwan Qureshi Reviewed-by: V Sowmya --- src/soc/intel/common/block/cse/Kconfig | 4 ++-- src/soc/intel/common/block/cse/Makefile.inc | 2 +- src/soc/intel/common/block/cse/cse.c | 16 ++++++++-------- .../common/block/cse/{custom_bp.c => cse_lite.c} | 12 ++++++------ .../intel/common/block/include/intelblocks/cse.h | 10 +++++----- 5 files changed, 22 insertions(+), 22 deletions(-) rename src/soc/intel/common/block/cse/{custom_bp.c => cse_lite.c} (96%) diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index e566dddcce..9f09d89656 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -13,9 +13,9 @@ config SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM Use this config to include common CSE block to make HECI function disable in SMM mode -config SOC_INTEL_CSE_CUSTOM_SKU +config SOC_INTEL_CSE_LITE_SKU bool default n depends on CHROMEOS help - Enables CSE Custom SKU + Enables CSE Lite SKU diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 418b7a2efa..30ff66bf6f 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -1,5 +1,5 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c -ramstage-$(CONFIG_SOC_INTEL_CSE_CUSTOM_SKU) += custom_bp.c +ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 0aa688dc4c..fecc71ee72 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -258,11 +258,11 @@ bool cse_is_hfs1_com_soft_temp_disable(void) return cse_check_hfs1_com(ME_HFS1_COM_SOFT_TEMP_DISABLE); } -bool cse_is_hfs3_fw_sku_custom(void) +bool cse_is_hfs3_fw_sku_lite(void) { union me_hfsts3 hfs3; hfs3.data = me_read_config32(PCI_ME_HFSTS3); - return hfs3.fields.fw_sku == ME_HFS3_FW_SKU_CUSTOM; + return hfs3.fields.fw_sku == ME_HFS3_FW_SKU_LITE; } /* Makes the host ready to communicate with CSE */ @@ -600,7 +600,7 @@ static bool cse_is_global_reset_allowed(void) * - CSE's current working state is Normal and current operation mode is Normal. * - (or) CSE's current working state is normal and current operation mode can * be Soft Temp Disable or Security Override Mode if CSE's Firmware SKU is - * Custom. + * Lite. */ if (!cse_is_hfs1_cws_normal()) return false; @@ -608,7 +608,7 @@ static bool cse_is_global_reset_allowed(void) if (cse_is_hfs1_com_normal()) return true; - if (cse_is_hfs3_fw_sku_custom()) { + if (cse_is_hfs3_fw_sku_lite()) { if (cse_is_hfs1_com_soft_temp_disable() || cse_is_hfs1_com_secover_mei_msg()) return true; } @@ -669,7 +669,7 @@ static bool cse_is_hmrfpo_enable_allowed(void) * Allow sending HMRFPO ENABLE command only if: * - CSE's current working state is Normal and current operation mode is Normal * - (or) cse's current working state is normal and current operation mode is - * Soft Temp Disable if CSE's Firmware SKU is Custom + * Soft Temp Disable if CSE's Firmware SKU is Lite */ if (!cse_is_hfs1_cws_normal()) return false; @@ -677,7 +677,7 @@ static bool cse_is_hmrfpo_enable_allowed(void) if (cse_is_hfs1_com_normal()) return true; - if (cse_is_hfs3_fw_sku_custom() && cse_is_hfs1_com_soft_temp_disable()) + if (cse_is_hfs3_fw_sku_lite() && cse_is_hfs1_com_soft_temp_disable()) return true; return false; @@ -818,10 +818,10 @@ void print_me_fw_version(void *unused) return; /* - * Ignore if ME Firmware SKU type is custom since + * Ignore if ME Firmware SKU type is Lite since * print_boot_partition_info() logs RO(BP1) and RW(BP2) versions. */ - if (cse_is_hfs3_fw_sku_custom()) + if (cse_is_hfs3_fw_sku_lite()) return; /* diff --git a/src/soc/intel/common/block/cse/custom_bp.c b/src/soc/intel/common/block/cse/cse_lite.c similarity index 96% rename from src/soc/intel/common/block/cse/custom_bp.c rename to src/soc/intel/common/block/cse/cse_lite.c index 14adb21984..9e154f453b 100644 --- a/src/soc/intel/common/block/cse/custom_bp.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -10,16 +10,16 @@ #define GET_BP_STR(bp_index) (bp_index ? "RW" : "RO") /* - * CSE Firmware supports 3 boot partitions. For CSE Custom SKU, only 2 boot partitions are + * CSE Firmware supports 3 boot partitions. For CSE Lite SKU, only 2 boot partitions are * used and 3rd boot partition is set to BP_STATUS_PARTITION_NOT_PRESENT. - * CSE Custom SKU Image Layout: + * CSE Lite SKU Image Layout: * ------------- ------------------- --------------------- * |CSE REGION | => | RO | RW | DATA | => | BP1 | BP2 | DATA | * ------------- ------------------- --------------------- */ #define CSE_MAX_BOOT_PARTITIONS 3 -/* CSE Custom SKU's valid bootable partition identifiers */ +/* CSE Lite SKU's valid bootable partition identifiers */ enum boot_partition_id { /* RO(BP1) contains recovery/minimal boot FW */ RO = 0, @@ -299,9 +299,9 @@ void cse_fw_sync(void *unused) return; } - /* If CSE SKU type is not Custom, skip enabling CSE Custom SKU */ - if (!cse_is_hfs3_fw_sku_custom()) { - printk(BIOS_ERR, "cse_bp: Not a CSE Custom SKU\n"); + /* If CSE SKU type is not Lite, skip enabling CSE Lite SKU */ + if (!cse_is_hfs3_fw_sku_lite()) { + printk(BIOS_ERR, "cse_bp: Not a CSE Lite SKU\n"); return; } diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 588d3eb79c..9f85730e3f 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -40,7 +40,7 @@ /* ME Firmware SKU Types */ #define ME_HFS3_FW_SKU_CONSUMER 0x2 #define ME_HFS3_FW_SKU_CORPORATE 0x3 -#define ME_HFS3_FW_SKU_CUSTOM 0x5 +#define ME_HFS3_FW_SKU_LITE 0x5 /* HFSTS register offsets in PCI config space */ enum { @@ -201,10 +201,10 @@ bool cse_is_hfs1_com_secover_mei_msg(void); bool cse_is_hfs1_com_soft_temp_disable(void); /* - * Checks CSE's Firmware SKU is Custom or not. - * Returns true if CSE's Firmware SKU is Custom, otherwise false + * Checks CSE's Firmware SKU is Lite or not. + * Returns true if CSE's Firmware SKU is Lite, otherwise false */ -bool cse_is_hfs3_fw_sku_custom(void); +bool cse_is_hfs3_fw_sku_lite(void); /* * Polls for CSE's current operation mode 'Soft Temp Disable'. @@ -213,7 +213,7 @@ bool cse_is_hfs3_fw_sku_custom(void); uint8_t cse_wait_com_soft_temp_disable(void); /* - * The CSE Custom SKU supports notion of RO and RW boot partitions. The function will set + * The CSE Lite SKU supports notion of RO and RW boot partitions. The function will set * CSE's boot partition as per Chrome OS boot modes. In normal mode, the function allows CSE to * boot from RW and triggers recovery mode if CSE fails to jump to RW. * In software triggered recovery mode, the function allows CSE to boot from whatever is From 81f9ae9ff1122b25340b851c54a477c59d955048 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Sun, 19 Apr 2020 16:03:24 -0400 Subject: [PATCH 092/405] mb/asus/p2b: Remove variant validation guards from DSDT With conversion to variant structure complete, remove temporary guards inserted to help validate the move. With this change, all P2B family boards (currently p2b and p2b-ls) share the same S-state declarations. TEST=No apparent ACPI regression observed on p2b-ls. Change-Id: Ibd6e49adeae2a42800ee5bfd74b3850eb19843a5 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/41051 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/asus/p2b/dsdt.asl | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index d97299c1f6..c1ac5996c6 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -19,13 +19,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1) P80, 8 } - /* - * For now only define 2 power states: - * - S0 which is fully on - * - S5 which is soft off - * Any others would involve declaring the wake up methods. - */ - /* * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142 * @@ -43,15 +36,9 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1) * 6: reserved * 7: reserved */ - /* Guard these entries for the purpose of variant validation. They will be aligned later. */ Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 }) -#if CONFIG(BOARD_ASUS_P2B) Name (\_S1, Package () { 0x03, 0x03, 0x00, 0x00 }) Name (\_S5, Package () { 0x00, 0x00, 0x00, 0x00 }) -#endif -#if CONFIG(BOARD_ASUS_P2B_LS) - Name (\_S5, Package () { 0x00, 0x06, 0x00, 0x00 }) -#endif OperationRegion (GPOB, SystemIO, DEFAULT_PMBASE+DEVCTL, 0x10) Field (GPOB, ByteAcc, NoLock, Preserve) From c1c6c51ec00906038a7add6de54ca59561842ba6 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 14 May 2020 11:19:55 +0200 Subject: [PATCH 093/405] drivers/xgi: Remove dead code This was used by the now-gone Asus KFSN4-DRE mainboard. Drop it. Change-Id: Id00c883ed0f80e7af96fdf3f6e2985dd5b227831 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41402 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Aaron Durbin --- src/drivers/xgi/common/Kconfig | 7 - src/drivers/xgi/common/Makefile.inc | 1 - src/drivers/xgi/common/XGI_main.c | 851 ---- src/drivers/xgi/common/XGI_main.h | 375 -- src/drivers/xgi/common/XGIfb.h | 138 - src/drivers/xgi/common/initdef.h | 704 ---- src/drivers/xgi/common/vb_def.h | 261 -- src/drivers/xgi/common/vb_init.c | 1275 ------ src/drivers/xgi/common/vb_init.h | 9 - src/drivers/xgi/common/vb_setmode.c | 5558 ------------------------- src/drivers/xgi/common/vb_setmode.h | 27 - src/drivers/xgi/common/vb_struct.h | 169 - src/drivers/xgi/common/vb_table.h | 2495 ----------- src/drivers/xgi/common/vb_util.c | 50 - src/drivers/xgi/common/vb_util.h | 12 - src/drivers/xgi/common/vgatypes.h | 48 - src/drivers/xgi/common/vstruct.h | 546 --- src/drivers/xgi/common/xgi_coreboot.c | 431 -- src/drivers/xgi/common/xgi_coreboot.h | 264 -- src/drivers/xgi/z9s/Kconfig | 3 - src/drivers/xgi/z9s/Makefile.inc | 1 - src/drivers/xgi/z9s/z9s.c | 48 - 22 files changed, 13273 deletions(-) delete mode 100644 src/drivers/xgi/common/Kconfig delete mode 100644 src/drivers/xgi/common/Makefile.inc delete mode 100644 src/drivers/xgi/common/XGI_main.c delete mode 100644 src/drivers/xgi/common/XGI_main.h delete mode 100644 src/drivers/xgi/common/XGIfb.h delete mode 100644 src/drivers/xgi/common/initdef.h delete mode 100644 src/drivers/xgi/common/vb_def.h delete mode 100644 src/drivers/xgi/common/vb_init.c delete mode 100644 src/drivers/xgi/common/vb_init.h delete mode 100644 src/drivers/xgi/common/vb_setmode.c delete mode 100644 src/drivers/xgi/common/vb_setmode.h delete mode 100644 src/drivers/xgi/common/vb_struct.h delete mode 100644 src/drivers/xgi/common/vb_table.h delete mode 100644 src/drivers/xgi/common/vb_util.c delete mode 100644 src/drivers/xgi/common/vb_util.h delete mode 100644 src/drivers/xgi/common/vgatypes.h delete mode 100644 src/drivers/xgi/common/vstruct.h delete mode 100644 src/drivers/xgi/common/xgi_coreboot.c delete mode 100644 src/drivers/xgi/common/xgi_coreboot.h delete mode 100644 src/drivers/xgi/z9s/Kconfig delete mode 100644 src/drivers/xgi/z9s/Makefile.inc delete mode 100644 src/drivers/xgi/z9s/z9s.c diff --git a/src/drivers/xgi/common/Kconfig b/src/drivers/xgi/common/Kconfig deleted file mode 100644 index 767dd841ba..0000000000 --- a/src/drivers/xgi/common/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -config DRIVERS_XGI_Z79_COMMON - bool - select VGA if VGA_TEXT_FRAMEBUFFER - select NO_EDID_FILL_FB - select MAINBOARD_HAS_NATIVE_VGA_INIT - select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT - select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/drivers/xgi/common/Makefile.inc b/src/drivers/xgi/common/Makefile.inc deleted file mode 100644 index 2bb35a8731..0000000000 --- a/src/drivers/xgi/common/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-$(CONFIG_DRIVERS_XGI_Z79_COMMON) += vb_init.c vb_util.c vb_setmode.c xgi_coreboot.c diff --git a/src/drivers/xgi/common/XGI_main.c b/src/drivers/xgi/common/XGI_main.c deleted file mode 100644 index 25c50375a2..0000000000 --- a/src/drivers/xgi/common/XGI_main.c +++ /dev/null @@ -1,851 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Code taken from the Linux xgifb driver (v3.18.5) - * Select functions taken from the Linux xgifb driver file XGI_main_26.c - * - * Original file header: - * XG20, XG21, XG40, XG42 frame buffer device - * for Linux kernels 2.5.x, 2.6.x - * Base on TW's sis fbdev code. - */ - - -#define Index_CR_GPIO_Reg1 0x48 -#define Index_CR_GPIO_Reg3 0x4a - -#define GPIOG_EN (1<<6) -#define GPIOG_READ (1<<1) - -// static char *mode; -static int vesa = -1; -static unsigned int refresh_rate; - -/* ---------------- Chip generation dependent routines ---------------- */ - -/* for XGI 315/550/650/740/330 */ - -static int XGIfb_get_dram_size(struct xgifb_video_info *xgifb_info) -{ - - u8 ChannelNum, tmp; - u8 reg = 0; - - /* xorg driver sets 32MB * 1 channel */ - if (xgifb_info->chip == XG27) - xgifb_reg_set(XGISR, IND_SIS_DRAM_SIZE, 0x51); - - reg = xgifb_reg_get(XGISR, IND_SIS_DRAM_SIZE); - if (!reg) - return -1; - - switch ((reg & XGI_DRAM_SIZE_MASK) >> 4) { - case XGI_DRAM_SIZE_1MB: - xgifb_info->video_size = 0x100000; - break; - case XGI_DRAM_SIZE_2MB: - xgifb_info->video_size = 0x200000; - break; - case XGI_DRAM_SIZE_4MB: - xgifb_info->video_size = 0x400000; - break; - case XGI_DRAM_SIZE_8MB: - xgifb_info->video_size = 0x800000; - break; - case XGI_DRAM_SIZE_16MB: - xgifb_info->video_size = 0x1000000; - break; - case XGI_DRAM_SIZE_32MB: - xgifb_info->video_size = 0x2000000; - break; - case XGI_DRAM_SIZE_64MB: - xgifb_info->video_size = 0x4000000; - break; - case XGI_DRAM_SIZE_128MB: - xgifb_info->video_size = 0x8000000; - break; - case XGI_DRAM_SIZE_256MB: - xgifb_info->video_size = 0x10000000; - break; - default: - return -1; - } - - tmp = (reg & 0x0c) >> 2; - switch (xgifb_info->chip) { - case XG20: - case XG21: - case XG27: - ChannelNum = 1; - break; - - case XG42: - if (reg & 0x04) - ChannelNum = 2; - else - ChannelNum = 1; - break; - - case XG40: - default: - if (tmp == 2) - ChannelNum = 2; - else if (tmp == 3) - ChannelNum = 3; - else - ChannelNum = 1; - break; - } - - xgifb_info->video_size = xgifb_info->video_size * ChannelNum; - - pr_info("SR14=%x DramSize %x ChannelNum %x\n", - reg, - xgifb_info->video_size, ChannelNum); - return 0; - -} - -void XGIRegInit(struct vb_device_info *XGI_Pr, unsigned long BaseAddr) -{ - XGI_Pr->P3c4 = BaseAddr + 0x14; - XGI_Pr->P3d4 = BaseAddr + 0x24; - XGI_Pr->P3c0 = BaseAddr + 0x10; - XGI_Pr->P3ce = BaseAddr + 0x1e; - XGI_Pr->P3c2 = BaseAddr + 0x12; - XGI_Pr->P3cc = BaseAddr + 0x1c; - XGI_Pr->P3ca = BaseAddr + 0x1a; - XGI_Pr->P3c6 = BaseAddr + 0x16; - XGI_Pr->P3c7 = BaseAddr + 0x17; - XGI_Pr->P3c8 = BaseAddr + 0x18; - XGI_Pr->P3c9 = BaseAddr + 0x19; - XGI_Pr->P3da = BaseAddr + 0x2A; - XGI_Pr->Part0Port = BaseAddr + XGI_CRT2_PORT_00; - /* Digital video interface registers (LCD) */ - XGI_Pr->Part1Port = BaseAddr + SIS_CRT2_PORT_04; - /* 301 TV Encoder registers */ - XGI_Pr->Part2Port = BaseAddr + SIS_CRT2_PORT_10; - /* 301 Macrovision registers */ - XGI_Pr->Part3Port = BaseAddr + SIS_CRT2_PORT_12; - /* 301 VGA2 (and LCD) registers */ - XGI_Pr->Part4Port = BaseAddr + SIS_CRT2_PORT_14; - /* 301 palette address port registers */ - XGI_Pr->Part5Port = BaseAddr + SIS_CRT2_PORT_14 + 2; - -} - -/* ------------------ Internal helper routines ----------------- */ - -static int XGIfb_GetXG21DefaultLVDSModeIdx(struct xgifb_video_info *xgifb_info) -{ - int i = 0; - - while ((XGIbios_mode[i].mode_no != 0) - && (XGIbios_mode[i].xres <= xgifb_info->lvds_data.LVDSHDE)) { - if ((XGIbios_mode[i].xres == xgifb_info->lvds_data.LVDSHDE) - && (XGIbios_mode[i].yres == xgifb_info->lvds_data.LVDSVDE) - && (XGIbios_mode[i].bpp == 8)) { - return i; - } - i++; - } - - return -1; -} - -static u8 XGIfb_search_refresh_rate(struct xgifb_video_info *xgifb_info, - unsigned int rate) -{ - u16 xres, yres; - int i = 0; - - xres = XGIbios_mode[xgifb_info->mode_idx].xres; - yres = XGIbios_mode[xgifb_info->mode_idx].yres; - - xgifb_info->rate_idx = 0; - while ((XGIfb_vrate[i].idx != 0) && (XGIfb_vrate[i].xres <= xres)) { - if ((XGIfb_vrate[i].xres == xres) && - (XGIfb_vrate[i].yres == yres)) { - if (XGIfb_vrate[i].refresh == rate) { - xgifb_info->rate_idx = XGIfb_vrate[i].idx; - break; - } else if (XGIfb_vrate[i].refresh > rate) { - if ((XGIfb_vrate[i].refresh - rate) <= 3) { - pr_debug("Adjusting rate from %d up to %d\n", - rate, XGIfb_vrate[i].refresh); - xgifb_info->rate_idx = - XGIfb_vrate[i].idx; - xgifb_info->refresh_rate = - XGIfb_vrate[i].refresh; - } else if (((rate - XGIfb_vrate[i - 1].refresh) - <= 2) && (XGIfb_vrate[i].idx - != 1)) { - pr_debug("Adjusting rate from %d down to %d\n", - rate, - XGIfb_vrate[i-1].refresh); - xgifb_info->rate_idx = - XGIfb_vrate[i - 1].idx; - xgifb_info->refresh_rate = - XGIfb_vrate[i - 1].refresh; - } - break; - } else if ((rate - XGIfb_vrate[i].refresh) <= 2) { - pr_debug("Adjusting rate from %d down to %d\n", - rate, XGIfb_vrate[i].refresh); - xgifb_info->rate_idx = XGIfb_vrate[i].idx; - break; - } - } - i++; - } - if (xgifb_info->rate_idx > 0) - return xgifb_info->rate_idx; - pr_info("Unsupported rate %d for %dx%d\n", - rate, xres, yres); - return 0; -} - -static void XGIfb_detect_VB(struct xgifb_video_info *xgifb_info) -{ - u8 cr32, temp = 0; - - xgifb_info->TV_plug = xgifb_info->TV_type = 0; - - cr32 = xgifb_reg_get(XGICR, IND_XGI_SCRATCH_REG_CR32); - - if ((cr32 & SIS_CRT1) && !XGIfb_crt1off) - XGIfb_crt1off = 0; - else { - if (cr32 & 0x5F) - XGIfb_crt1off = 1; - else - XGIfb_crt1off = 0; - } - - if (!xgifb_info->display2_force) { - if (cr32 & SIS_VB_TV) - xgifb_info->display2 = XGIFB_DISP_TV; - else if (cr32 & SIS_VB_LCD) - xgifb_info->display2 = XGIFB_DISP_LCD; - else if (cr32 & SIS_VB_CRT2) - xgifb_info->display2 = XGIFB_DISP_CRT; - else - xgifb_info->display2 = XGIFB_DISP_NONE; - } - - if (XGIfb_tvplug != -1) - /* Override with option */ - xgifb_info->TV_plug = XGIfb_tvplug; - else if (cr32 & SIS_VB_HIVISION) { - xgifb_info->TV_type = TVMODE_HIVISION; - xgifb_info->TV_plug = TVPLUG_SVIDEO; - } else if (cr32 & SIS_VB_SVIDEO) - xgifb_info->TV_plug = TVPLUG_SVIDEO; - else if (cr32 & SIS_VB_COMPOSITE) - xgifb_info->TV_plug = TVPLUG_COMPOSITE; - else if (cr32 & SIS_VB_SCART) - xgifb_info->TV_plug = TVPLUG_SCART; - - if (xgifb_info->TV_type == 0) { - temp = xgifb_reg_get(XGICR, 0x38); - if (temp & 0x10) - xgifb_info->TV_type = TVMODE_PAL; - else - xgifb_info->TV_type = TVMODE_NTSC; - } - - /* Copy forceCRT1 option to CRT1off if option is given */ - if (XGIfb_forcecrt1 != -1) { - if (XGIfb_forcecrt1) - XGIfb_crt1off = 0; - else - XGIfb_crt1off = 1; - } -} - -static int XGIfb_has_VB(struct xgifb_video_info *xgifb_info) -{ - u8 vb_chipid; - - vb_chipid = xgifb_reg_get(XGIPART4, 0x00); - switch (vb_chipid) { - case 0x01: - xgifb_info->hasVB = HASVB_301; - break; - case 0x02: - xgifb_info->hasVB = HASVB_302; - break; - default: - xgifb_info->hasVB = HASVB_NONE; - return 0; - } - return 1; -} - -static void XGIfb_get_VB_type(struct xgifb_video_info *xgifb_info) -{ - u8 reg; - - if (!XGIfb_has_VB(xgifb_info)) { - reg = xgifb_reg_get(XGICR, IND_XGI_SCRATCH_REG_CR37); - switch ((reg & SIS_EXTERNAL_CHIP_MASK) >> 1) { - case SIS_EXTERNAL_CHIP_LVDS: - xgifb_info->hasVB = HASVB_LVDS; - break; - case SIS_EXTERNAL_CHIP_LVDS_CHRONTEL: - xgifb_info->hasVB = HASVB_LVDS_CHRONTEL; - break; - default: - break; - } - } -} - -#if 0 -static void XGIfb_search_mode(struct xgifb_video_info *xgifb_info, - const char *name) -{ - unsigned int xres; - unsigned int yres; - unsigned int bpp; - int i; - - if (sscanf(name, "%ux%ux%u", &xres, &yres, &bpp) != 3) - goto invalid_mode; - - if (bpp == 24) - bpp = 32; /* That's for people who mix up color and fb depth. */ - - for (i = 0; XGIbios_mode[i].mode_no != 0; i++) - if (XGIbios_mode[i].xres == xres && - XGIbios_mode[i].yres == yres && - XGIbios_mode[i].bpp == bpp) { - xgifb_info->mode_idx = i; - return; - } -invalid_mode: - pr_info("Invalid mode '%s'\n", name); -} -#endif - -static void XGIfb_search_vesamode(struct xgifb_video_info *xgifb_info, - unsigned int vesamode) -{ - int i = 0; - - if (vesamode == 0) - goto invalid; - - vesamode &= 0x1dff; /* Clean VESA mode number from other flags */ - - while (XGIbios_mode[i].mode_no != 0) { - if ((XGIbios_mode[i].vesa_mode_no_1 == vesamode) || - (XGIbios_mode[i].vesa_mode_no_2 == vesamode)) { - xgifb_info->mode_idx = i; - return; - } - i++; - } - -invalid: - pr_info("Invalid VESA mode 0x%x'\n", vesamode); -} - -static int XGIfb_validate_mode(struct xgifb_video_info *xgifb_info, int myindex) -{ - u16 xres, yres; - struct xgi_hw_device_info *hw_info = &xgifb_info->hw_info; - unsigned long required_mem; - - if (xgifb_info->chip == XG21) { - if (xgifb_info->display2 == XGIFB_DISP_LCD) { - xres = xgifb_info->lvds_data.LVDSHDE; - yres = xgifb_info->lvds_data.LVDSVDE; - if (XGIbios_mode[myindex].xres > xres) - return -1; - if (XGIbios_mode[myindex].yres > yres) - return -1; - if ((XGIbios_mode[myindex].xres < xres) && - (XGIbios_mode[myindex].yres < yres)) { - if (XGIbios_mode[myindex].bpp > 8) - return -1; - } - - } - goto check_memory; - - } - - /* FIXME: for now, all is valid on XG27 */ - if (xgifb_info->chip == XG27) - goto check_memory; - - if (!(XGIbios_mode[myindex].chipset & MD_XGI315)) - return -1; - - switch (xgifb_info->display2) { - case XGIFB_DISP_LCD: - switch (hw_info->ulCRT2LCDType) { - case LCD_640x480: - xres = 640; - yres = 480; - break; - case LCD_800x600: - xres = 800; - yres = 600; - break; - case LCD_1024x600: - xres = 1024; - yres = 600; - break; - case LCD_1024x768: - xres = 1024; - yres = 768; - break; - case LCD_1152x768: - xres = 1152; - yres = 768; - break; - case LCD_1280x960: - xres = 1280; - yres = 960; - break; - case LCD_1280x768: - xres = 1280; - yres = 768; - break; - case LCD_1280x1024: - xres = 1280; - yres = 1024; - break; - case LCD_1400x1050: - xres = 1400; - yres = 1050; - break; - case LCD_1600x1200: - xres = 1600; - yres = 1200; - break; - default: - xres = 0; - yres = 0; - break; - } - if (XGIbios_mode[myindex].xres > xres) - return -1; - if (XGIbios_mode[myindex].yres > yres) - return -1; - if ((hw_info->ulExternalChip == 0x01) || /* LVDS */ - (hw_info->ulExternalChip == 0x05)) { /* LVDS+Chrontel */ - switch (XGIbios_mode[myindex].xres) { - case 512: - if (XGIbios_mode[myindex].yres != 512) - return -1; - if (hw_info->ulCRT2LCDType == LCD_1024x600) - return -1; - break; - case 640: - if ((XGIbios_mode[myindex].yres != 400) - && (XGIbios_mode[myindex].yres - != 480)) - return -1; - break; - case 800: - if (XGIbios_mode[myindex].yres != 600) - return -1; - break; - case 1024: - if ((XGIbios_mode[myindex].yres != 600) && - (XGIbios_mode[myindex].yres != 768)) - return -1; - if ((XGIbios_mode[myindex].yres == 600) && - (hw_info->ulCRT2LCDType != LCD_1024x600)) - return -1; - break; - case 1152: - if ((XGIbios_mode[myindex].yres) != 768) - return -1; - if (hw_info->ulCRT2LCDType != LCD_1152x768) - return -1; - break; - case 1280: - if ((XGIbios_mode[myindex].yres != 768) && - (XGIbios_mode[myindex].yres != 1024)) - return -1; - if ((XGIbios_mode[myindex].yres == 768) && - (hw_info->ulCRT2LCDType != LCD_1280x768)) - return -1; - break; - case 1400: - if (XGIbios_mode[myindex].yres != 1050) - return -1; - break; - case 1600: - if (XGIbios_mode[myindex].yres != 1200) - return -1; - break; - default: - return -1; - } - } else { - switch (XGIbios_mode[myindex].xres) { - case 512: - if (XGIbios_mode[myindex].yres != 512) - return -1; - break; - case 640: - if ((XGIbios_mode[myindex].yres != 400) && - (XGIbios_mode[myindex].yres != 480)) - return -1; - break; - case 800: - if (XGIbios_mode[myindex].yres != 600) - return -1; - break; - case 1024: - if (XGIbios_mode[myindex].yres != 768) - return -1; - break; - case 1280: - if ((XGIbios_mode[myindex].yres != 960) && - (XGIbios_mode[myindex].yres != 1024)) - return -1; - if (XGIbios_mode[myindex].yres == 960) { - if (hw_info->ulCRT2LCDType == - LCD_1400x1050) - return -1; - } - break; - case 1400: - if (XGIbios_mode[myindex].yres != 1050) - return -1; - break; - case 1600: - if (XGIbios_mode[myindex].yres != 1200) - return -1; - break; - default: - return -1; - } - } - break; - case XGIFB_DISP_TV: - switch (XGIbios_mode[myindex].xres) { - case 512: - case 640: - case 800: - break; - case 720: - if (xgifb_info->TV_type == TVMODE_NTSC) { - if (XGIbios_mode[myindex].yres != 480) - return -1; - } else if (xgifb_info->TV_type == TVMODE_PAL) { - if (XGIbios_mode[myindex].yres != 576) - return -1; - } - /* LVDS/CHRONTEL does not support 720 */ - if (xgifb_info->hasVB == HASVB_LVDS_CHRONTEL || - xgifb_info->hasVB == HASVB_CHRONTEL) { - return -1; - } - break; - case 1024: - if (xgifb_info->TV_type == TVMODE_NTSC) { - if (XGIbios_mode[myindex].bpp == 32) - return -1; - } - break; - default: - return -1; - } - break; - case XGIFB_DISP_CRT: - if (XGIbios_mode[myindex].xres > 1280) - return -1; - break; - case XGIFB_DISP_NONE: - break; - } - -check_memory: - required_mem = XGIbios_mode[myindex].xres * XGIbios_mode[myindex].yres * - XGIbios_mode[myindex].bpp / 8; - if (required_mem > xgifb_info->video_size) - return -1; - return myindex; - -} - -/* --------------------- SetMode routines ------------------------- */ - -static void XGIfb_pre_setmode(struct xgifb_video_info *xgifb_info) -{ - u8 cr30 = 0, cr31 = 0; - - cr31 = xgifb_reg_get(XGICR, 0x31); - cr31 &= ~0x60; - - switch (xgifb_info->display2) { - case XGIFB_DISP_CRT: - cr30 = (SIS_VB_OUTPUT_CRT2 | SIS_SIMULTANEOUS_VIEW_ENABLE); - cr31 |= SIS_DRIVER_MODE; - break; - case XGIFB_DISP_LCD: - cr30 = (SIS_VB_OUTPUT_LCD | SIS_SIMULTANEOUS_VIEW_ENABLE); - cr31 |= SIS_DRIVER_MODE; - break; - case XGIFB_DISP_TV: - if (xgifb_info->TV_type == TVMODE_HIVISION) - cr30 = (SIS_VB_OUTPUT_HIVISION - | SIS_SIMULTANEOUS_VIEW_ENABLE); - else if (xgifb_info->TV_plug == TVPLUG_SVIDEO) - cr30 = (SIS_VB_OUTPUT_SVIDEO - | SIS_SIMULTANEOUS_VIEW_ENABLE); - else if (xgifb_info->TV_plug == TVPLUG_COMPOSITE) - cr30 = (SIS_VB_OUTPUT_COMPOSITE - | SIS_SIMULTANEOUS_VIEW_ENABLE); - else if (xgifb_info->TV_plug == TVPLUG_SCART) - cr30 = (SIS_VB_OUTPUT_SCART - | SIS_SIMULTANEOUS_VIEW_ENABLE); - cr31 |= SIS_DRIVER_MODE; - - if (XGIfb_tvmode == 1 || xgifb_info->TV_type == TVMODE_PAL) - cr31 |= 0x01; - else - cr31 &= ~0x01; - break; - default: /* disable CRT2 */ - cr30 = 0x00; - cr31 |= (SIS_DRIVER_MODE | SIS_VB_OUTPUT_DISABLE); - } - - xgifb_reg_set(XGICR, IND_XGI_SCRATCH_REG_CR30, cr30); - xgifb_reg_set(XGICR, IND_XGI_SCRATCH_REG_CR31, cr31); - xgifb_reg_set(XGICR, IND_XGI_SCRATCH_REG_CR33, - (xgifb_info->rate_idx & 0x0F)); -} - -static void XGIfb_post_setmode(struct xgifb_video_info *xgifb_info) -{ - u8 reg; - unsigned char doit = 1; - - if (xgifb_info->video_bpp == 8) { - /* - * We can't switch off CRT1 on LVDS/Chrontel - * in 8bpp Modes - */ - if ((xgifb_info->hasVB == HASVB_LVDS) || - (xgifb_info->hasVB == HASVB_LVDS_CHRONTEL)) { - doit = 0; - } - /* - * We can't switch off CRT1 on 301B-DH - * in 8bpp Modes if using LCD - */ - if (xgifb_info->display2 == XGIFB_DISP_LCD) - doit = 0; - } - - /* We can't switch off CRT1 if bridge is in slave mode */ - if (xgifb_info->hasVB != HASVB_NONE) { - reg = xgifb_reg_get(XGIPART1, 0x00); - - if ((reg & 0x50) == 0x10) - doit = 0; - - } else { - XGIfb_crt1off = 0; - } - - reg = xgifb_reg_get(XGICR, 0x17); - if ((XGIfb_crt1off) && (doit)) - reg &= ~0x80; - else - reg |= 0x80; - xgifb_reg_set(XGICR, 0x17, reg); - - xgifb_reg_and(XGISR, IND_SIS_RAMDAC_CONTROL, ~0x04); - - if (xgifb_info->display2 == XGIFB_DISP_TV && - xgifb_info->hasVB == HASVB_301) { - - reg = xgifb_reg_get(XGIPART4, 0x01); - - if (reg < 0xB0) { /* Set filter for XGI301 */ - int filter_tb; - - switch (xgifb_info->video_width) { - case 320: - filter_tb = (xgifb_info->TV_type == - TVMODE_NTSC) ? 4 : 12; - break; - case 640: - filter_tb = (xgifb_info->TV_type == - TVMODE_NTSC) ? 5 : 13; - break; - case 720: - filter_tb = (xgifb_info->TV_type == - TVMODE_NTSC) ? 6 : 14; - break; - case 800: - filter_tb = (xgifb_info->TV_type == - TVMODE_NTSC) ? 7 : 15; - break; - default: - filter_tb = 0; - filter = -1; - break; - } - xgifb_reg_or(XGIPART1, - SIS_CRT2_WENABLE_315, - 0x01); - - if (xgifb_info->TV_type == TVMODE_NTSC) { - - xgifb_reg_and(XGIPART2, 0x3a, 0x1f); - - if (xgifb_info->TV_plug == TVPLUG_SVIDEO) { - - xgifb_reg_and(XGIPART2, 0x30, 0xdf); - - } else if (xgifb_info->TV_plug - == TVPLUG_COMPOSITE) { - - xgifb_reg_or(XGIPART2, 0x30, 0x20); - - switch (xgifb_info->video_width) { - case 640: - xgifb_reg_set(XGIPART2, - 0x35, - 0xEB); - xgifb_reg_set(XGIPART2, - 0x36, - 0x04); - xgifb_reg_set(XGIPART2, - 0x37, - 0x25); - xgifb_reg_set(XGIPART2, - 0x38, - 0x18); - break; - case 720: - xgifb_reg_set(XGIPART2, - 0x35, - 0xEE); - xgifb_reg_set(XGIPART2, - 0x36, - 0x0C); - xgifb_reg_set(XGIPART2, - 0x37, - 0x22); - xgifb_reg_set(XGIPART2, - 0x38, - 0x08); - break; - case 800: - xgifb_reg_set(XGIPART2, - 0x35, - 0xEB); - xgifb_reg_set(XGIPART2, - 0x36, - 0x15); - xgifb_reg_set(XGIPART2, - 0x37, - 0x25); - xgifb_reg_set(XGIPART2, - 0x38, - 0xF6); - break; - } - } - - } else if (xgifb_info->TV_type == TVMODE_PAL) { - - xgifb_reg_and(XGIPART2, 0x3A, 0x1F); - - if (xgifb_info->TV_plug == TVPLUG_SVIDEO) { - - xgifb_reg_and(XGIPART2, 0x30, 0xDF); - - } else if (xgifb_info->TV_plug - == TVPLUG_COMPOSITE) { - - xgifb_reg_or(XGIPART2, 0x30, 0x20); - - switch (xgifb_info->video_width) { - case 640: - xgifb_reg_set(XGIPART2, - 0x35, - 0xF1); - xgifb_reg_set(XGIPART2, - 0x36, - 0xF7); - xgifb_reg_set(XGIPART2, - 0x37, - 0x1F); - xgifb_reg_set(XGIPART2, - 0x38, - 0x32); - break; - case 720: - xgifb_reg_set(XGIPART2, - 0x35, - 0xF3); - xgifb_reg_set(XGIPART2, - 0x36, - 0x00); - xgifb_reg_set(XGIPART2, - 0x37, - 0x1D); - xgifb_reg_set(XGIPART2, - 0x38, - 0x20); - break; - case 800: - xgifb_reg_set(XGIPART2, - 0x35, - 0xFC); - xgifb_reg_set(XGIPART2, - 0x36, - 0xFB); - xgifb_reg_set(XGIPART2, - 0x37, - 0x14); - xgifb_reg_set(XGIPART2, - 0x38, - 0x2A); - break; - } - } - } - - if ((filter >= 0) && (filter <= 7)) { - pr_debug("FilterTable[%d]-%d: %*ph\n", - filter_tb, filter, - 4, XGI_TV_filter[filter_tb]. - filter[filter]); - xgifb_reg_set( - XGIPART2, - 0x35, - (XGI_TV_filter[filter_tb]. - filter[filter][0])); - xgifb_reg_set( - XGIPART2, - 0x36, - (XGI_TV_filter[filter_tb]. - filter[filter][1])); - xgifb_reg_set( - XGIPART2, - 0x37, - (XGI_TV_filter[filter_tb]. - filter[filter][2])); - xgifb_reg_set( - XGIPART2, - 0x38, - (XGI_TV_filter[filter_tb]. - filter[filter][3])); - } - } - } -} diff --git a/src/drivers/xgi/common/XGI_main.h b/src/drivers/xgi/common/XGI_main.h deleted file mode 100644 index 8f6589d21c..0000000000 --- a/src/drivers/xgi/common/XGI_main.h +++ /dev/null @@ -1,375 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* File taken from the Linux xgifb driver (v3.18.5) */ - -#ifndef _XGIFB_MAIN -#define _XGIFB_MAIN - -/* coreboot includes */ -#include "xgi_coreboot.h" - -/* ------------------- Constant Definitions ------------------------- */ -#include "XGIfb.h" -#include "vb_def.h" - -#define PCI_DEVICE_ID_XGI_42 0x042 -#define PCI_DEVICE_ID_XGI_27 0x027 - -/* To be included in fb.h */ -#define XGISR (xgifb_info->dev_info.P3c4) -#define XGICR (xgifb_info->dev_info.P3d4) -#define XGIDACA (xgifb_info->dev_info.P3c8) -#define XGIDACD (xgifb_info->dev_info.P3c9) -#define XGIPART1 (xgifb_info->dev_info.Part1Port) -#define XGIPART2 (xgifb_info->dev_info.Part2Port) -#define XGIPART3 (xgifb_info->dev_info.Part3Port) -#define XGIPART4 (xgifb_info->dev_info.Part4Port) -#define XGIPART5 (xgifb_info->dev_info.Part5Port) -#define XGIDAC2A XGIPART5 -#define XGIDAC2D (XGIPART5 + 1) - -#define IND_XGI_SCRATCH_REG_CR30 0x30 /* CRs */ -#define IND_XGI_SCRATCH_REG_CR31 0x31 -#define IND_XGI_SCRATCH_REG_CR32 0x32 -#define IND_XGI_SCRATCH_REG_CR33 0x33 -#define IND_XGI_LCD_PANEL 0x36 -#define IND_XGI_SCRATCH_REG_CR37 0x37 - -#define XGI_DRAM_SIZE_MASK 0xF0 /*SR14 */ -#define XGI_DRAM_SIZE_1MB 0x00 -#define XGI_DRAM_SIZE_2MB 0x01 -#define XGI_DRAM_SIZE_4MB 0x02 -#define XGI_DRAM_SIZE_8MB 0x03 -#define XGI_DRAM_SIZE_16MB 0x04 -#define XGI_DRAM_SIZE_32MB 0x05 -#define XGI_DRAM_SIZE_64MB 0x06 -#define XGI_DRAM_SIZE_128MB 0x07 -#define XGI_DRAM_SIZE_256MB 0x08 - -/* ------------------- Global Variables ----------------------------- */ - -/* display status */ -static int XGIfb_crt1off; -static int XGIfb_forcecrt1 = -1; - -/* global flags */ -static int XGIfb_tvmode; -static int enable_dstn; -// static int XGIfb_ypan = -1; - -/* TW: CRT2 type (for overriding autodetection) */ -static int XGIfb_crt2type = -1; -/* PR: Tv plug type (for overriding autodetection) */ -static int XGIfb_tvplug = -1; - -#define MD_XGI315 1 - -/* mode table */ -static const struct _XGIbios_mode { - u8 mode_no; - u16 vesa_mode_no_1; /* "XGI defined" VESA mode number */ - u16 vesa_mode_no_2; /* Real VESA mode numbers */ - u16 xres; - u16 yres; - u16 bpp; - u8 chipset; -} XGIbios_mode[] = { - { 0x56, 0x0000, 0x0000, 320, 240, 16, MD_XGI315 }, - { 0x5A, 0x0000, 0x0000, 320, 480, 8, MD_XGI315 }, - { 0x5B, 0x0000, 0x0000, 320, 480, 16, MD_XGI315 }, - { 0x2E, 0x0101, 0x0101, 640, 480, 8, MD_XGI315 }, - { 0x44, 0x0111, 0x0111, 640, 480, 16, MD_XGI315 }, - { 0x62, 0x013a, 0x0112, 640, 480, 32, MD_XGI315 }, - { 0x31, 0x0000, 0x0000, 720, 480, 8, MD_XGI315 }, - { 0x33, 0x0000, 0x0000, 720, 480, 16, MD_XGI315 }, - { 0x35, 0x0000, 0x0000, 720, 480, 32, MD_XGI315 }, - { 0x32, 0x0000, 0x0000, 720, 576, 8, MD_XGI315 }, - { 0x34, 0x0000, 0x0000, 720, 576, 16, MD_XGI315 }, - { 0x36, 0x0000, 0x0000, 720, 576, 32, MD_XGI315 }, - { 0x36, 0x0000, 0x0000, 720, 576, 32, MD_XGI315 }, - { 0x70, 0x0000, 0x0000, 800, 480, 8, MD_XGI315 }, - { 0x7a, 0x0000, 0x0000, 800, 480, 16, MD_XGI315 }, - { 0x76, 0x0000, 0x0000, 800, 480, 32, MD_XGI315 }, - { 0x30, 0x0103, 0x0103, 800, 600, 8, MD_XGI315 }, -#define DEFAULT_MODE 17 /* index for 800x600x16 */ - { 0x47, 0x0114, 0x0114, 800, 600, 16, MD_XGI315 }, - { 0x63, 0x013b, 0x0115, 800, 600, 32, MD_XGI315 }, - { 0x71, 0x0000, 0x0000, 1024, 576, 8, MD_XGI315 }, - { 0x74, 0x0000, 0x0000, 1024, 576, 16, MD_XGI315 }, - { 0x77, 0x0000, 0x0000, 1024, 576, 32, MD_XGI315 }, - { 0x77, 0x0000, 0x0000, 1024, 576, 32, MD_XGI315 }, - { 0x20, 0x0000, 0x0000, 1024, 600, 8, }, - { 0x21, 0x0000, 0x0000, 1024, 600, 16, }, - { 0x22, 0x0000, 0x0000, 1024, 600, 32, }, - { 0x38, 0x0105, 0x0105, 1024, 768, 8, MD_XGI315 }, - { 0x4A, 0x0117, 0x0117, 1024, 768, 16, MD_XGI315 }, - { 0x64, 0x013c, 0x0118, 1024, 768, 32, MD_XGI315 }, - { 0x64, 0x013c, 0x0118, 1024, 768, 32, MD_XGI315 }, - { 0x23, 0x0000, 0x0000, 1152, 768, 8, }, - { 0x24, 0x0000, 0x0000, 1152, 768, 16, }, - { 0x25, 0x0000, 0x0000, 1152, 768, 32, }, - { 0x79, 0x0000, 0x0000, 1280, 720, 8, MD_XGI315 }, - { 0x75, 0x0000, 0x0000, 1280, 720, 16, MD_XGI315 }, - { 0x78, 0x0000, 0x0000, 1280, 720, 32, MD_XGI315 }, - { 0x23, 0x0000, 0x0000, 1280, 768, 8, MD_XGI315 }, - { 0x24, 0x0000, 0x0000, 1280, 768, 16, MD_XGI315 }, - { 0x25, 0x0000, 0x0000, 1280, 768, 32, MD_XGI315 }, - { 0x7C, 0x0000, 0x0000, 1280, 960, 8, MD_XGI315 }, - { 0x7D, 0x0000, 0x0000, 1280, 960, 16, MD_XGI315 }, - { 0x7E, 0x0000, 0x0000, 1280, 960, 32, MD_XGI315 }, - { 0x3A, 0x0107, 0x0107, 1280, 1024, 8, MD_XGI315 }, - { 0x4D, 0x011a, 0x011a, 1280, 1024, 16, MD_XGI315 }, - { 0x65, 0x013d, 0x011b, 1280, 1024, 32, MD_XGI315 }, - { 0x26, 0x0000, 0x0000, 1400, 1050, 8, MD_XGI315 }, - { 0x27, 0x0000, 0x0000, 1400, 1050, 16, MD_XGI315 }, - { 0x28, 0x0000, 0x0000, 1400, 1050, 32, MD_XGI315 }, - { 0x3C, 0x0130, 0x011c, 1600, 1200, 8, MD_XGI315 }, - { 0x3D, 0x0131, 0x011e, 1600, 1200, 16, MD_XGI315 }, - { 0x66, 0x013e, 0x011f, 1600, 1200, 32, MD_XGI315 }, - { 0x68, 0x013f, 0x0000, 1920, 1440, 8, MD_XGI315 }, - { 0x69, 0x0140, 0x0000, 1920, 1440, 16, MD_XGI315 }, - { 0x6B, 0x0141, 0x0000, 1920, 1440, 32, MD_XGI315 }, - { 0x6c, 0x0000, 0x0000, 2048, 1536, 8, MD_XGI315 }, - { 0x6d, 0x0000, 0x0000, 2048, 1536, 16, MD_XGI315 }, - { 0x6e, 0x0000, 0x0000, 2048, 1536, 32, MD_XGI315 }, - { 0 }, -}; - -static const unsigned short XGI310paneltype[] = { - LCD_UNKNOWN, LCD_800x600, LCD_1024x768, LCD_1280x1024, - LCD_640x480, LCD_1024x600, LCD_1152x864, LCD_1280x960, - LCD_1152x768, LCD_1400x1050, LCD_1280x768, LCD_1600x1200, - LCD_1024x768, LCD_1024x768, LCD_1024x768}; - -static const struct _XGI_crt2type { - char name[10]; - int type_no; - int tvplug_no; -} XGI_crt2type[] = { - {"NONE", 0, -1}, - {"LCD", XGIFB_DISP_LCD, -1}, - {"TV", XGIFB_DISP_TV, -1}, - {"VGA", XGIFB_DISP_CRT, -1}, - {"SVIDEO", XGIFB_DISP_TV, TVPLUG_SVIDEO}, - {"COMPOSITE", XGIFB_DISP_TV, TVPLUG_COMPOSITE}, - {"SCART", XGIFB_DISP_TV, TVPLUG_SCART}, - {"none", 0, -1}, - {"lcd", XGIFB_DISP_LCD, -1}, - {"tv", XGIFB_DISP_TV, -1}, - {"vga", XGIFB_DISP_CRT, -1}, - {"svideo", XGIFB_DISP_TV, TVPLUG_SVIDEO}, - {"composite", XGIFB_DISP_TV, TVPLUG_COMPOSITE}, - {"scart", XGIFB_DISP_TV, TVPLUG_SCART}, - {"\0", -1, -1} -}; - -/* TV standard */ -static const struct _XGI_tvtype { - char name[6]; - int type_no; -} XGI_tvtype[] = { - {"PAL", 1}, - {"NTSC", 2}, - {"pal", 1}, - {"ntsc", 2}, - {"\0", -1} -}; - -static const struct _XGI_vrate { - u16 idx; - u16 xres; - u16 yres; - u16 refresh; -} XGIfb_vrate[] = { - {1, 640, 480, 60}, {2, 640, 480, 72}, - {3, 640, 480, 75}, {4, 640, 480, 85}, - - {5, 640, 480, 100}, {6, 640, 480, 120}, - {7, 640, 480, 160}, {8, 640, 480, 200}, - - {1, 720, 480, 60}, - {1, 720, 576, 58}, - {1, 800, 480, 60}, {2, 800, 480, 75}, {3, 800, 480, 85}, - {1, 800, 600, 60}, {2, 800, 600, 72}, {3, 800, 600, 75}, - {4, 800, 600, 85}, {5, 800, 600, 100}, - {6, 800, 600, 120}, {7, 800, 600, 160}, - - {1, 1024, 768, 60}, {2, 1024, 768, 70}, {3, 1024, 768, 75}, - {4, 1024, 768, 85}, {5, 1024, 768, 100}, {6, 1024, 768, 120}, - {1, 1024, 576, 60}, {2, 1024, 576, 75}, {3, 1024, 576, 85}, - {1, 1024, 600, 60}, - {1, 1152, 768, 60}, - {1, 1280, 720, 60}, {2, 1280, 720, 75}, {3, 1280, 720, 85}, - {1, 1280, 768, 60}, - {1, 1280, 1024, 60}, {2, 1280, 1024, 75}, {3, 1280, 1024, 85}, - {1, 1280, 960, 70}, - {1, 1400, 1050, 60}, - {1, 1600, 1200, 60}, {2, 1600, 1200, 65}, - {3, 1600, 1200, 70}, {4, 1600, 1200, 75}, - - {5, 1600, 1200, 85}, {6, 1600, 1200, 100}, - {7, 1600, 1200, 120}, - - {1, 1920, 1440, 60}, {2, 1920, 1440, 65}, - {3, 1920, 1440, 70}, {4, 1920, 1440, 75}, - - {5, 1920, 1440, 85}, {6, 1920, 1440, 100}, - {1, 2048, 1536, 60}, {2, 2048, 1536, 65}, - {3, 2048, 1536, 70}, {4, 2048, 1536, 75}, - - {5, 2048, 1536, 85}, - {0, 0, 0, 0} -}; - -static const struct _XGI_TV_filter { - u8 filter[9][4]; -} XGI_TV_filter[] = { - { { {0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_0 */ - {0x00, 0xE0, 0x10, 0x60}, - {0x00, 0xEE, 0x10, 0x44}, - {0x00, 0xF4, 0x10, 0x38}, - {0xF8, 0xF4, 0x18, 0x38}, - {0xFC, 0xFB, 0x14, 0x2A}, - {0x00, 0x00, 0x10, 0x20}, - {0x00, 0x04, 0x10, 0x18}, - {0xFF, 0xFF, 0xFF, 0xFF} } }, - { { {0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_1 */ - {0x00, 0xE0, 0x10, 0x60}, - {0x00, 0xEE, 0x10, 0x44}, - {0x00, 0xF4, 0x10, 0x38}, - {0xF8, 0xF4, 0x18, 0x38}, - {0xFC, 0xFB, 0x14, 0x2A}, - {0x00, 0x00, 0x10, 0x20}, - {0x00, 0x04, 0x10, 0x18}, - {0xFF, 0xFF, 0xFF, 0xFF} } }, - { { {0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_2 */ - {0xF5, 0xEE, 0x1B, 0x44}, - {0xF8, 0xF4, 0x18, 0x38}, - {0xEB, 0x04, 0x25, 0x18}, - {0xF1, 0x05, 0x1F, 0x16}, - {0xF6, 0x06, 0x1A, 0x14}, - {0xFA, 0x06, 0x16, 0x14}, - {0x00, 0x04, 0x10, 0x18}, - {0xFF, 0xFF, 0xFF, 0xFF} } }, - { { {0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_3 */ - {0xF1, 0x04, 0x1F, 0x18}, - {0xEE, 0x0D, 0x22, 0x06}, - {0xF7, 0x06, 0x19, 0x14}, - {0xF4, 0x0B, 0x1C, 0x0A}, - {0xFA, 0x07, 0x16, 0x12}, - {0xF9, 0x0A, 0x17, 0x0C}, - {0x00, 0x07, 0x10, 0x12}, - {0xFF, 0xFF, 0xFF, 0xFF} } }, - { { {0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_4 */ - {0x00, 0xE0, 0x10, 0x60}, - {0x00, 0xEE, 0x10, 0x44}, - {0x00, 0xF4, 0x10, 0x38}, - {0xF8, 0xF4, 0x18, 0x38}, - {0xFC, 0xFB, 0x14, 0x2A}, - {0x00, 0x00, 0x10, 0x20}, - {0x00, 0x04, 0x10, 0x18}, - {0xFF, 0xFF, 0xFF, 0xFF} } }, - { { {0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_5 */ - {0xF5, 0xEE, 0x1B, 0x44}, - {0xF8, 0xF4, 0x18, 0x38}, - {0xEB, 0x04, 0x25, 0x18}, - {0xF1, 0x05, 0x1F, 0x16}, - {0xF6, 0x06, 0x1A, 0x14}, - {0xFA, 0x06, 0x16, 0x14}, - {0x00, 0x04, 0x10, 0x18}, - {0xFF, 0xFF, 0xFF, 0xFF} } }, - { { {0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_6 */ - {0xEB, 0x04, 0x25, 0x18}, - {0xE7, 0x0E, 0x29, 0x04}, - {0xEE, 0x0C, 0x22, 0x08}, - {0xF6, 0x0B, 0x1A, 0x0A}, - {0xF9, 0x0A, 0x17, 0x0C}, - {0xFC, 0x0A, 0x14, 0x0C}, - {0x00, 0x08, 0x10, 0x10}, - {0xFF, 0xFF, 0xFF, 0xFF} } }, - { { {0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_7 */ - {0xEC, 0x02, 0x24, 0x1C}, - {0xF2, 0x04, 0x1E, 0x18}, - {0xEB, 0x15, 0x25, 0xF6}, - {0xF4, 0x10, 0x1C, 0x00}, - {0xF8, 0x0F, 0x18, 0x02}, - {0x00, 0x04, 0x10, 0x18}, - {0x01, 0x06, 0x0F, 0x14}, - {0xFF, 0xFF, 0xFF, 0xFF} } }, - { { {0x00, 0x00, 0x00, 0x40}, /* PALFilter_0 */ - {0x00, 0xE0, 0x10, 0x60}, - {0x00, 0xEE, 0x10, 0x44}, - {0x00, 0xF4, 0x10, 0x38}, - {0xF8, 0xF4, 0x18, 0x38}, - {0xFC, 0xFB, 0x14, 0x2A}, - {0x00, 0x00, 0x10, 0x20}, - {0x00, 0x04, 0x10, 0x18}, - {0xFF, 0xFF, 0xFF, 0xFF} } }, - { { {0x00, 0x00, 0x00, 0x40}, /* PALFilter_1 */ - {0x00, 0xE0, 0x10, 0x60}, - {0x00, 0xEE, 0x10, 0x44}, - {0x00, 0xF4, 0x10, 0x38}, - {0xF8, 0xF4, 0x18, 0x38}, - {0xFC, 0xFB, 0x14, 0x2A}, - {0x00, 0x00, 0x10, 0x20}, - {0x00, 0x04, 0x10, 0x18}, - {0xFF, 0xFF, 0xFF, 0xFF} } }, - { { {0x00, 0x00, 0x00, 0x40}, /* PALFilter_2 */ - {0xF5, 0xEE, 0x1B, 0x44}, - {0xF8, 0xF4, 0x18, 0x38}, - {0xF1, 0xF7, 0x01, 0x32}, - {0xF5, 0xFB, 0x1B, 0x2A}, - {0xF9, 0xFF, 0x17, 0x22}, - {0xFB, 0x01, 0x15, 0x1E}, - {0x00, 0x04, 0x10, 0x18}, - {0xFF, 0xFF, 0xFF, 0xFF} } }, - { { {0x00, 0x00, 0x00, 0x40}, /* PALFilter_3 */ - {0xF5, 0xFB, 0x1B, 0x2A}, - {0xEE, 0xFE, 0x22, 0x24}, - {0xF3, 0x00, 0x1D, 0x20}, - {0xF9, 0x03, 0x17, 0x1A}, - {0xFB, 0x02, 0x14, 0x1E}, - {0xFB, 0x04, 0x15, 0x18}, - {0x00, 0x06, 0x10, 0x14}, - {0xFF, 0xFF, 0xFF, 0xFF} } }, - { { {0x00, 0x00, 0x00, 0x40}, /* PALFilter_4 */ - {0x00, 0xE0, 0x10, 0x60}, - {0x00, 0xEE, 0x10, 0x44}, - {0x00, 0xF4, 0x10, 0x38}, - {0xF8, 0xF4, 0x18, 0x38}, - {0xFC, 0xFB, 0x14, 0x2A}, - {0x00, 0x00, 0x10, 0x20}, - {0x00, 0x04, 0x10, 0x18}, - {0xFF, 0xFF, 0xFF, 0xFF} } }, - { { {0x00, 0x00, 0x00, 0x40}, /* PALFilter_5 */ - {0xF5, 0xEE, 0x1B, 0x44}, - {0xF8, 0xF4, 0x18, 0x38}, - {0xF1, 0xF7, 0x1F, 0x32}, - {0xF5, 0xFB, 0x1B, 0x2A}, - {0xF9, 0xFF, 0x17, 0x22}, - {0xFB, 0x01, 0x15, 0x1E}, - {0x00, 0x04, 0x10, 0x18}, - {0xFF, 0xFF, 0xFF, 0xFF} } }, - { { {0x00, 0x00, 0x00, 0x40}, /* PALFilter_6 */ - {0xF5, 0xEE, 0x1B, 0x2A}, - {0xEE, 0xFE, 0x22, 0x24}, - {0xF3, 0x00, 0x1D, 0x20}, - {0xF9, 0x03, 0x17, 0x1A}, - {0xFB, 0x02, 0x14, 0x1E}, - {0xFB, 0x04, 0x15, 0x18}, - {0x00, 0x06, 0x10, 0x14}, - {0xFF, 0xFF, 0xFF, 0xFF} } }, - { { {0x00, 0x00, 0x00, 0x40}, /* PALFilter_7 */ - {0xF5, 0xEE, 0x1B, 0x44}, - {0xF8, 0xF4, 0x18, 0x38}, - {0xFC, 0xFB, 0x14, 0x2A}, - {0xEB, 0x05, 0x25, 0x16}, - {0xF1, 0x05, 0x1F, 0x16}, - {0xFA, 0x07, 0x16, 0x12}, - {0x00, 0x07, 0x10, 0x12}, - {0xFF, 0xFF, 0xFF, 0xFF} } } -}; - -static int filter = -1; - -#endif diff --git a/src/drivers/xgi/common/XGIfb.h b/src/drivers/xgi/common/XGIfb.h deleted file mode 100644 index 77fa5b3596..0000000000 --- a/src/drivers/xgi/common/XGIfb.h +++ /dev/null @@ -1,138 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* File taken from the Linux xgifb driver (v3.18.5) */ - -#ifndef _LINUX_XGIFB -#define _LINUX_XGIFB -#include "vgatypes.h" -#include "vb_struct.h" - -enum xgifb_display_type { - XGIFB_DISP_NONE = 0, - XGIFB_DISP_CRT, - XGIFB_DISP_LCD, - XGIFB_DISP_TV, -}; - -#define HASVB_NONE 0x00 -#define HASVB_301 0x01 -#define HASVB_LVDS 0x02 -#define HASVB_TRUMPION 0x04 -#define HASVB_LVDS_CHRONTEL 0x10 -#define HASVB_302 0x20 -#define HASVB_CHRONTEL 0x80 - -enum XGI_CHIP_TYPE { - XG40 = 32, - XG42, - XG20 = 48, - XG21, - XG27, -}; - -enum xgi_tvtype { - TVMODE_NTSC = 0, - TVMODE_PAL, - TVMODE_HIVISION, - TVTYPE_PALM, - TVTYPE_PALN, - TVTYPE_NTSCJ, - TVMODE_TOTAL -}; - -enum xgi_tv_plug { - TVPLUG_UNKNOWN = 0, - TVPLUG_COMPOSITE = 1, - TVPLUG_SVIDEO = 2, - TVPLUG_COMPOSITE_AND_SVIDEO = 3, - TVPLUG_SCART = 4, - TVPLUG_YPBPR_525i = 5, - TVPLUG_YPBPR_525P = 6, - TVPLUG_YPBPR_750P = 7, - TVPLUG_YPBPR_1080i = 8, - TVPLUG_TOTAL -}; - -struct XGIfb_info { - unsigned long XGIfb_id; - int chip_id; /* PCI ID of detected chip */ - int memory; /* video memory in KB which XGIfb manages */ - int heapstart; /* heap start (= XGIfb "mem" argument) in KB */ - unsigned char fbvidmode; /* current XGIfb mode */ - - unsigned char XGIfb_version; - unsigned char XGIfb_revision; - unsigned char XGIfb_patchlevel; - - unsigned char XGIfb_caps; /* XGIfb capabilities */ - - int XGIfb_tqlen; /* turbo queue length (in KB) */ - - unsigned int XGIfb_pcibus; /* The card's PCI ID */ - unsigned int XGIfb_pcislot; - unsigned int XGIfb_pcifunc; - - unsigned char XGIfb_lcdpdc; /* PanelDelayCompensation */ - - unsigned char XGIfb_lcda; /* Detected status of LCDA for low res/text modes */ - - char reserved[235]; /* for future use */ -}; - -struct xgifb_video_info { - struct fb_info *fb_info; - struct xgi_hw_device_info hw_info; - struct vb_device_info dev_info; - - int mode_idx; - int rate_idx; - - u32 pseudo_palette[17]; - - int chip_id; - unsigned int video_size; - phys_addr_t video_base; - void __iomem *video_vbase; - phys_addr_t mmio_base; - unsigned long mmio_size; - void __iomem *mmio_vbase; - unsigned long vga_base; - int mtrr; - - int video_bpp; - int video_cmap_len; - int video_width; - int video_height; - int video_vwidth; - int video_vheight; - int org_x; - int org_y; - int video_linelength; - unsigned int refresh_rate; - - enum xgifb_display_type display2; /* the second display output type */ - bool display2_force; - unsigned char hasVB; - unsigned char TV_type; - unsigned char TV_plug; - - struct XGI21_LVDSCapStruct lvds_data; - - enum XGI_CHIP_TYPE chip; - unsigned char revision_id; - - unsigned short DstColor; - unsigned long XGI310_AccelDepth; - unsigned long CommandReg; - - unsigned int pcibus; - unsigned int pcislot; - unsigned int pcifunc; - - unsigned short subsysvendor; - unsigned short subsysdevice; - - char reserved[236]; -}; - -#endif diff --git a/src/drivers/xgi/common/initdef.h b/src/drivers/xgi/common/initdef.h deleted file mode 100644 index e164e6bb66..0000000000 --- a/src/drivers/xgi/common/initdef.h +++ /dev/null @@ -1,704 +0,0 @@ -/* $XFree86$ */ -/* $XdotOrg$ */ -/* - * Global definitions for init.c and init301.c - * - * Copyright (C) 2001-2005 by Thomas Winischhofer, Vienna, Austria - * - * If distributed as part of the Linux kernel, the following license terms - * apply: - * - * * This program is free software; you can redistribute it and/or modify - * * it under the terms of the GNU General Public License as published by - * * the Free Software Foundation; either version 2 of the named License, - * * or any later version. - * * - * * This program is distributed in the hope that it will be useful, - * * but WITHOUT ANY WARRANTY; without even the implied warranty of - * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * * GNU General Public License for more details. - * - * Otherwise, the following license terms apply: - * - * * Redistribution and use in source and binary forms, with or without - * * modification, are permitted provided that the following conditions - * * are met: - * * 1) Redistributions of source code must retain the above copyright - * * notice, this list of conditions and the following disclaimer. - * * 2) Redistributions in binary form must reproduce the above copyright - * * notice, this list of conditions and the following disclaimer in the - * * documentation and/or other materials provided with the distribution. - * * 3) The name of the author may not be used to endorse or promote products - * * derived from this software without specific prior written permission. - * * - * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Author: Thomas Winischhofer - * - */ - -#ifndef _INITDEF_ -#define _INITDEF_ - -#define IS_SIS330 (SiS_Pr->ChipType == SIS_330) -#define IS_SIS550 (SiS_Pr->ChipType == SIS_550) -#define IS_SIS650 (SiS_Pr->ChipType == SIS_650) /* All versions, incl 651, M65x */ -#define IS_SIS740 (SiS_Pr->ChipType == SIS_740) -#define IS_SIS651 (SiS_Pr->SiS_SysFlags & (SF_Is651 | SF_Is652)) -#define IS_SISM650 (SiS_Pr->SiS_SysFlags & (SF_IsM650 | SF_IsM652 | SF_IsM653)) -#define IS_SIS65x (IS_SIS651 || IS_SISM650) /* Only special versions of 65x */ -#define IS_SIS661 (SiS_Pr->ChipType == SIS_661) -#define IS_SIS741 (SiS_Pr->ChipType == SIS_741) -#define IS_SIS660 (SiS_Pr->ChipType == SIS_660) -#define IS_SIS760 (SiS_Pr->ChipType == SIS_760) -#define IS_SIS761 (SiS_Pr->ChipType == SIS_761) -#define IS_SIS661741660760 (IS_SIS661 || IS_SIS741 || IS_SIS660 || IS_SIS760 || IS_SIS761) -#define IS_SIS650740 ((SiS_Pr->ChipType >= SIS_650) && (SiS_Pr->ChipType < SIS_330)) -#define IS_SIS550650740 (IS_SIS550 || IS_SIS650740) -#define IS_SIS650740660 (IS_SIS650 || IS_SIS740 || IS_SIS661741660760) -#define IS_SIS550650740660 (IS_SIS550 || IS_SIS650740660) - -#define SISGETROMW(x) (ROMAddr[(x)] | (ROMAddr[(x)+1] << 8)) - -/* SiS_VBType */ -#define VB_SIS301 0x0001 -#define VB_SIS301B 0x0002 -#define VB_SIS302B 0x0004 -#define VB_SIS301LV 0x0008 -#define VB_SIS302LV 0x0010 -#define VB_SIS302ELV 0x0020 -#define VB_SIS301C 0x0040 -#define VB_SIS307T 0x0080 -#define VB_SIS307LV 0x0100 -#define VB_UMC 0x4000 -#define VB_NoLCD 0x8000 -#define VB_SIS30xB (VB_SIS301B | VB_SIS301C | VB_SIS302B | VB_SIS307T) -#define VB_SIS30xC (VB_SIS301C | VB_SIS307T) -#define VB_SISTMDS (VB_SIS301 | VB_SIS301B | VB_SIS301C | VB_SIS302B | VB_SIS307T) -#define VB_SISLVDS (VB_SIS301LV | VB_SIS302LV | VB_SIS302ELV | VB_SIS307LV) -#define VB_SIS30xBLV (VB_SIS30xB | VB_SISLVDS) -#define VB_SIS30xCLV (VB_SIS30xC | VB_SIS302ELV | VB_SIS307LV) -#define VB_SISVB (VB_SIS301 | VB_SIS30xBLV) -#define VB_SISLCDA (VB_SIS302B | VB_SIS301C | VB_SIS307T | VB_SISLVDS) -#define VB_SISTMDSLCDA (VB_SIS301C | VB_SIS307T) -#define VB_SISPART4SCALER (VB_SIS301C | VB_SIS307T | VB_SIS302ELV | VB_SIS307LV) -#define VB_SISHIVISION (VB_SIS301 | VB_SIS301B | VB_SIS302B) -#define VB_SISYPBPR (VB_SIS301C | VB_SIS307T | VB_SIS301LV | VB_SIS302LV | VB_SIS302ELV | VB_SIS307LV) -#define VB_SISTAP4SCALER (VB_SIS301C | VB_SIS307T | VB_SIS302ELV | VB_SIS307LV) -#define VB_SISPART4OVERFLOW (VB_SIS301C | VB_SIS307T | VB_SIS302LV | VB_SIS302ELV | VB_SIS307LV) -#define VB_SISPWD (VB_SIS301C | VB_SIS307T | VB_SISLVDS) -#define VB_SISEMI (VB_SIS302LV | VB_SIS302ELV | VB_SIS307LV) -#define VB_SISPOWER (VB_SIS301C | VB_SIS307T | VB_SIS302LV | VB_SIS302ELV | VB_SIS307LV) -#define VB_SISDUALLINK (VB_SIS302LV | VB_SIS302ELV | VB_SIS307T | VB_SIS307LV) -#define VB_SISVGA2 VB_SISTMDS -#define VB_SISRAMDAC202 (VB_SIS301C | VB_SIS307T) - -/* VBInfo */ -#define SetSimuScanMode 0x0001 /* CR 30 */ -#define SwitchCRT2 0x0002 -#define SetCRT2ToAVIDEO 0x0004 -#define SetCRT2ToSVIDEO 0x0008 -#define SetCRT2ToSCART 0x0010 -#define SetCRT2ToLCD 0x0020 -#define SetCRT2ToRAMDAC 0x0040 -#define SetCRT2ToHiVision 0x0080 /* for SiS bridge */ -#define SetCRT2ToCHYPbPr SetCRT2ToHiVision /* for Chrontel */ -#define SetNTSCTV 0x0000 /* CR 31 */ -#define SetPALTV 0x0100 /* Deprecated here, now in TVMode */ -#define SetInSlaveMode 0x0200 -#define SetNotSimuMode 0x0400 -#define SetNotSimuTVMode SetNotSimuMode -#define SetDispDevSwitch 0x0800 -#define SetCRT2ToYPbPr525750 0x0800 -#define LoadDACFlag 0x1000 -#define DisableCRT2Display 0x2000 -#define DriverMode 0x4000 -#define HotKeySwitch 0x8000 -#define SetCRT2ToLCDA 0x8000 - -/* v-- Needs change in sis_vga.c if changed (GPIO) --v */ -#define SetCRT2ToTV (SetCRT2ToYPbPr525750|SetCRT2ToHiVision|SetCRT2ToSCART|SetCRT2ToSVIDEO|SetCRT2ToAVIDEO) -#define SetCRT2ToTVNoYPbPrHiVision (SetCRT2ToSCART | SetCRT2ToSVIDEO | SetCRT2ToAVIDEO) -#define SetCRT2ToTVNoHiVision (SetCRT2ToYPbPr525750 | SetCRT2ToSCART | SetCRT2ToSVIDEO | SetCRT2ToAVIDEO) - -/* SiS_ModeType */ -#define ModeText 0x00 -#define ModeCGA 0x01 -#define ModeEGA 0x02 -#define ModeVGA 0x03 -#define Mode15Bpp 0x04 -#define Mode16Bpp 0x05 -#define Mode24Bpp 0x06 -#define Mode32Bpp 0x07 - -#define ModeTypeMask 0x07 -#define IsTextMode 0x07 - -#define DACInfoFlag 0x0018 -#define MemoryInfoFlag 0x01E0 -#define MemorySizeShift 5 - -/* modeflag */ -#define Charx8Dot 0x0200 -#define LineCompareOff 0x0400 -#define CRT2Mode 0x0800 -#define HalfDCLK 0x1000 -#define NoSupportSimuTV 0x2000 -#define NoSupportLCDScale 0x4000 /* SiS bridge: No scaling possible (no matter what panel) */ -#define DoubleScanMode 0x8000 - -/* Infoflag */ -#define SupportTV 0x0008 -#define SupportTV1024 0x0800 -#define SupportCHTV 0x0800 -#define Support64048060Hz 0x0800 /* Special for 640x480 LCD */ -#define SupportHiVision 0x0010 -#define SupportYPbPr750p 0x1000 -#define SupportLCD 0x0020 -#define SupportRAMDAC2 0x0040 /* All (<= 100Mhz) */ -#define SupportRAMDAC2_135 0x0100 /* All except DH (<= 135Mhz) */ -#define SupportRAMDAC2_162 0x0200 /* B, C (<= 162Mhz) */ -#define SupportRAMDAC2_202 0x0400 /* C (<= 202Mhz) */ -#define InterlaceMode 0x0080 -#define SyncPP 0x0000 -#define HaveWideTiming 0x2000 /* Have specific wide- and non-wide timing */ -#define SyncPN 0x4000 -#define SyncNP 0x8000 -#define SyncNN 0xc000 - -/* SetFlag */ -#define ProgrammingCRT2 0x0001 -#define LowModeTests 0x0002 -/* #define TVSimuMode 0x0002 - deprecated */ -/* #define RPLLDIV2XO 0x0004 - deprecated */ -#define LCDVESATiming 0x0008 -#define EnableLVDSDDA 0x0010 -#define SetDispDevSwitchFlag 0x0020 -#define CheckWinDos 0x0040 -#define SetDOSMode 0x0080 - -/* TVMode flag */ -#define TVSetPAL 0x0001 -#define TVSetNTSCJ 0x0002 -#define TVSetPALM 0x0004 -#define TVSetPALN 0x0008 -#define TVSetCHOverScan 0x0010 -#define TVSetYPbPr525i 0x0020 /* new 0x10 */ -#define TVSetYPbPr525p 0x0040 /* new 0x20 */ -#define TVSetYPbPr750p 0x0080 /* new 0x40 */ -#define TVSetHiVision 0x0100 /* new 0x80; = 1080i, software-wise identical */ -#define TVSetTVSimuMode 0x0200 /* new 0x200, prev. 0x800 */ -#define TVRPLLDIV2XO 0x0400 /* prev 0x1000 */ -#define TVSetNTSC1024 0x0800 /* new 0x100, prev. 0x2000 */ -#define TVSet525p1024 0x1000 /* TW */ -#define TVAspect43 0x2000 -#define TVAspect169 0x4000 -#define TVAspect43LB 0x8000 - -/* YPbPr flag (>=315, <661; converted to TVMode) */ -#define YPbPr525p 0x0001 -#define YPbPr750p 0x0002 -#define YPbPr525i 0x0004 -#define YPbPrHiVision 0x0008 -#define YPbPrModeMask (YPbPr750p | YPbPr525p | YPbPr525i | YPbPrHiVision) - -/* SysFlags (to identify special versions) */ -#define SF_Is651 0x0001 -#define SF_IsM650 0x0002 -#define SF_Is652 0x0004 -#define SF_IsM652 0x0008 -#define SF_IsM653 0x0010 -#define SF_IsM661 0x0020 -#define SF_IsM741 0x0040 -#define SF_IsM760 0x0080 -#define SF_760UMA 0x4000 /* 76x: We have UMA */ -#define SF_760LFB 0x8000 /* 76x: We have LFB */ - -/* CR32 (Newer 630, and 315 series) - - [0] VB connected with CVBS - [1] VB connected with SVHS - [2] VB connected with SCART - [3] VB connected with LCD - [4] VB connected with CRT2 (secondary VGA) - [5] CRT1 monitor is connected - [6] VB connected with Hi-Vision TV - [7] <= 330: VB connected with DVI combo connector - >= 661: VB connected to YPbPr -*/ - -/* CR35 (300 series only) */ -#define TVOverScan 0x10 -#define TVOverScanShift 4 - -/* CR35 (661 series only) - [0] 1 = PAL, 0 = NTSC - [1] 1 = NTSC-J (if D0 = 0) - [2] 1 = PALM (if D0 = 1) - [3] 1 = PALN (if D0 = 1) - [4] 1 = Overscan (Chrontel only) - [7:5] (only if D2 in CR38 is set) - 000 525i - 001 525p - 010 750p - 011 1080i (or HiVision on 301, 301B) -*/ - -/* CR37 - [0] Set 24/18 bit (0/1) RGB to LVDS/TMDS transmitter (set by BIOS) - [3:1] External chip - 300 series: - 001 SiS301 (never seen) - 010 LVDS - 011 LVDS + Tumpion Zurac - 100 LVDS + Chrontel 7005 - 110 Chrontel 7005 - 315/330 series - 001 SiS30x (never seen) - 010 LVDS - 011 LVDS + Chrontel 7019 - 660 series [2:1] only: - reserved (chip type now in CR38) - All other combinations reserved - [3] 661 only: Pass 1:1 data - [4] LVDS: 0: Panel Link expands / 1: Panel Link does not expand - 30x: 0: Bridge scales / 1: Bridge does not scale = Panel scales (if possible) - [5] LCD polarity select - 0: VESA DMT Standard - 1: EDID 2.x defined - [6] LCD horizontal polarity select - 0: High active - 1: Low active - [7] LCD vertical polarity select - 0: High active - 1: Low active -*/ - -/* CR37: LCDInfo */ -#define LCDRGB18Bit 0x0001 -#define LCDNonExpanding 0x0010 -#define LCDSync 0x0020 -#define LCDPass11 0x0100 /* 0: center screen, 1: Pass 1:1 data */ -#define LCDDualLink 0x0200 - -#define DontExpandLCD LCDNonExpanding -#define LCDNonExpandingShift 4 -#define DontExpandLCDShift LCDNonExpandingShift -#define LCDSyncBit 0x00e0 -#define LCDSyncShift 6 - -/* CR38 (315 series) */ -#define EnableDualEdge 0x01 -#define SetToLCDA 0x02 /* LCD channel A (301C/302B/30x(E)LV and 650+LVDS only) */ -#define EnableCHScart 0x04 /* Scart on Ch7019 (unofficial definition - TW) */ -#define EnableCHYPbPr 0x08 /* YPbPr on Ch7019 (480i HDTV); only on 650/Ch7019 systems */ -#define EnableSiSYPbPr 0x08 /* Enable YPbPr mode (30xLV/301C only) */ -#define EnableYPbPr525i 0x00 /* Enable 525i YPbPr mode (30xLV/301C only) (mask 0x30) */ -#define EnableYPbPr525p 0x10 /* Enable 525p YPbPr mode (30xLV/301C only) (mask 0x30) */ -#define EnableYPbPr750p 0x20 /* Enable 750p YPbPr mode (30xLV/301C only) (mask 0x30) */ -#define EnableYPbPr1080i 0x30 /* Enable 1080i YPbPr mode (30xLV/301C only) (mask 0x30) */ -#define EnablePALM 0x40 /* 1 = Set PALM */ -#define EnablePALN 0x80 /* 1 = Set PALN */ -#define EnableNTSCJ EnablePALM /* Not BIOS */ - -/* CR38 (661 and later) - D[7:5] 000 No VB - 001 301 series VB - 010 LVDS - 011 Chrontel 7019 - 100 Conexant - D2 Enable YPbPr output (see CR35) - D[1:0] LCDA (like before) -*/ - -#define EnablePALMN 0x40 /* Romflag: 1 = Allow PALM/PALN */ - -/* CR39 (650 only) */ -#define LCDPass1_1 0x01 /* 0: center screen, 1: pass 1:1 data output */ -#define Enable302LV_DualLink 0x04 /* 302LV only; enable dual link */ - -/* CR39 (661 and later) - D[7] LVDS (SiS or third party) - D[1:0] YPbPr Aspect Ratio - 00 4:3 letterbox - 01 4:3 - 10 16:9 - 11 4:3 -*/ - -/* CR3B (651+301C) - D[1:0] YPbPr Aspect Ratio - ? -*/ - -/* CR79 (315/330 series only; not 661 and later) - [3-0] Notify driver - 0001 Mode Switch event (set by BIOS) - 0010 Epansion On/Off event - 0011 TV UnderScan/OverScan event - 0100 Set Brightness event - 0101 Set Contrast event - 0110 Set Mute event - 0111 Set Volume Up/Down event - [4] Enable Backlight Control by BIOS/driver - (set by driver; set means that the BIOS should - not touch the backlight registers because eg. - the driver already switched off the backlight) - [5] PAL/NTSC (set by BIOS) - [6] Expansion On/Off (set by BIOS; copied to CR32[4]) - [7] TV UnderScan/OverScan (set by BIOS) -*/ - -/* CR7C - 661 and later - [7] DualEdge enabled (or: to be enabled) - [6] CRT2 = TV/LCD/VGA enabled (or: to be enabled) - [5] Init done (set at end of SiS_Init) - {4] LVDS LCD capabilities - [3] LVDS LCD capabilities - [2] LVDS LCD capabilities (PWD) - [1] LVDS LCD capabilities (PWD) - [0] LVDS=1, TMDS=0 (SiS or third party) -*/ - -/* CR7E - 661 and later - VBType: - [7] LVDS (third party) - [3] 301C - [2] 302LV - [1] 301LV - [0] 301B -*/ - -/* LCDResInfo */ -#define Panel300_800x600 0x01 /* CR36 */ -#define Panel300_1024x768 0x02 -#define Panel300_1280x1024 0x03 -#define Panel300_1280x960 0x04 -#define Panel300_640x480 0x05 -#define Panel300_1024x600 0x06 -#define Panel300_1152x768 0x07 -#define Panel300_1280x768 0x0a -#define Panel300_Custom 0x0f -#define Panel300_Barco1366 0x10 - -#define Panel310_800x600 0x01 -#define Panel310_1024x768 0x02 -#define Panel310_1280x1024 0x03 -#define Panel310_640x480 0x04 -#define Panel310_1024x600 0x05 -#define Panel310_1152x864 0x06 -#define Panel310_1280x960 0x07 -#define Panel310_1152x768 0x08 /* LVDS only */ -#define Panel310_1400x1050 0x09 -#define Panel310_1280x768 0x0a -#define Panel310_1600x1200 0x0b -#define Panel310_320x240_2 0x0c /* xSTN */ -#define Panel310_320x240_3 0x0d /* xSTN */ -#define Panel310_320x240_1 0x0e /* xSTN - This is fake, can be any */ -#define Panel310_Custom 0x0f - -#define Panel661_800x600 0x01 -#define Panel661_1024x768 0x02 -#define Panel661_1280x1024 0x03 -#define Panel661_640x480 0x04 -#define Panel661_1024x600 0x05 -#define Panel661_1152x864 0x06 -#define Panel661_1280x960 0x07 -#define Panel661_1280x854 0x08 -#define Panel661_1400x1050 0x09 -#define Panel661_1280x768 0x0a -#define Panel661_1600x1200 0x0b -#define Panel661_1280x800 0x0c -#define Panel661_1680x1050 0x0d -#define Panel661_1280x720 0x0e -#define Panel661_Custom 0x0f - -#define Panel_800x600 0x01 /* Unified values */ -#define Panel_1024x768 0x02 /* MUST match BIOS values from 0-e */ -#define Panel_1280x1024 0x03 -#define Panel_640x480 0x04 -#define Panel_1024x600 0x05 -#define Panel_1152x864 0x06 -#define Panel_1280x960 0x07 -#define Panel_1152x768 0x08 /* LVDS only */ -#define Panel_1400x1050 0x09 -#define Panel_1280x768 0x0a /* 30xB/C and LVDS only (BIOS: all) */ -#define Panel_1600x1200 0x0b -#define Panel_1280x800 0x0c /* 661etc (TMDS) */ -#define Panel_1680x1050 0x0d /* 661etc */ -#define Panel_1280x720 0x0e /* 661etc */ -#define Panel_Custom 0x0f /* MUST BE 0x0f (for DVI DDC detection) */ -#define Panel_320x240_1 0x10 /* SiS 550 xSTN */ -#define Panel_Barco1366 0x11 -#define Panel_848x480 0x12 -#define Panel_320x240_2 0x13 /* SiS 550 xSTN */ -#define Panel_320x240_3 0x14 /* SiS 550 xSTN */ -#define Panel_1280x768_2 0x15 /* 30xLV */ -#define Panel_1280x768_3 0x16 /* (unused) */ -#define Panel_1280x800_2 0x17 /* 30xLV */ -#define Panel_856x480 0x18 -#define Panel_1280x854 0x19 /* 661etc */ - -/* Index in ModeResInfo table */ -#define SIS_RI_320x200 0 -#define SIS_RI_320x240 1 -#define SIS_RI_320x400 2 -#define SIS_RI_400x300 3 -#define SIS_RI_512x384 4 -#define SIS_RI_640x400 5 -#define SIS_RI_640x480 6 -#define SIS_RI_800x600 7 -#define SIS_RI_1024x768 8 -#define SIS_RI_1280x1024 9 -#define SIS_RI_1600x1200 10 -#define SIS_RI_1920x1440 11 -#define SIS_RI_2048x1536 12 -#define SIS_RI_720x480 13 -#define SIS_RI_720x576 14 -#define SIS_RI_1280x960 15 -#define SIS_RI_800x480 16 -#define SIS_RI_1024x576 17 -#define SIS_RI_1280x720 18 -#define SIS_RI_856x480 19 -#define SIS_RI_1280x768 20 -#define SIS_RI_1400x1050 21 -#define SIS_RI_1152x864 22 /* Up to here SiS conforming */ -#define SIS_RI_848x480 23 -#define SIS_RI_1360x768 24 -#define SIS_RI_1024x600 25 -#define SIS_RI_1152x768 26 -#define SIS_RI_768x576 27 -#define SIS_RI_1360x1024 28 -#define SIS_RI_1680x1050 29 -#define SIS_RI_1280x800 30 -#define SIS_RI_1920x1080 31 -#define SIS_RI_960x540 32 -#define SIS_RI_960x600 33 -#define SIS_RI_1280x854 34 - -/* CR5F */ -#define IsM650 0x80 - -/* Timing data */ -#define NTSCHT 1716 -#define NTSC2HT 1920 -#define NTSCVT 525 -#define PALHT 1728 -#define PALVT 625 -#define StHiTVHT 892 -#define StHiTVVT 1126 -#define StHiTextTVHT 1000 -#define StHiTextTVVT 1126 -#define ExtHiTVHT 2100 -#define ExtHiTVVT 1125 - -/* Indices in (VB)VCLKData tables */ - -#define VCLK28 0x00 /* Index in VCLKData table (300 and 315) */ -#define VCLK40 0x04 /* Index in VCLKData table (300 and 315) */ -#define VCLK65_300 0x09 /* Index in VCLKData table (300) */ -#define VCLK108_2_300 0x14 /* Index in VCLKData table (300) */ -#define VCLK81_300 0x3f /* Index in VCLKData table (300) */ -#define VCLK108_3_300 0x42 /* Index in VCLKData table (300) */ -#define VCLK100_300 0x43 /* Index in VCLKData table (300) */ -#define VCLK34_300 0x3d /* Index in VCLKData table (300) */ -#define VCLK_CUSTOM_300 0x47 - -#define VCLK65_315 0x0b /* Indices in (VB)VCLKData table (315) */ -#define VCLK108_2_315 0x19 -#define VCLK81_315 0x5b -#define VCLK162_315 0x5e -#define VCLK108_3_315 0x45 -#define VCLK100_315 0x46 -#define VCLK34_315 0x55 -#define VCLK68_315 0x0d -#define VCLK_1280x800_315_2 0x5c -#define VCLK121_315 0x5d -#define VCLK130_315 0x72 -#define VCLK_1280x720 0x5f -#define VCLK_1280x768_2 0x60 -#define VCLK_1280x768_3 0x61 /* (unused?) */ -#define VCLK_CUSTOM_315 0x62 -#define VCLK_1280x720_2 0x63 -#define VCLK_720x480 0x67 -#define VCLK_720x576 0x68 -#define VCLK_768x576 0x68 -#define VCLK_848x480 0x65 -#define VCLK_856x480 0x66 -#define VCLK_800x480 0x65 -#define VCLK_1024x576 0x51 -#define VCLK_1152x864 0x64 -#define VCLK_1360x768 0x58 -#define VCLK_1280x800_315 0x6c -#define VCLK_1280x854 0x76 - -#define TVCLKBASE_300 0x21 /* Indices on TV clocks in VCLKData table (300) */ -#define TVCLKBASE_315 0x3a /* Indices on TV clocks in (VB)VCLKData table (315) */ -#define TVVCLKDIV2 0x00 /* Index relative to TVCLKBASE */ -#define TVVCLK 0x01 /* Index relative to TVCLKBASE */ -#define HiTVVCLKDIV2 0x02 /* Index relative to TVCLKBASE */ -#define HiTVVCLK 0x03 /* Index relative to TVCLKBASE */ -#define HiTVSimuVCLK 0x04 /* Index relative to TVCLKBASE */ -#define HiTVTextVCLK 0x05 /* Index relative to TVCLKBASE */ -#define YPbPr750pVCLK 0x25 /* Index relative to TVCLKBASE; was 0x0f NOT relative */ - -/* ------------------------------ */ - -#define SetSCARTOutput 0x01 - -#define HotPlugFunction 0x08 - -#define StStructSize 0x06 - -#define SIS_VIDEO_CAPTURE 0x00 - 0x30 -#define SIS_VIDEO_PLAYBACK 0x02 - 0x30 -#define SIS_CRT2_PORT_04 0x04 - 0x30 -#define SIS_CRT2_PORT_10 0x10 - 0x30 -#define SIS_CRT2_PORT_12 0x12 - 0x30 -#define SIS_CRT2_PORT_14 0x14 - 0x30 - -#define ADR_CRT2PtrData 0x20E -#define offset_Zurac 0x210 /* TW: Trumpion Zurac data pointer */ -#define ADR_LVDSDesPtrData 0x212 -#define ADR_LVDSCRT1DataPtr 0x214 -#define ADR_CHTVVCLKPtr 0x216 -#define ADR_CHTVRegDataPtr 0x218 - -#define LCDDataLen 8 -#define HiTVDataLen 12 -#define TVDataLen 16 - -#define LVDSDataLen 6 -#define LVDSDesDataLen 3 -#define ActiveNonExpanding 0x40 -#define ActiveNonExpandingShift 6 -#define ActivePAL 0x20 -#define ActivePALShift 5 -#define ModeSwitchStatus 0x0F -#define SoftTVType 0x40 -#define SoftSettingAddr 0x52 -#define ModeSettingAddr 0x53 - -#define _PanelType00 0x00 -#define _PanelType01 0x08 -#define _PanelType02 0x10 -#define _PanelType03 0x18 -#define _PanelType04 0x20 -#define _PanelType05 0x28 -#define _PanelType06 0x30 -#define _PanelType07 0x38 -#define _PanelType08 0x40 -#define _PanelType09 0x48 -#define _PanelType0A 0x50 -#define _PanelType0B 0x58 -#define _PanelType0C 0x60 -#define _PanelType0D 0x68 -#define _PanelType0E 0x70 -#define _PanelType0F 0x78 - -#define PRIMARY_VGA 0 /* 1: SiS is primary vga 0:SiS is secondary vga */ - -#define BIOSIDCodeAddr 0x235 /* Offsets to ptrs in BIOS image */ -#define OEMUtilIDCodeAddr 0x237 -#define VBModeIDTableAddr 0x239 -#define OEMTVPtrAddr 0x241 -#define PhaseTableAddr 0x243 -#define NTSCFilterTableAddr 0x245 -#define PALFilterTableAddr 0x247 -#define OEMLCDPtr_1Addr 0x249 -#define OEMLCDPtr_2Addr 0x24B -#define LCDHPosTable_1Addr 0x24D -#define LCDHPosTable_2Addr 0x24F -#define LCDVPosTable_1Addr 0x251 -#define LCDVPosTable_2Addr 0x253 -#define OEMLCDPIDTableAddr 0x255 - -#define VBModeStructSize 5 -#define PhaseTableSize 4 -#define FilterTableSize 4 -#define LCDHPosTableSize 7 -#define LCDVPosTableSize 5 -#define OEMLVDSPIDTableSize 4 -#define LVDSHPosTableSize 4 -#define LVDSVPosTableSize 6 - -#define VB_ModeID 0 -#define VB_TVTableIndex 1 -#define VB_LCDTableIndex 2 -#define VB_LCDHIndex 3 -#define VB_LCDVIndex 4 - -#define OEMLCDEnable 0x0001 -#define OEMLCDDelayEnable 0x0002 -#define OEMLCDPOSEnable 0x0004 -#define OEMTVEnable 0x0100 -#define OEMTVDelayEnable 0x0200 -#define OEMTVFlickerEnable 0x0400 -#define OEMTVPhaseEnable 0x0800 -#define OEMTVFilterEnable 0x1000 - -#define OEMLCDPanelIDSupport 0x0080 - -/* - ============================================================= - for 315 series (old data layout) - ============================================================= -*/ -#define SoftDRAMType 0x80 -#define SoftSetting_OFFSET 0x52 -#define SR07_OFFSET 0x7C -#define SR15_OFFSET 0x7D -#define SR16_OFFSET 0x81 -#define SR17_OFFSET 0x85 -#define SR19_OFFSET 0x8D -#define SR1F_OFFSET 0x99 -#define SR21_OFFSET 0x9A -#define SR22_OFFSET 0x9B -#define SR23_OFFSET 0x9C -#define SR24_OFFSET 0x9D -#define SR25_OFFSET 0x9E -#define SR31_OFFSET 0x9F -#define SR32_OFFSET 0xA0 -#define SR33_OFFSET 0xA1 - -#define CR40_OFFSET 0xA2 -#define SR25_1_OFFSET 0xF6 -#define CR49_OFFSET 0xF7 - -#define VB310Data_1_2_Offset 0xB6 -#define VB310Data_4_D_Offset 0xB7 -#define VB310Data_4_E_Offset 0xB8 -#define VB310Data_4_10_Offset 0xBB - -#define RGBSenseDataOffset 0xBD -#define YCSenseDataOffset 0xBF -#define VideoSenseDataOffset 0xC1 -#define OutputSelectOffset 0xF3 - -#define ECLK_MCLK_DISTANCE 0x14 -#define VBIOSTablePointerStart 0x100 -#define StandTablePtrOffset VBIOSTablePointerStart+0x02 -#define EModeIDTablePtrOffset VBIOSTablePointerStart+0x04 -#define CRT1TablePtrOffset VBIOSTablePointerStart+0x06 -#define ScreenOffsetPtrOffset VBIOSTablePointerStart+0x08 -#define VCLKDataPtrOffset VBIOSTablePointerStart+0x0A -#define MCLKDataPtrOffset VBIOSTablePointerStart+0x0E -#define CRT2PtrDataPtrOffset VBIOSTablePointerStart+0x10 -#define TVAntiFlickPtrOffset VBIOSTablePointerStart+0x12 -#define TVDelayPtr1Offset VBIOSTablePointerStart+0x14 -#define TVPhaseIncrPtr1Offset VBIOSTablePointerStart+0x16 -#define TVYFilterPtr1Offset VBIOSTablePointerStart+0x18 -#define LCDDelayPtr1Offset VBIOSTablePointerStart+0x20 -#define TVEdgePtr1Offset VBIOSTablePointerStart+0x24 -#define CRT2Delay1Offset VBIOSTablePointerStart+0x28 - -#endif diff --git a/src/drivers/xgi/common/vb_def.h b/src/drivers/xgi/common/vb_def.h deleted file mode 100644 index 33efbc6cdf..0000000000 --- a/src/drivers/xgi/common/vb_def.h +++ /dev/null @@ -1,261 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* File taken from the Linux xgifb driver (v3.18.5) */ - -#ifndef _VB_DEF_ -#define _VB_DEF_ - -#define VB_XGI301C 0x0020 /* for 301C */ - -#define SupportCRT2in301C 0x0100 /* for 301C */ -#define SetCHTVOverScan 0x8000 - -#define Panel_320x480 0x07 /*fstn*/ -#define PanelResInfo 0x1F /* CR36 Panel Type/LCDResInfo */ -#define Panel_1024x768x75 0x22 -#define Panel_1280x1024x75 0x23 - -#define PanelRef60Hz 0x00 -#define PanelRef75Hz 0x20 - -#define YPbPr525iVCLK 0x03B -#define YPbPr525iVCLK_2 0x03A - -#define XGI_CRT2_PORT_00 (0x00 - 0x030) - -#define SupportAllCRT2 0x0078 -#define NoSupportTV 0x0070 -#define NoSupportHiVisionTV 0x0060 -#define NoSupportLCD 0x0058 - -/* -------------- SetMode Stack/Scratch */ -#define XGI_SetCRT2ToLCDA 0x0100 -#define SetCRT2ToDualEdge 0x8000 - -#define ReserveTVOption 0x0008 - -#define SetTVLowResolution 0x0400 -#define TVSimuMode 0x0800 -#define RPLLDIV2XO 0x1000 -#define NTSC1024x768 0x2000 -#define SetTVLockMode 0x4000 - -#define XGI_LCDVESATiming 0x0001 /* LCD Info/CR37 */ -#define XGI_EnableLVDSDDA 0x0002 -#define EnableScalingLCD 0x0008 -#define SetPWDEnable 0x0004 -#define SetLCDtoNonExpanding 0x0010 -#define SetLCDDualLink 0x0100 -#define SetLCDLowResolution 0x0200 - -/* LCD Capability shampoo */ -#define DefaultLCDCap 0x80ea -#define EnableLCD24bpp 0x0004 /* default */ -#define LCDPolarity 0x00c0 /* default: SyncNN */ -#define XGI_LCDDualLink 0x0100 -#define EnableSpectrum 0x0200 -#define PWDEnable 0x0400 -#define EnableVBCLKDRVLOW 0x4000 -#define EnablePLLSPLOW 0x8000 - -#define AVIDEOSense 0x01 /* CR32 */ -#define SVIDEOSense 0x02 -#define SCARTSense 0x04 -#define LCDSense 0x08 -#define Monitor2Sense 0x10 -#define Monitor1Sense 0x20 -#define HiTVSense 0x40 - -#define YPbPrSense 0x80 /* NEW SCRATCH */ - -#define TVSense 0xc7 - -#define YPbPrMode 0xe0 -#define YPbPrMode525i 0x00 -#define YPbPrMode525p 0x20 -#define YPbPrMode750p 0x40 -#define YPbPrMode1080i 0x60 - -#define ScalingLCD 0x08 - -#define SetYPbPr 0x04 - -/* ---------------------- VUMA Information */ -#define DisplayDeviceFromCMOS 0x10 - -/* ---------------------- HK Evnet Definition */ -#define XGI_ModeSwitchStatus 0xf0 -#define ActiveCRT1 0x10 -#define ActiveLCD 0x0020 -#define ActiveTV 0x40 -#define ActiveCRT2 0x80 - -#define ActiveAVideo 0x01 -#define ActiveSVideo 0x02 -#define ActiveSCART 0x04 -#define ActiveHiTV 0x08 -#define ActiveYPbPr 0x10 - -#define NTSC1024x768HT 1908 - -#define YPbPrTV525iHT 1716 /* YPbPr */ -#define YPbPrTV525iVT 525 -#define YPbPrTV525pHT 1716 -#define YPbPrTV525pVT 525 -#define YPbPrTV750pHT 1650 -#define YPbPrTV750pVT 750 - -#define VCLK25_175 0x00 -#define VCLK28_322 0x01 -#define VCLK31_5 0x02 -#define VCLK36 0x03 -#define VCLK43_163 0x05 -#define VCLK44_9 0x06 -#define VCLK49_5 0x07 -#define VCLK50 0x08 -#define VCLK52_406 0x09 -#define VCLK56_25 0x0A -#define VCLK68_179 0x0D -#define VCLK72_852 0x0E -#define VCLK75 0x0F -#define VCLK78_75 0x11 -#define VCLK79_411 0x12 -#define VCLK83_95 0x13 -#define VCLK86_6 0x15 -#define VCLK94_5 0x16 -#define VCLK113_309 0x1B -#define VCLK116_406 0x1C -#define VCLK135_5 0x1E -#define VCLK139_054 0x1F -#define VCLK157_5 0x20 -#define VCLK162 0x21 -#define VCLK175 0x22 -#define VCLK189 0x23 -#define VCLK202_5 0x25 -#define VCLK229_5 0x26 -#define VCLK234 0x27 -#define VCLK254_817 0x29 -#define VCLK266_952 0x2B -#define VCLK269_655 0x2C -#define VCLK277_015 0x2E -#define VCLK291_132 0x30 -#define VCLK291_766 0x31 -#define VCLK315_195 0x33 -#define VCLK323_586 0x34 -#define VCLK330_615 0x35 -#define VCLK340_477 0x37 -#define VCLK375_847 0x38 -#define VCLK388_631 0x39 -#define VCLK125_999 0x51 -#define VCLK148_5 0x52 -#define VCLK217_325 0x55 -#define XGI_YPbPr750pVCLK 0x57 - -#define VCLK39_77 0x40 -#define YPbPr525pVCLK 0x3A -#define NTSC1024VCLK 0x41 -#define VCLK35_2 0x49 /* ; 800x480 */ -#define VCLK122_61 0x4A -#define VCLK80_350 0x4B -#define VCLK107_385 0x4C - -#define RES320x200 0x00 -#define RES320x240 0x01 -#define RES400x300 0x02 -#define RES512x384 0x03 -#define RES640x400 0x04 -#define RES640x480x60 0x05 -#define RES640x480x72 0x06 -#define RES640x480x75 0x07 -#define RES640x480x85 0x08 -#define RES640x480x100 0x09 -#define RES640x480x120 0x0A -#define RES640x480x160 0x0B -#define RES640x480x200 0x0C -#define RES800x600x56 0x0D -#define RES800x600x60 0x0E -#define RES800x600x72 0x0F -#define RES800x600x75 0x10 -#define RES800x600x85 0x11 -#define RES800x600x100 0x12 -#define RES800x600x120 0x13 -#define RES800x600x160 0x14 -#define RES1024x768x43 0x15 -#define RES1024x768x60 0x16 -#define RES1024x768x70 0x17 -#define RES1024x768x75 0x18 -#define RES1024x768x85 0x19 -#define RES1024x768x100 0x1A -#define RES1024x768x120 0x1B -#define RES1280x1024x43 0x1C -#define RES1280x1024x60 0x1D -#define RES1280x1024x75 0x1E -#define RES1280x1024x85 0x1F -#define RES1600x1200x60 0x20 -#define RES1600x1200x65 0x21 -#define RES1600x1200x70 0x22 -#define RES1600x1200x75 0x23 -#define RES1600x1200x85 0x24 -#define RES1600x1200x100 0x25 -#define RES1600x1200x120 0x26 -#define RES1920x1440x60 0x27 -#define RES1920x1440x65 0x28 -#define RES1920x1440x70 0x29 -#define RES1920x1440x75 0x2A -#define RES1920x1440x85 0x2B -#define RES1920x1440x100 0x2C -#define RES2048x1536x60 0x2D -#define RES2048x1536x65 0x2E -#define RES2048x1536x70 0x2F -#define RES2048x1536x75 0x30 -#define RES2048x1536x85 0x31 -#define RES800x480x60 0x32 -#define RES800x480x75 0x33 -#define RES800x480x85 0x34 -#define RES1024x576x60 0x35 -#define RES1024x576x75 0x36 -#define RES1024x576x85 0x37 -#define RES1280x720x60 0x38 -#define RES1280x720x75 0x39 -#define RES1280x720x85 0x3A -#define RES1280x960x60 0x3B -#define RES720x480x60 0x3C -#define RES720x576x56 0x3D -#define RES856x480x79I 0x3E -#define RES856x480x60 0x3F -#define RES1280x768x60 0x40 -#define RES1400x1050x60 0x41 -#define RES1152x864x60 0x42 -#define RES1152x864x75 0x43 -#define RES1024x768x160 0x44 -#define RES1280x960x75 0x45 -#define RES1280x960x85 0x46 -#define RES1280x960x120 0x47 - - -#define XG27_CR8F 0x0C -#define XG27_SR36 0x30 -#define XG27_SR40 0x04 -#define XG27_SR41 0x00 -#define XG40_CRCF 0x13 -#define XGI330_CRT2Data_1_2 0 -#define XGI330_CRT2Data_4_D 0 -#define XGI330_CRT2Data_4_E 0 -#define XGI330_CRT2Data_4_10 0x80 -#define XGI330_SR07 0x18 -#define XGI330_SR1F 0 -#define XGI330_SR23 0xf6 -#define XGI330_SR24 0x0d -#define XGI330_SR31 0xc0 -#define XGI330_SR32 0x11 -#define XGI330_SR33 0 - -extern const struct XGI_ExtStruct XGI330_EModeIDTable[]; -extern const struct XGI_Ext2Struct XGI330_RefIndex[]; -extern const struct XGI_CRT1TableStruct XGI_CRT1Table[]; -extern const struct XGI_ECLKDataStruct XGI340_ECLKData[]; -extern const struct SiS_VCLKData XGI_VCLKData[]; -extern const unsigned char XGI340_CR6B[][4]; -extern const unsigned char XGI340_AGPReg[]; - -#endif diff --git a/src/drivers/xgi/common/vb_init.c b/src/drivers/xgi/common/vb_init.c deleted file mode 100644 index 19165db3bc..0000000000 --- a/src/drivers/xgi/common/vb_init.c +++ /dev/null @@ -1,1275 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* File taken from the Linux xgifb driver (v3.18.5) */ -/* coreboot related includes come indirectly from xgi_coreboot.h */ - -#include "xgi_coreboot.h" -#include "vstruct.h" -#include "XGIfb.h" -#include "vb_def.h" -#include "vb_util.h" -#include "vb_setmode.h" -#include "vb_init.h" - -static const unsigned short XGINew_DDRDRAM_TYPE340[4][2] = { - { 16, 0x45}, - { 8, 0x35}, - { 4, 0x31}, - { 2, 0x21} }; - -static const unsigned short XGINew_DDRDRAM_TYPE20[12][2] = { - { 128, 0x5D}, - { 64, 0x59}, - { 64, 0x4D}, - { 32, 0x55}, - { 32, 0x49}, - { 32, 0x3D}, - { 16, 0x51}, - { 16, 0x45}, - { 16, 0x39}, - { 8, 0x41}, - { 8, 0x35}, - { 4, 0x31} }; - -#define XGIFB_ROM_SIZE 65536 - -static unsigned char -XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension, - struct vb_device_info *pVBInfo) -{ - unsigned char data, temp; - - if (HwDeviceExtension->jChipType < XG20) { - data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02; - if (data == 0) - data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) & - 0x02) >> 1; - return data; - } else if (HwDeviceExtension->jChipType == XG27) { - temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B); - /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */ - if (((temp & 0x88) == 0x80) || ((temp & 0x88) == 0x08)) - data = 0; /* DDR */ - else - data = 1; /* DDRII */ - return data; - } else if (HwDeviceExtension->jChipType == XG21) { - /* Independent GPIO control */ - xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02); - udelay(800); - xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */ - /* GPIOF 0:DVI 1:DVO */ - data = xgifb_reg_get(pVBInfo->P3d4, 0x48); - /* HOTPLUG_SUPPORT */ - /* for current XG20 & XG21, GPIOH is floating, driver will - * fix DDR temporarily */ - /* DVI read GPIOH */ - data &= 0x01; /* 1=DDRII, 0=DDR */ - /* ~HOTPLUG_SUPPORT */ - xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02); - return data; - } - data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01; - - if (data == 1) - data++; - - return data; -} - -static void XGINew_DDR1x_MRS_340(unsigned long P3c4, - struct vb_device_info *pVBInfo) -{ - xgifb_reg_set(P3c4, 0x18, 0x01); - xgifb_reg_set(P3c4, 0x19, 0x20); - xgifb_reg_set(P3c4, 0x16, 0x00); - xgifb_reg_set(P3c4, 0x16, 0x80); - - mdelay(3); - xgifb_reg_set(P3c4, 0x18, 0x00); - xgifb_reg_set(P3c4, 0x19, 0x20); - xgifb_reg_set(P3c4, 0x16, 0x00); - xgifb_reg_set(P3c4, 0x16, 0x80); - - udelay(60); - xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */ - xgifb_reg_set(P3c4, 0x19, 0x01); - xgifb_reg_set(P3c4, 0x16, 0x03); - xgifb_reg_set(P3c4, 0x16, 0x83); - mdelay(1); - xgifb_reg_set(P3c4, 0x1B, 0x03); - udelay(500); - xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */ - xgifb_reg_set(P3c4, 0x19, 0x00); - xgifb_reg_set(P3c4, 0x16, 0x03); - xgifb_reg_set(P3c4, 0x16, 0x83); - xgifb_reg_set(P3c4, 0x1B, 0x00); -} - -static void XGINew_SetMemoryClock(struct vb_device_info *pVBInfo) -{ - xgifb_reg_set(pVBInfo->P3c4, - 0x28, - pVBInfo->MCLKData[pVBInfo->ram_type].SR28); - xgifb_reg_set(pVBInfo->P3c4, - 0x29, - pVBInfo->MCLKData[pVBInfo->ram_type].SR29); - xgifb_reg_set(pVBInfo->P3c4, - 0x2A, - pVBInfo->MCLKData[pVBInfo->ram_type].SR2A); - - xgifb_reg_set(pVBInfo->P3c4, - 0x2E, - XGI340_ECLKData[pVBInfo->ram_type].SR2E); - xgifb_reg_set(pVBInfo->P3c4, - 0x2F, - XGI340_ECLKData[pVBInfo->ram_type].SR2F); - xgifb_reg_set(pVBInfo->P3c4, - 0x30, - XGI340_ECLKData[pVBInfo->ram_type].SR30); -} - -static void XGINew_DDRII_Bootup_XG27( - struct xgi_hw_device_info *HwDeviceExtension, - unsigned long P3c4, struct vb_device_info *pVBInfo) -{ - unsigned long P3d4 = P3c4 + 0x10; - - pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo); - XGINew_SetMemoryClock(pVBInfo); - - /* Set Double Frequency */ - xgifb_reg_set(P3d4, 0x97, pVBInfo->XGINew_CR97); /* CR97 */ - - udelay(200); - - xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */ - xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */ - xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */ - udelay(15); - xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */ - udelay(15); - - xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */ - xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */ - xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */ - udelay(15); - xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */ - udelay(15); - - xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */ - xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */ - xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */ - udelay(30); - xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */ - udelay(15); - - xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */ - xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */ - xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */ - udelay(30); - xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */ - xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */ - - xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */ - udelay(60); - xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */ - - xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */ - xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */ - xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */ - - udelay(30); - xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */ - udelay(15); - - xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */ - xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */ - xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */ - udelay(30); - xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */ - udelay(15); - - xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */ - xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */ - xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */ - udelay(30); - xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */ - udelay(15); - - /* Set SR1B refresh control 000:close; 010:open */ - xgifb_reg_set(P3c4, 0x1B, 0x04); - udelay(200); - -} - -static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension, - unsigned long P3c4, struct vb_device_info *pVBInfo) -{ - unsigned long P3d4 = P3c4 + 0x10; - - pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo); - XGINew_SetMemoryClock(pVBInfo); - - xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */ - - udelay(200); - xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */ - xgifb_reg_set(P3c4, 0x19, 0x80); - xgifb_reg_set(P3c4, 0x16, 0x05); - xgifb_reg_set(P3c4, 0x16, 0x85); - - xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */ - xgifb_reg_set(P3c4, 0x19, 0xC0); - xgifb_reg_set(P3c4, 0x16, 0x05); - xgifb_reg_set(P3c4, 0x16, 0x85); - - xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */ - xgifb_reg_set(P3c4, 0x19, 0x40); - xgifb_reg_set(P3c4, 0x16, 0x05); - xgifb_reg_set(P3c4, 0x16, 0x85); - - xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */ - xgifb_reg_set(P3c4, 0x19, 0x02); - xgifb_reg_set(P3c4, 0x16, 0x05); - xgifb_reg_set(P3c4, 0x16, 0x85); - - udelay(15); - xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */ - udelay(30); - xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */ - udelay(100); - - xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */ - xgifb_reg_set(P3c4, 0x19, 0x00); - xgifb_reg_set(P3c4, 0x16, 0x05); - xgifb_reg_set(P3c4, 0x16, 0x85); - - udelay(200); -} - -static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, - struct vb_device_info *pVBInfo) -{ - xgifb_reg_set(P3c4, 0x18, 0x01); - xgifb_reg_set(P3c4, 0x19, 0x40); - xgifb_reg_set(P3c4, 0x16, 0x00); - xgifb_reg_set(P3c4, 0x16, 0x80); - udelay(60); - - xgifb_reg_set(P3c4, 0x18, 0x00); - xgifb_reg_set(P3c4, 0x19, 0x40); - xgifb_reg_set(P3c4, 0x16, 0x00); - xgifb_reg_set(P3c4, 0x16, 0x80); - udelay(60); - xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */ - xgifb_reg_set(P3c4, 0x19, 0x01); - xgifb_reg_set(P3c4, 0x16, 0x03); - xgifb_reg_set(P3c4, 0x16, 0x83); - mdelay(1); - xgifb_reg_set(P3c4, 0x1B, 0x03); - udelay(500); - xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */ - xgifb_reg_set(P3c4, 0x19, 0x00); - xgifb_reg_set(P3c4, 0x16, 0x03); - xgifb_reg_set(P3c4, 0x16, 0x83); - xgifb_reg_set(P3c4, 0x1B, 0x00); -} - -static void XGINew_DDR1x_DefaultRegister( - struct xgi_hw_device_info *HwDeviceExtension, - unsigned long Port, struct vb_device_info *pVBInfo) -{ - unsigned long P3d4 = Port, P3c4 = Port - 0x10; - - if (HwDeviceExtension->jChipType >= XG20) { - XGINew_SetMemoryClock(pVBInfo); - xgifb_reg_set(P3d4, - 0x82, - pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */ - xgifb_reg_set(P3d4, - 0x85, - pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */ - xgifb_reg_set(P3d4, - 0x86, - pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */ - - xgifb_reg_set(P3d4, 0x98, 0x01); - xgifb_reg_set(P3d4, 0x9A, 0x02); - - XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo); - } else { - XGINew_SetMemoryClock(pVBInfo); - - switch (HwDeviceExtension->jChipType) { - case XG42: - /* CR82 */ - xgifb_reg_set(P3d4, - 0x82, - pVBInfo->CR40[11][pVBInfo->ram_type]); - /* CR85 */ - xgifb_reg_set(P3d4, - 0x85, - pVBInfo->CR40[12][pVBInfo->ram_type]); - /* CR86 */ - xgifb_reg_set(P3d4, - 0x86, - pVBInfo->CR40[13][pVBInfo->ram_type]); - break; - default: - xgifb_reg_set(P3d4, 0x82, 0x88); - xgifb_reg_set(P3d4, 0x86, 0x00); - /* Insert read command for delay */ - xgifb_reg_get(P3d4, 0x86); - xgifb_reg_set(P3d4, 0x86, 0x88); - xgifb_reg_get(P3d4, 0x86); - xgifb_reg_set(P3d4, - 0x86, - pVBInfo->CR40[13][pVBInfo->ram_type]); - xgifb_reg_set(P3d4, 0x82, 0x77); - xgifb_reg_set(P3d4, 0x85, 0x00); - - /* Insert read command for delay */ - xgifb_reg_get(P3d4, 0x85); - xgifb_reg_set(P3d4, 0x85, 0x88); - - /* Insert read command for delay */ - xgifb_reg_get(P3d4, 0x85); - /* CR85 */ - xgifb_reg_set(P3d4, - 0x85, - pVBInfo->CR40[12][pVBInfo->ram_type]); - /* CR82 */ - xgifb_reg_set(P3d4, - 0x82, - pVBInfo->CR40[11][pVBInfo->ram_type]); - break; - } - - xgifb_reg_set(P3d4, 0x97, 0x00); - xgifb_reg_set(P3d4, 0x98, 0x01); - xgifb_reg_set(P3d4, 0x9A, 0x02); - XGINew_DDR1x_MRS_340(P3c4, pVBInfo); - } -} - -static void XGINew_DDR2_DefaultRegister( - struct xgi_hw_device_info *HwDeviceExtension, - unsigned long Port, struct vb_device_info *pVBInfo) -{ - unsigned long P3d4 = Port, P3c4 = Port - 0x10; - - /* keep following setting sequence, each setting in - * the same reg insert idle */ - xgifb_reg_set(P3d4, 0x82, 0x77); - xgifb_reg_set(P3d4, 0x86, 0x00); - xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */ - xgifb_reg_set(P3d4, 0x86, 0x88); - xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */ - /* CR86 */ - xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]); - xgifb_reg_set(P3d4, 0x82, 0x77); - xgifb_reg_set(P3d4, 0x85, 0x00); - xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */ - xgifb_reg_set(P3d4, 0x85, 0x88); - xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */ - xgifb_reg_set(P3d4, - 0x85, - pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */ - if (HwDeviceExtension->jChipType == XG27) - /* CR82 */ - xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]); - else - xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */ - - xgifb_reg_set(P3d4, 0x98, 0x01); - xgifb_reg_set(P3d4, 0x9A, 0x02); - if (HwDeviceExtension->jChipType == XG27) - XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo); - else - XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo); -} - -static void XGI_SetDRAM_Helper(unsigned long P3d4, u8 seed, u8 temp2, u8 reg, - u8 shift_factor, u8 mask1, u8 mask2) -{ - u8 j; - - for (j = 0; j < 4; j++) { - temp2 |= (((seed >> (2 * j)) & 0x03) << shift_factor); - xgifb_reg_set(P3d4, reg, temp2); - xgifb_reg_get(P3d4, reg); - temp2 &= mask1; - temp2 += mask2; - } -} - -static void XGINew_SetDRAMDefaultRegister340( - struct xgi_hw_device_info *HwDeviceExtension, - unsigned long Port, struct vb_device_info *pVBInfo) -{ - unsigned char temp, temp1, temp2, temp3, j, k; - - unsigned long P3d4 = Port, P3c4 = Port - 0x10; - - xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]); - xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]); - xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]); - xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]); - - /* CR6B DQS fine tune delay */ - temp = 0xaa; - XGI_SetDRAM_Helper(P3d4, temp, 0, 0x6B, 2, 0xF0, 0x10); - - /* CR6E DQM fine tune delay */ - XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6E, 2, 0xF0, 0x10); - - temp3 = 0; - for (k = 0; k < 4; k++) { - /* CR6E_D[1:0] select channel */ - xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3); - XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6F, 0, 0xF8, 0x08); - temp3 += 0x01; - } - - xgifb_reg_set(P3d4, - 0x80, - pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */ - xgifb_reg_set(P3d4, - 0x81, - pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */ - - temp2 = 0x80; - /* CR89 terminator type select */ - XGI_SetDRAM_Helper(P3d4, 0, temp2, 0x89, 0, 0xF0, 0x10); - - temp = 0; - temp1 = temp & 0x03; - temp2 |= temp1; - xgifb_reg_set(P3d4, 0x89, temp2); - - temp = pVBInfo->CR40[3][pVBInfo->ram_type]; - temp1 = temp & 0x0F; - temp2 = (temp >> 4) & 0x07; - temp3 = temp & 0x80; - xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */ - xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */ - xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */ - xgifb_reg_set(P3d4, - 0x41, - pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */ - - if (HwDeviceExtension->jChipType == XG27) - xgifb_reg_set(P3d4, 0x8F, XG27_CR8F); /* CR8F */ - - for (j = 0; j <= 6; j++) /* CR90 - CR96 */ - xgifb_reg_set(P3d4, (0x90 + j), - pVBInfo->CR40[14 + j][pVBInfo->ram_type]); - - for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */ - xgifb_reg_set(P3d4, (0xC3 + j), - pVBInfo->CR40[21 + j][pVBInfo->ram_type]); - - for (j = 0; j < 2; j++) /* CR8A - CR8B */ - xgifb_reg_set(P3d4, (0x8A + j), - pVBInfo->CR40[1 + j][pVBInfo->ram_type]); - - if (HwDeviceExtension->jChipType == XG42) - xgifb_reg_set(P3d4, 0x8C, 0x87); - - xgifb_reg_set(P3d4, - 0x59, - pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */ - - xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */ - xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */ - xgifb_reg_set(P3d4, 0xCF, XG40_CRCF); /* CRCF */ - if (pVBInfo->ram_type) { - xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */ - if (HwDeviceExtension->jChipType == XG27) - xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */ - - } else { - xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */ - } - xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */ - - temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo); - if (temp == 0) { - XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo); - } else { - xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */ - XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo); - } - xgifb_reg_set(P3c4, 0x1B, 0x03); /* SR1B */ -} - - -static unsigned short XGINew_SetDRAMSize20Reg( - unsigned short dram_size, - struct vb_device_info *pVBInfo) -{ - unsigned short data = 0, memsize = 0; - int RankSize; - unsigned char ChannelNo; - - RankSize = dram_size * pVBInfo->ram_bus / 8; - data = xgifb_reg_get(pVBInfo->P3c4, 0x13); - data &= 0x80; - - if (data == 0x80) - RankSize *= 2; - - data = 0; - - if (pVBInfo->ram_channel == 3) - ChannelNo = 4; - else - ChannelNo = pVBInfo->ram_channel; - - if (ChannelNo * RankSize <= 256) { - while ((RankSize >>= 1) > 0) - data += 0x10; - - memsize = data >> 4; - - /* Fix DRAM Sizing Error */ - xgifb_reg_set(pVBInfo->P3c4, - 0x14, - (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) | - (data & 0xF0)); - udelay(15); - } - return memsize; -} - -static int XGINew_ReadWriteRest(unsigned short StopAddr, - unsigned short StartAddr, struct vb_device_info *pVBInfo) -{ - int i; - unsigned long Position = 0; - void __iomem *fbaddr = pVBInfo->FBAddr; - - write32(fbaddr + Position, Position); - - for (i = StartAddr; i <= StopAddr; i++) { - Position = 1 << i; - write32(fbaddr + Position, Position); - } - - udelay(500); /* Fix #1759 Memory Size error in Multi-Adapter. */ - - Position = 0; - - if (read32(fbaddr + Position) != Position) - return 0; - - for (i = StartAddr; i <= StopAddr; i++) { - Position = 1 << i; - if (read32(fbaddr + Position) != Position) - return 0; - } - return 1; -} - -static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo) -{ - unsigned char data; - - data = xgifb_reg_get(pVBInfo->P3d4, 0x97); - - if ((data & 0x10) == 0) { - data = xgifb_reg_get(pVBInfo->P3c4, 0x39); - data = (data & 0x02) >> 1; - return data; - } - return data & 0x01; -} - -static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension, - struct vb_device_info *pVBInfo) -{ - unsigned char data; - - switch (HwDeviceExtension->jChipType) { - case XG20: - case XG21: - data = xgifb_reg_get(pVBInfo->P3d4, 0x97); - data = data & 0x01; - pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */ - - if (data == 0) { /* Single_32_16 */ - - if ((HwDeviceExtension->ulVideoMemorySize - 1) - > 0x1000000) { - - pVBInfo->ram_bus = 32; /* 32 bits */ - /* 22bit + 2 rank + 32bit */ - xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1); - xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52); - udelay(15); - - if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) - return; - - if ((HwDeviceExtension->ulVideoMemorySize - 1) > - 0x800000) { - /* 22bit + 1 rank + 32bit */ - xgifb_reg_set(pVBInfo->P3c4, - 0x13, - 0x31); - xgifb_reg_set(pVBInfo->P3c4, - 0x14, - 0x42); - udelay(15); - - if (XGINew_ReadWriteRest(23, - 23, - pVBInfo) == 1) - return; - } - } - - if ((HwDeviceExtension->ulVideoMemorySize - 1) > - 0x800000) { - pVBInfo->ram_bus = 16; /* 16 bits */ - /* 22bit + 2 rank + 16bit */ - xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1); - xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41); - udelay(15); - - if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1) - return; - xgifb_reg_set(pVBInfo->P3c4, - 0x13, - 0x31); - udelay(15); - } - - } else { /* Dual_16_8 */ - if ((HwDeviceExtension->ulVideoMemorySize - 1) > - 0x800000) { - pVBInfo->ram_bus = 16; /* 16 bits */ - /* (0x31:12x8x2) 22bit + 2 rank */ - xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1); - /* 0x41:16Mx16 bit*/ - xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41); - udelay(15); - - if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1) - return; - - if ((HwDeviceExtension->ulVideoMemorySize - 1) > - 0x400000) { - /* (0x31:12x8x2) 22bit + 1 rank */ - xgifb_reg_set(pVBInfo->P3c4, - 0x13, - 0x31); - /* 0x31:8Mx16 bit*/ - xgifb_reg_set(pVBInfo->P3c4, - 0x14, - 0x31); - udelay(15); - - if (XGINew_ReadWriteRest(22, - 22, - pVBInfo) == 1) - return; - } - } - - if ((HwDeviceExtension->ulVideoMemorySize - 1) > - 0x400000) { - pVBInfo->ram_bus = 8; /* 8 bits */ - /* (0x31:12x8x2) 22bit + 2 rank */ - xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1); - /* 0x30:8Mx8 bit*/ - xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30); - udelay(15); - - if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1) - return; - - /* (0x31:12x8x2) 22bit + 1 rank */ - xgifb_reg_set(pVBInfo->P3c4, - 0x13, - 0x31); - udelay(15); - } - } - break; - - case XG27: - pVBInfo->ram_bus = 16; /* 16 bits */ - pVBInfo->ram_channel = 1; /* Single channel */ - xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/ - break; - case XG42: - /* - XG42 SR14 D[3] Reserve - D[2] = 1, Dual Channel - = 0, Single Channel - - It's Different from Other XG40 Series. - */ - if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */ - pVBInfo->ram_bus = 32; /* 32 bits */ - pVBInfo->ram_channel = 2; /* 2 Channel */ - xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1); - xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44); - - if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) - return; - - xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21); - xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34); - if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1) - return; - - pVBInfo->ram_channel = 1; /* Single Channel */ - xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1); - xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40); - - if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1) - return; - xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21); - xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30); - } else { /* DDR */ - pVBInfo->ram_bus = 64; /* 64 bits */ - pVBInfo->ram_channel = 1; /* 1 channels */ - xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1); - xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52); - - if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) - return; - xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21); - xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42); - } - - break; - - default: /* XG40 */ - - if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */ - pVBInfo->ram_bus = 32; /* 32 bits */ - pVBInfo->ram_channel = 3; - xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1); - xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C); - - if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1) - return; - - pVBInfo->ram_channel = 2; /* 2 channels */ - xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48); - - if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) - return; - - xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21); - xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C); - - if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) { - pVBInfo->ram_channel = 3; /* 4 channels */ - } else { - pVBInfo->ram_channel = 2; /* 2 channels */ - xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38); - } - } else { /* DDR */ - pVBInfo->ram_bus = 64; /* 64 bits */ - pVBInfo->ram_channel = 2; /* 2 channels */ - xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1); - xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A); - - if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1) - return; - xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21); - xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A); - } - break; - } -} - -static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension, - struct vb_device_info *pVBInfo) -{ - u8 i, size; - unsigned short memsize, start_addr; - const unsigned short (*dram_table)[2]; - - xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */ - xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */ - XGINew_CheckChannel(HwDeviceExtension, pVBInfo); - - if (HwDeviceExtension->jChipType >= XG20) { - dram_table = XGINew_DDRDRAM_TYPE20; - size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE20); - start_addr = 5; - } else { - dram_table = XGINew_DDRDRAM_TYPE340; - size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE340); - start_addr = 9; - } - - for (i = 0; i < size; i++) { - /* SetDRAMSizingType */ - xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, dram_table[i][1]); - udelay(15); /* should delay 50 ns */ - - memsize = XGINew_SetDRAMSize20Reg(dram_table[i][0], pVBInfo); - - if (memsize == 0) - continue; - - memsize += (pVBInfo->ram_channel - 2) + 20; - if ((HwDeviceExtension->ulVideoMemorySize - 1) < - (unsigned long) (1 << memsize)) - continue; - - if (XGINew_ReadWriteRest(memsize, start_addr, pVBInfo) == 1) - return 1; - } - return 0; -} - -static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info, - struct xgi_hw_device_info *HwDeviceExtension, - struct vb_device_info *pVBInfo) -{ - unsigned short data; - - pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress; - - if (CONFIG(LINEAR_FRAMEBUFFER)) - XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e); - - data = xgifb_reg_get(pVBInfo->P3c4, 0x21); - /* disable read cache */ - xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF)); - XGI_DisplayOff(xgifb_info, HwDeviceExtension, pVBInfo); - - XGINew_DDRSizing340(HwDeviceExtension, pVBInfo); - data = xgifb_reg_get(pVBInfo->P3c4, 0x21); - /* enable read cache */ - xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20)); -} - -static void XGINew_ChkSenseStatus(struct vb_device_info *pVBInfo) -{ - unsigned short tempbx = 0, temp, tempcx, CR3CData; - - temp = xgifb_reg_get(pVBInfo->P3d4, 0x32); - - if (temp & Monitor1Sense) - tempbx |= ActiveCRT1; - if (temp & LCDSense) - tempbx |= ActiveLCD; - if (temp & Monitor2Sense) - tempbx |= ActiveCRT2; - if (temp & TVSense) { - tempbx |= ActiveTV; - if (temp & AVIDEOSense) - tempbx |= (ActiveAVideo << 8); - if (temp & SVIDEOSense) - tempbx |= (ActiveSVideo << 8); - if (temp & SCARTSense) - tempbx |= (ActiveSCART << 8); - if (temp & HiTVSense) - tempbx |= (ActiveHiTV << 8); - if (temp & YPbPrSense) - tempbx |= (ActiveYPbPr << 8); - } - - tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d); - tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8); - - if (tempbx & tempcx) { - CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c); - if (!(CR3CData & DisplayDeviceFromCMOS)) - tempcx = 0x1FF0; - } else { - tempcx = 0x1FF0; - } - - tempbx &= tempcx; - xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF)); - xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8)); -} - -static void XGINew_SetModeScratch(struct vb_device_info *pVBInfo) -{ - unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data; - - temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d); - temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8; - temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8; - - if (pVBInfo->IF_DEF_CRT2Monitor == 1) { - if (temp & ActiveCRT2) - tempcl = SetCRT2ToRAMDAC; - } - - if (temp & ActiveLCD) { - tempcl |= SetCRT2ToLCD; - if (temp & DriverMode) { - if (temp & ActiveTV) { - tempch = SetToLCDA | EnableDualEdge; - temp ^= SetCRT2ToLCD; - - if ((temp >> 8) & ActiveAVideo) - tempcl |= SetCRT2ToAVIDEO; - if ((temp >> 8) & ActiveSVideo) - tempcl |= SetCRT2ToSVIDEO; - if ((temp >> 8) & ActiveSCART) - tempcl |= SetCRT2ToSCART; - - if (pVBInfo->IF_DEF_HiVision == 1) { - if ((temp >> 8) & ActiveHiTV) - tempcl |= SetCRT2ToHiVision; - } - - if (pVBInfo->IF_DEF_YPbPr == 1) { - if ((temp >> 8) & ActiveYPbPr) - tempch |= SetYPbPr; - } - } - } - } else { - if ((temp >> 8) & ActiveAVideo) - tempcl |= SetCRT2ToAVIDEO; - if ((temp >> 8) & ActiveSVideo) - tempcl |= SetCRT2ToSVIDEO; - if ((temp >> 8) & ActiveSCART) - tempcl |= SetCRT2ToSCART; - - if (pVBInfo->IF_DEF_HiVision == 1) { - if ((temp >> 8) & ActiveHiTV) - tempcl |= SetCRT2ToHiVision; - } - - if (pVBInfo->IF_DEF_YPbPr == 1) { - if ((temp >> 8) & ActiveYPbPr) - tempch |= SetYPbPr; - } - } - - tempcl |= SetSimuScanMode; - if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV) - || (temp & ActiveCRT2))) - tempcl ^= (SetSimuScanMode | SwitchCRT2); - if ((temp & ActiveLCD) && (temp & ActiveTV)) - tempcl ^= (SetSimuScanMode | SwitchCRT2); - xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl); - - CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31); - CR31Data &= ~(SetNotSimuMode >> 8); - if (!(temp & ActiveCRT1)) - CR31Data |= (SetNotSimuMode >> 8); - CR31Data &= ~(DisableCRT2Display >> 8); - if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2))) - CR31Data |= (DisableCRT2Display >> 8); - xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data); - - CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38); - CR38Data &= ~SetYPbPr; - CR38Data |= tempch; - xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data); - -} - -static unsigned short XGINew_SenseLCD(struct xgi_hw_device_info - *HwDeviceExtension, - struct vb_device_info *pVBInfo) -{ - unsigned short temp = HwDeviceExtension->ulCRT2LCDType; - - switch (HwDeviceExtension->ulCRT2LCDType) { - case LCD_640x480: - case LCD_1024x600: - case LCD_1152x864: - case LCD_1280x960: - case LCD_1152x768: - case LCD_1920x1440: - case LCD_2048x1536: - temp = 0; /* overwrite used ulCRT2LCDType */ - break; - case LCD_UNKNOWN: /* unknown lcd, do nothing */ - return 0; - } - xgifb_reg_and_or(pVBInfo->P3d4, 0x36, 0xF0, temp); - return 1; -} - -static void XGINew_GetXG21Sense(struct pci_dev *pdev, - struct vb_device_info *pVBInfo) -{ - struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev); - unsigned char Temp; - - /* Enable GPIOA/B read */ - xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03); - Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0; - if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */ - XGINew_SenseLCD(&xgifb_info->hw_info, pVBInfo); - xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense); - /* Enable read GPIOF */ - xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20); - if (xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04) - Temp = 0xA0; /* Only DVO on chip */ - else - Temp = 0x80; /* TMDS on chip */ - xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, Temp); - /* Disable read GPIOF */ - xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20); - } -} - -static void XGINew_GetXG27Sense(struct vb_device_info *pVBInfo) -{ - unsigned char Temp, bCR4A; - - bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A); - /* Enable GPIOA/B/C read */ - xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07); - Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07; - xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A); - - if (Temp <= 0x02) { - /* LVDS setting */ - xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0); - xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21); - } else { - /* TMDS/DVO setting */ - xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0); - } - xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense); - -} - -static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo) -{ - unsigned char CR38, CR4A, temp; - - CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A); - /* enable GPIOE read */ - xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10); - CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38); - temp = 0; - if ((CR38 & 0xE0) > 0x80) { - temp = xgifb_reg_get(pVBInfo->P3d4, 0x48); - temp &= 0x08; - temp >>= 3; - } - - xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A); - - return temp; -} - -static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo) -{ - unsigned char CR4A, temp; - - CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A); - /* enable GPIOA/B/C read */ - xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03); - temp = xgifb_reg_get(pVBInfo->P3d4, 0x48); - if (temp > 2) - temp = ((temp & 0x04) >> 1) | ((~temp) & 0x01); - - xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A); - - return temp; -} - -static bool xgifb_bridge_is_on(struct vb_device_info *vb_info) -{ - u8 flag; - - flag = xgifb_reg_get(vb_info->Part4Port, 0x00); - return flag == 1 || flag == 2; -} - -unsigned char XGIInitNew(struct pci_dev *pdev) -{ - struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev); - struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info; - struct vb_device_info VBINF; - struct vb_device_info *pVBInfo = &VBINF; - unsigned char i, temp = 0, temp1; - - pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress; - - if (pVBInfo->FBAddr == NULL) { - dev_dbg(&pdev->dev, "pVBInfo->FBAddr == 0\n"); - return 0; - } - - XGIRegInit(pVBInfo, xgifb_info->vga_base); - - outb(0x67, pVBInfo->P3c2); - - InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo); - - /* Openkey */ - xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86); - - /* GetXG21Sense (GPIO) */ - if (HwDeviceExtension->jChipType == XG21) - XGINew_GetXG21Sense(pdev, pVBInfo); - - if (HwDeviceExtension->jChipType == XG27) - XGINew_GetXG27Sense(pVBInfo); - - /* Reset Extended register */ - - for (i = 0x06; i < 0x20; i++) - xgifb_reg_set(pVBInfo->P3c4, i, 0); - - for (i = 0x21; i <= 0x27; i++) - xgifb_reg_set(pVBInfo->P3c4, i, 0); - - for (i = 0x31; i <= 0x3B; i++) - xgifb_reg_set(pVBInfo->P3c4, i, 0); - - /* Auto over driver for XG42 */ - if (HwDeviceExtension->jChipType == XG42) - xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0); - - for (i = 0x79; i <= 0x7C; i++) - xgifb_reg_set(pVBInfo->P3d4, i, 0); - - if (HwDeviceExtension->jChipType >= XG20) - xgifb_reg_set(pVBInfo->P3d4, 0x97, pVBInfo->XGINew_CR97); - - /* SetDefExt1Regs begin */ - xgifb_reg_set(pVBInfo->P3c4, 0x07, XGI330_SR07); - if (HwDeviceExtension->jChipType == XG27) { - xgifb_reg_set(pVBInfo->P3c4, 0x40, XG27_SR40); - xgifb_reg_set(pVBInfo->P3c4, 0x41, XG27_SR41); - } - xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F); - xgifb_reg_set(pVBInfo->P3c4, 0x1F, XGI330_SR1F); - /* Frame buffer can read/write SR20 */ - xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0); - /* H/W request for slow corner chip */ - xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70); - if (HwDeviceExtension->jChipType == XG27) - xgifb_reg_set(pVBInfo->P3c4, 0x36, XG27_SR36); - - if (HwDeviceExtension->jChipType < XG20) { - u32 Temp; - - /* Set AGP customize registers (in SetDefAGPRegs) Start */ - for (i = 0x47; i <= 0x4C; i++) - xgifb_reg_set(pVBInfo->P3d4, - i, - XGI340_AGPReg[i - 0x47]); - - for (i = 0x70; i <= 0x71; i++) - xgifb_reg_set(pVBInfo->P3d4, - i, - XGI340_AGPReg[6 + i - 0x70]); - - for (i = 0x74; i <= 0x77; i++) - xgifb_reg_set(pVBInfo->P3d4, - i, - XGI340_AGPReg[8 + i - 0x74]); - - pci_read_config_dword(pdev, 0x50, &Temp); - Temp >>= 20; - Temp &= 0xF; - - if (Temp == 1) - xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */ - } /* != XG20 */ - - /* Set PCI */ - xgifb_reg_set(pVBInfo->P3c4, 0x23, XGI330_SR23); - xgifb_reg_set(pVBInfo->P3c4, 0x24, XGI330_SR24); - xgifb_reg_set(pVBInfo->P3c4, 0x25, 0); - - if (HwDeviceExtension->jChipType < XG20) { - /* Set VB */ - XGI_UnLockCRT2(pVBInfo); - /* disable VideoCapture */ - xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00); - xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00); - /* chk if BCLK>=100MHz */ - temp1 = xgifb_reg_get(pVBInfo->P3d4, 0x7B); - - xgifb_reg_set(pVBInfo->Part1Port, - 0x02, XGI330_CRT2Data_1_2); - - xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */ - } /* != XG20 */ - - xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F); - - if ((HwDeviceExtension->jChipType == XG42) && - XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) { - /* Not DDR */ - xgifb_reg_set(pVBInfo->P3c4, - 0x31, - (XGI330_SR31 & 0x3F) | 0x40); - xgifb_reg_set(pVBInfo->P3c4, - 0x32, - (XGI330_SR32 & 0xFC) | 0x01); - } else { - xgifb_reg_set(pVBInfo->P3c4, 0x31, XGI330_SR31); - xgifb_reg_set(pVBInfo->P3c4, 0x32, XGI330_SR32); - } - xgifb_reg_set(pVBInfo->P3c4, 0x33, XGI330_SR33); - - if (HwDeviceExtension->jChipType < XG20) { - if (xgifb_bridge_is_on(pVBInfo)) { - xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C); - xgifb_reg_set(pVBInfo->Part4Port, - 0x0D, XGI330_CRT2Data_4_D); - xgifb_reg_set(pVBInfo->Part4Port, - 0x0E, XGI330_CRT2Data_4_E); - xgifb_reg_set(pVBInfo->Part4Port, - 0x10, XGI330_CRT2Data_4_10); - xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F); - XGI_LockCRT2(pVBInfo); - } - } /* != XG20 */ - - XGI_SenseCRT1(pVBInfo); - - if (HwDeviceExtension->jChipType == XG21) { - - xgifb_reg_and_or(pVBInfo->P3d4, - 0x32, - ~Monitor1Sense, - Monitor1Sense); /* Z9 default has CRT */ - temp = GetXG21FPBits(pVBInfo); - xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp); - - } - if (HwDeviceExtension->jChipType == XG27) { - xgifb_reg_and_or(pVBInfo->P3d4, - 0x32, - ~Monitor1Sense, - Monitor1Sense); /* Z9 default has CRT */ - temp = GetXG27FPBits(pVBInfo); - xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp); - } - - pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo); - - XGINew_SetDRAMDefaultRegister340(HwDeviceExtension, - pVBInfo->P3d4, - pVBInfo); - - XGINew_SetDRAMSize_340(xgifb_info, HwDeviceExtension, pVBInfo); - - xgifb_reg_set(pVBInfo->P3c4, 0x22, 0xfa); - xgifb_reg_set(pVBInfo->P3c4, 0x21, 0xa3); - - XGINew_ChkSenseStatus(pVBInfo); - XGINew_SetModeScratch(pVBInfo); - - xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87); - - return 1; -} /* end of init */ diff --git a/src/drivers/xgi/common/vb_init.h b/src/drivers/xgi/common/vb_init.h deleted file mode 100644 index cf23abe407..0000000000 --- a/src/drivers/xgi/common/vb_init.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* File taken from the Linux xgifb driver (v3.18.5) */ - -#ifndef _VBINIT_ -#define _VBINIT_ -extern unsigned char XGIInitNew(struct pci_dev *pdev); -extern void XGIRegInit(struct vb_device_info *, unsigned long); -#endif diff --git a/src/drivers/xgi/common/vb_setmode.c b/src/drivers/xgi/common/vb_setmode.c deleted file mode 100644 index b8ab94b3a3..0000000000 --- a/src/drivers/xgi/common/vb_setmode.c +++ /dev/null @@ -1,5558 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* File taken from the Linux xgifb driver (v3.18.5) */ - -#include "xgi_coreboot.h" -#include "vstruct.h" -#include "XGIfb.h" -#include "vb_def.h" -#include "vb_init.h" -#include "vb_util.h" -#include "vb_table.h" -#include "vb_setmode.h" - -#define IndexMask 0xff -#define TVCLKBASE_315_25 (TVCLKBASE_315 + 25) - -static const unsigned short XGINew_VGA_DAC[] = { - 0x00, 0x10, 0x04, 0x14, 0x01, 0x11, 0x09, 0x15, - 0x2A, 0x3A, 0x2E, 0x3E, 0x2B, 0x3B, 0x2F, 0x3F, - 0x00, 0x05, 0x08, 0x0B, 0x0E, 0x11, 0x14, 0x18, - 0x1C, 0x20, 0x24, 0x28, 0x2D, 0x32, 0x38, 0x3F, - 0x00, 0x10, 0x1F, 0x2F, 0x3F, 0x1F, 0x27, 0x2F, - 0x37, 0x3F, 0x2D, 0x31, 0x36, 0x3A, 0x3F, 0x00, - 0x07, 0x0E, 0x15, 0x1C, 0x0E, 0x11, 0x15, 0x18, - 0x1C, 0x14, 0x16, 0x18, 0x1A, 0x1C, 0x00, 0x04, - 0x08, 0x0C, 0x10, 0x08, 0x0A, 0x0C, 0x0E, 0x10, - 0x0B, 0x0C, 0x0D, 0x0F, 0x10}; - -void InitTo330Pointer(unsigned char ChipType, struct vb_device_info *pVBInfo) -{ - pVBInfo->MCLKData = XGI340New_MCLKData; - - pVBInfo->LCDResInfo = 0; - pVBInfo->LCDTypeInfo = 0; - pVBInfo->LCDInfo = 0; - pVBInfo->VBInfo = 0; - pVBInfo->TVInfo = 0; - - pVBInfo->SR18 = XGI340_SR18; - pVBInfo->CR40 = XGI340_cr41; - - if (ChipType < XG20) - XGI_GetVBType(pVBInfo); - - /* 310 customization related */ - if ((pVBInfo->VBType & VB_SIS301LV) || (pVBInfo->VBType & VB_SIS302LV)) - pVBInfo->LCDCapList = XGI_LCDDLCapList; - else - pVBInfo->LCDCapList = XGI_LCDCapList; - - if (ChipType >= XG20) - pVBInfo->XGINew_CR97 = 0x10; - - if (ChipType == XG27) { - unsigned char temp; - - pVBInfo->MCLKData = XGI27New_MCLKData; - pVBInfo->CR40 = XGI27_cr41; - pVBInfo->XGINew_CR97 = 0xc1; - pVBInfo->SR18 = XG27_SR18; - - /*Z11m DDR*/ - temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B); - /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */ - if (((temp & 0x88) == 0x80) || ((temp & 0x88) == 0x08)) - pVBInfo->XGINew_CR97 = 0x80; - } - -} - -static void XGI_SetSeqRegs(struct vb_device_info *pVBInfo) -{ - unsigned char SRdata, i; - - xgifb_reg_set(pVBInfo->P3c4, 0x00, 0x03); /* Set SR0 */ - - for (i = 0; i < 4; i++) { - /* Get SR1,2,3,4 from file */ - /* SR1 is with screen off 0x20 */ - SRdata = XGI330_StandTable.SR[i]; - xgifb_reg_set(pVBInfo->P3c4, i+1, SRdata); /* Set SR 1 2 3 4 */ - } -} - -static void XGI_SetCRTCRegs(struct vb_device_info *pVBInfo) -{ - unsigned char CRTCdata; - unsigned short i; - - CRTCdata = xgifb_reg_get(pVBInfo->P3d4, 0x11); - CRTCdata &= 0x7f; - xgifb_reg_set(pVBInfo->P3d4, 0x11, CRTCdata); /* Unlock CRTC */ - - for (i = 0; i <= 0x18; i++) { - /* Get CRTC from file */ - CRTCdata = XGI330_StandTable.CRTC[i]; - xgifb_reg_set(pVBInfo->P3d4, i, CRTCdata); /* Set CRTC(3d4) */ - } -} - -static void XGI_SetATTRegs(unsigned short ModeIdIndex, - struct vb_device_info *pVBInfo) -{ - unsigned char ARdata; - unsigned short i, modeflag; - - modeflag = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeFlag; - - for (i = 0; i <= 0x13; i++) { - ARdata = XGI330_StandTable.ATTR[i]; - - if ((modeflag & Charx8Dot) && i == 0x13) { /* ifndef Dot9 */ - if (pVBInfo->VBInfo & XGI_SetCRT2ToLCDA) { - ARdata = 0; - } else if ((pVBInfo->VBInfo & - (SetCRT2ToTV | SetCRT2ToLCD)) && - (pVBInfo->VBInfo & SetInSlaveMode)) { - ARdata = 0; - } - } - - inb(pVBInfo->P3da); /* reset 3da */ - outb(i, pVBInfo->P3c0); /* set index */ - outb(ARdata, pVBInfo->P3c0); /* set data */ - } - - inb(pVBInfo->P3da); /* reset 3da */ - outb(0x14, pVBInfo->P3c0); /* set index */ - outb(0x00, pVBInfo->P3c0); /* set data */ - inb(pVBInfo->P3da); /* Enable Attribute */ - outb(0x20, pVBInfo->P3c0); -} - -static void XGI_SetGRCRegs(struct vb_device_info *pVBInfo) -{ - unsigned char GRdata; - unsigned short i; - - for (i = 0; i <= 0x08; i++) { - /* Get GR from file */ - GRdata = XGI330_StandTable.GRC[i]; - xgifb_reg_set(pVBInfo->P3ce, i, GRdata); /* Set GR(3ce) */ - } - - if (pVBInfo->ModeType > ModeVGA) { - GRdata = xgifb_reg_get(pVBInfo->P3ce, 0x05); - GRdata &= 0xBF; /* 256 color disable */ - xgifb_reg_set(pVBInfo->P3ce, 0x05, GRdata); - } -} - -static void XGI_ClearExt1Regs(struct vb_device_info *pVBInfo) -{ - unsigned short i; - - for (i = 0x0A; i <= 0x0E; i++) - xgifb_reg_set(pVBInfo->P3c4, i, 0x00); /* Clear SR0A-SR0E */ -} - -static unsigned char XGI_SetDefaultVCLK(struct vb_device_info *pVBInfo) -{ - - xgifb_reg_and_or(pVBInfo->P3c4, 0x31, ~0x30, 0x20); - xgifb_reg_set(pVBInfo->P3c4, 0x2B, XGI_VCLKData[0].SR2B); - xgifb_reg_set(pVBInfo->P3c4, 0x2C, XGI_VCLKData[0].SR2C); - - xgifb_reg_and_or(pVBInfo->P3c4, 0x31, ~0x30, 0x10); - xgifb_reg_set(pVBInfo->P3c4, 0x2B, XGI_VCLKData[1].SR2B); - xgifb_reg_set(pVBInfo->P3c4, 0x2C, XGI_VCLKData[1].SR2C); - - xgifb_reg_and(pVBInfo->P3c4, 0x31, ~0x30); - return 0; -} - -static unsigned char XGI_AjustCRT2Rate(unsigned short ModeIdIndex, - unsigned short RefreshRateTableIndex, unsigned short *i, - struct vb_device_info *pVBInfo) -{ - unsigned short tempax, tempbx, resinfo, modeflag, infoflag; - - modeflag = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeFlag; - resinfo = XGI330_EModeIDTable[ModeIdIndex].Ext_RESINFO; - tempbx = XGI330_RefIndex[RefreshRateTableIndex + (*i)].ModeID; - tempax = 0; - - if (pVBInfo->VBInfo & SetCRT2ToRAMDAC) { - tempax |= SupportRAMDAC2; - - if (pVBInfo->VBType & VB_XGI301C) - tempax |= SupportCRT2in301C; - } - - /* 301b */ - if (pVBInfo->VBInfo & (SetCRT2ToLCD | XGI_SetCRT2ToLCDA)) { - tempax |= SupportLCD; - - if (pVBInfo->LCDResInfo != Panel_1280x1024 && - pVBInfo->LCDResInfo != Panel_1280x960 && - (pVBInfo->LCDInfo & LCDNonExpanding) && - resinfo >= 9) - return 0; - } - - if (pVBInfo->VBInfo & SetCRT2ToHiVision) { /* for HiTV */ - tempax |= SupportHiVision; - if ((pVBInfo->VBInfo & SetInSlaveMode) && - ((resinfo == 4) || - (resinfo == 3 && (pVBInfo->SetFlag & TVSimuMode)) || - (resinfo > 7))) - return 0; - } else if (pVBInfo->VBInfo & (SetCRT2ToAVIDEO | SetCRT2ToSVIDEO | - SetCRT2ToSCART | SetCRT2ToYPbPr525750 | - SetCRT2ToHiVision)) { - tempax |= SupportTV; - - if (pVBInfo->VBType & (VB_SIS301B | VB_SIS302B | VB_SIS301LV | - VB_SIS302LV | VB_XGI301C)) - tempax |= SupportTV1024; - - if (!(pVBInfo->VBInfo & TVSetPAL) && - (modeflag & NoSupportSimuTV) && - (pVBInfo->VBInfo & SetInSlaveMode) && - (!(pVBInfo->VBInfo & SetNotSimuMode))) - return 0; - } - - for (; XGI330_RefIndex[RefreshRateTableIndex + (*i)].ModeID == - tempbx; (*i)--) { - infoflag = XGI330_RefIndex[RefreshRateTableIndex + (*i)]. - Ext_InfoFlag; - if (infoflag & tempax) - return 1; - - if ((*i) == 0) - break; - } - - for ((*i) = 0;; (*i)++) { - infoflag = XGI330_RefIndex[RefreshRateTableIndex + (*i)]. - Ext_InfoFlag; - if (XGI330_RefIndex[RefreshRateTableIndex + (*i)].ModeID - != tempbx) { - return 0; - } - - if (infoflag & tempax) - return 1; - } - return 1; -} - -static void XGI_SetSync(unsigned short RefreshRateTableIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short sync, temp; - - /* di+0x00 */ - sync = XGI330_RefIndex[RefreshRateTableIndex].Ext_InfoFlag >> 8; - sync &= 0xC0; - temp = 0x2F; - temp |= sync; - outb(temp, pVBInfo->P3c2); /* Set Misc(3c2) */ -} - -static void XGI_SetCRT1Timing_H(struct vb_device_info *pVBInfo, - struct xgi_hw_device_info *HwDeviceExtension) -{ - unsigned char data, data1, pushax; - unsigned short i, j; - - /* unlock cr0-7 */ - data = xgifb_reg_get(pVBInfo->P3d4, 0x11); - data &= 0x7F; - xgifb_reg_set(pVBInfo->P3d4, 0x11, data); - - data = pVBInfo->TimingH.data[0]; - xgifb_reg_set(pVBInfo->P3d4, 0, data); - - for (i = 0x01; i <= 0x04; i++) { - data = pVBInfo->TimingH.data[i]; - xgifb_reg_set(pVBInfo->P3d4, (unsigned short) (i + 1), data); - } - - for (i = 0x05; i <= 0x06; i++) { - data = pVBInfo->TimingH.data[i]; - xgifb_reg_set(pVBInfo->P3c4, (unsigned short) (i + 6), data); - } - - j = xgifb_reg_get(pVBInfo->P3c4, 0x0e); - j &= 0x1F; - data = pVBInfo->TimingH.data[7]; - data &= 0xE0; - data |= j; - xgifb_reg_set(pVBInfo->P3c4, 0x0e, data); - - if (HwDeviceExtension->jChipType >= XG20) { - data = xgifb_reg_get(pVBInfo->P3d4, 0x04); - data = data - 1; - xgifb_reg_set(pVBInfo->P3d4, 0x04, data); - data = xgifb_reg_get(pVBInfo->P3d4, 0x05); - data1 = data; - data1 &= 0xE0; - data &= 0x1F; - if (data == 0) { - pushax = data; - data = xgifb_reg_get(pVBInfo->P3c4, 0x0c); - data &= 0xFB; - xgifb_reg_set(pVBInfo->P3c4, 0x0c, data); - data = pushax; - } - data = data - 1; - data |= data1; - xgifb_reg_set(pVBInfo->P3d4, 0x05, data); - data = xgifb_reg_get(pVBInfo->P3c4, 0x0e); - data = data >> 5; - data = data + 3; - if (data > 7) - data = data - 7; - data = data << 5; - xgifb_reg_and_or(pVBInfo->P3c4, 0x0e, ~0xE0, data); - } -} - -static void XGI_SetCRT1Timing_V(unsigned short ModeIdIndex, - struct vb_device_info *pVBInfo) -{ - unsigned char data; - unsigned short i, j; - - for (i = 0x00; i <= 0x01; i++) { - data = pVBInfo->TimingV.data[i]; - xgifb_reg_set(pVBInfo->P3d4, (unsigned short) (i + 6), data); - } - - for (i = 0x02; i <= 0x03; i++) { - data = pVBInfo->TimingV.data[i]; - xgifb_reg_set(pVBInfo->P3d4, (unsigned short) (i + 0x0e), data); - } - - for (i = 0x04; i <= 0x05; i++) { - data = pVBInfo->TimingV.data[i]; - xgifb_reg_set(pVBInfo->P3d4, (unsigned short) (i + 0x11), data); - } - - j = xgifb_reg_get(pVBInfo->P3c4, 0x0a); - j &= 0xC0; - data = pVBInfo->TimingV.data[6]; - data &= 0x3F; - data |= j; - xgifb_reg_set(pVBInfo->P3c4, 0x0a, data); - - data = pVBInfo->TimingV.data[6]; - data &= 0x80; - data = data >> 2; - - i = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeFlag; - i &= DoubleScanMode; - if (i) - data |= 0x80; - - j = xgifb_reg_get(pVBInfo->P3d4, 0x09); - j &= 0x5F; - data |= j; - xgifb_reg_set(pVBInfo->P3d4, 0x09, data); -} - -static void XGI_SetCRT1CRTC(unsigned short ModeIdIndex, - unsigned short RefreshRateTableIndex, - struct vb_device_info *pVBInfo, - struct xgi_hw_device_info *HwDeviceExtension) -{ - unsigned char index, data; - unsigned short i; - - /* Get index */ - index = XGI330_RefIndex[RefreshRateTableIndex].Ext_CRT1CRTC; - index = index & IndexMask; - - data = xgifb_reg_get(pVBInfo->P3d4, 0x11); - data &= 0x7F; - xgifb_reg_set(pVBInfo->P3d4, 0x11, data); /* Unlock CRTC */ - - for (i = 0; i < 8; i++) - pVBInfo->TimingH.data[i] - = XGI_CRT1Table[index].CR[i]; - - for (i = 0; i < 7; i++) - pVBInfo->TimingV.data[i] - = XGI_CRT1Table[index].CR[i + 8]; - - XGI_SetCRT1Timing_H(pVBInfo, HwDeviceExtension); - - XGI_SetCRT1Timing_V(ModeIdIndex, pVBInfo); - - if (pVBInfo->ModeType > 0x03) - xgifb_reg_set(pVBInfo->P3d4, 0x14, 0x4F); -} - -/* --------------------------------------------------------------------- */ -/* Function : XGI_SetXG21CRTC */ -/* Input : Stand or enhance CRTC table */ -/* Output : Fill CRT Hsync/Vsync to SR2E/SR2F/SR30/SR33/SR34/SR3F */ -/* Description : Set LCD timing */ -/* --------------------------------------------------------------------- */ -static void XGI_SetXG21CRTC(unsigned short RefreshRateTableIndex, - struct vb_device_info *pVBInfo) -{ - unsigned char index, Tempax, Tempbx, Tempcx, Tempdx; - unsigned short Temp1, Temp2, Temp3; - - index = XGI330_RefIndex[RefreshRateTableIndex].Ext_CRT1CRTC; - /* Tempax: CR4 HRS */ - Tempax = XGI_CRT1Table[index].CR[3]; - Tempcx = Tempax; /* Tempcx: HRS */ - /* SR2E[7:0]->HRS */ - xgifb_reg_set(pVBInfo->P3c4, 0x2E, Tempax); - - Tempdx = XGI_CRT1Table[index].CR[5]; /* SRB */ - Tempdx &= 0xC0; /* Tempdx[7:6]: SRB[7:6] */ - Temp1 = Tempdx; /* Temp1[7:6]: HRS[9:8] */ - Temp1 <<= 2; /* Temp1[9:8]: HRS[9:8] */ - Temp1 |= Tempax; /* Temp1[9:0]: HRS[9:0] */ - - Tempax = XGI_CRT1Table[index].CR[4]; /* CR5 HRE */ - Tempax &= 0x1F; /* Tempax[4:0]: HRE[4:0] */ - - Tempbx = XGI_CRT1Table[index].CR[6]; /* SRC */ - Tempbx &= 0x04; /* Tempbx[2]: HRE[5] */ - Tempbx <<= 3; /* Tempbx[5]: HRE[5] */ - Tempax |= Tempbx; /* Tempax[5:0]: HRE[5:0] */ - - Temp2 = Temp1 & 0x3C0; /* Temp2[9:6]: HRS[9:6] */ - Temp2 |= Tempax; /* Temp2[9:0]: HRE[9:0] */ - - Tempcx &= 0x3F; /* Tempcx[5:0]: HRS[5:0] */ - if (Tempax < Tempcx) /* HRE < HRS */ - Temp2 |= 0x40; /* Temp2 + 0x40 */ - - Temp2 &= 0xFF; - Tempax = (unsigned char) Temp2; /* Tempax: HRE[7:0] */ - Tempax <<= 2; /* Tempax[7:2]: HRE[5:0] */ - Tempdx >>= 6; /* Tempdx[7:6]->[1:0] HRS[9:8] */ - Tempax |= Tempdx; /* HRE[5:0]HRS[9:8] */ - /* SR2F D[7:2]->HRE, D[1:0]->HRS */ - xgifb_reg_set(pVBInfo->P3c4, 0x2F, Tempax); - xgifb_reg_and_or(pVBInfo->P3c4, 0x30, 0xE3, 00); - - /* CR10 VRS */ - Tempax = XGI_CRT1Table[index].CR[10]; - Tempbx = Tempax; /* Tempbx: VRS */ - Tempax &= 0x01; /* Tempax[0]: VRS[0] */ - xgifb_reg_or(pVBInfo->P3c4, 0x33, Tempax); /* SR33[0]->VRS[0] */ - /* CR7[2][7] VRE */ - Tempax = XGI_CRT1Table[index].CR[9]; - Tempcx = Tempbx >> 1; /* Tempcx[6:0]: VRS[7:1] */ - Tempdx = Tempax & 0x04; /* Tempdx[2]: CR7[2] */ - Tempdx <<= 5; /* Tempdx[7]: VRS[8] */ - Tempcx |= Tempdx; /* Tempcx[7:0]: VRS[8:1] */ - xgifb_reg_set(pVBInfo->P3c4, 0x34, Tempcx); /* SR34[8:1]->VRS */ - - Temp1 = Tempdx; /* Temp1[7]: Tempdx[7] */ - Temp1 <<= 1; /* Temp1[8]: VRS[8] */ - Temp1 |= Tempbx; /* Temp1[8:0]: VRS[8:0] */ - Tempax &= 0x80; - Temp2 = Tempax << 2; /* Temp2[9]: VRS[9] */ - Temp1 |= Temp2; /* Temp1[9:0]: VRS[9:0] */ - /* Tempax: SRA */ - Tempax = XGI_CRT1Table[index].CR[14]; - Tempax &= 0x08; /* Tempax[3]: VRS[3] */ - Temp2 = Tempax; - Temp2 <<= 7; /* Temp2[10]: VRS[10] */ - Temp1 |= Temp2; /* Temp1[10:0]: VRS[10:0] */ - - /* Tempax: CR11 VRE */ - Tempax = XGI_CRT1Table[index].CR[11]; - Tempax &= 0x0F; /* Tempax[3:0]: VRE[3:0] */ - /* Tempbx: SRA */ - Tempbx = XGI_CRT1Table[index].CR[14]; - Tempbx &= 0x20; /* Tempbx[5]: VRE[5] */ - Tempbx >>= 1; /* Tempbx[4]: VRE[4] */ - Tempax |= Tempbx; /* Tempax[4:0]: VRE[4:0] */ - Temp2 = Temp1 & 0x7E0; /* Temp2[10:5]: VRS[10:5] */ - Temp2 |= Tempax; /* Temp2[10:5]: VRE[10:5] */ - - Temp3 = Temp1 & 0x1F; /* Temp3[4:0]: VRS[4:0] */ - if (Tempax < Temp3) /* VRE < VRS */ - Temp2 |= 0x20; /* VRE + 0x20 */ - - Temp2 &= 0xFF; - Tempax = (unsigned char) Temp2; /* Tempax: VRE[7:0] */ - Tempax <<= 2; /* Tempax[7:0]; VRE[5:0]00 */ - Temp1 &= 0x600; /* Temp1[10:9]: VRS[10:9] */ - Temp1 >>= 9; /* Temp1[1:0]: VRS[10:9] */ - Tempbx = (unsigned char) Temp1; - Tempax |= Tempbx; /* Tempax[7:0]: VRE[5:0]VRS[10:9] */ - Tempax &= 0x7F; - /* SR3F D[7:2]->VRE D[1:0]->VRS */ - xgifb_reg_set(pVBInfo->P3c4, 0x3F, Tempax); -} - -static void XGI_SetXG27CRTC(unsigned short RefreshRateTableIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short index, Tempax, Tempbx, Tempcx; - - index = XGI330_RefIndex[RefreshRateTableIndex].Ext_CRT1CRTC; - /* Tempax: CR4 HRS */ - Tempax = XGI_CRT1Table[index].CR[3]; - Tempbx = Tempax; /* Tempbx: HRS[7:0] */ - /* SR2E[7:0]->HRS */ - xgifb_reg_set(pVBInfo->P3c4, 0x2E, Tempax); - - /* SR0B */ - Tempax = XGI_CRT1Table[index].CR[5]; - Tempax &= 0xC0; /* Tempax[7:6]: SR0B[7:6]: HRS[9:8]*/ - Tempbx |= (Tempax << 2); /* Tempbx: HRS[9:0] */ - - Tempax = XGI_CRT1Table[index].CR[4]; /* CR5 HRE */ - Tempax &= 0x1F; /* Tempax[4:0]: HRE[4:0] */ - Tempcx = Tempax; /* Tempcx: HRE[4:0] */ - - Tempax = XGI_CRT1Table[index].CR[6]; /* SRC */ - Tempax &= 0x04; /* Tempax[2]: HRE[5] */ - Tempax <<= 3; /* Tempax[5]: HRE[5] */ - Tempcx |= Tempax; /* Tempcx[5:0]: HRE[5:0] */ - - Tempbx = Tempbx & 0x3C0; /* Tempbx[9:6]: HRS[9:6] */ - Tempbx |= Tempcx; /* Tempbx: HRS[9:6]HRE[5:0] */ - - /* Tempax: CR4 HRS */ - Tempax = XGI_CRT1Table[index].CR[3]; - Tempax &= 0x3F; /* Tempax: HRS[5:0] */ - if (Tempcx <= Tempax) /* HRE[5:0] < HRS[5:0] */ - Tempbx += 0x40; /* Tempbx= Tempbx + 0x40 : HRE[9:0]*/ - - Tempax = XGI_CRT1Table[index].CR[5]; /* SR0B */ - Tempax &= 0xC0; /* Tempax[7:6]: SR0B[7:6]: HRS[9:8]*/ - Tempax >>= 6; /* Tempax[1:0]: HRS[9:8]*/ - Tempax |= ((Tempbx << 2) & 0xFF); /* Tempax[7:2]: HRE[5:0] */ - /* SR2F [7:2][1:0]: HRE[5:0]HRS[9:8] */ - xgifb_reg_set(pVBInfo->P3c4, 0x2F, Tempax); - xgifb_reg_and_or(pVBInfo->P3c4, 0x30, 0xE3, 00); - - /* CR10 VRS */ - Tempax = XGI_CRT1Table[index].CR[10]; - /* SR34[7:0]->VRS[7:0] */ - xgifb_reg_set(pVBInfo->P3c4, 0x34, Tempax); - - Tempcx = Tempax; /* Tempcx <= VRS[7:0] */ - /* CR7[7][2] VRS[9][8] */ - Tempax = XGI_CRT1Table[index].CR[9]; - Tempbx = Tempax; /* Tempbx <= CR07[7:0] */ - Tempax = Tempax & 0x04; /* Tempax[2]: CR7[2]: VRS[8] */ - Tempax >>= 2; /* Tempax[0]: VRS[8] */ - /* SR35[0]: VRS[8] */ - xgifb_reg_and_or(pVBInfo->P3c4, 0x35, ~0x01, Tempax); - Tempcx |= (Tempax << 8); /* Tempcx <= VRS[8:0] */ - Tempcx |= ((Tempbx & 0x80) << 2); /* Tempcx <= VRS[9:0] */ - /* Tempax: SR0A */ - Tempax = XGI_CRT1Table[index].CR[14]; - Tempax &= 0x08; /* SR0A[3] VRS[10] */ - Tempcx |= (Tempax << 7); /* Tempcx <= VRS[10:0] */ - - /* Tempax: CR11 VRE */ - Tempax = XGI_CRT1Table[index].CR[11]; - Tempax &= 0x0F; /* Tempax[3:0]: VRE[3:0] */ - /* Tempbx: SR0A */ - Tempbx = XGI_CRT1Table[index].CR[14]; - Tempbx &= 0x20; /* Tempbx[5]: SR0A[5]: VRE[4] */ - Tempbx >>= 1; /* Tempbx[4]: VRE[4] */ - Tempax |= Tempbx; /* Tempax[4:0]: VRE[4:0] */ - Tempbx = Tempcx; /* Tempbx: VRS[10:0] */ - Tempbx &= 0x7E0; /* Tempbx[10:5]: VRS[10:5] */ - Tempbx |= Tempax; /* Tempbx: VRS[10:5]VRE[4:0] */ - - if (Tempbx <= Tempcx) /* VRE <= VRS */ - Tempbx |= 0x20; /* VRE + 0x20 */ - - /* Tempax: Tempax[7:0]; VRE[5:0]00 */ - Tempax = (Tempbx << 2) & 0xFF; - /* SR3F[7:2]:VRE[5:0] */ - xgifb_reg_and_or(pVBInfo->P3c4, 0x3F, ~0xFC, Tempax); - Tempax = Tempcx >> 8; - /* SR35[2:0]:VRS[10:8] */ - xgifb_reg_and_or(pVBInfo->P3c4, 0x35, ~0x07, Tempax); -} - -static void XGI_SetXG27FPBits(struct vb_device_info *pVBInfo) -{ - unsigned char temp; - - /* D[1:0] 01: 18bit, 00: dual 12, 10: single 24 */ - temp = xgifb_reg_get(pVBInfo->P3d4, 0x37); - temp = (temp & 3) << 6; - /* SR06[7]0: dual 12/1: single 24 [6] 18bit Dither <= 0 h/w recommend */ - xgifb_reg_and_or(pVBInfo->P3c4, 0x06, ~0xc0, temp & 0x80); - /* SR09[7] enable FP output, SR09[6] 1: sigle 18bits, 0: 24bits */ - xgifb_reg_and_or(pVBInfo->P3c4, 0x09, ~0xc0, temp | 0x80); - -} - -static void xgifb_set_lcd(int chip_id, - struct vb_device_info *pVBInfo, - unsigned short RefreshRateTableIndex) -{ - unsigned short temp; - - xgifb_reg_set(pVBInfo->P3d4, 0x2E, 0x00); - xgifb_reg_set(pVBInfo->P3d4, 0x2F, 0x00); - xgifb_reg_set(pVBInfo->P3d4, 0x46, 0x00); - xgifb_reg_set(pVBInfo->P3d4, 0x47, 0x00); - - if (chip_id == XG27) { - temp = xgifb_reg_get(pVBInfo->P3d4, 0x37); - if ((temp & 0x03) == 0) { /* dual 12 */ - xgifb_reg_set(pVBInfo->P3d4, 0x46, 0x13); - xgifb_reg_set(pVBInfo->P3d4, 0x47, 0x13); - } - } - - if (chip_id == XG27) { - XGI_SetXG27FPBits(pVBInfo); - } else { - temp = xgifb_reg_get(pVBInfo->P3d4, 0x37); - if (temp & 0x01) { - /* 18 bits FP */ - xgifb_reg_or(pVBInfo->P3c4, 0x06, 0x40); - xgifb_reg_or(pVBInfo->P3c4, 0x09, 0x40); - } - } - - xgifb_reg_or(pVBInfo->P3c4, 0x1E, 0x01); /* Negative blank polarity */ - - xgifb_reg_and(pVBInfo->P3c4, 0x30, ~0x20); /* Hsync polarity */ - xgifb_reg_and(pVBInfo->P3c4, 0x35, ~0x80); /* Vsync polarity */ - - temp = XGI330_RefIndex[RefreshRateTableIndex].Ext_InfoFlag; - if (temp & 0x4000) - /* Hsync polarity */ - xgifb_reg_or(pVBInfo->P3c4, 0x30, 0x20); - if (temp & 0x8000) - /* Vsync polarity */ - xgifb_reg_or(pVBInfo->P3c4, 0x35, 0x80); -} - -/* --------------------------------------------------------------------- */ -/* Function : XGI_UpdateXG21CRTC */ -/* Input : */ -/* Output : CRT1 CRTC */ -/* Description : Modify CRT1 Hsync/Vsync to fix LCD mode timing */ -/* --------------------------------------------------------------------- */ -static void XGI_UpdateXG21CRTC(unsigned short ModeNo, - struct vb_device_info *pVBInfo, - unsigned short RefreshRateTableIndex) -{ - int index = -1; - - xgifb_reg_and(pVBInfo->P3d4, 0x11, 0x7F); /* Unlock CR0~7 */ - if (ModeNo == 0x2E && - (XGI330_RefIndex[RefreshRateTableIndex].Ext_CRT1CRTC == - RES640x480x60)) - index = 12; - else if (ModeNo == 0x2E && (XGI330_RefIndex[RefreshRateTableIndex]. - Ext_CRT1CRTC == RES640x480x72)) - index = 13; - else if (ModeNo == 0x2F) - index = 14; - else if (ModeNo == 0x50) - index = 15; - else if (ModeNo == 0x59) - index = 16; - - if (index != -1) { - xgifb_reg_set(pVBInfo->P3d4, 0x02, - XGI_UpdateCRT1Table[index].CR02); - xgifb_reg_set(pVBInfo->P3d4, 0x03, - XGI_UpdateCRT1Table[index].CR03); - xgifb_reg_set(pVBInfo->P3d4, 0x15, - XGI_UpdateCRT1Table[index].CR15); - xgifb_reg_set(pVBInfo->P3d4, 0x16, - XGI_UpdateCRT1Table[index].CR16); - } -} - -static void XGI_SetCRT1DE(unsigned short ModeIdIndex, - unsigned short RefreshRateTableIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short resindex, tempax, tempbx, tempcx, temp, modeflag; - - unsigned char data; - - resindex = XGI330_EModeIDTable[ModeIdIndex].Ext_RESINFO; - - modeflag = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeFlag; - tempax = XGI330_ModeResInfo[resindex].HTotal; - tempbx = XGI330_ModeResInfo[resindex].VTotal; - - if (modeflag & HalfDCLK) - tempax = tempax >> 1; - - if (modeflag & HalfDCLK) - tempax = tempax << 1; - - temp = XGI330_RefIndex[RefreshRateTableIndex].Ext_InfoFlag; - - if (temp & InterlaceMode) - tempbx = tempbx >> 1; - - if (modeflag & DoubleScanMode) - tempbx = tempbx << 1; - - tempcx = 8; - - tempax /= tempcx; - tempax -= 1; - tempbx -= 1; - tempcx = tempax; - temp = xgifb_reg_get(pVBInfo->P3d4, 0x11); - data = xgifb_reg_get(pVBInfo->P3d4, 0x11); - data &= 0x7F; - xgifb_reg_set(pVBInfo->P3d4, 0x11, data); /* Unlock CRTC */ - xgifb_reg_set(pVBInfo->P3d4, 0x01, (unsigned short) (tempcx & 0xff)); - xgifb_reg_and_or(pVBInfo->P3d4, 0x0b, ~0x0c, - (unsigned short) ((tempcx & 0x0ff00) >> 10)); - xgifb_reg_set(pVBInfo->P3d4, 0x12, (unsigned short) (tempbx & 0xff)); - tempax = 0; - tempbx = tempbx >> 8; - - if (tempbx & 0x01) - tempax |= 0x02; - - if (tempbx & 0x02) - tempax |= 0x40; - - xgifb_reg_and_or(pVBInfo->P3d4, 0x07, ~0x42, tempax); - data = xgifb_reg_get(pVBInfo->P3d4, 0x07); - tempax = 0; - - if (tempbx & 0x04) - tempax |= 0x02; - - xgifb_reg_and_or(pVBInfo->P3d4, 0x0a, ~0x02, tempax); - xgifb_reg_set(pVBInfo->P3d4, 0x11, temp); -} - -static void XGI_SetCRT1Offset(unsigned short ModeNo, - unsigned short ModeIdIndex, - unsigned short RefreshRateTableIndex, - struct xgi_hw_device_info *HwDeviceExtension, - struct vb_device_info *pVBInfo) -{ - unsigned short temp, ah, al, temp2, i, DisplayUnit; - - /* GetOffset */ - temp = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeInfo; - temp = temp >> 8; - temp = XGI330_ScreenOffset[temp]; - - temp2 = XGI330_RefIndex[RefreshRateTableIndex].Ext_InfoFlag; - temp2 &= InterlaceMode; - - if (temp2) - temp = temp << 1; - - temp2 = pVBInfo->ModeType - ModeEGA; - - switch (temp2) { - case 0: - temp2 = 1; - break; - case 1: - temp2 = 2; - break; - case 2: - temp2 = 4; - break; - case 3: - temp2 = 4; - break; - case 4: - temp2 = 6; - break; - case 5: - temp2 = 8; - break; - default: - break; - } - - if ((ModeNo >= 0x26) && (ModeNo <= 0x28)) - temp = temp * temp2 + temp2 / 2; - else - temp *= temp2; - - /* SetOffset */ - DisplayUnit = temp; - temp2 = temp; - temp = temp >> 8; /* ah */ - temp &= 0x0F; - i = xgifb_reg_get(pVBInfo->P3c4, 0x0E); - i &= 0xF0; - i |= temp; - xgifb_reg_set(pVBInfo->P3c4, 0x0E, i); - - temp = (unsigned char) temp2; - temp &= 0xFF; /* al */ - xgifb_reg_set(pVBInfo->P3d4, 0x13, temp); - - /* SetDisplayUnit */ - temp2 = XGI330_RefIndex[RefreshRateTableIndex].Ext_InfoFlag; - temp2 &= InterlaceMode; - if (temp2) - DisplayUnit >>= 1; - - DisplayUnit = DisplayUnit << 5; - ah = (DisplayUnit & 0xff00) >> 8; - al = DisplayUnit & 0x00ff; - if (al == 0) - ah += 1; - else - ah += 2; - - if (HwDeviceExtension->jChipType >= XG20) - if ((ModeNo == 0x4A) | (ModeNo == 0x49)) - ah -= 1; - - xgifb_reg_set(pVBInfo->P3c4, 0x10, ah); -} - -static unsigned short XGI_GetVCLK2Ptr(unsigned short ModeIdIndex, - unsigned short RefreshRateTableIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short VCLKIndex, modeflag; - - /* si+Ext_ResInfo */ - modeflag = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeFlag; - - if (pVBInfo->VBInfo & (SetCRT2ToLCD | XGI_SetCRT2ToLCDA)) { /*301b*/ - if (pVBInfo->LCDResInfo != Panel_1024x768) - /* LCDXlat2VCLK */ - VCLKIndex = VCLK108_2_315 + 5; - else - VCLKIndex = VCLK65_315 + 2; /* LCDXlat1VCLK */ - } else if (pVBInfo->VBInfo & SetCRT2ToHiVision) { - if (pVBInfo->SetFlag & RPLLDIV2XO) - VCLKIndex = TVCLKBASE_315_25 + HiTVVCLKDIV2; - else - VCLKIndex = TVCLKBASE_315_25 + HiTVVCLK; - - if (pVBInfo->SetFlag & TVSimuMode) { - if (modeflag & Charx8Dot) - VCLKIndex = TVCLKBASE_315_25 + HiTVSimuVCLK; - else - VCLKIndex = TVCLKBASE_315_25 + HiTVTextVCLK; - } - - /* 301lv */ - if (pVBInfo->VBType & VB_SIS301LV) { - if (pVBInfo->SetFlag & RPLLDIV2XO) - VCLKIndex = YPbPr525iVCLK_2; - else - VCLKIndex = YPbPr525iVCLK; - } - } else if (pVBInfo->VBInfo & SetCRT2ToTV) { - if (pVBInfo->SetFlag & RPLLDIV2XO) - VCLKIndex = TVCLKBASE_315_25 + TVVCLKDIV2; - else - VCLKIndex = TVCLKBASE_315_25 + TVVCLK; - } else { /* for CRT2 */ - /* di+Ext_CRTVCLK */ - VCLKIndex = XGI330_RefIndex[RefreshRateTableIndex].Ext_CRTVCLK; - VCLKIndex &= IndexMask; - } - - return VCLKIndex; -} - -static void XGI_SetCRT1VCLK(unsigned short ModeIdIndex, - struct xgi_hw_device_info *HwDeviceExtension, - unsigned short RefreshRateTableIndex, - struct vb_device_info *pVBInfo) -{ - unsigned char index, data; - unsigned short vclkindex; - - if ((pVBInfo->IF_DEF_LVDS == 0) && - (pVBInfo->VBType & (VB_SIS301B | VB_SIS302B | VB_SIS301LV | - VB_SIS302LV | VB_XGI301C)) && - (pVBInfo->VBInfo & XGI_SetCRT2ToLCDA)) { - vclkindex = XGI_GetVCLK2Ptr(ModeIdIndex, RefreshRateTableIndex, - pVBInfo); - data = xgifb_reg_get(pVBInfo->P3c4, 0x31) & 0xCF; - xgifb_reg_set(pVBInfo->P3c4, 0x31, data); - data = XGI_VBVCLKData[vclkindex].Part4_A; - xgifb_reg_set(pVBInfo->P3c4, 0x2B, data); - data = XGI_VBVCLKData[vclkindex].Part4_B; - xgifb_reg_set(pVBInfo->P3c4, 0x2C, data); - xgifb_reg_set(pVBInfo->P3c4, 0x2D, 0x01); - } else { - index = XGI330_RefIndex[RefreshRateTableIndex].Ext_CRTVCLK; - data = xgifb_reg_get(pVBInfo->P3c4, 0x31) & 0xCF; - xgifb_reg_set(pVBInfo->P3c4, 0x31, data); - xgifb_reg_set(pVBInfo->P3c4, 0x2B, XGI_VCLKData[index].SR2B); - xgifb_reg_set(pVBInfo->P3c4, 0x2C, XGI_VCLKData[index].SR2C); - xgifb_reg_set(pVBInfo->P3c4, 0x2D, 0x01); - } - - if (HwDeviceExtension->jChipType >= XG20) { - if (XGI330_EModeIDTable[ModeIdIndex].Ext_ModeFlag & - HalfDCLK) { - data = xgifb_reg_get(pVBInfo->P3c4, 0x2B); - xgifb_reg_set(pVBInfo->P3c4, 0x2B, data); - data = xgifb_reg_get(pVBInfo->P3c4, 0x2C); - index = data; - index &= 0xE0; - data &= 0x1F; - data = data << 1; - data += 1; - data |= index; - xgifb_reg_set(pVBInfo->P3c4, 0x2C, data); - } - } -} - -static void XGI_SetXG21FPBits(struct vb_device_info *pVBInfo) -{ - unsigned char temp; - - temp = xgifb_reg_get(pVBInfo->P3d4, 0x37); /* D[0] 1: 18bit */ - temp = (temp & 1) << 6; - /* SR06[6] 18bit Dither */ - xgifb_reg_and_or(pVBInfo->P3c4, 0x06, ~0x40, temp); - /* SR09[7] enable FP output, SR09[6] 1: sigle 18bits, 0: dual 12bits */ - xgifb_reg_and_or(pVBInfo->P3c4, 0x09, ~0xc0, temp | 0x80); - -} - -static void XGI_SetCRT1FIFO(struct xgi_hw_device_info *HwDeviceExtension, - struct vb_device_info *pVBInfo) -{ - unsigned short data; - - data = xgifb_reg_get(pVBInfo->P3c4, 0x3D); - data &= 0xfe; - xgifb_reg_set(pVBInfo->P3c4, 0x3D, data); /* disable auto-threshold */ - - xgifb_reg_set(pVBInfo->P3c4, 0x08, 0x34); - data = xgifb_reg_get(pVBInfo->P3c4, 0x09); - data &= 0xC0; - xgifb_reg_set(pVBInfo->P3c4, 0x09, data | 0x30); - data = xgifb_reg_get(pVBInfo->P3c4, 0x3D); - data |= 0x01; - xgifb_reg_set(pVBInfo->P3c4, 0x3D, data); - - if (HwDeviceExtension->jChipType == XG21) - XGI_SetXG21FPBits(pVBInfo); /* Fix SR9[7:6] can't read back */ -} - -static void XGI_SetVCLKState(struct xgi_hw_device_info *HwDeviceExtension, - unsigned short RefreshRateTableIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short data, data2 = 0; - short VCLK; - - unsigned char index; - - index = XGI330_RefIndex[RefreshRateTableIndex].Ext_CRTVCLK; - index &= IndexMask; - VCLK = XGI_VCLKData[index].CLOCK; - - data = xgifb_reg_get(pVBInfo->P3c4, 0x32); - data &= 0xf3; - if (VCLK >= 200) - data |= 0x0c; /* VCLK > 200 */ - - if (HwDeviceExtension->jChipType >= XG20) - data &= ~0x04; /* 2 pixel mode */ - - xgifb_reg_set(pVBInfo->P3c4, 0x32, data); - - if (HwDeviceExtension->jChipType < XG20) { - data = xgifb_reg_get(pVBInfo->P3c4, 0x1F); - data &= 0xE7; - if (VCLK < 200) - data |= 0x10; - xgifb_reg_set(pVBInfo->P3c4, 0x1F, data); - } - - data2 = 0x00; - - xgifb_reg_and_or(pVBInfo->P3c4, 0x07, 0xFC, data2); - if (HwDeviceExtension->jChipType >= XG27) - xgifb_reg_and_or(pVBInfo->P3c4, 0x40, 0xFC, data2 & 0x03); - -} - -static void XGI_SetCRT1ModeRegs(struct xgi_hw_device_info *HwDeviceExtension, - unsigned short ModeIdIndex, - unsigned short RefreshRateTableIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short data, data2, data3, infoflag = 0, modeflag, resindex, - xres; - - modeflag = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeFlag; - infoflag = XGI330_RefIndex[RefreshRateTableIndex].Ext_InfoFlag; - - if (xgifb_reg_get(pVBInfo->P3d4, 0x31) & 0x01) - xgifb_reg_and_or(pVBInfo->P3c4, 0x1F, 0x3F, 0x00); - - data = infoflag; - data2 = 0; - data2 |= 0x02; - data3 = pVBInfo->ModeType - ModeVGA; - data3 = data3 << 2; - data2 |= data3; - data &= InterlaceMode; - - if (data) - data2 |= 0x20; - - xgifb_reg_and_or(pVBInfo->P3c4, 0x06, ~0x3F, data2); - resindex = XGI330_EModeIDTable[ModeIdIndex].Ext_RESINFO; - xres = XGI330_ModeResInfo[resindex].HTotal; /* xres->ax */ - - data = 0x0000; - if (infoflag & InterlaceMode) { - if (xres == 1024) - data = 0x0035; - else if (xres == 1280) - data = 0x0048; - } - - xgifb_reg_and_or(pVBInfo->P3d4, 0x19, 0xFF, data); - xgifb_reg_and_or(pVBInfo->P3d4, 0x19, 0xFC, 0); - - if (modeflag & HalfDCLK) - xgifb_reg_and_or(pVBInfo->P3c4, 0x01, 0xF7, 0x08); - - data2 = 0; - - if (modeflag & LineCompareOff) - data2 |= 0x08; - - xgifb_reg_and_or(pVBInfo->P3c4, 0x0F, ~0x48, data2); - data = 0x60; - data = data ^ 0x60; - data = data ^ 0xA0; - xgifb_reg_and_or(pVBInfo->P3c4, 0x21, 0x1F, data); - - XGI_SetVCLKState(HwDeviceExtension, RefreshRateTableIndex, pVBInfo); - - data = xgifb_reg_get(pVBInfo->P3d4, 0x31); - - if (HwDeviceExtension->jChipType == XG27) { - if (data & 0x40) - data = 0x2c; - else - data = 0x6c; - xgifb_reg_set(pVBInfo->P3d4, 0x52, data); - xgifb_reg_or(pVBInfo->P3d4, 0x51, 0x10); - } else if (HwDeviceExtension->jChipType >= XG20) { - if (data & 0x40) - data = 0x33; - else - data = 0x73; - xgifb_reg_set(pVBInfo->P3d4, 0x52, data); - xgifb_reg_set(pVBInfo->P3d4, 0x51, 0x02); - } else { - if (data & 0x40) - data = 0x2c; - else - data = 0x6c; - xgifb_reg_set(pVBInfo->P3d4, 0x52, data); - } - -} - -static void XGI_WriteDAC(unsigned short dl, - unsigned short ah, - unsigned short al, - unsigned short dh, - struct vb_device_info *pVBInfo) -{ - unsigned short temp, bh, bl; - - bh = ah; - bl = al; - - if (dl != 0) { - temp = bh; - bh = dh; - dh = temp; - if (dl == 1) { - temp = bl; - bl = dh; - dh = temp; - } else { - temp = bl; - bl = bh; - bh = temp; - } - } - outb((unsigned short) dh, pVBInfo->P3c9); - outb((unsigned short) bh, pVBInfo->P3c9); - outb((unsigned short) bl, pVBInfo->P3c9); -} - -static void XGI_LoadDAC(struct vb_device_info *pVBInfo) -{ - unsigned short data, data2, i, k, m, n, o, si, di, bx, dl, al, ah, dh; - const unsigned short *table = XGINew_VGA_DAC; - - outb(0xFF, pVBInfo->P3c6); - outb(0x00, pVBInfo->P3c8); - - for (i = 0; i < 16; i++) { - data = table[i]; - - for (k = 0; k < 3; k++) { - data2 = 0; - - if (data & 0x01) - data2 = 0x2A; - - if (data & 0x02) - data2 += 0x15; - - outb(data2, pVBInfo->P3c9); - data = data >> 2; - } - } - - for (i = 16; i < 32; i++) { - data = table[i]; - - for (k = 0; k < 3; k++) - outb(data, pVBInfo->P3c9); - } - - si = 32; - - for (m = 0; m < 9; m++) { - di = si; - bx = si + 0x04; - dl = 0; - - for (n = 0; n < 3; n++) { - for (o = 0; o < 5; o++) { - dh = table[si]; - ah = table[di]; - al = table[bx]; - si++; - XGI_WriteDAC(dl, ah, al, dh, pVBInfo); - } - - si -= 2; - - for (o = 0; o < 3; o++) { - dh = table[bx]; - ah = table[di]; - al = table[si]; - si--; - XGI_WriteDAC(dl, ah, al, dh, pVBInfo); - } - - dl++; - } - - si += 5; - } -} - -static void XGI_GetLVDSResInfo(unsigned short ModeIdIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short resindex, xres, yres, modeflag; - - /* si+Ext_ResInfo */ - modeflag = XGI330_EModeIDTable[ModeIdIndex].Ext_RESINFO; - - /* si+Ext_ResInfo */ - resindex = XGI330_EModeIDTable[ModeIdIndex].Ext_RESINFO; - - xres = XGI330_ModeResInfo[resindex].HTotal; - yres = XGI330_ModeResInfo[resindex].VTotal; - - if (modeflag & HalfDCLK) - xres = xres << 1; - - if (modeflag & DoubleScanMode) - yres = yres << 1; - - if (xres == 720) - xres = 640; - - pVBInfo->VGAHDE = xres; - pVBInfo->HDE = xres; - pVBInfo->VGAVDE = yres; - pVBInfo->VDE = yres; -} - -static void const *XGI_GetLcdPtr(struct XGI330_LCDDataTablStruct const *table, - unsigned short ModeIdIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short i, tempdx, tempbx, modeflag; - - tempbx = 0; - - modeflag = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeFlag; - - i = 0; - - while (table[i].PANELID != 0xff) { - tempdx = pVBInfo->LCDResInfo; - if (tempbx & 0x0080) { /* OEMUtil */ - tempbx &= (~0x0080); - tempdx = pVBInfo->LCDTypeInfo; - } - - if (pVBInfo->LCDInfo & EnableScalingLCD) - tempdx &= (~PanelResInfo); - - if (table[i].PANELID == tempdx) { - tempbx = table[i].MASK; - tempdx = pVBInfo->LCDInfo; - - if (modeflag & HalfDCLK) - tempdx |= SetLCDLowResolution; - - tempbx &= tempdx; - if (tempbx == table[i].CAP) - break; - } - i++; - } - - return table[i].DATAPTR; -} - -static struct SiS_TVData const *XGI_GetTVPtr(unsigned short ModeIdIndex, - unsigned short RefreshRateTableIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short i, tempdx, tempal, modeflag; - - modeflag = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeFlag; - tempal = XGI330_RefIndex[RefreshRateTableIndex].Ext_CRT2CRTC; - tempal = tempal & 0x3f; - tempdx = pVBInfo->TVInfo; - - if (pVBInfo->VBInfo & SetInSlaveMode) - tempdx = tempdx | SetTVLockMode; - - if (modeflag & HalfDCLK) - tempdx = tempdx | SetTVLowResolution; - - i = 0; - - while (XGI_TVDataTable[i].MASK != 0xffff) { - if ((tempdx & XGI_TVDataTable[i].MASK) == - XGI_TVDataTable[i].CAP) - break; - i++; - } - - return &XGI_TVDataTable[i].DATAPTR[tempal]; -} - -static void XGI_GetLVDSData(unsigned short ModeIdIndex, - struct vb_device_info *pVBInfo) -{ - struct SiS_LVDSData const *LCDPtr; - - if (!(pVBInfo->VBInfo & (SetCRT2ToLCD | XGI_SetCRT2ToLCDA))) - return; - - LCDPtr = XGI_GetLcdPtr(XGI_EPLLCDDataPtr, ModeIdIndex, pVBInfo); - pVBInfo->VGAHT = LCDPtr->VGAHT; - pVBInfo->VGAVT = LCDPtr->VGAVT; - pVBInfo->HT = LCDPtr->LCDHT; - pVBInfo->VT = LCDPtr->LCDVT; - - if (pVBInfo->LCDInfo & (SetLCDtoNonExpanding | EnableScalingLCD)) - return; - - if ((pVBInfo->LCDResInfo == Panel_1024x768) || - (pVBInfo->LCDResInfo == Panel_1024x768x75)) { - pVBInfo->HDE = 1024; - pVBInfo->VDE = 768; - } else if ((pVBInfo->LCDResInfo == Panel_1280x1024) || - (pVBInfo->LCDResInfo == Panel_1280x1024x75)) { - pVBInfo->HDE = 1280; - pVBInfo->VDE = 1024; - } else if (pVBInfo->LCDResInfo == Panel_1400x1050) { - pVBInfo->HDE = 1400; - pVBInfo->VDE = 1050; - } else { - pVBInfo->HDE = 1600; - pVBInfo->VDE = 1200; - } -} - -static void XGI_ModCRT1Regs(unsigned short ModeIdIndex, - struct xgi_hw_device_info *HwDeviceExtension, - struct vb_device_info *pVBInfo) -{ - unsigned short i; - struct XGI_LVDSCRT1HDataStruct const *LCDPtr = NULL; - struct XGI_LVDSCRT1VDataStruct const *LCDPtr1 = NULL; - - if (pVBInfo->VBInfo & (SetCRT2ToLCD | XGI_SetCRT2ToLCDA)) { - LCDPtr = XGI_GetLcdPtr(xgifb_epllcd_crt1_h, ModeIdIndex, - pVBInfo); - - for (i = 0; i < 8; i++) - pVBInfo->TimingH.data[i] = LCDPtr[0].Reg[i]; - } - - XGI_SetCRT1Timing_H(pVBInfo, HwDeviceExtension); - - if (pVBInfo->VBInfo & (SetCRT2ToLCD | XGI_SetCRT2ToLCDA)) { - LCDPtr1 = XGI_GetLcdPtr(xgifb_epllcd_crt1_v, ModeIdIndex, - pVBInfo); - for (i = 0; i < 7; i++) - pVBInfo->TimingV.data[i] = LCDPtr1[0].Reg[i]; - } - - XGI_SetCRT1Timing_V(ModeIdIndex, pVBInfo); -} - -static unsigned short XGI_GetLCDCapPtr(struct vb_device_info *pVBInfo) -{ - unsigned char tempal, tempah, tempbl, i; - - tempah = xgifb_reg_get(pVBInfo->P3d4, 0x36); - tempal = tempah & 0x0F; - tempah = tempah & 0xF0; - i = 0; - tempbl = pVBInfo->LCDCapList[i].LCD_ID; - - while (tempbl != 0xFF) { - if (tempbl & 0x80) { /* OEMUtil */ - tempal = tempah; - tempbl = tempbl & ~(0x80); - } - - if (tempal == tempbl) - break; - - i++; - - tempbl = pVBInfo->LCDCapList[i].LCD_ID; - } - - return i; -} - -static unsigned short XGI_GetLCDCapPtr1(struct vb_device_info *pVBInfo) -{ - unsigned short tempah, tempal, tempbl, i; - - tempal = pVBInfo->LCDResInfo; - tempah = pVBInfo->LCDTypeInfo; - - i = 0; - tempbl = pVBInfo->LCDCapList[i].LCD_ID; - - while (tempbl != 0xFF) { - if ((tempbl & 0x80) && (tempbl != 0x80)) { - tempal = tempah; - tempbl &= ~0x80; - } - - if (tempal == tempbl) - break; - - i++; - tempbl = pVBInfo->LCDCapList[i].LCD_ID; - } - - if (tempbl == 0xFF) { - pVBInfo->LCDResInfo = Panel_1024x768; - pVBInfo->LCDTypeInfo = 0; - i = 0; - } - - return i; -} - -static void XGI_GetLCDSync(unsigned short *HSyncWidth, - unsigned short *VSyncWidth, - struct vb_device_info *pVBInfo) -{ - unsigned short Index; - - Index = XGI_GetLCDCapPtr(pVBInfo); - *HSyncWidth = pVBInfo->LCDCapList[Index].LCD_HSyncWidth; - *VSyncWidth = pVBInfo->LCDCapList[Index].LCD_VSyncWidth; -} - -static void XGI_SetLVDSRegs(unsigned short ModeIdIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short tempbx, tempax, tempcx, tempdx, push1, push2, modeflag; - unsigned long temp, temp1, temp2, temp3, push3; - struct XGI330_LCDDataDesStruct2 const *LCDPtr1 = NULL; - - modeflag = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeFlag; - LCDPtr1 = XGI_GetLcdPtr(XGI_EPLLCDDesDataPtr, ModeIdIndex, pVBInfo); - - XGI_GetLCDSync(&tempax, &tempbx, pVBInfo); - push1 = tempbx; - push2 = tempax; - - /* GetLCDResInfo */ - if ((pVBInfo->LCDResInfo == Panel_1024x768) || - (pVBInfo->LCDResInfo == Panel_1024x768x75)) { - tempax = 1024; - tempbx = 768; - } else if ((pVBInfo->LCDResInfo == Panel_1280x1024) || - (pVBInfo->LCDResInfo == Panel_1280x1024x75)) { - tempax = 1280; - tempbx = 1024; - } else if (pVBInfo->LCDResInfo == Panel_1400x1050) { - tempax = 1400; - tempbx = 1050; - } else { - tempax = 1600; - tempbx = 1200; - } - - if (pVBInfo->LCDInfo & SetLCDtoNonExpanding) { - pVBInfo->HDE = tempax; - pVBInfo->VDE = tempbx; - pVBInfo->VGAHDE = tempax; - pVBInfo->VGAVDE = tempbx; - } - - tempax = pVBInfo->HT; - - tempbx = LCDPtr1->LCDHDES; - - tempcx = pVBInfo->HDE; - tempbx = tempbx & 0x0fff; - tempcx += tempbx; - - if (tempcx >= tempax) - tempcx -= tempax; - - xgifb_reg_set(pVBInfo->Part1Port, 0x1A, tempbx & 0x07); - - tempcx = tempcx >> 3; - tempbx = tempbx >> 3; - - xgifb_reg_set(pVBInfo->Part1Port, 0x16, - (unsigned short) (tempbx & 0xff)); - xgifb_reg_set(pVBInfo->Part1Port, 0x17, - (unsigned short) (tempcx & 0xff)); - - tempax = pVBInfo->HT; - - tempbx = LCDPtr1->LCDHRS; - - tempcx = push2; - - if (pVBInfo->LCDInfo & EnableScalingLCD) - tempcx = LCDPtr1->LCDHSync; - - tempcx += tempbx; - - if (tempcx >= tempax) - tempcx -= tempax; - - tempax = tempbx & 0x07; - tempax = tempax >> 5; - tempcx = tempcx >> 3; - tempbx = tempbx >> 3; - - tempcx &= 0x1f; - tempax |= tempcx; - - xgifb_reg_set(pVBInfo->Part1Port, 0x15, tempax); - xgifb_reg_set(pVBInfo->Part1Port, 0x14, - (unsigned short) (tempbx & 0xff)); - - tempax = pVBInfo->VT; - tempbx = LCDPtr1->LCDVDES; - tempcx = pVBInfo->VDE; - - tempbx = tempbx & 0x0fff; - tempcx += tempbx; - if (tempcx >= tempax) - tempcx -= tempax; - - xgifb_reg_set(pVBInfo->Part1Port, 0x1b, - (unsigned short) (tempbx & 0xff)); - xgifb_reg_set(pVBInfo->Part1Port, 0x1c, - (unsigned short) (tempcx & 0xff)); - - tempbx = (tempbx >> 8) & 0x07; - tempcx = (tempcx >> 8) & 0x07; - - xgifb_reg_set(pVBInfo->Part1Port, 0x1d, - (unsigned short) ((tempcx << 3) - | tempbx)); - - tempax = pVBInfo->VT; - tempbx = LCDPtr1->LCDVRS; - - tempcx = push1; - - if (pVBInfo->LCDInfo & EnableScalingLCD) - tempcx = LCDPtr1->LCDVSync; - - tempcx += tempbx; - if (tempcx >= tempax) - tempcx -= tempax; - - xgifb_reg_set(pVBInfo->Part1Port, 0x18, - (unsigned short) (tempbx & 0xff)); - xgifb_reg_and_or(pVBInfo->Part1Port, 0x19, ~0x0f, - (unsigned short) (tempcx & 0x0f)); - - tempax = ((tempbx >> 8) & 0x07) << 3; - - tempbx = pVBInfo->VGAVDE; - if (tempbx != pVBInfo->VDE) - tempax |= 0x40; - - if (pVBInfo->LCDInfo & XGI_EnableLVDSDDA) - tempax |= 0x40; - - xgifb_reg_and_or(pVBInfo->Part1Port, 0x1a, 0x07, - tempax); - - tempbx = pVBInfo->VDE; - tempax = pVBInfo->VGAVDE; - - temp = tempax; /* 0430 ylshieh */ - temp1 = (temp << 18) / tempbx; - - tempdx = (unsigned short) ((temp << 18) % tempbx); - - if (tempdx != 0) - temp1 += 1; - - temp2 = temp1; - push3 = temp2; - - xgifb_reg_set(pVBInfo->Part1Port, 0x37, - (unsigned short) (temp2 & 0xff)); - xgifb_reg_set(pVBInfo->Part1Port, 0x36, - (unsigned short) ((temp2 >> 8) & 0xff)); - - tempbx = (unsigned short) (temp2 >> 16); - tempax = tempbx & 0x03; - - tempbx = pVBInfo->VGAVDE; - if (tempbx == pVBInfo->VDE) - tempax |= 0x04; - - xgifb_reg_set(pVBInfo->Part1Port, 0x35, tempax); - - if (pVBInfo->VBType & VB_XGI301C) { - temp2 = push3; - xgifb_reg_set(pVBInfo->Part4Port, - 0x3c, - (unsigned short) (temp2 & 0xff)); - xgifb_reg_set(pVBInfo->Part4Port, - 0x3b, - (unsigned short) ((temp2 >> 8) & - 0xff)); - tempbx = (unsigned short) (temp2 >> 16); - xgifb_reg_and_or(pVBInfo->Part4Port, 0x3a, - ~0xc0, - (unsigned short) ((tempbx & - 0xff) << 6)); - - tempcx = pVBInfo->VGAVDE; - if (tempcx == pVBInfo->VDE) - xgifb_reg_and_or(pVBInfo->Part4Port, - 0x30, ~0x0c, 0x00); - else - xgifb_reg_and_or(pVBInfo->Part4Port, - 0x30, ~0x0c, 0x08); - } - - tempcx = pVBInfo->VGAHDE; - tempbx = pVBInfo->HDE; - - temp1 = tempcx << 16; - - tempax = (unsigned short) (temp1 / tempbx); - - if ((tempbx & 0xffff) == (tempcx & 0xffff)) - tempax = 65535; - - temp3 = tempax; - temp1 = pVBInfo->VGAHDE << 16; - - temp1 /= temp3; - temp3 = temp3 << 16; - temp1 -= 1; - - temp3 = (temp3 & 0xffff0000) + (temp1 & 0xffff); - - tempax = (unsigned short) (temp3 & 0xff); - xgifb_reg_set(pVBInfo->Part1Port, 0x1f, tempax); - - temp1 = pVBInfo->VGAVDE << 18; - temp1 = temp1 / push3; - tempbx = (unsigned short) (temp1 & 0xffff); - - if (pVBInfo->LCDResInfo == Panel_1024x768) - tempbx -= 1; - - tempax = ((tempbx >> 8) & 0xff) << 3; - tempax |= (unsigned short) ((temp3 >> 8) & 0x07); - xgifb_reg_set(pVBInfo->Part1Port, 0x20, - (unsigned short) (tempax & 0xff)); - xgifb_reg_set(pVBInfo->Part1Port, 0x21, - (unsigned short) (tempbx & 0xff)); - - temp3 = temp3 >> 16; - - if (modeflag & HalfDCLK) - temp3 = temp3 >> 1; - - xgifb_reg_set(pVBInfo->Part1Port, 0x22, - (unsigned short) ((temp3 >> 8) & 0xff)); - xgifb_reg_set(pVBInfo->Part1Port, 0x23, - (unsigned short) (temp3 & 0xff)); -} - -/* --------------------------------------------------------------------- */ -/* Function : XGI_GETLCDVCLKPtr */ -/* Input : */ -/* Output : al -> VCLK Index */ -/* Description : */ -/* --------------------------------------------------------------------- */ -static void XGI_GetLCDVCLKPtr(unsigned char *di_0, unsigned char *di_1, - struct vb_device_info *pVBInfo) -{ - unsigned short index; - - if (pVBInfo->VBInfo & (SetCRT2ToLCD | XGI_SetCRT2ToLCDA)) { - index = XGI_GetLCDCapPtr1(pVBInfo); - - if (pVBInfo->VBInfo & SetCRT2ToLCD) { /* LCDB */ - *di_0 = pVBInfo->LCDCapList[index].LCUCHAR_VCLKData1; - *di_1 = pVBInfo->LCDCapList[index].LCUCHAR_VCLKData2; - } else { /* LCDA */ - *di_0 = pVBInfo->LCDCapList[index].LCDA_VCLKData1; - *di_1 = pVBInfo->LCDCapList[index].LCDA_VCLKData2; - } - } -} - -static unsigned char XGI_GetVCLKPtr(unsigned short RefreshRateTableIndex, - unsigned short ModeIdIndex, struct vb_device_info *pVBInfo) -{ - - unsigned short index, modeflag; - unsigned char tempal; - - /* si+Ext_ResInfo */ - modeflag = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeFlag; - - if ((pVBInfo->SetFlag & ProgrammingCRT2) && - (!(pVBInfo->LCDInfo & EnableScalingLCD))) { /* {LCDA/LCDB} */ - index = XGI_GetLCDCapPtr(pVBInfo); - tempal = pVBInfo->LCDCapList[index].LCD_VCLK; - - if (pVBInfo->VBInfo & (SetCRT2ToLCD | XGI_SetCRT2ToLCDA)) - return tempal; - - /* {TV} */ - if (pVBInfo->VBType & - (VB_SIS301B | - VB_SIS302B | - VB_SIS301LV | - VB_SIS302LV | - VB_XGI301C)) { - if (pVBInfo->VBInfo & SetCRT2ToHiVision) { - tempal = TVCLKBASE_315 + HiTVVCLKDIV2; - if (!(pVBInfo->TVInfo & RPLLDIV2XO)) - tempal = TVCLKBASE_315 + HiTVVCLK; - if (pVBInfo->TVInfo & TVSimuMode) { - tempal = TVCLKBASE_315 + HiTVSimuVCLK; - if (!(modeflag & Charx8Dot)) - tempal = TVCLKBASE_315 + - HiTVTextVCLK; - - } - return tempal; - } - - if (pVBInfo->TVInfo & TVSetYPbPr750p) { - tempal = XGI_YPbPr750pVCLK; - return tempal; - } - - if (pVBInfo->TVInfo & TVSetYPbPr525p) { - tempal = YPbPr525pVCLK; - return tempal; - } - - tempal = NTSC1024VCLK; - - if (!(pVBInfo->TVInfo & NTSC1024x768)) { - tempal = TVCLKBASE_315 + TVVCLKDIV2; - if (!(pVBInfo->TVInfo & RPLLDIV2XO)) - tempal = TVCLKBASE_315 + TVVCLK; - } - - if (pVBInfo->VBInfo & SetCRT2ToTV) - return tempal; - } - } /* {End of VB} */ - - inb((pVBInfo->P3ca + 0x02)); - tempal = XGI330_RefIndex[RefreshRateTableIndex].Ext_CRTVCLK; - return tempal; -} - -static void XGI_GetVCLKLen(unsigned char tempal, unsigned char *di_0, - unsigned char *di_1, struct vb_device_info *pVBInfo) -{ - if (pVBInfo->VBType & (VB_SIS301 | VB_SIS301B | VB_SIS302B - | VB_SIS301LV | VB_SIS302LV | VB_XGI301C)) { - if ((!(pVBInfo->VBInfo & XGI_SetCRT2ToLCDA)) && - (pVBInfo->SetFlag & ProgrammingCRT2)) { - *di_0 = XGI_VBVCLKData[tempal].Part4_A; - *di_1 = XGI_VBVCLKData[tempal].Part4_B; - } - } else { - *di_0 = XGI_VCLKData[tempal].SR2B; - *di_1 = XGI_VCLKData[tempal].SR2C; - } -} - -static void XGI_SetCRT2ECLK(unsigned short ModeIdIndex, - unsigned short RefreshRateTableIndex, - struct vb_device_info *pVBInfo) -{ - unsigned char di_0, di_1, tempal; - int i; - - tempal = XGI_GetVCLKPtr(RefreshRateTableIndex, ModeIdIndex, pVBInfo); - XGI_GetVCLKLen(tempal, &di_0, &di_1, pVBInfo); - XGI_GetLCDVCLKPtr(&di_0, &di_1, pVBInfo); - - for (i = 0; i < 4; i++) { - xgifb_reg_and_or(pVBInfo->P3d4, 0x31, ~0x30, - (unsigned short) (0x10 * i)); - if ((!(pVBInfo->VBInfo & XGI_SetCRT2ToLCDA)) - && (!(pVBInfo->VBInfo & SetInSlaveMode))) { - xgifb_reg_set(pVBInfo->P3c4, 0x2e, di_0); - xgifb_reg_set(pVBInfo->P3c4, 0x2f, di_1); - } else { - xgifb_reg_set(pVBInfo->P3c4, 0x2b, di_0); - xgifb_reg_set(pVBInfo->P3c4, 0x2c, di_1); - } - } -} - -static void XGI_UpdateModeInfo(struct vb_device_info *pVBInfo) -{ - unsigned short tempcl, tempch, temp, tempbl, tempax; - - if (pVBInfo->VBType & (VB_SIS301B | VB_SIS302B | VB_SIS301LV - | VB_SIS302LV | VB_XGI301C)) { - tempcl = 0; - tempch = 0; - temp = xgifb_reg_get(pVBInfo->P3c4, 0x01); - - if (!(temp & 0x20)) { - temp = xgifb_reg_get(pVBInfo->P3d4, 0x17); - if (temp & 0x80) { - temp = xgifb_reg_get(pVBInfo->P3d4, 0x53); - if (!(temp & 0x40)) - tempcl |= ActiveCRT1; - } - } - - temp = xgifb_reg_get(pVBInfo->Part1Port, 0x2e); - temp &= 0x0f; - - if (!(temp == 0x08)) { - /* Check ChannelA */ - tempax = xgifb_reg_get(pVBInfo->Part1Port, 0x13); - if (tempax & 0x04) - tempcl = tempcl | ActiveLCD; - - temp &= 0x05; - - if (!(tempcl & ActiveLCD)) - if (temp == 0x01) - tempcl |= ActiveCRT2; - - if (temp == 0x04) - tempcl |= ActiveLCD; - - if (temp == 0x05) { - temp = xgifb_reg_get(pVBInfo->Part2Port, 0x00); - - if (!(temp & 0x08)) - tempch |= ActiveAVideo; - - if (!(temp & 0x04)) - tempch |= ActiveSVideo; - - if (temp & 0x02) - tempch |= ActiveSCART; - - if (pVBInfo->VBInfo & SetCRT2ToHiVision) { - if (temp & 0x01) - tempch |= ActiveHiTV; - } - - if (pVBInfo->VBInfo & SetCRT2ToYPbPr525750) { - temp = xgifb_reg_get( - pVBInfo->Part2Port, - 0x4d); - - if (temp & 0x10) - tempch |= ActiveYPbPr; - } - - if (tempch != 0) - tempcl |= ActiveTV; - } - } - - temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d); - if (tempcl & ActiveLCD) { - if ((pVBInfo->SetFlag & ReserveTVOption)) { - if (temp & ActiveTV) - tempcl |= ActiveTV; - } - } - temp = tempcl; - tempbl = ~XGI_ModeSwitchStatus; - xgifb_reg_and_or(pVBInfo->P3d4, 0x3d, tempbl, temp); - - if (!(pVBInfo->SetFlag & ReserveTVOption)) - xgifb_reg_set(pVBInfo->P3d4, 0x3e, tempch); - } -} - -void XGI_GetVBType(struct vb_device_info *pVBInfo) -{ - unsigned short flag, tempbx, tempah; - - tempbx = VB_SIS302B; - flag = xgifb_reg_get(pVBInfo->Part4Port, 0x00); - if (flag == 0x02) - goto finish; - - tempbx = VB_SIS301; - flag = xgifb_reg_get(pVBInfo->Part4Port, 0x01); - if (flag < 0xB0) - goto finish; - - tempbx = VB_SIS301B; - if (flag < 0xC0) - goto bigger_than_0xB0; - - tempbx = VB_XGI301C; - if (flag < 0xD0) - goto bigger_than_0xB0; - - tempbx = VB_SIS301LV; - if (flag < 0xE0) - goto bigger_than_0xB0; - - tempbx = VB_SIS302LV; - tempah = xgifb_reg_get(pVBInfo->Part4Port, 0x39); - if (tempah != 0xFF) - tempbx = VB_XGI301C; - -bigger_than_0xB0: - if (tempbx & (VB_SIS301B | VB_SIS302B)) { - flag = xgifb_reg_get(pVBInfo->Part4Port, 0x23); - if (!(flag & 0x02)) - tempbx = tempbx | VB_NoLCD; - } - -finish: - pVBInfo->VBType = tempbx; -} - -static void XGI_GetVBInfo(unsigned short ModeIdIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short tempax, push, tempbx, temp, modeflag; - - modeflag = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeFlag; - pVBInfo->SetFlag = 0; - pVBInfo->ModeType = modeflag & ModeTypeMask; - tempbx = 0; - - if (!(pVBInfo->VBType & 0xFFFF)) - return; - - /* Check Display Device */ - temp = xgifb_reg_get(pVBInfo->P3d4, 0x30); - tempbx = tempbx | temp; - temp = xgifb_reg_get(pVBInfo->P3d4, 0x31); - push = temp; - push = push << 8; - tempax = temp << 8; - tempbx = tempbx | tempax; - temp = (SetCRT2ToDualEdge | SetCRT2ToYPbPr525750 | XGI_SetCRT2ToLCDA - | SetInSlaveMode | DisableCRT2Display); - temp = 0xFFFF ^ temp; - tempbx &= temp; - - temp = xgifb_reg_get(pVBInfo->P3d4, 0x38); - - if (pVBInfo->VBType & (VB_SIS302B | VB_SIS301LV | VB_SIS302LV | - VB_XGI301C)) { - if (temp & EnableDualEdge) { - tempbx |= SetCRT2ToDualEdge; - if (temp & SetToLCDA) - tempbx |= XGI_SetCRT2ToLCDA; - } - } - - if (pVBInfo->VBType & (VB_SIS301LV|VB_SIS302LV|VB_XGI301C)) { - if (temp & SetYPbPr) { - /* shampoo add for new scratch */ - temp = xgifb_reg_get(pVBInfo->P3d4, 0x35); - temp &= YPbPrMode; - tempbx |= SetCRT2ToHiVision; - - if (temp != YPbPrMode1080i) { - tempbx &= (~SetCRT2ToHiVision); - tempbx |= SetCRT2ToYPbPr525750; - } - } - } - - tempax = push; /* restore CR31 */ - - temp = 0x09FC; - - if (!(tempbx & temp)) { - tempax |= DisableCRT2Display; - tempbx = 0; - } - - if (!(pVBInfo->VBType & VB_NoLCD)) { - if (tempbx & XGI_SetCRT2ToLCDA) { - if (tempbx & SetSimuScanMode) - tempbx &= (~(SetCRT2ToLCD | SetCRT2ToRAMDAC | - SwitchCRT2)); - else - tempbx &= (~(SetCRT2ToLCD | SetCRT2ToRAMDAC | - SetCRT2ToTV | SwitchCRT2)); - } - } - - /* shampoo add */ - /* for driver abnormal */ - if (!(tempbx & (SwitchCRT2 | SetSimuScanMode))) { - if (tempbx & SetCRT2ToRAMDAC) { - tempbx &= (0xFF00 | SetCRT2ToRAMDAC | - SwitchCRT2 | SetSimuScanMode); - tempbx &= (0x00FF | (~SetCRT2ToYPbPr525750)); - } - } - - if (!(pVBInfo->VBType & VB_NoLCD)) { - if (tempbx & SetCRT2ToLCD) { - tempbx &= (0xFF00 | SetCRT2ToLCD | SwitchCRT2 | - SetSimuScanMode); - tempbx &= (0x00FF | (~SetCRT2ToYPbPr525750)); - } - } - - if (tempbx & SetCRT2ToSCART) { - tempbx &= (0xFF00 | SetCRT2ToSCART | SwitchCRT2 | - SetSimuScanMode); - tempbx &= (0x00FF | (~SetCRT2ToYPbPr525750)); - } - - if (tempbx & SetCRT2ToYPbPr525750) - tempbx &= (0xFF00 | SwitchCRT2 | SetSimuScanMode); - - if (tempbx & SetCRT2ToHiVision) - tempbx &= (0xFF00 | SetCRT2ToHiVision | SwitchCRT2 | - SetSimuScanMode); - - if (tempax & DisableCRT2Display) { /* Set Display Device Info */ - if (!(tempbx & (SwitchCRT2 | SetSimuScanMode))) - tempbx = DisableCRT2Display; - } - - if (!(tempbx & DisableCRT2Display)) { - if ((!(tempbx & DriverMode)) || (!(modeflag & CRT2Mode))) { - if (!(tempbx & XGI_SetCRT2ToLCDA)) - tempbx |= (SetInSlaveMode | SetSimuScanMode); - } - - /* LCD+TV can't support in slave mode - * (Force LCDA+TV->LCDB) */ - if ((tempbx & SetInSlaveMode) && (tempbx & XGI_SetCRT2ToLCDA)) { - tempbx ^= (SetCRT2ToLCD | XGI_SetCRT2ToLCDA | - SetCRT2ToDualEdge); - pVBInfo->SetFlag |= ReserveTVOption; - } - } - - pVBInfo->VBInfo = tempbx; -} - -static void XGI_GetTVInfo(unsigned short ModeIdIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short tempbx = 0, resinfo = 0, modeflag, index1; - - if (pVBInfo->VBInfo & SetCRT2ToTV) { - modeflag = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeFlag; - resinfo = XGI330_EModeIDTable[ModeIdIndex].Ext_RESINFO; - - tempbx = xgifb_reg_get(pVBInfo->P3d4, 0x35); - if (tempbx & TVSetPAL) { - tempbx &= (SetCHTVOverScan | - TVSetPALM | - TVSetPALN | - TVSetPAL); - if (tempbx & TVSetPALM) - /* set to NTSC if PAL-M */ - tempbx &= ~TVSetPAL; - } else - tempbx &= (SetCHTVOverScan | - TVSetNTSCJ | - TVSetPAL); - - if (pVBInfo->VBInfo & SetCRT2ToSCART) - tempbx |= TVSetPAL; - - if (pVBInfo->VBInfo & SetCRT2ToYPbPr525750) { - index1 = xgifb_reg_get(pVBInfo->P3d4, 0x35); - index1 &= YPbPrMode; - - if (index1 == YPbPrMode525i) - tempbx |= TVSetYPbPr525i; - - if (index1 == YPbPrMode525p) - tempbx = tempbx | TVSetYPbPr525p; - if (index1 == YPbPrMode750p) - tempbx = tempbx | TVSetYPbPr750p; - } - - if (pVBInfo->VBInfo & SetCRT2ToHiVision) - tempbx = tempbx | TVSetHiVision | TVSetPAL; - - if ((pVBInfo->VBInfo & SetInSlaveMode) && - (!(pVBInfo->VBInfo & SetNotSimuMode))) - tempbx |= TVSimuMode; - - if (!(tempbx & TVSetPAL) && (modeflag > 13) && (resinfo == 8)) - /* NTSC 1024x768, */ - tempbx |= NTSC1024x768; - - tempbx |= RPLLDIV2XO; - - if (pVBInfo->VBInfo & SetCRT2ToHiVision) { - if (pVBInfo->VBInfo & SetInSlaveMode) - tempbx &= (~RPLLDIV2XO); - } else if (tempbx & (TVSetYPbPr525p | TVSetYPbPr750p)) { - tempbx &= (~RPLLDIV2XO); - } else if (!(pVBInfo->VBType & (VB_SIS301B | VB_SIS302B | - VB_SIS301LV | VB_SIS302LV | - VB_XGI301C))) { - if (tempbx & TVSimuMode) - tempbx &= (~RPLLDIV2XO); - } - } - pVBInfo->TVInfo = tempbx; -} - -static unsigned char XGI_GetLCDInfo(unsigned short ModeIdIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short temp, tempax, tempbx, resinfo = 0, LCDIdIndex; - - pVBInfo->LCDResInfo = 0; - pVBInfo->LCDTypeInfo = 0; - pVBInfo->LCDInfo = 0; - - /* si+Ext_ResInfo // */ - resinfo = XGI330_EModeIDTable[ModeIdIndex].Ext_RESINFO; - temp = xgifb_reg_get(pVBInfo->P3d4, 0x36); /* Get LCD Res.Info */ - tempbx = temp & 0x0F; - - if (tempbx == 0) - tempbx = Panel_1024x768; /* default */ - - /* LCD75 */ - if ((tempbx == Panel_1024x768) || (tempbx == Panel_1280x1024)) { - if (pVBInfo->VBInfo & DriverMode) { - tempax = xgifb_reg_get(pVBInfo->P3d4, 0x33); - if (pVBInfo->VBInfo & XGI_SetCRT2ToLCDA) - tempax &= 0x0F; - else - tempax = tempax >> 4; - - if ((resinfo == 6) || (resinfo == 9)) { - if (tempax >= 3) - tempbx |= PanelRef75Hz; - } else if ((resinfo == 7) || (resinfo == 8)) { - if (tempax >= 4) - tempbx |= PanelRef75Hz; - } - } - } - - pVBInfo->LCDResInfo = tempbx; - - /* End of LCD75 */ - - if (!(pVBInfo->VBInfo & (SetCRT2ToLCD | XGI_SetCRT2ToLCDA))) - return 0; - - tempbx = 0; - - temp = xgifb_reg_get(pVBInfo->P3d4, 0x37); - - temp &= (ScalingLCD | LCDNonExpanding | LCDSyncBit | SetPWDEnable); - - tempbx |= temp; - - LCDIdIndex = XGI_GetLCDCapPtr1(pVBInfo); - - tempax = pVBInfo->LCDCapList[LCDIdIndex].LCD_Capability; - - if (((pVBInfo->VBType & VB_SIS302LV) || - (pVBInfo->VBType & VB_XGI301C)) && (tempax & XGI_LCDDualLink)) - tempbx |= SetLCDDualLink; - - if ((pVBInfo->LCDResInfo == Panel_1400x1050) && - (pVBInfo->VBInfo & SetCRT2ToLCD) && (resinfo == 9) && - (!(tempbx & EnableScalingLCD))) - /* - * set to center in 1280x1024 LCDB - * for Panel_1400x1050 - */ - tempbx |= SetLCDtoNonExpanding; - - if (pVBInfo->VBInfo & SetInSlaveMode) { - if (pVBInfo->VBInfo & SetNotSimuMode) - tempbx |= XGI_LCDVESATiming; - } else { - tempbx |= XGI_LCDVESATiming; - } - - pVBInfo->LCDInfo = tempbx; - - return 1; -} - -unsigned char XGI_SearchModeID(unsigned short ModeNo, - unsigned short *ModeIdIndex) -{ - for (*ModeIdIndex = 0;; (*ModeIdIndex)++) { - if (XGI330_EModeIDTable[*ModeIdIndex].Ext_ModeID == ModeNo) - break; - if (XGI330_EModeIDTable[*ModeIdIndex].Ext_ModeID == 0xFF) - return 0; - } - - return 1; -} - -static unsigned char XG21GPIODataTransfer(unsigned char ujDate) -{ - unsigned char ujRet = 0; - unsigned char i = 0; - - for (i = 0; i < 8; i++) { - ujRet = ujRet << 1; - ujRet |= (ujDate >> i) & 1; - } - - return ujRet; -} - -/*----------------------------------------------------------------------------*/ -/* output */ -/* bl[5] : LVDS signal */ -/* bl[1] : LVDS backlight */ -/* bl[0] : LVDS VDD */ -/*----------------------------------------------------------------------------*/ -static unsigned char XGI_XG21GetPSCValue(struct vb_device_info *pVBInfo) -{ - unsigned char CR4A, temp; - - CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A); - xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x23); /* enable GPIO write */ - - temp = xgifb_reg_get(pVBInfo->P3d4, 0x48); - - temp = XG21GPIODataTransfer(temp); - temp &= 0x23; - xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A); - return temp; -} - -/*----------------------------------------------------------------------------*/ -/* output */ -/* bl[5] : LVDS signal */ -/* bl[1] : LVDS backlight */ -/* bl[0] : LVDS VDD */ -/*----------------------------------------------------------------------------*/ -static unsigned char XGI_XG27GetPSCValue(struct vb_device_info *pVBInfo) -{ - unsigned char CR4A, CRB4, temp; - - CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A); - xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x0C); /* enable GPIO write */ - - temp = xgifb_reg_get(pVBInfo->P3d4, 0x48); - - temp &= 0x0C; - temp >>= 2; - xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A); - CRB4 = xgifb_reg_get(pVBInfo->P3d4, 0xB4); - temp |= ((CRB4 & 0x04) << 3); - return temp; -} - -/*----------------------------------------------------------------------------*/ -/* input */ -/* bl[5] : 1;LVDS signal on */ -/* bl[1] : 1;LVDS backlight on */ -/* bl[0] : 1:LVDS VDD on */ -/* bh: 100000b : clear bit 5, to set bit5 */ -/* 000010b : clear bit 1, to set bit1 */ -/* 000001b : clear bit 0, to set bit0 */ -/*----------------------------------------------------------------------------*/ -static void XGI_XG21BLSignalVDD(unsigned short tempbh, unsigned short tempbl, - struct vb_device_info *pVBInfo) -{ - unsigned char CR4A, temp; - - CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A); - tempbh &= 0x23; - tempbl &= 0x23; - xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~tempbh); /* enable GPIO write */ - - if (tempbh & 0x20) { - temp = (tempbl >> 4) & 0x02; - - /* CR B4[1] */ - xgifb_reg_and_or(pVBInfo->P3d4, 0xB4, ~0x02, temp); - - } - - temp = xgifb_reg_get(pVBInfo->P3d4, 0x48); - - temp = XG21GPIODataTransfer(temp); - temp &= ~tempbh; - temp |= tempbl; - xgifb_reg_set(pVBInfo->P3d4, 0x48, temp); -} - -static void XGI_XG27BLSignalVDD(unsigned short tempbh, unsigned short tempbl, - struct vb_device_info *pVBInfo) -{ - unsigned char CR4A, temp; - unsigned short tempbh0, tempbl0; - - tempbh0 = tempbh; - tempbl0 = tempbl; - tempbh0 &= 0x20; - tempbl0 &= 0x20; - tempbh0 >>= 3; - tempbl0 >>= 3; - - if (tempbh & 0x20) { - temp = (tempbl >> 4) & 0x02; - - /* CR B4[1] */ - xgifb_reg_and_or(pVBInfo->P3d4, 0xB4, ~0x02, temp); - - } - xgifb_reg_and_or(pVBInfo->P3d4, 0xB4, ~tempbh0, tempbl0); - - CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A); - tempbh &= 0x03; - tempbl &= 0x03; - tempbh <<= 2; - tempbl <<= 2; /* GPIOC,GPIOD */ - xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~tempbh); /* enable GPIO write */ - xgifb_reg_and_or(pVBInfo->P3d4, 0x48, ~tempbh, tempbl); -} - -static void XGI_DisplayOn(struct xgifb_video_info *xgifb_info, - struct xgi_hw_device_info *pXGIHWDE, - struct vb_device_info *pVBInfo) -{ - - xgifb_reg_and_or(pVBInfo->P3c4, 0x01, 0xDF, 0x00); - if (pXGIHWDE->jChipType == XG21) { - if (pVBInfo->IF_DEF_LVDS == 1) { - if (!(XGI_XG21GetPSCValue(pVBInfo) & 0x1)) { - /* LVDS VDD on */ - XGI_XG21BLSignalVDD(0x01, 0x01, pVBInfo); - mdelay(xgifb_info->lvds_data.PSC_S2); - } - if (!(XGI_XG21GetPSCValue(pVBInfo) & 0x20)) - /* LVDS signal on */ - XGI_XG21BLSignalVDD(0x20, 0x20, pVBInfo); - mdelay(xgifb_info->lvds_data.PSC_S3); - /* LVDS backlight on */ - XGI_XG21BLSignalVDD(0x02, 0x02, pVBInfo); - } else { - /* DVO/DVI signal on */ - XGI_XG21BLSignalVDD(0x20, 0x20, pVBInfo); - } - - } - - if (pXGIHWDE->jChipType == XG27) { - if (pVBInfo->IF_DEF_LVDS == 1) { - if (!(XGI_XG27GetPSCValue(pVBInfo) & 0x1)) { - /* LVDS VDD on */ - XGI_XG27BLSignalVDD(0x01, 0x01, pVBInfo); - mdelay(xgifb_info->lvds_data.PSC_S2); - } - if (!(XGI_XG27GetPSCValue(pVBInfo) & 0x20)) - /* LVDS signal on */ - XGI_XG27BLSignalVDD(0x20, 0x20, pVBInfo); - mdelay(xgifb_info->lvds_data.PSC_S3); - /* LVDS backlight on */ - XGI_XG27BLSignalVDD(0x02, 0x02, pVBInfo); - } else { - /* DVO/DVI signal on */ - XGI_XG27BLSignalVDD(0x20, 0x20, pVBInfo); - } - - } -} - -void XGI_DisplayOff(struct xgifb_video_info *xgifb_info, - struct xgi_hw_device_info *pXGIHWDE, - struct vb_device_info *pVBInfo) -{ - - if (pXGIHWDE->jChipType == XG21) { - if (pVBInfo->IF_DEF_LVDS == 1) { - /* LVDS backlight off */ - XGI_XG21BLSignalVDD(0x02, 0x00, pVBInfo); - mdelay(xgifb_info->lvds_data.PSC_S3); - } else { - /* DVO/DVI signal off */ - XGI_XG21BLSignalVDD(0x20, 0x00, pVBInfo); - } - } - - if (pXGIHWDE->jChipType == XG27) { - if ((XGI_XG27GetPSCValue(pVBInfo) & 0x2)) { - /* LVDS backlight off */ - XGI_XG27BLSignalVDD(0x02, 0x00, pVBInfo); - mdelay(xgifb_info->lvds_data.PSC_S3); - } - - if (pVBInfo->IF_DEF_LVDS == 0) - /* DVO/DVI signal off */ - XGI_XG27BLSignalVDD(0x20, 0x00, pVBInfo); - } - - xgifb_reg_and_or(pVBInfo->P3c4, 0x01, 0xDF, 0x20); -} - -static void XGI_WaitDisply(struct vb_device_info *pVBInfo) -{ - while ((inb(pVBInfo->P3da) & 0x01)) - break; - - while (!(inb(pVBInfo->P3da) & 0x01)) - break; -} - -static void XGI_AutoThreshold(struct vb_device_info *pVBInfo) -{ - xgifb_reg_or(pVBInfo->Part1Port, 0x01, 0x40); -} - -static void XGI_SaveCRT2Info(unsigned short ModeNo, - struct vb_device_info *pVBInfo) -{ - unsigned short temp1, temp2; - - /* reserve CR34 for CRT1 Mode No */ - xgifb_reg_set(pVBInfo->P3d4, 0x34, ModeNo); - temp1 = (pVBInfo->VBInfo & SetInSlaveMode) >> 8; - temp2 = ~(SetInSlaveMode >> 8); - xgifb_reg_and_or(pVBInfo->P3d4, 0x31, temp2, temp1); -} - -static void XGI_GetCRT2ResInfo(unsigned short ModeIdIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short xres, yres, modeflag, resindex; - - resindex = XGI330_EModeIDTable[ModeIdIndex].Ext_RESINFO; - xres = XGI330_ModeResInfo[resindex].HTotal; /* xres->ax */ - yres = XGI330_ModeResInfo[resindex].VTotal; /* yres->bx */ - /* si+St_ModeFlag */ - modeflag = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeFlag; - - if (modeflag & HalfDCLK) - xres *= 2; - - if (modeflag & DoubleScanMode) - yres *= 2; - - if (!(pVBInfo->VBInfo & SetCRT2ToLCD)) - goto exit; - - if (pVBInfo->LCDResInfo == Panel_1600x1200) { - if (!(pVBInfo->LCDInfo & XGI_LCDVESATiming)) { - if (yres == 1024) - yres = 1056; - } - } - - if (pVBInfo->LCDResInfo == Panel_1280x1024) { - if (yres == 400) - yres = 405; - else if (yres == 350) - yres = 360; - - if (pVBInfo->LCDInfo & XGI_LCDVESATiming) { - if (yres == 360) - yres = 375; - } - } - - if (pVBInfo->LCDResInfo == Panel_1024x768) { - if (!(pVBInfo->LCDInfo & XGI_LCDVESATiming)) { - if (!(pVBInfo->LCDInfo & LCDNonExpanding)) { - if (yres == 350) - yres = 357; - else if (yres == 400) - yres = 420; - else if (yres == 480) - yres = 525; - } - } - } - - if (xres == 720) - xres = 640; - -exit: - pVBInfo->VGAHDE = xres; - pVBInfo->HDE = xres; - pVBInfo->VGAVDE = yres; - pVBInfo->VDE = yres; -} - -static unsigned char XGI_IsLCDDualLink(struct vb_device_info *pVBInfo) -{ - - if ((pVBInfo->VBInfo & (SetCRT2ToLCD | XGI_SetCRT2ToLCDA)) && - (pVBInfo->LCDInfo & SetLCDDualLink)) /* shampoo0129 */ - return 1; - - return 0; -} - -static void XGI_GetRAMDAC2DATA(unsigned short ModeIdIndex, - unsigned short RefreshRateTableIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short tempax, tempbx, temp1, temp2, modeflag = 0, tempcx, - CRT1Index; - - pVBInfo->RVBHCMAX = 1; - pVBInfo->RVBHCFACT = 1; - modeflag = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeFlag; - CRT1Index = XGI330_RefIndex[RefreshRateTableIndex].Ext_CRT1CRTC; - CRT1Index &= IndexMask; - temp1 = (unsigned short) XGI_CRT1Table[CRT1Index].CR[0]; - temp2 = (unsigned short) XGI_CRT1Table[CRT1Index].CR[5]; - tempax = (temp1 & 0xFF) | ((temp2 & 0x03) << 8); - tempbx = (unsigned short) XGI_CRT1Table[CRT1Index].CR[8]; - tempcx = (unsigned short) - XGI_CRT1Table[CRT1Index].CR[14] << 8; - tempcx &= 0x0100; - tempcx = tempcx << 2; - tempbx |= tempcx; - temp1 = (unsigned short) XGI_CRT1Table[CRT1Index].CR[9]; - - if (temp1 & 0x01) - tempbx |= 0x0100; - - if (temp1 & 0x20) - tempbx |= 0x0200; - tempax += 5; - - if (modeflag & Charx8Dot) - tempax *= 8; - else - tempax *= 9; - - pVBInfo->VGAHT = tempax; - pVBInfo->HT = tempax; - tempbx++; - pVBInfo->VGAVT = tempbx; - pVBInfo->VT = tempbx; -} - -static void XGI_GetCRT2Data(unsigned short ModeIdIndex, - unsigned short RefreshRateTableIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short tempax = 0, tempbx = 0, modeflag, resinfo; - - struct SiS_LCDData const *LCDPtr = NULL; - - /* si+Ext_ResInfo */ - modeflag = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeFlag; - resinfo = XGI330_EModeIDTable[ModeIdIndex].Ext_RESINFO; - pVBInfo->NewFlickerMode = 0; - pVBInfo->RVBHRS = 50; - - if (pVBInfo->VBInfo & SetCRT2ToRAMDAC) { - XGI_GetRAMDAC2DATA(ModeIdIndex, RefreshRateTableIndex, pVBInfo); - return; - } - - if (pVBInfo->VBInfo & (SetCRT2ToLCD | XGI_SetCRT2ToLCDA)) { - LCDPtr = XGI_GetLcdPtr(XGI_LCDDataTable, ModeIdIndex, - pVBInfo); - - pVBInfo->RVBHCMAX = LCDPtr->RVBHCMAX; - pVBInfo->RVBHCFACT = LCDPtr->RVBHCFACT; - pVBInfo->VGAHT = LCDPtr->VGAHT; - pVBInfo->VGAVT = LCDPtr->VGAVT; - pVBInfo->HT = LCDPtr->LCDHT; - pVBInfo->VT = LCDPtr->LCDVT; - - if (pVBInfo->LCDResInfo == Panel_1024x768) { - tempax = 1024; - tempbx = 768; - - if (!(pVBInfo->LCDInfo & XGI_LCDVESATiming)) { - if (pVBInfo->VGAVDE == 357) - tempbx = 527; - else if (pVBInfo->VGAVDE == 420) - tempbx = 620; - else if (pVBInfo->VGAVDE == 525) - tempbx = 775; - else if (pVBInfo->VGAVDE == 600) - tempbx = 775; - } - } else if (pVBInfo->LCDResInfo == Panel_1024x768x75) { - tempax = 1024; - tempbx = 768; - } else if (pVBInfo->LCDResInfo == Panel_1280x1024) { - tempax = 1280; - if (pVBInfo->VGAVDE == 360) - tempbx = 768; - else if (pVBInfo->VGAVDE == 375) - tempbx = 800; - else if (pVBInfo->VGAVDE == 405) - tempbx = 864; - else - tempbx = 1024; - } else if (pVBInfo->LCDResInfo == Panel_1280x1024x75) { - tempax = 1280; - tempbx = 1024; - } else if (pVBInfo->LCDResInfo == Panel_1280x960) { - tempax = 1280; - if (pVBInfo->VGAVDE == 350) - tempbx = 700; - else if (pVBInfo->VGAVDE == 400) - tempbx = 800; - else if (pVBInfo->VGAVDE == 1024) - tempbx = 960; - else - tempbx = 960; - } else if (pVBInfo->LCDResInfo == Panel_1400x1050) { - tempax = 1400; - tempbx = 1050; - - if (pVBInfo->VGAVDE == 1024) { - tempax = 1280; - tempbx = 1024; - } - } else if (pVBInfo->LCDResInfo == Panel_1600x1200) { - tempax = 1600; - tempbx = 1200; /* alan 10/14/2003 */ - if (!(pVBInfo->LCDInfo & XGI_LCDVESATiming)) { - if (pVBInfo->VGAVDE == 350) - tempbx = 875; - else if (pVBInfo->VGAVDE == 400) - tempbx = 1000; - } - } - - if (pVBInfo->LCDInfo & LCDNonExpanding) { - tempax = pVBInfo->VGAHDE; - tempbx = pVBInfo->VGAVDE; - } - - pVBInfo->HDE = tempax; - pVBInfo->VDE = tempbx; - return; - } - - if (pVBInfo->VBInfo & (SetCRT2ToTV)) { - struct SiS_TVData const *TVPtr; - - TVPtr = XGI_GetTVPtr(ModeIdIndex, RefreshRateTableIndex, - pVBInfo); - - pVBInfo->RVBHCMAX = TVPtr->RVBHCMAX; - pVBInfo->RVBHCFACT = TVPtr->RVBHCFACT; - pVBInfo->VGAHT = TVPtr->VGAHT; - pVBInfo->VGAVT = TVPtr->VGAVT; - pVBInfo->HDE = TVPtr->TVHDE; - pVBInfo->VDE = TVPtr->TVVDE; - pVBInfo->RVBHRS = TVPtr->RVBHRS; - pVBInfo->NewFlickerMode = TVPtr->FlickerMode; - - if (pVBInfo->VBInfo & SetCRT2ToHiVision) { - if (resinfo == 0x08) - pVBInfo->NewFlickerMode = 0x40; - else if (resinfo == 0x09) - pVBInfo->NewFlickerMode = 0x40; - else if (resinfo == 0x12) - pVBInfo->NewFlickerMode = 0x40; - - if (pVBInfo->VGAVDE == 350) - pVBInfo->TVInfo |= TVSimuMode; - - tempax = ExtHiTVHT; - tempbx = ExtHiTVVT; - - if (pVBInfo->VBInfo & SetInSlaveMode) { - if (pVBInfo->TVInfo & TVSimuMode) { - tempax = StHiTVHT; - tempbx = StHiTVVT; - - if (!(modeflag & Charx8Dot)) { - tempax = StHiTextTVHT; - tempbx = StHiTextTVVT; - } - } - } - } else if (pVBInfo->VBInfo & SetCRT2ToYPbPr525750) { - if (pVBInfo->TVInfo & TVSetYPbPr750p) { - tempax = YPbPrTV750pHT; /* Ext750pTVHT */ - tempbx = YPbPrTV750pVT; /* Ext750pTVVT */ - } - - if (pVBInfo->TVInfo & TVSetYPbPr525p) { - tempax = YPbPrTV525pHT; /* Ext525pTVHT */ - tempbx = YPbPrTV525pVT; /* Ext525pTVVT */ - } else if (pVBInfo->TVInfo & TVSetYPbPr525i) { - tempax = YPbPrTV525iHT; /* Ext525iTVHT */ - tempbx = YPbPrTV525iVT; /* Ext525iTVVT */ - if (pVBInfo->TVInfo & NTSC1024x768) - tempax = NTSC1024x768HT; - } - } else { - tempax = PALHT; - tempbx = PALVT; - if (!(pVBInfo->TVInfo & TVSetPAL)) { - tempax = NTSCHT; - tempbx = NTSCVT; - if (pVBInfo->TVInfo & NTSC1024x768) - tempax = NTSC1024x768HT; - } - } - - pVBInfo->HT = tempax; - pVBInfo->VT = tempbx; - } -} - -static void XGI_SetCRT2VCLK(unsigned short ModeIdIndex, - unsigned short RefreshRateTableIndex, - struct vb_device_info *pVBInfo) -{ - unsigned char di_0, di_1, tempal; - - tempal = XGI_GetVCLKPtr(RefreshRateTableIndex, ModeIdIndex, pVBInfo); - XGI_GetVCLKLen(tempal, &di_0, &di_1, pVBInfo); - XGI_GetLCDVCLKPtr(&di_0, &di_1, pVBInfo); - - if (pVBInfo->VBType & VB_SIS301) { /* shampoo 0129 */ - /* 301 */ - xgifb_reg_set(pVBInfo->Part4Port, 0x0A, 0x10); - xgifb_reg_set(pVBInfo->Part4Port, 0x0B, di_1); - xgifb_reg_set(pVBInfo->Part4Port, 0x0A, di_0); - } else { /* 301b/302b/301lv/302lv */ - xgifb_reg_set(pVBInfo->Part4Port, 0x0A, di_0); - xgifb_reg_set(pVBInfo->Part4Port, 0x0B, di_1); - } - - xgifb_reg_set(pVBInfo->Part4Port, 0x00, 0x12); - - if (pVBInfo->VBInfo & SetCRT2ToRAMDAC) - xgifb_reg_or(pVBInfo->Part4Port, 0x12, 0x28); - else - xgifb_reg_or(pVBInfo->Part4Port, 0x12, 0x08); -} - -static unsigned short XGI_GetColorDepth(unsigned short ModeIdIndex) -{ - unsigned short ColorDepth[6] = { 1, 2, 4, 4, 6, 8 }; - short index; - unsigned short modeflag; - - modeflag = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeFlag; - index = (modeflag & ModeTypeMask) - ModeEGA; - - if (index < 0) - index = 0; - - return ColorDepth[index]; -} - -static unsigned short XGI_GetOffset(unsigned short ModeNo, - unsigned short ModeIdIndex, - unsigned short RefreshRateTableIndex) -{ - unsigned short temp, colordepth, modeinfo, index, infoflag, - ColorDepth[] = { 0x01, 0x02, 0x04 }; - - modeinfo = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeInfo; - infoflag = XGI330_RefIndex[RefreshRateTableIndex].Ext_InfoFlag; - - index = (modeinfo >> 8) & 0xFF; - - temp = XGI330_ScreenOffset[index]; - - if (infoflag & InterlaceMode) - temp = temp << 1; - - colordepth = XGI_GetColorDepth(ModeIdIndex); - - if ((ModeNo >= 0x7C) && (ModeNo <= 0x7E)) { - temp = ModeNo - 0x7C; - colordepth = ColorDepth[temp]; - temp = 0x6B; - if (infoflag & InterlaceMode) - temp = temp << 1; - } - return temp * colordepth; -} - -static void XGI_SetCRT2Offset(unsigned short ModeNo, - unsigned short ModeIdIndex, - unsigned short RefreshRateTableIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short offset; - unsigned char temp; - - if (pVBInfo->VBInfo & SetInSlaveMode) - return; - - offset = XGI_GetOffset(ModeNo, ModeIdIndex, RefreshRateTableIndex); - temp = (unsigned char) (offset & 0xFF); - xgifb_reg_set(pVBInfo->Part1Port, 0x07, temp); - temp = (unsigned char) ((offset & 0xFF00) >> 8); - xgifb_reg_set(pVBInfo->Part1Port, 0x09, temp); - temp = (unsigned char) (((offset >> 3) & 0xFF) + 1); - xgifb_reg_set(pVBInfo->Part1Port, 0x03, temp); -} - -static void XGI_SetCRT2FIFO(struct vb_device_info *pVBInfo) -{ - /* threshold high, disable auto threshold */ - xgifb_reg_set(pVBInfo->Part1Port, 0x01, 0x3B); - /* threshold low default 04h */ - xgifb_reg_and_or(pVBInfo->Part1Port, 0x02, ~(0x3F), 0x04); -} - -static void XGI_PreSetGroup1(unsigned short ModeNo, unsigned short ModeIdIndex, - unsigned short RefreshRateTableIndex, - struct vb_device_info *pVBInfo) -{ - u8 tempcx; - - XGI_SetCRT2Offset(ModeNo, ModeIdIndex, RefreshRateTableIndex, pVBInfo); - XGI_SetCRT2FIFO(pVBInfo); - - for (tempcx = 4; tempcx < 7; tempcx++) - xgifb_reg_set(pVBInfo->Part1Port, tempcx, 0x0); - - xgifb_reg_set(pVBInfo->Part1Port, 0x50, 0x00); - xgifb_reg_set(pVBInfo->Part1Port, 0x02, 0x44); /* temp 0206 */ -} - -static void XGI_SetGroup1(unsigned short ModeIdIndex, - unsigned short RefreshRateTableIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short temp = 0, tempax = 0, tempbx = 0, tempcx = 0, - pushbx = 0, CRT1Index, modeflag; - - CRT1Index = XGI330_RefIndex[RefreshRateTableIndex].Ext_CRT1CRTC; - CRT1Index &= IndexMask; - modeflag = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeFlag; - - /* bainy change table name */ - if (modeflag & HalfDCLK) { - /* BTVGA2HT 0x08,0x09 */ - temp = (pVBInfo->VGAHT / 2 - 1) & 0x0FF; - xgifb_reg_set(pVBInfo->Part1Port, 0x08, temp); - temp = (((pVBInfo->VGAHT / 2 - 1) & 0xFF00) >> 8) << 4; - xgifb_reg_and_or(pVBInfo->Part1Port, 0x09, ~0x0F0, temp); - /* BTVGA2HDEE 0x0A,0x0C */ - temp = (pVBInfo->VGAHDE / 2 + 16) & 0x0FF; - xgifb_reg_set(pVBInfo->Part1Port, 0x0A, temp); - tempcx = ((pVBInfo->VGAHT - pVBInfo->VGAHDE) / 2) >> 2; - pushbx = pVBInfo->VGAHDE / 2 + 16; - tempcx = tempcx >> 1; - tempbx = pushbx + tempcx; /* bx BTVGA@HRS 0x0B,0x0C */ - tempcx += tempbx; - - if (pVBInfo->VBInfo & SetCRT2ToRAMDAC) { - tempbx = XGI_CRT1Table[CRT1Index].CR[4]; - tempbx |= ((XGI_CRT1Table[CRT1Index].CR[14] & - 0xC0) << 2); - tempbx = (tempbx - 3) << 3; /* (VGAHRS-3)*8 */ - tempcx = XGI_CRT1Table[CRT1Index].CR[5]; - tempcx &= 0x1F; - temp = XGI_CRT1Table[CRT1Index].CR[15]; - temp = (temp & 0x04) << (5 - 2); /* VGAHRE D[5] */ - tempcx = ((tempcx | temp) - 3) << 3; /* (VGAHRE-3)*8 */ - } - - tempbx += 4; - tempcx += 4; - - if (tempcx > (pVBInfo->VGAHT / 2)) - tempcx = pVBInfo->VGAHT / 2; - - temp = tempbx & 0x00FF; - - xgifb_reg_set(pVBInfo->Part1Port, 0x0B, temp); - } else { - temp = (pVBInfo->VGAHT - 1) & 0x0FF; /* BTVGA2HT 0x08,0x09 */ - xgifb_reg_set(pVBInfo->Part1Port, 0x08, temp); - temp = (((pVBInfo->VGAHT - 1) & 0xFF00) >> 8) << 4; - xgifb_reg_and_or(pVBInfo->Part1Port, 0x09, ~0x0F0, temp); - /* BTVGA2HDEE 0x0A,0x0C */ - temp = (pVBInfo->VGAHDE + 16) & 0x0FF; - xgifb_reg_set(pVBInfo->Part1Port, 0x0A, temp); - tempcx = (pVBInfo->VGAHT - pVBInfo->VGAHDE) >> 2; /* cx */ - pushbx = pVBInfo->VGAHDE + 16; - tempcx = tempcx >> 1; - tempbx = pushbx + tempcx; /* bx BTVGA@HRS 0x0B,0x0C */ - tempcx += tempbx; - - if (pVBInfo->VBInfo & SetCRT2ToRAMDAC) { - tempbx = XGI_CRT1Table[CRT1Index].CR[3]; - tempbx |= ((XGI_CRT1Table[CRT1Index].CR[5] & - 0xC0) << 2); - tempbx = (tempbx - 3) << 3; /* (VGAHRS-3)*8 */ - tempcx = XGI_CRT1Table[CRT1Index].CR[4]; - tempcx &= 0x1F; - temp = XGI_CRT1Table[CRT1Index].CR[6]; - temp = (temp & 0x04) << (5 - 2); /* VGAHRE D[5] */ - tempcx = ((tempcx | temp) - 3) << 3; /* (VGAHRE-3)*8 */ - tempbx += 16; - tempcx += 16; - } - - if (tempcx > pVBInfo->VGAHT) - tempcx = pVBInfo->VGAHT; - - temp = tempbx & 0x00FF; - xgifb_reg_set(pVBInfo->Part1Port, 0x0B, temp); - } - - tempax = (tempax & 0x00FF) | (tempbx & 0xFF00); - tempbx = pushbx; - tempbx = (tempbx & 0x00FF) | ((tempbx & 0xFF00) << 4); - tempax |= (tempbx & 0xFF00); - temp = (tempax & 0xFF00) >> 8; - xgifb_reg_set(pVBInfo->Part1Port, 0x0C, temp); - temp = tempcx & 0x00FF; - xgifb_reg_set(pVBInfo->Part1Port, 0x0D, temp); - tempcx = (pVBInfo->VGAVT - 1); - temp = tempcx & 0x00FF; - - xgifb_reg_set(pVBInfo->Part1Port, 0x0E, temp); - tempbx = pVBInfo->VGAVDE - 1; - temp = tempbx & 0x00FF; - xgifb_reg_set(pVBInfo->Part1Port, 0x0F, temp); - temp = ((tempbx & 0xFF00) << 3) >> 8; - temp |= ((tempcx & 0xFF00) >> 8); - xgifb_reg_set(pVBInfo->Part1Port, 0x12, temp); - - /* BTVGA2VRS 0x10,0x11 */ - tempbx = (pVBInfo->VGAVT + pVBInfo->VGAVDE) >> 1; - /* BTVGA2VRE 0x11 */ - tempcx = ((pVBInfo->VGAVT - pVBInfo->VGAVDE) >> 4) + tempbx + 1; - - if (pVBInfo->VBInfo & SetCRT2ToRAMDAC) { - tempbx = XGI_CRT1Table[CRT1Index].CR[10]; - temp = XGI_CRT1Table[CRT1Index].CR[9]; - - if (temp & 0x04) - tempbx |= 0x0100; - - if (temp & 0x080) - tempbx |= 0x0200; - - temp = XGI_CRT1Table[CRT1Index].CR[14]; - - if (temp & 0x08) - tempbx |= 0x0400; - - temp = XGI_CRT1Table[CRT1Index].CR[11]; - tempcx = (tempcx & 0xFF00) | (temp & 0x00FF); - } - - temp = tempbx & 0x00FF; - xgifb_reg_set(pVBInfo->Part1Port, 0x10, temp); - temp = ((tempbx & 0xFF00) >> 8) << 4; - temp = ((tempcx & 0x000F) | (temp)); - xgifb_reg_set(pVBInfo->Part1Port, 0x11, temp); - tempax = 0; - - if (modeflag & DoubleScanMode) - tempax |= 0x80; - - if (modeflag & HalfDCLK) - tempax |= 0x40; - - xgifb_reg_and_or(pVBInfo->Part1Port, 0x2C, ~0x0C0, tempax); -} - -static unsigned short XGI_GetVGAHT2(struct vb_device_info *pVBInfo) -{ - unsigned long tempax, tempbx; - - tempbx = ((pVBInfo->VGAVT - pVBInfo->VGAVDE) * pVBInfo->RVBHCMAX) - & 0xFFFF; - tempax = (pVBInfo->VT - pVBInfo->VDE) * pVBInfo->RVBHCFACT; - tempax = (tempax * pVBInfo->HT) / tempbx; - - return (unsigned short) tempax; -} - -static void XGI_SetLockRegs(unsigned short ModeNo, unsigned short ModeIdIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short push1, push2, tempax, tempbx = 0, tempcx, temp, resinfo, - modeflag; - - /* si+Ext_ResInfo */ - modeflag = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeFlag; - resinfo = XGI330_EModeIDTable[ModeIdIndex].Ext_RESINFO; - - if (!(pVBInfo->VBInfo & SetInSlaveMode)) - return; - - temp = 0xFF; /* set MAX HT */ - xgifb_reg_set(pVBInfo->Part1Port, 0x03, temp); - tempcx = 0x08; - - if (pVBInfo->VBType & (VB_SIS301LV | VB_SIS302LV | VB_XGI301C)) - modeflag |= Charx8Dot; - - tempax = pVBInfo->VGAHDE; /* 0x04 Horizontal Display End */ - - if (modeflag & HalfDCLK) - tempax = tempax >> 1; - - tempax = (tempax / tempcx) - 1; - tempbx |= ((tempax & 0x00FF) << 8); - temp = tempax & 0x00FF; - xgifb_reg_set(pVBInfo->Part1Port, 0x04, temp); - - temp = (tempbx & 0xFF00) >> 8; - - if (pVBInfo->VBInfo & SetCRT2ToTV) { - if (!(pVBInfo->VBType & (VB_SIS301B | VB_SIS302B | VB_SIS301LV - | VB_SIS302LV | VB_XGI301C))) - temp += 2; - - if ((pVBInfo->VBInfo & SetCRT2ToHiVision) && - !(pVBInfo->VBType & VB_SIS301LV) && (resinfo == 7)) - temp -= 2; - } - - /* 0x05 Horizontal Display Start */ - xgifb_reg_set(pVBInfo->Part1Port, 0x05, temp); - /* 0x06 Horizontal Blank end */ - xgifb_reg_set(pVBInfo->Part1Port, 0x06, 0x03); - - if (!(pVBInfo->VBInfo & DisableCRT2Display)) { /* 030226 bainy */ - if (pVBInfo->VBInfo & SetCRT2ToTV) - tempax = pVBInfo->VGAHT; - else - tempax = XGI_GetVGAHT2(pVBInfo); - } - - if (tempax >= pVBInfo->VGAHT) - tempax = pVBInfo->VGAHT; - - if (modeflag & HalfDCLK) - tempax = tempax >> 1; - - tempax = (tempax / tempcx) - 5; - tempcx = tempax; /* 20030401 0x07 horizontal Retrace Start */ - if (pVBInfo->VBInfo & SetCRT2ToHiVision) { - temp = (tempbx & 0x00FF) - 1; - if (!(modeflag & HalfDCLK)) { - temp -= 6; - if (pVBInfo->TVInfo & TVSimuMode) { - temp -= 4; - temp -= 10; - } - } - } else { - tempbx = (tempbx & 0xFF00) >> 8; - tempcx = (tempcx + tempbx) >> 1; - temp = (tempcx & 0x00FF) + 2; - - if (pVBInfo->VBInfo & SetCRT2ToTV) { - temp -= 1; - if (!(modeflag & HalfDCLK)) { - if ((modeflag & Charx8Dot)) { - temp += 4; - if (pVBInfo->VGAHDE >= 800) - temp -= 6; - } - } - } else if (!(modeflag & HalfDCLK)) { - temp -= 4; - if (pVBInfo->LCDResInfo != Panel_1280x960 && - pVBInfo->VGAHDE >= 800) { - temp -= 7; - if (pVBInfo->VGAHDE >= 1280 && - pVBInfo->LCDResInfo != Panel_1280x960 && - (pVBInfo->LCDInfo & LCDNonExpanding)) - temp += 28; - } - } - } - - /* 0x07 Horizontal Retrace Start */ - xgifb_reg_set(pVBInfo->Part1Port, 0x07, temp); - /* 0x08 Horizontal Retrace End */ - xgifb_reg_set(pVBInfo->Part1Port, 0x08, 0); - - if (pVBInfo->VBInfo & SetCRT2ToTV) { - if (pVBInfo->TVInfo & TVSimuMode) { - if (ModeNo == 0x50) { - if (pVBInfo->TVInfo == SetNTSCTV) { - xgifb_reg_set(pVBInfo->Part1Port, - 0x07, 0x30); - xgifb_reg_set(pVBInfo->Part1Port, - 0x08, 0x03); - } else { - xgifb_reg_set(pVBInfo->Part1Port, - 0x07, 0x2f); - xgifb_reg_set(pVBInfo->Part1Port, - 0x08, 0x02); - } - } - } - } - - xgifb_reg_set(pVBInfo->Part1Port, 0x18, 0x03); /* 0x18 SR0B */ - xgifb_reg_and_or(pVBInfo->Part1Port, 0x19, 0xF0, 0x00); - xgifb_reg_set(pVBInfo->Part1Port, 0x09, 0xFF); /* 0x09 Set Max VT */ - - tempbx = pVBInfo->VGAVT; - push1 = tempbx; - tempcx = 0x121; - tempbx = pVBInfo->VGAVDE; /* 0x0E Virtical Display End */ - - if (tempbx == 357) - tempbx = 350; - if (tempbx == 360) - tempbx = 350; - if (tempbx == 375) - tempbx = 350; - if (tempbx == 405) - tempbx = 400; - if (tempbx == 525) - tempbx = 480; - - push2 = tempbx; - - if (pVBInfo->VBInfo & SetCRT2ToLCD) { - if (pVBInfo->LCDResInfo == Panel_1024x768) { - if (!(pVBInfo->LCDInfo & XGI_LCDVESATiming)) { - if (tempbx == 350) - tempbx += 5; - if (tempbx == 480) - tempbx += 5; - } - } - } - tempbx--; - tempbx--; - temp = tempbx & 0x00FF; - /* 0x10 vertical Blank Start */ - xgifb_reg_set(pVBInfo->Part1Port, 0x10, temp); - tempbx = push2; - tempbx--; - temp = tempbx & 0x00FF; - xgifb_reg_set(pVBInfo->Part1Port, 0x0E, temp); - - if (tempbx & 0x0100) - tempcx |= 0x0002; - - tempax = 0x000B; - - if (modeflag & DoubleScanMode) - tempax |= 0x08000; - - if (tempbx & 0x0200) - tempcx |= 0x0040; - - temp = (tempax & 0xFF00) >> 8; - xgifb_reg_set(pVBInfo->Part1Port, 0x0B, temp); - - if (tempbx & 0x0400) - tempcx |= 0x0600; - - /* 0x11 Vertival Blank End */ - xgifb_reg_set(pVBInfo->Part1Port, 0x11, 0x00); - - tempax = push1; - tempax -= tempbx; /* 0x0C Vertical Retrace Start */ - tempax = tempax >> 2; - push1 = tempax; /* push ax */ - - if (resinfo != 0x09) { - tempax = tempax << 1; - tempbx += tempax; - } - - if (pVBInfo->VBInfo & SetCRT2ToHiVision) { - if ((pVBInfo->VBType & VB_SIS301LV) && - !(pVBInfo->TVInfo & TVSetHiVision)) { - if ((pVBInfo->TVInfo & TVSimuMode) && - (pVBInfo->TVInfo & TVSetPAL)) { - if (!(pVBInfo->VBType & VB_SIS301LV) || - !(pVBInfo->TVInfo & - (TVSetYPbPr525p | - TVSetYPbPr750p | - TVSetHiVision))) - tempbx += 40; - } - } else { - tempbx -= 10; - } - } else if (pVBInfo->TVInfo & TVSimuMode) { - if (pVBInfo->TVInfo & TVSetPAL) { - if (pVBInfo->VBType & VB_SIS301LV) { - if (!(pVBInfo->TVInfo & - (TVSetYPbPr525p | - TVSetYPbPr750p | - TVSetHiVision))) - tempbx += 40; - } else { - tempbx += 40; - } - } - } - tempax = push1; - tempax = tempax >> 2; - tempax++; - tempax += tempbx; - push1 = tempax; /* push ax */ - - if ((pVBInfo->TVInfo & TVSetPAL)) { - if (tempbx <= 513) { - if (tempax >= 513) - tempbx = 513; - } - } - - temp = tempbx & 0x00FF; - xgifb_reg_set(pVBInfo->Part1Port, 0x0C, temp); - tempbx--; - temp = tempbx & 0x00FF; - xgifb_reg_set(pVBInfo->Part1Port, 0x10, temp); - - if (tempbx & 0x0100) - tempcx |= 0x0008; - - if (tempbx & 0x0200) - xgifb_reg_and_or(pVBInfo->Part1Port, 0x0B, 0x0FF, 0x20); - - tempbx++; - - if (tempbx & 0x0100) - tempcx |= 0x0004; - - if (tempbx & 0x0200) - tempcx |= 0x0080; - - if (tempbx & 0x0400) - tempcx |= 0x0C00; - - tempbx = push1; /* pop ax */ - temp = tempbx & 0x00FF; - temp &= 0x0F; - /* 0x0D vertical Retrace End */ - xgifb_reg_set(pVBInfo->Part1Port, 0x0D, temp); - - if (tempbx & 0x0010) - tempcx |= 0x2000; - - temp = tempcx & 0x00FF; - xgifb_reg_set(pVBInfo->Part1Port, 0x0A, temp); /* 0x0A CR07 */ - temp = (tempcx & 0x0FF00) >> 8; - xgifb_reg_set(pVBInfo->Part1Port, 0x17, temp); /* 0x17 SR0A */ - tempax = modeflag; - temp = (tempax & 0xFF00) >> 8; - - temp = (temp >> 1) & 0x09; - - if (pVBInfo->VBType & (VB_SIS301LV | VB_SIS302LV | VB_XGI301C)) - temp |= 0x01; - - xgifb_reg_set(pVBInfo->Part1Port, 0x16, temp); /* 0x16 SR01 */ - xgifb_reg_set(pVBInfo->Part1Port, 0x0F, 0); /* 0x0F CR14 */ - xgifb_reg_set(pVBInfo->Part1Port, 0x12, 0); /* 0x12 CR17 */ - - if (pVBInfo->LCDInfo & LCDRGB18Bit) - temp = 0x80; - else - temp = 0x00; - - xgifb_reg_set(pVBInfo->Part1Port, 0x1A, temp); /* 0x1A SR0E */ -} - -static void XGI_SetGroup2(unsigned short ModeNo, unsigned short ModeIdIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short i, j, tempax, tempbx, tempcx, temp, push1, push2, - modeflag; - unsigned char const *TimingPoint; - - unsigned long longtemp, tempeax, tempebx, temp2, tempecx; - - /* si+Ext_ResInfo */ - modeflag = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeFlag; - - tempax = 0; - - if (!(pVBInfo->VBInfo & SetCRT2ToAVIDEO)) - tempax |= 0x0800; - - if (!(pVBInfo->VBInfo & SetCRT2ToSVIDEO)) - tempax |= 0x0400; - - if (pVBInfo->VBInfo & SetCRT2ToSCART) - tempax |= 0x0200; - - if (!(pVBInfo->TVInfo & TVSetPAL)) - tempax |= 0x1000; - - if (pVBInfo->VBInfo & SetCRT2ToHiVision) - tempax |= 0x0100; - - if (pVBInfo->TVInfo & (TVSetYPbPr525p | TVSetYPbPr750p)) - tempax &= 0xfe00; - - tempax = (tempax & 0xff00) >> 8; - - xgifb_reg_set(pVBInfo->Part2Port, 0x0, tempax); - TimingPoint = XGI330_NTSCTiming; - - if (pVBInfo->TVInfo & TVSetPAL) - TimingPoint = XGI330_PALTiming; - - if (pVBInfo->VBInfo & SetCRT2ToHiVision) { - TimingPoint = XGI330_HiTVExtTiming; - - if (pVBInfo->VBInfo & SetInSlaveMode) - TimingPoint = XGI330_HiTVSt2Timing; - - if (pVBInfo->SetFlag & TVSimuMode) - TimingPoint = XGI330_HiTVSt1Timing; - - if (!(modeflag & Charx8Dot)) - TimingPoint = XGI330_HiTVTextTiming; - } - - if (pVBInfo->VBInfo & SetCRT2ToYPbPr525750) { - if (pVBInfo->TVInfo & TVSetYPbPr525i) - TimingPoint = XGI330_YPbPr525iTiming; - - if (pVBInfo->TVInfo & TVSetYPbPr525p) - TimingPoint = XGI330_YPbPr525pTiming; - - if (pVBInfo->TVInfo & TVSetYPbPr750p) - TimingPoint = XGI330_YPbPr750pTiming; - } - - for (i = 0x01, j = 0; i <= 0x2D; i++, j++) - xgifb_reg_set(pVBInfo->Part2Port, i, TimingPoint[j]); - - for (i = 0x39; i <= 0x45; i++, j++) - /* di->temp2[j] */ - xgifb_reg_set(pVBInfo->Part2Port, i, TimingPoint[j]); - - if (pVBInfo->VBInfo & SetCRT2ToTV) - xgifb_reg_and_or(pVBInfo->Part2Port, 0x3A, 0x1F, 0x00); - - temp = pVBInfo->NewFlickerMode; - temp &= 0x80; - xgifb_reg_and_or(pVBInfo->Part2Port, 0x0A, 0xFF, temp); - - if (pVBInfo->TVInfo & TVSetPAL) - tempax = 520; - else - tempax = 440; - - if (pVBInfo->VDE <= tempax) { - tempax -= pVBInfo->VDE; - tempax = tempax >> 2; - tempax = (tempax & 0x00FF) | ((tempax & 0x00FF) << 8); - push1 = tempax; - temp = (tempax & 0xFF00) >> 8; - temp += (unsigned short) TimingPoint[0]; - - if (pVBInfo->VBType & (VB_SIS301B | VB_SIS302B | VB_SIS301LV - | VB_SIS302LV | VB_XGI301C)) { - if (pVBInfo->VBInfo & (SetCRT2ToAVIDEO - | SetCRT2ToSVIDEO | SetCRT2ToSCART - | SetCRT2ToYPbPr525750)) { - tempcx = pVBInfo->VGAHDE; - if (tempcx >= 1024) { - temp = 0x17; /* NTSC */ - if (pVBInfo->TVInfo & TVSetPAL) - temp = 0x19; /* PAL */ - } - } - } - - xgifb_reg_set(pVBInfo->Part2Port, 0x01, temp); - tempax = push1; - temp = (tempax & 0xFF00) >> 8; - temp += TimingPoint[1]; - - if (pVBInfo->VBType & (VB_SIS301B | VB_SIS302B | VB_SIS301LV - | VB_SIS302LV | VB_XGI301C)) { - if ((pVBInfo->VBInfo & (SetCRT2ToAVIDEO - | SetCRT2ToSVIDEO | SetCRT2ToSCART - | SetCRT2ToYPbPr525750))) { - tempcx = pVBInfo->VGAHDE; - if (tempcx >= 1024) { - temp = 0x1D; /* NTSC */ - if (pVBInfo->TVInfo & TVSetPAL) - temp = 0x52; /* PAL */ - } - } - } - xgifb_reg_set(pVBInfo->Part2Port, 0x02, temp); - } - - /* 301b */ - tempcx = pVBInfo->HT; - - if (XGI_IsLCDDualLink(pVBInfo)) - tempcx = tempcx >> 1; - - tempcx -= 2; - temp = tempcx & 0x00FF; - xgifb_reg_set(pVBInfo->Part2Port, 0x1B, temp); - - temp = (tempcx & 0xFF00) >> 8; - xgifb_reg_and_or(pVBInfo->Part2Port, 0x1D, ~0x0F, temp); - - tempcx = pVBInfo->HT >> 1; - push1 = tempcx; /* push cx */ - tempcx += 7; - - if (pVBInfo->VBInfo & SetCRT2ToHiVision) - tempcx -= 4; - - temp = tempcx & 0x00FF; - temp = temp << 4; - xgifb_reg_and_or(pVBInfo->Part2Port, 0x22, 0x0F, temp); - - tempbx = TimingPoint[j] | ((TimingPoint[j + 1]) << 8); - tempbx += tempcx; - push2 = tempbx; - temp = tempbx & 0x00FF; - xgifb_reg_set(pVBInfo->Part2Port, 0x24, temp); - temp = (tempbx & 0xFF00) >> 8; - temp = temp << 4; - xgifb_reg_and_or(pVBInfo->Part2Port, 0x25, 0x0F, temp); - - tempbx = push2; - tempbx = tempbx + 8; - if (pVBInfo->VBInfo & SetCRT2ToHiVision) { - tempbx = tempbx - 4; - tempcx = tempbx; - } - - temp = (tempbx & 0x00FF) << 4; - xgifb_reg_and_or(pVBInfo->Part2Port, 0x29, 0x0F, temp); - - j += 2; - tempcx += (TimingPoint[j] | ((TimingPoint[j + 1]) << 8)); - temp = tempcx & 0x00FF; - xgifb_reg_set(pVBInfo->Part2Port, 0x27, temp); - temp = ((tempcx & 0xFF00) >> 8) << 4; - xgifb_reg_and_or(pVBInfo->Part2Port, 0x28, 0x0F, temp); - - tempcx += 8; - if (pVBInfo->VBInfo & SetCRT2ToHiVision) - tempcx -= 4; - - temp = tempcx & 0xFF; - temp = temp << 4; - xgifb_reg_and_or(pVBInfo->Part2Port, 0x2A, 0x0F, temp); - - tempcx = push1; /* pop cx */ - j += 2; - temp = TimingPoint[j] | ((TimingPoint[j + 1]) << 8); - tempcx -= temp; - temp = tempcx & 0x00FF; - temp = temp << 4; - xgifb_reg_and_or(pVBInfo->Part2Port, 0x2D, 0x0F, temp); - - tempcx -= 11; - - if (!(pVBInfo->VBInfo & SetCRT2ToTV)) { - tempax = XGI_GetVGAHT2(pVBInfo); - tempcx = tempax - 1; - } - temp = tempcx & 0x00FF; - xgifb_reg_set(pVBInfo->Part2Port, 0x2E, temp); - - tempbx = pVBInfo->VDE; - - if (pVBInfo->VGAVDE == 360) - tempbx = 746; - if (pVBInfo->VGAVDE == 375) - tempbx = 746; - if (pVBInfo->VGAVDE == 405) - tempbx = 853; - - if (pVBInfo->VBInfo & SetCRT2ToTV) { - if (pVBInfo->VBType & - (VB_SIS301LV | VB_SIS302LV | VB_XGI301C)) { - if (!(pVBInfo->TVInfo & - (TVSetYPbPr525p | TVSetYPbPr750p))) - tempbx = tempbx >> 1; - } else - tempbx = tempbx >> 1; - } - - tempbx -= 2; - temp = tempbx & 0x00FF; - - if (pVBInfo->VBInfo & SetCRT2ToHiVision) { - if (pVBInfo->VBType & VB_SIS301LV) { - if (pVBInfo->TVInfo & TVSetHiVision) { - if (pVBInfo->VBInfo & SetInSlaveMode) { - if (ModeNo == 0x2f) - temp += 1; - } - } - } else if (pVBInfo->VBInfo & SetInSlaveMode) { - if (ModeNo == 0x2f) - temp += 1; - } - } - - xgifb_reg_set(pVBInfo->Part2Port, 0x2F, temp); - - temp = (tempcx & 0xFF00) >> 8; - temp |= ((tempbx & 0xFF00) >> 8) << 6; - - if (!(pVBInfo->VBInfo & SetCRT2ToHiVision)) { - if (pVBInfo->VBType & VB_SIS301LV) { - if (pVBInfo->TVInfo & TVSetHiVision) { - temp |= 0x10; - - if (!(pVBInfo->VBInfo & SetCRT2ToSVIDEO)) - temp |= 0x20; - } - } else { - temp |= 0x10; - if (!(pVBInfo->VBInfo & SetCRT2ToSVIDEO)) - temp |= 0x20; - } - } - - xgifb_reg_set(pVBInfo->Part2Port, 0x30, temp); - - if (pVBInfo->VBType & (VB_SIS301B | VB_SIS302B | VB_SIS301LV - | VB_SIS302LV | VB_XGI301C)) { /* TV gatingno */ - tempbx = pVBInfo->VDE; - tempcx = tempbx - 2; - - if (pVBInfo->VBInfo & SetCRT2ToTV) { - if (!(pVBInfo->TVInfo & (TVSetYPbPr525p - | TVSetYPbPr750p))) - tempbx = tempbx >> 1; - } - - if (pVBInfo->VBType & (VB_SIS302LV | VB_XGI301C)) { - temp = 0; - if (tempcx & 0x0400) - temp |= 0x20; - - if (tempbx & 0x0400) - temp |= 0x40; - - xgifb_reg_set(pVBInfo->Part4Port, 0x10, temp); - } - - temp = (((tempbx - 3) & 0x0300) >> 8) << 5; - xgifb_reg_set(pVBInfo->Part2Port, 0x46, temp); - temp = (tempbx - 3) & 0x00FF; - xgifb_reg_set(pVBInfo->Part2Port, 0x47, temp); - } - - tempbx = tempbx & 0x00FF; - - if (!(modeflag & HalfDCLK)) { - tempcx = pVBInfo->VGAHDE; - if (tempcx >= pVBInfo->HDE) { - tempbx |= 0x2000; - tempax &= 0x00FF; - } - } - - tempcx = 0x0101; - - if (pVBInfo->VBInfo & SetCRT2ToTV) { /*301b*/ - if (pVBInfo->VGAHDE >= 1024) { - tempcx = 0x1920; - if (pVBInfo->VGAHDE >= 1280) { - tempcx = 0x1420; - tempbx = tempbx & 0xDFFF; - } - } - } - - if (!(tempbx & 0x2000)) { - if (modeflag & HalfDCLK) - tempcx = (tempcx & 0xFF00) | ((tempcx & 0x00FF) << 1); - - push1 = tempbx; - tempeax = pVBInfo->VGAHDE; - tempebx = (tempcx & 0xFF00) >> 8; - longtemp = tempeax * tempebx; - tempecx = tempcx & 0x00FF; - longtemp = longtemp / tempecx; - - /* 301b */ - tempecx = 8 * 1024; - - if (pVBInfo->VBType & (VB_SIS301B | VB_SIS302B | VB_SIS301LV - | VB_SIS302LV | VB_XGI301C)) { - tempecx = tempecx * 8; - } - - longtemp = longtemp * tempecx; - tempecx = pVBInfo->HDE; - temp2 = longtemp % tempecx; - tempeax = longtemp / tempecx; - if (temp2 != 0) - tempeax += 1; - - tempax = (unsigned short) tempeax; - - /* 301b */ - if (pVBInfo->VBType & (VB_SIS301B | VB_SIS302B | VB_SIS301LV - | VB_SIS302LV | VB_XGI301C)) { - tempcx = ((tempax & 0xFF00) >> 5) >> 8; - } - /* end 301b */ - - tempbx = push1; - tempbx = (unsigned short) (((tempeax & 0x0000FF00) & 0x1F00) - | (tempbx & 0x00FF)); - tempax = (unsigned short) (((tempeax & 0x000000FF) << 8) - | (tempax & 0x00FF)); - temp = (tempax & 0xFF00) >> 8; - } else { - temp = (tempax & 0x00FF); - } - - xgifb_reg_set(pVBInfo->Part2Port, 0x44, temp); - temp = (tempbx & 0xFF00) >> 8; - xgifb_reg_and_or(pVBInfo->Part2Port, 0x45, ~0x03F, temp); - temp = tempcx & 0x00FF; - - if (tempbx & 0x2000) - temp = 0; - - if (!(pVBInfo->VBInfo & SetCRT2ToLCD)) - temp |= 0x18; - - xgifb_reg_and_or(pVBInfo->Part2Port, 0x46, ~0x1F, temp); - if (pVBInfo->TVInfo & TVSetPAL) { - tempbx = 0x0382; - tempcx = 0x007e; - } else { - tempbx = 0x0369; - tempcx = 0x0061; - } - - temp = tempbx & 0x00FF; - xgifb_reg_set(pVBInfo->Part2Port, 0x4b, temp); - temp = tempcx & 0x00FF; - xgifb_reg_set(pVBInfo->Part2Port, 0x4c, temp); - - temp = ((tempcx & 0xFF00) >> 8) & 0x03; - temp = temp << 2; - temp |= ((tempbx & 0xFF00) >> 8) & 0x03; - - if (pVBInfo->VBInfo & SetCRT2ToYPbPr525750) { - temp |= 0x10; - - if (pVBInfo->TVInfo & TVSetYPbPr525p) - temp |= 0x20; - - if (pVBInfo->TVInfo & TVSetYPbPr750p) - temp |= 0x60; - } - - xgifb_reg_set(pVBInfo->Part2Port, 0x4d, temp); - temp = xgifb_reg_get(pVBInfo->Part2Port, 0x43); /* 301b change */ - xgifb_reg_set(pVBInfo->Part2Port, 0x43, (unsigned short) (temp - 3)); - - if (!(pVBInfo->TVInfo & (TVSetYPbPr525p | TVSetYPbPr750p))) { - if (pVBInfo->TVInfo & NTSC1024x768) { - TimingPoint = XGI_NTSC1024AdjTime; - for (i = 0x1c, j = 0; i <= 0x30; i++, j++) { - xgifb_reg_set(pVBInfo->Part2Port, i, - TimingPoint[j]); - } - xgifb_reg_set(pVBInfo->Part2Port, 0x43, 0x72); - } - } - - /* Modify for 301C PALM Support */ - if (pVBInfo->VBType & VB_XGI301C) { - if (pVBInfo->TVInfo & TVSetPALM) - xgifb_reg_and_or(pVBInfo->Part2Port, 0x4E, ~0x08, - 0x08); /* PALM Mode */ - } - - if (pVBInfo->TVInfo & TVSetPALM) { - tempax = xgifb_reg_get(pVBInfo->Part2Port, 0x01); - tempax--; - xgifb_reg_and(pVBInfo->Part2Port, 0x01, tempax); - - xgifb_reg_and(pVBInfo->Part2Port, 0x00, 0xEF); - } - - if (pVBInfo->VBInfo & SetCRT2ToHiVision) { - if (!(pVBInfo->VBInfo & SetInSlaveMode)) - xgifb_reg_set(pVBInfo->Part2Port, 0x0B, 0x00); - } -} - -static void XGI_SetLCDRegs(unsigned short ModeIdIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short pushbx, tempax, tempbx, tempcx, temp, tempah, - tempbh, tempch; - - struct XGI_LCDDesStruct const *LCDBDesPtr = NULL; - - /* si+Ext_ResInfo */ - if (!(pVBInfo->VBInfo & SetCRT2ToLCD)) - return; - - tempbx = pVBInfo->HDE; /* RHACTE=HDE-1 */ - - if (XGI_IsLCDDualLink(pVBInfo)) - tempbx = tempbx >> 1; - - tempbx -= 1; - temp = tempbx & 0x00FF; - xgifb_reg_set(pVBInfo->Part2Port, 0x2C, temp); - temp = (tempbx & 0xFF00) >> 8; - temp = temp << 4; - xgifb_reg_and_or(pVBInfo->Part2Port, 0x2B, 0x0F, temp); - temp = 0x01; - - xgifb_reg_set(pVBInfo->Part2Port, 0x0B, temp); - tempbx = pVBInfo->VDE; /* RTVACTEO=(VDE-1)&0xFF */ - tempbx--; - temp = tempbx & 0x00FF; - xgifb_reg_set(pVBInfo->Part2Port, 0x03, temp); - temp = ((tempbx & 0xFF00) >> 8) & 0x07; - xgifb_reg_and_or(pVBInfo->Part2Port, 0x0C, ~0x07, temp); - - tempcx = pVBInfo->VT - 1; - temp = tempcx & 0x00FF; /* RVTVT=VT-1 */ - xgifb_reg_set(pVBInfo->Part2Port, 0x19, temp); - temp = (tempcx & 0xFF00) >> 8; - temp = temp << 5; - xgifb_reg_set(pVBInfo->Part2Port, 0x1A, temp); - xgifb_reg_and_or(pVBInfo->Part2Port, 0x09, 0xF0, 0x00); - xgifb_reg_and_or(pVBInfo->Part2Port, 0x0A, 0xF0, 0x00); - xgifb_reg_and_or(pVBInfo->Part2Port, 0x17, 0xFB, 0x00); - xgifb_reg_and_or(pVBInfo->Part2Port, 0x18, 0xDF, 0x00); - - /* Customized LCDB Does not add */ - if ((pVBInfo->VBType & VB_SIS301LV) || (pVBInfo->VBType & VB_SIS302LV)) - LCDBDesPtr = XGI_GetLcdPtr(xgifb_lcddldes, ModeIdIndex, - pVBInfo); - else - LCDBDesPtr = XGI_GetLcdPtr(XGI_LCDDesDataTable, ModeIdIndex, - pVBInfo); - - tempah = pVBInfo->LCDResInfo; - tempah &= PanelResInfo; - - if ((tempah == Panel_1024x768) || (tempah == Panel_1024x768x75)) { - tempbx = 1024; - tempcx = 768; - } else if ((tempah == Panel_1280x1024) || - (tempah == Panel_1280x1024x75)) { - tempbx = 1280; - tempcx = 1024; - } else if (tempah == Panel_1400x1050) { - tempbx = 1400; - tempcx = 1050; - } else { - tempbx = 1600; - tempcx = 1200; - } - - if (pVBInfo->LCDInfo & EnableScalingLCD) { - tempbx = pVBInfo->HDE; - tempcx = pVBInfo->VDE; - } - - pushbx = tempbx; - tempax = pVBInfo->VT; - pVBInfo->LCDHDES = LCDBDesPtr->LCDHDES; - pVBInfo->LCDHRS = LCDBDesPtr->LCDHRS; - pVBInfo->LCDVDES = LCDBDesPtr->LCDVDES; - pVBInfo->LCDVRS = LCDBDesPtr->LCDVRS; - tempbx = pVBInfo->LCDVDES; - tempcx += tempbx; - - if (tempcx >= tempax) - tempcx -= tempax; /* lcdvdes */ - - temp = tempbx & 0x00FF; /* RVEQ1EQ=lcdvdes */ - xgifb_reg_set(pVBInfo->Part2Port, 0x05, temp); - temp = tempcx & 0x00FF; - xgifb_reg_set(pVBInfo->Part2Port, 0x06, temp); - tempch = ((tempcx & 0xFF00) >> 8) & 0x07; - tempbh = ((tempbx & 0xFF00) >> 8) & 0x07; - tempah = tempch; - tempah = tempah << 3; - tempah |= tempbh; - xgifb_reg_set(pVBInfo->Part2Port, 0x02, tempah); - - /* getlcdsync() */ - XGI_GetLCDSync(&tempax, &tempbx, pVBInfo); - tempcx = tempbx; - tempax = pVBInfo->VT; - tempbx = pVBInfo->LCDVRS; - - tempcx += tempbx; - if (tempcx >= tempax) - tempcx -= tempax; - - temp = tempbx & 0x00FF; /* RTVACTEE=lcdvrs */ - xgifb_reg_set(pVBInfo->Part2Port, 0x04, temp); - temp = (tempbx & 0xFF00) >> 8; - temp = temp << 4; - temp |= (tempcx & 0x000F); - xgifb_reg_set(pVBInfo->Part2Port, 0x01, temp); - tempcx = pushbx; - tempax = pVBInfo->HT; - tempbx = pVBInfo->LCDHDES; - tempbx &= 0x0FFF; - - if (XGI_IsLCDDualLink(pVBInfo)) { - tempax = tempax >> 1; - tempbx = tempbx >> 1; - tempcx = tempcx >> 1; - } - - if (pVBInfo->VBType & VB_SIS302LV) - tempbx += 1; - - if (pVBInfo->VBType & VB_XGI301C) /* tap4 */ - tempbx += 1; - - tempcx += tempbx; - - if (tempcx >= tempax) - tempcx -= tempax; - - temp = tempbx & 0x00FF; - xgifb_reg_set(pVBInfo->Part2Port, 0x1F, temp); /* RHBLKE=lcdhdes */ - temp = ((tempbx & 0xFF00) >> 8) << 4; - xgifb_reg_set(pVBInfo->Part2Port, 0x20, temp); - temp = tempcx & 0x00FF; - xgifb_reg_set(pVBInfo->Part2Port, 0x23, temp); /* RHEQPLE=lcdhdee */ - temp = (tempcx & 0xFF00) >> 8; - xgifb_reg_set(pVBInfo->Part2Port, 0x25, temp); - - XGI_GetLCDSync(&tempax, &tempbx, pVBInfo); - tempcx = tempax; - tempax = pVBInfo->HT; - tempbx = pVBInfo->LCDHRS; - if (XGI_IsLCDDualLink(pVBInfo)) { - tempax = tempax >> 1; - tempbx = tempbx >> 1; - tempcx = tempcx >> 1; - } - - if (pVBInfo->VBType & VB_SIS302LV) - tempbx += 1; - - tempcx += tempbx; - - if (tempcx >= tempax) - tempcx -= tempax; - - temp = tempbx & 0x00FF; /* RHBURSTS=lcdhrs */ - xgifb_reg_set(pVBInfo->Part2Port, 0x1C, temp); - - temp = (tempbx & 0xFF00) >> 8; - temp = temp << 4; - xgifb_reg_and_or(pVBInfo->Part2Port, 0x1D, ~0x0F0, temp); - temp = tempcx & 0x00FF; /* RHSYEXP2S=lcdhre */ - xgifb_reg_set(pVBInfo->Part2Port, 0x21, temp); - - if (!(pVBInfo->LCDInfo & XGI_LCDVESATiming)) { - if (pVBInfo->VGAVDE == 525) { - if (pVBInfo->VBType & (VB_SIS301B | VB_SIS302B - | VB_SIS301LV | VB_SIS302LV - | VB_XGI301C)) { - temp = 0xC6; - } else - temp = 0xC4; - - xgifb_reg_set(pVBInfo->Part2Port, 0x2f, temp); - xgifb_reg_set(pVBInfo->Part2Port, 0x30, 0xB3); - } - - if (pVBInfo->VGAVDE == 420) { - if (pVBInfo->VBType & (VB_SIS301B | VB_SIS302B - | VB_SIS301LV | VB_SIS302LV - | VB_XGI301C)) { - temp = 0x4F; - } else - temp = 0x4E; - xgifb_reg_set(pVBInfo->Part2Port, 0x2f, temp); - } - } -} - -/* --------------------------------------------------------------------- */ -/* Function : XGI_GetTap4Ptr */ -/* Input : */ -/* Output : di -> Tap4 Reg. Setting Pointer */ -/* Description : */ -/* --------------------------------------------------------------------- */ -static struct XGI301C_Tap4TimingStruct const -*XGI_GetTap4Ptr(unsigned short tempcx, struct vb_device_info *pVBInfo) -{ - unsigned short tempax, tempbx, i; - struct XGI301C_Tap4TimingStruct const *Tap4TimingPtr; - - if (tempcx == 0) { - tempax = pVBInfo->VGAHDE; - tempbx = pVBInfo->HDE; - } else { - tempax = pVBInfo->VGAVDE; - tempbx = pVBInfo->VDE; - } - - if (tempax <= tempbx) - return &xgifb_tap4_timing[0]; - Tap4TimingPtr = xgifb_ntsc_525_tap4_timing; /* NTSC */ - - if (pVBInfo->TVInfo & TVSetPAL) - Tap4TimingPtr = PALTap4Timing; - - if (pVBInfo->VBInfo & SetCRT2ToYPbPr525750) { - if ((pVBInfo->TVInfo & TVSetYPbPr525i) || - (pVBInfo->TVInfo & TVSetYPbPr525p)) - Tap4TimingPtr = xgifb_ntsc_525_tap4_timing; - if (pVBInfo->TVInfo & TVSetYPbPr750p) - Tap4TimingPtr = YPbPr750pTap4Timing; - } - - if (pVBInfo->VBInfo & SetCRT2ToHiVision) - Tap4TimingPtr = xgifb_tap4_timing; - - i = 0; - while (Tap4TimingPtr[i].DE != 0xFFFF) { - if (Tap4TimingPtr[i].DE == tempax) - break; - i++; - } - return &Tap4TimingPtr[i]; -} - -static void XGI_SetTap4Regs(struct vb_device_info *pVBInfo) -{ - unsigned short i, j; - struct XGI301C_Tap4TimingStruct const *Tap4TimingPtr; - - if (!(pVBInfo->VBType & VB_XGI301C)) - return; - - Tap4TimingPtr = XGI_GetTap4Ptr(0, pVBInfo); /* Set Horizontal Scaling */ - for (i = 0x80, j = 0; i <= 0xBF; i++, j++) - xgifb_reg_set(pVBInfo->Part2Port, i, Tap4TimingPtr->Reg[j]); - - if ((pVBInfo->VBInfo & SetCRT2ToTV) && - (!(pVBInfo->VBInfo & SetCRT2ToHiVision))) { - /* Set Vertical Scaling */ - Tap4TimingPtr = XGI_GetTap4Ptr(1, pVBInfo); - for (i = 0xC0, j = 0; i < 0xFF; i++, j++) - xgifb_reg_set(pVBInfo->Part2Port, - i, - Tap4TimingPtr->Reg[j]); - } - - if ((pVBInfo->VBInfo & SetCRT2ToTV) && - (!(pVBInfo->VBInfo & SetCRT2ToHiVision))) - /* Enable V.Scaling */ - xgifb_reg_and_or(pVBInfo->Part2Port, 0x4E, ~0x14, 0x04); - else - /* Enable H.Scaling */ - xgifb_reg_and_or(pVBInfo->Part2Port, 0x4E, ~0x14, 0x10); -} - -static void XGI_SetGroup3(unsigned short ModeIdIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short i; - unsigned char const *tempdi; - unsigned short modeflag; - - /* si+Ext_ResInfo */ - modeflag = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeFlag; - - xgifb_reg_set(pVBInfo->Part3Port, 0x00, 0x00); - if (pVBInfo->TVInfo & TVSetPAL) { - xgifb_reg_set(pVBInfo->Part3Port, 0x13, 0xFA); - xgifb_reg_set(pVBInfo->Part3Port, 0x14, 0xC8); - } else { - xgifb_reg_set(pVBInfo->Part3Port, 0x13, 0xF5); - xgifb_reg_set(pVBInfo->Part3Port, 0x14, 0xB7); - } - - if (!(pVBInfo->VBInfo & SetCRT2ToTV)) - return; - - if (pVBInfo->TVInfo & TVSetPALM) { - xgifb_reg_set(pVBInfo->Part3Port, 0x13, 0xFA); - xgifb_reg_set(pVBInfo->Part3Port, 0x14, 0xC8); - xgifb_reg_set(pVBInfo->Part3Port, 0x3D, 0xA8); - } - - if ((pVBInfo->VBInfo & SetCRT2ToHiVision) || (pVBInfo->VBInfo - & SetCRT2ToYPbPr525750)) { - if (pVBInfo->TVInfo & TVSetYPbPr525i) - return; - - tempdi = XGI330_HiTVGroup3Data; - if (pVBInfo->SetFlag & TVSimuMode) { - tempdi = XGI330_HiTVGroup3Simu; - if (!(modeflag & Charx8Dot)) - tempdi = XGI330_HiTVGroup3Text; - } - - if (pVBInfo->TVInfo & TVSetYPbPr525p) - tempdi = XGI330_Ren525pGroup3; - - if (pVBInfo->TVInfo & TVSetYPbPr750p) - tempdi = XGI330_Ren750pGroup3; - - for (i = 0; i <= 0x3E; i++) - xgifb_reg_set(pVBInfo->Part3Port, i, tempdi[i]); - - if (pVBInfo->VBType & VB_XGI301C) { /* Marcovision */ - if (pVBInfo->TVInfo & TVSetYPbPr525p) - xgifb_reg_set(pVBInfo->Part3Port, 0x28, 0x3f); - } - } -} - -static void XGI_SetGroup4(unsigned short ModeIdIndex, - unsigned short RefreshRateTableIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short tempax, tempcx, tempbx, modeflag, temp, temp2; - - unsigned long tempebx, tempeax, templong; - - /* si+Ext_ResInfo */ - modeflag = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeFlag; - temp = pVBInfo->RVBHCFACT; - xgifb_reg_set(pVBInfo->Part4Port, 0x13, temp); - - tempbx = pVBInfo->RVBHCMAX; - temp = tempbx & 0x00FF; - xgifb_reg_set(pVBInfo->Part4Port, 0x14, temp); - temp2 = ((tempbx & 0xFF00) >> 8) << 7; - tempcx = pVBInfo->VGAHT - 1; - temp = tempcx & 0x00FF; - xgifb_reg_set(pVBInfo->Part4Port, 0x16, temp); - - temp = ((tempcx & 0xFF00) >> 8) << 3; - temp2 |= temp; - - tempcx = pVBInfo->VGAVT - 1; - if (!(pVBInfo->VBInfo & SetCRT2ToTV)) - tempcx -= 5; - - temp = tempcx & 0x00FF; - xgifb_reg_set(pVBInfo->Part4Port, 0x17, temp); - temp = temp2 | ((tempcx & 0xFF00) >> 8); - xgifb_reg_set(pVBInfo->Part4Port, 0x15, temp); - xgifb_reg_or(pVBInfo->Part4Port, 0x0D, 0x08); - tempcx = pVBInfo->VBInfo; - tempbx = pVBInfo->VGAHDE; - - if (modeflag & HalfDCLK) - tempbx = tempbx >> 1; - - if (XGI_IsLCDDualLink(pVBInfo)) - tempbx = tempbx >> 1; - - if (tempcx & SetCRT2ToHiVision) { - temp = 0; - if (tempbx <= 1024) - temp = 0xA0; - if (tempbx == 1280) - temp = 0xC0; - } else if (tempcx & SetCRT2ToTV) { - temp = 0xA0; - if (tempbx <= 800) - temp = 0x80; - } else { - temp = 0x80; - if (pVBInfo->VBInfo & SetCRT2ToLCD) { - temp = 0; - if (tempbx > 800) - temp = 0x60; - } - } - - if (pVBInfo->TVInfo & (TVSetYPbPr525p | TVSetYPbPr750p)) { - temp = 0x00; - if (pVBInfo->VGAHDE == 1280) - temp = 0x40; - if (pVBInfo->VGAHDE == 1024) - temp = 0x20; - } - xgifb_reg_and_or(pVBInfo->Part4Port, 0x0E, ~0xEF, temp); - - tempebx = pVBInfo->VDE; - - tempcx = pVBInfo->RVBHRS; - temp = tempcx & 0x00FF; - xgifb_reg_set(pVBInfo->Part4Port, 0x18, temp); - - tempeax = pVBInfo->VGAVDE; - tempcx |= 0x04000; - - if (tempeax <= tempebx) { - tempcx = (tempcx & (~0x4000)); - tempeax = pVBInfo->VGAVDE; - } else { - tempeax -= tempebx; - } - - templong = (tempeax * 256 * 1024) % tempebx; - tempeax = (tempeax * 256 * 1024) / tempebx; - tempebx = tempeax; - - if (templong != 0) - tempebx++; - - temp = (unsigned short) (tempebx & 0x000000FF); - xgifb_reg_set(pVBInfo->Part4Port, 0x1B, temp); - - temp = (unsigned short) ((tempebx & 0x0000FF00) >> 8); - xgifb_reg_set(pVBInfo->Part4Port, 0x1A, temp); - tempbx = (unsigned short) (tempebx >> 16); - temp = tempbx & 0x00FF; - temp = temp << 4; - temp |= ((tempcx & 0xFF00) >> 8); - xgifb_reg_set(pVBInfo->Part4Port, 0x19, temp); - - /* 301b */ - if (pVBInfo->VBType & (VB_SIS301B | VB_SIS302B | VB_SIS301LV - | VB_SIS302LV | VB_XGI301C)) { - temp = 0x0028; - xgifb_reg_set(pVBInfo->Part4Port, 0x1C, temp); - tempax = pVBInfo->VGAHDE; - if (modeflag & HalfDCLK) - tempax = tempax >> 1; - - if (XGI_IsLCDDualLink(pVBInfo)) - tempax = tempax >> 1; - - if (pVBInfo->VBInfo & SetCRT2ToLCD) { - if (tempax > 800) - tempax -= 800; - } else if (pVBInfo->VGAHDE > 800) { - if (pVBInfo->VGAHDE == 1024) - tempax = (tempax * 25 / 32) - 1; - else - tempax = (tempax * 20 / 32) - 1; - } - tempax -= 1; - - temp = (tempax & 0xFF00) >> 8; - temp = ((temp & 0x0003) << 4); - xgifb_reg_set(pVBInfo->Part4Port, 0x1E, temp); - temp = (tempax & 0x00FF); - xgifb_reg_set(pVBInfo->Part4Port, 0x1D, temp); - - if (pVBInfo->VBInfo & (SetCRT2ToTV | SetCRT2ToHiVision)) { - if (pVBInfo->VGAHDE > 800) - xgifb_reg_or(pVBInfo->Part4Port, 0x1E, 0x08); - - } - temp = 0x0036; - - if (pVBInfo->VBInfo & SetCRT2ToTV) { - if (!(pVBInfo->TVInfo & (NTSC1024x768 - | TVSetYPbPr525p | TVSetYPbPr750p - | TVSetHiVision))) { - temp |= 0x0001; - if ((pVBInfo->VBInfo & SetInSlaveMode) - && (!(pVBInfo->TVInfo - & TVSimuMode))) - temp &= (~0x0001); - } - } - - xgifb_reg_and_or(pVBInfo->Part4Port, 0x1F, 0x00C0, temp); - tempbx = pVBInfo->HT; - if (XGI_IsLCDDualLink(pVBInfo)) - tempbx = tempbx >> 1; - tempbx = (tempbx >> 1) - 2; - temp = ((tempbx & 0x0700) >> 8) << 3; - xgifb_reg_and_or(pVBInfo->Part4Port, 0x21, 0x00C0, temp); - temp = tempbx & 0x00FF; - xgifb_reg_set(pVBInfo->Part4Port, 0x22, temp); - } - /* end 301b */ - - XGI_SetCRT2VCLK(ModeIdIndex, RefreshRateTableIndex, pVBInfo); -} - -static void XGINew_EnableCRT2(struct vb_device_info *pVBInfo) -{ - xgifb_reg_and_or(pVBInfo->P3c4, 0x1E, 0xFF, 0x20); -} - -static void XGI_SetGroup5(struct vb_device_info *pVBInfo) -{ - if (pVBInfo->ModeType == ModeVGA) { - if (!(pVBInfo->VBInfo & (SetInSlaveMode | LoadDACFlag - | DisableCRT2Display))) { - XGINew_EnableCRT2(pVBInfo); - } - } -} - -static void XGI_DisableGatingCRT(struct vb_device_info *pVBInfo) -{ - xgifb_reg_and_or(pVBInfo->P3d4, 0x63, 0xBF, 0x00); -} - -static unsigned char XGI_XG21CheckLVDSMode(struct xgifb_video_info *xgifb_info, - unsigned short ModeNo, unsigned short ModeIdIndex) -{ - unsigned short xres, yres, colordepth, modeflag, resindex; - - resindex = XGI330_EModeIDTable[ModeIdIndex].Ext_RESINFO; - xres = XGI330_ModeResInfo[resindex].HTotal; /* xres->ax */ - yres = XGI330_ModeResInfo[resindex].VTotal; /* yres->bx */ - /* si+St_ModeFlag */ - modeflag = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeFlag; - - if (!(modeflag & Charx8Dot)) { - xres /= 9; - xres *= 8; - } - - if ((ModeNo > 0x13) && (modeflag & HalfDCLK)) - xres *= 2; - - if ((ModeNo > 0x13) && (modeflag & DoubleScanMode)) - yres *= 2; - - if (xres > xgifb_info->lvds_data.LVDSHDE) - return 0; - - if (yres > xgifb_info->lvds_data.LVDSVDE) - return 0; - - if (xres != xgifb_info->lvds_data.LVDSHDE || - yres != xgifb_info->lvds_data.LVDSVDE) { - colordepth = XGI_GetColorDepth(ModeIdIndex); - if (colordepth > 2) - return 0; - } - return 1; -} - -static void xgifb_set_lvds(struct xgifb_video_info *xgifb_info, - int chip_id, - unsigned short ModeIdIndex, - struct vb_device_info *pVBInfo) -{ - unsigned char temp, Miscdata; - unsigned short xres, yres, modeflag, resindex; - unsigned short LVDSHT, LVDSHBS, LVDSHRS, LVDSHRE, LVDSHBE; - unsigned short LVDSVT, LVDSVBS, LVDSVRS, LVDSVRE, LVDSVBE; - unsigned short value; - - temp = (unsigned char) ((xgifb_info->lvds_data.LVDS_Capability & - (LCDPolarity << 8)) >> 8); - temp &= LCDPolarity; - Miscdata = inb(pVBInfo->P3cc); - - outb((Miscdata & 0x3F) | temp, pVBInfo->P3c2); - - temp = xgifb_info->lvds_data.LVDS_Capability & LCDPolarity; - /* SR35[7] FP VSync polarity */ - xgifb_reg_and_or(pVBInfo->P3c4, 0x35, ~0x80, temp & 0x80); - /* SR30[5] FP HSync polarity */ - xgifb_reg_and_or(pVBInfo->P3c4, 0x30, ~0x20, (temp & 0x40) >> 1); - - if (chip_id == XG27) - XGI_SetXG27FPBits(pVBInfo); - else - XGI_SetXG21FPBits(pVBInfo); - - resindex = XGI330_EModeIDTable[ModeIdIndex].Ext_RESINFO; - xres = XGI330_ModeResInfo[resindex].HTotal; /* xres->ax */ - yres = XGI330_ModeResInfo[resindex].VTotal; /* yres->bx */ - /* si+St_ModeFlag */ - modeflag = XGI330_EModeIDTable[ModeIdIndex].Ext_ModeFlag; - - if (!(modeflag & Charx8Dot)) - xres = xres * 8 / 9; - - LVDSHT = xgifb_info->lvds_data.LVDSHT; - - LVDSHBS = xres + (xgifb_info->lvds_data.LVDSHDE - xres) / 2; - - if (LVDSHBS > LVDSHT) - LVDSHBS -= LVDSHT; - - LVDSHRS = LVDSHBS + xgifb_info->lvds_data.LVDSHFP; - if (LVDSHRS > LVDSHT) - LVDSHRS -= LVDSHT; - - LVDSHRE = LVDSHRS + xgifb_info->lvds_data.LVDSHSYNC; - if (LVDSHRE > LVDSHT) - LVDSHRE -= LVDSHT; - - LVDSHBE = LVDSHBS + LVDSHT - xgifb_info->lvds_data.LVDSHDE; - - LVDSVT = xgifb_info->lvds_data.LVDSVT; - - LVDSVBS = yres + (xgifb_info->lvds_data.LVDSVDE - yres) / 2; - if (modeflag & DoubleScanMode) - LVDSVBS += yres / 2; - - if (LVDSVBS > LVDSVT) - LVDSVBS -= LVDSVT; - - LVDSVRS = LVDSVBS + xgifb_info->lvds_data.LVDSVFP; - if (LVDSVRS > LVDSVT) - LVDSVRS -= LVDSVT; - - LVDSVRE = LVDSVRS + xgifb_info->lvds_data.LVDSVSYNC; - if (LVDSVRE > LVDSVT) - LVDSVRE -= LVDSVT; - - LVDSVBE = LVDSVBS + LVDSVT - xgifb_info->lvds_data.LVDSVDE; - - temp = xgifb_reg_get(pVBInfo->P3d4, 0x11); - xgifb_reg_set(pVBInfo->P3d4, 0x11, temp & 0x7f); /* Unlock CRTC */ - - if (!(modeflag & Charx8Dot)) - xgifb_reg_or(pVBInfo->P3c4, 0x1, 0x1); - - /* HT SR0B[1:0] CR00 */ - value = (LVDSHT >> 3) - 5; - xgifb_reg_and_or(pVBInfo->P3c4, 0x0B, ~0x03, (value & 0x300) >> 8); - xgifb_reg_set(pVBInfo->P3d4, 0x0, (value & 0xFF)); - - /* HBS SR0B[5:4] CR02 */ - value = (LVDSHBS >> 3) - 1; - xgifb_reg_and_or(pVBInfo->P3c4, 0x0B, ~0x30, (value & 0x300) >> 4); - xgifb_reg_set(pVBInfo->P3d4, 0x2, (value & 0xFF)); - - /* HBE SR0C[1:0] CR05[7] CR03[4:0] */ - value = (LVDSHBE >> 3) - 1; - xgifb_reg_and_or(pVBInfo->P3c4, 0x0C, ~0x03, (value & 0xC0) >> 6); - xgifb_reg_and_or(pVBInfo->P3d4, 0x05, ~0x80, (value & 0x20) << 2); - xgifb_reg_and_or(pVBInfo->P3d4, 0x03, ~0x1F, value & 0x1F); - - /* HRS SR0B[7:6] CR04 */ - value = (LVDSHRS >> 3) + 2; - xgifb_reg_and_or(pVBInfo->P3c4, 0x0B, ~0xC0, (value & 0x300) >> 2); - xgifb_reg_set(pVBInfo->P3d4, 0x4, (value & 0xFF)); - - /* Panel HRS SR2F[1:0] SR2E[7:0] */ - value--; - xgifb_reg_and_or(pVBInfo->P3c4, 0x2F, ~0x03, (value & 0x300) >> 8); - xgifb_reg_set(pVBInfo->P3c4, 0x2E, (value & 0xFF)); - - /* HRE SR0C[2] CR05[4:0] */ - value = (LVDSHRE >> 3) + 2; - xgifb_reg_and_or(pVBInfo->P3c4, 0x0C, ~0x04, (value & 0x20) >> 3); - xgifb_reg_and_or(pVBInfo->P3d4, 0x05, ~0x1F, value & 0x1F); - - /* Panel HRE SR2F[7:2] */ - value--; - xgifb_reg_and_or(pVBInfo->P3c4, 0x2F, ~0xFC, value << 2); - - /* VT SR0A[0] CR07[5][0] CR06 */ - value = LVDSVT - 2; - xgifb_reg_and_or(pVBInfo->P3c4, 0x0A, ~0x01, (value & 0x400) >> 10); - xgifb_reg_and_or(pVBInfo->P3d4, 0x07, ~0x20, (value & 0x200) >> 4); - xgifb_reg_and_or(pVBInfo->P3d4, 0x07, ~0x01, (value & 0x100) >> 8); - xgifb_reg_set(pVBInfo->P3d4, 0x06, (value & 0xFF)); - - /* VBS SR0A[2] CR09[5] CR07[3] CR15 */ - value = LVDSVBS - 1; - xgifb_reg_and_or(pVBInfo->P3c4, 0x0A, ~0x04, (value & 0x400) >> 8); - xgifb_reg_and_or(pVBInfo->P3d4, 0x09, ~0x20, (value & 0x200) >> 4); - xgifb_reg_and_or(pVBInfo->P3d4, 0x07, ~0x08, (value & 0x100) >> 5); - xgifb_reg_set(pVBInfo->P3d4, 0x15, (value & 0xFF)); - - /* VBE SR0A[4] CR16 */ - value = LVDSVBE - 1; - xgifb_reg_and_or(pVBInfo->P3c4, 0x0A, ~0x10, (value & 0x100) >> 4); - xgifb_reg_set(pVBInfo->P3d4, 0x16, (value & 0xFF)); - - /* VRS SR0A[3] CR7[7][2] CR10 */ - value = LVDSVRS - 1; - xgifb_reg_and_or(pVBInfo->P3c4, 0x0A, ~0x08, (value & 0x400) >> 7); - xgifb_reg_and_or(pVBInfo->P3d4, 0x07, ~0x80, (value & 0x200) >> 2); - xgifb_reg_and_or(pVBInfo->P3d4, 0x07, ~0x04, (value & 0x100) >> 6); - xgifb_reg_set(pVBInfo->P3d4, 0x10, (value & 0xFF)); - - if (chip_id == XG27) { - /* Panel VRS SR35[2:0] SR34[7:0] */ - xgifb_reg_and_or(pVBInfo->P3c4, 0x35, ~0x07, - (value & 0x700) >> 8); - xgifb_reg_set(pVBInfo->P3c4, 0x34, value & 0xFF); - } else { - /* Panel VRS SR3F[1:0] SR34[7:0] SR33[0] */ - xgifb_reg_and_or(pVBInfo->P3c4, 0x3F, ~0x03, - (value & 0x600) >> 9); - xgifb_reg_set(pVBInfo->P3c4, 0x34, (value >> 1) & 0xFF); - xgifb_reg_and_or(pVBInfo->P3d4, 0x33, ~0x01, value & 0x01); - } - - /* VRE SR0A[5] CR11[3:0] */ - value = LVDSVRE - 1; - xgifb_reg_and_or(pVBInfo->P3c4, 0x0A, ~0x20, (value & 0x10) << 1); - xgifb_reg_and_or(pVBInfo->P3d4, 0x11, ~0x0F, value & 0x0F); - - /* Panel VRE SR3F[7:2] */ - if (chip_id == XG27) - xgifb_reg_and_or(pVBInfo->P3c4, 0x3F, ~0xFC, - (value << 2) & 0xFC); - else - /* SR3F[7] has to be 0, h/w bug */ - xgifb_reg_and_or(pVBInfo->P3c4, 0x3F, ~0xFC, - (value << 2) & 0x7C); - - for (temp = 0, value = 0; temp < 3; temp++) { - - xgifb_reg_and_or(pVBInfo->P3c4, 0x31, ~0x30, value); - xgifb_reg_set(pVBInfo->P3c4, - 0x2B, xgifb_info->lvds_data.VCLKData1); - xgifb_reg_set(pVBInfo->P3c4, - 0x2C, xgifb_info->lvds_data.VCLKData2); - value += 0x10; - } - - if (!(modeflag & Charx8Dot)) { - inb(pVBInfo->P3da); /* reset 3da */ - outb(0x13, pVBInfo->P3c0); /* set index */ - /* set data, panning = 0, shift left 1 dot*/ - outb(0x00, pVBInfo->P3c0); - - inb(pVBInfo->P3da); /* Enable Attribute */ - outb(0x20, pVBInfo->P3c0); - - inb(pVBInfo->P3da); /* reset 3da */ - } - -} - -/* --------------------------------------------------------------------- */ -/* Function : XGI_IsLCDON */ -/* Input : */ -/* Output : 0 : Skip PSC Control */ -/* 1: Disable PSC */ -/* Description : */ -/* --------------------------------------------------------------------- */ -static unsigned char XGI_IsLCDON(struct vb_device_info *pVBInfo) -{ - unsigned short tempax; - - tempax = pVBInfo->VBInfo; - if (tempax & SetCRT2ToDualEdge) - return 0; - else if (tempax & (DisableCRT2Display | SwitchCRT2 | SetSimuScanMode)) - return 1; - - return 0; -} - -static void XGI_DisableBridge(struct xgifb_video_info *xgifb_info, - struct xgi_hw_device_info *HwDeviceExtension, - struct vb_device_info *pVBInfo) -{ - unsigned short tempah = 0; - - if (pVBInfo->VBType & (VB_SIS301B | VB_SIS302B | VB_SIS301LV - | VB_SIS302LV | VB_XGI301C)) { - tempah = 0x3F; - if (!(pVBInfo->VBInfo & - (DisableCRT2Display | SetSimuScanMode))) { - if (pVBInfo->VBInfo & XGI_SetCRT2ToLCDA) { - if (pVBInfo->VBInfo & SetCRT2ToDualEdge) - tempah = 0x7F; /* Disable Channel A */ - } - } - - /* disable part4_1f */ - xgifb_reg_and(pVBInfo->Part4Port, 0x1F, tempah); - - if (pVBInfo->VBType & (VB_SIS302LV | VB_XGI301C)) { - if (((pVBInfo->VBInfo & - (SetCRT2ToLCD | XGI_SetCRT2ToLCDA))) || - (XGI_IsLCDON(pVBInfo))) - /* LVDS Driver power down */ - xgifb_reg_or(pVBInfo->Part4Port, 0x30, 0x80); - } - - if (pVBInfo->VBInfo & (DisableCRT2Display | XGI_SetCRT2ToLCDA | - SetSimuScanMode)) - XGI_DisplayOff(xgifb_info, HwDeviceExtension, pVBInfo); - - if (pVBInfo->VBInfo & XGI_SetCRT2ToLCDA) - /* Power down */ - xgifb_reg_and(pVBInfo->Part1Port, 0x1e, 0xdf); - - /* disable TV as primary VGA swap */ - xgifb_reg_and(pVBInfo->P3c4, 0x32, 0xdf); - - if ((pVBInfo->VBInfo & (SetSimuScanMode | SetCRT2ToDualEdge))) - xgifb_reg_and(pVBInfo->Part2Port, 0x00, 0xdf); - - if ((pVBInfo->VBInfo & - (DisableCRT2Display | SetSimuScanMode)) || - ((!(pVBInfo->VBInfo & XGI_SetCRT2ToLCDA)) && - (pVBInfo->VBInfo & - (SetCRT2ToRAMDAC | SetCRT2ToLCD | SetCRT2ToTV)))) - xgifb_reg_or(pVBInfo->Part1Port, 0x00, 0x80); - - if ((pVBInfo->VBInfo & - (DisableCRT2Display | SetSimuScanMode)) || - (!(pVBInfo->VBInfo & XGI_SetCRT2ToLCDA)) || - (pVBInfo->VBInfo & - (SetCRT2ToRAMDAC | SetCRT2ToLCD | SetCRT2ToTV))) { - /* save Part1 index 0 */ - tempah = xgifb_reg_get(pVBInfo->Part1Port, 0x00); - /* BTDAC = 1, avoid VB reset */ - xgifb_reg_or(pVBInfo->Part1Port, 0x00, 0x10); - /* disable CRT2 */ - xgifb_reg_and(pVBInfo->Part1Port, 0x1E, 0xDF); - /* restore Part1 index 0 */ - xgifb_reg_set(pVBInfo->Part1Port, 0x00, tempah); - } - } else { /* {301} */ - if (pVBInfo->VBInfo & (SetCRT2ToLCD | SetCRT2ToTV)) { - xgifb_reg_or(pVBInfo->Part1Port, 0x00, 0x80); - /* Disable CRT2 */ - xgifb_reg_and(pVBInfo->Part1Port, 0x1E, 0xDF); - /* Disable TV asPrimary VGA swap */ - xgifb_reg_and(pVBInfo->P3c4, 0x32, 0xDF); - } - - if (pVBInfo->VBInfo & (DisableCRT2Display | XGI_SetCRT2ToLCDA - | SetSimuScanMode)) - XGI_DisplayOff(xgifb_info, HwDeviceExtension, pVBInfo); - } -} - -/* --------------------------------------------------------------------- */ -/* Function : XGI_GetTVPtrIndex */ -/* Input : */ -/* Output : */ -/* Description : bx 0 : ExtNTSC */ -/* 1 : StNTSC */ -/* 2 : ExtPAL */ -/* 3 : StPAL */ -/* 4 : ExtHiTV */ -/* 5 : StHiTV */ -/* 6 : Ext525i */ -/* 7 : St525i */ -/* 8 : Ext525p */ -/* 9 : St525p */ -/* A : Ext750p */ -/* B : St750p */ -/* --------------------------------------------------------------------- */ -static unsigned short XGI_GetTVPtrIndex(struct vb_device_info *pVBInfo) -{ - unsigned short tempbx = 0; - - if (pVBInfo->TVInfo & TVSetPAL) - tempbx = 2; - if (pVBInfo->TVInfo & TVSetHiVision) - tempbx = 4; - if (pVBInfo->TVInfo & TVSetYPbPr525i) - tempbx = 6; - if (pVBInfo->TVInfo & TVSetYPbPr525p) - tempbx = 8; - if (pVBInfo->TVInfo & TVSetYPbPr750p) - tempbx = 10; - if (pVBInfo->TVInfo & TVSimuMode) - tempbx++; - - return tempbx; -} - -/* --------------------------------------------------------------------- */ -/* Function : XGI_GetTVPtrIndex2 */ -/* Input : */ -/* Output : bx 0 : NTSC */ -/* 1 : PAL */ -/* 2 : PALM */ -/* 3 : PALN */ -/* 4 : NTSC1024x768 */ -/* 5 : PAL-M 1024x768 */ -/* 6-7: reserved */ -/* cl 0 : YFilter1 */ -/* 1 : YFilter2 */ -/* ch 0 : 301A */ -/* 1 : 301B/302B/301LV/302LV */ -/* Description : */ -/* --------------------------------------------------------------------- */ -static void XGI_GetTVPtrIndex2(unsigned short *tempbx, unsigned char *tempcl, - unsigned char *tempch, struct vb_device_info *pVBInfo) -{ - *tempbx = 0; - *tempcl = 0; - *tempch = 0; - - if (pVBInfo->TVInfo & TVSetPAL) - *tempbx = 1; - - if (pVBInfo->TVInfo & TVSetPALM) - *tempbx = 2; - - if (pVBInfo->TVInfo & TVSetPALN) - *tempbx = 3; - - if (pVBInfo->TVInfo & NTSC1024x768) { - *tempbx = 4; - if (pVBInfo->TVInfo & TVSetPALM) - *tempbx = 5; - } - - if (pVBInfo->VBType & (VB_SIS301B | VB_SIS302B | VB_SIS301LV - | VB_SIS302LV | VB_XGI301C)) { - if ((!(pVBInfo->VBInfo & SetInSlaveMode)) || (pVBInfo->TVInfo - & TVSimuMode)) { - *tempbx += 8; - *tempcl += 1; - } - } - - if (pVBInfo->VBType & (VB_SIS301B | VB_SIS302B | VB_SIS301LV - | VB_SIS302LV | VB_XGI301C)) - (*tempch)++; -} - -static void XGI_SetDelayComp(struct vb_device_info *pVBInfo) -{ - unsigned char tempah, tempbl, tempbh; - - if (pVBInfo->VBType & (VB_SIS301B | VB_SIS302B | VB_SIS301LV - | VB_SIS302LV | VB_XGI301C)) { - if (pVBInfo->VBInfo & (SetCRT2ToLCD | XGI_SetCRT2ToLCDA - | SetCRT2ToTV | SetCRT2ToRAMDAC)) { - tempbh = 0; - tempbl = XGI301TVDelay; - - if (pVBInfo->VBInfo & SetCRT2ToDualEdge) - tempbl = tempbl >> 4; - if (pVBInfo->VBInfo & - (SetCRT2ToLCD | XGI_SetCRT2ToLCDA)) { - tempbh = XGI301LCDDelay; - - if (!(pVBInfo->VBInfo & XGI_SetCRT2ToLCDA)) - tempbl = tempbh; - } - - tempbl &= 0x0F; - tempbh &= 0xF0; - tempah = xgifb_reg_get(pVBInfo->Part1Port, 0x2D); - - if (pVBInfo->VBInfo & (SetCRT2ToRAMDAC | SetCRT2ToLCD - | SetCRT2ToTV)) { /* Channel B */ - tempah &= 0xF0; - tempah |= tempbl; - } - - if (pVBInfo->VBInfo & XGI_SetCRT2ToLCDA) { - /* Channel A */ - tempah &= 0x0F; - tempah |= tempbh; - } - xgifb_reg_set(pVBInfo->Part1Port, 0x2D, tempah); - } - } -} - -static void XGI_SetLCDCap_A(unsigned short tempcx, - struct vb_device_info *pVBInfo) -{ - unsigned short temp; - - temp = xgifb_reg_get(pVBInfo->P3d4, 0x37); - - if (temp & LCDRGB18Bit) { - xgifb_reg_and_or(pVBInfo->Part1Port, 0x19, 0x0F, - /* Enable Dither */ - (unsigned short) (0x20 | (tempcx & 0x00C0))); - xgifb_reg_and_or(pVBInfo->Part1Port, 0x1A, 0x7F, 0x80); - } else { - xgifb_reg_and_or(pVBInfo->Part1Port, 0x19, 0x0F, - (unsigned short) (0x30 | (tempcx & 0x00C0))); - xgifb_reg_and_or(pVBInfo->Part1Port, 0x1A, 0x7F, 0x00); - } -} - -/* --------------------------------------------------------------------- */ -/* Function : XGI_SetLCDCap_B */ -/* Input : cx -> LCD Capability */ -/* Output : */ -/* Description : */ -/* --------------------------------------------------------------------- */ -static void XGI_SetLCDCap_B(unsigned short tempcx, - struct vb_device_info *pVBInfo) -{ - if (tempcx & EnableLCD24bpp) /* 24bits */ - xgifb_reg_and_or(pVBInfo->Part2Port, 0x1A, 0xE0, - (unsigned short) (((tempcx & 0x00ff) >> 6) - | 0x0c)); - else - xgifb_reg_and_or(pVBInfo->Part2Port, 0x1A, 0xE0, - (unsigned short) (((tempcx & 0x00ff) >> 6) - | 0x18)); /* Enable Dither */ -} - -static void XGI_LongWait(struct vb_device_info *pVBInfo) -{ - unsigned short i; - - i = xgifb_reg_get(pVBInfo->P3c4, 0x1F); - - if (!(i & 0xC0)) { - for (i = 0; i < 0xFFFF; i++) { - if (!(inb(pVBInfo->P3da) & 0x08)) - break; - } - - for (i = 0; i < 0xFFFF; i++) { - if ((inb(pVBInfo->P3da) & 0x08)) - break; - } - } -} - -static void SetSpectrum(struct vb_device_info *pVBInfo) -{ - unsigned short index; - - index = XGI_GetLCDCapPtr(pVBInfo); - - /* disable down spectrum D[4] */ - xgifb_reg_and(pVBInfo->Part4Port, 0x30, 0x8F); - XGI_LongWait(pVBInfo); - xgifb_reg_or(pVBInfo->Part4Port, 0x30, 0x20); /* reset spectrum */ - XGI_LongWait(pVBInfo); - - xgifb_reg_set(pVBInfo->Part4Port, 0x31, - pVBInfo->LCDCapList[index].Spectrum_31); - xgifb_reg_set(pVBInfo->Part4Port, 0x32, - pVBInfo->LCDCapList[index].Spectrum_32); - xgifb_reg_set(pVBInfo->Part4Port, 0x33, - pVBInfo->LCDCapList[index].Spectrum_33); - xgifb_reg_set(pVBInfo->Part4Port, 0x34, - pVBInfo->LCDCapList[index].Spectrum_34); - XGI_LongWait(pVBInfo); - xgifb_reg_or(pVBInfo->Part4Port, 0x30, 0x40); /* enable spectrum */ -} - -static void XGI_SetLCDCap(struct vb_device_info *pVBInfo) -{ - unsigned short tempcx; - - tempcx = pVBInfo->LCDCapList[XGI_GetLCDCapPtr(pVBInfo)].LCD_Capability; - - if (pVBInfo->VBType & (VB_SIS301B | VB_SIS302B | VB_SIS301LV | - VB_SIS302LV | VB_XGI301C)) { - if (pVBInfo->VBType & - (VB_SIS301LV | VB_SIS302LV | VB_XGI301C)) { - /* Set 301LV Capability */ - xgifb_reg_set(pVBInfo->Part4Port, 0x24, - (unsigned char) (tempcx & 0x1F)); - } - /* VB Driving */ - xgifb_reg_and_or(pVBInfo->Part4Port, 0x0D, - ~((EnableVBCLKDRVLOW | EnablePLLSPLOW) >> 8), - (unsigned short) ((tempcx & (EnableVBCLKDRVLOW - | EnablePLLSPLOW)) >> 8)); - - if (pVBInfo->VBInfo & SetCRT2ToLCD) - XGI_SetLCDCap_B(tempcx, pVBInfo); - else if (pVBInfo->VBInfo & XGI_SetCRT2ToLCDA) - XGI_SetLCDCap_A(tempcx, pVBInfo); - - if (pVBInfo->VBType & (VB_SIS302LV | VB_XGI301C)) { - if (tempcx & EnableSpectrum) - SetSpectrum(pVBInfo); - } - } else { - /* LVDS,CH7017 */ - XGI_SetLCDCap_A(tempcx, pVBInfo); - } -} - -/* --------------------------------------------------------------------- */ -/* Function : XGI_SetAntiFlicker */ -/* Input : */ -/* Output : */ -/* Description : Set TV Customized Param. */ -/* --------------------------------------------------------------------- */ -static void XGI_SetAntiFlicker(struct vb_device_info *pVBInfo) -{ - unsigned short tempbx; - - unsigned char tempah; - - if (pVBInfo->TVInfo & (TVSetYPbPr525p | TVSetYPbPr750p)) - return; - - tempbx = XGI_GetTVPtrIndex(pVBInfo); - tempbx &= 0xFE; - tempah = TVAntiFlickList[tempbx]; - tempah = tempah << 4; - - xgifb_reg_and_or(pVBInfo->Part2Port, 0x0A, 0x8F, tempah); -} - -static void XGI_SetEdgeEnhance(struct vb_device_info *pVBInfo) -{ - unsigned short tempbx; - - unsigned char tempah; - - tempbx = XGI_GetTVPtrIndex(pVBInfo); - tempbx &= 0xFE; - tempah = TVEdgeList[tempbx]; - tempah = tempah << 5; - - xgifb_reg_and_or(pVBInfo->Part2Port, 0x3A, 0x1F, tempah); -} - -static void XGI_SetPhaseIncr(struct vb_device_info *pVBInfo) -{ - unsigned short tempbx; - - unsigned char tempcl, tempch; - - unsigned long tempData; - - XGI_GetTVPtrIndex2(&tempbx, &tempcl, &tempch, pVBInfo); /* bx, cl, ch */ - tempData = TVPhaseList[tempbx]; - - xgifb_reg_set(pVBInfo->Part2Port, 0x31, (unsigned short) (tempData - & 0x000000FF)); - xgifb_reg_set(pVBInfo->Part2Port, 0x32, (unsigned short) ((tempData - & 0x0000FF00) >> 8)); - xgifb_reg_set(pVBInfo->Part2Port, 0x33, (unsigned short) ((tempData - & 0x00FF0000) >> 16)); - xgifb_reg_set(pVBInfo->Part2Port, 0x34, (unsigned short) ((tempData - & 0xFF000000) >> 24)); -} - -static void XGI_SetYFilter(unsigned short ModeIdIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short tempbx, index; - unsigned char const *filterPtr; - unsigned char tempcl, tempch, tempal; - - XGI_GetTVPtrIndex2(&tempbx, &tempcl, &tempch, pVBInfo); /* bx, cl, ch */ - - switch (tempbx) { - case 0x00: - case 0x04: - filterPtr = NTSCYFilter1; - break; - - case 0x01: - filterPtr = PALYFilter1; - break; - - case 0x02: - case 0x05: - case 0x0D: - case 0x03: - filterPtr = xgifb_palmn_yfilter1; - break; - - case 0x08: - case 0x0C: - case 0x0A: - case 0x0B: - case 0x09: - filterPtr = xgifb_yfilter2; - break; - - default: - return; - } - - tempal = XGI330_EModeIDTable[ModeIdIndex].VB_ExtTVYFilterIndex; - if (tempcl == 0) - index = tempal * 4; - else - index = tempal * 7; - - if ((tempcl == 0) && (tempch == 1)) { - xgifb_reg_set(pVBInfo->Part2Port, 0x35, 0); - xgifb_reg_set(pVBInfo->Part2Port, 0x36, 0); - xgifb_reg_set(pVBInfo->Part2Port, 0x37, 0); - xgifb_reg_set(pVBInfo->Part2Port, 0x38, filterPtr[index++]); - } else { - xgifb_reg_set(pVBInfo->Part2Port, 0x35, filterPtr[index++]); - xgifb_reg_set(pVBInfo->Part2Port, 0x36, filterPtr[index++]); - xgifb_reg_set(pVBInfo->Part2Port, 0x37, filterPtr[index++]); - xgifb_reg_set(pVBInfo->Part2Port, 0x38, filterPtr[index++]); - } - - if (pVBInfo->VBType & (VB_SIS301B | VB_SIS302B | VB_SIS301LV - | VB_SIS302LV | VB_XGI301C)) { - xgifb_reg_set(pVBInfo->Part2Port, 0x48, filterPtr[index++]); - xgifb_reg_set(pVBInfo->Part2Port, 0x49, filterPtr[index++]); - xgifb_reg_set(pVBInfo->Part2Port, 0x4A, filterPtr[index++]); - } -} - -/* --------------------------------------------------------------------- */ -/* Function : XGI_OEM310Setting */ -/* Input : */ -/* Output : */ -/* Description : Customized Param. for 301 */ -/* --------------------------------------------------------------------- */ -static void XGI_OEM310Setting(unsigned short ModeIdIndex, - struct vb_device_info *pVBInfo) -{ - XGI_SetDelayComp(pVBInfo); - - if (pVBInfo->VBInfo & (SetCRT2ToLCD | XGI_SetCRT2ToLCDA)) - XGI_SetLCDCap(pVBInfo); - - if (pVBInfo->VBInfo & SetCRT2ToTV) { - XGI_SetPhaseIncr(pVBInfo); - XGI_SetYFilter(ModeIdIndex, pVBInfo); - XGI_SetAntiFlicker(pVBInfo); - - if (pVBInfo->VBType & VB_SIS301) - XGI_SetEdgeEnhance(pVBInfo); - } -} - -/* --------------------------------------------------------------------- */ -/* Function : XGI_SetCRT2ModeRegs */ -/* Input : */ -/* Output : */ -/* Description : Origin code for crt2group */ -/* --------------------------------------------------------------------- */ -static void XGI_SetCRT2ModeRegs(struct vb_device_info *pVBInfo) -{ - unsigned short tempbl; - short tempcl; - - unsigned char tempah; - - tempah = 0; - if (!(pVBInfo->VBInfo & DisableCRT2Display)) { - tempah = xgifb_reg_get(pVBInfo->Part1Port, 0x00); - tempah &= ~0x10; /* BTRAMDAC */ - tempah |= 0x40; /* BTRAM */ - - if (pVBInfo->VBInfo & (SetCRT2ToRAMDAC | SetCRT2ToTV - | SetCRT2ToLCD)) { - tempah = 0x40; /* BTDRAM */ - tempcl = pVBInfo->ModeType; - tempcl -= ModeVGA; - if (tempcl >= 0) { - /* BT Color */ - tempah = (0x008 >> tempcl); - if (tempah == 0) - tempah = 1; - tempah |= 0x040; - } - if (pVBInfo->VBInfo & SetInSlaveMode) - tempah ^= 0x50; /* BTDAC */ - } - } - - xgifb_reg_set(pVBInfo->Part1Port, 0x00, tempah); - tempah = 0x08; - tempbl = 0xf0; - - if (pVBInfo->VBInfo & DisableCRT2Display) - goto reg_and_or; - - tempah = 0x00; - tempbl = 0xff; - - if (!(pVBInfo->VBInfo & (SetCRT2ToRAMDAC | SetCRT2ToTV | - SetCRT2ToLCD | XGI_SetCRT2ToLCDA))) - goto reg_and_or; - - if ((pVBInfo->VBInfo & XGI_SetCRT2ToLCDA) && - (!(pVBInfo->VBInfo & SetSimuScanMode))) { - tempbl &= 0xf7; - tempah |= 0x01; - goto reg_and_or; - } - - if (pVBInfo->VBInfo & XGI_SetCRT2ToLCDA) { - tempbl &= 0xf7; - tempah |= 0x01; - } - - if (!(pVBInfo->VBInfo & (SetCRT2ToRAMDAC | SetCRT2ToTV | SetCRT2ToLCD))) - goto reg_and_or; - - tempbl &= 0xf8; - tempah = 0x01; - - if (!(pVBInfo->VBInfo & SetInSlaveMode)) - tempah |= 0x02; - - if (!(pVBInfo->VBInfo & SetCRT2ToRAMDAC)) { - tempah = tempah ^ 0x05; - if (!(pVBInfo->VBInfo & SetCRT2ToLCD)) - tempah = tempah ^ 0x01; - } - - if (!(pVBInfo->VBInfo & SetCRT2ToDualEdge)) - tempah |= 0x08; - -reg_and_or: - xgifb_reg_and_or(pVBInfo->Part1Port, 0x2e, tempbl, tempah); - - if (pVBInfo->VBInfo & (SetCRT2ToRAMDAC | SetCRT2ToTV | SetCRT2ToLCD - | XGI_SetCRT2ToLCDA)) { - tempah &= (~0x08); - if ((pVBInfo->ModeType == ModeVGA) && (!(pVBInfo->VBInfo - & SetInSlaveMode))) { - tempah |= 0x010; - } - tempah |= 0x080; - - if (pVBInfo->VBInfo & SetCRT2ToTV) { - tempah |= 0x020; - if (pVBInfo->VBInfo & DriverMode) - tempah = tempah ^ 0x20; - } - - xgifb_reg_and_or(pVBInfo->Part4Port, 0x0D, ~0x0BF, tempah); - tempah = 0; - - if (pVBInfo->LCDInfo & SetLCDDualLink) - tempah |= 0x40; - - if (pVBInfo->VBInfo & SetCRT2ToTV) { - if (pVBInfo->TVInfo & RPLLDIV2XO) - tempah |= 0x40; - } - - if ((pVBInfo->LCDResInfo == Panel_1280x1024) - || (pVBInfo->LCDResInfo == Panel_1280x1024x75)) - tempah |= 0x80; - - if (pVBInfo->LCDResInfo == Panel_1280x960) - tempah |= 0x80; - - xgifb_reg_set(pVBInfo->Part4Port, 0x0C, tempah); - } - - if (pVBInfo->VBType & (VB_SIS301B | VB_SIS302B | VB_SIS301LV - | VB_SIS302LV | VB_XGI301C)) { - tempah = 0; - tempbl = 0xfb; - - if (pVBInfo->VBInfo & SetCRT2ToDualEdge) { - tempbl = 0xff; - if (pVBInfo->VBInfo & XGI_SetCRT2ToLCDA) - tempah |= 0x04; /* shampoo 0129 */ - } - - xgifb_reg_and_or(pVBInfo->Part1Port, 0x13, tempbl, tempah); - tempah = 0x00; - tempbl = 0xcf; - if (!(pVBInfo->VBInfo & DisableCRT2Display)) { - if (pVBInfo->VBInfo & SetCRT2ToDualEdge) - tempah |= 0x30; - } - - xgifb_reg_and_or(pVBInfo->Part1Port, 0x2c, tempbl, tempah); - tempah = 0; - tempbl = 0x3f; - - if (!(pVBInfo->VBInfo & DisableCRT2Display)) { - if (pVBInfo->VBInfo & SetCRT2ToDualEdge) - tempah |= 0xc0; - } - xgifb_reg_and_or(pVBInfo->Part4Port, 0x21, tempbl, tempah); - } - - tempah = 0; - tempbl = 0x7f; - if (!(pVBInfo->VBInfo & XGI_SetCRT2ToLCDA)) { - tempbl = 0xff; - if (!(pVBInfo->VBInfo & SetCRT2ToDualEdge)) - tempah |= 0x80; - } - - xgifb_reg_and_or(pVBInfo->Part4Port, 0x23, tempbl, tempah); - - if (pVBInfo->VBType & (VB_SIS302LV | VB_XGI301C)) { - if (pVBInfo->LCDInfo & SetLCDDualLink) { - xgifb_reg_or(pVBInfo->Part4Port, 0x27, 0x20); - xgifb_reg_or(pVBInfo->Part4Port, 0x34, 0x10); - } - } -} - - -void XGI_UnLockCRT2(struct vb_device_info *pVBInfo) -{ - xgifb_reg_and_or(pVBInfo->Part1Port, 0x2f, 0xFF, 0x01); -} - -void XGI_LockCRT2(struct vb_device_info *pVBInfo) -{ - xgifb_reg_and_or(pVBInfo->Part1Port, 0x2F, 0xFE, 0x00); -} - -unsigned short XGI_GetRatePtrCRT2(struct xgi_hw_device_info *pXGIHWDE, - unsigned short ModeNo, unsigned short ModeIdIndex, - struct vb_device_info *pVBInfo) -{ - const u8 LCDARefreshIndex[] = { - 0x00, 0x00, 0x03, 0x01, 0x01, 0x01, 0x01, 0x00 }; - - unsigned short RefreshRateTableIndex, i, index, temp; - - index = xgifb_reg_get(pVBInfo->P3d4, 0x33); - index = index >> pVBInfo->SelectCRT2Rate; - index &= 0x0F; - - if (pVBInfo->LCDInfo & LCDNonExpanding) - index = 0; - - if (index > 0) - index--; - - if (pVBInfo->SetFlag & ProgrammingCRT2) { - if (pVBInfo->VBInfo & (SetCRT2ToLCD | XGI_SetCRT2ToLCDA)) { - temp = LCDARefreshIndex[pVBInfo->LCDResInfo & 0x07]; - - if (index > temp) - index = temp; - } - } - - RefreshRateTableIndex = XGI330_EModeIDTable[ModeIdIndex].REFindex; - ModeNo = XGI330_RefIndex[RefreshRateTableIndex].ModeID; - if (pXGIHWDE->jChipType >= XG20) { /* for XG20, XG21, XG27 */ - if ((XGI330_RefIndex[RefreshRateTableIndex].XRes == 800) && - (XGI330_RefIndex[RefreshRateTableIndex].YRes == 600)) { - index++; - } - /* do the similar adjustment like XGISearchCRT1Rate() */ - if ((XGI330_RefIndex[RefreshRateTableIndex].XRes == 1024) && - (XGI330_RefIndex[RefreshRateTableIndex].YRes == 768)) { - index++; - } - if ((XGI330_RefIndex[RefreshRateTableIndex].XRes == 1280) && - (XGI330_RefIndex[RefreshRateTableIndex].YRes == 1024)) { - index++; - } - } - - i = 0; - do { - if (XGI330_RefIndex[RefreshRateTableIndex + i]. - ModeID != ModeNo) - break; - temp = XGI330_RefIndex[RefreshRateTableIndex + i].Ext_InfoFlag; - temp &= ModeTypeMask; - if (temp < pVBInfo->ModeType) - break; - i++; - index--; - - } while (index != 0xFFFF); - if (!(pVBInfo->VBInfo & SetCRT2ToRAMDAC)) { - if (pVBInfo->VBInfo & SetInSlaveMode) { - temp = XGI330_RefIndex[RefreshRateTableIndex + i - 1]. - Ext_InfoFlag; - if (temp & InterlaceMode) - i++; - } - } - i--; - if ((pVBInfo->SetFlag & ProgrammingCRT2)) { - temp = XGI_AjustCRT2Rate(ModeIdIndex, RefreshRateTableIndex, - &i, pVBInfo); - } - return RefreshRateTableIndex + i; -} - -static void XGI_SetLCDAGroup(unsigned short ModeNo, unsigned short ModeIdIndex, - struct xgi_hw_device_info *HwDeviceExtension, - struct vb_device_info *pVBInfo) -{ - unsigned short RefreshRateTableIndex; - - pVBInfo->SetFlag |= ProgrammingCRT2; - RefreshRateTableIndex = XGI_GetRatePtrCRT2(HwDeviceExtension, ModeNo, - ModeIdIndex, pVBInfo); - XGI_GetLVDSResInfo(ModeIdIndex, pVBInfo); - XGI_GetLVDSData(ModeIdIndex, pVBInfo); - XGI_ModCRT1Regs(ModeIdIndex, HwDeviceExtension, pVBInfo); - XGI_SetLVDSRegs(ModeIdIndex, pVBInfo); - XGI_SetCRT2ECLK(ModeIdIndex, RefreshRateTableIndex, pVBInfo); -} - -static unsigned char XGI_SetCRT2Group301(unsigned short ModeNo, - struct xgi_hw_device_info *HwDeviceExtension, - struct vb_device_info *pVBInfo) -{ - unsigned short ModeIdIndex, RefreshRateTableIndex; - - pVBInfo->SetFlag |= ProgrammingCRT2; - XGI_SearchModeID(ModeNo, &ModeIdIndex); - pVBInfo->SelectCRT2Rate = 4; - RefreshRateTableIndex = XGI_GetRatePtrCRT2(HwDeviceExtension, ModeNo, - ModeIdIndex, pVBInfo); - XGI_SaveCRT2Info(ModeNo, pVBInfo); - XGI_GetCRT2ResInfo(ModeIdIndex, pVBInfo); - XGI_GetCRT2Data(ModeIdIndex, RefreshRateTableIndex, pVBInfo); - XGI_PreSetGroup1(ModeNo, ModeIdIndex, RefreshRateTableIndex, pVBInfo); - XGI_SetGroup1(ModeIdIndex, RefreshRateTableIndex, pVBInfo); - XGI_SetLockRegs(ModeNo, ModeIdIndex, pVBInfo); - XGI_SetGroup2(ModeNo, ModeIdIndex, pVBInfo); - XGI_SetLCDRegs(ModeIdIndex, pVBInfo); - XGI_SetTap4Regs(pVBInfo); - XGI_SetGroup3(ModeIdIndex, pVBInfo); - XGI_SetGroup4(ModeIdIndex, RefreshRateTableIndex, pVBInfo); - XGI_SetCRT2VCLK(ModeIdIndex, RefreshRateTableIndex, pVBInfo); - XGI_SetGroup5(pVBInfo); - XGI_AutoThreshold(pVBInfo); - return 1; -} - -void XGI_SenseCRT1(struct vb_device_info *pVBInfo) -{ - unsigned char CRTCData[17] = { 0x5F, 0x4F, 0x50, 0x82, 0x55, 0x81, - 0x0B, 0x3E, 0xE9, 0x0B, 0xDF, 0xE7, 0x04, 0x00, 0x00, - 0x05, 0x00 }; - - unsigned char SR01 = 0, SR1F = 0, SR07 = 0, SR06 = 0; - - unsigned char CR17, CR63, SR31; - unsigned short temp; - - int i; - - xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86); - - /* to fix XG42 single LCD sense to CRT+LCD */ - xgifb_reg_set(pVBInfo->P3d4, 0x57, 0x4A); - xgifb_reg_set(pVBInfo->P3d4, 0x53, (xgifb_reg_get( - pVBInfo->P3d4, 0x53) | 0x02)); - - SR31 = xgifb_reg_get(pVBInfo->P3c4, 0x31); - CR63 = xgifb_reg_get(pVBInfo->P3d4, 0x63); - SR01 = xgifb_reg_get(pVBInfo->P3c4, 0x01); - - xgifb_reg_set(pVBInfo->P3c4, 0x01, (unsigned char) (SR01 & 0xDF)); - xgifb_reg_set(pVBInfo->P3d4, 0x63, (unsigned char) (CR63 & 0xBF)); - - CR17 = xgifb_reg_get(pVBInfo->P3d4, 0x17); - xgifb_reg_set(pVBInfo->P3d4, 0x17, (unsigned char) (CR17 | 0x80)); - - SR1F = xgifb_reg_get(pVBInfo->P3c4, 0x1F); - xgifb_reg_set(pVBInfo->P3c4, 0x1F, (unsigned char) (SR1F | 0x04)); - - SR07 = xgifb_reg_get(pVBInfo->P3c4, 0x07); - xgifb_reg_set(pVBInfo->P3c4, 0x07, (unsigned char) (SR07 & 0xFB)); - SR06 = xgifb_reg_get(pVBInfo->P3c4, 0x06); - xgifb_reg_set(pVBInfo->P3c4, 0x06, (unsigned char) (SR06 & 0xC3)); - - xgifb_reg_set(pVBInfo->P3d4, 0x11, 0x00); - - for (i = 0; i < 8; i++) - xgifb_reg_set(pVBInfo->P3d4, (unsigned short) i, CRTCData[i]); - - for (i = 8; i < 11; i++) - xgifb_reg_set(pVBInfo->P3d4, (unsigned short) (i + 8), - CRTCData[i]); - - for (i = 11; i < 13; i++) - xgifb_reg_set(pVBInfo->P3d4, (unsigned short) (i + 4), - CRTCData[i]); - - for (i = 13; i < 16; i++) - xgifb_reg_set(pVBInfo->P3c4, (unsigned short) (i - 3), - CRTCData[i]); - - xgifb_reg_set(pVBInfo->P3c4, 0x0E, (unsigned char) (CRTCData[16] - & 0xE0)); - - xgifb_reg_set(pVBInfo->P3c4, 0x31, 0x00); - xgifb_reg_set(pVBInfo->P3c4, 0x2B, 0x1B); - xgifb_reg_set(pVBInfo->P3c4, 0x2C, 0xE1); - - outb(0x00, pVBInfo->P3c8); - - for (i = 0; i < 256 * 3; i++) - outb(0x0F, (pVBInfo->P3c8 + 1)); /* DAC_TEST_PARMS */ - - mdelay(1); - - XGI_WaitDisply(pVBInfo); - temp = inb(pVBInfo->P3c2); - - if (temp & 0x10) - xgifb_reg_and_or(pVBInfo->P3d4, 0x32, 0xDF, 0x20); - else - xgifb_reg_and_or(pVBInfo->P3d4, 0x32, 0xDF, 0x00); - - /* avoid display something, set BLACK DAC if not restore DAC */ - outb(0x00, pVBInfo->P3c8); - - for (i = 0; i < 256 * 3; i++) - outb(0, (pVBInfo->P3c8 + 1)); - - xgifb_reg_set(pVBInfo->P3c4, 0x01, SR01); - xgifb_reg_set(pVBInfo->P3d4, 0x63, CR63); - xgifb_reg_set(pVBInfo->P3c4, 0x31, SR31); - - xgifb_reg_set(pVBInfo->P3d4, 0x53, (xgifb_reg_get( - pVBInfo->P3d4, 0x53) & 0xFD)); - xgifb_reg_set(pVBInfo->P3c4, 0x1F, (unsigned char) SR1F); -} - -static void XGI_EnableBridge(struct xgifb_video_info *xgifb_info, - struct xgi_hw_device_info *HwDeviceExtension, - struct vb_device_info *pVBInfo) -{ - unsigned short tempah; - - if (pVBInfo->VBType & (VB_SIS301B | VB_SIS302B | VB_SIS301LV - | VB_SIS302LV | VB_XGI301C)) { - if (pVBInfo->VBInfo & SetCRT2ToDualEdge) - /* Power on */ - xgifb_reg_set(pVBInfo->Part1Port, 0x1E, 0x20); - - if (pVBInfo->VBInfo & (SetCRT2ToLCD | SetCRT2ToTV | - SetCRT2ToRAMDAC)) { - tempah = xgifb_reg_get(pVBInfo->P3c4, 0x32); - tempah &= 0xDF; - if (pVBInfo->VBInfo & SetInSlaveMode) { - if (!(pVBInfo->VBInfo & SetCRT2ToRAMDAC)) - tempah |= 0x20; - } - xgifb_reg_set(pVBInfo->P3c4, 0x32, tempah); - xgifb_reg_or(pVBInfo->P3c4, 0x1E, 0x20); - - tempah = xgifb_reg_get(pVBInfo->Part1Port, 0x2E); - - if (!(tempah & 0x80)) - xgifb_reg_or(pVBInfo->Part1Port, 0x2E, 0x80); - xgifb_reg_and(pVBInfo->Part1Port, 0x00, 0x7F); - } - - if (!(pVBInfo->VBInfo & DisableCRT2Display)) { - xgifb_reg_and_or(pVBInfo->Part2Port, 0x00, ~0xE0, - 0x20); /* shampoo 0129 */ - if (pVBInfo->VBType & (VB_SIS302LV | VB_XGI301C)) { - if (pVBInfo->VBInfo & - (SetCRT2ToLCD | XGI_SetCRT2ToLCDA)) - /* LVDS PLL power on */ - xgifb_reg_and(pVBInfo->Part4Port, 0x2A, - 0x7F); - /* LVDS Driver power on */ - xgifb_reg_and(pVBInfo->Part4Port, 0x30, 0x7F); - } - } - - tempah = 0x00; - - if (!(pVBInfo->VBInfo & DisableCRT2Display)) { - tempah = 0xc0; - - if (!(pVBInfo->VBInfo & SetSimuScanMode) && - (pVBInfo->VBInfo & XGI_SetCRT2ToLCDA) && - (pVBInfo->VBInfo & SetCRT2ToDualEdge)) { - tempah = tempah & 0x40; - if (pVBInfo->VBInfo & XGI_SetCRT2ToLCDA) - tempah = tempah ^ 0xC0; - } - } - - /* EnablePart4_1F */ - xgifb_reg_or(pVBInfo->Part4Port, 0x1F, tempah); - - XGI_DisableGatingCRT(pVBInfo); - XGI_DisplayOn(xgifb_info, HwDeviceExtension, pVBInfo); - } /* 301 */ - else { /* LVDS */ - if (pVBInfo->VBInfo & (SetCRT2ToTV | SetCRT2ToLCD - | XGI_SetCRT2ToLCDA)) - /* enable CRT2 */ - xgifb_reg_or(pVBInfo->Part1Port, 0x1E, 0x20); - - tempah = xgifb_reg_get(pVBInfo->Part1Port, 0x2E); - if (!(tempah & 0x80)) - xgifb_reg_or(pVBInfo->Part1Port, 0x2E, 0x80); - - xgifb_reg_and(pVBInfo->Part1Port, 0x00, 0x7F); - XGI_DisplayOn(xgifb_info, HwDeviceExtension, pVBInfo); - } /* End of VB */ -} - -static void XGI_SetCRT1Group(struct xgifb_video_info *xgifb_info, - struct xgi_hw_device_info *HwDeviceExtension, - unsigned short ModeNo, unsigned short ModeIdIndex, - struct vb_device_info *pVBInfo) -{ - unsigned short RefreshRateTableIndex, temp; - - XGI_SetSeqRegs(pVBInfo); - outb(XGI330_StandTable.MISC, pVBInfo->P3c2); - XGI_SetCRTCRegs(pVBInfo); - XGI_SetATTRegs(ModeIdIndex, pVBInfo); - XGI_SetGRCRegs(pVBInfo); - XGI_ClearExt1Regs(pVBInfo); - - if (HwDeviceExtension->jChipType == XG27) { - if (pVBInfo->IF_DEF_LVDS == 0) - XGI_SetDefaultVCLK(pVBInfo); - } - - temp = ~ProgrammingCRT2; - pVBInfo->SetFlag &= temp; - pVBInfo->SelectCRT2Rate = 0; - - if (pVBInfo->VBType & (VB_SIS301B | VB_SIS302B | VB_SIS301LV - | VB_SIS302LV | VB_XGI301C)) { - if (pVBInfo->VBInfo & (SetSimuScanMode | XGI_SetCRT2ToLCDA - | SetInSlaveMode)) { - pVBInfo->SetFlag |= ProgrammingCRT2; - } - } - - RefreshRateTableIndex = XGI_GetRatePtrCRT2(HwDeviceExtension, ModeNo, - ModeIdIndex, pVBInfo); - if (RefreshRateTableIndex != 0xFFFF) { - XGI_SetSync(RefreshRateTableIndex, pVBInfo); - XGI_SetCRT1CRTC(ModeIdIndex, RefreshRateTableIndex, - pVBInfo, HwDeviceExtension); - XGI_SetCRT1DE(ModeIdIndex, RefreshRateTableIndex, pVBInfo); - XGI_SetCRT1Offset(ModeNo, ModeIdIndex, RefreshRateTableIndex, - HwDeviceExtension, pVBInfo); - XGI_SetCRT1VCLK(ModeIdIndex, HwDeviceExtension, - RefreshRateTableIndex, pVBInfo); - } - - if (HwDeviceExtension->jChipType >= XG21) { - temp = xgifb_reg_get(pVBInfo->P3d4, 0x38); - if (temp & 0xA0) { - - if (HwDeviceExtension->jChipType == XG27) - XGI_SetXG27CRTC(RefreshRateTableIndex, pVBInfo); - else - XGI_SetXG21CRTC(RefreshRateTableIndex, pVBInfo); - - XGI_UpdateXG21CRTC(ModeNo, pVBInfo, - RefreshRateTableIndex); - - xgifb_set_lcd(HwDeviceExtension->jChipType, - pVBInfo, RefreshRateTableIndex); - - if (pVBInfo->IF_DEF_LVDS == 1) - xgifb_set_lvds(xgifb_info, - HwDeviceExtension->jChipType, - ModeIdIndex, pVBInfo); - } - } - - pVBInfo->SetFlag &= (~ProgrammingCRT2); - XGI_SetCRT1FIFO(HwDeviceExtension, pVBInfo); - XGI_SetCRT1ModeRegs(HwDeviceExtension, ModeIdIndex, - RefreshRateTableIndex, pVBInfo); - XGI_LoadDAC(pVBInfo); -} - -unsigned char XGISetModeNew(struct xgifb_video_info *xgifb_info, - struct xgi_hw_device_info *HwDeviceExtension, - unsigned short ModeNo) -{ - unsigned short ModeIdIndex; - struct vb_device_info VBINF; - struct vb_device_info *pVBInfo = &VBINF; - - pVBInfo->IF_DEF_LVDS = 0; - - if (HwDeviceExtension->jChipType >= XG20) - pVBInfo->VBType = 0; /*set VBType default 0*/ - - XGIRegInit(pVBInfo, xgifb_info->vga_base); - - /* for x86 Linux, XG21 LVDS */ - if (HwDeviceExtension->jChipType == XG21) { - if ((xgifb_reg_get(pVBInfo->P3d4, 0x38) & 0xE0) == 0xC0) - pVBInfo->IF_DEF_LVDS = 1; - } - if (HwDeviceExtension->jChipType == XG27) { - if ((xgifb_reg_get(pVBInfo->P3d4, 0x38) & 0xE0) == 0xC0) { - if (xgifb_reg_get(pVBInfo->P3d4, 0x30) & 0x20) - pVBInfo->IF_DEF_LVDS = 1; - } - } - - InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo); - if (ModeNo & 0x80) - ModeNo = ModeNo & 0x7F; - xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86); - - if (HwDeviceExtension->jChipType < XG20) - XGI_UnLockCRT2(pVBInfo); - - XGI_SearchModeID(ModeNo, &ModeIdIndex); - - if (HwDeviceExtension->jChipType < XG20) { - XGI_GetVBInfo(ModeIdIndex, pVBInfo); - XGI_GetTVInfo(ModeIdIndex, pVBInfo); - XGI_GetLCDInfo(ModeIdIndex, pVBInfo); - XGI_DisableBridge(xgifb_info, HwDeviceExtension, pVBInfo); - - if (pVBInfo->VBInfo & (SetSimuScanMode | XGI_SetCRT2ToLCDA) || - (!(pVBInfo->VBInfo & SwitchCRT2))) { - XGI_SetCRT1Group(xgifb_info, HwDeviceExtension, ModeNo, - ModeIdIndex, pVBInfo); - - if (pVBInfo->VBInfo & XGI_SetCRT2ToLCDA) { - XGI_SetLCDAGroup(ModeNo, ModeIdIndex, - HwDeviceExtension, pVBInfo); - } - } - - if (pVBInfo->VBInfo & (SetSimuScanMode | SwitchCRT2)) { - switch (HwDeviceExtension->ujVBChipID) { - case VB_CHIP_301: /* fall through */ - case VB_CHIP_302: - XGI_SetCRT2Group301(ModeNo, HwDeviceExtension, - pVBInfo); /*add for CRT2 */ - break; - - default: - break; - } - } - - XGI_SetCRT2ModeRegs(pVBInfo); - XGI_OEM310Setting(ModeIdIndex, pVBInfo); /*0212*/ - XGI_EnableBridge(xgifb_info, HwDeviceExtension, pVBInfo); - } /* !XG20 */ - else { - if (pVBInfo->IF_DEF_LVDS == 1) - if (!XGI_XG21CheckLVDSMode(xgifb_info, ModeNo, - ModeIdIndex)) - return 0; - - pVBInfo->ModeType = XGI330_EModeIDTable[ModeIdIndex]. - Ext_ModeFlag & ModeTypeMask; - - pVBInfo->SetFlag = 0; - pVBInfo->VBInfo = DisableCRT2Display; - - XGI_DisplayOff(xgifb_info, HwDeviceExtension, pVBInfo); - - XGI_SetCRT1Group(xgifb_info, HwDeviceExtension, ModeNo, - ModeIdIndex, pVBInfo); - - XGI_DisplayOn(xgifb_info, HwDeviceExtension, pVBInfo); - } - - XGI_UpdateModeInfo(pVBInfo); - - if (HwDeviceExtension->jChipType < XG20) - XGI_LockCRT2(pVBInfo); - - return 1; -} diff --git a/src/drivers/xgi/common/vb_setmode.h b/src/drivers/xgi/common/vb_setmode.h deleted file mode 100644 index 3d11d4ad4e..0000000000 --- a/src/drivers/xgi/common/vb_setmode.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* File taken from the Linux xgifb driver (v3.18.5) */ - -#ifndef _VBSETMODE_ -#define _VBSETMODE_ - -extern void InitTo330Pointer(unsigned char, struct vb_device_info *); -extern void XGI_UnLockCRT2(struct vb_device_info *); -extern void XGI_LockCRT2(struct vb_device_info *); -extern void XGI_DisplayOff(struct xgifb_video_info *, - struct xgi_hw_device_info *, - struct vb_device_info *); -extern void XGI_GetVBType(struct vb_device_info *); -extern void XGI_SenseCRT1(struct vb_device_info *); -extern unsigned char XGISetModeNew(struct xgifb_video_info *xgifb_info, - struct xgi_hw_device_info *HwDeviceExtension, - unsigned short ModeNo); - -extern unsigned char XGI_SearchModeID(unsigned short ModeNo, - unsigned short *ModeIdIndex); -extern unsigned short XGI_GetRatePtrCRT2(struct xgi_hw_device_info *pXGIHWDE, - unsigned short ModeNo, - unsigned short ModeIdIndex, - struct vb_device_info *); - -#endif diff --git a/src/drivers/xgi/common/vb_struct.h b/src/drivers/xgi/common/vb_struct.h deleted file mode 100644 index 11aa634a2f..0000000000 --- a/src/drivers/xgi/common/vb_struct.h +++ /dev/null @@ -1,169 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* File taken from the Linux xgifb driver (v3.18.5) */ - -#ifndef _VB_STRUCT_ -#define _VB_STRUCT_ - -struct XGI_LVDSCRT1HDataStruct { - unsigned char Reg[8]; -}; - -struct XGI_LVDSCRT1VDataStruct { - unsigned char Reg[7]; -}; - -struct XGI_ExtStruct { - unsigned char Ext_ModeID; - unsigned short Ext_ModeFlag; - unsigned short Ext_ModeInfo; - unsigned char Ext_RESINFO; - unsigned char VB_ExtTVYFilterIndex; - unsigned char REFindex; -}; - -struct XGI_Ext2Struct { - unsigned short Ext_InfoFlag; - unsigned char Ext_CRT1CRTC; - unsigned char Ext_CRTVCLK; - unsigned char Ext_CRT2CRTC; - unsigned char Ext_CRT2CRTC2; - unsigned char ModeID; - unsigned short XRes; - unsigned short YRes; -}; - -struct XGI_ECLKDataStruct { - unsigned char SR2E, SR2F, SR30; - unsigned short CLOCK; -}; - -/*add for new UNIVGABIOS*/ -struct XGI_LCDDesStruct { - unsigned short LCDHDES; - unsigned short LCDHRS; - unsigned short LCDVDES; - unsigned short LCDVRS; -}; - -struct XGI330_LCDDataDesStruct2 { - unsigned short LCDHDES; - unsigned short LCDHRS; - unsigned short LCDVDES; - unsigned short LCDVRS; - unsigned short LCDHSync; - unsigned short LCDVSync; -}; - -struct XGI330_LCDDataTablStruct { - unsigned char PANELID; - unsigned short MASK; - unsigned short CAP; - void const *DATAPTR; -}; - -struct XGI330_TVDataTablStruct { - unsigned short MASK; - unsigned short CAP; - struct SiS_TVData const *DATAPTR; -}; - - -struct XGI_TimingHStruct { - unsigned char data[8]; -}; - -struct XGI_TimingVStruct { - unsigned char data[7]; -}; - -struct XGI_XG21CRT1Struct { - unsigned char ModeID, CR02, CR03, CR15, CR16; -}; - -struct XGI330_LCDCapStruct { - unsigned char LCD_ID; - unsigned short LCD_Capability; - unsigned char LCD_HSyncWidth; - unsigned char LCD_VSyncWidth; - unsigned char LCD_VCLK; - unsigned char LCDA_VCLKData1; - unsigned char LCDA_VCLKData2; - unsigned char LCUCHAR_VCLKData1; - unsigned char LCUCHAR_VCLKData2; - unsigned char Spectrum_31; - unsigned char Spectrum_32; - unsigned char Spectrum_33; - unsigned char Spectrum_34; -}; - -struct XGI21_LVDSCapStruct { - unsigned short LVDS_Capability; - unsigned short LVDSHT; - unsigned short LVDSVT; - unsigned short LVDSHDE; - unsigned short LVDSVDE; - unsigned short LVDSHFP; - unsigned short LVDSVFP; - unsigned short LVDSHSYNC; - unsigned short LVDSVSYNC; - unsigned char VCLKData1; - unsigned char VCLKData2; - unsigned char PSC_S1; /* Duration between CPL on and signal on */ - unsigned char PSC_S2; /* Duration signal on and Vdd on */ - unsigned char PSC_S3; /* Duration between CPL off and signal off */ - unsigned char PSC_S4; /* Duration signal off and Vdd off */ - unsigned char PSC_S5; -}; - -struct XGI_CRT1TableStruct { - unsigned char CR[16]; -}; - - -struct XGI301C_Tap4TimingStruct { - unsigned short DE; - unsigned char Reg[64]; /* C0-FF */ -}; - -struct vb_device_info { - unsigned long P3c4, P3d4, P3c0, P3ce, P3c2, P3cc; - unsigned long P3ca, P3c6, P3c7, P3c8, P3c9, P3da; - unsigned long Part0Port, Part1Port, Part2Port; - unsigned long Part3Port, Part4Port, Part5Port; - unsigned short RVBHCFACT, RVBHCMAX, RVBHRS; - unsigned short VGAVT, VGAHT, VGAVDE, VGAHDE; - unsigned short VT, HT, VDE, HDE; - unsigned short LCDHRS, LCDVRS, LCDHDES, LCDVDES; - - unsigned short ModeType; - unsigned short IF_DEF_LVDS; - unsigned short IF_DEF_CRT2Monitor; - unsigned short IF_DEF_YPbPr; - unsigned short IF_DEF_HiVision; - unsigned short LCDResInfo, LCDTypeInfo, VBType;/*301b*/ - unsigned short VBInfo, TVInfo, LCDInfo; - unsigned short SetFlag; - unsigned short NewFlickerMode; - unsigned short SelectCRT2Rate; - - void __iomem *FBAddr; - - unsigned char const *SR18; - unsigned char const (*CR40)[3]; - - struct SiS_MCLKData const *MCLKData; - - unsigned char XGINew_CR97; - - struct XGI330_LCDCapStruct const *LCDCapList; - - struct XGI_TimingHStruct TimingH; - struct XGI_TimingVStruct TimingV; - - int ram_type; - int ram_channel; - int ram_bus; -}; /* _struct vb_device_info */ - -#endif /* _VB_STRUCT_ */ diff --git a/src/drivers/xgi/common/vb_table.h b/src/drivers/xgi/common/vb_table.h deleted file mode 100644 index 59c88984ad..0000000000 --- a/src/drivers/xgi/common/vb_table.h +++ /dev/null @@ -1,2495 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* File taken from the Linux xgifb driver (v3.18.5) */ - -#ifndef _VB_TABLE_ -#define _VB_TABLE_ -static const struct SiS_MCLKData XGI340New_MCLKData[] = { - {0x16, 0x01, 0x01, 166}, - {0x19, 0x02, 0x01, 124}, - {0x7C, 0x08, 0x01, 200}, -}; - -static const struct SiS_MCLKData XGI27New_MCLKData[] = { - {0x5c, 0x23, 0x01, 166}, - {0x19, 0x02, 0x01, 124}, - {0x7C, 0x08, 0x80, 200}, -}; - -const struct XGI_ECLKDataStruct XGI340_ECLKData[] = { - {0x5c, 0x23, 0x01, 166}, - {0x55, 0x84, 0x01, 123}, - {0x7C, 0x08, 0x01, 200}, -}; - -static const unsigned char XG27_SR18[3] = { - 0x32, 0x32, 0x42 /* SR18 */ -}; - -static const unsigned char XGI340_SR18[3] = { - 0x31, 0x42, 0x42 /* SR18 */ -}; - -static const unsigned char XGI340_cr41[24][3] = { - {0x20, 0x50, 0x60}, /* 0 CR41 */ - {0xc4, 0x40, 0x84}, /* 1 CR8A */ - {0xc4, 0x40, 0x84}, /* 2 CR8B */ - {0xb5, 0xa4, 0xa4}, - {0xf0, 0xf0, 0xf0}, - {0x90, 0x90, 0x24}, /* 5 CR68 */ - {0x77, 0x77, 0x44}, /* 6 CR69 */ - {0x77, 0x77, 0x44}, /* 7 CR6A */ - {0xff, 0xff, 0xff}, /* 8 CR6D */ - {0x55, 0x55, 0x55}, /* 9 CR80 */ - {0x00, 0x00, 0x00}, /* 10 CR81 */ - {0x88, 0xa8, 0x48}, /* 11 CR82 */ - {0x44, 0x44, 0x77}, /* 12 CR85 */ - {0x48, 0x48, 0x88}, /* 13 CR86 */ - {0x54, 0x54, 0x44}, /* 14 CR90 */ - {0x54, 0x54, 0x44}, /* 15 CR91 */ - {0x0a, 0x0a, 0x07}, /* 16 CR92 */ - {0x44, 0x44, 0x44}, /* 17 CR93 */ - {0x10, 0x10, 0x0A}, /* 18 CR94 */ - {0x11, 0x11, 0x0a}, /* 19 CR95 */ - {0x05, 0x05, 0x05}, /* 20 CR96 */ - {0xf0, 0xf0, 0xf0}, /* 21 CRC3 */ - {0x05, 0x00, 0x02}, /* 22 CRC4 */ - {0x00, 0x00, 0x00} /* 23 CRC5 */ -}; - -static const unsigned char XGI27_cr41[24][3] = { - {0x20, 0x40, 0x60}, /* 0 CR41 */ - {0xC4, 0x40, 0x84}, /* 1 CR8A */ - {0xC4, 0x40, 0x84}, /* 2 CR8B */ - {0xB3, 0x13, 0xa4}, /* 3 CR40[7], - CR99[2:0], - CR45[3:0]*/ - {0xf0, 0xf5, 0xf0}, /* 4 CR59 */ - {0x90, 0x90, 0x24}, /* 5 CR68 */ - {0x77, 0x67, 0x44}, /* 6 CR69 */ - {0x77, 0x77, 0x44}, /* 7 CR6A */ - {0xff, 0xff, 0xff}, /* 8 CR6D */ - {0x55, 0x55, 0x55}, /* 9 CR80 */ - {0x00, 0x00, 0x00}, /* 10 CR81 */ - {0x88, 0xcc, 0x48}, /* 11 CR82 */ - {0x44, 0x88, 0x77}, /* 12 CR85 */ - {0x48, 0x88, 0x88}, /* 13 CR86 */ - {0x54, 0x32, 0x44}, /* 14 CR90 */ - {0x54, 0x33, 0x44}, /* 15 CR91 */ - {0x0a, 0x07, 0x07}, /* 16 CR92 */ - {0x44, 0x63, 0x44}, /* 17 CR93 */ - {0x10, 0x14, 0x0A}, /* 18 CR94 */ - {0x11, 0x0B, 0x0C}, /* 19 CR95 */ - {0x05, 0x22, 0x05}, /* 20 CR96 */ - {0xf0, 0xf0, 0x00}, /* 21 CRC3 */ - {0x05, 0x00, 0x02}, /* 22 CRC4 */ - {0x00, 0x00, 0x00} /* 23 CRC5 */ -}; - -/* CR47,CR48,CR49,CR4A,CR4B,CR4C,CR70,CR71,CR74,CR75,CR76,CR77 */ -const unsigned char XGI340_AGPReg[12] = { - 0x28, 0x23, 0x00, 0x20, 0x00, 0x20, - 0x00, 0x05, 0xd0, 0x10, 0x10, 0x00 -}; - -const struct XGI_ExtStruct XGI330_EModeIDTable[] = { - {0x2e, 0x0a1b, 0x0306, 0x06, 0x05, 0x06}, - {0x2f, 0x0a1b, 0x0305, 0x05, 0x05, 0x05}, - {0x30, 0x2a1b, 0x0407, 0x07, 0x07, 0x0e}, - {0x31, 0x0a1b, 0x030d, 0x0d, 0x06, 0x3d}, - {0x32, 0x0a1b, 0x0a0e, 0x0e, 0x06, 0x3e}, - {0x33, 0x0a1d, 0x0a0d, 0x0d, 0x06, 0x3d}, - {0x34, 0x2a1d, 0x0a0e, 0x0e, 0x06, 0x3e}, - {0x35, 0x0a1f, 0x0a0d, 0x0d, 0x06, 0x3d}, - {0x36, 0x2a1f, 0x0a0e, 0x0e, 0x06, 0x3e}, - {0x38, 0x0a1b, 0x0508, 0x08, 0x00, 0x16}, - {0x3a, 0x0e3b, 0x0609, 0x09, 0x00, 0x1e}, - {0x3c, 0x0e3b, 0x070a, 0x0a, 0x00, 0x22}, /* mode 1600x1200 - add CRT2MODE [2003/10/07] */ - {0x3d, 0x0e7d, 0x070a, 0x0a, 0x00, 0x22}, /* mode 1600x1200 - add CRT2MODE */ - {0x40, 0x9a1c, 0x0000, 0x00, 0x04, 0x00}, - {0x41, 0x9a1d, 0x0000, 0x00, 0x04, 0x00}, - {0x43, 0x0a1c, 0x0306, 0x06, 0x05, 0x06}, - {0x44, 0x0a1d, 0x0306, 0x06, 0x05, 0x06}, - {0x46, 0x2a1c, 0x0407, 0x07, 0x07, 0x0e}, - {0x47, 0x2a1d, 0x0407, 0x07, 0x07, 0x0e}, - {0x49, 0x0a3c, 0x0508, 0x08, 0x00, 0x16}, - {0x4a, 0x0a3d, 0x0508, 0x08, 0x00, 0x16}, - {0x4c, 0x0e7c, 0x0609, 0x09, 0x00, 0x1e}, - {0x4d, 0x0e7d, 0x0609, 0x09, 0x00, 0x1e}, - {0x50, 0x9a1b, 0x0001, 0x01, 0x04, 0x02}, - {0x51, 0xba1b, 0x0103, 0x03, 0x07, 0x03}, - {0x52, 0x9a1b, 0x0204, 0x04, 0x00, 0x04}, - {0x56, 0x9a1d, 0x0001, 0x01, 0x04, 0x02}, - {0x57, 0xba1d, 0x0103, 0x03, 0x07, 0x03}, - {0x58, 0x9a1d, 0x0204, 0x04, 0x00, 0x04}, - {0x59, 0x9a1b, 0x0000, 0x00, 0x04, 0x00}, - {0x5A, 0x021b, 0x0014, 0x01, 0x04, 0x3f}, - {0x5B, 0x0a1d, 0x0014, 0x01, 0x04, 0x3f}, - {0x5d, 0x0a1d, 0x0305, 0x05, 0x07, 0x05}, - {0x62, 0x0a3f, 0x0306, 0x06, 0x05, 0x06}, - {0x63, 0x2a3f, 0x0407, 0x07, 0x07, 0x0e}, - {0x64, 0x0a7f, 0x0508, 0x08, 0x00, 0x16}, - {0x65, 0x0eff, 0x0609, 0x09, 0x00, 0x1e}, - {0x66, 0x0eff, 0x070a, 0x0a, 0x00, 0x22}, /* mode 1600x1200 - add CRT2MODE */ - {0x68, 0x067b, 0x080b, 0x0b, 0x00, 0x29}, - {0x69, 0x06fd, 0x080b, 0x0b, 0x00, 0x29}, - {0x6b, 0x07ff, 0x080b, 0x0b, 0x00, 0x29}, - {0x6c, 0x067b, 0x090c, 0x0c, 0x00, 0x2f}, - {0x6d, 0x06fd, 0x090c, 0x0c, 0x00, 0x2f}, - {0x6e, 0x07ff, 0x090c, 0x0c, 0x00, 0x2f}, - {0x70, 0x2a1b, 0x0410, 0x10, 0x07, 0x34}, - {0x71, 0x0a1b, 0x0511, 0x11, 0x00, 0x37}, - {0x74, 0x0a1d, 0x0511, 0x11, 0x00, 0x37}, - {0x75, 0x0a3d, 0x0612, 0x12, 0x00, 0x3a}, - {0x76, 0x2a1f, 0x0410, 0x10, 0x07, 0x34}, - {0x77, 0x0a1f, 0x0511, 0x11, 0x00, 0x37}, - {0x78, 0x0a3f, 0x0612, 0x12, 0x00, 0x3a}, - {0x79, 0x0a3b, 0x0612, 0x12, 0x00, 0x3a}, - {0x7a, 0x2a1d, 0x0410, 0x10, 0x07, 0x34}, - {0x7b, 0x0e3b, 0x060f, 0x0f, 0x00, 0x1d}, - {0x7c, 0x0e7d, 0x060f, 0x0f, 0x00, 0x1d}, - {0x7d, 0x0eff, 0x060f, 0x0f, 0x00, 0x1d}, - {0x20, 0x0e3b, 0x0D16, 0x16, 0x00, 0x43}, - {0x21, 0x0e7d, 0x0D16, 0x16, 0x00, 0x43}, - {0x22, 0x0eff, 0x0D16, 0x16, 0x00, 0x43}, - {0x23, 0x0e3b, 0x0614, 0x14, 0x00, 0x41}, - {0x24, 0x0e7d, 0x0614, 0x14, 0x00, 0x41}, - {0x25, 0x0eff, 0x0614, 0x14, 0x00, 0x41}, - {0x26, 0x063b, 0x0c15, 0x15, 0x00, 0x42}, - {0x27, 0x067d, 0x0c15, 0x15, 0x00, 0x42}, - {0x28, 0x06ff, 0x0c15, 0x15, 0x00, 0x42}, - {0xff, 0x0000, 0x0000, 0x00, 0x00, 0x00} -}; - -static const struct SiS_StandTable_S XGI330_StandTable = { -/* ExtVGATable */ - 0x00, 0x00, 0x00, 0x0000, - {0x21, 0x0f, 0x00, 0x0e}, /* 0x21 = 0x01 | (0x20 = screen off) */ - 0x23, - {0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, - 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xea, 0x8c, 0xdf, 0x28, 0x40, 0xe7, 0x04, 0xa3, - 0xff}, - {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, - 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - 0x01, 0x00, 0x00, 0x00}, - {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0f, - 0xff} -}; - -static const struct XGI_XG21CRT1Struct XGI_UpdateCRT1Table[] = { - {0x01, 0x27, 0x91, 0x8f, 0xc0}, /* 00 */ - {0x03, 0x4f, 0x83, 0x8f, 0xc0}, /* 01 */ - {0x05, 0x27, 0x91, 0x8f, 0xc0}, /* 02 */ - {0x06, 0x4f, 0x83, 0x8f, 0xc0}, /* 03 */ - {0x07, 0x4f, 0x83, 0x8f, 0xc0}, /* 04 */ - {0x0d, 0x27, 0x91, 0x8f, 0xc0}, /* 05 */ - {0x0e, 0x4f, 0x83, 0x8f, 0xc0}, /* 06 */ - {0x0f, 0x4f, 0x83, 0x5d, 0xc0}, /* 07 */ - {0x10, 0x4f, 0x83, 0x5d, 0xc0}, /* 08 */ - {0x11, 0x4f, 0x83, 0xdf, 0x0c}, /* 09 */ - {0x12, 0x4f, 0x83, 0xdf, 0x0c}, /* 10 */ - {0x13, 0x4f, 0x83, 0x8f, 0xc0}, /* 11 */ - {0x2e, 0x4f, 0x83, 0xdf, 0x0c}, /* 12 */ - {0x2e, 0x4f, 0x87, 0xdf, 0xc0}, /* 13 */ - {0x2f, 0x4f, 0x83, 0x8f, 0xc0}, /* 14 */ - {0x50, 0x27, 0x91, 0xdf, 0x0c}, /* 15 */ - {0x59, 0x27, 0x91, 0x8f, 0xc0} /* 16 */ -}; - -const struct XGI_CRT1TableStruct XGI_CRT1Table[] = { - { {0x2d, 0x28, 0x90, 0x2c, 0x90, 0x00, 0x04, 0x00, - 0xbf, 0x1f, 0x9c, 0x8e, 0x96, 0xb9, 0x30} }, /* 0x0 */ - { {0x2d, 0x28, 0x90, 0x2c, 0x90, 0x00, 0x04, 0x00, - 0x0b, 0x3e, 0xe9, 0x8b, 0xe7, 0x04, 0x00} }, /* 0x1 */ - { {0x3D, 0x31, 0x81, 0x37, 0x1F, 0x00, 0x05, 0x00, - 0x72, 0xF0, 0x58, 0x8C, 0x57, 0x73, 0xA0} }, /* 0x2 */ - { {0x4F, 0x3F, 0x93, 0x45, 0x0D, 0x00, 0x01, 0x00, - 0x24, 0xF5, 0x02, 0x88, 0xFF, 0x25, 0x90} }, /* 0x3 */ - { {0x5F, 0x50, 0x82, 0x55, 0x81, 0x00, 0x05, 0x00, - 0xBF, 0x1F, 0x9C, 0x8E, 0x96, 0xB9, 0x30} }, /* 0x4 */ - { {0x5F, 0x50, 0x82, 0x55, 0x81, 0x00, 0x05, 0x00, - 0x0B, 0x3E, 0xE9, 0x8B, 0xE7, 0x04, 0x00} }, /* 0x5 */ - { {0x63, 0x50, 0x86, 0x56, 0x9B, 0x00, 0x01, 0x00, - 0x06, 0x3E, 0xE8, 0x8B, 0xE7, 0xFF, 0x10} }, /* 0x6 */ - { {0x64, 0x4F, 0x88, 0x55, 0x9D, 0x00, 0x01, 0x00, - 0xF2, 0x1F, 0xE0, 0x83, 0xDF, 0xF3, 0x10} }, /* 0x7 */ - { {0x63, 0x4F, 0x87, 0x5A, 0x81, 0x00, 0x05, 0x00, - 0xFB, 0x1F, 0xE0, 0x83, 0xDF, 0xFC, 0x10} }, /* 0x8 */ - { {0x65, 0x4F, 0x89, 0x58, 0x80, 0x00, 0x05, 0x60, - 0xFB, 0x1F, 0xE0, 0x83, 0xDF, 0xFC, 0x80} }, /* 0x9 */ - { {0x65, 0x4F, 0x89, 0x58, 0x80, 0x00, 0x05, 0x60, - 0x01, 0x3E, 0xE0, 0x83, 0xDF, 0x02, 0x80} }, /* 0xa */ - { {0x67, 0x4F, 0x8B, 0x58, 0x81, 0x00, 0x05, 0x60, - 0x0D, 0x3E, 0xE0, 0x83, 0xDF, 0x0E, 0x90} }, /* 0xb */ - { {0x65, 0x4F, 0x89, 0x57, 0x9F, 0x00, 0x01, 0x00, - 0xFB, 0x1F, 0xE6, 0x8A, 0xDF, 0xFC, 0x10} }, /* 0xc */ - { {0x7B, 0x63, 0x9F, 0x6A, 0x93, 0x00, 0x05, 0x00, /* ; - 0D (800x600,56Hz) */ - 0x6F, 0xF0, 0x58, 0x8A, 0x57, 0x70, 0xA0} }, /* ; - (VCLK 36.0MHz) */ - { {0x7F, 0x63, 0x83, 0x6C, 0x1C, 0x00, 0x06, 0x00, /* ; - 0E (800x600,60Hz) */ - 0x72, 0xF0, 0x58, 0x8C, 0x57, 0x73, 0xA0} }, /* ; - (VCLK 40.0MHz) */ - { {0x7D, 0x63, 0x81, 0x6E, 0x1D, 0x00, 0x06, 0x00, /* ; - 0F (800x600,72Hz) */ - 0x98, 0xF0, 0x7C, 0x82, 0x57, 0x99, 0x80} }, /* ; - (VCLK 50.0MHz) */ - { {0x7F, 0x63, 0x83, 0x69, 0x13, 0x00, 0x06, 0x00, /* ; - 10 (800x600,75Hz) */ - 0x6F, 0xF0, 0x58, 0x8B, 0x57, 0x70, 0xA0} }, /* ; - (VCLK 49.5MHz) */ - { {0x7E, 0x63, 0x82, 0x6B, 0x13, 0x00, 0x06, 0x00, /* ; - 11 (800x600,85Hz) */ - 0x75, 0xF0, 0x58, 0x8B, 0x57, 0x76, 0xA0} }, /* ; - (VCLK 56.25MHz) */ - { {0x81, 0x63, 0x85, 0x6D, 0x18, 0x00, 0x06, 0x60, /* ; - 12 (800x600,100Hz) */ - 0x7A, 0xF0, 0x58, 0x8B, 0x57, 0x7B, 0xA0} }, /* ; - (VCLK 75.8MHz) */ - { {0x83, 0x63, 0x87, 0x6E, 0x19, 0x00, 0x06, 0x60, /* ; - 13 (800x600,120Hz) */ - 0x81, 0xF0, 0x58, 0x8B, 0x57, 0x82, 0xA0} }, /* ; - (VCLK 79.411MHz) */ - { {0x85, 0x63, 0x89, 0x6F, 0x1A, 0x00, 0x06, 0x60, /* ; - 14 (800x600,160Hz) */ - 0x91, 0xF0, 0x58, 0x8B, 0x57, 0x92, 0xA0} }, /* ; - (VCLK 105.822MHz) */ - { {0x99, 0x7F, 0x9D, 0x84, 0x1A, 0x00, 0x02, 0x00, - 0x96, 0x1F, 0x7F, 0x83, 0x7F, 0x97, 0x10} }, /* 0x15 */ - { {0xA3, 0x7F, 0x87, 0x86, 0x97, 0x00, 0x02, 0x00, - 0x24, 0xF5, 0x02, 0x88, 0xFF, 0x25, 0x90} }, /* 0x16 */ - { {0xA1, 0x7F, 0x85, 0x86, 0x97, 0x00, 0x02, 0x00, - 0x24, 0xF5, 0x02, 0x88, 0xFF, 0x25, 0x90} }, /* 0x17 */ - { {0x9F, 0x7F, 0x83, 0x85, 0x91, 0x00, 0x02, 0x00, - 0x1E, 0xF5, 0x00, 0x83, 0xFF, 0x1F, 0x90} }, /* 0x18 */ - { {0xA7, 0x7F, 0x8B, 0x89, 0x95, 0x00, 0x02, 0x00, - 0x26, 0xF5, 0x00, 0x83, 0xFF, 0x27, 0x90} }, /* 0x19 */ - { {0xA9, 0x7F, 0x8D, 0x8C, 0x9A, 0x00, 0x02, 0x62, - 0x2C, 0xF5, 0x00, 0x83, 0xFF, 0x2D, 0x14} }, /* 0x1a */ - { {0xAB, 0x7F, 0x8F, 0x8D, 0x9B, 0x00, 0x02, 0x62, - 0x35, 0xF5, 0x00, 0x83, 0xFF, 0x36, 0x14} }, /* 0x1b */ - { {0xCF, 0x9F, 0x93, 0xB2, 0x01, 0x00, 0x03, 0x00, - 0x14, 0xBA, 0x00, 0x83, 0xFF, 0x15, 0x00} }, /* 0x1c */ - { {0xCE, 0x9F, 0x92, 0xA9, 0x17, 0x00, 0x07, 0x00, - 0x28, 0x5A, 0x00, 0x83, 0xFF, 0x29, 0x89} }, /* 0x1d */ - { {0xCE, 0x9F, 0x92, 0xA5, 0x17, 0x00, 0x07, 0x00, - 0x28, 0x5A, 0x00, 0x83, 0xFF, 0x29, 0x89} }, /* 0x1e */ - { {0xD3, 0x9F, 0x97, 0xAB, 0x1F, 0x00, 0x07, 0x00, - 0x2E, 0x5A, 0x00, 0x83, 0xFF, 0x2F, 0x89} }, /* 0x1f */ - { {0x09, 0xC7, 0x8D, 0xD3, 0x0B, 0x01, 0x04, 0x00, - 0xE0, 0x10, 0xB0, 0x83, 0xAF, 0xE1, 0x2F} }, /* 0x20 */ - { {0x09, 0xC7, 0x8D, 0xD3, 0x0B, 0x01, 0x04, 0x00, - 0xE0, 0x10, 0xB0, 0x83, 0xAF, 0xE1, 0x2F} }, /* 0x21 */ - { {0x09, 0xC7, 0x8D, 0xD3, 0x0B, 0x01, 0x04, 0x00, - 0xE0, 0x10, 0xB0, 0x83, 0xAF, 0xE1, 0x2F} }, /* 0x22 */ - { {0x09, 0xC7, 0x8D, 0xD3, 0x0B, 0x01, 0x04, 0x00, - 0xE0, 0x10, 0xB0, 0x83, 0xAF, 0xE1, 0x2F} }, /* 0x23 */ - { {0x09, 0xC7, 0x8D, 0xD3, 0x0B, 0x01, 0x04, 0x00, - 0xE0, 0x10, 0xB0, 0x83, 0xAF, 0xE1, 0x2F} }, /* 0x24 */ - { {0x09, 0xC7, 0x8D, 0xD3, 0x0B, 0x01, 0x04, 0x00, - 0xE0, 0x10, 0xB0, 0x83, 0xAF, 0xE1, 0x2F} }, /* 0x25 */ - { {0x09, 0xC7, 0x8D, 0xD3, 0x0B, 0x01, 0x04, 0x00, - 0xE0, 0x10, 0xB0, 0x83, 0xAF, 0xE1, 0x2F} }, /* 0x26 */ - { {0x40, 0xEF, 0x84, 0x03, 0x1D, 0x41, 0x01, 0x00, - 0xDA, 0x1F, 0xA0, 0x83, 0x9F, 0xDB, 0x1F} }, /* 0x27 */ - { {0x43, 0xEF, 0x87, 0x06, 0x00, 0x41, 0x05, 0x62, - 0xD4, 0x1F, 0xA0, 0x83, 0x9F, 0xD5, 0x9F} }, /* 0x28 */ - { {0x45, 0xEF, 0x89, 0x07, 0x01, 0x41, 0x05, 0x62, - 0xD9, 0x1F, 0xA0, 0x83, 0x9F, 0xDA, 0x9F} }, /* 0x29 */ - { {0x40, 0xEF, 0x84, 0x03, 0x1D, 0x41, 0x01, 0x00, - 0xDA, 0x1F, 0xA0, 0x83, 0x9F, 0xDB, 0x1F} }, /* 0x2a */ - { {0x40, 0xEF, 0x84, 0x03, 0x1D, 0x41, 0x01, 0x00, - 0xDA, 0x1F, 0xA0, 0x83, 0x9F, 0xDB, 0x1F} }, /* 0x2b */ - { {0x40, 0xEF, 0x84, 0x03, 0x1D, 0x41, 0x01, 0x00, - 0xDA, 0x1F, 0xA0, 0x83, 0x9F, 0xDB, 0x1F} }, /* 0x2c */ - { {0x59, 0xFF, 0x9D, 0x17, 0x13, 0x41, 0x05, 0x44, - 0x33, 0xBA, 0x00, 0x83, 0xFF, 0x34, 0x0F} }, /* 0x2d */ - { {0x5B, 0xFF, 0x9F, 0x18, 0x14, 0x41, 0x05, 0x44, - 0x38, 0xBA, 0x00, 0x83, 0xFF, 0x39, 0x0F} }, /* 0x2e */ - { {0x5B, 0xFF, 0x9F, 0x18, 0x14, 0x41, 0x05, 0x44, - 0x3D, 0xBA, 0x00, 0x83, 0xFF, 0x3E, 0x0F} }, /* 0x2f */ - { {0x5D, 0xFF, 0x81, 0x19, 0x95, 0x41, 0x05, 0x44, - 0x41, 0xBA, 0x00, 0x84, 0xFF, 0x42, 0x0F} }, /* 0x30 */ - { {0x55, 0xFF, 0x99, 0x0D, 0x0C, 0x41, 0x05, 0x00, - 0x3E, 0xBA, 0x00, 0x84, 0xFF, 0x3F, 0x0F} }, /* 0x31 */ - { {0x7F, 0x63, 0x83, 0x6C, 0x1C, 0x00, 0x06, 0x00, - 0x72, 0xBA, 0x27, 0x8B, 0xDF, 0x73, 0x80} }, /* 0x32 */ - { {0x7F, 0x63, 0x83, 0x69, 0x13, 0x00, 0x06, 0x00, - 0x6F, 0xBA, 0x26, 0x89, 0xDF, 0x6F, 0x80} }, /* 0x33 */ - { {0x7F, 0x63, 0x82, 0x6B, 0x13, 0x00, 0x06, 0x00, - 0x75, 0xBA, 0x29, 0x8C, 0xDF, 0x75, 0x80} }, /* 0x34 */ - { {0xA3, 0x7F, 0x87, 0x86, 0x97, 0x00, 0x02, 0x00, - 0x24, 0xF1, 0xAF, 0x85, 0x3F, 0x25, 0xB0} }, /* 0x35 */ - { {0x9F, 0x7F, 0x83, 0x85, 0x91, 0x00, 0x02, 0x00, - 0x1E, 0xF1, 0xAD, 0x81, 0x3F, 0x1F, 0xB0} }, /* 0x36 */ - { {0xA7, 0x7F, 0x88, 0x89, 0x15, 0x00, 0x02, 0x00, - 0x26, 0xF1, 0xB1, 0x85, 0x3F, 0x27, 0xB0} }, /* 0x37 */ - { {0xCE, 0x9F, 0x92, 0xA9, 0x17, 0x00, 0x07, 0x00, - 0x28, 0xC4, 0x7A, 0x8E, 0xCF, 0x29, 0xA1} }, /* 0x38 */ - { {0xCE, 0x9F, 0x92, 0xA5, 0x17, 0x00, 0x07, 0x00, - 0x28, 0xD4, 0x7A, 0x8E, 0xCF, 0x29, 0xA1} }, /* 0x39 */ - { {0xD3, 0x9F, 0x97, 0xAB, 0x1F, 0x00, 0x07, 0x00, - 0x2E, 0xD4, 0x7D, 0x81, 0xCF, 0x2F, 0xA1} }, /* 0x3a */ - { {0xDC, 0x9F, 0x00, 0xAB, 0x19, 0x00, 0x07, 0x00, - 0xE6, 0xEF, 0xC0, 0xC3, 0xBF, 0xE7, 0x90} }, /* 0x3b */ - { {0x6B, 0x59, 0x8F, 0x5E, 0x8C, 0x00, 0x05, 0x00, - 0x0B, 0x3E, 0xE9, 0x8B, 0xE7, 0x04, 0x00} }, /* 0x3c */ - { {0x7B, 0x63, 0x9F, 0x6A, 0x93, 0x00, 0x05, 0x00, - 0x6F, 0xF0, 0x58, 0x8A, 0x57, 0x70, 0xA0} }, /* 0x3d */ - { {0x86, 0x6A, 0x8a, 0x74, 0x06, 0x00, 0x02, 0x00, - 0x8c, 0x15, 0x4f, 0x83, 0xef, 0x8d, 0x30} }, /* 0x3e */ - { {0x81, 0x6A, 0x85, 0x70, 0x00, 0x00, 0x02, 0x00, - 0x0f, 0x3e, 0xeb, 0x8e, 0xdf, 0x10, 0x00} }, /* 0x3f */ - { {0xCE, 0x9F, 0x92, 0xA9, 0x17, 0x00, 0x07, 0x00, - 0x20, 0xF5, 0x03, 0x88, 0xFF, 0x21, 0x90} }, /* 0x40 */ - { {0xE6, 0xAE, 0x8A, 0xBD, 0x90, 0x00, 0x03, 0x00, - 0x3D, 0x10, 0x1A, 0x8D, 0x19, 0x3E, 0x2F} }, /* 0x41 */ - { {0xB9, 0x8F, 0x9D, 0x9B, 0x8A, 0x00, 0x06, 0x00, - 0x7D, 0xFF, 0x60, 0x83, 0x5F, 0x7E, 0x90} }, /* 0x42 */ - { {0xC3, 0x8F, 0x87, 0x9B, 0x0B, 0x00, 0x07, 0x00, - 0x82, 0xFF, 0x60, 0x83, 0x5F, 0x83, 0x90} }, /* 0x43 */ - { {0xAD, 0x7F, 0x91, 0x8E, 0x9C, 0x00, 0x02, 0x82, - 0x49, 0xF5, 0x00, 0x83, 0xFF, 0x4A, 0x90} }, /* 0x44 */ - { {0xCD, 0x9F, 0x91, 0xA7, 0x19, 0x00, 0x07, 0x60, - 0xE6, 0xFF, 0xC0, 0x83, 0xBF, 0xE7, 0x90} }, /* 0x45 */ - { {0xD3, 0x9F, 0x97, 0xAB, 0x1F, 0x00, 0x07, 0x60, - 0xF1, 0xFF, 0xC0, 0x83, 0xBF, 0xF2, 0x90} }, /* 0x46 */ - { {0xD7, 0x9F, 0x9B, 0xAC, 0x1E, 0x00, 0x07, 0x00, - 0x03, 0xDE, 0xC0, 0x84, 0xBF, 0x04, 0x90} } /* 0x47 */ -}; - -/*add for new UNIVGABIOS*/ -static const struct SiS_LCDData XGI_StLCD1024x768Data[] = { - {62, 25, 800, 546, 1344, 806}, - {32, 15, 930, 546, 1344, 806}, - {62, 25, 800, 546, 1344, 806}, /*chiawenfordot9->dot8*/ - {104, 45, 945, 496, 1344, 806}, - {62, 25, 800, 546, 1344, 806}, - {31, 18, 1008, 624, 1344, 806}, - {1, 1, 1344, 806, 1344, 806} -}; - -static const struct SiS_LCDData XGI_ExtLCD1024x768Data[] = { - {42, 25, 1536, 419, 1344, 806}, - {48, 25, 1536, 369, 1344, 806}, - {42, 25, 1536, 419, 1344, 806}, - {48, 25, 1536, 369, 1344, 806}, - {12, 5, 896, 500, 1344, 806}, - {42, 25, 1024, 625, 1344, 806}, - {1, 1, 1344, 806, 1344, 806}, - {12, 5, 896, 500, 1344, 806}, - {42, 25, 1024, 625, 1344, 806}, - {1, 1, 1344, 806, 1344, 806}, - {12, 5, 896, 500, 1344, 806}, - {42, 25, 1024, 625, 1344, 806}, - {1, 1, 1344, 806, 1344, 806} -}; - -static const struct SiS_LCDData XGI_CetLCD1024x768Data[] = { - {1, 1, 1344, 806, 1344, 806}, /* ; 00 (320x200,320x400, - 640x200,640x400) */ - {1, 1, 1344, 806, 1344, 806}, /* 01 (320x350,640x350) */ - {1, 1, 1344, 806, 1344, 806}, /* 02 (360x400,720x400) */ - {1, 1, 1344, 806, 1344, 806}, /* 03 (720x350) */ - {1, 1, 1344, 806, 1344, 806}, /* 04 (640x480x60Hz) */ - {1, 1, 1344, 806, 1344, 806}, /* 05 (800x600x60Hz) */ - {1, 1, 1344, 806, 1344, 806} /* 06 (1024x768x60Hz) */ -}; - -static const struct SiS_LCDData XGI_StLCD1280x1024Data[] = { - {22, 5, 800, 510, 1650, 1088}, - {22, 5, 800, 510, 1650, 1088}, - {176, 45, 900, 510, 1650, 1088}, - {176, 45, 900, 510, 1650, 1088}, - {22, 5, 800, 510, 1650, 1088}, - {13, 5, 1024, 675, 1560, 1152}, - {16, 9, 1266, 804, 1688, 1072}, - {1, 1, 1688, 1066, 1688, 1066} -}; - -static const struct SiS_LCDData XGI_ExtLCD1280x1024Data[] = { - {211, 60, 1024, 501, 1688, 1066}, - {211, 60, 1024, 508, 1688, 1066}, - {211, 60, 1024, 501, 1688, 1066}, - {211, 60, 1024, 508, 1688, 1066}, - {211, 60, 1024, 500, 1688, 1066}, - {211, 75, 1024, 625, 1688, 1066}, - {211, 120, 1280, 798, 1688, 1066}, - {1, 1, 1688, 1066, 1688, 1066} -}; - -static const struct SiS_LCDData XGI_CetLCD1280x1024Data[] = { - {1, 1, 1688, 1066, 1688, 1066}, /* 00 (320x200,320x400, - 640x200,640x400) */ - {1, 1, 1688, 1066, 1688, 1066}, /* 01 (320x350,640x350) */ - {1, 1, 1688, 1066, 1688, 1066}, /* 02 (360x400,720x400) */ - {1, 1, 1688, 1066, 1688, 1066}, /* 03 (720x350) */ - {1, 1, 1688, 1066, 1688, 1066}, /* 04 (640x480x60Hz) */ - {1, 1, 1688, 1066, 1688, 1066}, /* 05 (800x600x60Hz) */ - {1, 1, 1688, 1066, 1688, 1066}, /* 06 (1024x768x60Hz) */ - {1, 1, 1688, 1066, 1688, 1066}, /* 07 (1280x1024x60Hz) */ - {1, 1, 1688, 1066, 1688, 1066} /* 08 (1400x1050x60Hz) */ -}; - -static const struct SiS_LCDData xgifb_lcd_1400x1050[] = { - {211, 100, 2100, 408, 1688, 1066}, /* 00 (320x200,320x400, - 640x200,640x400) */ - {211, 64, 1536, 358, 1688, 1066}, /* 01 (320x350,640x350) */ - {211, 100, 2100, 408, 1688, 1066}, /* 02 (360x400,720x400) */ - {211, 64, 1536, 358, 1688, 1066}, /* 03 (720x350) */ - {211, 48, 840, 488, 1688, 1066}, /* 04 (640x480x60Hz) */ - {211, 72, 1008, 609, 1688, 1066}, /* 05 (800x600x60Hz) */ - {211, 128, 1400, 776, 1688, 1066}, /* 06 (1024x768x60Hz) */ - {1, 1, 1688, 1066, 1688, 1066}, /* 07 (1280x1024x60Hz - w/o Scaling) */ - {1, 1, 1688, 1066, 1688, 1066} /* 08 (1400x1050x60Hz) */ -}; - -static const struct SiS_LCDData XGI_ExtLCD1600x1200Data[] = { - {4, 1, 1620, 420, 2160, 1250}, /* 00 (320x200,320x400, - 640x200,640x400)*/ - {27, 7, 1920, 375, 2160, 1250}, /* 01 (320x350,640x350) */ - {4, 1, 1620, 420, 2160, 1250}, /* 02 (360x400,720x400)*/ - {27, 7, 1920, 375, 2160, 1250}, /* 03 (720x350) */ - {27, 4, 800, 500, 2160, 1250}, /* 04 (640x480x60Hz) */ - {4, 1, 1080, 625, 2160, 1250}, /* 05 (800x600x60Hz) */ - {5, 2, 1350, 800, 2160, 1250}, /* 06 (1024x768x60Hz) */ - {27, 16, 1500, 1064, 2160, 1250}, /* 07 (1280x1024x60Hz) */ - {9, 7, 1920, 1106, 2160, 1250}, /* 08 (1400x1050x60Hz) */ - {1, 1, 2160, 1250, 2160, 1250} /* 09 (1600x1200x60Hz) ;302lv */ -}; - -static const struct SiS_LCDData XGI_StLCD1600x1200Data[] = { - {27, 4, 800, 500, 2160, 1250}, /* 00 (320x200,320x400, - 640x200,640x400) */ - {27, 4, 800, 500, 2160, 1250}, /* 01 (320x350,640x350) */ - {27, 4, 800, 500, 2160, 1250}, /* 02 (360x400,720x400) */ - {27, 4, 800, 500, 2160, 1250}, /* 03 (720x350) */ - {27, 4, 800, 500, 2160, 1250}, /* 04 (320x240,640x480) */ - {4, 1, 1080, 625, 2160, 1250}, /* 05 (400x300,800x600) */ - {5, 2, 1350, 800, 2160, 1250}, /* 06 (512x384,1024x768) */ - {135, 88, 1600, 1100, 2160, 1250}, /* 07 (1280x1024) */ - {1, 1, 1800, 1500, 2160, 1250}, /* 08 (1400x1050) */ - {1, 1, 2160, 1250, 2160, 1250} /* 09 (1600x1200) */ -}; - -#define XGI_CetLCD1400x1050Data XGI_CetLCD1280x1024Data - -static const struct SiS_LCDData XGI_NoScalingData[] = { - {1, 1, 800, 449, 800, 449}, - {1, 1, 800, 449, 800, 449}, - {1, 1, 900, 449, 900, 449}, - {1, 1, 900, 449, 900, 449}, - {1, 1, 800, 525, 800, 525}, - {1, 1, 1056, 628, 1056, 628}, - {1, 1, 1344, 806, 1344, 806}, - {1, 1, 1688, 1066, 1688, 1066} -}; - -static const struct SiS_LCDData XGI_ExtLCD1024x768x75Data[] = { - {42, 25, 1536, 419, 1344, 806}, /* ; 00 (320x200,320x400, - 640x200,640x400) */ - {48, 25, 1536, 369, 1344, 806}, /* ; 01 (320x350,640x350) */ - {42, 25, 1536, 419, 1344, 806}, /* ; 02 (360x400,720x400) */ - {48, 25, 1536, 369, 1344, 806}, /* ; 03 (720x350) */ - {8, 5, 1312, 500, 1312, 800}, /* ; 04 (640x480x75Hz) */ - {41, 25, 1024, 625, 1312, 800}, /* ; 05 (800x600x75Hz) */ - {1, 1, 1312, 800, 1312, 800} /* ; 06 (1024x768x75Hz) */ -}; - -static const struct SiS_LCDData XGI_CetLCD1024x768x75Data[] = { - {1, 1, 1312, 800, 1312, 800}, /* ; 00 (320x200,320x400, - 640x200,640x400) */ - {1, 1, 1312, 800, 1312, 800}, /* ; 01 (320x350,640x350) */ - {1, 1, 1312, 800, 1312, 800}, /* ; 02 (360x400,720x400) */ - {1, 1, 1312, 800, 1312, 800}, /* ; 03 (720x350) */ - {1, 1, 1312, 800, 1312, 800}, /* ; 04 (640x480x75Hz) */ - {1, 1, 1312, 800, 1312, 800}, /* ; 05 (800x600x75Hz) */ - {1, 1, 1312, 800, 1312, 800} /* ; 06 (1024x768x75Hz) */ -}; - -static const struct SiS_LCDData xgifb_lcd_1280x1024x75[] = { - {211, 60, 1024, 501, 1688, 1066}, /* ; 00 (320x200,320x400, - 640x200,640x400) */ - {211, 60, 1024, 508, 1688, 1066}, /* ; 01 (320x350,640x350) */ - {211, 60, 1024, 501, 1688, 1066}, /* ; 02 (360x400,720x400) */ - {211, 60, 1024, 508, 1688, 1066}, /* ; 03 (720x350) */ - {211, 45, 768, 498, 1688, 1066}, /* ; 04 (640x480x75Hz) */ - {211, 75, 1024, 625, 1688, 1066}, /* ; 05 (800x600x75Hz) */ - {211, 120, 1280, 798, 1688, 1066}, /* ; 06 (1024x768x75Hz) */ - {1, 1, 1688, 1066, 1688, 1066} /* ; 07 (1280x1024x75Hz) */ -}; - -#define XGI_CetLCD1280x1024x75Data XGI_CetLCD1280x1024Data - -static const struct SiS_LCDData XGI_NoScalingDatax75[] = { - {1, 1, 800, 449, 800, 449}, /* ; 00 (320x200, 320x400, - 640x200, 640x400) */ - {1, 1, 800, 449, 800, 449}, /* ; 01 (320x350, 640x350) */ - {1, 1, 900, 449, 900, 449}, /* ; 02 (360x400, 720x400) */ - {1, 1, 900, 449, 900, 449}, /* ; 03 (720x350) */ - {1, 1, 840, 500, 840, 500}, /* ; 04 (640x480x75Hz) */ - {1, 1, 1056, 625, 1056, 625}, /* ; 05 (800x600x75Hz) */ - {1, 1, 1312, 800, 1312, 800}, /* ; 06 (1024x768x75Hz) */ - {1, 1, 1688, 1066, 1688, 1066}, /* ; 07 (1280x1024x75Hz) */ - {1, 1, 1688, 1066, 1688, 1066}, /* ; 08 (1400x1050x75Hz)*/ - {1, 1, 2160, 1250, 2160, 1250}, /* ; 09 (1600x1200x75Hz) */ - {1, 1, 1688, 806, 1688, 806} /* ; 0A (1280x768x75Hz) */ -}; - -static const struct XGI_LCDDesStruct XGI_ExtLCDDes1024x768Data[] = { - {9, 1057, 0, 771}, /* ; 00 (320x200,320x400,640x200,640x400) */ - {9, 1057, 0, 771}, /* ; 01 (320x350,640x350) */ - {9, 1057, 0, 771}, /* ; 02 (360x400,720x400) */ - {9, 1057, 0, 771}, /* ; 03 (720x350) */ - {9, 1057, 0, 771}, /* ; 04 (640x480x60Hz) */ - {9, 1057, 0, 771}, /* ; 05 (800x600x60Hz) */ - {9, 1057, 805, 770} /* ; 06 (1024x768x60Hz) */ -}; - -static const struct XGI_LCDDesStruct XGI_StLCDDes1024x768Data[] = { - {9, 1057, 737, 703}, /* ; 00 (320x200,320x400,640x200,640x400) */ - {9, 1057, 686, 651}, /* ; 01 (320x350,640x350) */ - {9, 1057, 737, 703}, /* ; 02 (360x400,720x400) */ - {9, 1057, 686, 651}, /* ; 03 (720x350) */ - {9, 1057, 776, 741}, /* ; 04 (640x480x60Hz) */ - {9, 1057, 0, 771}, /* ; 05 (800x600x60Hz) */ - {9, 1057, 805, 770} /* ; 06 (1024x768x60Hz) */ -}; - -static const struct XGI_LCDDesStruct XGI_CetLCDDes1024x768Data[] = { - {1152, 856, 622, 587}, /* ; 00 (320x200,320x400,640x200,640x400) */ - {1152, 856, 597, 562}, /* ; 01 (320x350,640x350) */ - {1152, 856, 622, 587}, /* ; 02 (360x400,720x400) */ - {1152, 856, 597, 562}, /* ; 03 (720x350) */ - {1152, 856, 662, 627}, /* ; 04 (640x480x60Hz) */ - {1232, 936, 722, 687}, /* ; 05 (800x600x60Hz) */ - {0, 1048, 805, 770} /* ; 06 (1024x768x60Hz) */ -}; - -static const struct XGI_LCDDesStruct XGI_ExtLCDDLDes1280x1024Data[] = { - {18, 1346, 981, 940}, /* 00 (320x200,320x400,640x200,640x400) */ - {18, 1346, 926, 865}, /* 01 (320x350,640x350) */ - {18, 1346, 981, 940}, /* 02 (360x400,720x400) */ - {18, 1346, 926, 865}, /* 03 (720x350) */ - {18, 1346, 0, 1025}, /* 04 (640x480x60Hz) */ - {18, 1346, 0, 1025}, /* 05 (800x600x60Hz) */ - {18, 1346, 1065, 1024}, /* 06 (1024x768x60Hz) */ - {18, 1346, 1065, 1024} /* 07 (1280x1024x60Hz) */ -}; - -static const struct XGI_LCDDesStruct XGI_StLCDDLDes1280x1024Data[] = { - {18, 1346, 970, 907}, /* 00 (320x200,320x400,640x200,640x400) */ - {18, 1346, 917, 854}, /* 01 (320x350,640x350) */ - {18, 1346, 970, 907}, /* 02 (360x400,720x400) */ - {18, 1346, 917, 854}, /* 03 (720x350) */ - {18, 1346, 0, 1025}, /* 04 (640x480x60Hz) */ - {18, 1346, 0, 1025}, /* 05 (800x600x60Hz) */ - {18, 1346, 1065, 1024}, /* 06 (1024x768x60Hz) */ - {18, 1346, 1065, 1024} /* 07 (1280x1024x60Hz) */ -}; - -static const struct XGI_LCDDesStruct XGI_CetLCDDLDes1280x1024Data[] = { - {1368, 1008, 752, 711}, /* 00 (320x200,320x400,640x200,640x400) */ - {1368, 1008, 729, 688}, /* 01 (320x350,640x350) */ - {1368, 1008, 752, 711}, /* 02 (360x400,720x400) */ - {1368, 1008, 729, 688}, /* 03 (720x350) */ - {1368, 1008, 794, 753}, /* 04 (640x480x60Hz) */ - {1448, 1068, 854, 813}, /* 05 (800x600x60Hz) */ - {1560, 1200, 938, 897}, /* 06 (1024x768x60Hz) */ - {18, 1346, 1065, 1024} /* 07 (1280x1024x60Hz) */ -}; - -static const struct XGI_LCDDesStruct XGI_ExtLCDDes1280x1024Data[] = { - {9, 1337, 981, 940}, /* ; 00 (320x200,320x400,640x200,640x400) */ - {9, 1337, 926, 884}, /* ; 01 (320x350,640x350) alan, 2003/09/30 */ - {9, 1337, 981, 940}, /* ; 02 (360x400,720x400) */ - {9, 1337, 926, 884}, /* ; 03 (720x350) alan, 2003/09/30 */ - {9, 1337, 0, 1025}, /* ; 04 (640x480x60Hz) */ - {9, 1337, 0, 1025}, /* ; 05 (800x600x60Hz) */ - {9, 1337, 1065, 1024}, /* ; 06 (1024x768x60Hz) */ - {9, 1337, 1065, 1024} /* ; 07 (1280x1024x60Hz) */ -}; - -static const struct XGI_LCDDesStruct XGI_StLCDDes1280x1024Data[] = { - {9, 1337, 970, 907}, /* ; 00 (320x200,320x400,640x200,640x400) */ - {9, 1337, 917, 854}, /* ; 01 (320x350,640x350) */ - {9, 1337, 970, 907}, /* ; 02 (360x400,720x400) */ - {9, 1337, 917, 854}, /* ; 03 (720x350) */ - {9, 1337, 0, 1025}, /* ; 04 (640x480x60Hz) */ - {9, 1337, 0, 1025}, /* ; 05 (800x600x60Hz) */ - {9, 1337, 1065, 1024}, /* ; 06 (1024x768x60Hz) */ - {9, 1337, 1065, 1024} /* ; 07 (1280x1024x60Hz) */ -}; - -static const struct XGI_LCDDesStruct XGI_CetLCDDes1280x1024Data[] = { - {1368, 1008, 752, 711}, /* 00 (320x200,320x400,640x200,640x400) */ - {1368, 1008, 729, 688}, /* 01 (320x350,640x350) */ - {1368, 1008, 752, 711}, /* 02 (360x400,720x400) */ - {1368, 1008, 729, 688}, /* 03 (720x350) */ - {1368, 1008, 794, 753}, /* 04 (640x480x60Hz) */ - {1448, 1068, 854, 813}, /* 05 (800x600x60Hz) */ - {1560, 1200, 938, 897}, /* 06 (1024x768x60Hz) */ - {9, 1337, 1065, 1024} /* 07 (1280x1024x60Hz) */ -}; - -static const struct XGI_LCDDesStruct xgifb_lcddldes_1400x1050[] = { - {18, 1464, 0, 1051}, /* 00 (320x200,320x400,640x200,640x400) */ - {18, 1464, 0, 1051}, /* 01 (320x350,640x350) */ - {18, 1464, 0, 1051}, /* 02 (360x400,720x400) */ - {18, 1464, 0, 1051}, /* 03 (720x350) */ - {18, 1464, 0, 1051}, /* 04 (640x480x60Hz) */ - {18, 1464, 0, 1051}, /* 05 (800x600x60Hz) */ - {18, 1464, 0, 1051}, /* 06 (1024x768x60Hz) */ - {1646, 1406, 1053, 1038}, /* 07 (1280x1024x60Hz) */ - {18, 1464, 0, 1051} /* 08 (1400x1050x60Hz) */ -}; - -static const struct XGI_LCDDesStruct xgifb_lcddes_1400x1050[] = { - {9, 1455, 0, 1051}, /* 00 (320x200,320x400,640x200,640x400) */ - {9, 1455, 0, 1051}, /* 01 (320x350,640x350) */ - {9, 1455, 0, 1051}, /* 02 (360x400,720x400) */ - {9, 1455, 0, 1051}, /* 03 (720x350) */ - {9, 1455, 0, 1051}, /* 04 (640x480x60Hz) */ - {9, 1455, 0, 1051}, /* 05 (800x600x60Hz) */ - {9, 1455, 0, 1051}, /* 06 (1024x768x60Hz) */ - {1637, 1397, 1053, 1038}, /* 07 (1280x1024x60Hz) */ - {9, 1455, 0, 1051} /* 08 (1400x1050x60Hz) */ -}; - -static const struct XGI_LCDDesStruct XGI_CetLCDDes1400x1050Data[] = { - {1308, 1068, 781, 766}, /* 00 (320x200,320x400,640x200,640x400) */ - {1308, 1068, 781, 766}, /* 01 (320x350,640x350) */ - {1308, 1068, 781, 766}, /* 02 (360x400,720x400) */ - {1308, 1068, 781, 766}, /* 03 (720x350) */ - {1308, 1068, 781, 766}, /* 04 (640x480x60Hz) */ - {1388, 1148, 841, 826}, /* 05 (800x600x60Hz) */ - {1490, 1250, 925, 910}, /* 06 (1024x768x60Hz) */ - {1646, 1406, 1053, 1038}, /* 07 (1280x1024x60Hz) */ - {18, 1464, 0, 1051} /* 08 (1400x1050x60Hz) */ -}; - -static const struct XGI_LCDDesStruct XGI_CetLCDDes1400x1050Data2[] = { - {0, 1448, 0, 1051}, /* 00 (320x200,320x400,640x200,640x400) */ - {0, 1448, 0, 1051}, /* 01 (320x350,640x350) */ - {0, 1448, 0, 1051}, /* 02 (360x400,720x400) */ - {0, 1448, 0, 1051}, /* 03 (720x350) */ - {0, 1448, 0, 1051} /* 04 (640x480x60Hz) */ -}; - -static const struct XGI_LCDDesStruct XGI_ExtLCDDLDes1600x1200Data[] = { - {18, 1682, 0, 1201}, /* 00 (320x200,320x400,640x200,640x400) */ - {18, 1682, 0, 1201}, /* 01 (320x350,640x350) */ - {18, 1682, 0, 1201}, /* 02 (360x400,720x400) */ - {18, 1682, 0, 1201}, /* 03 (720x350) */ - {18, 1682, 0, 1201}, /* 04 (640x480x60Hz) */ - {18, 1682, 0, 1201}, /* 05 (800x600x60Hz) */ - {18, 1682, 0, 1201}, /* 06 (1024x768x60Hz) */ - {18, 1682, 0, 1201}, /* 07 (1280x1024x60Hz) */ - {18, 1682, 0, 1201}, /* 08 (1400x1050x60Hz) */ - {18, 1682, 0, 1201} /* 09 (1600x1200x60Hz) */ -}; - -static const struct XGI_LCDDesStruct XGI_StLCDDLDes1600x1200Data[] = { - {18, 1682, 1150, 1101}, /* 00 (320x200,320x400,640x200,640x400) */ - {18, 1682, 1083, 1034}, /* 01 (320x350,640x350) */ - {18, 1682, 1150, 1101}, /* 02 (360x400,720x400) */ - {18, 1682, 1083, 1034}, /* 03 (720x350) */ - {18, 1682, 0, 1201}, /* 04 (640x480x60Hz) */ - {18, 1682, 0, 1201}, /* 05 (800x600x60Hz) */ - {18, 1682, 0, 1201}, /* 06 (1024x768x60Hz) */ - {18, 1682, 1232, 1183}, /* 07 (1280x1024x60Hz) */ - {18, 1682, 0, 1201}, /* 08 (1400x1050x60Hz) */ - {18, 1682, 0, 1201} /* 09 (1600x1200x60Hz) */ -}; - -static const struct XGI_LCDDesStruct XGI_ExtLCDDes1600x1200Data[] = { - {9, 1673, 0, 1201}, /* 00 (320x200,320x400,640x200,640x400) */ - {9, 1673, 0, 1201}, /* 01 (320x350,640x350) */ - {9, 1673, 0, 1201}, /* 02 (360x400,720x400) */ - {9, 1673, 0, 1201}, /* 03 (720x350) */ - {9, 1673, 0, 1201}, /* 04 (640x480x60Hz) */ - {9, 1673, 0, 1201}, /* 05 (800x600x60Hz) */ - {9, 1673, 0, 1201}, /* 06 (1024x768x60Hz) */ - {9, 1673, 0, 1201}, /* 07 (1280x1024x60Hz) */ - {9, 1673, 0, 1201}, /* 08 (1400x1050x60Hz) */ - {9, 1673, 0, 1201} /* 09 (1600x1200x60Hz) */ -}; - -static const struct XGI_LCDDesStruct XGI_StLCDDes1600x1200Data[] = { - {9, 1673, 1150, 1101}, /* 00 (320x200,320x400,640x200,640x400) */ - {9, 1673, 1083, 1034}, /* 01 (320x350,640x350) */ - {9, 1673, 1150, 1101}, /* 02 (360x400,720x400) */ - {9, 1673, 1083, 1034}, /* 03 (720x350) */ - {9, 1673, 0, 1201}, /* 04 (640x480x60Hz) */ - {9, 1673, 0, 1201}, /* 05 (800x600x60Hz) */ - {9, 1673, 0, 1201}, /* 06 (1024x768x60Hz) */ - {9, 1673, 1232, 1183}, /* 07 (1280x1024x60Hz) */ - {9, 1673, 0, 1201}, /* 08 (1400x1050x60Hz) */ - {9, 1673, 0, 1201} /* 09 (1600x1200x60Hz) */ -}; - -static const struct XGI330_LCDDataDesStruct2 XGI_NoScalingDesData[] = { - {9, 657, 448, 405, 96, 2}, /* 00 (320x200,320x400, - 640x200,640x400) */ - {9, 657, 448, 355, 96, 2}, /* 01 (320x350,640x350) */ - {9, 657, 448, 405, 96, 2}, /* 02 (360x400,720x400) */ - {9, 657, 448, 355, 96, 2}, /* 03 (720x350) */ - {9, 657, 1, 483, 96, 2}, /* 04 (640x480x60Hz) */ - {9, 849, 627, 600, 128, 4}, /* 05 (800x600x60Hz) */ - {9, 1057, 805, 770, 0136, 6}, /* 06 (1024x768x60Hz) */ - {9, 1337, 0, 1025, 112, 3}, /* 07 (1280x1024x60Hz) */ - {9, 1457, 0, 1051, 112, 3}, /* 08 (1400x1050x60Hz)*/ - {9, 1673, 0, 1201, 192, 3}, /* 09 (1600x1200x60Hz) */ - {9, 1337, 0, 771, 112, 6} /* 0A (1280x768x60Hz) */ -}; - -/* ;;1024x768x75Hz */ -static const struct XGI_LCDDesStruct xgifb_lcddes_1024x768x75[] = { - {9, 1049, 0, 769}, /* ; 00 (320x200,320x400,640x200,640x400) */ - {9, 1049, 0, 769}, /* ; 01 (320x350,640x350) */ - {9, 1049, 0, 769}, /* ; 02 (360x400,720x400) */ - {9, 1049, 0, 769}, /* ; 03 (720x350) */ - {9, 1049, 0, 769}, /* ; 04 (640x480x75Hz) */ - {9, 1049, 0, 769}, /* ; 05 (800x600x75Hz) */ - {9, 1049, 0, 769} /* ; 06 (1024x768x75Hz) */ -}; - -/* ;;1024x768x75Hz */ -static const struct XGI_LCDDesStruct XGI_CetLCDDes1024x768x75Data[] = { - {1152, 856, 622, 587}, /* ; 00 (320x200,320x400,640x200,640x400) */ - {1152, 856, 597, 562}, /* ; 01 (320x350,640x350) */ - {1192, 896, 622, 587}, /* ; 02 (360x400,720x400) */ - {1192, 896, 597, 562}, /* ; 03 (720x350) */ - {1129, 857, 656, 625}, /* ; 04 (640x480x75Hz) */ - {1209, 937, 716, 685}, /* ; 05 (800x600x75Hz) */ - {9, 1049, 0, 769} /* ; 06 (1024x768x75Hz) */ -}; - -/* ;;1280x1024x75Hz */ -static const struct XGI_LCDDesStruct xgifb_lcddldes_1280x1024x75[] = { - {18, 1314, 0, 1025}, /* ; 00 (320x200,320x400,640x200,640x400) */ - {18, 1314, 0, 1025}, /* ; 01 (320x350,640x350) */ - {18, 1314, 0, 1025}, /* ; 02 (360x400,720x400) */ - {18, 1314, 0, 1025}, /* ; 03 (720x350) */ - {18, 1314, 0, 1025}, /* ; 04 (640x480x60Hz) */ - {18, 1314, 0, 1025}, /* ; 05 (800x600x60Hz) */ - {18, 1314, 0, 1025}, /* ; 06 (1024x768x60Hz) */ - {18, 1314, 0, 1025} /* ; 07 (1280x1024x60Hz) */ -}; - -/* 1280x1024x75Hz */ -static const struct XGI_LCDDesStruct XGI_CetLCDDLDes1280x1024x75Data[] = { - {1368, 1008, 752, 711}, /* ; 00 (320x200,320x400,640x200,640x400) */ - {1368, 1008, 729, 688}, /* ; 01 (320x350,640x350) */ - {1408, 1048, 752, 711}, /* ; 02 (360x400,720x400) */ - {1408, 1048, 729, 688}, /* ; 03 (720x350) */ - {1377, 985, 794, 753}, /* ; 04 (640x480x75Hz) */ - {1457, 1065, 854, 813}, /* ; 05 (800x600x75Hz) */ - {1569, 1177, 938, 897}, /* ; 06 (1024x768x75Hz) */ - {18, 1314, 0, 1025} /* ; 07 (1280x1024x75Hz) */ -}; - -/* ;;1280x1024x75Hz */ -static const struct XGI_LCDDesStruct xgifb_lcddes_1280x1024x75[] = { - {9, 1305, 0, 1025}, /* ; 00 (320x200,320x400,640x200,640x400) */ - {9, 1305, 0, 1025}, /* ; 01 (320x350,640x350) */ - {9, 1305, 0, 1025}, /* ; 02 (360x400,720x400) */ - {9, 1305, 0, 1025}, /* ; 03 (720x350) */ - {9, 1305, 0, 1025}, /* ; 04 (640x480x60Hz) */ - {9, 1305, 0, 1025}, /* ; 05 (800x600x60Hz) */ - {9, 1305, 0, 1025}, /* ; 06 (1024x768x60Hz) */ - {9, 1305, 0, 1025} /* ; 07 (1280x1024x60Hz) */ -}; - -/* 1280x1024x75Hz */ -static const struct XGI_LCDDesStruct XGI_CetLCDDes1280x1024x75Data[] = { - {1368, 1008, 752, 711}, /* ; 00 (320x200,320x400,640x200,640x400) */ - {1368, 1008, 729, 688}, /* ; 01 (320x350,640x350) */ - {1408, 1048, 752, 711}, /* ; 02 (360x400,720x400) */ - {1408, 1048, 729, 688}, /* ; 03 (720x350) */ - {1377, 985, 794, 753}, /* ; 04 (640x480x75Hz) */ - {1457, 1065, 854, 813}, /* ; 05 (800x600x75Hz) */ - {1569, 1177, 938, 897}, /* ; 06 (1024x768x75Hz) */ - {9, 1305, 0, 1025} /* ; 07 (1280x1024x75Hz) */ -}; - -/* Scaling LCD 75Hz */ -static const struct XGI330_LCDDataDesStruct2 XGI_NoScalingDesDatax75[] = { - {9, 657, 448, 405, 96, 2}, /* ; 00 (320x200,320x400, - 640x200,640x400) */ - {9, 657, 448, 355, 96, 2}, /* ; 01 (320x350,640x350) */ - {9, 738, 448, 405, 108, 2}, /* ; 02 (360x400,720x400) */ - {9, 738, 448, 355, 108, 2}, /* ; 03 (720x350) */ - {9, 665, 0, 481, 64, 3}, /* ; 04 (640x480x75Hz) */ - {9, 825, 0, 601, 80, 3}, /* ; 05 (800x600x75Hz) */ - {9, 1049, 0, 769, 96, 3}, /* ; 06 (1024x768x75Hz) */ - {9, 1305, 0, 1025, 144, 3}, /* ; 07 (1280x1024x75Hz) */ - {9, 1457, 0, 1051, 112, 3}, /* ; 08 (1400x1050x60Hz)*/ - {9, 1673, 0, 1201, 192, 3}, /* ; 09 (1600x1200x75Hz) */ - {9, 1337, 0, 771, 112, 6} /* ; 0A (1280x768x60Hz) */ -}; - -static const struct SiS_TVData XGI_StPALData[] = { - {1, 1, 864, 525, 1270, 400, 100, 0, 760}, - {1, 1, 864, 525, 1270, 350, 100, 0, 760}, - {1, 1, 864, 525, 1270, 400, 0, 0, 720}, - {1, 1, 864, 525, 1270, 350, 0, 0, 720}, - {1, 1, 864, 525, 1270, 480, 50, 0, 760}, - {1, 1, 864, 525, 1270, 600, 50, 0, 0} -}; - -static const struct SiS_TVData XGI_ExtPALData[] = { - {2, 1, 1080, 463, 1270, 500, 50, 0, 50}, - {15, 7, 1152, 413, 1270, 500, 50, 0, 50}, - {2, 1, 1080, 463, 1270, 500, 50, 0, 50}, - {15, 7, 1152, 413, 1270, 500, 50, 0, 50}, - {2, 1, 900, 543, 1270, 500, 0, 0, 50}, - {4, 3, 1080, 663, 1270, 500, 438, 0, 438}, - {1, 1, 1125, 831, 1270, 500, 686, 0, 686}, /*301b*/ - {3, 2, 1080, 619, 1270, 540, 438, 0, 438} -}; - -static const struct SiS_TVData XGI_StNTSCData[] = { - {1, 1, 858, 525, 1270, 400, 50, 0, 760}, - {1, 1, 858, 525, 1270, 350, 50, 0, 640}, - {1, 1, 858, 525, 1270, 400, 0, 0, 720}, - {1, 1, 858, 525, 1270, 350, 0, 0, 720}, - {1, 1, 858, 525, 1270, 480, 0, 0, 760} -}; - -static const struct SiS_TVData XGI_ExtNTSCData[] = { - {9, 5, 1001, 453, 1270, 420, 171, 0, 171}, - {12, 5, 858, 403, 1270, 420, 171, 0, 171}, - {9, 5, 1001, 453, 1270, 420, 171, 0, 171}, - {12, 5, 858, 403, 1270, 420, 171, 0, 171}, - {143, 80, 836, 523, 1270, 420, 224, 0, 0}, - {143, 120, 1008, 643, 1270, 420, 0, 1, 0}, - {1, 1, 1120, 821, 1516, 420, 0, 1, 0}, /*301b*/ - {2, 1, 858, 503, 1584, 480, 0, 1, 0}, - {3, 2, 1001, 533, 1270, 420, 0, 0, 0} -}; - -static const struct SiS_TVData XGI_St1HiTVData[] = { - {1, 1, 892, 563, 690, 800, 0, 0, 0}, /* 00 (320x200,320x400, - 640x200,640x400) */ - {1, 1, 892, 563, 690, 700, 0, 0, 0}, /* 01 (320x350,640x350) */ - {1, 1, 1000, 563, 785, 800, 0, 0, 0}, /* 02 (360x400,720x400) */ - {1, 1, 1000, 563, 785, 700, 0, 0, 0}, /* 03 (720x350) */ - {1, 1, 892, 563, 690, 960, 0, 0, 0}, /* 04 (320x240,640x480) */ - {8, 5, 1050, 683, 1648, 960, 0x150, 1, 0} /* 05 (400x300,800x600) */ -}; - -static const struct SiS_TVData XGI_St2HiTVData[] = { - {3, 1, 840, 483, 1648, 960, 0x032, 0, 0}, /* 00 (320x200,320x400, - 640x200,640x400) */ - {1, 1, 892, 563, 690, 700, 0, 0, 0}, /* 01 (320x350,640x350) */ - {3, 1, 840, 483, 1648, 960, 0x032, 0, 0}, /* 02 (360x400,720x400) */ - {1, 1, 1000, 563, 785, 700, 0, 0, 0}, /* 03 (720x350) */ - {5, 2, 840, 563, 1648, 960, 0x08D, 1, 0}, /* 04 (320x240,640x480) */ - {8, 5, 1050, 683, 1648, 960, 0x17C, 1, 0} /* 05 (400x300,800x600) */ -}; - -static const struct SiS_TVData XGI_ExtHiTVData[] = { - {6, 1, 840, 563, 1632, 960, 0, 0, 0}, /* 00 (320x200,320x400, - 640x200,640x400) */ - {3, 1, 960, 563, 1632, 960, 0, 0, 0}, /* 01 (320x350,640x350) */ - {3, 1, 840, 483, 1632, 960, 0, 0, 0}, /* 02 (360x400,720x400) */ - {3, 1, 960, 563, 1632, 960, 0, 0, 0}, /* 03 (720x350) */ - {5, 1, 840, 563, 1648, 960, 0x166, 1, 0}, /* 04 (320x240,640x480) */ - {16, 5, 1050, 683, 1648, 960, 0x143, 1, 0}, /* 05 (400x300,800x600) */ - {25, 12, 1260, 851, 1648, 960, 0x032, 0, 0}, /* 06 (512x384,1024x768)*/ - {5, 4, 1575, 1124, 1648, 960, 0x128, 0, 0}, /* 07 (1280x1024) */ - {4, 1, 1050, 563, 1548, 960, 0x143, 1, 0}, /* 08 (800x480) */ - {5, 2, 1400, 659, 1648, 960, 0x032, 0, 0}, /* 09 (1024x576) */ - {8, 5, 1750, 803, 1648, 960, 0x128, 0, 0} /* 0A (1280x720) */ -}; - -static const struct SiS_TVData XGI_ExtYPbPr525iData[] = { - { 9, 5, 1001, 453, 1270, 420, 171, 0, 171}, - { 12, 5, 858, 403, 1270, 420, 171, 0, 171}, - { 9, 5, 1001, 453, 1270, 420, 171, 0, 171}, - { 12, 5, 858, 403, 1270, 420, 171, 0, 171}, - {143, 80, 836, 523, 1250, 420, 224, 0, 0}, - {143, 120, 1008, 643, 1250, 420, 0, 1, 0}, - { 1, 1, 1120, 821, 1516, 420, 0, 1, 0}, /*301b*/ - { 2, 1, 858, 503, 1584, 480, 0, 1, 0}, - { 3, 2, 1001, 533, 1250, 420, 0, 0, 0} -}; - -static const struct SiS_TVData XGI_StYPbPr525iData[] = { - {1, 1, 858, 525, 1270, 400, 50, 0, 760}, - {1, 1, 858, 525, 1270, 350, 50, 0, 640}, - {1, 1, 858, 525, 1270, 400, 0, 0, 720}, - {1, 1, 858, 525, 1270, 350, 0, 0, 720}, - {1, 1, 858, 525, 1270, 480, 0, 0, 760}, -}; - -static const struct SiS_TVData XGI_ExtYPbPr525pData[] = { - { 9, 5, 1001, 453, 1270, 420, 171, 0, 171}, - { 12, 5, 858, 403, 1270, 420, 171, 0, 171}, - { 9, 5, 1001, 453, 1270, 420, 171, 0, 171}, - { 12, 5, 858, 403, 1270, 420, 171, 0, 171}, - {143, 80, 836, 523, 1270, 420, 224, 0, 0}, - {143, 120, 1008, 643, 1270, 420, 0, 1, 0}, - { 1, 1, 1120, 821, 1516, 420, 0, 1, 0}, /*301b*/ - { 2, 1, 858, 503, 1584, 480, 0, 1, 0}, - { 3, 2, 1001, 533, 1270, 420, 0, 0, 0} -}; - -static const struct SiS_TVData XGI_StYPbPr525pData[] = { - {1, 1, 1716, 525, 1270, 400, 50, 0, 760}, - {1, 1, 1716, 525, 1270, 350, 50, 0, 640}, - {1, 1, 1716, 525, 1270, 400, 0, 0, 720}, - {1, 1, 1716, 525, 1270, 350, 0, 0, 720}, - {1, 1, 1716, 525, 1270, 480, 0, 0, 760}, -}; - -static const struct SiS_TVData XGI_ExtYPbPr750pData[] = { - { 3, 1, 935, 470, 1130, 680, 50, 0, 0}, /* 00 (320x200,320x400, - 640x200,640x400) */ - {24, 7, 935, 420, 1130, 680, 50, 0, 0}, /* 01 (320x350,640x350) */ - { 3, 1, 935, 470, 1130, 680, 50, 0, 0}, /* 02 (360x400,720x400) */ - {24, 7, 935, 420, 1130, 680, 50, 0, 0}, /* 03 (720x350) */ - { 2, 1, 1100, 590, 1130, 640, 50, 0, 0}, /* 04 (320x240,640x480) */ - { 3, 2, 1210, 690, 1130, 660, 50, 0, 0}, /* 05 (400x300,800x600) */ - { 1, 1, 1375, 878, 1130, 640, 638, 0, 0}, /* 06 (1024x768) */ - { 2, 1, 858, 503, 1130, 480, 0, 1, 0}, /* 07 (720x480) */ - { 5, 4, 1815, 570, 1130, 660, 50, 0, 0}, - { 5, 3, 1100, 686, 1130, 640, 50, 1, 0}, - {10, 9, 1320, 830, 1130, 640, 50, 0, 0} -}; - -static const struct SiS_TVData XGI_StYPbPr750pData[] = { - {1, 1, 1650, 750, 1280, 400, 50, 0, 760}, - {1, 1, 1650, 750, 1280, 350, 50, 0, 640}, - {1, 1, 1650, 750, 1280, 400, 0, 0, 720}, - {1, 1, 1650, 750, 1280, 350, 0, 0, 720}, - {1, 1, 1650, 750, 1280, 480, 0, 0, 760}, -}; - -static const unsigned char XGI330_NTSCTiming[] = { - 0x17, 0x1d, 0x03, 0x09, 0x05, 0x06, 0x0c, 0x0c, - 0x94, 0x49, 0x01, 0x0a, 0x06, 0x0d, 0x04, 0x0a, - 0x06, 0x14, 0x0d, 0x04, 0x0a, 0x00, 0x85, 0x1b, - 0x0c, 0x50, 0x00, 0x97, 0x00, 0xda, 0x4a, 0x17, - 0x7d, 0x05, 0x4b, 0x00, 0x00, 0xe2, 0x00, 0x02, - 0x03, 0x0a, 0x65, 0x9d, 0x08, 0x92, 0x8f, 0x40, - 0x60, 0x80, 0x14, 0x90, 0x8c, 0x60, 0x14, 0x50, - 0x00, 0x40, 0x44, 0x00, 0xdb, 0x02, 0x3b, 0x00 -}; - -static const unsigned char XGI330_PALTiming[] = { - 0x21, 0x5A, 0x35, 0x6e, 0x04, 0x38, 0x3d, 0x70, - 0x94, 0x49, 0x01, 0x12, 0x06, 0x3e, 0x35, 0x6d, - 0x06, 0x14, 0x3e, 0x35, 0x6d, 0x00, 0x45, 0x2b, - 0x70, 0x50, 0x00, 0x9b, 0x00, 0xd9, 0x5d, 0x17, - 0x7d, 0x05, 0x45, 0x00, 0x00, 0xe8, 0x00, 0x02, - 0x0d, 0x00, 0x68, 0xb0, 0x0b, 0x92, 0x8f, 0x40, - 0x60, 0x80, 0x14, 0x90, 0x8c, 0x60, 0x14, 0x63, - 0x00, 0x40, 0x3e, 0x00, 0xe1, 0x02, 0x28, 0x00 -}; - -static const unsigned char XGI330_HiTVExtTiming[] = { - 0x2D, 0x60, 0x2C, 0x5F, 0x08, 0x31, 0x3A, 0x64, - 0x28, 0x02, 0x01, 0x3D, 0x06, 0x3E, 0x35, 0x6D, - 0x06, 0x14, 0x3E, 0x35, 0x6D, 0x00, 0xC5, 0x3F, - 0x64, 0x90, 0x33, 0x8C, 0x18, 0x36, 0x3E, 0x13, - 0x2A, 0xDE, 0x2A, 0x44, 0x40, 0x2A, 0x44, 0x40, - 0x8E, 0x8E, 0x82, 0x07, 0x0B, - 0x92, 0x0F, 0x40, 0x60, 0x80, 0x14, 0x90, 0x8C, - 0x60, 0x14, 0x3D, 0x63, 0x4F, - 0x27, 0x00, 0xfc, 0xff, 0x6a, 0x00 -}; - -static const unsigned char XGI330_HiTVSt1Timing[] = { - 0x32, 0x65, 0x2C, 0x5F, 0x08, 0x31, 0x3A, 0x65, - 0x28, 0x02, 0x01, 0x3D, 0x06, 0x3E, 0x35, 0x6D, - 0x06, 0x14, 0x3E, 0x35, 0x6D, 0x00, 0xC5, 0x3F, - 0x65, 0x90, 0x7B, 0xA8, 0x03, 0xF0, 0x87, 0x03, - 0x11, 0x15, 0x11, 0xCF, 0x10, 0x11, 0xCF, 0x10, - 0x35, 0x35, 0x3B, 0x69, 0x1D, - 0x92, 0x0F, 0x40, 0x60, 0x80, 0x14, 0x90, 0x8C, - 0x60, 0x04, 0x86, 0xAF, 0x5D, - 0x0E, 0x00, 0xfc, 0xff, 0x2d, 0x00 -}; - -static const unsigned char XGI330_HiTVSt2Timing[] = { - 0x32, 0x65, 0x2C, 0x5F, 0x08, 0x31, 0x3A, 0x64, - 0x28, 0x02, 0x01, 0x3D, 0x06, 0x3E, 0x35, 0x6D, - 0x06, 0x14, 0x3E, 0x35, 0x6D, 0x00, 0xC5, 0x3F, - 0x64, 0x90, 0x33, 0x8C, 0x18, 0x36, 0x3E, 0x13, - 0x2A, 0xDE, 0x2A, 0x44, 0x40, 0x2A, 0x44, 0x40, - 0x8E, 0x8E, 0x82, 0x07, 0x0B, - 0x92, 0x0F, 0x40, 0x60, 0x80, 0x14, 0x90, 0x8C, - 0x60, 0x14, 0x3D, 0x63, 0x4F, - 0x27, 0x00, 0xFC, 0xff, 0x6a, 0x00 -}; - -static const unsigned char XGI330_HiTVTextTiming[] = { - 0x32, 0x65, 0x2C, 0x5F, 0x08, 0x31, 0x3A, 0x65, - 0x28, 0x02, 0x01, 0x3D, 0x06, 0x3E, 0x35, 0x6D, - 0x06, 0x14, 0x3E, 0x35, 0x6D, 0x00, 0xC5, 0x3F, - 0x65, 0x90, 0xE7, 0xBC, 0x03, 0x0C, 0x97, 0x03, - 0x14, 0x78, 0x14, 0x08, 0x20, 0x14, 0x08, 0x20, - 0xC8, 0xC8, 0x3B, 0xD2, 0x26, - 0x92, 0x0F, 0x40, 0x60, 0x80, 0x14, 0x90, 0x8C, - 0x60, 0x04, 0x96, 0x72, 0x5C, - 0x11, 0x00, 0xFC, 0xFF, 0x32, 0x00 -}; - -static const unsigned char XGI330_YPbPr750pTiming[] = { - 0x30, 0x1d, 0xe8, 0x09, 0x09, 0xed, 0x0c, 0x0c, - 0x98, 0x0a, 0x01, 0x0c, 0x06, 0x0d, 0x04, 0x0a, - 0x06, 0x14, 0x0d, 0x04, 0x0a, 0x00, 0x85, 0x3f, - 0xed, 0x50, 0x70, 0x9f, 0x16, 0x59, 0x60, 0x13, - 0x27, 0x0b, 0x27, 0xfc, 0x30, 0x27, 0x1c, 0xb0, - 0x4b, 0x4b, 0x6f, 0x2f, 0x63, - 0x92, 0x0F, 0x40, 0x60, 0x80, 0x14, 0x90, 0x8C, - 0x60, 0x14, 0x73, 0x00, 0x40, - 0x11, 0x00, 0xfc, 0xff, 0x32, 0x00 -}; - -static const unsigned char XGI330_YPbPr525pTiming[] = { - 0x3E, 0x11, 0x06, 0x09, 0x0b, 0x0c, 0x0c, 0x0c, - 0x98, 0x0a, 0x01, 0x0d, 0x06, 0x0d, 0x04, 0x0a, - 0x06, 0x14, 0x0d, 0x04, 0x0a, 0x00, 0x85, 0x3f, - 0x0c, 0x50, 0xb2, 0x9f, 0x16, 0x59, 0x4f, 0x13, - 0xad, 0x11, 0xad, 0x1d, 0x40, 0x8a, 0x3d, 0xb8, - 0x51, 0x5e, 0x60, 0x49, 0x7d, - 0x92, 0x0F, 0x40, 0x60, 0x80, 0x14, 0x90, 0x8C, - 0x60, 0x14, 0x4B, 0x43, 0x41, - 0x11, 0x00, 0xFC, 0xFF, 0x32, 0x00 -}; - -static const unsigned char XGI330_YPbPr525iTiming[] = { - 0x1B, 0x21, 0x03, 0x09, 0x05, 0x06, 0x0C, 0x0C, - 0x94, 0x49, 0x01, 0x0A, 0x06, 0x0D, 0x04, 0x0A, - 0x06, 0x14, 0x0D, 0x04, 0x0A, 0x00, 0x85, 0x1B, - 0x0C, 0x50, 0x00, 0x97, 0x00, 0xDA, 0x4A, 0x17, - 0x7D, 0x05, 0x4B, 0x00, 0x00, 0xE2, 0x00, 0x02, - 0x03, 0x0A, 0x65, 0x9D, 0x08, - 0x92, 0x8F, 0x40, 0x60, 0x80, 0x14, 0x90, 0x8C, - 0x60, 0x14, 0x4B, 0x00, 0x40, - 0x44, 0x00, 0xDB, 0x02, 0x3B, 0x00 -}; - -static const unsigned char XGI330_HiTVGroup3Data[] = { - 0x00, 0x1A, 0x22, 0x63, 0x62, 0x22, 0x08, 0x5F, - 0x05, 0x21, 0xB2, 0xB2, 0x55, 0x77, 0x2A, 0xA6, - 0x25, 0x2F, 0x47, 0xFA, 0xC8, 0xFF, 0x8E, 0x20, - 0x8C, 0x6E, 0x60, 0x2E, 0x58, 0x48, 0x72, 0x44, - 0x56, 0x36, 0x4F, 0x6E, 0x3F, 0x80, 0x00, 0x80, - 0x4F, 0x7F, 0x03, 0xA8, 0x7D, 0x20, 0x1A, 0xA9, - 0x14, 0x05, 0x03, 0x7E, 0x64, 0x31, 0x14, 0x75, - 0x18, 0x05, 0x18, 0x05, 0x4C, 0xA8, 0x01 -}; - -static const unsigned char XGI330_HiTVGroup3Simu[] = { - 0x00, 0x1A, 0x22, 0x63, 0x62, 0x22, 0x08, 0x95, - 0xDB, 0x20, 0xB8, 0xB8, 0x55, 0x47, 0x2A, 0xA6, - 0x25, 0x2F, 0x47, 0xFA, 0xC8, 0xFF, 0x8E, 0x20, - 0x8C, 0x6E, 0x60, 0x15, 0x26, 0xD3, 0xE4, 0x11, - 0x56, 0x36, 0x4F, 0x6E, 0x3F, 0x80, 0x00, 0x80, - 0x67, 0x36, 0x01, 0x47, 0x0E, 0x10, 0xBE, 0xB4, - 0x01, 0x05, 0x03, 0x7E, 0x65, 0x31, 0x14, 0x75, - 0x18, 0x05, 0x18, 0x05, 0x4C, 0xA8, 0x01 -}; - -static const unsigned char XGI330_HiTVGroup3Text[] = { - 0x00, 0x1A, 0x22, 0x63, 0x62, 0x22, 0x08, 0xA7, - 0xF5, 0x20, 0xCE, 0xCE, 0x55, 0x47, 0x2A, 0xA6, - 0x25, 0x2F, 0x47, 0xFA, 0xC8, 0xFF, 0x8E, 0x20, - 0x8C, 0x6E, 0x60, 0x18, 0x2C, 0x0C, 0x20, 0x22, - 0x56, 0x36, 0x4F, 0x6E, 0x3F, 0x80, 0x00, 0x80, - 0x93, 0x3C, 0x01, 0x50, 0x2F, 0x10, 0xF4, 0xCA, - 0x01, 0x05, 0x03, 0x7E, 0x65, 0x31, 0x14, 0x75, - 0x18, 0x05, 0x18, 0x05, 0x4C, 0xA8, 0x01 -}; - -static const unsigned char XGI330_Ren525pGroup3[] = { - 0x00, 0x14, 0x15, 0x25, 0x55, 0x15, 0x0b, 0x13, - 0xB1, 0x41, 0x62, 0x62, 0xFF, 0xF4, 0x45, 0xa6, - 0x25, 0x2F, 0x67, 0xF6, 0xbf, 0xFF, 0x8E, 0x20, - 0xAC, 0xDA, 0x60, 0xFe, 0x6A, 0x9A, 0x06, 0x10, - 0xd1, 0x04, 0x18, 0x0a, 0xFF, 0x80, 0x00, 0x80, - 0x3c, 0x77, 0x00, 0xEF, 0xE0, 0x10, 0xB0, 0xE0, - 0x10, 0x4F, 0x0F, 0x0F, 0x05, 0x0F, 0x08, 0x6E, - 0x1a, 0x1F, 0x25, 0x2a, 0x4C, 0xAA, 0x01 -}; - -static const unsigned char XGI330_Ren750pGroup3[] = { - 0x00, 0x14, 0x15, 0x25, 0x55, 0x15, 0x0b, 0x7a, - 0x54, 0x41, 0xE7, 0xE7, 0xFF, 0xF4, 0x45, 0xa6, - 0x25, 0x2F, 0x67, 0xF6, 0xbf, 0xFF, 0x8E, 0x20, - 0xAC, 0x6A, 0x60, 0x2b, 0x52, 0xCD, 0x61, 0x10, - 0x51, 0x04, 0x18, 0x0a, 0x1F, 0x80, 0x00, 0x80, - 0xFF, 0xA4, 0x04, 0x2B, 0x94, 0x21, 0x72, 0x94, - 0x26, 0x05, 0x01, 0x0F, 0xed, 0x0F, 0x0A, 0x64, - 0x18, 0x1D, 0x23, 0x28, 0x4C, 0xAA, 0x01 -}; - -static const struct SiS_LVDSData XGI_LVDS1024x768Data_1[] = { - { 960, 438, 1344, 806}, /* 00 (320x200,320x400,640x200,640x400) */ - { 960, 388, 1344, 806}, /* 01 (320x350,640x350) */ - {1040, 438, 1344, 806}, /* 02 (360x400,720x400) */ - {1040, 388, 1344, 806}, /* 03 (720x350) */ - { 960, 518, 1344, 806}, /* 04 (320x240,640x480) */ - {1120, 638, 1344, 806}, /* 05 (400x300,800x600) */ - {1344, 806, 1344, 806} /* 06 (512x384,1024x768) */ -}; - - -static const struct SiS_LVDSData XGI_LVDS1024x768Data_2[] = { - {1344, 806, 1344, 806}, - {1344, 806, 1344, 806}, - {1344, 806, 1344, 806}, - {1344, 806, 1344, 806}, - {1344, 806, 1344, 806}, - {1344, 806, 1344, 806}, - {1344, 806, 1344, 806}, - {800, 449, 1280, 801}, - {800, 525, 1280, 813} -}; - -static const struct SiS_LVDSData XGI_LVDS1280x1024Data_1[] = { - {1048, 442, 1688, 1066}, - {1048, 392, 1688, 1066}, - {1048, 442, 1688, 1066}, - {1048, 392, 1688, 1066}, - {1048, 522, 1688, 1066}, - {1208, 642, 1688, 1066}, - {1432, 810, 1688, 1066}, - {1688, 1066, 1688, 1066} -}; - -#define XGI_LVDS1280x1024Data_2 XGI_LVDS1024x768Data_2 - -static const struct SiS_LVDSData XGI_LVDS1400x1050Data_1[] = { - {928, 416, 1688, 1066}, - {928, 366, 1688, 1066}, - {928, 416, 1688, 1066}, - {928, 366, 1688, 1066}, - {928, 496, 1688, 1066}, - {1088, 616, 1688, 1066}, - {1312, 784, 1688, 1066}, - {1568, 1040, 1688, 1066}, - {1688, 1066, 1688, 1066} -}; - -static const struct SiS_LVDSData XGI_LVDS1400x1050Data_2[] = { - {1688, 1066, 1688, 1066}, - {1688, 1066, 1688, 1066}, - {1688, 1066, 1688, 1066}, - {1688, 1066, 1688, 1066}, - {1688, 1066, 1688, 1066}, - {1688, 1066, 1688, 1066}, - {1688, 1066, 1688, 1066}, - {1688, 1066, 1688, 1066}, - {1688, 1066, 1688, 1066} -}; - -/* ;;[ycchen] 12/05/02 LCDHTxLCDVT=2048x1320 */ -static const struct SiS_LVDSData XGI_LVDS1600x1200Data_1[] = { - {1088, 520, 2048, 1320}, /* 00 (320x200,320x400,640x200,640x400) */ - {1088, 470, 2048, 1320}, /* 01 (320x350,640x350) */ - {1088, 520, 2048, 1320}, /* 02 (360x400,720x400) */ - {1088, 470, 2048, 1320}, /* 03 (720x350) */ - {1088, 600, 2048, 1320}, /* 04 (320x240,640x480) */ - {1248, 720, 2048, 1320}, /* 05 (400x300,800x600) */ - {1472, 888, 2048, 1320}, /* 06 (512x384,1024x768) */ - {1728, 1144, 2048, 1320}, /* 07 (640x512,1280x1024) */ - {1848, 1170, 2048, 1320}, /* 08 (1400x1050) */ - {2048, 1320, 2048, 1320} /* 09 (1600x1200) */ -}; - -static const struct SiS_LVDSData XGI_LVDSNoScalingData[] = { - { 800, 449, 800, 449}, /* 00 (320x200,320x400,640x200,640x400) */ - { 800, 449, 800, 449}, /* 01 (320x350,640x350) */ - { 800, 449, 800, 449}, /* 02 (360x400,720x400) */ - { 800, 449, 800, 449}, /* 03 (720x350) */ - { 800, 525, 800, 525}, /* 04 (640x480x60Hz) */ - {1056, 628, 1056, 628}, /* 05 (800x600x60Hz) */ - {1344, 806, 1344, 806}, /* 06 (1024x768x60Hz) */ - {1688, 1066, 1688, 1066}, /* 07 (1280x1024x60Hz) */ - {1688, 1066, 1688, 1066}, /* 08 (1400x1050x60Hz) */ - {2160, 1250, 2160, 1250}, /* 09 (1600x1200x60Hz) */ - {1688, 806, 1688, 806} /* 0A (1280x768x60Hz) */ -}; - -static const struct SiS_LVDSData XGI_LVDS1024x768Data_1x75[] = { - { 960, 438, 1312, 800}, /* 00 (320x200,320x400,640x200,640x400) */ - { 960, 388, 1312, 800}, /* 01 (320x350,640x350) */ - {1040, 438, 1312, 800}, /* 02 (360x400,720x400) */ - {1040, 388, 1312, 800}, /* 03 (720x350) */ - { 928, 512, 1312, 800}, /* 04 (320x240,640x480) */ - {1088, 632, 1312, 800}, /* 05 (400x300,800x600) */ - {1312, 800, 1312, 800}, /* 06 (512x384,1024x768) */ -}; - - -static const struct SiS_LVDSData XGI_LVDS1024x768Data_2x75[] = { - {1312, 800, 1312, 800}, /* ; 00 (320x200,320x400,640x200,640x400) */ - {1312, 800, 1312, 800}, /* ; 01 (320x350,640x350) */ - {1312, 800, 1312, 800}, /* ; 02 (360x400,720x400) */ - {1312, 800, 1312, 800}, /* ; 03 (720x350) */ - {1312, 800, 1312, 800}, /* ; 04 (320x240,640x480) */ - {1312, 800, 1312, 800}, /* ; 05 (400x300,800x600) */ - {1312, 800, 1312, 800}, /* ; 06 (512x384,1024x768) */ -}; - -static const struct SiS_LVDSData XGI_LVDS1280x1024Data_1x75[] = { - {1048, 442, 1688, 1066 }, /* ; 00 (320x200,320x400,640x200,640x400) */ - {1048, 392, 1688, 1066 }, /* ; 01 (320x350,640x350) */ - {1128, 442, 1688, 1066 }, /* ; 02 (360x400,720x400) */ - {1128, 392, 1688, 1066 }, /* ; 03 (720x350) */ - {1048, 522, 1688, 1066 }, /* ; 04 (320x240,640x480) */ - {1208, 642, 1688, 1066 }, /* ; 05 (400x300,800x600) */ - {1432, 810, 1688, 1066 }, /* ; 06 (512x384,1024x768) */ - {1688, 1066, 1688, 1066 }, /* ; 06; 07 (640x512,1280x1024) */ -}; - -static const struct SiS_LVDSData XGI_LVDS1280x1024Data_2x75[] = { - {1688, 1066, 1688, 1066 }, /* ; 00 (320x200,320x400,640x200,640x400) */ - {1688, 1066, 1688, 1066 }, /* ; 01 (320x350,640x350) */ - {1688, 1066, 1688, 1066 }, /* ; 02 (360x400,720x400) */ - {1688, 1066, 1688, 1066 }, /* ; 03 (720x350) */ - {1688, 1066, 1688, 1066 }, /* ; 04 (320x240,640x480) */ - {1688, 1066, 1688, 1066 }, /* ; 05 (400x300,800x600) */ - {1688, 1066, 1688, 1066 }, /* ; 06 (512x384,1024x768) */ - {1688, 1066, 1688, 1066 }, /* ; 06; 07 (640x512,1280x1024) */ -}; - -static const struct SiS_LVDSData XGI_LVDSNoScalingDatax75[] = { - { 800, 449, 800, 449}, /* ; 00 (320x200,320x400,640x200,640x400) */ - { 800, 449, 800, 449}, /* ; 01 (320x350,640x350) */ - { 900, 449, 900, 449}, /* ; 02 (360x400,720x400) */ - { 900, 449, 900, 449}, /* ; 03 (720x350) */ - { 800, 500, 800, 500}, /* ; 04 (640x480x75Hz) */ - {1056, 625, 1056, 625}, /* ; 05 (800x600x75Hz) */ - {1312, 800, 1312, 800}, /* ; 06 (1024x768x75Hz) */ - {1688, 1066, 1688, 1066}, /* ; 07 (1280x1024x75Hz) */ - {1688, 1066, 1688, 1066}, /* ; 08 (1400x1050x75Hz) - ;;[ycchen] 12/19/02 */ - {2160, 1250, 2160, 1250}, /* ; 09 (1600x1200x75Hz) */ - {1688, 806, 1688, 806}, /* ; 0A (1280x768x75Hz) */ -}; - -static const struct SiS_LVDSData XGI_LVDS1024x768Des_1[] = { - {0, 1048, 0, 771}, /* 00 (320x200,320x400,640x200,640x400) */ - {0, 1048, 0, 771}, /* 01 (320x350,640x350) */ - {0, 1048, 0, 771}, /* 02 (360x400,720x400) */ - {0, 1048, 0, 771}, /* 03 (720x350) */ - {0, 1048, 0, 771}, /* 04 (640x480x60Hz) */ - {0, 1048, 0, 771}, /* 05 (800x600x60Hz) */ - {0, 1048, 805, 770} /* 06 (1024x768x60Hz) */ -}; - -static const struct SiS_LVDSData XGI_LVDS1024x768Des_2[] = { - {1142, 856, 622, 587}, /* 00 (320x200,320x400,640x200,640x400) */ - {1142, 856, 597, 562}, /* 01 (320x350,640x350) */ - {1142, 856, 622, 587}, /* 02 (360x400,720x400) */ - {1142, 856, 597, 562}, /* 03 (720x350) */ - {1142, 1048, 722, 687}, /* 04 (640x480x60Hz) */ - {1232, 936, 722, 687}, /* 05 (800x600x60Hz) */ - { 0, 1048, 805, 771} /* 06 (1024x768x60Hz) */ -}; - -static const struct SiS_LVDSData XGI_LVDS1024x768Des_3[] = { - {320, 24, 622, 587}, /* 00 (320x200,320x400,640x200,640x400) */ - {320, 24, 597, 562}, /* 01 (320x350,640x350) */ - {320, 24, 622, 587}, /* 02 (360x400,720x400) */ - {320, 24, 597, 562}, /* 03 (720x350) */ - {320, 24, 722, 687} /* 04 (640x480x60Hz) */ -}; - -static const struct SiS_LVDSData XGI_LVDS1280x1024Des_1[] = { - {0, 1328, 0, 1025}, /* 00 (320x200,320x400,640x200,640x400) */ - {0, 1328, 0, 1025}, /* 01 (320x350,640x350) */ - {0, 1328, 0, 1025}, /* 02 (360x400,720x400) */ - {0, 1328, 0, 1025}, /* 03 (720x350) */ - {0, 1328, 0, 1025}, /* 04 (640x480x60Hz) */ - {0, 1328, 0, 1025}, /* 05 (800x600x60Hz) */ - {0, 1328, 0, 1025}, /* 06 (1024x768x60Hz) */ - {0, 1328, 1065, 1024} /* 07 (1280x1024x60Hz) */ -}; - - /* The Display setting for DE Mode Panel */ -static const struct SiS_LVDSData XGI_LVDS1280x1024Des_2[] = { - {1368, 1008, 752, 711}, /* 00 (320x200,320x400,640x200,640x400) */ - {1368, 1008, 729, 688}, /* 01 (320x350,640x350) */ - {1408, 1048, 752, 711}, /* 02 (360x400,720x400) */ - {1408, 1048, 729, 688}, /* 03 (720x350) */ - {1368, 1008, 794, 753}, /* 04 (640x480x60Hz) */ - {1448, 1068, 854, 813}, /* 05 (800x600x60Hz) */ - {1560, 1200, 938, 897}, /* 06 (1024x768x60Hz) */ - {0000, 1328, 0, 1025} /* 07 (1280x1024x60Hz) */ -}; - -static const struct SiS_LVDSData XGI_LVDS1400x1050Des_1[] = { - {0, 1448, 0, 1051}, /* 00 (320x200,320x400,640x200,640x400) */ - {0, 1448, 0, 1051}, /* 01 (320x350,640x350) */ - {0, 1448, 0, 1051}, /* 02 (360x400,720x400) */ - {0, 1448, 0, 1051}, /* 03 (720x350) */ - {0, 1448, 0, 1051}, /* 04 (640x480x60Hz) */ - {0, 1448, 0, 1051}, /* 05 (800x600x60Hz) */ - {0, 1448, 0, 1051}, /* 06 (1024x768x60Hz) */ - {0, 1448, 0, 1051}, /* 07 (1280x1024x60Hz) */ - {0, 1448, 0, 1051} /* 08 (1400x1050x60Hz) */ -}; - -static const struct SiS_LVDSData XGI_LVDS1400x1050Des_2[] = { - {1308, 1068, 781, 766}, /* 00 (320x200,320x400,640x200,640x400) */ - {1308, 1068, 781, 766}, /* 01 (320x350,640x350) */ - {1308, 1068, 781, 766}, /* 02 (360x400,720x400) */ - {1308, 1068, 781, 766}, /* 03 (720x350) */ - {1308, 1068, 781, 766}, /* 04 (640x480x60Hz) */ - {1388, 1148, 841, 826}, /* 05 (800x600x60Hz) */ - {1490, 1250, 925, 910}, /* 06 (1024x768x60Hz) */ - {1608, 1368, 1053, 1038}, /* 07 (1280x1024x60Hz) */ - { 0, 1448, 0, 1051} /* 08 (1400x1050x60Hz) */ -}; - -static const struct SiS_LVDSData XGI_LVDS1600x1200Des_1[] = { - {0, 1664, 0, 1201}, /* 00 (320x200,320x400,640x200,640x400) */ - {0, 1664, 0, 1201}, /* 01 (320x350,640x350) */ - {0, 1664, 0, 1201}, /* 02 (360x400,720x400) */ - {0, 1664, 0, 1201}, /* 03 (720x350) */ - {0, 1664, 0, 1201}, /* 04 (640x480x60Hz) */ - {0, 1664, 0, 1201}, /* 05 (800x600x60Hz) */ - {0, 1664, 0, 1201}, /* 06 (1024x768x60Hz) */ - {0, 1664, 0, 1201}, /* 07 (1280x1024x60Hz) */ - {0, 1664, 0, 1201}, /* 08 (1400x1050x60Hz) */ - {0, 1664, 0, 1201} /* 09 (1600x1200x60Hz) */ -}; - -static const struct XGI330_LCDDataDesStruct2 XGI_LVDSNoScalingDesData[] = { - {0, 648, 448, 405, 96, 2}, /* 00 (320x200,320x400, - 640x200,640x400) */ - {0, 648, 448, 355, 96, 2}, /* 01 (320x350,640x350) */ - {0, 648, 448, 405, 96, 2}, /* 02 (360x400,720x400) */ - {0, 648, 448, 355, 96, 2}, /* 03 (720x350) */ - {0, 648, 1, 483, 96, 2}, /* 04 (640x480x60Hz) */ - {0, 840, 627, 600, 128, 4}, /* 05 (800x600x60Hz) */ - {0, 1048, 805, 770, 136, 6}, /* 06 (1024x768x60Hz) */ - {0, 1328, 0, 1025, 112, 3}, /* 07 (1280x1024x60Hz) */ - {0, 1438, 0, 1051, 112, 3}, /* 08 (1400x1050x60Hz)*/ - {0, 1664, 0, 1201, 192, 3}, /* 09 (1600x1200x60Hz) */ - {0, 1328, 0, 0771, 112, 6} /* 0A (1280x768x60Hz) */ -}; - -/* ; 1024x768 Full-screen */ -static const struct SiS_LVDSData XGI_LVDS1024x768Des_1x75[] = { - {0, 1040, 0, 769}, /* ; 00 (320x200,320x400,640x200,640x400) */ - {0, 1040, 0, 769}, /* ; 01 (320x350,640x350) */ - {0, 1040, 0, 769}, /* ; 02 (360x400,720x400) */ - {0, 1040, 0, 769}, /* ; 03 (720x350) */ - {0, 1040, 0, 769}, /* ; 04 (640x480x75Hz) */ - {0, 1040, 0, 769}, /* ; 05 (800x600x75Hz) */ - {0, 1040, 0, 769} /* ; 06 (1024x768x75Hz) */ -}; - -/* ; 1024x768 center-screen (Enh. Mode) */ -static const struct SiS_LVDSData XGI_LVDS1024x768Des_2x75[] = { - {1142, 856, 622, 587}, /* 00 (320x200,320x400,640x200,640x400) */ - {1142, 856, 597, 562}, /* 01 (320x350,640x350) */ - {1142, 856, 622, 587}, /* 02 (360x400,720x400) */ - {1142, 856, 597, 562}, /* 03 (720x350) */ - {1142, 1048, 722, 687}, /* 04 (640x480x60Hz) */ - {1232, 936, 722, 687}, /* 05 (800x600x60Hz) */ - { 0, 1048, 805, 771} /* 06 (1024x768x60Hz) */ -}; - -/* ; 1024x768 center-screen (St.Mode) */ -static const struct SiS_LVDSData XGI_LVDS1024x768Des_3x75[] = { - {320, 24, 622, 587}, /* ; 00 (320x200,320x400,640x200,640x400) */ - {320, 24, 597, 562}, /* ; 01 (320x350,640x350) */ - {320, 24, 622, 587}, /* ; 02 (360x400,720x400) */ - {320, 24, 597, 562}, /* ; 03 (720x350) */ - {320, 24, 722, 687} /* ; 04 (640x480x60Hz) */ -}; - -static const struct SiS_LVDSData XGI_LVDS1280x1024Des_1x75[] = { - {0, 1296, 0, 1025}, /* ; 00 (320x200,320x400,640x200,640x400) */ - {0, 1296, 0, 1025}, /* ; 01 (320x350,640x350) */ - {0, 1296, 0, 1025}, /* ; 02 (360x400,720x400) */ - {0, 1296, 0, 1025}, /* ; 03 (720x350) */ - {0, 1296, 0, 1025}, /* ; 04 (640x480x75Hz) */ - {0, 1296, 0, 1025}, /* ; 05 (800x600x75Hz) */ - {0, 1296, 0, 1025}, /* ; 06 (1024x768x75Hz) */ - {0, 1296, 0, 1025} /* ; 07 (1280x1024x75Hz) */ -}; - -/* The Display setting for DE Mode Panel */ -/* Set DE as default */ -static const struct SiS_LVDSData XGI_LVDS1280x1024Des_2x75[] = { - {1368, 976, 752, 711}, /* ; 00 (320x200,320x400,640x200,640x400) */ - {1368, 976, 729, 688}, /* ; 01 (320x350,640x350) */ - {1408, 976, 752, 711}, /* ; 02 (360x400,720x400) */ - {1408, 976, 729, 688}, /* ; 03 (720x350) */ - {1368, 976, 794, 753}, /* ; 04 (640x480x75Hz) */ - {1448, 1036, 854, 813}, /* ; 05 (800x600x75Hz) */ - {1560, 1168, 938, 897}, /* ; 06 (1024x768x75Hz) */ - { 0, 1296, 0, 1025} /* ; 07 (1280x1024x75Hz) */ -}; - -/* Scaling LCD 75Hz */ -static const struct XGI330_LCDDataDesStruct2 XGI_LVDSNoScalingDesDatax75[] = { - {0, 648, 448, 405, 96, 2}, /* ; 00 (320x200,320x400, - 640x200,640x400) */ - {0, 648, 448, 355, 96, 2}, /* ; 01 (320x350,640x350) */ - {0, 729, 448, 405, 108, 2}, /* ; 02 (360x400,720x400) */ - {0, 729, 448, 355, 108, 2}, /* ; 03 (720x350) */ - {0, 656, 0, 481, 64, 3}, /* ; 04 (640x480x75Hz) */ - {0, 816, 0, 601, 80, 3}, /* ; 05 (800x600x75Hz) */ - {0, 1040, 0, 769, 96, 3}, /* ; 06 (1024x768x75Hz) */ - {0, 1296, 0, 1025, 144, 3}, /* ; 07 (1280x1024x75Hz) */ - {0, 1448, 0, 1051, 112, 3}, /* ; 08 (1400x1050x75Hz) */ - {0, 1664, 0, 1201, 192, 3}, /* ; 09 (1600x1200x75Hz) */ - {0, 1328, 0, 771, 112, 6} /* ; 0A (1280x768x75Hz) */ -}; - -/* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */ -static const struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11024x768_1_H[] = { - { {0x4B, 0x27, 0x8F, 0x32, 0x1B, 0x00, 0x45, 0x00} }, /* 00 (320x) */ - { {0x4B, 0x27, 0x8F, 0x2B, 0x03, 0x00, 0x44, 0x00} }, /* 01 (360x) */ - { {0x55, 0x31, 0x99, 0x46, 0x1D, 0x00, 0x55, 0x00} }, /* 02 (400x) */ - { {0x63, 0x3F, 0x87, 0x4A, 0x93, 0x00, 0x01, 0x00} }, /* 03 (512x) */ - { {0x73, 0x4F, 0x97, 0x55, 0x86, 0x00, 0x05, 0x00} }, /* 04 (640x) */ - { {0x73, 0x4F, 0x97, 0x55, 0x86, 0x00, 0x05, 0x00} }, /* 05 (720x) */ - { {0x87, 0x63, 0x8B, 0x69, 0x1A, 0x00, 0x26, 0x00} }, /* 06 (800x) */ - { {0xA3, 0x7F, 0x87, 0x86, 0x97, 0x00, 0x02, 0x00} } /* 07 (1024x) */ -}; - -/* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */ -static const struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11280x1024_1_H[] = { - { {0x56, 0x27, 0x9A, 0x30, 0x1E, 0x00, 0x05, 0x00 } }, /* 00 (320x) */ - { {0x56, 0x27, 0x9A, 0x30, 0x1E, 0x00, 0x05, 0x00 } }, /* 01 (360x) */ - { {0x60, 0x31, 0x84, 0x3A, 0x88, 0x00, 0x01, 0x00 } }, /* 02 (400x) */ - { {0x6E, 0x3F, 0x92, 0x48, 0x96, 0x00, 0x01, 0x00 } }, /* 03 (512x) */ - { {0x7E, 0x4F, 0x82, 0x58, 0x06, 0x00, 0x06, 0x00 } }, /* 04 (640x) */ - { {0x7E, 0x4F, 0x82, 0x58, 0x06, 0x00, 0x06, 0x00 } }, /* 05 (720x) */ - { {0x92, 0x63, 0x96, 0x6C, 0x1A, 0x00, 0x06, 0x00 } }, /* 06 (800x) */ - { {0xAE, 0x7F, 0x92, 0x88, 0x96, 0x00, 0x02, 0x00 } }, /* 07 (1024x) */ - { {0xCE, 0x9F, 0x92, 0xA8, 0x16, 0x00, 0x07, 0x00 } } /* 08 (1280x) */ -}; - -/* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */ -static const struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11024x768_2_H[] = { - { {0x63, 0x27, 0x87, 0x3B, 0x8C, 0x00, 0x01, 0x00} }, /* 00 (320x) */ - { {0x63, 0x27, 0x87, 0x3B, 0x8C, 0x00, 0x01, 0x00} }, /* 01 (360x) */ - { {0x63, 0x31, 0x87, 0x3D, 0x8E, 0x00, 0x01, 0x00} }, /* 02 (400x) */ - { {0x63, 0x3F, 0x87, 0x45, 0x96, 0x00, 0x01, 0x00} }, /* 03 (512x) */ - { {0xA3, 0x4F, 0x87, 0x6E, 0x9F, 0x00, 0x06, 0x00} }, /* 04 (640x) */ - { {0xA3, 0x4F, 0x87, 0x6E, 0x9F, 0x00, 0x06, 0x00} }, /* 05 (720x) */ - { {0xA3, 0x63, 0x87, 0x78, 0x89, 0x00, 0x02, 0x00} }, /* 06 (800x) */ - { {0xA3, 0x7F, 0x87, 0x86, 0x97, 0x00, 0x02, 0x00} } /* 07 (1024x) */ -}; - -/* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */ -static const struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11280x1024_2_H[] = { - { {0x7E, 0x3B, 0x9A, 0x44, 0x12, 0x00, 0x01, 0x00} }, /* 00 (320x) */ - { {0x7E, 0x3B, 0x9A, 0x44, 0x12, 0x00, 0x01, 0x00} }, /* 01 (360x) */ - { {0x7E, 0x40, 0x84, 0x49, 0x91, 0x00, 0x01, 0x00} }, /* 02 (400x) */ - { {0x7E, 0x47, 0x93, 0x50, 0x9E, 0x00, 0x01, 0x00} }, /* 03 (512x) */ - { {0xCE, 0x77, 0x8A, 0x80, 0x8E, 0x00, 0x02, 0x00} }, /* 04 (640x) */ - { {0xCE, 0x77, 0x8A, 0x80, 0x8E, 0x00, 0x02, 0x00} }, /* 05 (720x) */ - { {0xCE, 0x81, 0x94, 0x8A, 0x98, 0x00, 0x02, 0x00} }, /* 06 (800x) */ - { {0xCE, 0x8F, 0x82, 0x98, 0x06, 0x00, 0x07, 0x00} }, /* 07 (1024x) */ - { {0xCE, 0x9F, 0x92, 0xA8, 0x16, 0x00, 0x07, 0x00} } /* 08 (1280x) */ -}; - -/* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */ -static const struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11400x1050_1_H[] = { - { {0x47, 0x27, 0x8B, 0x2C, 0x1A, 0x00, 0x05, 0x00} }, /* 00 (320x) */ - { {0x47, 0x27, 0x8B, 0x30, 0x1E, 0x00, 0x05, 0x00} }, /* 01 (360x) */ - { {0x51, 0x31, 0x95, 0x36, 0x04, 0x00, 0x01, 0x00} }, /* 02 (400x) */ - { {0x5F, 0x3F, 0x83, 0x44, 0x92, 0x00, 0x01, 0x00} }, /* 03 (512x) */ - { {0x6F, 0x4F, 0x93, 0x54, 0x82, 0x00, 0x05, 0x00} }, /* 04 (640x) */ - { {0x6F, 0x4F, 0x93, 0x54, 0x82, 0x00, 0x05, 0x00} }, /* 05 (720x) */ - { {0x83, 0x63, 0x87, 0x68, 0x16, 0x00, 0x06, 0x00} }, /* 06 (800x) */ - { {0x9F, 0x7F, 0x83, 0x84, 0x92, 0x00, 0x02, 0x00} }, /* 07 (1024x) */ - { {0xBF, 0x9F, 0x83, 0xA4, 0x12, 0x00, 0x07, 0x00} }, /* 08 (1280x) */ - { {0xCE, 0xAE, 0x92, 0xB3, 0x01, 0x00, 0x03, 0x00} } /* 09 (1400x) */ -}; - -/* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */ -static const struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11400x1050_2_H[] = { - { {0x76, 0x3F, 0x83, 0x45, 0x8C, 0x00, 0x41, 0x00} }, /* 00 (320x) */ - { {0x76, 0x3F, 0x83, 0x45, 0x8C, 0x00, 0x41, 0x00} }, /* 01 (360x) */ - { {0x76, 0x31, 0x9A, 0x48, 0x9F, 0x00, 0x41, 0x00} }, /* 02 (400x) */ - { {0x76, 0x3F, 0x9A, 0x4F, 0x96, 0x00, 0x41, 0x00} }, /* 03 (512x) */ - { {0xCE, 0x7E, 0x82, 0x87, 0x9E, 0x00, 0x02, 0x00} }, /* 04 (640x) */ - { {0xCE, 0x7E, 0x82, 0x87, 0x9E, 0x00, 0x02, 0x00} }, /* 05 (720x) */ - { {0xCE, 0x63, 0x92, 0x96, 0x04, 0x00, 0x07, 0x00} }, /* 06 (800x) */ - { {0xCE, 0x7F, 0x92, 0xA4, 0x12, 0x00, 0x07, 0x00} }, /* 07 (1024x) */ - { {0xCE, 0x9F, 0x92, 0xB4, 0x02, 0x00, 0x03, 0x00} }, /* 08 (1280x) */ - { {0xCE, 0xAE, 0x92, 0xBC, 0x0A, 0x00, 0x03, 0x00} } /* 09 (1400x) */ -}; - -/* ;302lv channelA [ycchen] 12/05/02 LCDHT=2048 */ -/* ; CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */ -static const struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11600x1200_1_H[] = { - { {0x5B, 0x27, 0x9F, 0x32, 0x0A, 0x00, 0x01, 0x00} }, /* 00 (320x) */ - { {0x5B, 0x27, 0x9F, 0x32, 0x0A, 0x00, 0x01, 0x00} }, /* 01 (360x) */ - { {0x65, 0x31, 0x89, 0x3C, 0x94, 0x00, 0x01, 0x00} }, /* 02 (400x) */ - { {0x73, 0x3F, 0x97, 0x4A, 0x82, 0x00, 0x05, 0x00} }, /* 03 (512x) */ - { {0x83, 0x4F, 0x87, 0x51, 0x09, 0x00, 0x06, 0x00} }, /* 04 (640x) */ - { {0x83, 0x4F, 0x87, 0x51, 0x09, 0x00, 0x06, 0x00} }, /* 05 (720x) */ - { {0x97, 0x63, 0x9B, 0x65, 0x1D, 0x00, 0x06, 0xF0} }, /* 06 (800x) */ - { {0xB3, 0x7F, 0x97, 0x81, 0x99, 0x00, 0x02, 0x00} }, /* 07 (1024x) */ - { {0xD3, 0x9F, 0x97, 0xA1, 0x19, 0x00, 0x07, 0x00} }, /* 08 (1280x) */ - { {0xE2, 0xAE, 0x86, 0xB9, 0x91, 0x00, 0x03, 0x00} }, /* 09 (1400x) */ - { {0xFB, 0xC7, 0x9F, 0xC9, 0x81, 0x00, 0x07, 0x00} } /* 0A (1600x) */ -}; - -/* CR06,CR07,CR10,CR11,CR15,CR16,SR0A+CR09(5->7) */ -static const struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11024x768_1_V[] = { - { {0x97, 0x1F, 0x60, 0x87, 0x5D, 0x83, 0x10} }, /* 00 (x350) */ - { {0xB4, 0x1F, 0x92, 0x89, 0x8F, 0xB5, 0x30} }, /* 01 (x400) */ - { {0x04, 0x3E, 0xE2, 0x89, 0xDF, 0x05, 0x00} }, /* 02 (x480) */ - { {0x7C, 0xF0, 0x5A, 0x8F, 0x57, 0x7D, 0xA0} }, /* 03 (x600) */ - { {0x24, 0xF5, 0x02, 0x88, 0xFF, 0x25, 0x90} } /* 04 (x768) */ -}; - -/* CR06,CR07,CR10,CR11,CR15,CR16,SR0A */ -static const struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11024x768_2_V[] = { - { {0x24, 0xBB, 0x31, 0x87, 0x5D, 0x25, 0x30} }, /* 00 (x350) */ - { {0x24, 0xBB, 0x4A, 0x80, 0x8F, 0x25, 0x30} }, /* 01 (x400) */ - { {0x24, 0xBB, 0x72, 0x88, 0xDF, 0x25, 0x30} }, /* 02 (x480) */ - { {0x24, 0xF1, 0xAE, 0x84, 0x57, 0x25, 0xB0} }, /* 03 (x600) */ - { {0x24, 0xF5, 0x02, 0x88, 0xFF, 0x25, 0x90} } /* 04 (x768) */ -}; - -/* CR06,CR07,CR10,CR11,CR15,CR16,SR0A */ -static const struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11280x1024_1_V[] = { - { {0x86, 0x1F, 0x5E, 0x82, 0x5D, 0x87, 0x00} }, /* 00 (x350) */ - { {0xB8, 0x1F, 0x90, 0x84, 0x8F, 0xB9, 0x30} }, /* 01 (x400) */ - { {0x08, 0x3E, 0xE0, 0x84, 0xDF, 0x09, 0x00} }, /* 02 (x480) */ - { {0x80, 0xF0, 0x58, 0x8C, 0x57, 0x81, 0xA0} }, /* 03 (x600) */ - { {0x28, 0xF5, 0x00, 0x84, 0xFF, 0x29, 0x90} }, /* 04 (x768) */ - { {0x28, 0x5A, 0x13, 0x87, 0xFF, 0x29, 0xA9} } /* 05 (x1024) */ -}; - -/* CR06,CR07,CR10,CR11,CR15,CR16,SR0A */ -static const struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11280x1024_2_V[] = { - { {0x28, 0xD2, 0xAF, 0x83, 0xAE, 0xD8, 0xA1} }, /* 00 (x350) */ - { {0x28, 0xD2, 0xC8, 0x8C, 0xC7, 0xF2, 0x81} }, /* 01 (x400) */ - { {0x28, 0xD2, 0xF0, 0x84, 0xEF, 0x1A, 0xB1} }, /* 02 (x480) */ - { {0x28, 0xDE, 0x2C, 0x8F, 0x2B, 0x56, 0x91} }, /* 03 (x600) */ - { {0x28, 0xDE, 0x80, 0x83, 0x7F, 0xAA, 0x91} }, /* 04 (x768) */ - { {0x28, 0x5A, 0x13, 0x87, 0xFF, 0x29, 0xA9} } /* 05 (x1024) */ -}; - -/* CR06,CR07,CR10,CR11,CR15,CR16,SR0A */ -static const struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11400x1050_1_V[] = { - { {0x6C, 0x1F, 0x60, 0x84, 0x5D, 0x6D, 0x10} }, /* 00 (x350) */ - { {0x9E, 0x1F, 0x93, 0x86, 0x8F, 0x9F, 0x30} }, /* 01 (x400) */ - { {0xEE, 0x1F, 0xE2, 0x86, 0xDF, 0xEF, 0x10} }, /* 02 (x480) */ - { {0x66, 0xF0, 0x5A, 0x8e, 0x57, 0x67, 0xA0} }, /* 03 (x600) */ - { {0x0E, 0xF5, 0x02, 0x86, 0xFF, 0x0F, 0x90} }, /* 04 (x768) */ - { {0x0E, 0x5A, 0x02, 0x86, 0xFF, 0x0F, 0x89} }, /* 05 (x1024) */ - { {0x28, 0x10, 0x1A, 0x80, 0x19, 0x29, 0x0F} } /* 06 (x1050) */ -}; - -/* CR06,CR07,CR10,CR11,CR15,CR16,SR0A */ -static const struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11400x1050_2_V[] = { - { {0x28, 0x92, 0xB6, 0x83, 0xB5, 0xCF, 0x81} }, /* 00 (x350) */ - { {0x28, 0x92, 0xD5, 0x82, 0xD4, 0xEE, 0x81} }, /* 01 (x400) */ - { {0x28, 0x92, 0xFD, 0x8A, 0xFC, 0x16, 0xB1} }, /* 02 (x480) */ - { {0x28, 0xD4, 0x39, 0x86, 0x57, 0x29, 0x81} }, /* 03 (x600) */ - { {0x28, 0xD4, 0x8D, 0x9A, 0xFF, 0x29, 0xA1} }, /* 04 (x768) */ - { {0x28, 0x5A, 0x0D, 0x9A, 0xFF, 0x29, 0xA9} }, /* 05 (x1024) */ - { {0x28, 0x10, 0x1A, 0x87, 0x19, 0x29, 0x8F} } /* 06 (x1050) */ -}; - -/* CR06,CR07,CR10,CR11,CR15,CR16,SR0A+CR09(5->7) */ -static const struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11600x1200_1_V[] = { - { {0xd4, 0x1F, 0x81, 0x84, 0x5D, 0xd5, 0x10} }, /* 00 (x350) */ - { {0x06, 0x3e, 0xb3, 0x86, 0x8F, 0x07, 0x20} }, /* 01 (x400) */ - { {0x56, 0xba, 0x03, 0x86, 0xDF, 0x57, 0x00} }, /* 02 (x480) */ - { {0xce, 0xF0, 0x7b, 0x8e, 0x57, 0xcf, 0xa0} }, /* 03 (x600) */ - { {0x76, 0xF5, 0x23, 0x86, 0xFF, 0x77, 0x90} }, /* 04 (x768) */ - { {0x76, 0x5A, 0x23, 0x86, 0xFF, 0x77, 0x89} }, /* 05 (x1024) */ - { {0x90, 0x10, 0x1A, 0x8E, 0x19, 0x91, 0x2F} }, /* 06 (x1050) */ - { {0x26, 0x11, 0xd3, 0x86, 0xaF, 0x27, 0x3f} } /* 07 (x1200) */ -}; - -/* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */ -static const struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11024x768_1_Hx75[] = { - { {0x4B, 0x27, 0x8F, 0x32, 0x1B, 0x00, 0x45, 0x00} },/* ; 00 (320x) */ - { {0x4B, 0x27, 0x8F, 0x2B, 0x03, 0x00, 0x44, 0x00} },/* ; 01 (360x) */ - { {0x55, 0x31, 0x99, 0x46, 0x1D, 0x00, 0x55, 0x00} },/* ; 02 (400x) */ - { {0x63, 0x3F, 0x87, 0x4A, 0x93, 0x00, 0x01, 0x00} },/* ; 03 (512x) */ - { {0x6F, 0x4F, 0x93, 0x54, 0x80, 0x00, 0x05, 0x00} },/* ; 04 (640x) */ - { {0x6F, 0x4F, 0x93, 0x54, 0x80, 0x00, 0x05, 0x00} },/* ; 05 (720x) */ - { {0x83, 0x63, 0x87, 0x68, 0x14, 0x00, 0x26, 0x00} },/* ; 06 (800x) */ - { {0x9F, 0x7F, 0x83, 0x85, 0x91, 0x00, 0x02, 0x00} } /* ; 07 (1024x) */ -}; - -/* CR06,CR07,CR10,CR11,CR15,CR16,SR0A+CR09(5->7) */ -static const struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11024x768_1_Vx75[] = { - { {0x97, 0x1F, 0x60, 0x87, 0x5D, 0x83, 0x10} },/* ; 00 (x350) */ - { {0xB4, 0x1F, 0x92, 0x89, 0x8F, 0xB5, 0x30} },/* ; 01 (x400) */ - { {0xFE, 0x1F, 0xE0, 0x84, 0xDF, 0xFF, 0x10} },/* ; 02 (x480) */ - { {0x76, 0xF0, 0x58, 0x8C, 0x57, 0x77, 0xA0} },/* ; 03 (x600) */ - { {0x1E, 0xF5, 0x00, 0x83, 0xFF, 0x1F, 0x90} } /* ; 04 (x768) */ -}; - -/* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */ -static const struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11024x768_2_Hx75[] = { - { {0x63, 0x27, 0x87, 0x3B, 0x8C, 0x00, 0x01, 0x00} },/* ; 00 (320x) */ - { {0x63, 0x27, 0x87, 0x3B, 0x8C, 0x00, 0x01, 0x00} },/* ; 01 (360x) */ - { {0x63, 0x31, 0x87, 0x3D, 0x8E, 0x00, 0x01, 0x00} },/* ; 02 (400x) */ - { {0x63, 0x3F, 0x87, 0x45, 0x96, 0x00, 0x01, 0x00} },/* ; 03 (512x) */ - { {0xA3, 0x4F, 0x87, 0x6E, 0x9F, 0x00, 0x06, 0x00} },/* ; 04 (640x) */ - { {0xA3, 0x4F, 0x87, 0x6E, 0x9F, 0x00, 0x06, 0x00} },/* ; 05 (720x) */ - { {0xA3, 0x63, 0x87, 0x78, 0x89, 0x00, 0x02, 0x00} },/* ; 06 (800x) */ - { {0xA3, 0x7F, 0x87, 0x86, 0x97, 0x00, 0x02, 0x00} } /* ; 07 (1024x) */ -}; - -/* CR06,CR07,CR10,CR11,CR15,CR16,SR0A */ -static const struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11024x768_2_Vx75[] = { - { {0x24, 0xBB, 0x31, 0x87, 0x5D, 0x25, 0x30} },/* ; 00 (x350) */ - { {0x24, 0xBB, 0x4A, 0x80, 0x8F, 0x25, 0x30} },/* ; 01 (x400) */ - { {0x24, 0xBB, 0x72, 0x88, 0xDF, 0x25, 0x30} },/* ; 02 (x480) */ - { {0x24, 0xF1, 0xAE, 0x84, 0x57, 0x25, 0xB0} },/* ; 03 (x600) */ - { {0x24, 0xF5, 0x02, 0x88, 0xFF, 0x25, 0x90} } /* ; 04 (x768) */ -}; - -/* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */ -static const struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11280x1024_1_Hx75[] = { - { {0x56, 0x27, 0x9A, 0x30, 0x1E, 0x00, 0x05, 0x00} },/* ; 00 (320x) */ - { {0x56, 0x27, 0x9A, 0x30, 0x1E, 0x00, 0x05, 0x00} },/* ; 01 (360x) */ - { {0x60, 0x31, 0x84, 0x3A, 0x88, 0x00, 0x01, 0x00} },/* ; 02 (400x) */ - { {0x6E, 0x3F, 0x92, 0x48, 0x96, 0x00, 0x01, 0x00} },/* ; 03 (512x) */ - { {0x7E, 0x4F, 0x82, 0x54, 0x06, 0x00, 0x06, 0x00} },/* ; 04 (640x) */ - { {0x7E, 0x4F, 0x82, 0x54, 0x06, 0x00, 0x06, 0x00} },/* ; 05 (720x) */ - { {0x92, 0x63, 0x96, 0x68, 0x1A, 0x00, 0x06, 0x00} },/* ; 06 (800x) */ - { {0xAE, 0x7F, 0x92, 0x84, 0x96, 0x00, 0x02, 0x00} },/* ; 07 (1024x) */ - { {0xCE, 0x9F, 0x92, 0xA5, 0x17, 0x00, 0x07, 0x00} } /* ; 08 (1280x) */ -}; - -/* CR06,CR07,CR10,CR11,CR15,CR16,SR0A */ -static const struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11280x1024_1_Vx75[] = { - { {0x86, 0xD1, 0xBC, 0x80, 0xBB, 0xE5, 0x00} },/* ; 00 (x350) */ - { {0xB8, 0x1F, 0x90, 0x84, 0x8F, 0xB9, 0x30} },/* ; 01 (x400) */ - { {0x08, 0x3E, 0xE0, 0x84, 0xDF, 0x09, 0x00} },/* ; 02 (x480) */ - { {0x80, 0xF0, 0x58, 0x8C, 0x57, 0x81, 0xA0} },/* ; 03 (x600) */ - { {0x28, 0xF5, 0x00, 0x84, 0xFF, 0x29, 0x90} },/* ; 04 (x768) */ - { {0x28, 0x5A, 0x13, 0x87, 0xFF, 0x29, 0xA9} } /* ; 05 (x1024) */ -}; -/* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */ -static const struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11280x1024_2_Hx75[] = { - { {0x7E, 0x3B, 0x9A, 0x44, 0x12, 0x00, 0x01, 0x00} },/* ; 00 (320x) */ - { {0x7E, 0x3B, 0x9A, 0x44, 0x12, 0x00, 0x01, 0x00} },/* ; 01 (360x) */ - { {0x7E, 0x40, 0x84, 0x49, 0x91, 0x00, 0x01, 0x00} },/* ; 02 (400x) */ - { {0x7E, 0x47, 0x93, 0x50, 0x9E, 0x00, 0x01, 0x00} },/* ; 03 (512x) */ - { {0xCE, 0x77, 0x8A, 0x80, 0x8E, 0x00, 0x02, 0x00} },/* ; 04 (640x) */ - { {0xCE, 0x77, 0x8A, 0x80, 0x8E, 0x00, 0x02, 0x00} },/* ; 05 (720x) */ - { {0xCE, 0x81, 0x94, 0x8A, 0x98, 0x00, 0x02, 0x00} },/* ; 06 (800x) */ - { {0xCE, 0x8F, 0x82, 0x98, 0x06, 0x00, 0x07, 0x00} },/* ; 07 (1024x) */ - { {0xCE, 0x9F, 0x92, 0xA8, 0x16, 0x00, 0x07, 0x00} } /* ; 08 (1280x) */ -}; - -/* CR06,CR07,CR10,CR11,CR15,CR16,SR0A */ -static const struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11280x1024_2_Vx75[] = { - { {0x28, 0xD2, 0xAF, 0x83, 0xAE, 0xD8, 0xA1} },/* ; 00 (x350) */ - { {0x28, 0xD2, 0xC8, 0x8C, 0xC7, 0xF2, 0x81} },/* ; 01 (x400) */ - { {0x28, 0xD2, 0xF0, 0x84, 0xEF, 0x1A, 0xB1} },/* ; 02 (x480) */ - { {0x28, 0xDE, 0x2C, 0x8F, 0x2B, 0x56, 0x91} },/* ; 03 (x600) */ - { {0x28, 0xDE, 0x80, 0x83, 0x7F, 0xAA, 0x91} },/* ; 04 (x768) */ - { {0x28, 0x5A, 0x13, 0x87, 0xFF, 0x29, 0xA9} } /* ; 05 (x1024) */ -}; - -/*add for new UNIVGABIOS*/ -static const struct XGI330_LCDDataTablStruct XGI_LCDDataTable[] = { - {Panel_1024x768, 0x0019, 0x0001, XGI_ExtLCD1024x768Data }, - {Panel_1024x768, 0x0019, 0x0000, XGI_StLCD1024x768Data }, - {Panel_1024x768, 0x0018, 0x0010, XGI_CetLCD1024x768Data }, - {Panel_1280x1024, 0x0019, 0x0001, XGI_ExtLCD1280x1024Data }, - {Panel_1280x1024, 0x0019, 0x0000, XGI_StLCD1280x1024Data }, - {Panel_1280x1024, 0x0018, 0x0010, XGI_CetLCD1280x1024Data }, - {Panel_1400x1050, 0x0019, 0x0001, xgifb_lcd_1400x1050 }, - {Panel_1400x1050, 0x0019, 0x0000, xgifb_lcd_1400x1050 }, - {Panel_1400x1050, 0x0018, 0x0010, XGI_CetLCD1400x1050Data }, - {Panel_1600x1200, 0x0019, 0x0001, XGI_ExtLCD1600x1200Data }, - {Panel_1600x1200, 0x0019, 0x0000, XGI_StLCD1600x1200Data }, - {PanelRef60Hz, 0x0008, 0x0008, XGI_NoScalingData }, - {Panel_1024x768x75, 0x0019, 0x0001, XGI_ExtLCD1024x768x75Data }, - {Panel_1024x768x75, 0x0019, 0x0000, XGI_ExtLCD1024x768x75Data }, - {Panel_1024x768x75, 0x0018, 0x0010, XGI_CetLCD1024x768x75Data }, - {Panel_1280x1024x75, 0x0019, 0x0001, xgifb_lcd_1280x1024x75 }, - {Panel_1280x1024x75, 0x0019, 0x0000, xgifb_lcd_1280x1024x75 }, - {Panel_1280x1024x75, 0x0018, 0x0010, XGI_CetLCD1280x1024x75Data }, - {PanelRef75Hz, 0x0008, 0x0008, XGI_NoScalingDatax75 }, - {0xFF, 0x0000, 0x0000, NULL } /* End of table */ -}; - -static const struct XGI330_LCDDataTablStruct XGI_LCDDesDataTable[] = { - {Panel_1024x768, 0x0019, 0x0001, XGI_ExtLCDDes1024x768Data }, - {Panel_1024x768, 0x0019, 0x0000, XGI_StLCDDes1024x768Data }, - {Panel_1024x768, 0x0018, 0x0010, XGI_CetLCDDes1024x768Data }, - {Panel_1280x1024, 0x0019, 0x0001, XGI_ExtLCDDes1280x1024Data }, - {Panel_1280x1024, 0x0019, 0x0000, XGI_StLCDDes1280x1024Data }, - {Panel_1280x1024, 0x0018, 0x0010, XGI_CetLCDDes1280x1024Data }, - {Panel_1400x1050, 0x0019, 0x0001, xgifb_lcddes_1400x1050 }, - {Panel_1400x1050, 0x0019, 0x0000, xgifb_lcddes_1400x1050 }, - {Panel_1400x1050, 0x0418, 0x0010, XGI_CetLCDDes1400x1050Data }, - {Panel_1400x1050, 0x0418, 0x0410, XGI_CetLCDDes1400x1050Data2 }, - {Panel_1600x1200, 0x0019, 0x0001, XGI_ExtLCDDes1600x1200Data }, - {Panel_1600x1200, 0x0019, 0x0000, XGI_StLCDDes1600x1200Data }, - {PanelRef60Hz, 0x0008, 0x0008, XGI_NoScalingDesData }, - {Panel_1024x768x75, 0x0019, 0x0001, xgifb_lcddes_1024x768x75 }, - {Panel_1024x768x75, 0x0019, 0x0000, xgifb_lcddes_1024x768x75 }, - {Panel_1024x768x75, 0x0018, 0x0010, XGI_CetLCDDes1024x768x75Data }, - {Panel_1280x1024x75, 0x0019, 0x0001, xgifb_lcddes_1280x1024x75 }, - {Panel_1280x1024x75, 0x0019, 0x0000, xgifb_lcddes_1280x1024x75 }, - {Panel_1280x1024x75, 0x0018, 0x0010, XGI_CetLCDDes1280x1024x75Data }, - {PanelRef75Hz, 0x0008, 0x0008, XGI_NoScalingDesDatax75 }, - {0xFF, 0x0000, 0x0000, NULL } -}; - -static const struct XGI330_LCDDataTablStruct xgifb_lcddldes[] = { - {Panel_1024x768, 0x0019, 0x0001, XGI_ExtLCDDes1024x768Data }, - {Panel_1024x768, 0x0019, 0x0000, XGI_StLCDDes1024x768Data }, - {Panel_1024x768, 0x0018, 0x0010, XGI_CetLCDDes1024x768Data }, - {Panel_1280x1024, 0x0019, 0x0001, XGI_ExtLCDDLDes1280x1024Data }, - {Panel_1280x1024, 0x0019, 0x0000, XGI_StLCDDLDes1280x1024Data }, - {Panel_1280x1024, 0x0018, 0x0010, XGI_CetLCDDLDes1280x1024Data }, - {Panel_1400x1050, 0x0019, 0x0001, xgifb_lcddldes_1400x1050 }, - {Panel_1400x1050, 0x0019, 0x0000, xgifb_lcddldes_1400x1050 }, - {Panel_1400x1050, 0x0418, 0x0010, XGI_CetLCDDes1400x1050Data }, - {Panel_1400x1050, 0x0418, 0x0410, XGI_CetLCDDes1400x1050Data2 }, - {Panel_1600x1200, 0x0019, 0x0001, XGI_ExtLCDDLDes1600x1200Data }, - {Panel_1600x1200, 0x0019, 0x0000, XGI_StLCDDLDes1600x1200Data }, - {PanelRef60Hz, 0x0008, 0x0008, XGI_NoScalingDesData }, - {Panel_1024x768x75, 0x0019, 0x0001, xgifb_lcddes_1024x768x75 }, - {Panel_1024x768x75, 0x0019, 0x0000, xgifb_lcddes_1024x768x75 }, - {Panel_1024x768x75, 0x0018, 0x0010, XGI_CetLCDDes1024x768x75Data }, - {Panel_1280x1024x75, 0x0019, 0x0001, xgifb_lcddldes_1280x1024x75 }, - {Panel_1280x1024x75, 0x0019, 0x0000, xgifb_lcddldes_1280x1024x75 }, - {Panel_1280x1024x75, 0x0018, 0x0010, XGI_CetLCDDLDes1280x1024x75Data }, - {PanelRef75Hz, 0x0008, 0x0008, XGI_NoScalingDesDatax75 }, - {0xFF, 0x0000, 0x0000, NULL } -}; - -static const struct XGI330_LCDDataTablStruct xgifb_epllcd_crt1_h[] = { - {Panel_1024x768, 0x0018, 0x0000, XGI_LVDSCRT11024x768_1_H }, - {Panel_1024x768, 0x0018, 0x0010, XGI_LVDSCRT11024x768_2_H }, - {Panel_1280x1024, 0x0018, 0x0000, XGI_LVDSCRT11280x1024_1_H }, - {Panel_1280x1024, 0x0018, 0x0010, XGI_LVDSCRT11280x1024_2_H }, - {Panel_1400x1050, 0x0018, 0x0000, XGI_LVDSCRT11400x1050_1_H }, - {Panel_1400x1050, 0x0018, 0x0010, XGI_LVDSCRT11400x1050_2_H }, - {Panel_1600x1200, 0x0018, 0x0000, XGI_LVDSCRT11600x1200_1_H }, - {Panel_1024x768x75, 0x0018, 0x0000, XGI_LVDSCRT11024x768_1_Hx75 }, - {Panel_1024x768x75, 0x0018, 0x0010, XGI_LVDSCRT11024x768_2_Hx75 }, - {Panel_1280x1024x75, 0x0018, 0x0000, XGI_LVDSCRT11280x1024_1_Hx75 }, - {Panel_1280x1024x75, 0x0018, 0x0010, XGI_LVDSCRT11280x1024_2_Hx75 }, - {0xFF, 0x0000, 0x0000, NULL } -}; - -static const struct XGI330_LCDDataTablStruct xgifb_epllcd_crt1_v[] = { - {Panel_1024x768, 0x0018, 0x0000, XGI_LVDSCRT11024x768_1_V }, - {Panel_1024x768, 0x0018, 0x0010, XGI_LVDSCRT11024x768_2_V }, - {Panel_1280x1024, 0x0018, 0x0000, XGI_LVDSCRT11280x1024_1_V }, - {Panel_1280x1024, 0x0018, 0x0010, XGI_LVDSCRT11280x1024_2_V }, - {Panel_1400x1050, 0x0018, 0x0000, XGI_LVDSCRT11400x1050_1_V }, - {Panel_1400x1050, 0x0018, 0x0010, XGI_LVDSCRT11400x1050_2_V }, - {Panel_1600x1200, 0x0018, 0x0000, XGI_LVDSCRT11600x1200_1_V }, - {Panel_1024x768x75, 0x0018, 0x0000, XGI_LVDSCRT11024x768_1_Vx75 }, - {Panel_1024x768x75, 0x0018, 0x0010, XGI_LVDSCRT11024x768_2_Vx75 }, - {Panel_1280x1024x75, 0x0018, 0x0000, XGI_LVDSCRT11280x1024_1_Vx75 }, - {Panel_1280x1024x75, 0x0018, 0x0010, XGI_LVDSCRT11280x1024_2_Vx75 }, - {0xFF, 0x0000, 0x0000, NULL } -}; - -static const struct XGI330_LCDDataTablStruct XGI_EPLLCDDataPtr[] = { - {Panel_1024x768, 0x0018, 0x0000, XGI_LVDS1024x768Data_1 }, - {Panel_1024x768, 0x0018, 0x0010, XGI_LVDS1024x768Data_2 }, - {Panel_1280x1024, 0x0018, 0x0000, XGI_LVDS1280x1024Data_1 }, - {Panel_1280x1024, 0x0018, 0x0010, XGI_LVDS1280x1024Data_2 }, - {Panel_1400x1050, 0x0018, 0x0000, XGI_LVDS1400x1050Data_1 }, - {Panel_1400x1050, 0x0018, 0x0010, XGI_LVDS1400x1050Data_2 }, - {Panel_1600x1200, 0x0018, 0x0000, XGI_LVDS1600x1200Data_1 }, - {PanelRef60Hz, 0x0008, 0x0008, XGI_LVDSNoScalingData }, - {Panel_1024x768x75, 0x0018, 0x0000, XGI_LVDS1024x768Data_1x75 }, - {Panel_1024x768x75, 0x0018, 0x0010, XGI_LVDS1024x768Data_2x75 }, - {Panel_1280x1024x75, 0x0018, 0x0000, XGI_LVDS1280x1024Data_1x75 }, - {Panel_1280x1024x75, 0x0018, 0x0010, XGI_LVDS1280x1024Data_2x75 }, - {PanelRef75Hz, 0x0008, 0x0008, XGI_LVDSNoScalingDatax75 }, - {0xFF, 0x0000, 0x0000, NULL } -}; - -static const struct XGI330_LCDDataTablStruct XGI_EPLLCDDesDataPtr[] = { - {Panel_1024x768, 0x0018, 0x0000, XGI_LVDS1024x768Des_1 }, - {Panel_1024x768, 0x0618, 0x0410, XGI_LVDS1024x768Des_3 }, - {Panel_1024x768, 0x0018, 0x0010, XGI_LVDS1024x768Des_2 }, - {Panel_1280x1024, 0x0018, 0x0000, XGI_LVDS1280x1024Des_1 }, - {Panel_1280x1024, 0x0018, 0x0010, XGI_LVDS1280x1024Des_2 }, - {Panel_1400x1050, 0x0018, 0x0000, XGI_LVDS1400x1050Des_1 }, - {Panel_1400x1050, 0x0018, 0x0010, XGI_LVDS1400x1050Des_2 }, - {Panel_1600x1200, 0x0018, 0x0000, XGI_LVDS1600x1200Des_1 }, - {PanelRef60Hz, 0x0008, 0x0008, XGI_LVDSNoScalingDesData }, - {Panel_1024x768x75, 0x0018, 0x0000, XGI_LVDS1024x768Des_1x75 }, - {Panel_1024x768x75, 0x0618, 0x0410, XGI_LVDS1024x768Des_3x75 }, - {Panel_1024x768x75, 0x0018, 0x0010, XGI_LVDS1024x768Des_2x75 }, - {Panel_1280x1024x75, 0x0018, 0x0000, XGI_LVDS1280x1024Des_1x75 }, - {Panel_1280x1024x75, 0x0018, 0x0010, XGI_LVDS1280x1024Des_2x75 }, - {PanelRef75Hz, 0x0008, 0x0008, XGI_LVDSNoScalingDesDatax75 }, - {0xFF, 0x0000, 0x0000, NULL } -}; - -static const struct XGI330_TVDataTablStruct XGI_TVDataTable[] = { - {0x09E1, 0x0001, XGI_ExtPALData}, - {0x09E1, 0x0000, XGI_ExtNTSCData}, - {0x09E1, 0x0801, XGI_StPALData}, - {0x09E1, 0x0800, XGI_StNTSCData}, - {0x49E0, 0x0100, XGI_ExtHiTVData}, - {0x49E0, 0x4100, XGI_St2HiTVData}, - {0x49E0, 0x4900, XGI_St1HiTVData}, - {0x09E0, 0x0020, XGI_ExtYPbPr525iData}, - {0x09E0, 0x0040, XGI_ExtYPbPr525pData}, - {0x09E0, 0x0080, XGI_ExtYPbPr750pData}, - {0x09E0, 0x0820, XGI_StYPbPr525iData}, - {0x09E0, 0x0840, XGI_StYPbPr525pData}, - {0x09E0, 0x0880, XGI_StYPbPr750pData}, - {0xffff, 0x0000, XGI_ExtNTSCData}, -}; - -/* Dual link only */ -static const struct XGI330_LCDCapStruct XGI_LCDDLCapList[] = { -/* LCDCap1024x768 */ - {Panel_1024x768, DefaultLCDCap, 0x88, 0x06, VCLK65_315, - 0x6C, 0xC3, 0x35, 0x62, - 0x0A, 0xC0, 0x28, 0x10}, -/* LCDCap1280x1024 */ - {Panel_1280x1024, XGI_LCDDualLink+DefaultLCDCap, - 0x70, 0x03, VCLK108_2_315, - 0x70, 0x44, 0xF8, 0x2F, - 0x0A, 0xC0, 0x30, 0x10}, -/* LCDCap1400x1050 */ - {Panel_1400x1050, XGI_LCDDualLink+DefaultLCDCap, - 0x70, 0x03, VCLK108_2_315, - 0x70, 0x44, 0xF8, 0x2F, - 0x0A, 0xC0, 0x30, 0x10}, -/* LCDCap1600x1200 */ - {Panel_1600x1200, XGI_LCDDualLink+DefaultLCDCap, - 0xC0, 0x03, VCLK162, - 0x43, 0x22, 0x70, 0x24, - 0x0A, 0xC0, 0x30, 0x10}, -/* LCDCap1024x768x75 */ - {Panel_1024x768x75, DefaultLCDCap, 0x60, 0, VCLK78_75, - 0x2B, 0x61, 0x2B, 0x61, - 0x0A, 0xC0, 0x28, 0x10}, -/* LCDCap1280x1024x75 */ - {Panel_1280x1024x75, XGI_LCDDualLink+DefaultLCDCap, - 0x90, 0x03, VCLK135_5, - 0x54, 0x42, 0x4A, 0x61, - 0x0A, 0xC0, 0x30, 0x10}, -/* LCDCapDefault */ - {0xFF, DefaultLCDCap, 0x88, 0x06, VCLK65_315, - 0x6C, 0xC3, 0x35, 0x62, - 0x0A, 0xC0, 0x28, 0x10} -}; - -static const struct XGI330_LCDCapStruct XGI_LCDCapList[] = { -/* LCDCap1024x768 */ - {Panel_1024x768, DefaultLCDCap, 0x88, 0x06, VCLK65_315, - 0x6C, 0xC3, 0x35, 0x62, - 0x0A, 0xC0, 0x28, 0x10}, -/* LCDCap1280x1024 */ - {Panel_1280x1024, DefaultLCDCap, - 0x70, 0x03, VCLK108_2_315, - 0x70, 0x44, 0xF8, 0x2F, - 0x0A, 0xC0, 0x30, 0x10}, -/* LCDCap1400x1050 */ - {Panel_1400x1050, DefaultLCDCap, - 0x70, 0x03, VCLK108_2_315, - 0x70, 0x44, 0xF8, 0x2F, - 0x0A, 0xC0, 0x30, 0x10}, -/* LCDCap1600x1200 */ - {Panel_1600x1200, DefaultLCDCap, - 0xC0, 0x03, VCLK162, - 0x5A, 0x23, 0x5A, 0x23, - 0x0A, 0xC0, 0x30, 0x10}, -/* LCDCap1024x768x75 */ - {Panel_1024x768x75, DefaultLCDCap, 0x60, 0, VCLK78_75, - 0x2B, 0x61, 0x2B, 0x61, - 0x0A, 0xC0, 0x28, 0x10}, -/* LCDCap1280x1024x75 */ - {Panel_1280x1024x75, DefaultLCDCap, - 0x90, 0x03, VCLK135_5, - 0x54, 0x42, 0x4A, 0x61, - 0x0A, 0xC0, 0x30, 0x10}, -/* LCDCapDefault */ - {0xFF, DefaultLCDCap, 0x88, 0x06, VCLK65_315, - 0x6C, 0xC3, 0x35, 0x62, - 0x0A, 0xC0, 0x28, 0x10} -}; - -const struct XGI_Ext2Struct XGI330_RefIndex[] = { - {Mode32Bpp + SupportAllCRT2 + SyncPN, RES320x200, VCLK25_175, - 0x00, 0x10, 0x59, 320, 200},/* 00 */ - {Mode32Bpp + SupportAllCRT2 + SyncPN, RES320x200, VCLK25_175, - 0x00, 0x10, 0x00, 320, 400},/* 01 */ - {Mode32Bpp + SupportAllCRT2 + SyncNN, RES320x240, VCLK25_175, - 0x04, 0x20, 0x50, 320, 240},/* 02 */ - {Mode32Bpp + SupportAllCRT2 + SyncPP, RES400x300, VCLK40, - 0x05, 0x32, 0x51, 400, 300},/* 03 */ - {Mode32Bpp + NoSupportTV + SyncNN + SupportTV1024, RES512x384, - VCLK65_315, 0x06, 0x43, 0x52, 512, 384},/* 04 */ - {Mode32Bpp + SupportAllCRT2 + SyncPN, RES640x400, VCLK25_175, - 0x00, 0x14, 0x2f, 640, 400},/* 05 */ - {Mode32Bpp + SupportAllCRT2 + SyncNN, RES640x480x60, VCLK25_175, - 0x04, 0x24, 0x2e, 640, 480},/* 06 640x480x60Hz (LCD 640x480x60z) */ - {Mode32Bpp + NoSupportHiVisionTV + SyncNN, RES640x480x72, VCLK31_5, - 0x04, 0x24, 0x2e, 640, 480},/* 07 640x480x72Hz (LCD 640x480x70Hz) */ - {Mode32Bpp + NoSupportHiVisionTV + SyncNN, RES640x480x75, VCLK31_5, - 0x47, 0x24, 0x2e, 640, 480},/* 08 640x480x75Hz (LCD 640x480x75Hz) */ - {Mode32Bpp + SupportRAMDAC2 + SyncNN, RES640x480x85, VCLK36, - 0x8A, 0x24, 0x2e, 640, 480},/* 09 640x480x85Hz */ - {Mode32Bpp + SupportRAMDAC2 + SyncPN, RES640x480x100, VCLK43_163, - 0x00, 0x24, 0x2e, 640, 480},/* 0a 640x480x100Hz */ - {Mode32Bpp + SupportRAMDAC2 + SyncPN, RES640x480x120, VCLK52_406, - 0x00, 0x24, 0x2e, 640, 480},/* 0b 640x480x120Hz */ - {Mode32Bpp + SupportRAMDAC2 + SyncPN, RES640x480x160, VCLK72_852, - 0x00, 0x24, 0x2e, 640, 480},/* 0c 640x480x160Hz */ - {Mode32Bpp + SupportRAMDAC2 + SyncNN, RES640x480x200, VCLK86_6, - 0x00, 0x24, 0x2e, 640, 480},/* 0d 640x480x200Hz */ - {Mode32Bpp + NoSupportLCD + SyncPP, RES800x600x56, VCLK36, - 0x05, 0x36, 0x6a, 800, 600},/* 0e 800x600x56Hz */ - {Mode32Bpp + NoSupportTV + SyncPP, RES800x600x60, VCLK40, - 0x05, 0x36, 0x6a, 800, 600},/* 0f 800x600x60Hz (LCD 800x600x60Hz) */ - {Mode32Bpp + NoSupportHiVisionTV + SyncPP, RES800x600x72, VCLK50, - 0x48, 0x36, 0x6a, 800, 600},/* 10 800x600x72Hz (LCD 800x600x70Hz) */ - {Mode32Bpp + NoSupportHiVisionTV + SyncPP, RES800x600x75, VCLK49_5, - 0x8B, 0x36, 0x6a, 800, 600},/* 11 800x600x75Hz (LCD 800x600x75Hz) */ - {Mode32Bpp + SupportRAMDAC2 + SyncPP, RES800x600x85, VCLK56_25, - 0x00, 0x36, 0x6a, 800, 600},/* 12 800x600x85Hz */ - {Mode32Bpp + SupportRAMDAC2 + SyncPN, RES800x600x100, VCLK68_179, - 0x00, 0x36, 0x6a, 800, 600},/* 13 800x600x100Hz */ - {Mode32Bpp + SupportRAMDAC2 + SyncPN, RES800x600x120, VCLK83_95, - 0x00, 0x36, 0x6a, 800, 600},/* 14 800x600x120Hz */ - {Mode32Bpp + SupportRAMDAC2 + SyncPN, RES800x600x160, VCLK116_406, - 0x00, 0x36, 0x6a, 800, 600},/* 15 800x600x160Hz */ - {Mode32Bpp + InterlaceMode + SyncPP, RES1024x768x43, VCLK44_9, - 0x00, 0x47, 0x37, 1024, 768},/* 16 1024x768x43Hz */ - /* 17 1024x768x60Hz (LCD 1024x768x60Hz) */ - {Mode32Bpp + NoSupportTV + SyncNN + SupportTV1024, RES1024x768x60, - VCLK65_315, 0x06, 0x47, 0x37, 1024, 768}, - {Mode32Bpp + NoSupportHiVisionTV + SyncNN, RES1024x768x70, VCLK75, - 0x49, 0x47, 0x37, 1024, 768},/* 18 1024x768x70Hz (LCD 1024x768x70Hz) */ - {Mode32Bpp + NoSupportHiVisionTV + SyncPP, RES1024x768x75, VCLK78_75, - 0x00, 0x47, 0x37, 1024, 768},/* 19 1024x768x75Hz (LCD 1024x768x75Hz) */ - {Mode32Bpp + SupportRAMDAC2 + SyncPP, RES1024x768x85, VCLK94_5, - 0x8C, 0x47, 0x37, 1024, 768},/* 1a 1024x768x85Hz */ - {Mode32Bpp + SupportRAMDAC2 + SyncPN, RES1024x768x100, VCLK113_309, - 0x00, 0x47, 0x37, 1024, 768},/* 1b 1024x768x100Hz */ - {Mode32Bpp + SupportRAMDAC2 + SyncPN, RES1024x768x120, VCLK139_054, - 0x00, 0x47, 0x37, 1024, 768},/* 1c 1024x768x120Hz */ - {Mode32Bpp + SupportLCD + SyncPP, RES1280x960x60, VCLK108_2_315, - 0x08, 0x58, 0x7b, 1280, 960},/* 1d 1280x960x60Hz */ - {Mode32Bpp + InterlaceMode + SyncPP, RES1280x1024x43, VCLK78_75, - 0x00, 0x58, 0x3a, 1280, 1024},/* 1e 1280x1024x43Hz */ - {Mode32Bpp + NoSupportTV + SyncPP, RES1280x1024x60, VCLK108_2_315, - 0x07, 0x58, 0x3a, 1280, 1024},/*1f 1280x1024x60Hz (LCD 1280x1024x60Hz)*/ - {Mode32Bpp + NoSupportTV + SyncPP, RES1280x1024x75, VCLK135_5, - 0x00, 0x58, 0x3a, 1280, 1024},/*20 1280x1024x75Hz (LCD 1280x1024x75Hz)*/ - {Mode32Bpp + SyncPP, RES1280x1024x85, VCLK157_5, - 0x00, 0x58, 0x3a, 1280, 1024},/* 21 1280x1024x85Hz */ - /* 22 1600x1200x60Hz */ - {Mode32Bpp + SupportLCD + SyncPP + SupportCRT2in301C, - RES1600x1200x60, VCLK162, 0x09, 0x7A, 0x3c, 1600, 1200}, - {Mode32Bpp + SyncPP + SupportCRT2in301C, RES1600x1200x65, VCLK175, - 0x00, 0x69, 0x3c, 1600, 1200},/* 23 1600x1200x65Hz */ - {Mode32Bpp + SyncPP + SupportCRT2in301C, RES1600x1200x70, VCLK189, - 0x00, 0x69, 0x3c, 1600, 1200},/* 24 1600x1200x70Hz */ - {Mode32Bpp + SyncPP + SupportCRT2in301C, RES1600x1200x75, VCLK202_5, - 0x00, 0x69, 0x3c, 1600, 1200},/* 25 1600x1200x75Hz */ - {Mode32Bpp + SyncPP, RES1600x1200x85, VCLK229_5, - 0x00, 0x69, 0x3c, 1600, 1200},/* 26 1600x1200x85Hz */ - {Mode32Bpp + SyncPP, RES1600x1200x100, VCLK269_655, - 0x00, 0x69, 0x3c, 1600, 1200},/* 27 1600x1200x100Hz */ - {Mode32Bpp + SyncPP, RES1600x1200x120, VCLK323_586, - 0x00, 0x69, 0x3c, 1600, 1200},/* 28 1600x1200x120Hz */ - {Mode32Bpp + SupportLCD + SyncNP, RES1920x1440x60, VCLK234, - 0x00, 0x00, 0x68, 1920, 1440},/* 29 1920x1440x60Hz */ - {Mode32Bpp + SyncPN, RES1920x1440x65, VCLK254_817, - 0x00, 0x00, 0x68, 1920, 1440},/* 2a 1920x1440x65Hz */ - {Mode32Bpp + SyncPN, RES1920x1440x70, VCLK277_015, - 0x00, 0x00, 0x68, 1920, 1440},/* 2b 1920x1440x70Hz */ - {Mode32Bpp + SyncPN, RES1920x1440x75, VCLK291_132, - 0x00, 0x00, 0x68, 1920, 1440},/* 2c 1920x1440x75Hz */ - {Mode32Bpp + SyncPN, RES1920x1440x85, VCLK330_615, - 0x00, 0x00, 0x68, 1920, 1440},/* 2d 1920x1440x85Hz */ - {Mode16Bpp + SyncPN, RES1920x1440x100, VCLK388_631, - 0x00, 0x00, 0x68, 1920, 1440},/* 2e 1920x1440x100Hz */ - {Mode32Bpp + SupportLCD + SyncPN, RES2048x1536x60, VCLK266_952, - 0x00, 0x00, 0x6c, 2048, 1536},/* 2f 2048x1536x60Hz */ - {Mode32Bpp + SyncPN, RES2048x1536x65, VCLK291_766, - 0x00, 0x00, 0x6c, 2048, 1536},/* 30 2048x1536x65Hz */ - {Mode32Bpp + SyncPN, RES2048x1536x70, VCLK315_195, - 0x00, 0x00, 0x6c, 2048, 1536},/* 31 2048x1536x70Hz */ - {Mode32Bpp + SyncPN, RES2048x1536x75, VCLK340_477, - 0x00, 0x00, 0x6c, 2048, 1536},/* 32 2048x1536x75Hz */ - {Mode16Bpp + SyncPN, RES2048x1536x85, VCLK375_847, - 0x00, 0x00, 0x6c, 2048, 1536},/* 33 2048x1536x85Hz */ - {Mode32Bpp + SupportHiVision + SupportRAMDAC2 + - SyncPP + SupportYPbPr750p, RES800x480x60, VCLK39_77, - 0x08, 0x00, 0x70, 800, 480},/* 34 800x480x60Hz */ - {Mode32Bpp + SupportRAMDAC2 + SyncPP, RES800x480x75, VCLK49_5, - 0x08, 0x00, 0x70, 800, 480},/* 35 800x480x75Hz */ - {Mode32Bpp + SupportRAMDAC2 + SyncPP, RES800x480x85, VCLK56_25, - 0x08, 0x00, 0x70, 800, 480},/* 36 800x480x85Hz */ - {Mode32Bpp + SupportHiVision + SupportRAMDAC2 + - SyncPP + SupportYPbPr750p, RES1024x576x60, VCLK65_315, - 0x09, 0x00, 0x71, 1024, 576},/* 37 1024x576x60Hz */ - {Mode32Bpp + SupportRAMDAC2 + SyncPP, RES1024x576x75, VCLK78_75, - 0x09, 0x00, 0x71, 1024, 576},/* 38 1024x576x75Hz */ - {Mode32Bpp + SupportRAMDAC2 + SyncPP, RES1024x576x85, VCLK94_5, - 0x09, 0x00, 0x71, 1024, 576},/* 39 1024x576x85Hz */ - {Mode32Bpp + SupportHiVision + SupportRAMDAC2 + - SyncPP + SupportYPbPr750p, RES1280x720x60, VCLK108_2_315, - 0x0A, 0x00, 0x75, 1280, 720},/* 3a 1280x720x60Hz*/ - {Mode32Bpp + SupportRAMDAC2 + SyncPP, RES1280x720x75, VCLK135_5, - 0x0A, 0x00, 0x75, 1280, 720},/* 3b 1280x720x75Hz */ - {Mode32Bpp + SupportRAMDAC2 + SyncPP, RES1280x720x85, VCLK157_5, - 0x0A, 0x00, 0x75, 1280, 720},/* 3c 1280x720x85Hz */ - {Mode32Bpp + SupportTV + SyncNN, RES720x480x60, VCLK28_322, - 0x06, 0x00, 0x31, 720, 480},/* 3d 720x480x60Hz */ - {Mode32Bpp + SupportTV + SyncPP, RES720x576x56, VCLK36, - 0x06, 0x00, 0x32, 720, 576},/* 3e 720x576x56Hz */ - {Mode32Bpp + InterlaceMode + NoSupportLCD + SyncPP, RES856x480x79I, - VCLK35_2, 0x00, 0x00, 0x00, 856, 480},/* 3f 856x480x79I */ - {Mode32Bpp + NoSupportLCD + SyncNN, RES856x480x60, VCLK35_2, - 0x00, 0x00, 0x00, 856, 480},/* 40 856x480x60Hz */ - {Mode32Bpp + NoSupportHiVisionTV + SyncPP, RES1280x768x60, - VCLK79_411, 0x08, 0x48, 0x23, 1280, 768},/* 41 1280x768x60Hz */ - {Mode32Bpp + NoSupportHiVisionTV + SyncPP, RES1400x1050x60, - VCLK122_61, 0x08, 0x69, 0x26, 1400, 1050},/* 42 1400x1050x60Hz */ - {Mode32Bpp + SupportRAMDAC2 + SyncPP, RES1152x864x60, VCLK80_350, - 0x37, 0x00, 0x20, 1152, 864},/* 43 1152x864x60Hz */ - {Mode32Bpp + SupportRAMDAC2 + SyncPP, RES1152x864x75, VCLK107_385, - 0x37, 0x00, 0x20, 1152, 864},/* 44 1152x864x75Hz */ - {Mode32Bpp + SupportLCD + SupportRAMDAC2 + SyncPP, RES1280x960x75, - VCLK125_999, 0x3A, 0x88, 0x7b, 1280, 960},/* 45 1280x960x75Hz */ - {Mode32Bpp + SupportLCD + SupportRAMDAC2 + SyncPP, RES1280x960x85, - VCLK148_5, 0x0A, 0x88, 0x7b, 1280, 960},/* 46 1280x960x85Hz */ - {Mode32Bpp + SupportLCD + SupportRAMDAC2 + SyncPP, RES1280x960x120, - VCLK217_325, 0x3A, 0x88, 0x7b, 1280, 960},/* 47 1280x960x120Hz */ - {Mode32Bpp + SupportRAMDAC2 + SyncPN, RES1024x768x160, VCLK139_054, - 0x30, 0x47, 0x37, 1024, 768},/* 48 1024x768x160Hz */ -}; - -static const unsigned char XGI330_ScreenOffset[] = { - 0x14, 0x19, 0x20, 0x28, 0x32, 0x40, - 0x50, 0x64, 0x78, 0x80, 0x2d, 0x35, - 0x57, 0x48 -}; - -static const struct SiS_ModeResInfo_S XGI330_ModeResInfo[] = { - { 320, 200, 8, 8}, - { 320, 240, 8, 8}, - { 320, 400, 8, 8}, - { 400, 300, 8, 8}, - { 512, 384, 8, 8}, - { 640, 400, 8, 16}, - { 640, 480, 8, 16}, - { 800, 600, 8, 16}, - {1024, 768, 8, 16}, - {1280, 1024, 8, 16}, - {1600, 1200, 8, 16}, - {1920, 1440, 8, 16}, - {2048, 1536, 8, 16}, - { 720, 480, 8, 16}, - { 720, 576, 8, 16}, - {1280, 960, 8, 16}, - { 800, 480, 8, 16}, - {1024, 576, 8, 16}, - {1280, 720, 8, 16}, - { 856, 480, 8, 16}, - {1280, 768, 8, 16}, - {1400, 1050, 8, 16}, - {1152, 864, 8, 16} -}; - -const struct SiS_VCLKData XGI_VCLKData[] = { - /* SR2B,SR2C,SR2D */ - {0x1B, 0xE1, 25}, /* 00 (25.175MHz) */ - {0x4E, 0xE4, 28}, /* 01 (28.322MHz) */ - {0x57, 0xE4, 31}, /* 02 (31.500MHz) */ - {0xC3, 0xC8, 36}, /* 03 (36.000MHz) */ - {0x42, 0xE2, 40}, /* 04 (40.000MHz) */ - {0xFE, 0xCD, 43}, /* 05 (43.163MHz) */ - {0x5D, 0xC4, 44}, /* 06 (44.900MHz) */ - {0x52, 0xE2, 49}, /* 07 (49.500MHz) */ - {0x53, 0xE2, 50}, /* 08 (50.000MHz) */ - {0x74, 0x67, 52}, /* 09 (52.406MHz) */ - {0x6D, 0x66, 56}, /* 0A (56.250MHz) */ - {0x6C, 0xC3, 65}, /* 0B (65.000MHz) */ - {0x46, 0x44, 67}, /* 0C (67.765MHz) */ - {0xB1, 0x46, 68}, /* 0D (68.179MHz) */ - {0xD3, 0x4A, 72}, /* 0E (72.852MHz) */ - {0x29, 0x61, 75}, /* 0F (75.000MHz) */ - {0x6E, 0x46, 76}, /* 10 (75.800MHz) */ - {0x2B, 0x61, 78}, /* 11 (78.750MHz) */ - {0x31, 0x42, 79}, /* 12 (79.411MHz) */ - {0xAB, 0x44, 83}, /* 13 (83.950MHz) */ - {0x46, 0x25, 84}, /* 14 (84.800MHz) */ - {0x78, 0x29, 86}, /* 15 (86.600MHz) */ - {0x62, 0x44, 94}, /* 16 (94.500MHz) */ - {0x2B, 0x41, 104}, /* 17 (104.998MHz) */ - {0x3A, 0x23, 105}, /* 18 (105.882MHz) */ - {0x70, 0x44, 108}, /* 19 (107.862MHz) */ - {0x3C, 0x23, 109}, /* 1A (109.175MHz) */ - {0x5E, 0x43, 113}, /* 1B (113.309MHz) */ - {0xBC, 0x44, 116}, /* 1C (116.406MHz) */ - {0xE0, 0x46, 132}, /* 1D (132.258MHz) */ - {0x54, 0x42, 135}, /* 1E (135.500MHz) */ - {0x9C, 0x22, 139}, /* 1F (139.275MHz) */ - {0x41, 0x22, 157}, /* 20 (157.500MHz) */ - {0x70, 0x24, 162}, /* 21 (161.793MHz) */ - {0x30, 0x21, 175}, /* 22 (175.000MHz) */ - {0x4E, 0x22, 189}, /* 23 (188.520MHz) */ - {0xDE, 0x26, 194}, /* 24 (194.400MHz) */ - {0x62, 0x06, 202}, /* 25 (202.500MHz) */ - {0x3F, 0x03, 229}, /* 26 (229.500MHz) */ - {0xB8, 0x06, 234}, /* 27 (233.178MHz) */ - {0x34, 0x02, 253}, /* 28 (252.699MHz) */ - {0x58, 0x04, 255}, /* 29 (254.817MHz) */ - {0x24, 0x01, 265}, /* 2A (265.728MHz) */ - {0x9B, 0x02, 267}, /* 2B (266.952MHz) */ - {0x70, 0x05, 270}, /* 2C (269.65567MHz) */ - {0x25, 0x01, 272}, /* 2D (272.04199MHz) */ - {0x9C, 0x02, 277}, /* 2E (277.015MHz) */ - {0x27, 0x01, 286}, /* 2F (286.359985MHz) */ - {0xB3, 0x04, 291}, /* 30 (291.13266MHz) */ - {0xBC, 0x05, 292}, /* 31 (291.766MHz) */ - {0xF6, 0x0A, 310}, /* 32 (309.789459MHz) */ - {0x95, 0x01, 315}, /* 33 (315.195MHz) */ - {0xF0, 0x09, 324}, /* 34 (323.586792MHz) */ - {0xFE, 0x0A, 331}, /* 35 (330.615631MHz) */ - {0xF3, 0x09, 332}, /* 36 (332.177612MHz) */ - {0x5E, 0x03, 340}, /* 37 (340.477MHz) */ - {0xE8, 0x07, 376}, /* 38 (375.847504MHz) */ - {0xDE, 0x06, 389}, /* 39 (388.631439MHz) */ - {0x52, 0x2A, 54}, /* 3A (54.000MHz) */ - {0x52, 0x6A, 27}, /* 3B (27.000MHz) */ - {0x62, 0x24, 70}, /* 3C (70.874991MHz) */ - {0x62, 0x64, 70}, /* 3D (70.1048912MHz) */ - {0xA8, 0x4C, 30}, /* 3E (30.1048912MHz) */ - {0x20, 0x26, 33}, /* 3F (33.7499957MHz) */ - {0x31, 0xc2, 39}, /* 40 (39.77MHz) */ - {0x11, 0x21, 30}, /* 41 (30MHz) }// NTSC 1024X768 */ - {0x2E, 0x48, 25}, /* 42 (25.175MHz) }// ScaleLCD */ - {0x24, 0x46, 25}, /* 43 (25.175MHz) */ - {0x26, 0x64, 28}, /* 44 (28.322MHz) */ - {0x37, 0x64, 40}, /* 45 (40.000MHz) */ - {0xA1, 0x42, 108}, /* 46 (95.000MHz) }// QVGA */ - {0x37, 0x61, 100}, /* 47 (100.00MHz) */ - {0x78, 0x27, 108}, /* 48 (108.200MHz) */ - {0xBF, 0xC8, 35}, /* 49 (35.2MHz) */ - {0x66, 0x43, 123}, /* 4A (122.61Mhz) */ - {0x2C, 0x61, 80}, /* 4B (80.350Mhz) */ - {0x3B, 0x61, 108}, /* 4C (107.385Mhz) */ - {0x69, 0x61, 191}, /* 4D (190.96MHz ) */ - {0x4F, 0x22, 192}, /* 4E (192.069MHz) */ - {0x28, 0x26, 322}, /* 4F (322.273MHz) */ - {0x5C, 0x6B, 27}, /* 50 (27.74HMz) */ - {0x57, 0x24, 126}, /* 51 (125.999MHz) */ - {0x5C, 0x42, 148}, /* 52 (148.5MHz) */ - {0x42, 0x61, 120}, /* 53 (120.839MHz) */ - {0x62, 0x61, 178}, /* 54 (178.992MHz) */ - {0x59, 0x22, 217}, /* 55 (217.325MHz) */ - {0x29, 0x01, 300}, /* 56 (299.505Mhz) */ - {0x52, 0x63, 74}, /* 57 (74.25MHz) */ - {0xFF, 0x00, 0} /* End mark */ -}; - -static const struct SiS_VBVCLKData XGI_VBVCLKData[] = { - {0x1B, 0xE1, 25}, /* 00 (25.175MHz) */ - {0x4E, 0xE4, 28}, /* 01 (28.322MHz) */ - {0x57, 0xE4, 31}, /* 02 (31.500MHz) */ - {0xC3, 0xC8, 36}, /* 03 (36.000MHz) */ - {0x42, 0x47, 40}, /* 04 (40.000MHz) */ - {0xFE, 0xCD, 43}, /* 05 (43.163MHz) */ - {0x5D, 0xC4, 44}, /* 06 (44.900MHz) */ - {0x52, 0x47, 49}, /* 07 (49.500MHz) */ - {0x53, 0x47, 50}, /* 08 (50.000MHz) */ - {0x74, 0x67, 52}, /* 09 (52.406MHz) */ - {0x6D, 0x66, 56}, /* 0A (56.250MHz) */ - {0x35, 0x62, 65}, /* 0B (65.000MHz) */ - {0x46, 0x44, 67}, /* 0C (67.765MHz) */ - {0xB1, 0x46, 68}, /* 0D (68.179MHz) */ - {0xD3, 0x4A, 72}, /* 0E (72.852MHz) */ - {0x29, 0x61, 75}, /* 0F (75.000MHz) */ - {0x6D, 0x46, 75}, /* 10 (75.800MHz) */ - {0x41, 0x43, 78}, /* 11 (78.750MHz) */ - {0x31, 0x42, 79}, /* 12 (79.411MHz) */ - {0xAB, 0x44, 83}, /* 13 (83.950MHz) */ - {0x46, 0x25, 84}, /* 14 (84.800MHz) */ - {0x78, 0x29, 86}, /* 15 (86.600MHz) */ - {0x62, 0x44, 94}, /* 16 (94.500MHz) */ - {0x2B, 0x22, 104}, /* 17 (104.998MHz) */ - {0x49, 0x24, 105}, /* 18 (105.882MHz) */ - {0xF8, 0x2F, 108}, /* 19 (108.279MHz) */ - {0x3C, 0x23, 109}, /* 1A (109.175MHz) */ - {0x5E, 0x43, 113}, /* 1B (113.309MHz) */ - {0xBC, 0x44, 116}, /* 1C (116.406MHz) */ - {0xE0, 0x46, 132}, /* 1D (132.258MHz) */ - {0xD4, 0x28, 135}, /* 1E (135.220MHz) */ - {0xEA, 0x2A, 139}, /* 1F (139.275MHz) */ - {0x41, 0x22, 157}, /* 20 (157.500MHz) */ - {0x70, 0x24, 162}, /* 21 (161.793MHz) */ - {0x30, 0x21, 175}, /* 22 (175.000MHz) */ - {0x4E, 0x22, 189}, /* 23 (188.520MHz) */ - {0xDE, 0x26, 194}, /* 24 (194.400MHz) */ - {0x70, 0x07, 202}, /* 25 (202.500MHz) */ - {0x3F, 0x03, 229}, /* 26 (229.500MHz) */ - {0xB8, 0x06, 234}, /* 27 (233.178MHz) */ - {0x34, 0x02, 253}, /* 28 (252.699997 MHz) */ - {0x58, 0x04, 255}, /* 29 (254.817MHz) */ - {0x24, 0x01, 265}, /* 2A (265.728MHz) */ - {0x9B, 0x02, 267}, /* 2B (266.952MHz) */ - {0x70, 0x05, 270}, /* 2C (269.65567 MHz) */ - {0x25, 0x01, 272}, /* 2D (272.041992 MHz) */ - {0x9C, 0x02, 277}, /* 2E (277.015MHz) */ - {0x27, 0x01, 286}, /* 2F (286.359985 MHz) */ - {0x3C, 0x02, 291}, /* 30 (291.132660 MHz) */ - {0xEF, 0x0A, 292}, /* 31 (291.766MHz) */ - {0xF6, 0x0A, 310}, /* 32 (309.789459 MHz) */ - {0x95, 0x01, 315}, /* 33 (315.195MHz) */ - {0xF0, 0x09, 324}, /* 34 (323.586792 MHz) */ - {0xFE, 0x0A, 331}, /* 35 (330.615631 MHz) */ - {0xF3, 0x09, 332}, /* 36 (332.177612 MHz) */ - {0xEA, 0x08, 340}, /* 37 (340.477MHz) */ - {0xE8, 0x07, 376}, /* 38 (375.847504 MHz) */ - {0xDE, 0x06, 389}, /* 39 (388.631439 MHz) */ - {0x52, 0x2A, 54}, /* 3A (54.000MHz) */ - {0x52, 0x6A, 27}, /* 3B (27.000MHz) */ - {0x62, 0x24, 70}, /* 3C (70.874991MHz) */ - {0x62, 0x64, 70}, /* 3D (70.1048912MHz) */ - {0xA8, 0x4C, 30}, /* 3E (30.1048912MHz) */ - {0x20, 0x26, 33}, /* 3F (33.7499957MHz) */ - {0x31, 0xc2, 39}, /* 40 (39.77MHz) */ - {0x11, 0x21, 30}, /* 41 (30MHz) }// NTSC 1024X768 */ - {0x2E, 0x48, 25}, /* 42 (25.175MHz) }// ScaleLCD */ - {0x24, 0x46, 25}, /* 43 (25.175MHz) */ - {0x26, 0x64, 28}, /* 44 (28.322MHz) */ - {0x37, 0x64, 40}, /* 45 (40.000MHz) */ - {0xA1, 0x42, 108}, /* 46 (95.000MHz) }// QVGA */ - {0x37, 0x61, 100}, /* 47 (100.00MHz) */ - {0x78, 0x27, 108}, /* 48 (108.200MHz) */ - {0xBF, 0xC8, 35 }, /* 49 (35.2MHz) */ - {0x66, 0x43, 123}, /* 4A (122.61Mhz) */ - {0x2C, 0x61, 80 }, /* 4B (80.350Mhz) */ - {0x3B, 0x61, 108}, /* 4C (107.385Mhz) */ - {0x69, 0x61, 191}, /* 4D (190.96MHz ) */ - {0x4F, 0x22, 192}, /* 4E (192.069MHz) */ - {0x28, 0x26, 322}, /* 4F (322.273MHz) */ - {0x5C, 0x6B, 27}, /* 50 (27.74HMz) */ - {0x57, 0x24, 126}, /* 51 (125.999MHz) */ - {0x5C, 0x42, 148}, /* 52 (148.5MHz) */ - {0x42, 0x61, 120}, /* 53 (120.839MHz) */ - {0x62, 0x61, 178}, /* 54 (178.992MHz) */ - {0x59, 0x22, 217}, /* 55 (217.325MHz) */ - {0x29, 0x01, 300}, /* 56 (299.505Mhz) */ - {0x52, 0x63, 74}, /* 57 (74.25MHz) */ - {0xFF, 0x00, 0} /* End mark */ -}; - -#define XGI301TVDelay 0x22 -#define XGI301LCDDelay 0x12 - -static const unsigned char TVAntiFlickList[] = {/* NTSCAntiFlicker */ - 0x04, /* ; 0 Adaptive */ - 0x00, /* ; 1 new anti-flicker ? */ - - 0x04, /* ; 0 Adaptive */ - 0x08, /* ; 1 new anti-flicker ? */ - - 0x04, /* ; 0 ? */ - 0x00 /* ; 1 new anti-flicker ? */ -}; - - -static const unsigned char TVEdgeList[] = { - 0x00, /* ; 0 NTSC No Edge enhance */ - 0x04, /* ; 1 NTSC Adaptive Edge enhance */ - 0x00, /* ; 0 PAL No Edge enhance */ - 0x04, /* ; 1 PAL Adaptive Edge enhance */ - 0x00, /* ; 0 HiTV */ - 0x00 /* ; 1 HiTV */ -}; - -static const unsigned long TVPhaseList[] = { - 0x08BAED21, /* ; 0 NTSC phase */ - 0x00E3052A, /* ; 1 PAL phase */ - 0x9B2EE421, /* ; 2 PAL-M phase */ - 0xBA3EF421, /* ; 3 PAL-N phase */ - 0xA7A28B1E, /* ; 4 NTSC 1024x768 */ - 0xE00A831E, /* ; 5 PAL-M 1024x768 */ - 0x00000000, /* ; 6 reserved */ - 0x00000000, /* ; 7 reserved */ - 0xD67BF021, /* ; 8 NTSC phase */ - 0xE986092A, /* ; 9 PAL phase */ - 0xA4EFE621, /* ; A PAL-M phase */ - 0x4694F621, /* ; B PAL-N phase */ - 0x8BDE711C, /* ; C NTSC 1024x768 */ - 0xE00A831E /* ; D PAL-M 1024x768 */ -}; - -static const unsigned char NTSCYFilter1[] = { - 0x00, 0xF4, 0x10, 0x38, /* 0 : 320x text mode */ - 0x00, 0xF4, 0x10, 0x38, /* 1 : 360x text mode */ - 0xEB, 0x04, 0x25, 0x18, /* 2 : 640x text mode */ - 0xF1, 0x04, 0x1F, 0x18, /* 3 : 720x text mode */ - 0x00, 0xF4, 0x10, 0x38, /* 4 : 320x gra. mode */ - 0xEB, 0x04, 0x25, 0x18, /* 5 : 640x gra. mode */ - 0xEB, 0x15, 0x25, 0xF6 /* 6 : 800x gra. mode */ -}; - -static const unsigned char PALYFilter1[] = { - 0x00, 0xF4, 0x10, 0x38, /* 0 : 320x text mode */ - 0x00, 0xF4, 0x10, 0x38, /* 1 : 360x text mode */ - 0xF1, 0xF7, 0x1F, 0x32, /* 2 : 640x text mode */ - 0xF3, 0x00, 0x1D, 0x20, /* 3 : 720x text mode */ - 0x00, 0xF4, 0x10, 0x38, /* 4 : 320x gra. mode */ - 0xF1, 0xF7, 0x1F, 0x32, /* 5 : 640x gra. mode */ - 0xFC, 0xFB, 0x14, 0x2A /* 6 : 800x gra. mode */ -}; - -static const unsigned char xgifb_palmn_yfilter1[] = { - 0x00, 0xF4, 0x10, 0x38, /* 0 : 320x text mode */ - 0x00, 0xF4, 0x10, 0x38, /* 1 : 360x text mode */ - 0xEB, 0x04, 0x10, 0x18, /* 2 : 640x text mode */ - 0xF7, 0x06, 0x19, 0x14, /* 3 : 720x text mode */ - 0x00, 0xF4, 0x10, 0x38, /* 4 : 320x gra. mode */ - 0xEB, 0x04, 0x25, 0x18, /* 5 : 640x gra. mode */ - 0xEB, 0x15, 0x25, 0xF6, /* 6 : 800x gra. mode */ - 0xFF, 0xFF, 0xFF, 0xFF /* End of Table */ -}; - -static const unsigned char xgifb_yfilter2[] = { - 0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46, /* 0 : 320x text mode */ - 0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C, /* 1 : 360x text mode */ - 0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46, /* 2 : 640x text mode */ - 0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C, /* 3 : 720x text mode */ - 0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46, /* 4 : 320x gra. mode */ - 0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46, /* 5 : 640x gra. mode */ - 0x01, 0x01, 0xFC, 0xF8, 0x08, 0x26, 0x38, /* 6 : 800x gra. mode */ - 0xFF, 0xFF, 0xFC, 0x00, 0x0F, 0x22, 0x28 /* 7 : 1024xgra. mode */ -}; - -static const unsigned char XGI_NTSC1024AdjTime[] = { - 0xa7, 0x07, 0xf2, 0x6e, 0x17, 0x8b, 0x73, 0x53, - 0x13, 0x40, 0x34, 0xF4, 0x63, 0xBB, 0xCC, 0x7A, - 0x58, 0xe4, 0x73, 0xd0, 0x13 -}; - -static const struct XGI301C_Tap4TimingStruct xgifb_tap4_timing[] = { - {0, { - 0x00, 0x20, 0x00, 0x00, 0x7F, 0x20, 0x02, 0x7F, /* ; C0-C7 */ - 0x7D, 0x20, 0x04, 0x7F, 0x7D, 0x1F, 0x06, 0x7E, /* ; C8-CF */ - 0x7C, 0x1D, 0x09, 0x7E, 0x7C, 0x1B, 0x0B, 0x7E, /* ; D0-D7 */ - 0x7C, 0x19, 0x0E, 0x7D, 0x7C, 0x17, 0x11, 0x7C, /* ; D8-DF */ - 0x7C, 0x14, 0x14, 0x7C, 0x7C, 0x11, 0x17, 0x7C, /* ; E0-E7 */ - 0x7D, 0x0E, 0x19, 0x7C, 0x7E, 0x0B, 0x1B, 0x7C, /* ; EA-EF */ - 0x7E, 0x09, 0x1D, 0x7C, 0x7F, 0x06, 0x1F, 0x7C, /* ; F0-F7 */ - 0x7F, 0x04, 0x20, 0x7D, 0x00, 0x02, 0x20, 0x7E /* ; F8-FF */ - } - } -}; - -static const struct XGI301C_Tap4TimingStruct PALTap4Timing[] = { - {600, { - 0x05, 0x19, 0x05, 0x7D, 0x03, 0x19, 0x06, 0x7E, /* ; C0-C7 */ - 0x02, 0x19, 0x08, 0x7D, 0x01, 0x18, 0x0A, 0x7D, /* ; C8-CF */ - 0x00, 0x18, 0x0C, 0x7C, 0x7F, 0x17, 0x0E, 0x7C, /* ; D0-D7 */ - 0x7E, 0x16, 0x0F, 0x7D, 0x7E, 0x14, 0x11, 0x7D, /* ; D8-DF */ - 0x7D, 0x13, 0x13, 0x7D, 0x7D, 0x11, 0x14, 0x7E, /* ; E0-E7 */ - 0x7D, 0x0F, 0x16, 0x7E, 0x7D, 0x0E, 0x17, 0x7E, /* ; EA-EF */ - 0x7D, 0x0C, 0x18, 0x7F, 0x7D, 0x0A, 0x18, 0x01, /* ; F0-F7 */ - 0x7D, 0x08, 0x19, 0x02, 0x7D, 0x06, 0x19, 0x04 /* ; F8-FF */ - } - }, - {768, { - 0x08, 0x12, 0x08, 0x7E, 0x07, 0x12, 0x09, 0x7E, /* ; C0-C7 */ - 0x06, 0x12, 0x0A, 0x7E, 0x05, 0x11, 0x0B, 0x7F, /* ; C8-CF */ - 0x04, 0x11, 0x0C, 0x7F, 0x03, 0x11, 0x0C, 0x00, /* ; D0-D7 */ - 0x03, 0x10, 0x0D, 0x00, 0x02, 0x0F, 0x0E, 0x01, /* ; D8-DF */ - 0x01, 0x0F, 0x0F, 0x01, 0x01, 0x0E, 0x0F, 0x02, /* ; E0-E7 */ - 0x00, 0x0D, 0x10, 0x03, 0x7F, 0x0C, 0x11, 0x04, /* ; EA-EF */ - 0x7F, 0x0C, 0x11, 0x04, 0x7F, 0x0B, 0x11, 0x05, /* ; F0-F7 */ - 0x7E, 0x0A, 0x12, 0x06, 0x7E, 0x09, 0x12, 0x07 /* ; F8-FF */ - } - }, - {0xFFFF, { - 0x04, 0x1A, 0x04, 0x7E, 0x02, 0x1B, 0x05, 0x7E, /* ; C0-C7 */ - 0x01, 0x1A, 0x07, 0x7E, 0x00, 0x1A, 0x09, 0x7D, /* ; C8-CF */ - 0x7F, 0x19, 0x0B, 0x7D, 0x7E, 0x18, 0x0D, 0x7D, /* ; D0-D7 */ - 0x7D, 0x17, 0x10, 0x7C, 0x7D, 0x15, 0x12, 0x7C, /* ; D8-DF */ - 0x7C, 0x14, 0x14, 0x7C, 0x7C, 0x12, 0x15, 0x7D, /* ; E0-E7 */ - 0x7C, 0x10, 0x17, 0x7D, 0x7C, 0x0D, 0x18, 0x7F, /* ; EA-EF */ - 0x7D, 0x0B, 0x19, 0x7F, 0x7D, 0x09, 0x1A, 0x00, /* ; F0-F7 */ - 0x7D, 0x07, 0x1A, 0x02, 0x7E, 0x05, 0x1B, 0x02 /* ; F8-FF */ - } - } -}; - -static const struct XGI301C_Tap4TimingStruct xgifb_ntsc_525_tap4_timing[] = { - {480, { - 0x04, 0x1A, 0x04, 0x7E, 0x03, 0x1A, 0x06, 0x7D, /* ; C0-C7 */ - 0x01, 0x1A, 0x08, 0x7D, 0x00, 0x19, 0x0A, 0x7D, /* ; C8-CF */ - 0x7F, 0x19, 0x0C, 0x7C, 0x7E, 0x18, 0x0E, 0x7C, /* ; D0-D7 */ - 0x7E, 0x17, 0x10, 0x7B, 0x7D, 0x15, 0x12, 0x7C, /* ; D8-DF */ - 0x7D, 0x13, 0x13, 0x7D, 0x7C, 0x12, 0x15, 0x7D, /* ; E0-E7 */ - 0x7C, 0x10, 0x17, 0x7D, 0x7C, 0x0E, 0x18, 0x7E, /* ; EA-EF */ - 0x7D, 0x0C, 0x19, 0x7E, 0x7D, 0x0A, 0x19, 0x00, /* ; F0-F7 */ - 0x7D, 0x08, 0x1A, 0x01, 0x7E, 0x06, 0x1A, 0x02 /* ; F8-FF */ - } - }, - {600, { - 0x07, 0x14, 0x07, 0x7E, 0x06, 0x14, 0x09, 0x7D, /* ; C0-C7 */ - 0x05, 0x14, 0x0A, 0x7D, 0x04, 0x13, 0x0B, 0x7E, /* ; C8-CF */ - 0x03, 0x13, 0x0C, 0x7E, 0x02, 0x12, 0x0D, 0x7F, /* ; D0-D7 */ - 0x01, 0x12, 0x0E, 0x7F, 0x01, 0x11, 0x0F, 0x7F, /* ; D8-DF */ - 0x01, 0x10, 0x10, 0x00, 0x7F, 0x0F, 0x11, 0x01, /* ; E0-E7 */ - 0x7F, 0x0E, 0x12, 0x01, 0x7E, 0x0D, 0x12, 0x03, /* ; EA-EF */ - 0x7E, 0x0C, 0x13, 0x03, 0x7E, 0x0B, 0x13, 0x04, /* ; F0-F7 */ - 0x7E, 0x0A, 0x14, 0x04, 0x7D, 0x09, 0x14, 0x06 /* ; F8-FF */ - } - }, - {0xFFFF, { - 0x09, 0x0F, 0x09, 0x7F, 0x08, 0x0F, 0x09, 0x00, /* ; C0-C7 */ - 0x07, 0x0F, 0x0A, 0x00, 0x06, 0x0F, 0x0A, 0x01, /* ; C8-CF */ - 0x06, 0x0E, 0x0B, 0x01, 0x05, 0x0E, 0x0B, 0x02, /* ; D0-D7 */ - 0x04, 0x0E, 0x0C, 0x02, 0x04, 0x0D, 0x0C, 0x03, /* ; D8-DF */ - 0x03, 0x0D, 0x0D, 0x03, 0x02, 0x0C, 0x0D, 0x05, /* ; E0-E7 */ - 0x02, 0x0C, 0x0E, 0x04, 0x01, 0x0B, 0x0E, 0x06, /* ; EA-EF */ - 0x01, 0x0B, 0x0E, 0x06, 0x00, 0x0A, 0x0F, 0x07, /* ; F0-F7 */ - 0x00, 0x0A, 0x0F, 0x07, 0x00, 0x09, 0x0F, 0x08 /* ; F8-FF */ - } - } -}; - -static const struct XGI301C_Tap4TimingStruct YPbPr750pTap4Timing[] = { - {0xFFFF, { - 0x05, 0x19, 0x05, 0x7D, 0x03, 0x19, 0x06, 0x7E, /* ; C0-C7 */ - 0x02, 0x19, 0x08, 0x7D, 0x01, 0x18, 0x0A, 0x7D, /* ; C8-CF */ - 0x00, 0x18, 0x0C, 0x7C, 0x7F, 0x17, 0x0E, 0x7C, /* ; D0-D7 */ - 0x7E, 0x16, 0x0F, 0x7D, 0x7E, 0x14, 0x11, 0x7D, /* ; D8-DF */ - 0x7D, 0x13, 0x13, 0x7D, 0x7D, 0x11, 0x14, 0x7E, /* ; E0-E7 */ - 0x7D, 0x0F, 0x16, 0x7E, 0x7D, 0x0E, 0x17, 0x7E, /* ; EA-EF */ - 0x7D, 0x0C, 0x18, 0x7F, 0x7D, 0x0A, 0x18, 0x01, /* ; F0-F7 */ - 0x7D, 0x08, 0x19, 0x02, 0x7D, 0x06, 0x19, 0x04 /* F8-FF */ - } - } -}; -#endif diff --git a/src/drivers/xgi/common/vb_util.c b/src/drivers/xgi/common/vb_util.c deleted file mode 100644 index d88f329e5a..0000000000 --- a/src/drivers/xgi/common/vb_util.c +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* File taken from the Linux xgifb driver (v3.18.5) */ - -#include "xgi_coreboot.h" -#include "vgatypes.h" -#include "vb_util.h" - -void xgifb_reg_set(unsigned long port, u8 index, u8 data) -{ - outb(index, port); - outb(data, port + 1); -} - -u8 xgifb_reg_get(unsigned long port, u8 index) -{ - u8 data; - - outb(index, port); - data = inb(port + 1); - return data; -} - -void xgifb_reg_and_or(unsigned long port, u8 index, - unsigned int data_and, unsigned int data_or) -{ - u8 temp; - - temp = xgifb_reg_get(port, index); /* XGINew_Part1Port index 02 */ - temp = (temp & data_and) | data_or; - xgifb_reg_set(port, index, temp); -} - -void xgifb_reg_and(unsigned long port, u8 index, unsigned int data_and) -{ - u8 temp; - - temp = xgifb_reg_get(port, index); /* XGINew_Part1Port index 02 */ - temp &= data_and; - xgifb_reg_set(port, index, temp); -} - -void xgifb_reg_or(unsigned long port, u8 index, unsigned int data_or) -{ - u8 temp; - - temp = xgifb_reg_get(port, index); /* XGINew_Part1Port index 02 */ - temp |= data_or; - xgifb_reg_set(port, index, temp); -} diff --git a/src/drivers/xgi/common/vb_util.h b/src/drivers/xgi/common/vb_util.h deleted file mode 100644 index d6d2bcafa8..0000000000 --- a/src/drivers/xgi/common/vb_util.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* File taken from the Linux xgifb driver (v3.18.5) */ - -#ifndef _VBUTIL_ -#define _VBUTIL_ -extern void xgifb_reg_set(unsigned long, u8, u8); -extern u8 xgifb_reg_get(unsigned long, u8); -extern void xgifb_reg_or(unsigned long, u8, unsigned int); -extern void xgifb_reg_and(unsigned long, u8, unsigned int); -extern void xgifb_reg_and_or(unsigned long, u8, unsigned int, unsigned int); -#endif diff --git a/src/drivers/xgi/common/vgatypes.h b/src/drivers/xgi/common/vgatypes.h deleted file mode 100644 index 4be2c65c9a..0000000000 --- a/src/drivers/xgi/common/vgatypes.h +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* File taken from the Linux xgifb driver (v3.18.5) */ - -#ifndef _VGATYPES_ -#define _VGATYPES_ - -enum XGI_VB_CHIP_TYPE { - VB_CHIP_Legacy = 0, - VB_CHIP_301, - VB_CHIP_301B, - VB_CHIP_301LV, - VB_CHIP_302, - VB_CHIP_302B, - VB_CHIP_302LV, - VB_CHIP_301C, - VB_CHIP_302ELV, - VB_CHIP_UNKNOWN, /* other video bridge or no video bridge */ - MAX_VB_CHIP -}; - -struct xgi_hw_device_info { - unsigned long ulExternalChip; /* NO VB or other video bridge*/ - /* if ujVBChipID = VB_CHIP_UNKNOWN, */ - - void __iomem *pjVideoMemoryAddress;/* base virtual memory address */ - /* of Linear VGA memory */ - - unsigned long ulVideoMemorySize; /* size, in bytes, of the - memory on the board */ - - unsigned char jChipType; /* Used to Identify Graphics Chip */ - /* defined in the data structure type */ - /* "XGI_CHIP_TYPE" */ - - unsigned char jChipRevision; /* Used to Identify Graphics - Chip Revision */ - - unsigned char ujVBChipID; /* the ID of video bridge */ - /* defined in the data structure type */ - /* "XGI_VB_CHIP_TYPE" */ - - unsigned long ulCRT2LCDType; /* defined in the data structure type */ -}; - -/* Additional IOCTL for communication xgifb <> X driver */ -/* If changing this, xgifb.h must also be changed (for xgifb) */ -#endif diff --git a/src/drivers/xgi/common/vstruct.h b/src/drivers/xgi/common/vstruct.h deleted file mode 100644 index 3e530a2431..0000000000 --- a/src/drivers/xgi/common/vstruct.h +++ /dev/null @@ -1,546 +0,0 @@ -/* $XFree86$ */ -/* $XdotOrg$ */ -/* - * General structure definitions for universal mode switching modules - * - * Copyright (C) 2001-2005 by Thomas Winischhofer, Vienna, Austria - * - * If distributed as part of the Linux kernel, the following license terms - * apply: - * - * * This program is free software; you can redistribute it and/or modify - * * it under the terms of the GNU General Public License as published by - * * the Free Software Foundation; either version 2 of the named License, - * * or any later version. - * * - * * This program is distributed in the hope that it will be useful, - * * but WITHOUT ANY WARRANTY; without even the implied warranty of - * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * * GNU General Public License for more details. - * - * Otherwise, the following license terms apply: - * - * * Redistribution and use in source and binary forms, with or without - * * modification, are permitted provided that the following conditions - * * are met: - * * 1) Redistributions of source code must retain the above copyright - * * notice, this list of conditions and the following disclaimer. - * * 2) Redistributions in binary form must reproduce the above copyright - * * notice, this list of conditions and the following disclaimer in the - * * documentation and/or other materials provided with the distribution. - * * 3) The name of the author may not be used to endorse or promote products - * * derived from this software without specific prior written permission. - * * - * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Author: Thomas Winischhofer - * - */ - -#ifndef _VSTRUCT_H_ -#define _VSTRUCT_H_ - -struct SiS_PanelDelayTbl { - unsigned char timer[2]; -}; - -struct SiS_LCDData { - unsigned short RVBHCMAX; - unsigned short RVBHCFACT; - unsigned short VGAHT; - unsigned short VGAVT; - unsigned short LCDHT; - unsigned short LCDVT; -}; - -struct SiS_TVData { - unsigned short RVBHCMAX; - unsigned short RVBHCFACT; - unsigned short VGAHT; - unsigned short VGAVT; - unsigned short TVHDE; - unsigned short TVVDE; - unsigned short RVBHRS; - unsigned char FlickerMode; - unsigned short HALFRVBHRS; - unsigned short RVBHRS2; - unsigned char RY1COE; - unsigned char RY2COE; - unsigned char RY3COE; - unsigned char RY4COE; -}; - -struct SiS_LVDSData { - unsigned short VGAHT; - unsigned short VGAVT; - unsigned short LCDHT; - unsigned short LCDVT; -}; - -struct SiS_LVDSDes { - unsigned short LCDHDES; - unsigned short LCDVDES; -}; - -struct SiS_LVDSCRT1Data { - unsigned char CR[15]; -}; - -struct SiS_CHTVRegData { - unsigned char Reg[16]; -}; - -struct SiS_St { - unsigned char St_ModeID; - unsigned short St_ModeFlag; - unsigned char St_StTableIndex; - unsigned char St_CRT2CRTC; - unsigned char St_ResInfo; - unsigned char VB_StTVFlickerIndex; - unsigned char VB_StTVEdgeIndex; - unsigned char VB_StTVYFilterIndex; - unsigned char St_PDC; -}; - -struct SiS_VBMode { - unsigned char ModeID; - unsigned char VB_TVDelayIndex; - unsigned char VB_TVFlickerIndex; - unsigned char VB_TVPhaseIndex; - unsigned char VB_TVYFilterIndex; - unsigned char VB_LCDDelayIndex; - unsigned char _VB_LCDHIndex; - unsigned char _VB_LCDVIndex; -}; - -struct SiS_StandTable_S { - unsigned char CRT_COLS; - unsigned char ROWS; - unsigned char CHAR_HEIGHT; - unsigned short CRT_LEN; - unsigned char SR[4]; - unsigned char MISC; - unsigned char CRTC[0x19]; - unsigned char ATTR[0x14]; - unsigned char GRC[9]; -}; - -struct SiS_Ext { - unsigned char Ext_ModeID; - unsigned short Ext_ModeFlag; - unsigned short Ext_VESAID; - unsigned char Ext_RESINFO; - unsigned char VB_ExtTVFlickerIndex; - unsigned char VB_ExtTVEdgeIndex; - unsigned char VB_ExtTVYFilterIndex; - unsigned char VB_ExtTVYFilterIndexROM661; - unsigned char REFindex; - char ROMMODEIDX661; -}; - -struct SiS_Ext2 { - unsigned short Ext_InfoFlag; - unsigned char Ext_CRT1CRTC; - unsigned char Ext_CRTVCLK; - unsigned char Ext_CRT2CRTC; - unsigned char Ext_CRT2CRTC_NS; - unsigned char ModeID; - unsigned short XRes; - unsigned short YRes; - unsigned char Ext_PDC; - unsigned char Ext_FakeCRT2CRTC; - unsigned char Ext_FakeCRT2Clk; - unsigned char Ext_CRT1CRTC_NORM; - unsigned char Ext_CRTVCLK_NORM; - unsigned char Ext_CRT1CRTC_WIDE; - unsigned char Ext_CRTVCLK_WIDE; -}; - -struct SiS_Part2PortTbl { - unsigned char CR[12]; -}; - -struct SiS_CRT1Table { - unsigned char CR[17]; -}; - -struct SiS_MCLKData { - unsigned char SR28,SR29,SR2A; - unsigned short CLOCK; -}; - -struct SiS_VCLKData { - unsigned char SR2B,SR2C; - unsigned short CLOCK; -}; - -struct SiS_VBVCLKData { - unsigned char Part4_A,Part4_B; - unsigned short CLOCK; -}; - -struct SiS_StResInfo_S { - unsigned short HTotal; - unsigned short VTotal; -}; - -struct SiS_ModeResInfo_S { - unsigned short HTotal; - unsigned short VTotal; - unsigned char XChar; - unsigned char YChar; -}; - -/* Defines for SiS_CustomT */ -/* Never change these for sisfb compatibility */ -#define CUT_NONE 0 -#define CUT_FORCENONE 1 -#define CUT_BARCO1366 2 -#define CUT_BARCO1024 3 -#define CUT_COMPAQ1280 4 -#define CUT_COMPAQ12802 5 -#define CUT_PANEL848 6 -#define CUT_CLEVO1024 7 -#define CUT_CLEVO10242 8 -#define CUT_CLEVO1400 9 -#define CUT_CLEVO14002 10 -#define CUT_UNIWILL1024 11 -#define CUT_ASUSL3000D 12 -#define CUT_UNIWILL10242 13 -#define CUT_ACER1280 14 -#define CUT_COMPAL1400_1 15 -#define CUT_COMPAL1400_2 16 -#define CUT_ASUSA2H_1 17 -#define CUT_ASUSA2H_2 18 -#define CUT_UNKNOWNLCD 19 -#define CUT_AOP8060 20 -#define CUT_PANEL856 21 - -struct SiS_Private -{ - unsigned char ChipType; - unsigned char ChipRevision; - void *ivideo; - unsigned char *VirtualRomBase; - bool UseROM; - unsigned char SISIOMEMTYPE *VideoMemoryAddress; - unsigned int VideoMemorySize; - SISIOADDRESS IOAddress; - SISIOADDRESS IOAddress2; /* For dual chip XGI volari */ - - SISIOADDRESS RelIO; - SISIOADDRESS SiS_P3c4; - SISIOADDRESS SiS_P3d4; - SISIOADDRESS SiS_P3c0; - SISIOADDRESS SiS_P3ce; - SISIOADDRESS SiS_P3c2; - SISIOADDRESS SiS_P3ca; - SISIOADDRESS SiS_P3c6; - SISIOADDRESS SiS_P3c7; - SISIOADDRESS SiS_P3c8; - SISIOADDRESS SiS_P3c9; - SISIOADDRESS SiS_P3cb; - SISIOADDRESS SiS_P3cc; - SISIOADDRESS SiS_P3cd; - SISIOADDRESS SiS_P3da; - SISIOADDRESS SiS_Part1Port; - SISIOADDRESS SiS_Part2Port; - SISIOADDRESS SiS_Part3Port; - SISIOADDRESS SiS_Part4Port; - SISIOADDRESS SiS_Part5Port; - SISIOADDRESS SiS_VidCapt; - SISIOADDRESS SiS_VidPlay; - unsigned short SiS_IF_DEF_LVDS; - unsigned short SiS_IF_DEF_CH70xx; - unsigned short SiS_IF_DEF_CONEX; - unsigned short SiS_IF_DEF_TRUMPION; - unsigned short SiS_IF_DEF_DSTN; - unsigned short SiS_IF_DEF_FSTN; - unsigned short SiS_SysFlags; - unsigned char SiS_VGAINFO; - bool SiS_UseROM; - bool SiS_ROMNew; - bool SiS_XGIROM; - bool SiS_NeedRomModeData; - bool PanelSelfDetected; - bool DDCPortMixup; - int SiS_CHOverScan; - bool SiS_CHSOverScan; - bool SiS_ChSW; - bool SiS_UseLCDA; - int SiS_UseOEM; - unsigned int SiS_CustomT; - int SiS_UseWide, SiS_UseWideCRT2; - int SiS_TVBlue; - unsigned short SiS_Backup70xx; - bool HaveEMI; - bool HaveEMILCD; - bool OverruleEMI; - unsigned char EMI_30,EMI_31,EMI_32,EMI_33; - unsigned short SiS_EMIOffset; - unsigned short SiS_PWDOffset; - short PDC, PDCA; - unsigned char SiS_MyCR63; - unsigned short SiS_CRT1Mode; - unsigned short SiS_flag_clearbuffer; - int SiS_RAMType; - unsigned char SiS_ChannelAB; - unsigned char SiS_DataBusWidth; - unsigned short SiS_ModeType; - unsigned short SiS_VBInfo; - unsigned short SiS_TVMode; - unsigned short SiS_LCDResInfo; - unsigned short SiS_LCDTypeInfo; - unsigned short SiS_LCDInfo; - unsigned short SiS_LCDInfo661; - unsigned short SiS_VBType; - unsigned short SiS_VBExtInfo; - unsigned short SiS_YPbPr; - unsigned short SiS_SelectCRT2Rate; - unsigned short SiS_SetFlag; - unsigned short SiS_RVBHCFACT; - unsigned short SiS_RVBHCMAX; - unsigned short SiS_RVBHRS; - unsigned short SiS_RVBHRS2; - unsigned short SiS_VGAVT; - unsigned short SiS_VGAHT; - unsigned short SiS_VT; - unsigned short SiS_HT; - unsigned short SiS_VGAVDE; - unsigned short SiS_VGAHDE; - unsigned short SiS_VDE; - unsigned short SiS_HDE; - unsigned short SiS_NewFlickerMode; - unsigned short SiS_RY1COE; - unsigned short SiS_RY2COE; - unsigned short SiS_RY3COE; - unsigned short SiS_RY4COE; - unsigned short SiS_LCDHDES; - unsigned short SiS_LCDVDES; - SISIOADDRESS SiS_DDC_Port; - unsigned short SiS_DDC_Index; - unsigned short SiS_DDC_Data; - unsigned short SiS_DDC_NData; - unsigned short SiS_DDC_Clk; - unsigned short SiS_DDC_NClk; - unsigned short SiS_DDC_DeviceAddr; - unsigned short SiS_DDC_ReadAddr; - unsigned short SiS_DDC_SecAddr; - unsigned short SiS_ChrontelInit; - bool SiS_SensibleSR11; - unsigned short SiS661LCD2TableSize; - - unsigned short SiS_PanelMinLVDS; - unsigned short SiS_PanelMin301; - - const struct SiS_St *SiS_SModeIDTable; - const struct SiS_StandTable_S *SiS_StandTable; - const struct SiS_Ext *SiS_EModeIDTable; - const struct SiS_Ext2 *SiS_RefIndex; - const struct SiS_VBMode *SiS_VBModeIDTable; - const struct SiS_CRT1Table *SiS_CRT1Table; - const struct SiS_MCLKData *SiS_MCLKData_0; - const struct SiS_MCLKData *SiS_MCLKData_1; - struct SiS_VCLKData *SiS_VCLKData; - struct SiS_VBVCLKData *SiS_VBVCLKData; - const struct SiS_StResInfo_S *SiS_StResInfo; - const struct SiS_ModeResInfo_S *SiS_ModeResInfo; - - const unsigned char *pSiS_OutputSelect; - const unsigned char *pSiS_SoftSetting; - - const unsigned char *SiS_SR15; - - const struct SiS_PanelDelayTbl *SiS_PanelDelayTbl; - const struct SiS_PanelDelayTbl *SiS_PanelDelayTblLVDS; - - /* SiS bridge */ - - const struct SiS_LCDData *SiS_ExtLCD1024x768Data; - const struct SiS_LCDData *SiS_St2LCD1024x768Data; - const struct SiS_LCDData *SiS_LCD1280x720Data; - const struct SiS_LCDData *SiS_StLCD1280x768_2Data; - const struct SiS_LCDData *SiS_ExtLCD1280x768_2Data; - const struct SiS_LCDData *SiS_LCD1280x800Data; - const struct SiS_LCDData *SiS_LCD1280x800_2Data; - const struct SiS_LCDData *SiS_LCD1280x854Data; - const struct SiS_LCDData *SiS_LCD1280x960Data; - const struct SiS_LCDData *SiS_ExtLCD1280x1024Data; - const struct SiS_LCDData *SiS_St2LCD1280x1024Data; - const struct SiS_LCDData *SiS_StLCD1400x1050Data; - const struct SiS_LCDData *SiS_ExtLCD1400x1050Data; - const struct SiS_LCDData *SiS_StLCD1600x1200Data; - const struct SiS_LCDData *SiS_ExtLCD1600x1200Data; - const struct SiS_LCDData *SiS_LCD1680x1050Data; - const struct SiS_LCDData *SiS_NoScaleData; - const struct SiS_TVData *SiS_StPALData; - const struct SiS_TVData *SiS_ExtPALData; - const struct SiS_TVData *SiS_StNTSCData; - const struct SiS_TVData *SiS_ExtNTSCData; - const struct SiS_TVData *SiS_St1HiTVData; - const struct SiS_TVData *SiS_St2HiTVData; - const struct SiS_TVData *SiS_ExtHiTVData; - const struct SiS_TVData *SiS_St525iData; - const struct SiS_TVData *SiS_St525pData; - const struct SiS_TVData *SiS_St750pData; - const struct SiS_TVData *SiS_Ext525iData; - const struct SiS_TVData *SiS_Ext525pData; - const struct SiS_TVData *SiS_Ext750pData; - const unsigned char *SiS_NTSCTiming; - const unsigned char *SiS_PALTiming; - const unsigned char *SiS_HiTVExtTiming; - const unsigned char *SiS_HiTVSt1Timing; - const unsigned char *SiS_HiTVSt2Timing; - const unsigned char *SiS_HiTVGroup3Data; - const unsigned char *SiS_HiTVGroup3Simu; -#if 0 - const unsigned char *SiS_HiTVTextTiming; - const unsigned char *SiS_HiTVGroup3Text; -#endif - - const struct SiS_Part2PortTbl *SiS_CRT2Part2_1024x768_1; - const struct SiS_Part2PortTbl *SiS_CRT2Part2_1024x768_2; - const struct SiS_Part2PortTbl *SiS_CRT2Part2_1024x768_3; - - /* LVDS, Chrontel */ - - const struct SiS_LVDSData *SiS_LVDS320x240Data_1; - const struct SiS_LVDSData *SiS_LVDS320x240Data_2; - const struct SiS_LVDSData *SiS_LVDS640x480Data_1; - const struct SiS_LVDSData *SiS_LVDS800x600Data_1; - const struct SiS_LVDSData *SiS_LVDS1024x600Data_1; - const struct SiS_LVDSData *SiS_LVDS1024x768Data_1; - const struct SiS_LVDSData *SiS_LVDSBARCO1366Data_1; - const struct SiS_LVDSData *SiS_LVDSBARCO1366Data_2; - const struct SiS_LVDSData *SiS_LVDSBARCO1024Data_1; - const struct SiS_LVDSData *SiS_LVDS848x480Data_1; - const struct SiS_LVDSData *SiS_LVDS848x480Data_2; - const struct SiS_LVDSData *SiS_CHTVUNTSCData; - const struct SiS_LVDSData *SiS_CHTVONTSCData; - const struct SiS_LVDSData *SiS_CHTVUPALData; - const struct SiS_LVDSData *SiS_CHTVOPALData; - const struct SiS_LVDSData *SiS_CHTVUPALMData; - const struct SiS_LVDSData *SiS_CHTVOPALMData; - const struct SiS_LVDSData *SiS_CHTVUPALNData; - const struct SiS_LVDSData *SiS_CHTVOPALNData; - const struct SiS_LVDSData *SiS_CHTVSOPALData; - - const struct SiS_LVDSDes *SiS_PanelType04_1a; - const struct SiS_LVDSDes *SiS_PanelType04_2a; - const struct SiS_LVDSDes *SiS_PanelType04_1b; - const struct SiS_LVDSDes *SiS_PanelType04_2b; - - const struct SiS_LVDSCRT1Data *SiS_LVDSCRT1320x240_1; - const struct SiS_LVDSCRT1Data *SiS_LVDSCRT1320x240_2; - const struct SiS_LVDSCRT1Data *SiS_LVDSCRT1320x240_2_H; - const struct SiS_LVDSCRT1Data *SiS_LVDSCRT1320x240_3; - const struct SiS_LVDSCRT1Data *SiS_LVDSCRT1320x240_3_H; - const struct SiS_LVDSCRT1Data *SiS_LVDSCRT1640x480_1; - const struct SiS_LVDSCRT1Data *SiS_LVDSCRT1640x480_1_H; - const struct SiS_LVDSCRT1Data *SiS_CHTVCRT1UNTSC; - const struct SiS_LVDSCRT1Data *SiS_CHTVCRT1ONTSC; - const struct SiS_LVDSCRT1Data *SiS_CHTVCRT1UPAL; - const struct SiS_LVDSCRT1Data *SiS_CHTVCRT1OPAL; - const struct SiS_LVDSCRT1Data *SiS_CHTVCRT1SOPAL; - - const struct SiS_CHTVRegData *SiS_CHTVReg_UNTSC; - const struct SiS_CHTVRegData *SiS_CHTVReg_ONTSC; - const struct SiS_CHTVRegData *SiS_CHTVReg_UPAL; - const struct SiS_CHTVRegData *SiS_CHTVReg_OPAL; - const struct SiS_CHTVRegData *SiS_CHTVReg_UPALM; - const struct SiS_CHTVRegData *SiS_CHTVReg_OPALM; - const struct SiS_CHTVRegData *SiS_CHTVReg_UPALN; - const struct SiS_CHTVRegData *SiS_CHTVReg_OPALN; - const struct SiS_CHTVRegData *SiS_CHTVReg_SOPAL; - - const unsigned char *SiS_CHTVVCLKUNTSC; - const unsigned char *SiS_CHTVVCLKONTSC; - const unsigned char *SiS_CHTVVCLKUPAL; - const unsigned char *SiS_CHTVVCLKOPAL; - const unsigned char *SiS_CHTVVCLKUPALM; - const unsigned char *SiS_CHTVVCLKOPALM; - const unsigned char *SiS_CHTVVCLKUPALN; - const unsigned char *SiS_CHTVVCLKOPALN; - const unsigned char *SiS_CHTVVCLKSOPAL; - - unsigned short PanelXRes, PanelHT; - unsigned short PanelYRes, PanelVT; - unsigned short PanelHRS, PanelHRE; - unsigned short PanelVRS, PanelVRE; - unsigned short PanelVCLKIdx300; - unsigned short PanelVCLKIdx315; - bool Alternate1600x1200; - - bool UseCustomMode; - bool CRT1UsesCustomMode; - unsigned short CHDisplay; - unsigned short CHSyncStart; - unsigned short CHSyncEnd; - unsigned short CHTotal; - unsigned short CHBlankStart; - unsigned short CHBlankEnd; - unsigned short CVDisplay; - unsigned short CVSyncStart; - unsigned short CVSyncEnd; - unsigned short CVTotal; - unsigned short CVBlankStart; - unsigned short CVBlankEnd; - unsigned int CDClock; - unsigned int CFlags; - unsigned char CCRT1CRTC[17]; - unsigned char CSR2B; - unsigned char CSR2C; - unsigned short CSRClock; - unsigned short CSRClock_CRT1; - unsigned short CModeFlag; - unsigned short CModeFlag_CRT1; - unsigned short CInfoFlag; - - int LVDSHL; - - bool Backup; - unsigned char Backup_Mode; - unsigned char Backup_14; - unsigned char Backup_15; - unsigned char Backup_16; - unsigned char Backup_17; - unsigned char Backup_18; - unsigned char Backup_19; - unsigned char Backup_1a; - unsigned char Backup_1b; - unsigned char Backup_1c; - unsigned char Backup_1d; - - unsigned char Init_P4_0E; - - int UsePanelScaler; - int CenterScreen; - - unsigned short CP_Vendor, CP_Product; - bool CP_HaveCustomData; - int CP_PreferredX, CP_PreferredY, CP_PreferredIndex; - int CP_MaxX, CP_MaxY, CP_MaxClock; - unsigned char CP_PrefSR2B, CP_PrefSR2C; - unsigned short CP_PrefClock; - bool CP_Supports64048075; - int CP_HDisplay[7], CP_VDisplay[7]; /* For Custom LCD panel dimensions */ - int CP_HTotal[7], CP_VTotal[7]; - int CP_HSyncStart[7], CP_VSyncStart[7]; - int CP_HSyncEnd[7], CP_VSyncEnd[7]; - int CP_HBlankStart[7], CP_VBlankStart[7]; - int CP_HBlankEnd[7], CP_VBlankEnd[7]; - int CP_Clock[7]; - bool CP_DataValid[7]; - bool CP_HSync_P[7], CP_VSync_P[7], CP_SyncValid[7]; -}; - -#endif diff --git a/src/drivers/xgi/common/xgi_coreboot.c b/src/drivers/xgi/common/xgi_coreboot.c deleted file mode 100644 index 6d0dd71755..0000000000 --- a/src/drivers/xgi/common/xgi_coreboot.c +++ /dev/null @@ -1,431 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - /* Code taken from the Linux xgifb driver (v3.18.5) */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "xgi_coreboot.h" -#include "vstruct.h" -#include "XGIfb.h" -#include "XGI_main.h" -#include "vb_init.h" -#include "vb_util.h" -#include "vb_setmode.h" -#include "XGI_main.c" - -static int xgi_vbe_valid; -static struct lb_framebuffer xgi_fb; - -int xgifb_probe(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info) -{ - u8 reg, reg1; - u8 CR48, CR38; - int ret; - struct xgi_hw_device_info *hw_info; - unsigned long video_size_max; - - hw_info = &xgifb_info->hw_info; - xgifb_info->chip_id = pdev->device; - pci_read_config_byte(pdev, - PCI_REVISION_ID, - &xgifb_info->revision_id); - hw_info->jChipRevision = xgifb_info->revision_id; - - xgifb_info->subsysvendor = pdev->subsystem_vendor; - xgifb_info->subsysdevice = pdev->subsystem_device; - - video_size_max = pci_resource_len(pdev, 0); - xgifb_info->video_base = pci_resource_start(pdev, 0); - xgifb_info->mmio_base = pci_resource_start(pdev, 1); - xgifb_info->mmio_size = pci_resource_len(pdev, 1); - xgifb_info->vga_base = pci_resource_start(pdev, 2) + 0x30; - dev_info(&pdev->dev, "Relocate IO address: %Lx [%08lx]\n", - (u64) pci_resource_start(pdev, 2), - xgifb_info->vga_base); - - if (XGIfb_crt2type != -1) { - xgifb_info->display2 = XGIfb_crt2type; - xgifb_info->display2_force = true; - } - - XGIRegInit(&xgifb_info->dev_info, xgifb_info->vga_base); - - xgifb_reg_set(XGISR, IND_SIS_PASSWORD, SIS_PASSWORD); - reg1 = xgifb_reg_get(XGISR, IND_SIS_PASSWORD); - - if (reg1 != 0xa1) { - dev_err(&pdev->dev, "I/O error\n"); - ret = -5; - goto error_disable; - } - - switch (xgifb_info->chip_id) { - case PCI_DEVICE_ID_XGI_20: - xgifb_reg_or(XGICR, Index_CR_GPIO_Reg3, GPIOG_EN); - CR48 = xgifb_reg_get(XGICR, Index_CR_GPIO_Reg1); - if (CR48&GPIOG_READ) - xgifb_info->chip = XG21; - else - xgifb_info->chip = XG20; - break; - case PCI_DEVICE_ID_XGI_40: - xgifb_info->chip = XG40; - break; - case PCI_DEVICE_ID_XGI_42: - xgifb_info->chip = XG42; - break; - case PCI_DEVICE_ID_XGI_27: - xgifb_info->chip = XG27; - break; - default: - ret = -19; - goto error_disable; - } - - dev_info(&pdev->dev, "chipid = %x\n", xgifb_info->chip); - hw_info->jChipType = xgifb_info->chip; - - if (XGIfb_get_dram_size(xgifb_info)) { - xgifb_info->video_size = min_t(unsigned long, video_size_max, - SZ_16M); - } else if (xgifb_info->video_size > video_size_max) { - xgifb_info->video_size = video_size_max; - } - - if (CONFIG(LINEAR_FRAMEBUFFER)) { - /* Enable PCI_LINEAR_ADDRESSING and MMIO_ENABLE */ - xgifb_reg_or(XGISR, - IND_SIS_PCI_ADDRESS_SET, - (SIS_PCI_ADDR_ENABLE | SIS_MEM_MAP_IO_ENABLE)); - /* Enable 2D accelerator engine */ - xgifb_reg_or(XGISR, IND_SIS_MODULE_ENABLE, SIS_ENABLE_2D); - } - - hw_info->ulVideoMemorySize = xgifb_info->video_size; - - xgifb_info->video_vbase = hw_info->pjVideoMemoryAddress = - (void *)(intptr_t)xgifb_info->video_base; - xgifb_info->mmio_vbase = (void *)(intptr_t)xgifb_info->mmio_base; - - dev_info(&pdev->dev, - "Framebuffer at 0x%Lx, mapped to %p, size %dk\n", - (u64) xgifb_info->video_base, - xgifb_info->video_vbase, - xgifb_info->video_size / 1024); - - dev_info(&pdev->dev, - "MMIO at 0x%Lx, mapped to %p, size %ldk\n", - (u64) xgifb_info->mmio_base, xgifb_info->mmio_vbase, - xgifb_info->mmio_size / 1024); - - pci_set_drvdata(pdev, xgifb_info); - if (!XGIInitNew(pdev)) - dev_err(&pdev->dev, "XGIInitNew() failed!\n"); - - xgifb_info->mtrr = -1; - - xgifb_info->hasVB = HASVB_NONE; - if ((xgifb_info->chip == XG20) || - (xgifb_info->chip == XG27)) { - xgifb_info->hasVB = HASVB_NONE; - } else if (xgifb_info->chip == XG21) { - CR38 = xgifb_reg_get(XGICR, 0x38); - if ((CR38 & 0xE0) == 0xC0) - xgifb_info->display2 = XGIFB_DISP_LCD; - else if ((CR38 & 0xE0) == 0x60) - xgifb_info->hasVB = HASVB_CHRONTEL; - else - xgifb_info->hasVB = HASVB_NONE; - } else { - XGIfb_get_VB_type(xgifb_info); - } - - hw_info->ujVBChipID = VB_CHIP_UNKNOWN; - - hw_info->ulExternalChip = 0; - - switch (xgifb_info->hasVB) { - case HASVB_301: - reg = xgifb_reg_get(XGIPART4, 0x01); - if (reg >= 0xE0) { - hw_info->ujVBChipID = VB_CHIP_302LV; - dev_info(&pdev->dev, - "XGI302LV bridge detected (revision 0x%02x)\n", - reg); - } else if (reg >= 0xD0) { - hw_info->ujVBChipID = VB_CHIP_301LV; - dev_info(&pdev->dev, - "XGI301LV bridge detected (revision 0x%02x)\n", - reg); - } else { - hw_info->ujVBChipID = VB_CHIP_301; - dev_info(&pdev->dev, "XGI301 bridge detected\n"); - } - break; - case HASVB_302: - reg = xgifb_reg_get(XGIPART4, 0x01); - if (reg >= 0xE0) { - hw_info->ujVBChipID = VB_CHIP_302LV; - dev_info(&pdev->dev, - "XGI302LV bridge detected (revision 0x%02x)\n", - reg); - } else if (reg >= 0xD0) { - hw_info->ujVBChipID = VB_CHIP_301LV; - dev_info(&pdev->dev, - "XGI302LV bridge detected (revision 0x%02x)\n", - reg); - } else if (reg >= 0xB0) { - reg1 = xgifb_reg_get(XGIPART4, 0x23); - - hw_info->ujVBChipID = VB_CHIP_302B; - - } else { - hw_info->ujVBChipID = VB_CHIP_302; - dev_info(&pdev->dev, "XGI302 bridge detected\n"); - } - break; - case HASVB_LVDS: - hw_info->ulExternalChip = 0x1; - dev_info(&pdev->dev, "LVDS transmitter detected\n"); - break; - case HASVB_TRUMPION: - hw_info->ulExternalChip = 0x2; - dev_info(&pdev->dev, "Trumpion Zurac LVDS scaler detected\n"); - break; - case HASVB_CHRONTEL: - hw_info->ulExternalChip = 0x4; - dev_info(&pdev->dev, "Chrontel TV encoder detected\n"); - break; - case HASVB_LVDS_CHRONTEL: - hw_info->ulExternalChip = 0x5; - dev_info(&pdev->dev, - "LVDS transmitter and Chrontel TV encoder detected\n"); - break; - default: - dev_info(&pdev->dev, "No or unknown bridge type detected\n"); - break; - } - - if (xgifb_info->hasVB != HASVB_NONE) - XGIfb_detect_VB(xgifb_info); - else if (xgifb_info->chip != XG21) - xgifb_info->display2 = XGIFB_DISP_NONE; - - if (xgifb_info->display2 == XGIFB_DISP_LCD) { - if (!enable_dstn) { - reg = xgifb_reg_get(XGICR, IND_XGI_LCD_PANEL); - reg &= 0x0f; - hw_info->ulCRT2LCDType = XGI310paneltype[reg]; - } - } - - xgifb_info->mode_idx = -1; - - /* FIXME coreboot does not provide sscanf, needed by XGIfb_search_mode */ - /* if (mode) - XGIfb_search_mode(xgifb_info, mode); - else */if (vesa != -1) - XGIfb_search_vesamode(xgifb_info, vesa); - - if (xgifb_info->mode_idx >= 0) - xgifb_info->mode_idx = - XGIfb_validate_mode(xgifb_info, xgifb_info->mode_idx); - - if (xgifb_info->mode_idx < 0) { - if (xgifb_info->display2 == XGIFB_DISP_LCD && - xgifb_info->chip == XG21) - xgifb_info->mode_idx = - XGIfb_GetXG21DefaultLVDSModeIdx(xgifb_info); - else - if (CONFIG(LINEAR_FRAMEBUFFER)) - xgifb_info->mode_idx = DEFAULT_MODE; - else - xgifb_info->mode_idx = DEFAULT_TEXT_MODE; - } - - if (xgifb_info->mode_idx < 0) { - dev_err(&pdev->dev, "No supported video mode found\n"); - ret = -22; - goto error_1; - } - - /* set default refresh rate */ - xgifb_info->refresh_rate = refresh_rate; - if (xgifb_info->refresh_rate == 0) - xgifb_info->refresh_rate = 60; - if (XGIfb_search_refresh_rate(xgifb_info, - xgifb_info->refresh_rate) == 0) { - xgifb_info->rate_idx = 1; - xgifb_info->refresh_rate = 60; - } - - xgifb_info->video_bpp = XGIbios_mode[xgifb_info->mode_idx].bpp; - xgifb_info->video_vwidth = - xgifb_info->video_width = - XGIbios_mode[xgifb_info->mode_idx].xres; - xgifb_info->video_vheight = - xgifb_info->video_height = - XGIbios_mode[xgifb_info->mode_idx].yres; - xgifb_info->org_x = xgifb_info->org_y = 0; - xgifb_info->video_linelength = - xgifb_info->video_width * - (xgifb_info->video_bpp >> 3); - switch (xgifb_info->video_bpp) { - case 8: - xgifb_info->DstColor = 0x0000; - xgifb_info->XGI310_AccelDepth = 0x00000000; - xgifb_info->video_cmap_len = 256; - break; - case 16: - xgifb_info->DstColor = 0x8000; - xgifb_info->XGI310_AccelDepth = 0x00010000; - xgifb_info->video_cmap_len = 16; - break; - case 32: - xgifb_info->DstColor = 0xC000; - xgifb_info->XGI310_AccelDepth = 0x00020000; - xgifb_info->video_cmap_len = 16; - break; - default: - xgifb_info->video_cmap_len = 16; - pr_info("Unsupported depth %d\n", - xgifb_info->video_bpp); - break; - } - - pr_info("Default mode is %dx%dx%d (%dHz)\n", - xgifb_info->video_width, - xgifb_info->video_height, - xgifb_info->video_bpp, - xgifb_info->refresh_rate); - - return 0; - -error_1: -error_disable: - return ret; -} - -int xgifb_modeset(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info) -{ - struct xgi_hw_device_info *hw_info; - - hw_info = &xgifb_info->hw_info; - - if (CONFIG(LINEAR_FRAMEBUFFER)) { - /* Set mode */ - XGIfb_pre_setmode(xgifb_info); - if (XGISetModeNew(xgifb_info, hw_info, - XGIbios_mode[xgifb_info->mode_idx].mode_no) - == 0) { - pr_err("Setting mode[0x%x] failed\n", - XGIbios_mode[xgifb_info->mode_idx].mode_no); - return -22; - } - xgifb_info->video_linelength = - xgifb_info->video_width * - (xgifb_info->video_bpp >> 3); - - xgifb_reg_set(XGISR, IND_SIS_PASSWORD, SIS_PASSWORD); - - xgifb_reg_set(XGICR, 0x13, - (xgifb_info->video_linelength & 0x00ff)); - xgifb_reg_set(XGISR, 0x0e, - (xgifb_info->video_linelength & 0xff00) >> 8); - - XGIfb_post_setmode(xgifb_info); - - pr_debug("Set new mode: %dx%dx%d-%d\n", - XGIbios_mode[xgifb_info->mode_idx].xres, - XGIbios_mode[xgifb_info->mode_idx].yres, - XGIbios_mode[xgifb_info->mode_idx].bpp, - xgifb_info->refresh_rate); - - /* Set LinuxBIOS framebuffer information */ - xgi_vbe_valid = 1; - xgi_fb.physical_address = xgifb_info->video_base; - xgi_fb.x_resolution = xgifb_info->video_width; - xgi_fb.y_resolution = xgifb_info->video_height; - xgi_fb.bytes_per_line = - xgifb_info->video_width * xgifb_info->video_bpp; - xgi_fb.bits_per_pixel = xgifb_info->video_bpp; - - xgi_fb.reserved_mask_pos = 0; - xgi_fb.reserved_mask_size = 0; - switch (xgifb_info->video_bpp) { - case 32: - case 24: - /* packed into 4-byte words */ - xgi_fb.reserved_mask_pos = 24; - xgi_fb.reserved_mask_size = 8; - xgi_fb.red_mask_pos = 16; - xgi_fb.red_mask_size = 8; - xgi_fb.green_mask_pos = 8; - xgi_fb.green_mask_size = 8; - xgi_fb.blue_mask_pos = 0; - xgi_fb.blue_mask_size = 8; - break; - case 16: - /* packed into 2-byte words */ - xgi_fb.red_mask_pos = 11; - xgi_fb.red_mask_size = 5; - xgi_fb.green_mask_pos = 5; - xgi_fb.green_mask_size = 6; - xgi_fb.blue_mask_pos = 0; - xgi_fb.blue_mask_size = 5; - break; - default: - printk(BIOS_SPEW, "%s: unsupported BPP %d\n", __func__, - xgifb_info->video_bpp); - xgi_vbe_valid = 0; - } - } else { - /* - * FIXME - * Text mode is slightly unstable/jittery - * (bad/incomplete DDR init?) - */ - - /* Initialize standard VGA text mode */ - vga_io_init(); - vga_textmode_init(); - printk(BIOS_INFO, "XGI VGA text mode initialized\n"); - - /* if we don't have console, at least print something... */ - vga_line_write(0, "XGI VGA text mode initialized"); - } - - return 0; -} - -static int vbe_mode_info_valid(void) -{ - return xgi_vbe_valid; -} - -int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) -{ - if (!vbe_mode_info_valid()) - return -1; - - *framebuffer = xgi_fb; - - return 0; -} - -struct xgifb_video_info *xgifb_video_info_ptr; - -struct xgifb_video_info *pci_get_drvdata(struct pci_dev *pdev) { - return xgifb_video_info_ptr; -} - -void pci_set_drvdata(struct pci_dev *pdev, struct xgifb_video_info *data) { - xgifb_video_info_ptr = data; -} diff --git a/src/drivers/xgi/common/xgi_coreboot.h b/src/drivers/xgi/common/xgi_coreboot.h deleted file mode 100644 index a021539043..0000000000 --- a/src/drivers/xgi/common/xgi_coreboot.h +++ /dev/null @@ -1,264 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* Portions marked below taken from XGI/SiS Linux kernel drivers */ - -#ifndef _XGI_COREBOOT_ -#define _XGI_COREBOOT_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "initdef.h" - -/* Begin code taken from Linux kernel 3.18.5 */ - -/* For 315/Xabre series */ -#define COMMAND_QUEUE_AREA_SIZE (512 * 1024) /* 512K */ -#define COMMAND_QUEUE_AREA_SIZE_Z7 (128 * 1024) /* 128k for XGI Z7 */ -#define HW_CURSOR_AREA_SIZE_315 16384 /* 16K */ -#define COMMAND_QUEUE_THRESHOLD 0x1F - -#define SIS_OH_ALLOC_SIZE 4000 -#define SENTINEL 0x7fffffff - -#define SEQ_ADR 0x14 -#define SEQ_DATA 0x15 -#define DAC_ADR 0x18 -#define DAC_DATA 0x19 -#define CRTC_ADR 0x24 -#define CRTC_DATA 0x25 -#define DAC2_ADR (0x16-0x30) -#define DAC2_DATA (0x17-0x30) -#define VB_PART1_ADR (0x04-0x30) -#define VB_PART1_DATA (0x05-0x30) -#define VB_PART2_ADR (0x10-0x30) -#define VB_PART2_DATA (0x11-0x30) -#define VB_PART3_ADR (0x12-0x30) -#define VB_PART3_DATA (0x13-0x30) -#define VB_PART4_ADR (0x14-0x30) -#define VB_PART4_DATA (0x15-0x30) - -#define SISSR ivideo->SiS_Pr.SiS_P3c4 -#define SISCR ivideo->SiS_Pr.SiS_P3d4 -#define SISDACA ivideo->SiS_Pr.SiS_P3c8 -#define SISDACD ivideo->SiS_Pr.SiS_P3c9 -#define SISPART1 ivideo->SiS_Pr.SiS_Part1Port -#define SISPART2 ivideo->SiS_Pr.SiS_Part2Port -#define SISPART3 ivideo->SiS_Pr.SiS_Part3Port -#define SISPART4 ivideo->SiS_Pr.SiS_Part4Port -#define SISPART5 ivideo->SiS_Pr.SiS_Part5Port -#define SISDAC2A SISPART5 -#define SISDAC2D (SISPART5 + 1) -#define SISMISCR (ivideo->SiS_Pr.RelIO + 0x1c) -#define SISMISCW ivideo->SiS_Pr.SiS_P3c2 -#define SISINPSTAT (ivideo->SiS_Pr.RelIO + 0x2a) -#define SISPEL ivideo->SiS_Pr.SiS_P3c6 -#define SISVGAENABLE (ivideo->SiS_Pr.RelIO + 0x13) -#define SISVID (ivideo->SiS_Pr.RelIO + 0x02 - 0x30) -#define SISCAP (ivideo->SiS_Pr.RelIO + 0x00 - 0x30) - -#define IND_SIS_PASSWORD 0x05 /* SRs */ -#define IND_SIS_COLOR_MODE 0x06 -#define IND_SIS_RAMDAC_CONTROL 0x07 -#define IND_SIS_DRAM_SIZE 0x14 -#define IND_SIS_MODULE_ENABLE 0x1E -#define IND_SIS_PCI_ADDRESS_SET 0x20 -#define IND_SIS_TURBOQUEUE_ADR 0x26 -#define IND_SIS_TURBOQUEUE_SET 0x27 -#define IND_SIS_POWER_ON_TRAP 0x38 -#define IND_SIS_POWER_ON_TRAP2 0x39 -#define IND_SIS_CMDQUEUE_SET 0x26 -#define IND_SIS_CMDQUEUE_THRESHOLD 0x27 - -#define IND_SIS_AGP_IO_PAD 0x48 - -#define SIS_CRT2_WENABLE_300 0x24 /* Part1 */ -#define SIS_CRT2_WENABLE_315 0x2F - -#define SIS_PASSWORD 0x86 /* SR05 */ - -#define SIS_INTERLACED_MODE 0x20 /* SR06 */ -#define SIS_8BPP_COLOR_MODE 0x0 -#define SIS_15BPP_COLOR_MODE 0x1 -#define SIS_16BPP_COLOR_MODE 0x2 -#define SIS_32BPP_COLOR_MODE 0x4 - -#define SIS_ENABLE_2D 0x40 /* SR1E */ - -#define SIS_MEM_MAP_IO_ENABLE 0x01 /* SR20 */ -#define SIS_PCI_ADDR_ENABLE 0x80 - -#define SIS_AGP_CMDQUEUE_ENABLE 0x80 /* 315/330/340 series SR26 */ -#define SIS_VRAM_CMDQUEUE_ENABLE 0x40 -#define SIS_MMIO_CMD_ENABLE 0x20 -#define SIS_CMD_QUEUE_SIZE_512k 0x00 -#define SIS_CMD_QUEUE_SIZE_1M 0x04 -#define SIS_CMD_QUEUE_SIZE_2M 0x08 -#define SIS_CMD_QUEUE_SIZE_4M 0x0C -#define SIS_CMD_QUEUE_RESET 0x01 -#define SIS_CMD_AUTO_CORR 0x02 - -#define SIS_CMD_QUEUE_SIZE_Z7_64k 0x00 /* XGI Z7 */ -#define SIS_CMD_QUEUE_SIZE_Z7_128k 0x04 - -#define SIS_SIMULTANEOUS_VIEW_ENABLE 0x01 /* CR30 */ -#define SIS_MODE_SELECT_CRT2 0x02 -#define SIS_VB_OUTPUT_COMPOSITE 0x04 -#define SIS_VB_OUTPUT_SVIDEO 0x08 -#define SIS_VB_OUTPUT_SCART 0x10 -#define SIS_VB_OUTPUT_LCD 0x20 -#define SIS_VB_OUTPUT_CRT2 0x40 -#define SIS_VB_OUTPUT_HIVISION 0x80 - -#define SIS_VB_OUTPUT_DISABLE 0x20 /* CR31 */ -#define SIS_DRIVER_MODE 0x40 - -#define SIS_VB_COMPOSITE 0x01 /* CR32 */ -#define SIS_VB_SVIDEO 0x02 -#define SIS_VB_SCART 0x04 -#define SIS_VB_LCD 0x08 -#define SIS_VB_CRT2 0x10 -#define SIS_CRT1 0x20 -#define SIS_VB_HIVISION 0x40 -#define SIS_VB_YPBPR 0x80 -#define SIS_VB_TV (SIS_VB_COMPOSITE | SIS_VB_SVIDEO | \ - SIS_VB_SCART | SIS_VB_HIVISION | SIS_VB_YPBPR) - -#define SIS_EXTERNAL_CHIP_MASK 0x0E /* CR37 (< SiS 660) */ -#define SIS_EXTERNAL_CHIP_SIS301 0x01 /* in CR37 << 1 ! */ -#define SIS_EXTERNAL_CHIP_LVDS 0x02 -#define SIS_EXTERNAL_CHIP_TRUMPION 0x03 -#define SIS_EXTERNAL_CHIP_LVDS_CHRONTEL 0x04 -#define SIS_EXTERNAL_CHIP_CHRONTEL 0x05 -#define SIS310_EXTERNAL_CHIP_LVDS 0x02 -#define SIS310_EXTERNAL_CHIP_LVDS_CHRONTEL 0x03 - -#define SIS_AGP_2X 0x20 /* CR48 */ - -/* vbflags, private entries (others in sisfb.h) */ -#define VB_CONEXANT 0x00000800 /* 661 series only */ -#define VB_TRUMPION VB_CONEXANT /* 300 series only */ -#define VB_302ELV 0x00004000 -#define VB_301 0x00100000 /* Video bridge type */ -#define VB_301B 0x00200000 -#define VB_302B 0x00400000 -#define VB_30xBDH 0x00800000 /* 30xB DH version (w/o LCD support) */ -#define VB_LVDS 0x01000000 -#define VB_CHRONTEL 0x02000000 -#define VB_301LV 0x04000000 -#define VB_302LV 0x08000000 -#define VB_301C 0x10000000 - -#define VB_SISBRIDGE (VB_301|VB_301B|VB_301C|VB_302B|VB_301LV|VB_302LV|VB_302ELV) -#define VB_VIDEOBRIDGE (VB_SISBRIDGE | VB_LVDS | VB_CHRONTEL | VB_CONEXANT) - -enum _SIS_LCD_TYPE { - LCD_INVALID = 0, - LCD_800x600, - LCD_1024x768, - LCD_1280x1024, - LCD_1280x960, - LCD_640x480, - LCD_1600x1200, - LCD_1920x1440, - LCD_2048x1536, - LCD_320x240, /* FSTN */ - LCD_1400x1050, - LCD_1152x864, - LCD_1152x768, - LCD_1280x768, - LCD_1024x600, - LCD_320x240_2, /* DSTN */ - LCD_320x240_3, /* DSTN */ - LCD_848x480, - LCD_1280x800, - LCD_1680x1050, - LCD_1280x720, - LCD_1280x854, - LCD_CUSTOM, - LCD_UNKNOWN -}; - -/* End code taken from Linux kernel 3.18.5 */ - -#define DEFAULT_TEXT_MODE 16 /* index for 800x600x8 */ - -/* coreboot <--> kernel code interface */ -#define __iomem -#define SISIOMEMTYPE -typedef unsigned long SISIOADDRESS; -typedef u64 phys_addr_t; -#define pci_dev device - -#define SZ_16M 0x01000000 - -#define min_t(type, x, y) ({ \ - type __min1 = (x); \ - type __min2 = (y); \ - __min1 < __min2 ? __min1 : __min2; }) - -#define dev_info(dev, format, arg...) printk(BIOS_INFO, "XGI VGA: " format, ##arg) -#define dev_dbg(dev, format, arg...) printk(BIOS_DEBUG, "XGI VGA: " format, ##arg) -#define dev_err(dev, format, arg...) printk(BIOS_ERR, "XGI VGA: " format, ##arg) - -#define pr_info(format, arg...) printk(BIOS_INFO, "XGI VGA: " format, ##arg) -#define pr_debug(format, arg...) printk(BIOS_INFO, "XGI VGA: " format, ##arg) -#define pr_err(format, arg...) printk(BIOS_ERR, "XGI VGA: " format, ##arg) - -static inline int pci_read_config_dword(struct pci_dev *dev, int where, - u32 *val) -{ - *val = pci_read_config32(dev, where); - return 0; -} - -static inline int pci_read_config_byte(struct pci_dev *dev, int where, - u8 *val) -{ - *val = pci_read_config8(dev, where); - return 0; -} - -static inline struct resource* resource_at_bar(struct pci_dev *dev, u8 bar) { - struct resource *res = dev->resource_list; - int i; - for (i = 0; i < bar; i++) { - res = res->next; - if (res == NULL) - return NULL; - } - - return res; -} - -static inline resource_t pci_resource_len(struct pci_dev *dev, u8 bar) { - struct resource *res = resource_at_bar(dev, bar); - if (res) - return res->size; - else - return 0; -} - -static inline resource_t pci_resource_start(struct pci_dev *dev, u8 bar) { - struct resource *res = resource_at_bar(dev, bar); - if (res) - return res->base; - else - return 0; -} - -struct xgifb_video_info *pci_get_drvdata(struct pci_dev *pdev); -void pci_set_drvdata(struct pci_dev *pdev, struct xgifb_video_info *data); - -int xgifb_probe(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info); -int xgifb_modeset(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info); - -#endif diff --git a/src/drivers/xgi/z9s/Kconfig b/src/drivers/xgi/z9s/Kconfig deleted file mode 100644 index b8000c1a8c..0000000000 --- a/src/drivers/xgi/z9s/Kconfig +++ /dev/null @@ -1,3 +0,0 @@ -config DRIVERS_XGI_Z9S - bool - select DRIVERS_XGI_Z79_COMMON diff --git a/src/drivers/xgi/z9s/Makefile.inc b/src/drivers/xgi/z9s/Makefile.inc deleted file mode 100644 index 995543325f..0000000000 --- a/src/drivers/xgi/z9s/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-$(CONFIG_DRIVERS_XGI_Z9S) += z9s.c diff --git a/src/drivers/xgi/z9s/z9s.c b/src/drivers/xgi/z9s/z9s.c deleted file mode 100644 index a3b757534c..0000000000 --- a/src/drivers/xgi/z9s/z9s.c +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include - -#include "../common/xgi_coreboot.h" -#include "../common/XGIfb.h" - -static void xgi_z9s_set_resources(struct device *dev) -{ - /* Reserve VGA regions */ - mmio_resource(dev, 3, 0xa0000 >> 10, 0x1ffff >> 10); - - /* Run standard resource set routine */ - pci_dev_set_resources(dev); -} - -static void xgi_z9s_init(struct device *dev) -{ - u8 ret; - struct xgifb_video_info *xgifb_info; - - if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { - printk(BIOS_INFO, "XGI Z9s: initializing video device\n"); - xgifb_info = malloc(sizeof(*xgifb_info)); - ret = xgifb_probe(dev, xgifb_info); - if (!ret) - xgifb_modeset(dev, xgifb_info); - free(xgifb_info); - } -} - -static struct device_operations xgi_z9s_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = xgi_z9s_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = xgi_z9s_init, -}; - -static const struct pci_driver xgi_z9s_driver __pci_driver = { - .ops = &xgi_z9s_ops, - .vendor = PCI_VENDOR_ID_XGI, - .device = PCI_DEVICE_ID_XGI_20, -}; From 7449b625f8fa4b54e0f4aa1e13a117a4317f585c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 16 May 2020 22:57:51 +0200 Subject: [PATCH 094/405] sb/intel/lynxpoint/lp_gpio.h: Include stdint.h The struct definition makes use of types defined in that header. Change-Id: I1d989298b8bf6266905330491c136874be7f5e28 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41475 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: HAOUAS Elyes Reviewed-by: Paul Menzel --- src/southbridge/intel/lynxpoint/lp_gpio.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h index 7fef30567f..fbad7d020e 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.h +++ b/src/southbridge/intel/lynxpoint/lp_gpio.h @@ -3,6 +3,8 @@ #ifndef INTEL_LYNXPOINT_LP_GPIO_H #define INTEL_LYNXPOINT_LP_GPIO_H +#include + /* LynxPoint LP GPIOBASE Registers */ #define GPIO_OWNER(set) (0x00 + ((set) * 4)) #define GPIO_PIRQ_APIC_EN 0x10 From 3e30c1284fd2cda12023bab30e5aa7c760b0906f Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Thu, 14 May 2020 15:06:41 -0600 Subject: [PATCH 095/405] 3rdparty/amd_blobs: Update with Picasso images Signed-off-by: Marshall Dawson Change-Id: Ie886815ed354762ea52fd6a76169cf25576f8852 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41410 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- 3rdparty/amd_blobs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 17d0288698..dcfc2275a7 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 17d028869899e1ea0f6f385501088f7623121fcb +Subproject commit dcfc2275a7b7c195a7afb657e9829b6bd1b86538 From 189e753cbfc3b3b2c7cca70215610fb3da6267be Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Thu, 14 May 2020 10:20:46 +0900 Subject: [PATCH 096/405] driver/i2c/max98390: Correct included file path Fix coreboot build error with adding this driver BUG=b:149443429 BRANCH=None TEST=built without errors Signed-off-by: Seunghwan Kim Change-Id: I46bced77a50903c16239a5162d144697e9d704a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41389 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/drivers/i2c/max98390/max98390.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/drivers/i2c/max98390/max98390.c b/src/drivers/i2c/max98390/max98390.c index 64c2e3ff2d..c8d7699d0b 100644 --- a/src/drivers/i2c/max98390/max98390.c +++ b/src/drivers/i2c/max98390/max98390.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include -#include -#include +#include +#include +#include #include #include #include From c4b70276ed525bfcc59320b72bcd7c8cd13b78f0 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 13 May 2020 11:42:12 +0200 Subject: [PATCH 097/405] src: Remove leading blank lines from SPDX header Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/Kconfig | 3 --- src/arch/arm/Makefile.inc | 3 --- src/arch/arm/armv4/Makefile.inc | 4 ---- src/arch/arm/armv7/Makefile.inc | 4 ---- src/arch/arm/libgcc/Makefile.inc | 4 ---- src/arch/arm64/Makefile.inc | 4 ---- src/arch/arm64/armv8/Makefile.inc | 4 ---- src/arch/ppc64/Makefile.inc | 4 ---- src/arch/riscv/Makefile.inc | 4 ---- src/arch/x86/Kconfig | 2 -- src/arch/x86/Makefile.inc | 2 -- src/commonlib/storage/Kconfig | 2 -- src/commonlib/storage/Makefile.inc | 2 -- src/cpu/amd/agesa/Kconfig | 2 -- src/cpu/amd/agesa/Makefile.inc | 2 -- src/cpu/amd/agesa/family14/Kconfig | 2 -- src/cpu/amd/agesa/family14/Makefile.inc | 2 -- src/cpu/amd/agesa/family15tn/Kconfig | 2 -- src/cpu/amd/agesa/family15tn/Makefile.inc | 2 -- src/cpu/amd/agesa/family16kb/Kconfig | 2 -- src/cpu/amd/agesa/family16kb/Makefile.inc | 2 -- src/cpu/amd/pi/00630F01/Kconfig | 2 -- src/cpu/amd/pi/00630F01/Makefile.inc | 2 -- src/cpu/amd/pi/00660F01/Kconfig | 2 -- src/cpu/amd/pi/00660F01/Makefile.inc | 2 -- src/cpu/amd/pi/00730F01/Kconfig | 2 -- src/cpu/amd/pi/00730F01/Makefile.inc | 2 -- src/cpu/amd/pi/Kconfig | 2 -- src/cpu/amd/pi/Makefile.inc | 2 -- src/cpu/intel/slot_1/Kconfig | 2 -- src/cpu/qemu-power8/Kconfig | 2 -- src/cpu/qemu-x86/Kconfig | 2 -- src/cpu/x86/name/Makefile.inc | 2 -- src/cpu/x86/smm/Makefile.inc | 2 -- src/device/Kconfig | 2 -- src/device/oprom/Makefile.inc | 2 -- src/device/oprom/realmode/Makefile.inc | 2 -- src/drivers/amd/agesa/Kconfig | 2 -- src/drivers/amd/agesa/Makefile.inc | 2 -- src/drivers/analogix/anx7625/Kconfig | 3 --- src/drivers/analogix/anx7625/Makefile.inc | 3 --- src/drivers/asmedia/Makefile.inc | 2 -- src/drivers/broadcom/Makefile.inc | 2 -- src/drivers/elog/Kconfig | 2 -- src/drivers/generic/gpio_regulator/Kconfig | 2 -- src/drivers/generic/gpio_regulator/Makefile.inc | 2 -- src/drivers/i2c/pcf8523/Kconfig | 2 -- src/drivers/i2c/pcf8523/Makefile.inc | 2 -- src/drivers/intel/fsp1_1/Kconfig | 2 -- src/drivers/intel/fsp1_1/Makefile.inc | 2 -- src/drivers/intel/fsp2_0/Kconfig | 2 -- src/drivers/intel/fsp2_0/Makefile.inc | 2 -- src/drivers/intel/fsp2_0/ppi/Kconfig | 2 -- src/drivers/intel/fsp2_0/ppi/Makefile.inc | 2 -- src/drivers/intel/gma/Kconfig | 2 -- src/drivers/intel/gma/Makefile.inc | 2 -- src/drivers/intel/i210/Makefile.inc | 2 -- src/drivers/intel/wifi/Makefile.inc | 2 -- src/drivers/lenovo/hybrid_graphics/Makefile.inc | 2 -- src/drivers/maxim/max77686/Kconfig | 2 -- src/drivers/maxim/max77686/Makefile.inc | 2 -- src/drivers/parade/ps8625/Kconfig | 2 -- src/drivers/parade/ps8625/Makefile.inc | 2 -- src/drivers/parade/ps8640/Kconfig | 2 -- src/drivers/parade/ps8640/Makefile.inc | 2 -- src/drivers/siemens/nc_fpga/Makefile.inc | 2 -- src/drivers/smmstore/Kconfig | 2 -- src/drivers/spi/Kconfig | 2 -- src/drivers/spi/acpi/Kconfig | 2 -- src/drivers/spi/acpi/Makefile.inc | 2 -- src/drivers/ti/tps65090/Kconfig | 2 -- src/drivers/ti/tps65090/Makefile.inc | 2 -- src/drivers/ti/tps65913/Kconfig | 2 -- src/drivers/ti/tps65913/Makefile.inc | 2 -- src/drivers/vpd/Kconfig | 2 -- src/ec/hp/kbc1126/Kconfig | 3 --- src/ec/hp/kbc1126/Makefile.inc | 3 --- src/ec/roda/it8518/Kconfig | 3 --- src/ec/roda/it8518/Makefile.inc | 3 --- src/lib/Makefile.inc | 3 --- src/lib/gnat/Makefile.inc | 3 --- src/mainboard/amd/gardenia/Makefile.inc | 3 --- src/mainboard/amd/inagua/Makefile.inc | 3 --- src/mainboard/amd/olivehill/Makefile.inc | 3 --- src/mainboard/amd/padmelon/Makefile.inc | 3 --- src/mainboard/amd/parmer/Makefile.inc | 3 --- src/mainboard/amd/persimmon/Makefile.inc | 3 --- src/mainboard/amd/south_station/Makefile.inc | 3 --- src/mainboard/amd/thatcher/Makefile.inc | 3 --- src/mainboard/amd/union_station/Makefile.inc | 3 --- src/mainboard/aopen/dxplplusu/Makefile.inc | 2 -- src/mainboard/apple/macbook21/cmos.layout | 3 --- src/mainboard/apple/macbookair4_2/cmos.layout | 2 -- src/mainboard/asrock/Kconfig | 3 --- src/mainboard/asrock/b75pro3-m/Makefile.inc | 3 --- src/mainboard/asrock/e350m1/Makefile.inc | 3 --- src/mainboard/asrock/g41c-gs/cmos.layout | 3 --- src/mainboard/asrock/h110m/Makefile.inc | 3 --- src/mainboard/asrock/h110m/cmos.layout | 3 --- src/mainboard/asrock/h81m-hds/cmos.layout | 3 --- src/mainboard/asrock/imb-a180/Makefile.inc | 3 --- src/mainboard/asus/Kconfig | 3 --- src/mainboard/asus/am1i-a/Makefile.inc | 3 --- src/mainboard/asus/f2a85-m/Makefile.inc | 3 --- src/mainboard/asus/h61m-cs/cmos.layout | 3 --- src/mainboard/asus/maximus_iv_gene-z/cmos.layout | 3 --- src/mainboard/asus/p5gc-mx/cmos.layout | 3 --- src/mainboard/asus/p5qc/Makefile.inc | 2 -- src/mainboard/asus/p5qc/cmos.layout | 3 --- src/mainboard/asus/p5ql-em/Makefile.inc | 2 -- src/mainboard/asus/p5ql-em/cmos.layout | 2 -- src/mainboard/asus/p5qpl-am/cmos.layout | 3 --- src/mainboard/asus/p8h61-m_lx/cmos.layout | 3 --- src/mainboard/asus/p8h61-m_pro/cmos.layout | 3 --- src/mainboard/asus/p8z77-m_pro/cmos.default | 3 --- src/mainboard/asus/p8z77-m_pro/cmos.layout | 3 --- src/mainboard/bap/Kconfig | 3 --- src/mainboard/bap/ode_e20XX/Makefile.inc | 3 --- src/mainboard/bap/ode_e21XX/Makefile.inc | 3 --- src/mainboard/biostar/Kconfig | 3 --- src/mainboard/biostar/a68n_5200/Makefile.inc | 3 --- src/mainboard/biostar/am1ml/Makefile.inc | 3 --- src/mainboard/cavium/Kconfig | 3 --- src/mainboard/cavium/cn8100_sff_evb/Makefile.inc | 3 --- src/mainboard/elmex/pcm205400/Makefile.inc | 3 --- src/mainboard/emulation/qemu-aarch64/Makefile.inc | 3 --- src/mainboard/emulation/qemu-armv7/Makefile.inc | 3 --- src/mainboard/emulation/qemu-power8/Makefile.inc | 3 --- src/mainboard/emulation/qemu-riscv/Makefile.inc | 3 --- src/mainboard/emulation/spike-riscv/Makefile.inc | 3 --- src/mainboard/facebook/fbg1701/Makefile.inc | 3 --- src/mainboard/facebook/fbg1701/cmos.layout | 3 --- src/mainboard/facebook/monolith/Makefile.inc | 3 --- src/mainboard/facebook/monolith/cmos.layout | 3 --- src/mainboard/facebook/monolith/spd/Makefile.inc | 3 --- src/mainboard/foxconn/Kconfig | 3 --- src/mainboard/foxconn/d41s/cmos.layout | 3 --- src/mainboard/foxconn/g41s-k/cmos.layout | 3 --- src/mainboard/getac/Kconfig | 3 --- src/mainboard/getac/p470/Makefile.inc | 3 --- src/mainboard/getac/p470/cmos.layout | 3 --- src/mainboard/gigabyte/Kconfig | 3 --- src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout | 3 --- src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc | 3 --- src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout | 3 --- src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout | 3 --- src/mainboard/gigabyte/ga-h61m-series/cmos.layout | 3 --- src/mainboard/gizmosphere/Kconfig | 3 --- src/mainboard/gizmosphere/gizmo/Makefile.inc | 3 --- src/mainboard/gizmosphere/gizmo2/Makefile.inc | 3 --- src/mainboard/google/Kconfig | 3 --- src/mainboard/google/auron/Makefile.inc | 3 --- src/mainboard/google/auron/cmos.layout | 3 --- .../google/auron/variants/auron_paine/spd/Makefile.inc | 3 --- .../google/auron/variants/auron_yuna/spd/Makefile.inc | 3 --- src/mainboard/google/auron/variants/buddy/spd/Makefile.inc | 3 --- src/mainboard/google/auron/variants/gandof/spd/Makefile.inc | 3 --- src/mainboard/google/auron/variants/lulu/spd/Makefile.inc | 3 --- src/mainboard/google/auron/variants/samus/Makefile.inc | 2 -- src/mainboard/google/auron/variants/samus/spd/Makefile.inc | 3 --- src/mainboard/google/beltino/Makefile.inc | 3 --- src/mainboard/google/beltino/cmos.layout | 3 --- src/mainboard/google/butterfly/Makefile.inc | 3 --- src/mainboard/google/butterfly/cmos.layout | 3 --- src/mainboard/google/cheza/Makefile.inc | 3 --- src/mainboard/google/cyan/Makefile.inc | 3 --- src/mainboard/google/cyan/cmos.layout | 3 --- src/mainboard/google/cyan/variants/banon/Makefile.inc | 3 --- src/mainboard/google/cyan/variants/celes/Makefile.inc | 3 --- src/mainboard/google/cyan/variants/cyan/Makefile.inc | 3 --- src/mainboard/google/cyan/variants/edgar/Makefile.inc | 3 --- src/mainboard/google/cyan/variants/kefka/Makefile.inc | 3 --- src/mainboard/google/cyan/variants/reks/Makefile.inc | 3 --- src/mainboard/google/cyan/variants/relm/Makefile.inc | 3 --- src/mainboard/google/cyan/variants/setzer/Makefile.inc | 3 --- src/mainboard/google/cyan/variants/terra/Makefile.inc | 3 --- src/mainboard/google/cyan/variants/ultima/Makefile.inc | 3 --- src/mainboard/google/cyan/variants/wizpig/Makefile.inc | 3 --- src/mainboard/google/daisy/Makefile.inc | 3 --- src/mainboard/google/dedede/board_info.c | 6 +----- src/mainboard/google/dedede/bootblock.c | 6 +----- src/mainboard/google/dedede/chromeos.c | 6 +----- src/mainboard/google/dedede/dsdt.asl | 6 +----- src/mainboard/google/dedede/ec.c | 6 +----- src/mainboard/google/dedede/mainboard.c | 6 +----- src/mainboard/google/dedede/romstage.c | 6 +----- src/mainboard/google/dedede/smihandler.c | 6 +----- src/mainboard/google/dedede/spd/Makefile.inc | 4 ---- src/mainboard/google/dedede/variants/baseboard/gpio.c | 6 +----- src/mainboard/google/dedede/variants/baseboard/memory.c | 6 +----- src/mainboard/google/dedede/variants/waddledee/Makefile.inc | 4 ---- src/mainboard/google/dedede/variants/waddledee/memory.c | 6 +----- src/mainboard/google/dedede/variants/waddledoo/Makefile.inc | 4 ---- src/mainboard/google/dedede/variants/waddledoo/memory.c | 6 +----- src/mainboard/google/dedede/variants/wheelie/Makefile.inc | 4 ---- src/mainboard/google/deltaur/Makefile.inc | 3 --- src/mainboard/google/deltaur/bootblock.c | 5 +---- src/mainboard/google/deltaur/chromeos.c | 5 +---- src/mainboard/google/deltaur/dsdt.asl | 5 +---- src/mainboard/google/deltaur/ec.c | 5 +---- src/mainboard/google/deltaur/mainboard.c | 5 +---- src/mainboard/google/deltaur/romstage.c | 5 +---- src/mainboard/google/deltaur/smihandler.c | 5 +---- .../google/deltaur/variants/baseboard/Makefile.inc | 3 --- src/mainboard/google/deltaur/variants/baseboard/gpio.c | 5 +---- src/mainboard/google/deltaur/variants/baseboard/sku.c | 5 +---- src/mainboard/google/deltaur/variants/deltan/Makefile.inc | 4 ---- src/mainboard/google/deltaur/variants/deltan/gpio.c | 5 +---- src/mainboard/google/deltaur/variants/deltan/memory.c | 5 +---- src/mainboard/google/deltaur/variants/deltaur/Makefile.inc | 4 ---- src/mainboard/google/deltaur/variants/deltaur/gpio.c | 5 +---- src/mainboard/google/deltaur/variants/deltaur/memory.c | 5 +---- src/mainboard/google/dragonegg/Makefile.inc | 3 --- src/mainboard/google/dragonegg/spd/Makefile.inc | 3 --- .../google/dragonegg/variants/baseboard/Makefile.inc | 3 --- src/mainboard/google/drallion/Makefile.inc | 3 --- src/mainboard/google/drallion/spd/Makefile.inc | 3 --- .../google/drallion/variants/drallion/Makefile.inc | 3 --- src/mainboard/google/eve/Makefile.inc | 3 --- src/mainboard/google/eve/spd/Makefile.inc | 3 --- src/mainboard/google/fizz/Makefile.inc | 3 --- src/mainboard/google/foster/Makefile.inc | 3 --- src/mainboard/google/foster/bct/Makefile.inc | 3 --- src/mainboard/google/gale/Makefile.inc | 3 --- src/mainboard/google/glados/Makefile.inc | 3 --- src/mainboard/google/glados/cmos.layout | 3 --- src/mainboard/google/glados/variants/asuka/Makefile.inc | 3 --- src/mainboard/google/glados/variants/caroline/Makefile.inc | 3 --- src/mainboard/google/glados/variants/cave/Makefile.inc | 3 --- src/mainboard/google/glados/variants/chell/Makefile.inc | 3 --- src/mainboard/google/glados/variants/glados/Makefile.inc | 3 --- src/mainboard/google/glados/variants/lars/Makefile.inc | 3 --- src/mainboard/google/glados/variants/sentry/Makefile.inc | 3 --- src/mainboard/google/gru/Makefile.inc | 3 --- src/mainboard/google/gru/sdram_params/Makefile.inc | 3 --- src/mainboard/google/hatch/Makefile.inc | 3 --- src/mainboard/google/hatch/spd/Makefile.inc | 3 --- src/mainboard/google/hatch/variants/akemi/Makefile.inc | 2 -- src/mainboard/google/hatch/variants/baseboard/Makefile.inc | 2 -- src/mainboard/google/hatch/variants/dratini/Makefile.inc | 2 -- src/mainboard/google/hatch/variants/duffy/Makefile.inc | 2 -- src/mainboard/google/hatch/variants/hatch/Makefile.inc | 2 -- src/mainboard/google/hatch/variants/helios/Makefile.inc | 2 -- src/mainboard/google/hatch/variants/jinlon/Makefile.inc | 2 -- src/mainboard/google/hatch/variants/kaisa/Makefile.inc | 2 -- src/mainboard/google/hatch/variants/kindred/Makefile.inc | 2 -- src/mainboard/google/hatch/variants/kohaku/Makefile.inc | 2 -- src/mainboard/google/hatch/variants/mushu/Makefile.inc | 2 -- src/mainboard/google/hatch/variants/nightfury/Makefile.inc | 2 -- src/mainboard/google/hatch/variants/palkia/Makefile.inc | 3 --- src/mainboard/google/hatch/variants/puff/Makefile.inc | 2 -- src/mainboard/google/hatch/variants/stryke/Makefile.inc | 1 - src/mainboard/google/hatch/variants/sushi/Makefile.inc | 1 - src/mainboard/google/jecht/Makefile.inc | 3 --- src/mainboard/google/jecht/cmos.layout | 3 --- src/mainboard/google/jecht/spd/Makefile.inc | 3 --- src/mainboard/google/kahlee/Makefile.inc | 3 --- src/mainboard/google/kahlee/variants/aleena/Makefile.inc | 3 --- src/mainboard/google/kahlee/variants/aleena/devicetree.cb | 3 --- src/mainboard/google/kahlee/variants/baseboard/Makefile.inc | 3 --- .../google/kahlee/variants/baseboard/spd/Makefile.inc | 3 --- src/mainboard/google/kahlee/variants/careena/Makefile.inc | 3 --- src/mainboard/google/kahlee/variants/careena/devicetree.cb | 3 --- .../google/kahlee/variants/careena/spd/Makefile.inc | 3 --- src/mainboard/google/kahlee/variants/grunt/Makefile.inc | 3 --- src/mainboard/google/kahlee/variants/grunt/devicetree.cb | 3 --- src/mainboard/google/kahlee/variants/liara/Makefile.inc | 3 --- src/mainboard/google/kahlee/variants/liara/devicetree.cb | 3 --- src/mainboard/google/kahlee/variants/nuwani/Makefile.inc | 3 --- src/mainboard/google/kahlee/variants/nuwani/devicetree.cb | 3 --- .../google/kahlee/variants/nuwani/spd/Makefile.inc | 3 --- src/mainboard/google/kahlee/variants/treeya/Makefile.inc | 3 --- src/mainboard/google/kahlee/variants/treeya/devicetree.cb | 3 --- .../google/kahlee/variants/treeya/spd/Makefile.inc | 3 --- src/mainboard/google/link/Makefile.inc | 3 --- src/mainboard/google/link/cmos.layout | 3 --- src/mainboard/google/nyan/Makefile.inc | 3 --- src/mainboard/google/nyan/bct/Makefile.inc | 3 --- src/mainboard/google/nyan_big/Makefile.inc | 3 --- src/mainboard/google/nyan_big/bct/Makefile.inc | 3 --- src/mainboard/google/nyan_blaze/Makefile.inc | 3 --- src/mainboard/google/nyan_blaze/bct/Makefile.inc | 3 --- src/mainboard/google/oak/Makefile.inc | 3 --- src/mainboard/google/parrot/Makefile.inc | 3 --- src/mainboard/google/parrot/cmos.layout | 3 --- src/mainboard/google/peach_pit/Makefile.inc | 3 --- src/mainboard/google/poppy/Makefile.inc | 3 --- src/mainboard/google/rambi/Makefile.inc | 3 --- src/mainboard/google/rambi/cmos.layout | 3 --- src/mainboard/google/rambi/variants/banjo/Makefile.inc | 3 --- src/mainboard/google/rambi/variants/candy/Makefile.inc | 3 --- src/mainboard/google/rambi/variants/clapper/Makefile.inc | 3 --- src/mainboard/google/rambi/variants/enguarde/Makefile.inc | 3 --- src/mainboard/google/rambi/variants/glimmer/Makefile.inc | 3 --- src/mainboard/google/rambi/variants/gnawty/Makefile.inc | 3 --- src/mainboard/google/rambi/variants/heli/Makefile.inc | 3 --- src/mainboard/google/rambi/variants/kip/Makefile.inc | 3 --- src/mainboard/google/rambi/variants/ninja/Makefile.inc | 3 --- src/mainboard/google/rambi/variants/orco/Makefile.inc | 3 --- src/mainboard/google/rambi/variants/quawks/Makefile.inc | 3 --- src/mainboard/google/rambi/variants/rambi/Makefile.inc | 3 --- src/mainboard/google/rambi/variants/squawks/Makefile.inc | 3 --- src/mainboard/google/rambi/variants/sumo/Makefile.inc | 3 --- src/mainboard/google/rambi/variants/swanky/Makefile.inc | 3 --- src/mainboard/google/rambi/variants/winky/Makefile.inc | 3 --- src/mainboard/google/sarien/Makefile.inc | 3 --- src/mainboard/google/sarien/variants/arcada/Makefile.inc | 3 --- src/mainboard/google/sarien/variants/sarien/Makefile.inc | 3 --- src/mainboard/google/slippy/Makefile.inc | 3 --- src/mainboard/google/slippy/cmos.layout | 3 --- src/mainboard/google/slippy/variants/falco/Makefile.inc | 3 --- src/mainboard/google/slippy/variants/leon/Makefile.inc | 3 --- src/mainboard/google/slippy/variants/peppy/Makefile.inc | 3 --- src/mainboard/google/slippy/variants/wolf/Makefile.inc | 3 --- src/mainboard/google/smaug/Makefile.inc | 3 --- src/mainboard/google/smaug/bct/Makefile.inc | 3 --- src/mainboard/google/storm/Makefile.inc | 3 --- src/mainboard/google/stout/Makefile.inc | 3 --- src/mainboard/google/stout/cmos.layout | 3 --- src/mainboard/google/trogdor/Makefile.inc | 3 --- src/mainboard/google/veyron/Makefile.inc | 3 --- src/mainboard/google/veyron_mickey/Makefile.inc | 3 --- src/mainboard/google/veyron_rialto/Makefile.inc | 3 --- src/mainboard/google/volteer/Makefile.inc | 3 --- src/mainboard/google/volteer/spd/Makefile.inc | 3 --- .../google/volteer/variants/baseboard/Makefile.inc | 3 --- src/mainboard/google/volteer/variants/ripto/Makefile.inc | 3 --- src/mainboard/google/volteer/variants/volteer/Makefile.inc | 3 --- src/mainboard/hp/abm/Makefile.inc | 3 --- src/mainboard/hp/compaq_8200_elite_sff/cmos.layout | 3 --- src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc | 3 --- src/mainboard/hp/snb_ivb_laptops/Makefile.inc | 3 --- src/mainboard/hp/snb_ivb_laptops/cmos.layout | 3 --- src/mainboard/hp/z220_sff_workstation/cmos.layout | 3 --- src/mainboard/ibase/mb899/cmos.layout | 3 --- src/mainboard/intel/baskingridge/Makefile.inc | 3 --- src/mainboard/intel/baskingridge/cmos.layout | 3 --- src/mainboard/intel/cannonlake_rvp/Makefile.inc | 3 --- src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc | 3 --- src/mainboard/intel/coffeelake_rvp/Makefile.inc | 3 --- src/mainboard/intel/d510mo/cmos.layout | 3 --- src/mainboard/intel/d945gclf/cmos.layout | 3 --- src/mainboard/intel/dg41wv/cmos.layout | 3 --- src/mainboard/intel/dg43gt/Makefile.inc | 2 -- src/mainboard/intel/dg43gt/cmos.layout | 3 --- src/mainboard/intel/emeraldlake2/Makefile.inc | 3 --- src/mainboard/intel/emeraldlake2/cmos.layout | 3 --- src/mainboard/intel/galileo/Makefile.inc | 3 --- src/mainboard/intel/harcuvar/Makefile.inc | 3 --- src/mainboard/intel/harcuvar/spd/Makefile.inc | 3 --- src/mainboard/intel/icelake_rvp/Makefile.inc | 3 --- src/mainboard/intel/icelake_rvp/spd/Makefile.inc | 3 --- src/mainboard/intel/icelake_rvp/variants/icl_u/Makefile.inc | 3 --- src/mainboard/intel/icelake_rvp/variants/icl_y/Makefile.inc | 3 --- src/mainboard/intel/jasperlake_rvp/Makefile.inc | 3 --- src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc | 3 --- .../intel/jasperlake_rvp/variants/jslrvp/Makefile.inc | 3 --- src/mainboard/intel/kblrvp/Makefile.inc | 3 --- src/mainboard/intel/kblrvp/cmos.layout | 3 --- src/mainboard/intel/kblrvp/spd/Makefile.inc | 3 --- src/mainboard/intel/kunimitsu/Makefile.inc | 3 --- src/mainboard/intel/kunimitsu/cmos.layout | 3 --- src/mainboard/intel/kunimitsu/spd/Makefile.inc | 3 --- src/mainboard/intel/saddlebrook/Makefile.inc | 3 --- src/mainboard/intel/saddlebrook/cmos.layout | 3 --- src/mainboard/intel/saddlebrook/spd/Makefile.inc | 3 --- src/mainboard/intel/strago/Makefile.inc | 3 --- src/mainboard/intel/strago/cmos.layout | 3 --- src/mainboard/intel/tglrvp/Makefile.inc | 3 --- src/mainboard/intel/tglrvp/spd/Makefile.inc | 3 --- src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc | 3 --- src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc | 3 --- src/mainboard/intel/wtm2/Makefile.inc | 3 --- src/mainboard/intel/wtm2/cmos.layout | 3 --- src/mainboard/jetway/nf81-t56n-lf/Makefile.inc | 3 --- src/mainboard/kontron/986lcd-m/cmos.layout | 3 --- src/mainboard/kontron/ktqm77/cmos.layout | 3 --- src/mainboard/lenovo/g505s/Makefile.inc | 3 --- src/mainboard/lenovo/l520/Makefile.inc | 3 --- src/mainboard/lenovo/l520/cmos.layout | 3 --- src/mainboard/lenovo/t400/Makefile.inc | 3 --- src/mainboard/lenovo/t400/cmos.layout | 3 --- src/mainboard/lenovo/t410/Makefile.inc | 3 --- src/mainboard/lenovo/t410/cmos.layout | 3 --- src/mainboard/lenovo/t420/Makefile.inc | 3 --- src/mainboard/lenovo/t420/cmos.layout | 3 --- src/mainboard/lenovo/t420s/Makefile.inc | 3 --- src/mainboard/lenovo/t420s/cmos.layout | 3 --- src/mainboard/lenovo/t430/cmos.layout | 3 --- src/mainboard/lenovo/t430s/Makefile.inc | 3 --- src/mainboard/lenovo/t430s/cmos.layout | 3 --- src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc | 3 --- src/mainboard/lenovo/t440p/cmos.layout | 3 --- src/mainboard/lenovo/t520/Makefile.inc | 3 --- src/mainboard/lenovo/t520/cmos.layout | 3 --- src/mainboard/lenovo/t530/Makefile.inc | 3 --- src/mainboard/lenovo/t530/cmos.layout | 3 --- src/mainboard/lenovo/t60/Makefile.inc | 3 --- src/mainboard/lenovo/t60/cmos.layout | 3 --- src/mainboard/lenovo/t60/variants/t60/overridetree.cb | 3 --- src/mainboard/lenovo/t60/variants/z61t/overridetree.cb | 3 --- src/mainboard/lenovo/thinkcentre_a58/cmos.layout | 3 --- src/mainboard/lenovo/x131e/Makefile.inc | 3 --- src/mainboard/lenovo/x131e/cmos.layout | 3 --- src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc | 3 --- src/mainboard/lenovo/x1_carbon_gen1/cmos.layout | 3 --- src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc | 3 --- src/mainboard/lenovo/x200/Makefile.inc | 3 --- src/mainboard/lenovo/x200/cmos.layout | 3 --- src/mainboard/lenovo/x201/Makefile.inc | 3 --- src/mainboard/lenovo/x201/cmos.layout | 3 --- src/mainboard/lenovo/x220/Makefile.inc | 3 --- src/mainboard/lenovo/x220/cmos.layout | 3 --- src/mainboard/lenovo/x230/Makefile.inc | 3 --- src/mainboard/lenovo/x230/cmos.layout | 3 --- src/mainboard/lenovo/x60/Makefile.inc | 3 --- src/mainboard/lenovo/x60/cmos.layout | 3 --- src/mainboard/lippert/frontrunner-af/Makefile.inc | 3 --- src/mainboard/lippert/toucan-af/Makefile.inc | 3 --- src/mainboard/msi/Kconfig | 3 --- src/mainboard/msi/ms7721/Makefile.inc | 3 --- src/mainboard/opencellular/Kconfig | 3 --- src/mainboard/opencellular/elgon/Makefile.inc | 3 --- src/mainboard/packardbell/ms2290/Makefile.inc | 3 --- src/mainboard/packardbell/ms2290/cmos.layout | 3 --- src/mainboard/pcengines/apu1/Makefile.inc | 3 --- src/mainboard/pcengines/apu2/Makefile.inc | 3 --- src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb | 3 --- src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb | 3 --- src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb | 3 --- src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb | 3 --- src/mainboard/portwell/m107/Makefile.inc | 3 --- src/mainboard/portwell/m107/cmos.layout | 3 --- src/mainboard/purism/Kconfig | 3 --- src/mainboard/purism/librem_bdw/Makefile.inc | 3 --- src/mainboard/purism/librem_skl/Makefile.inc | 3 --- src/mainboard/razer/blade_stealth_kbl/Makefile.inc | 3 --- src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc | 3 --- src/mainboard/roda/rk886ex/Makefile.inc | 3 --- src/mainboard/roda/rk886ex/cmos.layout | 3 --- src/mainboard/roda/rk9/Makefile.inc | 3 --- src/mainboard/roda/rk9/cmos.layout | 3 --- src/mainboard/roda/rv11/Makefile.inc | 3 --- src/mainboard/roda/rv11/cmos.layout | 3 --- src/mainboard/roda/rv11/variants/rv11/devicetree.cb | 3 --- src/mainboard/roda/rv11/variants/rw11/devicetree.cb | 3 --- src/mainboard/samsung/lumpy/Makefile.inc | 3 --- src/mainboard/samsung/lumpy/cmos.layout | 3 --- src/mainboard/samsung/stumpy/Makefile.inc | 3 --- src/mainboard/samsung/stumpy/cmos.layout | 3 --- src/mainboard/sapphire/pureplatinumh61/cmos.layout | 3 --- src/mainboard/scaleway/tagada/Makefile.inc | 3 --- src/mainboard/sifive/hifive-unleashed/Makefile.inc | 2 -- src/mainboard/supermicro/x10slm-f/cmos.layout | 3 --- src/mainboard/supermicro/x11-lga1151-series/Makefile.inc | 3 --- src/mainboard/supermicro/x11-lga1151-series/cmos.layout | 3 --- src/mainboard/ti/Kconfig | 3 --- src/mainboard/ti/beaglebone/Makefile.inc | 3 --- src/northbridge/amd/agesa/Makefile.inc | 3 --- src/northbridge/amd/agesa/family14/Makefile.inc | 3 --- src/northbridge/amd/agesa/family15tn/Makefile.inc | 3 --- src/northbridge/amd/agesa/family16kb/Makefile.inc | 3 --- src/northbridge/amd/pi/00630F01/Makefile.inc | 3 --- src/northbridge/amd/pi/00660F01/Makefile.inc | 3 --- src/northbridge/amd/pi/00730F01/Makefile.inc | 3 --- src/northbridge/amd/pi/Makefile.inc | 3 --- src/northbridge/intel/gm45/Makefile.inc | 3 --- src/northbridge/intel/haswell/Makefile.inc | 3 --- src/northbridge/intel/i945/Makefile.inc | 3 --- src/northbridge/intel/ironlake/Makefile.inc | 3 --- src/northbridge/intel/pineview/Makefile.inc | 3 --- src/northbridge/intel/x4x/Makefile.inc | 3 --- src/security/vboot/Makefile.inc | 3 --- src/soc/cavium/cn81xx/Makefile.inc | 3 --- src/soc/cavium/common/Makefile.inc | 3 --- src/soc/intel/cannonlake/romstage/Makefile.inc | 3 --- src/soc/intel/denverton_ns/Makefile.inc | 3 --- src/soc/intel/icelake/romstage/Makefile.inc | 3 --- src/soc/intel/jasperlake/romstage/Makefile.inc | 3 --- src/soc/intel/quark/Makefile.inc | 3 --- src/soc/intel/quark/romstage/Makefile.inc | 3 --- src/soc/intel/tigerlake/romstage/Makefile.inc | 3 --- src/soc/intel/xeon_sp/cpx/Kconfig | 2 -- src/soc/intel/xeon_sp/cpx/Makefile.inc | 2 -- src/soc/intel/xeon_sp/skx/Kconfig | 2 -- src/soc/intel/xeon_sp/skx/Makefile.inc | 2 -- src/soc/mediatek/mt8173/Makefile.inc | 3 --- src/soc/nvidia/tegra124/lp0/Makefile | 3 --- src/soc/nvidia/tegra210/lp0/Makefile | 3 --- src/soc/qualcomm/ipq40xx/Makefile.inc | 3 --- src/soc/qualcomm/ipq806x/Makefile.inc | 3 --- src/soc/rockchip/rk3288/Makefile.inc | 3 --- src/soc/rockchip/rk3399/Makefile.inc | 3 --- src/soc/sifive/fu540/Makefile.inc | 2 -- src/southbridge/amd/agesa/Makefile.inc | 3 --- src/southbridge/amd/cimx/Makefile.inc | 3 --- src/southbridge/amd/cimx/sb800/Makefile.inc | 3 --- src/southbridge/amd/pi/Makefile.inc | 3 --- src/southbridge/intel/common/Makefile.inc | 3 --- src/southbridge/intel/common/firmware/Makefile.inc | 3 --- src/southbridge/intel/i82801dx/Makefile.inc | 3 --- src/southbridge/intel/i82801gx/Makefile.inc | 3 --- src/southbridge/intel/i82801ix/Makefile.inc | 3 --- src/southbridge/intel/i82801jx/Makefile.inc | 3 --- src/southbridge/intel/ibexpeak/Makefile.inc | 3 --- src/southbridge/ti/pci7420/Makefile.inc | 3 --- src/southbridge/ti/pcixx12/Makefile.inc | 3 --- 507 files changed, 25 insertions(+), 1477 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index e7fd0aff98..2a2a144235 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only mainmenu "coreboot configuration" diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index 48d3e4e5aa..66bf9c4f31 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -1,7 +1,4 @@ -################################################################################ -## ## SPDX-License-Identifier: GPL-2.0-only -## ############################################################################### # ARM specific options diff --git a/src/arch/arm/armv4/Makefile.inc b/src/arch/arm/armv4/Makefile.inc index 60a60b1fb9..f4ccaf3f91 100644 --- a/src/arch/arm/armv4/Makefile.inc +++ b/src/arch/arm/armv4/Makefile.inc @@ -1,8 +1,4 @@ -################################################################################ -## ## SPDX-License-Identifier: GPL-2.0-only -## -############################################################################### armv4_flags = -marm -march=armv4t -I$(src)/arch/arm/include/armv4/ \ -D__COREBOOT_ARM_ARCH__=4 diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index 48cd4587ed..66ddc98da5 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -1,8 +1,4 @@ -################################################################################ -## ## SPDX-License-Identifier: GPL-2.0-only -## -############################################################################### armv7_flags = -mthumb -I$(src)/arch/arm/include/armv7/ -D__COREBOOT_ARM_ARCH__=7 armv7-a_flags = -march=armv7-a $(armv7_flags) -D__COREBOOT_ARM_V7_A__ diff --git a/src/arch/arm/libgcc/Makefile.inc b/src/arch/arm/libgcc/Makefile.inc index 08fb1e0775..0da655ea98 100644 --- a/src/arch/arm/libgcc/Makefile.inc +++ b/src/arch/arm/libgcc/Makefile.inc @@ -1,8 +1,4 @@ -################################################################################ -## ## SPDX-License-Identifier: GPL-2.0-only -## -################################################################################ libgcc_files = ashldi3.S lib1funcs.S lshrdi3.S muldi3.S ucmpdi2.S uldivmod.S libgcc_files += udivmoddi4.c umoddi3.c diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index f635def940..5fd316aa7b 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -1,8 +1,4 @@ -################################################################################ -## ## SPDX-License-Identifier: GPL-2.0-only -## -################################################################################ ################################################################################ # Take care of subdirectories diff --git a/src/arch/arm64/armv8/Makefile.inc b/src/arch/arm64/armv8/Makefile.inc index 115742a641..15d80e64e8 100644 --- a/src/arch/arm64/armv8/Makefile.inc +++ b/src/arch/arm64/armv8/Makefile.inc @@ -1,8 +1,4 @@ -################################################################################ -## ## SPDX-License-Identifier: GPL-2.0-only -## -################################################################################ ifeq ($(CONFIG_ARCH_ARMV8_EXTENSION),0) march = armv8-a diff --git a/src/arch/ppc64/Makefile.inc b/src/arch/ppc64/Makefile.inc index 1fbd70b0f7..f1a2487a57 100644 --- a/src/arch/ppc64/Makefile.inc +++ b/src/arch/ppc64/Makefile.inc @@ -1,8 +1,4 @@ -################################################################################ -## ## SPDX-License-Identifier: GPL-2.0-only -## -################################################################################ ppc64_flags = -I$(src)/arch/ppc64/ -mbig-endian -mcpu=power8 -mtune=power8 diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 3c5d7e7cfa..632e220410 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -1,8 +1,4 @@ -################################################################################ -## ## SPDX-License-Identifier: GPL-2.0-only -## -################################################################################ ################################################################################ ## RISC-V specific options diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 989255832e..0a207e19b0 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -1,6 +1,4 @@ -## ## SPDX-License-Identifier: GPL-2.0-only -## config ARCH_X86 bool diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index d30be40cca..0dd8d2b71e 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -1,6 +1,4 @@ -## ## SPDX-License-Identifier: GPL-2.0-only -## ifeq ($(CONFIG_POSTCAR_STAGE),y) $(eval $(call init_standard_toolchain,postcar)) diff --git a/src/commonlib/storage/Kconfig b/src/commonlib/storage/Kconfig index 97d09ff997..7b98ca190f 100644 --- a/src/commonlib/storage/Kconfig +++ b/src/commonlib/storage/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only config COMMONLIB_STORAGE diff --git a/src/commonlib/storage/Makefile.inc b/src/commonlib/storage/Makefile.inc index d33c316562..a2eb4359e9 100644 --- a/src/commonlib/storage/Makefile.inc +++ b/src/commonlib/storage/Makefile.inc @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_COMMONLIB_STORAGE),y) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 6aae36844e..35e2f93268 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only config CPU_AMD_AGESA diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 6336d0c9e8..14067e1fed 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14 diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 2fb54537dc..103903fc1e 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only config CPU_AMD_AGESA_FAMILY14 diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 0eec1be8ed..c940232f9f 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only romstage-y += fixme.c diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index 9b580a58da..70f71ed946 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only config CPU_AMD_AGESA_FAMILY15_TN diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 66a151a06b..bc04cfd6da 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only romstage-y += fixme.c diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig index 3a83b6789a..e41ddece4d 100644 --- a/src/cpu/amd/agesa/family16kb/Kconfig +++ b/src/cpu/amd/agesa/family16kb/Kconfig @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only config CPU_AMD_AGESA_FAMILY16_KB diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc index 6131df5917..c097b2c25a 100644 --- a/src/cpu/amd/agesa/family16kb/Makefile.inc +++ b/src/cpu/amd/agesa/family16kb/Makefile.inc @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only romstage-y += fixme.c diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig index 173a7f3b8d..c14cd54dc6 100644 --- a/src/cpu/amd/pi/00630F01/Kconfig +++ b/src/cpu/amd/pi/00630F01/Kconfig @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only config CPU_AMD_PI_00630F01 diff --git a/src/cpu/amd/pi/00630F01/Makefile.inc b/src/cpu/amd/pi/00630F01/Makefile.inc index 66a151a06b..bc04cfd6da 100644 --- a/src/cpu/amd/pi/00630F01/Makefile.inc +++ b/src/cpu/amd/pi/00630F01/Makefile.inc @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only romstage-y += fixme.c diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig index 8f381448d9..1cdfb1d7be 100644 --- a/src/cpu/amd/pi/00660F01/Kconfig +++ b/src/cpu/amd/pi/00660F01/Kconfig @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only config CPU_AMD_PI_00660F01 diff --git a/src/cpu/amd/pi/00660F01/Makefile.inc b/src/cpu/amd/pi/00660F01/Makefile.inc index 52777dcd15..69635fc1f2 100644 --- a/src/cpu/amd/pi/00660F01/Makefile.inc +++ b/src/cpu/amd/pi/00660F01/Makefile.inc @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only romstage-y += fixme.c diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig index af9731eee4..5296ee6399 100644 --- a/src/cpu/amd/pi/00730F01/Kconfig +++ b/src/cpu/amd/pi/00730F01/Kconfig @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only config CPU_AMD_PI_00730F01 diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc index a3508ae6bf..45ec1d9a2b 100644 --- a/src/cpu/amd/pi/00730F01/Makefile.inc +++ b/src/cpu/amd/pi/00730F01/Makefile.inc @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only romstage-y += fixme.c diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 9e795dc3b7..bc1253856f 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only config CPU_AMD_PI diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc index 300a3398f1..969434700e 100644 --- a/src/cpu/amd/pi/Makefile.inc +++ b/src/cpu/amd/pi/Makefile.inc @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01 diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 1ba71ad9cb..6928335ada 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only config CPU_INTEL_SLOT_1 diff --git a/src/cpu/qemu-power8/Kconfig b/src/cpu/qemu-power8/Kconfig index 37fd356d30..7e9b4cbf22 100644 --- a/src/cpu/qemu-power8/Kconfig +++ b/src/cpu/qemu-power8/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only config CPU_QEMU_POWER8 diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 2bf7eab305..21ada02a5d 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only config CPU_QEMU_X86 diff --git a/src/cpu/x86/name/Makefile.inc b/src/cpu/x86/name/Makefile.inc index 98c778cf4b..f76927094b 100644 --- a/src/cpu/x86/name/Makefile.inc +++ b/src/cpu/x86/name/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += name.c diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 824a3f1056..500f169edb 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-y += smm_module_loader.c diff --git a/src/device/Kconfig b/src/device/Kconfig index 6096a38b6f..751083cf81 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only menu "Devices" diff --git a/src/device/oprom/Makefile.inc b/src/device/oprom/Makefile.inc index b00b983cf8..15285c7556 100644 --- a/src/device/oprom/Makefile.inc +++ b/src/device/oprom/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only subdirs-$(CONFIG_PCI_OPTION_ROM_RUN_YABEL) += x86emu diff --git a/src/device/oprom/realmode/Makefile.inc b/src/device/oprom/realmode/Makefile.inc index d1bf9e6efd..a3c7774ff5 100644 --- a/src/device/oprom/realmode/Makefile.inc +++ b/src/device/oprom/realmode/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) += x86.c diff --git a/src/drivers/amd/agesa/Kconfig b/src/drivers/amd/agesa/Kconfig index 2cdca8f231..1aa2c33dc5 100644 --- a/src/drivers/amd/agesa/Kconfig +++ b/src/drivers/amd/agesa/Kconfig @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only config DRIVERS_AMD_PI diff --git a/src/drivers/amd/agesa/Makefile.inc b/src/drivers/amd/agesa/Makefile.inc index c97138fac0..6d80c4c6c3 100644 --- a/src/drivers/amd/agesa/Makefile.inc +++ b/src/drivers/amd/agesa/Makefile.inc @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_DRIVERS_AMD_PI),y) diff --git a/src/drivers/analogix/anx7625/Kconfig b/src/drivers/analogix/anx7625/Kconfig index b59b9f463c..69fc1960b0 100644 --- a/src/drivers/analogix/anx7625/Kconfig +++ b/src/drivers/analogix/anx7625/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only config DRIVER_ANALOGIX_ANX7625 diff --git a/src/drivers/analogix/anx7625/Makefile.inc b/src/drivers/analogix/anx7625/Makefile.inc index 43a1e13303..2514048002 100644 --- a/src/drivers/analogix/anx7625/Makefile.inc +++ b/src/drivers/analogix/anx7625/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_DRIVER_ANALOGIX_ANX7625) += anx7625.c diff --git a/src/drivers/asmedia/Makefile.inc b/src/drivers/asmedia/Makefile.inc index 7ff84db178..1088eaebba 100644 --- a/src/drivers/asmedia/Makefile.inc +++ b/src/drivers/asmedia/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_DRIVERS_ASMEDIA_ASPM_BLACKLIST) += aspm_blacklist.c diff --git a/src/drivers/broadcom/Makefile.inc b/src/drivers/broadcom/Makefile.inc index 906dc7a639..464cd47606 100644 --- a/src/drivers/broadcom/Makefile.inc +++ b/src/drivers/broadcom/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_PCIEXP_ASPM) += bcm57xx_aspm_disable.c diff --git a/src/drivers/elog/Kconfig b/src/drivers/elog/Kconfig index c4261ef045..bc25d1cebb 100644 --- a/src/drivers/elog/Kconfig +++ b/src/drivers/elog/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only config ELOG diff --git a/src/drivers/generic/gpio_regulator/Kconfig b/src/drivers/generic/gpio_regulator/Kconfig index 96fa7f2213..c4c83e40bc 100644 --- a/src/drivers/generic/gpio_regulator/Kconfig +++ b/src/drivers/generic/gpio_regulator/Kconfig @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only config DRIVERS_GENERIC_GPIO_REGULATOR diff --git a/src/drivers/generic/gpio_regulator/Makefile.inc b/src/drivers/generic/gpio_regulator/Makefile.inc index 538657d5e6..232e65e347 100644 --- a/src/drivers/generic/gpio_regulator/Makefile.inc +++ b/src/drivers/generic/gpio_regulator/Makefile.inc @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_DRIVERS_GENERIC_GPIO_REGULATOR) += gpio_regulator.c diff --git a/src/drivers/i2c/pcf8523/Kconfig b/src/drivers/i2c/pcf8523/Kconfig index f3e9d4b417..16db5a20a4 100644 --- a/src/drivers/i2c/pcf8523/Kconfig +++ b/src/drivers/i2c/pcf8523/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only config DRIVERS_I2C_PCF8523 diff --git a/src/drivers/i2c/pcf8523/Makefile.inc b/src/drivers/i2c/pcf8523/Makefile.inc index bf15cdaa07..349f5622d3 100644 --- a/src/drivers/i2c/pcf8523/Makefile.inc +++ b/src/drivers/i2c/pcf8523/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_DRIVERS_I2C_PCF8523) += pcf8523.c diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index c0d7923f1a..b1c6898bb4 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only config PLATFORM_USES_FSP1_1 diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 2740c0e3e0..86d1f2f760 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index dcd8f72f28..cad652b905 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only config PLATFORM_USES_FSP2_0 diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 19ac920cf4..a46f9b88a2 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) diff --git a/src/drivers/intel/fsp2_0/ppi/Kconfig b/src/drivers/intel/fsp2_0/ppi/Kconfig index 9a3e0ea1db..4f77a32cb2 100644 --- a/src/drivers/intel/fsp2_0/ppi/Kconfig +++ b/src/drivers/intel/fsp2_0/ppi/Kconfig @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only config FSP_USES_MP_SERVICES_PPI diff --git a/src/drivers/intel/fsp2_0/ppi/Makefile.inc b/src/drivers/intel/fsp2_0/ppi/Makefile.inc index bd57938e88..8d8d990abb 100644 --- a/src/drivers/intel/fsp2_0/ppi/Makefile.inc +++ b/src/drivers/intel/fsp2_0/ppi/Makefile.inc @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_FSP_USES_MP_SERVICES_PPI) += mp_service_ppi.c diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 2d1161fbfc..ad44a2f480 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only config INTEL_DDI diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index 366ffecee3..964d13e30c 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_INTEL_DDI) += intel_ddi.c diff --git a/src/drivers/intel/i210/Makefile.inc b/src/drivers/intel/i210/Makefile.inc index b765a07626..218b1b45f9 100644 --- a/src/drivers/intel/i210/Makefile.inc +++ b/src/drivers/intel/i210/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_DRIVER_INTEL_I210)+= i210.c diff --git a/src/drivers/intel/wifi/Makefile.inc b/src/drivers/intel/wifi/Makefile.inc index 689df7c3c3..57f60afb99 100644 --- a/src/drivers/intel/wifi/Makefile.inc +++ b/src/drivers/intel/wifi/Makefile.inc @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_DRIVERS_INTEL_WIFI) += wifi.c diff --git a/src/drivers/lenovo/hybrid_graphics/Makefile.inc b/src/drivers/lenovo/hybrid_graphics/Makefile.inc index bb16480023..ec08d12777 100644 --- a/src/drivers/lenovo/hybrid_graphics/Makefile.inc +++ b/src/drivers/lenovo/hybrid_graphics/Makefile.inc @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS) += hybrid_graphics.c diff --git a/src/drivers/maxim/max77686/Kconfig b/src/drivers/maxim/max77686/Kconfig index 51352f60e8..f32dc74f79 100644 --- a/src/drivers/maxim/max77686/Kconfig +++ b/src/drivers/maxim/max77686/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only config DRIVER_MAXIM_MAX77686 diff --git a/src/drivers/maxim/max77686/Makefile.inc b/src/drivers/maxim/max77686/Makefile.inc index 36238af460..f65e7fa981 100644 --- a/src/drivers/maxim/max77686/Makefile.inc +++ b/src/drivers/maxim/max77686/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-$(CONFIG_DRIVER_MAXIM_MAX77686) += max77686.c diff --git a/src/drivers/parade/ps8625/Kconfig b/src/drivers/parade/ps8625/Kconfig index e4e3401f58..9cec5acc05 100644 --- a/src/drivers/parade/ps8625/Kconfig +++ b/src/drivers/parade/ps8625/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only config DRIVER_PARADE_PS8625 diff --git a/src/drivers/parade/ps8625/Makefile.inc b/src/drivers/parade/ps8625/Makefile.inc index 40b6ed372a..2db5bbd85f 100644 --- a/src/drivers/parade/ps8625/Makefile.inc +++ b/src/drivers/parade/ps8625/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_DRIVER_PARADE_PS8625) += ps8625.c diff --git a/src/drivers/parade/ps8640/Kconfig b/src/drivers/parade/ps8640/Kconfig index 4824d90d21..293f0ba6e6 100644 --- a/src/drivers/parade/ps8640/Kconfig +++ b/src/drivers/parade/ps8640/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only config DRIVER_PARADE_PS8640 diff --git a/src/drivers/parade/ps8640/Makefile.inc b/src/drivers/parade/ps8640/Makefile.inc index 6bafcd4371..5a458b0c49 100644 --- a/src/drivers/parade/ps8640/Makefile.inc +++ b/src/drivers/parade/ps8640/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_DRIVER_PARADE_PS8640) += ps8640.c diff --git a/src/drivers/siemens/nc_fpga/Makefile.inc b/src/drivers/siemens/nc_fpga/Makefile.inc index 3334f614c7..ac2875f52f 100644 --- a/src/drivers/siemens/nc_fpga/Makefile.inc +++ b/src/drivers/siemens/nc_fpga/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_DRIVER_SIEMENS_NC_FPGA) += nc_fpga.c diff --git a/src/drivers/smmstore/Kconfig b/src/drivers/smmstore/Kconfig index a9debd259b..019666b1ff 100644 --- a/src/drivers/smmstore/Kconfig +++ b/src/drivers/smmstore/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only config SMMSTORE diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index d1f8f87e90..42068f4fce 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only config COMMON_CBFS_SPI_WRAPPER diff --git a/src/drivers/spi/acpi/Kconfig b/src/drivers/spi/acpi/Kconfig index b155bba434..499049c799 100644 --- a/src/drivers/spi/acpi/Kconfig +++ b/src/drivers/spi/acpi/Kconfig @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only config DRIVERS_SPI_ACPI diff --git a/src/drivers/spi/acpi/Makefile.inc b/src/drivers/spi/acpi/Makefile.inc index ae7f8e1384..18ab84a5af 100644 --- a/src/drivers/spi/acpi/Makefile.inc +++ b/src/drivers/spi/acpi/Makefile.inc @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_DRIVERS_SPI_ACPI) += acpi.c diff --git a/src/drivers/ti/tps65090/Kconfig b/src/drivers/ti/tps65090/Kconfig index a351f63e9b..e83bbcc11b 100644 --- a/src/drivers/ti/tps65090/Kconfig +++ b/src/drivers/ti/tps65090/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only config DRIVER_TI_TPS65090 diff --git a/src/drivers/ti/tps65090/Makefile.inc b/src/drivers/ti/tps65090/Makefile.inc index 7629686636..26f5b501f5 100644 --- a/src/drivers/ti/tps65090/Makefile.inc +++ b/src/drivers/ti/tps65090/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_DRIVER_TI_TPS65090) += tps65090.c diff --git a/src/drivers/ti/tps65913/Kconfig b/src/drivers/ti/tps65913/Kconfig index e2f023576e..2fc980622b 100644 --- a/src/drivers/ti/tps65913/Kconfig +++ b/src/drivers/ti/tps65913/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only config DRIVERS_TI_TPS65913_RTC diff --git a/src/drivers/ti/tps65913/Makefile.inc b/src/drivers/ti/tps65913/Makefile.inc index 3c2b62cdf3..acadae9282 100644 --- a/src/drivers/ti/tps65913/Makefile.inc +++ b/src/drivers/ti/tps65913/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_DRIVERS_TI_TPS65913_RTC) += tps65913rtc.c diff --git a/src/drivers/vpd/Kconfig b/src/drivers/vpd/Kconfig index a4f9c1808f..eda9130dd4 100644 --- a/src/drivers/vpd/Kconfig +++ b/src/drivers/vpd/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only config VPD diff --git a/src/ec/hp/kbc1126/Kconfig b/src/ec/hp/kbc1126/Kconfig index 93f8545bdd..924501fbeb 100644 --- a/src/ec/hp/kbc1126/Kconfig +++ b/src/ec/hp/kbc1126/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only config EC_HP_KBC1126 diff --git a/src/ec/hp/kbc1126/Makefile.inc b/src/ec/hp/kbc1126/Makefile.inc index c9534f7390..54e8b2afc3 100644 --- a/src/ec/hp/kbc1126/Makefile.inc +++ b/src/ec/hp/kbc1126/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_EC_HP_KBC1126),y) diff --git a/src/ec/roda/it8518/Kconfig b/src/ec/roda/it8518/Kconfig index 3c63c98953..e8b914acb8 100644 --- a/src/ec/roda/it8518/Kconfig +++ b/src/ec/roda/it8518/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only config EC_RODA_IT8518 diff --git a/src/ec/roda/it8518/Makefile.inc b/src/ec/roda/it8518/Makefile.inc index 824f1bcf0d..e5b483f7a6 100644 --- a/src/ec/roda/it8518/Makefile.inc +++ b/src/ec/roda/it8518/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_EC_RODA_IT8518) += ec.c diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index b6d318e7a3..6511c0c328 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only subdirs-y += gnat diff --git a/src/lib/gnat/Makefile.inc b/src/lib/gnat/Makefile.inc index 1318ebde73..e7405648d6 100644 --- a/src/lib/gnat/Makefile.inc +++ b/src/lib/gnat/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only define libgnat-template diff --git a/src/mainboard/amd/gardenia/Makefile.inc b/src/mainboard/amd/gardenia/Makefile.inc index 78011e97a3..a2e4aa5721 100644 --- a/src/mainboard/amd/gardenia/Makefile.inc +++ b/src/mainboard/amd/gardenia/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock/bootblock.c diff --git a/src/mainboard/amd/inagua/Makefile.inc b/src/mainboard/amd/inagua/Makefile.inc index 49e8b4baa4..9655909056 100644 --- a/src/mainboard/amd/inagua/Makefile.inc +++ b/src/mainboard/amd/inagua/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_AHCI_BIOS),y) diff --git a/src/mainboard/amd/olivehill/Makefile.inc b/src/mainboard/amd/olivehill/Makefile.inc index db9b1b68cb..549801d78f 100644 --- a/src/mainboard/amd/olivehill/Makefile.inc +++ b/src/mainboard/amd/olivehill/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/amd/padmelon/Makefile.inc b/src/mainboard/amd/padmelon/Makefile.inc index 43ba88d38d..30fd82c293 100644 --- a/src/mainboard/amd/padmelon/Makefile.inc +++ b/src/mainboard/amd/padmelon/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock/bootblock.c diff --git a/src/mainboard/amd/parmer/Makefile.inc b/src/mainboard/amd/parmer/Makefile.inc index db9b1b68cb..549801d78f 100644 --- a/src/mainboard/amd/parmer/Makefile.inc +++ b/src/mainboard/amd/parmer/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/amd/persimmon/Makefile.inc b/src/mainboard/amd/persimmon/Makefile.inc index 49e8b4baa4..9655909056 100644 --- a/src/mainboard/amd/persimmon/Makefile.inc +++ b/src/mainboard/amd/persimmon/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_AHCI_BIOS),y) diff --git a/src/mainboard/amd/south_station/Makefile.inc b/src/mainboard/amd/south_station/Makefile.inc index db9b1b68cb..549801d78f 100644 --- a/src/mainboard/amd/south_station/Makefile.inc +++ b/src/mainboard/amd/south_station/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/amd/thatcher/Makefile.inc b/src/mainboard/amd/thatcher/Makefile.inc index db9b1b68cb..549801d78f 100644 --- a/src/mainboard/amd/thatcher/Makefile.inc +++ b/src/mainboard/amd/thatcher/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/amd/union_station/Makefile.inc b/src/mainboard/amd/union_station/Makefile.inc index db9b1b68cb..549801d78f 100644 --- a/src/mainboard/amd/union_station/Makefile.inc +++ b/src/mainboard/amd/union_station/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/aopen/dxplplusu/Makefile.inc b/src/mainboard/aopen/dxplplusu/Makefile.inc index d838ba6840..d604d021c5 100644 --- a/src/mainboard/aopen/dxplplusu/Makefile.inc +++ b/src/mainboard/aopen/dxplplusu/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/apple/macbook21/cmos.layout b/src/mainboard/apple/macbook21/cmos.layout index 248f05453e..2df318f036 100644 --- a/src/mainboard/apple/macbook21/cmos.layout +++ b/src/mainboard/apple/macbook21/cmos.layout @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/apple/macbookair4_2/cmos.layout b/src/mainboard/apple/macbookair4_2/cmos.layout index df95bf88e1..f4ecb1ecdf 100644 --- a/src/mainboard/apple/macbookair4_2/cmos.layout +++ b/src/mainboard/apple/macbookair4_2/cmos.layout @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/asrock/Kconfig b/src/mainboard/asrock/Kconfig index f6e9a0bbd7..3fe439728d 100644 --- a/src/mainboard/asrock/Kconfig +++ b/src/mainboard/asrock/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if VENDOR_ASROCK diff --git a/src/mainboard/asrock/b75pro3-m/Makefile.inc b/src/mainboard/asrock/b75pro3-m/Makefile.inc index 58d309e956..e4b6fbf0f0 100644 --- a/src/mainboard/asrock/b75pro3-m/Makefile.inc +++ b/src/mainboard/asrock/b75pro3-m/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c diff --git a/src/mainboard/asrock/e350m1/Makefile.inc b/src/mainboard/asrock/e350m1/Makefile.inc index db9b1b68cb..549801d78f 100644 --- a/src/mainboard/asrock/e350m1/Makefile.inc +++ b/src/mainboard/asrock/e350m1/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/asrock/g41c-gs/cmos.layout b/src/mainboard/asrock/g41c-gs/cmos.layout index de5066b56f..f90467cdb9 100644 --- a/src/mainboard/asrock/g41c-gs/cmos.layout +++ b/src/mainboard/asrock/g41c-gs/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/asrock/h110m/Makefile.inc b/src/mainboard/asrock/h110m/Makefile.inc index edf0e1088a..e8ff53e6e8 100644 --- a/src/mainboard/asrock/h110m/Makefile.inc +++ b/src/mainboard/asrock/h110m/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only subdirs-y += spd diff --git a/src/mainboard/asrock/h110m/cmos.layout b/src/mainboard/asrock/h110m/cmos.layout index 588a27b024..8c2244fa55 100644 --- a/src/mainboard/asrock/h110m/cmos.layout +++ b/src/mainboard/asrock/h110m/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/asrock/h81m-hds/cmos.layout b/src/mainboard/asrock/h81m-hds/cmos.layout index 42fac4b778..e03d040796 100644 --- a/src/mainboard/asrock/h81m-hds/cmos.layout +++ b/src/mainboard/asrock/h81m-hds/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/asrock/imb-a180/Makefile.inc b/src/mainboard/asrock/imb-a180/Makefile.inc index db9b1b68cb..549801d78f 100644 --- a/src/mainboard/asrock/imb-a180/Makefile.inc +++ b/src/mainboard/asrock/imb-a180/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index beaa4621a7..4643fc916d 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if VENDOR_ASUS diff --git a/src/mainboard/asus/am1i-a/Makefile.inc b/src/mainboard/asus/am1i-a/Makefile.inc index db9b1b68cb..549801d78f 100644 --- a/src/mainboard/asus/am1i-a/Makefile.inc +++ b/src/mainboard/asus/am1i-a/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/asus/f2a85-m/Makefile.inc b/src/mainboard/asus/f2a85-m/Makefile.inc index db9b1b68cb..549801d78f 100644 --- a/src/mainboard/asus/f2a85-m/Makefile.inc +++ b/src/mainboard/asus/f2a85-m/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/asus/h61m-cs/cmos.layout b/src/mainboard/asus/h61m-cs/cmos.layout index d99f6dbe30..1860a78326 100644 --- a/src/mainboard/asus/h61m-cs/cmos.layout +++ b/src/mainboard/asus/h61m-cs/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/asus/maximus_iv_gene-z/cmos.layout b/src/mainboard/asus/maximus_iv_gene-z/cmos.layout index f5c7aad06b..c8c53e745c 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/cmos.layout +++ b/src/mainboard/asus/maximus_iv_gene-z/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/asus/p5gc-mx/cmos.layout b/src/mainboard/asus/p5gc-mx/cmos.layout index 6c50a44fe4..a7c4b7dba7 100644 --- a/src/mainboard/asus/p5gc-mx/cmos.layout +++ b/src/mainboard/asus/p5gc-mx/cmos.layout @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/asus/p5qc/Makefile.inc b/src/mainboard/asus/p5qc/Makefile.inc index 87118a8f68..eeeef1e7ed 100644 --- a/src/mainboard/asus/p5qc/Makefile.inc +++ b/src/mainboard/asus/p5qc/Makefile.inc @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only CONFIG_GPIO_C:=$(call strip_quotes, $(CONFIG_GPIO_C)) diff --git a/src/mainboard/asus/p5qc/cmos.layout b/src/mainboard/asus/p5qc/cmos.layout index 2073ee458e..79f7347410 100644 --- a/src/mainboard/asus/p5qc/cmos.layout +++ b/src/mainboard/asus/p5qc/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/asus/p5ql-em/Makefile.inc b/src/mainboard/asus/p5ql-em/Makefile.inc index 1adafa5ecd..097c9f9aa9 100644 --- a/src/mainboard/asus/p5ql-em/Makefile.inc +++ b/src/mainboard/asus/p5ql-em/Makefile.inc @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only bootblock-y += early_init.c diff --git a/src/mainboard/asus/p5ql-em/cmos.layout b/src/mainboard/asus/p5ql-em/cmos.layout index 648f640a03..e98886258b 100644 --- a/src/mainboard/asus/p5ql-em/cmos.layout +++ b/src/mainboard/asus/p5ql-em/cmos.layout @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/asus/p5qpl-am/cmos.layout b/src/mainboard/asus/p5qpl-am/cmos.layout index 1b1ce10f3d..4905f1d133 100644 --- a/src/mainboard/asus/p5qpl-am/cmos.layout +++ b/src/mainboard/asus/p5qpl-am/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/asus/p8h61-m_lx/cmos.layout b/src/mainboard/asus/p8h61-m_lx/cmos.layout index dc55ab31b2..2aef2ac876 100644 --- a/src/mainboard/asus/p8h61-m_lx/cmos.layout +++ b/src/mainboard/asus/p8h61-m_lx/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/asus/p8h61-m_pro/cmos.layout b/src/mainboard/asus/p8h61-m_pro/cmos.layout index d99f6dbe30..1860a78326 100644 --- a/src/mainboard/asus/p8h61-m_pro/cmos.layout +++ b/src/mainboard/asus/p8h61-m_pro/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/asus/p8z77-m_pro/cmos.default b/src/mainboard/asus/p8z77-m_pro/cmos.default index 039264db19..6811b0b076 100644 --- a/src/mainboard/asus/p8z77-m_pro/cmos.default +++ b/src/mainboard/asus/p8z77-m_pro/cmos.default @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only boot_option=Fallback diff --git a/src/mainboard/asus/p8z77-m_pro/cmos.layout b/src/mainboard/asus/p8z77-m_pro/cmos.layout index 48ee05c637..1b82ffde13 100644 --- a/src/mainboard/asus/p8z77-m_pro/cmos.layout +++ b/src/mainboard/asus/p8z77-m_pro/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/bap/Kconfig b/src/mainboard/bap/Kconfig index a3ade8168d..a262952cf6 100644 --- a/src/mainboard/bap/Kconfig +++ b/src/mainboard/bap/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if VENDOR_BAP diff --git a/src/mainboard/bap/ode_e20XX/Makefile.inc b/src/mainboard/bap/ode_e20XX/Makefile.inc index d43fd7365e..5e83e6586f 100644 --- a/src/mainboard/bap/ode_e20XX/Makefile.inc +++ b/src/mainboard/bap/ode_e20XX/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/bap/ode_e21XX/Makefile.inc b/src/mainboard/bap/ode_e21XX/Makefile.inc index 148adac631..2abdc71607 100644 --- a/src/mainboard/bap/ode_e21XX/Makefile.inc +++ b/src/mainboard/bap/ode_e21XX/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only romstage-y += BiosCallOuts.c diff --git a/src/mainboard/biostar/Kconfig b/src/mainboard/biostar/Kconfig index 74b6207104..1122c43563 100644 --- a/src/mainboard/biostar/Kconfig +++ b/src/mainboard/biostar/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if VENDOR_BIOSTAR diff --git a/src/mainboard/biostar/a68n_5200/Makefile.inc b/src/mainboard/biostar/a68n_5200/Makefile.inc index db9b1b68cb..549801d78f 100644 --- a/src/mainboard/biostar/a68n_5200/Makefile.inc +++ b/src/mainboard/biostar/a68n_5200/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/biostar/am1ml/Makefile.inc b/src/mainboard/biostar/am1ml/Makefile.inc index db9b1b68cb..549801d78f 100644 --- a/src/mainboard/biostar/am1ml/Makefile.inc +++ b/src/mainboard/biostar/am1ml/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/cavium/Kconfig b/src/mainboard/cavium/Kconfig index 2db95ce991..332ecd916a 100644 --- a/src/mainboard/cavium/Kconfig +++ b/src/mainboard/cavium/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if VENDOR_CAVIUM diff --git a/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc b/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc index 344193d139..c73bc334c4 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc +++ b/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/elmex/pcm205400/Makefile.inc b/src/mainboard/elmex/pcm205400/Makefile.inc index 49e8b4baa4..9655909056 100644 --- a/src/mainboard/elmex/pcm205400/Makefile.inc +++ b/src/mainboard/elmex/pcm205400/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_AHCI_BIOS),y) diff --git a/src/mainboard/emulation/qemu-aarch64/Makefile.inc b/src/mainboard/emulation/qemu-aarch64/Makefile.inc index 7858921ccf..754656ffa2 100644 --- a/src/mainboard/emulation/qemu-aarch64/Makefile.inc +++ b/src/mainboard/emulation/qemu-aarch64/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-or-later bootblock-y += bootblock.c diff --git a/src/mainboard/emulation/qemu-armv7/Makefile.inc b/src/mainboard/emulation/qemu-armv7/Makefile.inc index e5ed6b3d5b..1b9e997ce1 100644 --- a/src/mainboard/emulation/qemu-armv7/Makefile.inc +++ b/src/mainboard/emulation/qemu-armv7/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += romstage.c diff --git a/src/mainboard/emulation/qemu-power8/Makefile.inc b/src/mainboard/emulation/qemu-power8/Makefile.inc index b8b39be758..b713df71c9 100644 --- a/src/mainboard/emulation/qemu-power8/Makefile.inc +++ b/src/mainboard/emulation/qemu-power8/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc index 0a75a01d3b..7ca7e5930c 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.inc +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += uart.c diff --git a/src/mainboard/emulation/spike-riscv/Makefile.inc b/src/mainboard/emulation/spike-riscv/Makefile.inc index 2a47a7b036..6d2911662d 100644 --- a/src/mainboard/emulation/spike-riscv/Makefile.inc +++ b/src/mainboard/emulation/spike-riscv/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += uart.c diff --git a/src/mainboard/facebook/fbg1701/Makefile.inc b/src/mainboard/facebook/fbg1701/Makefile.inc index fbc7a2ee42..9a46d7942d 100644 --- a/src/mainboard/facebook/fbg1701/Makefile.inc +++ b/src/mainboard/facebook/fbg1701/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBOOT)),) diff --git a/src/mainboard/facebook/fbg1701/cmos.layout b/src/mainboard/facebook/fbg1701/cmos.layout index 846e8b2b11..f80f2c597f 100644 --- a/src/mainboard/facebook/fbg1701/cmos.layout +++ b/src/mainboard/facebook/fbg1701/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/facebook/monolith/Makefile.inc b/src/mainboard/facebook/monolith/Makefile.inc index 37c5f495e6..3b6f881021 100644 --- a/src/mainboard/facebook/monolith/Makefile.inc +++ b/src/mainboard/facebook/monolith/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only subdirs-y += spd diff --git a/src/mainboard/facebook/monolith/cmos.layout b/src/mainboard/facebook/monolith/cmos.layout index 9149dbe04f..61c34f3a94 100644 --- a/src/mainboard/facebook/monolith/cmos.layout +++ b/src/mainboard/facebook/monolith/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/facebook/monolith/spd/Makefile.inc b/src/mainboard/facebook/monolith/spd/Makefile.inc index 4b201f52a2..1a7ff99875 100644 --- a/src/mainboard/facebook/monolith/spd/Makefile.inc +++ b/src/mainboard/facebook/monolith/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += spd_util.c diff --git a/src/mainboard/foxconn/Kconfig b/src/mainboard/foxconn/Kconfig index 7e88a3647f..13a6b85819 100644 --- a/src/mainboard/foxconn/Kconfig +++ b/src/mainboard/foxconn/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if VENDOR_FOXCONN diff --git a/src/mainboard/foxconn/d41s/cmos.layout b/src/mainboard/foxconn/d41s/cmos.layout index 14c10a775d..0a329956af 100644 --- a/src/mainboard/foxconn/d41s/cmos.layout +++ b/src/mainboard/foxconn/d41s/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/foxconn/g41s-k/cmos.layout b/src/mainboard/foxconn/g41s-k/cmos.layout index de5066b56f..f90467cdb9 100644 --- a/src/mainboard/foxconn/g41s-k/cmos.layout +++ b/src/mainboard/foxconn/g41s-k/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/getac/Kconfig b/src/mainboard/getac/Kconfig index 463356f134..68447c5b02 100644 --- a/src/mainboard/getac/Kconfig +++ b/src/mainboard/getac/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if VENDOR_GETAC diff --git a/src/mainboard/getac/p470/Makefile.inc b/src/mainboard/getac/p470/Makefile.inc index 780390cdd8..95250e28a6 100644 --- a/src/mainboard/getac/p470/Makefile.inc +++ b/src/mainboard/getac/p470/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-y += cstates.c diff --git a/src/mainboard/getac/p470/cmos.layout b/src/mainboard/getac/p470/cmos.layout index cd84fa0cf2..5f60dc98af 100644 --- a/src/mainboard/getac/p470/cmos.layout +++ b/src/mainboard/getac/p470/cmos.layout @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/gigabyte/Kconfig b/src/mainboard/gigabyte/Kconfig index e18a91d474..a4d41191ff 100644 --- a/src/mainboard/gigabyte/Kconfig +++ b/src/mainboard/gigabyte/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if VENDOR_GIGABYTE diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout b/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout index b311022912..e0d6ec5244 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc index a475f4ebb0..5dcf9e206a 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += variants/$(VARIANT_DIR)/gpio.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout index d99f6dbe30..1860a78326 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout +++ b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout index a3fa3a3cc3..79094e6009 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/gigabyte/ga-h61m-series/cmos.layout b/src/mainboard/gigabyte/ga-h61m-series/cmos.layout index d99f6dbe30..1860a78326 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/cmos.layout +++ b/src/mainboard/gigabyte/ga-h61m-series/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/gizmosphere/Kconfig b/src/mainboard/gizmosphere/Kconfig index 4cef41d933..245bf52e89 100644 --- a/src/mainboard/gizmosphere/Kconfig +++ b/src/mainboard/gizmosphere/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if VENDOR_GIZMOSPHERE diff --git a/src/mainboard/gizmosphere/gizmo/Makefile.inc b/src/mainboard/gizmosphere/gizmo/Makefile.inc index 83912e2316..1ae2f7b31e 100644 --- a/src/mainboard/gizmosphere/gizmo/Makefile.inc +++ b/src/mainboard/gizmosphere/gizmo/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_AHCI_BIOS),y) diff --git a/src/mainboard/gizmosphere/gizmo2/Makefile.inc b/src/mainboard/gizmosphere/gizmo2/Makefile.inc index 710b80c4f1..653dcc3529 100644 --- a/src/mainboard/gizmosphere/gizmo2/Makefile.inc +++ b/src/mainboard/gizmosphere/gizmo2/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index eb5ba6cfc1..48b6e52cf2 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if VENDOR_GOOGLE diff --git a/src/mainboard/google/auron/Makefile.inc b/src/mainboard/google/auron/Makefile.inc index 0d2f404176..7d31655177 100644 --- a/src/mainboard/google/auron/Makefile.inc +++ b/src/mainboard/google/auron/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c diff --git a/src/mainboard/google/auron/cmos.layout b/src/mainboard/google/auron/cmos.layout index 57032a19ce..da1b185c7e 100644 --- a/src/mainboard/google/auron/cmos.layout +++ b/src/mainboard/google/auron/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc b/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc index a9b7392982..a446268132 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += spd.c diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc b/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc index a9b7392982..a446268132 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += spd.c diff --git a/src/mainboard/google/auron/variants/buddy/spd/Makefile.inc b/src/mainboard/google/auron/variants/buddy/spd/Makefile.inc index e4f1f10097..6ecc95b482 100644 --- a/src/mainboard/google/auron/variants/buddy/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/buddy/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += spd.c diff --git a/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc b/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc index 527618a5fe..a6a8232f48 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += spd.c diff --git a/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc b/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc index cb982857d6..c136955d4c 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += spd.c diff --git a/src/mainboard/google/auron/variants/samus/Makefile.inc b/src/mainboard/google/auron/variants/samus/Makefile.inc index 0407e0ab11..e43d21be11 100644 --- a/src/mainboard/google/auron/variants/samus/Makefile.inc +++ b/src/mainboard/google/auron/variants/samus/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += board_version.c diff --git a/src/mainboard/google/auron/variants/samus/spd/Makefile.inc b/src/mainboard/google/auron/variants/samus/spd/Makefile.inc index 60fb157018..aaf9b36b3a 100644 --- a/src/mainboard/google/auron/variants/samus/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/samus/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += spd.c diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc index 2da7acd658..0b448fc697 100644 --- a/src/mainboard/google/beltino/Makefile.inc +++ b/src/mainboard/google/beltino/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout index 57032a19ce..da1b185c7e 100644 --- a/src/mainboard/google/beltino/cmos.layout +++ b/src/mainboard/google/beltino/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/google/butterfly/Makefile.inc b/src/mainboard/google/butterfly/Makefile.inc index 2827d58a00..342c9f7dde 100644 --- a/src/mainboard/google/butterfly/Makefile.inc +++ b/src/mainboard/google/butterfly/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-y += ec.c diff --git a/src/mainboard/google/butterfly/cmos.layout b/src/mainboard/google/butterfly/cmos.layout index 87b8785821..bee1e86fe5 100644 --- a/src/mainboard/google/butterfly/cmos.layout +++ b/src/mainboard/google/butterfly/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/google/cheza/Makefile.inc b/src/mainboard/google/cheza/Makefile.inc index 21de91468a..e54aefb0e1 100644 --- a/src/mainboard/google/cheza/Makefile.inc +++ b/src/mainboard/google/cheza/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += boardid.c diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc index ef9645b55a..1ecc55e697 100644 --- a/src/mainboard/google/cyan/Makefile.inc +++ b/src/mainboard/google/cyan/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c diff --git a/src/mainboard/google/cyan/cmos.layout b/src/mainboard/google/cyan/cmos.layout index 588a27b024..8c2244fa55 100644 --- a/src/mainboard/google/cyan/cmos.layout +++ b/src/mainboard/google/cyan/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/google/cyan/variants/banon/Makefile.inc b/src/mainboard/google/cyan/variants/banon/Makefile.inc index f21fe0679b..5e3cf38f90 100644 --- a/src/mainboard/google/cyan/variants/banon/Makefile.inc +++ b/src/mainboard/google/cyan/variants/banon/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += romstage.c diff --git a/src/mainboard/google/cyan/variants/celes/Makefile.inc b/src/mainboard/google/cyan/variants/celes/Makefile.inc index 5e5817e9de..11f918b79a 100644 --- a/src/mainboard/google/cyan/variants/celes/Makefile.inc +++ b/src/mainboard/google/cyan/variants/celes/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += spd_util.c diff --git a/src/mainboard/google/cyan/variants/cyan/Makefile.inc b/src/mainboard/google/cyan/variants/cyan/Makefile.inc index 47774af052..a1521d4234 100644 --- a/src/mainboard/google/cyan/variants/cyan/Makefile.inc +++ b/src/mainboard/google/cyan/variants/cyan/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += spd_util.c diff --git a/src/mainboard/google/cyan/variants/edgar/Makefile.inc b/src/mainboard/google/cyan/variants/edgar/Makefile.inc index 3771bfc061..b3651eac90 100644 --- a/src/mainboard/google/cyan/variants/edgar/Makefile.inc +++ b/src/mainboard/google/cyan/variants/edgar/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += romstage.c diff --git a/src/mainboard/google/cyan/variants/kefka/Makefile.inc b/src/mainboard/google/cyan/variants/kefka/Makefile.inc index ebf6d67d11..ff707b4dee 100644 --- a/src/mainboard/google/cyan/variants/kefka/Makefile.inc +++ b/src/mainboard/google/cyan/variants/kefka/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += romstage.c diff --git a/src/mainboard/google/cyan/variants/reks/Makefile.inc b/src/mainboard/google/cyan/variants/reks/Makefile.inc index 58fd136f91..b45a2b229e 100644 --- a/src/mainboard/google/cyan/variants/reks/Makefile.inc +++ b/src/mainboard/google/cyan/variants/reks/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += romstage.c diff --git a/src/mainboard/google/cyan/variants/relm/Makefile.inc b/src/mainboard/google/cyan/variants/relm/Makefile.inc index 655ff3a978..3de47937e6 100644 --- a/src/mainboard/google/cyan/variants/relm/Makefile.inc +++ b/src/mainboard/google/cyan/variants/relm/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += romstage.c diff --git a/src/mainboard/google/cyan/variants/setzer/Makefile.inc b/src/mainboard/google/cyan/variants/setzer/Makefile.inc index efdbc536cd..d99926b203 100644 --- a/src/mainboard/google/cyan/variants/setzer/Makefile.inc +++ b/src/mainboard/google/cyan/variants/setzer/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += romstage.c diff --git a/src/mainboard/google/cyan/variants/terra/Makefile.inc b/src/mainboard/google/cyan/variants/terra/Makefile.inc index 241dc51ca1..af07a93bc7 100644 --- a/src/mainboard/google/cyan/variants/terra/Makefile.inc +++ b/src/mainboard/google/cyan/variants/terra/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += romstage.c diff --git a/src/mainboard/google/cyan/variants/ultima/Makefile.inc b/src/mainboard/google/cyan/variants/ultima/Makefile.inc index b2fe6703af..10500c43c2 100644 --- a/src/mainboard/google/cyan/variants/ultima/Makefile.inc +++ b/src/mainboard/google/cyan/variants/ultima/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += spd_util.c diff --git a/src/mainboard/google/cyan/variants/wizpig/Makefile.inc b/src/mainboard/google/cyan/variants/wizpig/Makefile.inc index 7913cbd657..aa1621addb 100644 --- a/src/mainboard/google/cyan/variants/wizpig/Makefile.inc +++ b/src/mainboard/google/cyan/variants/wizpig/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += spd_util.c diff --git a/src/mainboard/google/daisy/Makefile.inc b/src/mainboard/google/daisy/Makefile.inc index 667e64d7bc..9faa2e09ef 100644 --- a/src/mainboard/google/daisy/Makefile.inc +++ b/src/mainboard/google/daisy/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += wakeup.c diff --git a/src/mainboard/google/dedede/board_info.c b/src/mainboard/google/dedede/board_info.c index 6476776be8..38d722c16c 100644 --- a/src/mainboard/google/dedede/board_info.c +++ b/src/mainboard/google/dedede/board_info.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/dedede/bootblock.c b/src/mainboard/google/dedede/bootblock.c index ff9c5ed9f5..328480e3bc 100644 --- a/src/mainboard/google/dedede/bootblock.c +++ b/src/mainboard/google/dedede/bootblock.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/dedede/chromeos.c b/src/mainboard/google/dedede/chromeos.c index 61d9ccd474..0b77ebbd75 100644 --- a/src/mainboard/google/dedede/chromeos.c +++ b/src/mainboard/google/dedede/chromeos.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 6137f3bd0a..dce0bf35f0 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/dedede/ec.c b/src/mainboard/google/dedede/ec.c index 44adbb900f..6badbb2076 100644 --- a/src/mainboard/google/dedede/ec.c +++ b/src/mainboard/google/dedede/ec.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index 2069fbd4e3..c503a86a6e 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c index 80640cdcf7..af79c809a8 100644 --- a/src/mainboard/google/dedede/romstage.c +++ b/src/mainboard/google/dedede/romstage.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/dedede/smihandler.c b/src/mainboard/google/dedede/smihandler.c index 8a6dcceb9e..0254810ef3 100644 --- a/src/mainboard/google/dedede/smihandler.c +++ b/src/mainboard/google/dedede/smihandler.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/dedede/spd/Makefile.inc b/src/mainboard/google/dedede/spd/Makefile.inc index 90b1fc20bd..24c34651bc 100644 --- a/src/mainboard/google/dedede/spd/Makefile.inc +++ b/src/mainboard/google/dedede/spd/Makefile.inc @@ -1,8 +1,4 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-or-later -## ifneq ($(SPD_SOURCES),) SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 051c71fc27..ca28e3d525 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/dedede/variants/baseboard/memory.c b/src/mainboard/google/dedede/variants/baseboard/memory.c index 82d72959bc..dc43ea59b5 100644 --- a/src/mainboard/google/dedede/variants/baseboard/memory.c +++ b/src/mainboard/google/dedede/variants/baseboard/memory.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc index f1e5330c71..6101f1583d 100644 --- a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc @@ -1,8 +1,4 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-or-later -## SPD_SOURCES = Micron_MT53E512M32D2NP_2GB #0b0000 SPD_SOURCES += empty #0b0001 diff --git a/src/mainboard/google/dedede/variants/waddledee/memory.c b/src/mainboard/google/dedede/variants/waddledee/memory.c index 94099c4d6e..2c81650887 100644 --- a/src/mainboard/google/dedede/variants/waddledee/memory.c +++ b/src/mainboard/google/dedede/variants/waddledee/memory.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc index 4fd530f295..c0553b55f0 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc @@ -1,8 +1,4 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-or-later -## SPD_SOURCES = empty #0b0000 SPD_SOURCES += Micron_MT53E512M32D2NP_2GB #0b0001 diff --git a/src/mainboard/google/dedede/variants/waddledoo/memory.c b/src/mainboard/google/dedede/variants/waddledoo/memory.c index 94099c4d6e..2c81650887 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/memory.c +++ b/src/mainboard/google/dedede/variants/waddledoo/memory.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/dedede/variants/wheelie/Makefile.inc b/src/mainboard/google/dedede/variants/wheelie/Makefile.inc index af8e4fe4b7..6c8c913302 100644 --- a/src/mainboard/google/dedede/variants/wheelie/Makefile.inc +++ b/src/mainboard/google/dedede/variants/wheelie/Makefile.inc @@ -1,7 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-or-later -## SPD_SOURCES = Micron_MT53E512M32D2NP_2GB #0b0000 diff --git a/src/mainboard/google/deltaur/Makefile.inc b/src/mainboard/google/deltaur/Makefile.inc index f62fa5e4c4..ab22a36d9f 100644 --- a/src/mainboard/google/deltaur/Makefile.inc +++ b/src/mainboard/google/deltaur/Makefile.inc @@ -1,7 +1,4 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-or-later -## bootblock-y += bootblock.c bootblock-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/deltaur/bootblock.c b/src/mainboard/google/deltaur/bootblock.c index 5e5c462ee1..9cd427eace 100644 --- a/src/mainboard/google/deltaur/bootblock.c +++ b/src/mainboard/google/deltaur/bootblock.c @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/deltaur/chromeos.c b/src/mainboard/google/deltaur/chromeos.c index 89a48ce418..9d3929e1df 100644 --- a/src/mainboard/google/deltaur/chromeos.c +++ b/src/mainboard/google/deltaur/chromeos.c @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/deltaur/dsdt.asl b/src/mainboard/google/deltaur/dsdt.asl index 03067ae260..b439d06793 100644 --- a/src/mainboard/google/deltaur/dsdt.asl +++ b/src/mainboard/google/deltaur/dsdt.asl @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include "variant/ec.h" diff --git a/src/mainboard/google/deltaur/ec.c b/src/mainboard/google/deltaur/ec.c index 7bf7b8c1b8..ae441fd3f4 100644 --- a/src/mainboard/google/deltaur/ec.c +++ b/src/mainboard/google/deltaur/ec.c @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/deltaur/mainboard.c b/src/mainboard/google/deltaur/mainboard.c index 6dd018ecf1..faca003ab7 100644 --- a/src/mainboard/google/deltaur/mainboard.c +++ b/src/mainboard/google/deltaur/mainboard.c @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/deltaur/romstage.c b/src/mainboard/google/deltaur/romstage.c index 97a45eb23b..c04f6fb1a9 100644 --- a/src/mainboard/google/deltaur/romstage.c +++ b/src/mainboard/google/deltaur/romstage.c @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/deltaur/smihandler.c b/src/mainboard/google/deltaur/smihandler.c index 15373823bb..388a37f00b 100644 --- a/src/mainboard/google/deltaur/smihandler.c +++ b/src/mainboard/google/deltaur/smihandler.c @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/deltaur/variants/baseboard/Makefile.inc b/src/mainboard/google/deltaur/variants/baseboard/Makefile.inc index 4334939938..af00674177 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/deltaur/variants/baseboard/Makefile.inc @@ -1,7 +1,4 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-or-later -## bootblock-y += gpio.c diff --git a/src/mainboard/google/deltaur/variants/baseboard/gpio.c b/src/mainboard/google/deltaur/variants/baseboard/gpio.c index 432b9f88d8..0715f275f5 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/gpio.c +++ b/src/mainboard/google/deltaur/variants/baseboard/gpio.c @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/deltaur/variants/baseboard/sku.c b/src/mainboard/google/deltaur/variants/baseboard/sku.c index a6c0e01b30..fb19e3c67f 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/sku.c +++ b/src/mainboard/google/deltaur/variants/baseboard/sku.c @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/deltaur/variants/deltan/Makefile.inc b/src/mainboard/google/deltaur/variants/deltan/Makefile.inc index 13572c1be2..596b0a9f34 100644 --- a/src/mainboard/google/deltaur/variants/deltan/Makefile.inc +++ b/src/mainboard/google/deltaur/variants/deltan/Makefile.inc @@ -1,8 +1,4 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-or-later -## bootblock-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/deltaur/variants/deltan/gpio.c b/src/mainboard/google/deltaur/variants/deltan/gpio.c index b9c762fa40..4a163b2348 100644 --- a/src/mainboard/google/deltaur/variants/deltan/gpio.c +++ b/src/mainboard/google/deltaur/variants/deltan/gpio.c @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/deltaur/variants/deltan/memory.c b/src/mainboard/google/deltaur/variants/deltan/memory.c index 00e254b5c9..2184f9b16f 100644 --- a/src/mainboard/google/deltaur/variants/deltan/memory.c +++ b/src/mainboard/google/deltaur/variants/deltan/memory.c @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/deltaur/variants/deltaur/Makefile.inc b/src/mainboard/google/deltaur/variants/deltaur/Makefile.inc index 13572c1be2..596b0a9f34 100644 --- a/src/mainboard/google/deltaur/variants/deltaur/Makefile.inc +++ b/src/mainboard/google/deltaur/variants/deltaur/Makefile.inc @@ -1,8 +1,4 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-or-later -## bootblock-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/deltaur/variants/deltaur/gpio.c b/src/mainboard/google/deltaur/variants/deltaur/gpio.c index bb2696035f..def3b1ea8c 100644 --- a/src/mainboard/google/deltaur/variants/deltaur/gpio.c +++ b/src/mainboard/google/deltaur/variants/deltaur/gpio.c @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/deltaur/variants/deltaur/memory.c b/src/mainboard/google/deltaur/variants/deltaur/memory.c index 3bd4f997bb..68c8d0e991 100644 --- a/src/mainboard/google/deltaur/variants/deltaur/memory.c +++ b/src/mainboard/google/deltaur/variants/deltaur/memory.c @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/dragonegg/Makefile.inc b/src/mainboard/google/dragonegg/Makefile.inc index e4036708bb..818df63c84 100644 --- a/src/mainboard/google/dragonegg/Makefile.inc +++ b/src/mainboard/google/dragonegg/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/google/dragonegg/spd/Makefile.inc b/src/mainboard/google/dragonegg/spd/Makefile.inc index e14253960b..b5dc608707 100644 --- a/src/mainboard/google/dragonegg/spd/Makefile.inc +++ b/src/mainboard/google/dragonegg/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc b/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc index 267f3cf3dd..fb7eaf11e9 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c diff --git a/src/mainboard/google/drallion/Makefile.inc b/src/mainboard/google/drallion/Makefile.inc index 2ca65ebf16..4c8b888aad 100644 --- a/src/mainboard/google/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/google/drallion/spd/Makefile.inc b/src/mainboard/google/drallion/spd/Makefile.inc index 10df1051cc..99aea9c827 100644 --- a/src/mainboard/google/drallion/spd/Makefile.inc +++ b/src/mainboard/google/drallion/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/drallion/variants/drallion/Makefile.inc b/src/mainboard/google/drallion/variants/drallion/Makefile.inc index 113c94fa2f..effd545c64 100644 --- a/src/mainboard/google/drallion/variants/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/variants/drallion/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ## GPP_F12-F16 indicates mem_id to match specific spd file diff --git a/src/mainboard/google/eve/Makefile.inc b/src/mainboard/google/eve/Makefile.inc index fa93ec6162..ef8b0bd110 100644 --- a/src/mainboard/google/eve/Makefile.inc +++ b/src/mainboard/google/eve/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only subdirs-y += spd diff --git a/src/mainboard/google/eve/spd/Makefile.inc b/src/mainboard/google/eve/spd/Makefile.inc index 2a94d9cfec..767281504d 100644 --- a/src/mainboard/google/eve/spd/Makefile.inc +++ b/src/mainboard/google/eve/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += spd.c diff --git a/src/mainboard/google/fizz/Makefile.inc b/src/mainboard/google/fizz/Makefile.inc index 4d28efd033..13bf370c40 100644 --- a/src/mainboard/google/fizz/Makefile.inc +++ b/src/mainboard/google/fizz/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/google/foster/Makefile.inc b/src/mainboard/google/foster/Makefile.inc index f40d0a92ce..1b576a9512 100644 --- a/src/mainboard/google/foster/Makefile.inc +++ b/src/mainboard/google/foster/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # Add a handler for BCT config files diff --git a/src/mainboard/google/foster/bct/Makefile.inc b/src/mainboard/google/foster/bct/Makefile.inc index 93bba4a177..ab16334798 100644 --- a/src/mainboard/google/foster/bct/Makefile.inc +++ b/src/mainboard/google/foster/bct/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bct-cfg-$(CONFIG_FOSTER_BCT_CFG_EMMC) += emmc.cfg diff --git a/src/mainboard/google/gale/Makefile.inc b/src/mainboard/google/gale/Makefile.inc index 0cbda5b956..84b41e6ebf 100644 --- a/src/mainboard/google/gale/Makefile.inc +++ b/src/mainboard/google/gale/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/google/glados/Makefile.inc b/src/mainboard/google/glados/Makefile.inc index 83de22a930..9bf68727de 100644 --- a/src/mainboard/google/glados/Makefile.inc +++ b/src/mainboard/google/glados/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only subdirs-y += spd diff --git a/src/mainboard/google/glados/cmos.layout b/src/mainboard/google/glados/cmos.layout index 588a27b024..8c2244fa55 100644 --- a/src/mainboard/google/glados/cmos.layout +++ b/src/mainboard/google/glados/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/google/glados/variants/asuka/Makefile.inc b/src/mainboard/google/glados/variants/asuka/Makefile.inc index 9275f7241f..ee3447823f 100644 --- a/src/mainboard/google/glados/variants/asuka/Makefile.inc +++ b/src/mainboard/google/glados/variants/asuka/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += variant.c diff --git a/src/mainboard/google/glados/variants/caroline/Makefile.inc b/src/mainboard/google/glados/variants/caroline/Makefile.inc index 134c75a2a2..a2545fcf08 100644 --- a/src/mainboard/google/glados/variants/caroline/Makefile.inc +++ b/src/mainboard/google/glados/variants/caroline/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += variant.c diff --git a/src/mainboard/google/glados/variants/cave/Makefile.inc b/src/mainboard/google/glados/variants/cave/Makefile.inc index c14bf03aca..2f19b3fbd2 100644 --- a/src/mainboard/google/glados/variants/cave/Makefile.inc +++ b/src/mainboard/google/glados/variants/cave/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += variant.c diff --git a/src/mainboard/google/glados/variants/chell/Makefile.inc b/src/mainboard/google/glados/variants/chell/Makefile.inc index 2b637f614f..b820684b7c 100644 --- a/src/mainboard/google/glados/variants/chell/Makefile.inc +++ b/src/mainboard/google/glados/variants/chell/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += variant.c diff --git a/src/mainboard/google/glados/variants/glados/Makefile.inc b/src/mainboard/google/glados/variants/glados/Makefile.inc index 103aa38796..3cf91e8f03 100644 --- a/src/mainboard/google/glados/variants/glados/Makefile.inc +++ b/src/mainboard/google/glados/variants/glados/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += variant.c diff --git a/src/mainboard/google/glados/variants/lars/Makefile.inc b/src/mainboard/google/glados/variants/lars/Makefile.inc index 7abb253697..e7ab2511f2 100644 --- a/src/mainboard/google/glados/variants/lars/Makefile.inc +++ b/src/mainboard/google/glados/variants/lars/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += variant.c diff --git a/src/mainboard/google/glados/variants/sentry/Makefile.inc b/src/mainboard/google/glados/variants/sentry/Makefile.inc index c8560713e8..019820a4b2 100644 --- a/src/mainboard/google/glados/variants/sentry/Makefile.inc +++ b/src/mainboard/google/glados/variants/sentry/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += variant.c diff --git a/src/mainboard/google/gru/Makefile.inc b/src/mainboard/google/gru/Makefile.inc index 9b098a2c4c..8849162ce0 100644 --- a/src/mainboard/google/gru/Makefile.inc +++ b/src/mainboard/google/gru/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only subdirs-y += sdram_params/ diff --git a/src/mainboard/google/gru/sdram_params/Makefile.inc b/src/mainboard/google/gru/sdram_params/Makefile.inc index 2b5665ed3d..3314c0af91 100644 --- a/src/mainboard/google/gru/sdram_params/Makefile.inc +++ b/src/mainboard/google/gru/sdram_params/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only sdram-params := diff --git a/src/mainboard/google/hatch/Makefile.inc b/src/mainboard/google/hatch/Makefile.inc index fdd6f7a78b..f82325f177 100644 --- a/src/mainboard/google/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/google/hatch/spd/Makefile.inc b/src/mainboard/google/hatch/spd/Makefile.inc index b10f785624..dc1c9978a0 100644 --- a/src/mainboard/google/hatch/spd/Makefile.inc +++ b/src/mainboard/google/hatch/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifneq ($(SPD_SOURCES),) diff --git a/src/mainboard/google/hatch/variants/akemi/Makefile.inc b/src/mainboard/google/hatch/variants/akemi/Makefile.inc index ca0d1343cc..0285219153 100644 --- a/src/mainboard/google/hatch/variants/akemi/Makefile.inc +++ b/src/mainboard/google/hatch/variants/akemi/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_SOURCES = 4G_2400 # 0b000 diff --git a/src/mainboard/google/hatch/variants/baseboard/Makefile.inc b/src/mainboard/google/hatch/variants/baseboard/Makefile.inc index a8e1f3bd0f..c0514376ac 100644 --- a/src/mainboard/google/hatch/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/hatch/variants/baseboard/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/dratini/Makefile.inc b/src/mainboard/google/hatch/variants/dratini/Makefile.inc index 5972056edc..0180d5a0f0 100644 --- a/src/mainboard/google/hatch/variants/dratini/Makefile.inc +++ b/src/mainboard/google/hatch/variants/dratini/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_SOURCES = 4G_2400 # 0b0000 diff --git a/src/mainboard/google/hatch/variants/duffy/Makefile.inc b/src/mainboard/google/hatch/variants/duffy/Makefile.inc index 1ac835c134..2afd49410a 100644 --- a/src/mainboard/google/hatch/variants/duffy/Makefile.inc +++ b/src/mainboard/google/hatch/variants/duffy/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/hatch/Makefile.inc b/src/mainboard/google/hatch/variants/hatch/Makefile.inc index 9fbd1bde0d..b6c3162f1d 100644 --- a/src/mainboard/google/hatch/variants/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/variants/hatch/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_SOURCES = 4G_2400 # 0b000 diff --git a/src/mainboard/google/hatch/variants/helios/Makefile.inc b/src/mainboard/google/hatch/variants/helios/Makefile.inc index 9744500a53..b980e9bea5 100644 --- a/src/mainboard/google/hatch/variants/helios/Makefile.inc +++ b/src/mainboard/google/hatch/variants/helios/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_SOURCES = LP_8G_2133 # 0b0000 diff --git a/src/mainboard/google/hatch/variants/jinlon/Makefile.inc b/src/mainboard/google/hatch/variants/jinlon/Makefile.inc index 025d3e1f71..5f7912b355 100644 --- a/src/mainboard/google/hatch/variants/jinlon/Makefile.inc +++ b/src/mainboard/google/hatch/variants/jinlon/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_SOURCES = 4G_2400 # 0b000 diff --git a/src/mainboard/google/hatch/variants/kaisa/Makefile.inc b/src/mainboard/google/hatch/variants/kaisa/Makefile.inc index 1ac835c134..2afd49410a 100644 --- a/src/mainboard/google/hatch/variants/kaisa/Makefile.inc +++ b/src/mainboard/google/hatch/variants/kaisa/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/kindred/Makefile.inc b/src/mainboard/google/hatch/variants/kindred/Makefile.inc index 31f7af705b..1676fd9798 100644 --- a/src/mainboard/google/hatch/variants/kindred/Makefile.inc +++ b/src/mainboard/google/hatch/variants/kindred/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_SOURCES = 4G_2400 # 0b000 diff --git a/src/mainboard/google/hatch/variants/kohaku/Makefile.inc b/src/mainboard/google/hatch/variants/kohaku/Makefile.inc index 9badf9c5cb..3e5c58173c 100644 --- a/src/mainboard/google/hatch/variants/kohaku/Makefile.inc +++ b/src/mainboard/google/hatch/variants/kohaku/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_SOURCES = LP_8G_2133 # 0b000 diff --git a/src/mainboard/google/hatch/variants/mushu/Makefile.inc b/src/mainboard/google/hatch/variants/mushu/Makefile.inc index 9fbd1bde0d..b6c3162f1d 100644 --- a/src/mainboard/google/hatch/variants/mushu/Makefile.inc +++ b/src/mainboard/google/hatch/variants/mushu/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_SOURCES = 4G_2400 # 0b000 diff --git a/src/mainboard/google/hatch/variants/nightfury/Makefile.inc b/src/mainboard/google/hatch/variants/nightfury/Makefile.inc index 263be0d3d5..7799cd29c9 100644 --- a/src/mainboard/google/hatch/variants/nightfury/Makefile.inc +++ b/src/mainboard/google/hatch/variants/nightfury/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_SOURCES = LP_8G_2133 # 0b000 diff --git a/src/mainboard/google/hatch/variants/palkia/Makefile.inc b/src/mainboard/google/hatch/variants/palkia/Makefile.inc index ee9a0bd727..a6a72229ae 100644 --- a/src/mainboard/google/hatch/variants/palkia/Makefile.inc +++ b/src/mainboard/google/hatch/variants/palkia/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-or-later ## diff --git a/src/mainboard/google/hatch/variants/puff/Makefile.inc b/src/mainboard/google/hatch/variants/puff/Makefile.inc index 1ac835c134..2afd49410a 100644 --- a/src/mainboard/google/hatch/variants/puff/Makefile.inc +++ b/src/mainboard/google/hatch/variants/puff/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/stryke/Makefile.inc b/src/mainboard/google/hatch/variants/stryke/Makefile.inc index d852053695..ba66a9a2b1 100644 --- a/src/mainboard/google/hatch/variants/stryke/Makefile.inc +++ b/src/mainboard/google/hatch/variants/stryke/Makefile.inc @@ -1,4 +1,3 @@ -## ## SPDX-License-Identifier: GPL-2.0-only SPD_SOURCES = 4G_2400 # 0b000 diff --git a/src/mainboard/google/hatch/variants/sushi/Makefile.inc b/src/mainboard/google/hatch/variants/sushi/Makefile.inc index 61b23ede99..a115aa9c89 100644 --- a/src/mainboard/google/hatch/variants/sushi/Makefile.inc +++ b/src/mainboard/google/hatch/variants/sushi/Makefile.inc @@ -1,4 +1,3 @@ -## ## SPDX-License-Identifier: GPL-2.0-only SPD_SOURCES = diff --git a/src/mainboard/google/jecht/Makefile.inc b/src/mainboard/google/jecht/Makefile.inc index 662d191e54..845fb0bd2c 100644 --- a/src/mainboard/google/jecht/Makefile.inc +++ b/src/mainboard/google/jecht/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only subdirs-y += spd diff --git a/src/mainboard/google/jecht/cmos.layout b/src/mainboard/google/jecht/cmos.layout index 588a27b024..8c2244fa55 100644 --- a/src/mainboard/google/jecht/cmos.layout +++ b/src/mainboard/google/jecht/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/google/jecht/spd/Makefile.inc b/src/mainboard/google/jecht/spd/Makefile.inc index e4f1f10097..6ecc95b482 100644 --- a/src/mainboard/google/jecht/spd/Makefile.inc +++ b/src/mainboard/google/jecht/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += spd.c diff --git a/src/mainboard/google/kahlee/Makefile.inc b/src/mainboard/google/kahlee/Makefile.inc index 00212f4766..faa2496a19 100644 --- a/src/mainboard/google/kahlee/Makefile.inc +++ b/src/mainboard/google/kahlee/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock/bootblock.c diff --git a/src/mainboard/google/kahlee/variants/aleena/Makefile.inc b/src/mainboard/google/kahlee/variants/aleena/Makefile.inc index a163f25225..24e0090c5e 100644 --- a/src/mainboard/google/kahlee/variants/aleena/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/aleena/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only subdirs-y += ../baseboard/spd diff --git a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb index 226703d8a0..fda218df24 100644 --- a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip soc/amd/stoneyridge diff --git a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc index ac22182f3f..9f33a0b224 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/Makefile.inc b/src/mainboard/google/kahlee/variants/baseboard/spd/Makefile.inc index e93586ccfa..482fdec085 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/spd/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/baseboard/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/kahlee/variants/careena/Makefile.inc b/src/mainboard/google/kahlee/variants/careena/Makefile.inc index fe9a25fc3e..cd19d7cab5 100644 --- a/src/mainboard/google/kahlee/variants/careena/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/careena/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only subdirs-y += ./spd diff --git a/src/mainboard/google/kahlee/variants/careena/devicetree.cb b/src/mainboard/google/kahlee/variants/careena/devicetree.cb index f7a00bdb54..2658a6e466 100644 --- a/src/mainboard/google/kahlee/variants/careena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/careena/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip soc/amd/stoneyridge diff --git a/src/mainboard/google/kahlee/variants/careena/spd/Makefile.inc b/src/mainboard/google/kahlee/variants/careena/spd/Makefile.inc index 8e5c681e31..ca459d270a 100644 --- a/src/mainboard/google/kahlee/variants/careena/spd/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/careena/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/kahlee/variants/grunt/Makefile.inc b/src/mainboard/google/kahlee/variants/grunt/Makefile.inc index a163f25225..24e0090c5e 100644 --- a/src/mainboard/google/kahlee/variants/grunt/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/grunt/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only subdirs-y += ../baseboard/spd diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb index 715f3b17f2..e26ad5803e 100644 --- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip soc/amd/stoneyridge diff --git a/src/mainboard/google/kahlee/variants/liara/Makefile.inc b/src/mainboard/google/kahlee/variants/liara/Makefile.inc index a163f25225..24e0090c5e 100644 --- a/src/mainboard/google/kahlee/variants/liara/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/liara/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only subdirs-y += ../baseboard/spd diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/devicetree.cb index 82f93b7c89..b366280526 100644 --- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/liara/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip soc/amd/stoneyridge diff --git a/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc b/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc index 5fcbd1ebd0..c4dcffc780 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only subdirs-y += ./spd diff --git a/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb b/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb index 4aa73dd45e..d7772c442d 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip soc/amd/stoneyridge diff --git a/src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc b/src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc index 6b7c588bb6..2d3cd88581 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/kahlee/variants/treeya/Makefile.inc b/src/mainboard/google/kahlee/variants/treeya/Makefile.inc index 5fcbd1ebd0..c4dcffc780 100644 --- a/src/mainboard/google/kahlee/variants/treeya/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/treeya/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only subdirs-y += ./spd diff --git a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb index 09eecb8226..1cc3d437cc 100644 --- a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip soc/amd/stoneyridge diff --git a/src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc b/src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc index 6b7c588bb6..2d3cd88581 100644 --- a/src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc index 9330ae0f4d..ee411c2f28 100644 --- a/src/mainboard/google/link/Makefile.inc +++ b/src/mainboard/google/link/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-y += ec.c diff --git a/src/mainboard/google/link/cmos.layout b/src/mainboard/google/link/cmos.layout index cdafb3fc3c..0cf582192b 100644 --- a/src/mainboard/google/link/cmos.layout +++ b/src/mainboard/google/link/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/google/nyan/Makefile.inc b/src/mainboard/google/nyan/Makefile.inc index b0d82ab356..124d4121d7 100644 --- a/src/mainboard/google/nyan/Makefile.inc +++ b/src/mainboard/google/nyan/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # Add a handler for BCT config files diff --git a/src/mainboard/google/nyan/bct/Makefile.inc b/src/mainboard/google/nyan/bct/Makefile.inc index aa70355c63..0c7b2b746a 100644 --- a/src/mainboard/google/nyan/bct/Makefile.inc +++ b/src/mainboard/google/nyan/bct/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bct-cfg-$(CONFIG_NYAN_BCT_CFG_EMMC) += emmc.cfg diff --git a/src/mainboard/google/nyan_big/Makefile.inc b/src/mainboard/google/nyan_big/Makefile.inc index 07eacf9cc8..5cf7356ec1 100644 --- a/src/mainboard/google/nyan_big/Makefile.inc +++ b/src/mainboard/google/nyan_big/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # Add a handler for BCT config files diff --git a/src/mainboard/google/nyan_big/bct/Makefile.inc b/src/mainboard/google/nyan_big/bct/Makefile.inc index 6385d2a79c..f83c93263d 100644 --- a/src/mainboard/google/nyan_big/bct/Makefile.inc +++ b/src/mainboard/google/nyan_big/bct/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bct-cfg-$(CONFIG_NYAN_BIG_BCT_CFG_EMMC) += emmc.cfg diff --git a/src/mainboard/google/nyan_blaze/Makefile.inc b/src/mainboard/google/nyan_blaze/Makefile.inc index e1e42d4dbb..de582badda 100644 --- a/src/mainboard/google/nyan_blaze/Makefile.inc +++ b/src/mainboard/google/nyan_blaze/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # Add a handler for BCT config files diff --git a/src/mainboard/google/nyan_blaze/bct/Makefile.inc b/src/mainboard/google/nyan_blaze/bct/Makefile.inc index 50ad83fc03..02f32a59bd 100644 --- a/src/mainboard/google/nyan_blaze/bct/Makefile.inc +++ b/src/mainboard/google/nyan_blaze/bct/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bct-cfg-$(CONFIG_NYAN_BLAZE_BCT_CFG_EMMC) += emmc.cfg diff --git a/src/mainboard/google/oak/Makefile.inc b/src/mainboard/google/oak/Makefile.inc index d01c4a5b28..63ccc1e335 100644 --- a/src/mainboard/google/oak/Makefile.inc +++ b/src/mainboard/google/oak/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/google/parrot/Makefile.inc b/src/mainboard/google/parrot/Makefile.inc index 5f6fb09e27..f2166e11e7 100644 --- a/src/mainboard/google/parrot/Makefile.inc +++ b/src/mainboard/google/parrot/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-y += ec.c diff --git a/src/mainboard/google/parrot/cmos.layout b/src/mainboard/google/parrot/cmos.layout index cdafb3fc3c..0cf582192b 100644 --- a/src/mainboard/google/parrot/cmos.layout +++ b/src/mainboard/google/parrot/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/google/peach_pit/Makefile.inc b/src/mainboard/google/peach_pit/Makefile.inc index 667e64d7bc..9faa2e09ef 100644 --- a/src/mainboard/google/peach_pit/Makefile.inc +++ b/src/mainboard/google/peach_pit/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += wakeup.c diff --git a/src/mainboard/google/poppy/Makefile.inc b/src/mainboard/google/poppy/Makefile.inc index 1cd4797ec8..3b54531625 100644 --- a/src/mainboard/google/poppy/Makefile.inc +++ b/src/mainboard/google/poppy/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/google/rambi/Makefile.inc b/src/mainboard/google/rambi/Makefile.inc index 7c615c8a0c..da2e474614 100644 --- a/src/mainboard/google/rambi/Makefile.inc +++ b/src/mainboard/google/rambi/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/rambi/cmos.layout b/src/mainboard/google/rambi/cmos.layout index 57032a19ce..da1b185c7e 100644 --- a/src/mainboard/google/rambi/cmos.layout +++ b/src/mainboard/google/rambi/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/google/rambi/variants/banjo/Makefile.inc b/src/mainboard/google/rambi/variants/banjo/Makefile.inc index e7aa3cc086..1d6619bf8f 100644 --- a/src/mainboard/google/rambi/variants/banjo/Makefile.inc +++ b/src/mainboard/google/rambi/variants/banjo/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/rambi/variants/candy/Makefile.inc b/src/mainboard/google/rambi/variants/candy/Makefile.inc index 12747b0bdd..4630519b4e 100644 --- a/src/mainboard/google/rambi/variants/candy/Makefile.inc +++ b/src/mainboard/google/rambi/variants/candy/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/rambi/variants/clapper/Makefile.inc b/src/mainboard/google/rambi/variants/clapper/Makefile.inc index 3f92ee4b04..2a641ba881 100644 --- a/src/mainboard/google/rambi/variants/clapper/Makefile.inc +++ b/src/mainboard/google/rambi/variants/clapper/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/rambi/variants/enguarde/Makefile.inc b/src/mainboard/google/rambi/variants/enguarde/Makefile.inc index 8afe3d8a72..5b7d58b8e3 100644 --- a/src/mainboard/google/rambi/variants/enguarde/Makefile.inc +++ b/src/mainboard/google/rambi/variants/enguarde/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/rambi/variants/glimmer/Makefile.inc b/src/mainboard/google/rambi/variants/glimmer/Makefile.inc index 91c103e2e3..da99edce4c 100644 --- a/src/mainboard/google/rambi/variants/glimmer/Makefile.inc +++ b/src/mainboard/google/rambi/variants/glimmer/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/rambi/variants/gnawty/Makefile.inc b/src/mainboard/google/rambi/variants/gnawty/Makefile.inc index cb89e88cd3..eb87d0c619 100644 --- a/src/mainboard/google/rambi/variants/gnawty/Makefile.inc +++ b/src/mainboard/google/rambi/variants/gnawty/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/rambi/variants/heli/Makefile.inc b/src/mainboard/google/rambi/variants/heli/Makefile.inc index 294801d055..8a9adf3d81 100644 --- a/src/mainboard/google/rambi/variants/heli/Makefile.inc +++ b/src/mainboard/google/rambi/variants/heli/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/rambi/variants/kip/Makefile.inc b/src/mainboard/google/rambi/variants/kip/Makefile.inc index fcb3f94dcc..bf95c739e8 100644 --- a/src/mainboard/google/rambi/variants/kip/Makefile.inc +++ b/src/mainboard/google/rambi/variants/kip/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/rambi/variants/ninja/Makefile.inc b/src/mainboard/google/rambi/variants/ninja/Makefile.inc index c82094099b..723a5e592d 100644 --- a/src/mainboard/google/rambi/variants/ninja/Makefile.inc +++ b/src/mainboard/google/rambi/variants/ninja/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/rambi/variants/orco/Makefile.inc b/src/mainboard/google/rambi/variants/orco/Makefile.inc index 3a1dc91fe4..2c2496ebc9 100644 --- a/src/mainboard/google/rambi/variants/orco/Makefile.inc +++ b/src/mainboard/google/rambi/variants/orco/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/rambi/variants/quawks/Makefile.inc b/src/mainboard/google/rambi/variants/quawks/Makefile.inc index 67f3b09a3e..2c0127cbef 100644 --- a/src/mainboard/google/rambi/variants/quawks/Makefile.inc +++ b/src/mainboard/google/rambi/variants/quawks/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/rambi/variants/rambi/Makefile.inc b/src/mainboard/google/rambi/variants/rambi/Makefile.inc index 05f1e5ab8f..5bddd5c15a 100644 --- a/src/mainboard/google/rambi/variants/rambi/Makefile.inc +++ b/src/mainboard/google/rambi/variants/rambi/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/rambi/variants/squawks/Makefile.inc b/src/mainboard/google/rambi/variants/squawks/Makefile.inc index 67f3b09a3e..2c0127cbef 100644 --- a/src/mainboard/google/rambi/variants/squawks/Makefile.inc +++ b/src/mainboard/google/rambi/variants/squawks/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/rambi/variants/sumo/Makefile.inc b/src/mainboard/google/rambi/variants/sumo/Makefile.inc index c82094099b..723a5e592d 100644 --- a/src/mainboard/google/rambi/variants/sumo/Makefile.inc +++ b/src/mainboard/google/rambi/variants/sumo/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/rambi/variants/swanky/Makefile.inc b/src/mainboard/google/rambi/variants/swanky/Makefile.inc index 33a0e369e1..7269afd299 100644 --- a/src/mainboard/google/rambi/variants/swanky/Makefile.inc +++ b/src/mainboard/google/rambi/variants/swanky/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/rambi/variants/winky/Makefile.inc b/src/mainboard/google/rambi/variants/winky/Makefile.inc index caafda8162..105684f7eb 100644 --- a/src/mainboard/google/rambi/variants/winky/Makefile.inc +++ b/src/mainboard/google/rambi/variants/winky/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/sarien/Makefile.inc b/src/mainboard/google/sarien/Makefile.inc index 5b85874f39..eea7f472e6 100644 --- a/src/mainboard/google/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/google/sarien/variants/arcada/Makefile.inc b/src/mainboard/google/sarien/variants/arcada/Makefile.inc index 5c26f10546..eff19f5a5f 100644 --- a/src/mainboard/google/sarien/variants/arcada/Makefile.inc +++ b/src/mainboard/google/sarien/variants/arcada/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c diff --git a/src/mainboard/google/sarien/variants/sarien/Makefile.inc b/src/mainboard/google/sarien/variants/sarien/Makefile.inc index 5c26f10546..eff19f5a5f 100644 --- a/src/mainboard/google/sarien/variants/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/variants/sarien/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc index c66032a322..e652dac2d9 100644 --- a/src/mainboard/google/slippy/Makefile.inc +++ b/src/mainboard/google/slippy/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout index 57032a19ce..da1b185c7e 100644 --- a/src/mainboard/google/slippy/cmos.layout +++ b/src/mainboard/google/slippy/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/google/slippy/variants/falco/Makefile.inc b/src/mainboard/google/slippy/variants/falco/Makefile.inc index 2969c33ae2..6d1ee81ec7 100644 --- a/src/mainboard/google/slippy/variants/falco/Makefile.inc +++ b/src/mainboard/google/slippy/variants/falco/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ## DIMM SPD for on-board memory diff --git a/src/mainboard/google/slippy/variants/leon/Makefile.inc b/src/mainboard/google/slippy/variants/leon/Makefile.inc index da23a0c536..3dab895e9c 100644 --- a/src/mainboard/google/slippy/variants/leon/Makefile.inc +++ b/src/mainboard/google/slippy/variants/leon/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ## DIMM SPD for on-board memory diff --git a/src/mainboard/google/slippy/variants/peppy/Makefile.inc b/src/mainboard/google/slippy/variants/peppy/Makefile.inc index 6f421d4ede..c19326e0c5 100644 --- a/src/mainboard/google/slippy/variants/peppy/Makefile.inc +++ b/src/mainboard/google/slippy/variants/peppy/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ## DIMM SPD for on-board memory diff --git a/src/mainboard/google/slippy/variants/wolf/Makefile.inc b/src/mainboard/google/slippy/variants/wolf/Makefile.inc index c4d943480e..3306b797f0 100644 --- a/src/mainboard/google/slippy/variants/wolf/Makefile.inc +++ b/src/mainboard/google/slippy/variants/wolf/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ## DIMM SPD for on-board memory diff --git a/src/mainboard/google/smaug/Makefile.inc b/src/mainboard/google/smaug/Makefile.inc index dc503fac07..342e0dd35f 100644 --- a/src/mainboard/google/smaug/Makefile.inc +++ b/src/mainboard/google/smaug/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # Add a handler for BCT config files diff --git a/src/mainboard/google/smaug/bct/Makefile.inc b/src/mainboard/google/smaug/bct/Makefile.inc index 276e4747a9..68449bf4fc 100644 --- a/src/mainboard/google/smaug/bct/Makefile.inc +++ b/src/mainboard/google/smaug/bct/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bct-cfg-$(CONFIG_SMAUG_BCT_CFG_EMMC) += emmc.cfg diff --git a/src/mainboard/google/storm/Makefile.inc b/src/mainboard/google/storm/Makefile.inc index 2d2488f8cd..272c49b602 100644 --- a/src/mainboard/google/storm/Makefile.inc +++ b/src/mainboard/google/storm/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/google/stout/Makefile.inc b/src/mainboard/google/stout/Makefile.inc index 275f064edb..5c196f07f0 100644 --- a/src/mainboard/google/stout/Makefile.inc +++ b/src/mainboard/google/stout/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-y += ec.c diff --git a/src/mainboard/google/stout/cmos.layout b/src/mainboard/google/stout/cmos.layout index cdafb3fc3c..0cf582192b 100644 --- a/src/mainboard/google/stout/cmos.layout +++ b/src/mainboard/google/stout/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/google/trogdor/Makefile.inc b/src/mainboard/google/trogdor/Makefile.inc index 9c4749af42..4a2b5d47c6 100644 --- a/src/mainboard/google/trogdor/Makefile.inc +++ b/src/mainboard/google/trogdor/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += memlayout.ld diff --git a/src/mainboard/google/veyron/Makefile.inc b/src/mainboard/google/veyron/Makefile.inc index 0eb3fb42e3..76d141fa27 100644 --- a/src/mainboard/google/veyron/Makefile.inc +++ b/src/mainboard/google/veyron/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/google/veyron_mickey/Makefile.inc b/src/mainboard/google/veyron_mickey/Makefile.inc index 0eb3fb42e3..76d141fa27 100644 --- a/src/mainboard/google/veyron_mickey/Makefile.inc +++ b/src/mainboard/google/veyron_mickey/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/google/veyron_rialto/Makefile.inc b/src/mainboard/google/veyron_rialto/Makefile.inc index 0eb3fb42e3..76d141fa27 100644 --- a/src/mainboard/google/veyron_rialto/Makefile.inc +++ b/src/mainboard/google/veyron_rialto/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/google/volteer/Makefile.inc b/src/mainboard/google/volteer/Makefile.inc index 75f8a58245..c7e1daef2e 100644 --- a/src/mainboard/google/volteer/Makefile.inc +++ b/src/mainboard/google/volteer/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-or-later ## diff --git a/src/mainboard/google/volteer/spd/Makefile.inc b/src/mainboard/google/volteer/spd/Makefile.inc index eb53fc00a3..5891b6d622 100644 --- a/src/mainboard/google/volteer/spd/Makefile.inc +++ b/src/mainboard/google/volteer/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-or-later ## diff --git a/src/mainboard/google/volteer/variants/baseboard/Makefile.inc b/src/mainboard/google/volteer/variants/baseboard/Makefile.inc index c8938960a7..4dd8eb6861 100644 --- a/src/mainboard/google/volteer/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/volteer/variants/baseboard/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-or-later ## diff --git a/src/mainboard/google/volteer/variants/ripto/Makefile.inc b/src/mainboard/google/volteer/variants/ripto/Makefile.inc index b1e365d5ac..826bab1db3 100644 --- a/src/mainboard/google/volteer/variants/ripto/Makefile.inc +++ b/src/mainboard/google/volteer/variants/ripto/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_SOURCES = SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267 # 0b0000 diff --git a/src/mainboard/google/volteer/variants/volteer/Makefile.inc b/src/mainboard/google/volteer/variants/volteer/Makefile.inc index d075c1fe95..5b97e8d729 100644 --- a/src/mainboard/google/volteer/variants/volteer/Makefile.inc +++ b/src/mainboard/google/volteer/variants/volteer/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-or-later ## diff --git a/src/mainboard/hp/abm/Makefile.inc b/src/mainboard/hp/abm/Makefile.inc index db9b1b68cb..549801d78f 100644 --- a/src/mainboard/hp/abm/Makefile.inc +++ b/src/mainboard/hp/abm/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout b/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout index 122d5d5ff5..e26a347b0e 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout +++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc index b359aa4b64..77ae870b6c 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc +++ b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only romstage-y += buildOpts.c diff --git a/src/mainboard/hp/snb_ivb_laptops/Makefile.inc b/src/mainboard/hp/snb_ivb_laptops/Makefile.inc index 2d082ad55a..c007bb68cd 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Makefile.inc +++ b/src/mainboard/hp/snb_ivb_laptops/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += variants/$(VARIANT_DIR)/early_init.c diff --git a/src/mainboard/hp/snb_ivb_laptops/cmos.layout b/src/mainboard/hp/snb_ivb_laptops/cmos.layout index 066baee8b9..858dc4e69e 100644 --- a/src/mainboard/hp/snb_ivb_laptops/cmos.layout +++ b/src/mainboard/hp/snb_ivb_laptops/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/hp/z220_sff_workstation/cmos.layout b/src/mainboard/hp/z220_sff_workstation/cmos.layout index 1f2e2d673c..33b2068e2b 100644 --- a/src/mainboard/hp/z220_sff_workstation/cmos.layout +++ b/src/mainboard/hp/z220_sff_workstation/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/ibase/mb899/cmos.layout b/src/mainboard/ibase/mb899/cmos.layout index 0afd7fcb1a..e51185bc8f 100644 --- a/src/mainboard/ibase/mb899/cmos.layout +++ b/src/mainboard/ibase/mb899/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc index e58fee3758..f157ec005d 100644 --- a/src/mainboard/intel/baskingridge/Makefile.inc +++ b/src/mainboard/intel/baskingridge/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += chromeos.c diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout index ab4c85fd1d..7c4d614196 100644 --- a/src/mainboard/intel/baskingridge/cmos.layout +++ b/src/mainboard/intel/baskingridge/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/cannonlake_rvp/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/Makefile.inc index b1f72a9fd6..695b1ff349 100644 --- a/src/mainboard/intel/cannonlake_rvp/Makefile.inc +++ b/src/mainboard/intel/cannonlake_rvp/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only subdirs-y += spd diff --git a/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc index 9ff3d1e9b8..48e6375819 100644 --- a/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc +++ b/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += spd_util.c diff --git a/src/mainboard/intel/coffeelake_rvp/Makefile.inc b/src/mainboard/intel/coffeelake_rvp/Makefile.inc index 51e00399dc..a3061e3db5 100644 --- a/src/mainboard/intel/coffeelake_rvp/Makefile.inc +++ b/src/mainboard/intel/coffeelake_rvp/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/intel/d510mo/cmos.layout b/src/mainboard/intel/d510mo/cmos.layout index 14c10a775d..0a329956af 100644 --- a/src/mainboard/intel/d510mo/cmos.layout +++ b/src/mainboard/intel/d510mo/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/d945gclf/cmos.layout b/src/mainboard/intel/d945gclf/cmos.layout index b311022912..e0d6ec5244 100644 --- a/src/mainboard/intel/d945gclf/cmos.layout +++ b/src/mainboard/intel/d945gclf/cmos.layout @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/dg41wv/cmos.layout b/src/mainboard/intel/dg41wv/cmos.layout index 1b1ce10f3d..4905f1d133 100644 --- a/src/mainboard/intel/dg41wv/cmos.layout +++ b/src/mainboard/intel/dg41wv/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/dg43gt/Makefile.inc b/src/mainboard/intel/dg43gt/Makefile.inc index 430ada7df6..ede8d87e92 100644 --- a/src/mainboard/intel/dg43gt/Makefile.inc +++ b/src/mainboard/intel/dg43gt/Makefile.inc @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only ramstage-y += cstates.c diff --git a/src/mainboard/intel/dg43gt/cmos.layout b/src/mainboard/intel/dg43gt/cmos.layout index 742bdaee9f..79bb1b8956 100644 --- a/src/mainboard/intel/dg43gt/cmos.layout +++ b/src/mainboard/intel/dg43gt/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/emeraldlake2/Makefile.inc b/src/mainboard/intel/emeraldlake2/Makefile.inc index 124fb75830..151a3c382b 100644 --- a/src/mainboard/intel/emeraldlake2/Makefile.inc +++ b/src/mainboard/intel/emeraldlake2/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += chromeos.c diff --git a/src/mainboard/intel/emeraldlake2/cmos.layout b/src/mainboard/intel/emeraldlake2/cmos.layout index 7266e548d4..8c19c753b1 100644 --- a/src/mainboard/intel/emeraldlake2/cmos.layout +++ b/src/mainboard/intel/emeraldlake2/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index 9ccb29bb3f..004f83280f 100644 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/quark diff --git a/src/mainboard/intel/harcuvar/Makefile.inc b/src/mainboard/intel/harcuvar/Makefile.inc index 6431346de8..bfcde9c934 100644 --- a/src/mainboard/intel/harcuvar/Makefile.inc +++ b/src/mainboard/intel/harcuvar/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only subdirs-$(CONFIG_ENABLE_FSP_MEMORY_DOWN) += spd diff --git a/src/mainboard/intel/harcuvar/spd/Makefile.inc b/src/mainboard/intel/harcuvar/spd/Makefile.inc index 8e09454652..55a6aef7a8 100644 --- a/src/mainboard/intel/harcuvar/spd/Makefile.inc +++ b/src/mainboard/intel/harcuvar/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += spd.c diff --git a/src/mainboard/intel/icelake_rvp/Makefile.inc b/src/mainboard/intel/icelake_rvp/Makefile.inc index d8e5822647..60551c5213 100644 --- a/src/mainboard/intel/icelake_rvp/Makefile.inc +++ b/src/mainboard/intel/icelake_rvp/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only subdirs-y += spd diff --git a/src/mainboard/intel/icelake_rvp/spd/Makefile.inc b/src/mainboard/intel/icelake_rvp/spd/Makefile.inc index 7aeb93f044..3114eebaf5 100644 --- a/src/mainboard/intel/icelake_rvp/spd/Makefile.inc +++ b/src/mainboard/intel/icelake_rvp/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += spd_util.c diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/Makefile.inc b/src/mainboard/intel/icelake_rvp/variants/icl_u/Makefile.inc index 74f4976495..9f8b7815b5 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/Makefile.inc +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/Makefile.inc b/src/mainboard/intel/icelake_rvp/variants/icl_y/Makefile.inc index 74f4976495..9f8b7815b5 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/Makefile.inc +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c diff --git a/src/mainboard/intel/jasperlake_rvp/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/Makefile.inc index 26663d8df7..20b3be4bd9 100644 --- a/src/mainboard/intel/jasperlake_rvp/Makefile.inc +++ b/src/mainboard/intel/jasperlake_rvp/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only subdirs-y += spd diff --git a/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc index 0934460168..3c8040c7c2 100644 --- a/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc +++ b/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc index 34de9a9c1f..641e814351 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c diff --git a/src/mainboard/intel/kblrvp/Makefile.inc b/src/mainboard/intel/kblrvp/Makefile.inc index 9612c563ee..c168b6dbf3 100644 --- a/src/mainboard/intel/kblrvp/Makefile.inc +++ b/src/mainboard/intel/kblrvp/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only subdirs-y += spd diff --git a/src/mainboard/intel/kblrvp/cmos.layout b/src/mainboard/intel/kblrvp/cmos.layout index 588a27b024..8c2244fa55 100644 --- a/src/mainboard/intel/kblrvp/cmos.layout +++ b/src/mainboard/intel/kblrvp/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/kblrvp/spd/Makefile.inc b/src/mainboard/intel/kblrvp/spd/Makefile.inc index 9a69ffd238..d04269969a 100644 --- a/src/mainboard/intel/kblrvp/spd/Makefile.inc +++ b/src/mainboard/intel/kblrvp/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += spd_util.c diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc index 818cddecd8..63c39cf5e7 100644 --- a/src/mainboard/intel/kunimitsu/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only subdirs-y += spd diff --git a/src/mainboard/intel/kunimitsu/cmos.layout b/src/mainboard/intel/kunimitsu/cmos.layout index 588a27b024..8c2244fa55 100644 --- a/src/mainboard/intel/kunimitsu/cmos.layout +++ b/src/mainboard/intel/kunimitsu/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/kunimitsu/spd/Makefile.inc b/src/mainboard/intel/kunimitsu/spd/Makefile.inc index 743fb29db2..9ecf28d1fe 100644 --- a/src/mainboard/intel/kunimitsu/spd/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += spd_util.c diff --git a/src/mainboard/intel/saddlebrook/Makefile.inc b/src/mainboard/intel/saddlebrook/Makefile.inc index e1e6c7057a..ece007c75c 100644 --- a/src/mainboard/intel/saddlebrook/Makefile.inc +++ b/src/mainboard/intel/saddlebrook/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only subdirs-y += spd diff --git a/src/mainboard/intel/saddlebrook/cmos.layout b/src/mainboard/intel/saddlebrook/cmos.layout index e43d313423..cc55ccfc71 100644 --- a/src/mainboard/intel/saddlebrook/cmos.layout +++ b/src/mainboard/intel/saddlebrook/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/saddlebrook/spd/Makefile.inc b/src/mainboard/intel/saddlebrook/spd/Makefile.inc index 4b201f52a2..1a7ff99875 100644 --- a/src/mainboard/intel/saddlebrook/spd/Makefile.inc +++ b/src/mainboard/intel/saddlebrook/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += spd_util.c diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc index 25c9048134..bf35b669a8 100644 --- a/src/mainboard/intel/strago/Makefile.inc +++ b/src/mainboard/intel/strago/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c diff --git a/src/mainboard/intel/strago/cmos.layout b/src/mainboard/intel/strago/cmos.layout index 588a27b024..8c2244fa55 100644 --- a/src/mainboard/intel/strago/cmos.layout +++ b/src/mainboard/intel/strago/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/tglrvp/Makefile.inc b/src/mainboard/intel/tglrvp/Makefile.inc index 74bd5697d8..fbdac4d1eb 100644 --- a/src/mainboard/intel/tglrvp/Makefile.inc +++ b/src/mainboard/intel/tglrvp/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only subdirs-y += spd diff --git a/src/mainboard/intel/tglrvp/spd/Makefile.inc b/src/mainboard/intel/tglrvp/spd/Makefile.inc index 60775a4234..8dd1507544 100644 --- a/src/mainboard/intel/tglrvp/spd/Makefile.inc +++ b/src/mainboard/intel/tglrvp/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc index 267f3cf3dd..fb7eaf11e9 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc index 267f3cf3dd..fb7eaf11e9 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c diff --git a/src/mainboard/intel/wtm2/Makefile.inc b/src/mainboard/intel/wtm2/Makefile.inc index ce1ea6aec8..14e7d98ff6 100644 --- a/src/mainboard/intel/wtm2/Makefile.inc +++ b/src/mainboard/intel/wtm2/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += gpio.c diff --git a/src/mainboard/intel/wtm2/cmos.layout b/src/mainboard/intel/wtm2/cmos.layout index 57032a19ce..da1b185c7e 100644 --- a/src/mainboard/intel/wtm2/cmos.layout +++ b/src/mainboard/intel/wtm2/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc index 49e8b4baa4..9655909056 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc +++ b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_AHCI_BIOS),y) diff --git a/src/mainboard/kontron/986lcd-m/cmos.layout b/src/mainboard/kontron/986lcd-m/cmos.layout index bef8cbf400..cf758b1c38 100644 --- a/src/mainboard/kontron/986lcd-m/cmos.layout +++ b/src/mainboard/kontron/986lcd-m/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index a2335ef1d0..d63c75deb1 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/g505s/Makefile.inc b/src/mainboard/lenovo/g505s/Makefile.inc index b359aa4b64..77ae870b6c 100644 --- a/src/mainboard/lenovo/g505s/Makefile.inc +++ b/src/mainboard/lenovo/g505s/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only romstage-y += buildOpts.c diff --git a/src/mainboard/lenovo/l520/Makefile.inc b/src/mainboard/lenovo/l520/Makefile.inc index 35e9fb9df8..0126a75fa0 100644 --- a/src/mainboard/lenovo/l520/Makefile.inc +++ b/src/mainboard/lenovo/l520/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c diff --git a/src/mainboard/lenovo/l520/cmos.layout b/src/mainboard/lenovo/l520/cmos.layout index 5ef2849ad0..aecd7f3bca 100644 --- a/src/mainboard/lenovo/l520/cmos.layout +++ b/src/mainboard/lenovo/l520/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/t400/Makefile.inc b/src/mainboard/lenovo/t400/Makefile.inc index 7a6d3af4f4..982c2098d0 100644 --- a/src/mainboard/lenovo/t400/Makefile.inc +++ b/src/mainboard/lenovo/t400/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index ced8fcacb2..8d6b608cde 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/t410/Makefile.inc b/src/mainboard/lenovo/t410/Makefile.inc index e083775275..20ec7604c9 100644 --- a/src/mainboard/lenovo/t410/Makefile.inc +++ b/src/mainboard/lenovo/t410/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += early_init.c diff --git a/src/mainboard/lenovo/t410/cmos.layout b/src/mainboard/lenovo/t410/cmos.layout index b62df8b994..f3e1559a01 100644 --- a/src/mainboard/lenovo/t410/cmos.layout +++ b/src/mainboard/lenovo/t410/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/t420/Makefile.inc b/src/mainboard/lenovo/t420/Makefile.inc index b9d5597932..991eadbff2 100644 --- a/src/mainboard/lenovo/t420/Makefile.inc +++ b/src/mainboard/lenovo/t420/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only smm-y += smihandler.c diff --git a/src/mainboard/lenovo/t420/cmos.layout b/src/mainboard/lenovo/t420/cmos.layout index 779e701a70..ce5f04d47f 100644 --- a/src/mainboard/lenovo/t420/cmos.layout +++ b/src/mainboard/lenovo/t420/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/t420s/Makefile.inc b/src/mainboard/lenovo/t420s/Makefile.inc index b9d5597932..991eadbff2 100644 --- a/src/mainboard/lenovo/t420s/Makefile.inc +++ b/src/mainboard/lenovo/t420s/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only smm-y += smihandler.c diff --git a/src/mainboard/lenovo/t420s/cmos.layout b/src/mainboard/lenovo/t420s/cmos.layout index 779e701a70..ce5f04d47f 100644 --- a/src/mainboard/lenovo/t420s/cmos.layout +++ b/src/mainboard/lenovo/t420s/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/t430/cmos.layout b/src/mainboard/lenovo/t430/cmos.layout index 18a0d8c963..b38a91b189 100644 --- a/src/mainboard/lenovo/t430/cmos.layout +++ b/src/mainboard/lenovo/t430/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/t430s/Makefile.inc b/src/mainboard/lenovo/t430s/Makefile.inc index 8ff4ba40f8..196a0981f6 100644 --- a/src/mainboard/lenovo/t430s/Makefile.inc +++ b/src/mainboard/lenovo/t430s/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only smm-y += smihandler.c diff --git a/src/mainboard/lenovo/t430s/cmos.layout b/src/mainboard/lenovo/t430s/cmos.layout index f59a16b101..451bf7daf0 100644 --- a/src/mainboard/lenovo/t430s/cmos.layout +++ b/src/mainboard/lenovo/t430s/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc b/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc index fe28eb0584..38d83d6be8 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc +++ b/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/lenovo/t440p/cmos.layout b/src/mainboard/lenovo/t440p/cmos.layout index 0938742558..222ab40fb8 100644 --- a/src/mainboard/lenovo/t440p/cmos.layout +++ b/src/mainboard/lenovo/t440p/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/t520/Makefile.inc b/src/mainboard/lenovo/t520/Makefile.inc index b0aa6bb777..ab5aa4de91 100644 --- a/src/mainboard/lenovo/t520/Makefile.inc +++ b/src/mainboard/lenovo/t520/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only smm-y += smihandler.c diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout index 710f03f3fd..2dfd682c5a 100644 --- a/src/mainboard/lenovo/t520/cmos.layout +++ b/src/mainboard/lenovo/t520/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/t530/Makefile.inc b/src/mainboard/lenovo/t530/Makefile.inc index b0aa6bb777..ab5aa4de91 100644 --- a/src/mainboard/lenovo/t530/Makefile.inc +++ b/src/mainboard/lenovo/t530/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only smm-y += smihandler.c diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout index 995a0c5c51..4130b5f806 100644 --- a/src/mainboard/lenovo/t530/cmos.layout +++ b/src/mainboard/lenovo/t530/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/t60/Makefile.inc b/src/mainboard/lenovo/t60/Makefile.inc index c18ba21297..5ded71b41a 100644 --- a/src/mainboard/lenovo/t60/Makefile.inc +++ b/src/mainboard/lenovo/t60/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only smm-y += dock.c diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout index ba7e92a9a3..246d15d0c5 100644 --- a/src/mainboard/lenovo/t60/cmos.layout +++ b/src/mainboard/lenovo/t60/cmos.layout @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/t60/variants/t60/overridetree.cb b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb index 2bafd53f63..dc6abfb061 100644 --- a/src/mainboard/lenovo/t60/variants/t60/overridetree.cb +++ b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/i945 diff --git a/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb b/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb index 8a6c7287ab..9bac582af1 100644 --- a/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb +++ b/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/i945 diff --git a/src/mainboard/lenovo/thinkcentre_a58/cmos.layout b/src/mainboard/lenovo/thinkcentre_a58/cmos.layout index 1b1ce10f3d..4905f1d133 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/cmos.layout +++ b/src/mainboard/lenovo/thinkcentre_a58/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/x131e/Makefile.inc b/src/mainboard/lenovo/x131e/Makefile.inc index 58d309e956..e4b6fbf0f0 100644 --- a/src/mainboard/lenovo/x131e/Makefile.inc +++ b/src/mainboard/lenovo/x131e/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c diff --git a/src/mainboard/lenovo/x131e/cmos.layout b/src/mainboard/lenovo/x131e/cmos.layout index a9efc65670..32394de59a 100644 --- a/src/mainboard/lenovo/x131e/cmos.layout +++ b/src/mainboard/lenovo/x131e/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc index e948bcb5e6..e9e74ddf3f 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc +++ b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only subdirs-y += spd diff --git a/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout b/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout index d7dcf4ad8d..a3d2a0fb64 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout +++ b/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc b/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc index f3716494a9..e047c6ee58 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc +++ b/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/lenovo/x200/Makefile.inc b/src/mainboard/lenovo/x200/Makefile.inc index 002e35da6c..77333b31f0 100644 --- a/src/mainboard/lenovo/x200/Makefile.inc +++ b/src/mainboard/lenovo/x200/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_BOARD_LENOVO_X200) += variants/$(VARIANT_DIR)/dock.c diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout index 1ec4d42aaa..95c7930fd5 100644 --- a/src/mainboard/lenovo/x200/cmos.layout +++ b/src/mainboard/lenovo/x200/cmos.layout @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/x201/Makefile.inc b/src/mainboard/lenovo/x201/Makefile.inc index 672e52cabd..80e513cd72 100644 --- a/src/mainboard/lenovo/x201/Makefile.inc +++ b/src/mainboard/lenovo/x201/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += early_init.c diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index 97d206ca22..6dc55b24ec 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc index 1475b9b329..d870c4dd19 100644 --- a/src/mainboard/lenovo/x220/Makefile.inc +++ b/src/mainboard/lenovo/x220/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only smm-y += smihandler.c diff --git a/src/mainboard/lenovo/x220/cmos.layout b/src/mainboard/lenovo/x220/cmos.layout index 1e4654322d..740f57a700 100644 --- a/src/mainboard/lenovo/x220/cmos.layout +++ b/src/mainboard/lenovo/x220/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc index fc8c35995a..5316d24d88 100644 --- a/src/mainboard/lenovo/x230/Makefile.inc +++ b/src/mainboard/lenovo/x230/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only smm-y += smihandler.c diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout index 66f56281b8..314e4de089 100644 --- a/src/mainboard/lenovo/x230/cmos.layout +++ b/src/mainboard/lenovo/x230/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/x60/Makefile.inc b/src/mainboard/lenovo/x60/Makefile.inc index 755a790ac2..56fa18b13a 100644 --- a/src/mainboard/lenovo/x60/Makefile.inc +++ b/src/mainboard/lenovo/x60/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only smm-y += dock.c diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index 90887f970d..70dcd35210 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/lippert/frontrunner-af/Makefile.inc b/src/mainboard/lippert/frontrunner-af/Makefile.inc index a04fd883a4..9b9e5aeb11 100644 --- a/src/mainboard/lippert/frontrunner-af/Makefile.inc +++ b/src/mainboard/lippert/frontrunner-af/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_AHCI_BIOS),y) diff --git a/src/mainboard/lippert/toucan-af/Makefile.inc b/src/mainboard/lippert/toucan-af/Makefile.inc index 806a398551..caabc74565 100644 --- a/src/mainboard/lippert/toucan-af/Makefile.inc +++ b/src/mainboard/lippert/toucan-af/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_AHCI_BIOS),y) diff --git a/src/mainboard/msi/Kconfig b/src/mainboard/msi/Kconfig index 43bb4eba01..25350426f7 100644 --- a/src/mainboard/msi/Kconfig +++ b/src/mainboard/msi/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if VENDOR_MSI diff --git a/src/mainboard/msi/ms7721/Makefile.inc b/src/mainboard/msi/ms7721/Makefile.inc index db9b1b68cb..549801d78f 100644 --- a/src/mainboard/msi/ms7721/Makefile.inc +++ b/src/mainboard/msi/ms7721/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/opencellular/Kconfig b/src/mainboard/opencellular/Kconfig index bae8e23d35..1d31427398 100644 --- a/src/mainboard/opencellular/Kconfig +++ b/src/mainboard/opencellular/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if VENDOR_OPENCELLULAR diff --git a/src/mainboard/opencellular/elgon/Makefile.inc b/src/mainboard/opencellular/elgon/Makefile.inc index 92cc15fdb9..6b019825ab 100644 --- a/src/mainboard/opencellular/elgon/Makefile.inc +++ b/src/mainboard/opencellular/elgon/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/packardbell/ms2290/Makefile.inc b/src/mainboard/packardbell/ms2290/Makefile.inc index 7a79aa3293..9b1ea087bd 100644 --- a/src/mainboard/packardbell/ms2290/Makefile.inc +++ b/src/mainboard/packardbell/ms2290/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only smm-y += smihandler.c diff --git a/src/mainboard/packardbell/ms2290/cmos.layout b/src/mainboard/packardbell/ms2290/cmos.layout index 7e87085e2d..a3cd554cd2 100644 --- a/src/mainboard/packardbell/ms2290/cmos.layout +++ b/src/mainboard/packardbell/ms2290/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/pcengines/apu1/Makefile.inc b/src/mainboard/pcengines/apu1/Makefile.inc index 926dcc4264..bec5873b02 100644 --- a/src/mainboard/pcengines/apu1/Makefile.inc +++ b/src/mainboard/pcengines/apu1/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_AHCI_BIOS),y) diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc index 7fb04ddb53..93df43d17d 100644 --- a/src/mainboard/pcengines/apu2/Makefile.inc +++ b/src/mainboard/pcengines/apu2/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb index b9167ed294..243a9ba5ca 100644 --- a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/pi/00730F01/root_complex diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index fed816b5be..8273a9604c 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/pi/00730F01/root_complex diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb index 5087f6be60..f399d8bef1 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/pi/00730F01/root_complex diff --git a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb index 1ad86c2d59..c69401be1e 100644 --- a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/pi/00730F01/root_complex diff --git a/src/mainboard/portwell/m107/Makefile.inc b/src/mainboard/portwell/m107/Makefile.inc index 14647ecaae..d880fdb776 100644 --- a/src/mainboard/portwell/m107/Makefile.inc +++ b/src/mainboard/portwell/m107/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += com_init.c diff --git a/src/mainboard/portwell/m107/cmos.layout b/src/mainboard/portwell/m107/cmos.layout index 846e8b2b11..f80f2c597f 100644 --- a/src/mainboard/portwell/m107/cmos.layout +++ b/src/mainboard/portwell/m107/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/purism/Kconfig b/src/mainboard/purism/Kconfig index 2b62eeb151..a892e72b23 100644 --- a/src/mainboard/purism/Kconfig +++ b/src/mainboard/purism/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if VENDOR_PURISM diff --git a/src/mainboard/purism/librem_bdw/Makefile.inc b/src/mainboard/purism/librem_bdw/Makefile.inc index 2ca138e566..603dc194e5 100644 --- a/src/mainboard/purism/librem_bdw/Makefile.inc +++ b/src/mainboard/purism/librem_bdw/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += gpio.c diff --git a/src/mainboard/purism/librem_skl/Makefile.inc b/src/mainboard/purism/librem_skl/Makefile.inc index 7c33902077..5983578bb6 100644 --- a/src/mainboard/purism/librem_skl/Makefile.inc +++ b/src/mainboard/purism/librem_skl/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-y += ramstage.c diff --git a/src/mainboard/razer/blade_stealth_kbl/Makefile.inc b/src/mainboard/razer/blade_stealth_kbl/Makefile.inc index 4401f0033d..3d8d4fc847 100644 --- a/src/mainboard/razer/blade_stealth_kbl/Makefile.inc +++ b/src/mainboard/razer/blade_stealth_kbl/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only subdirs-y += spd diff --git a/src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc b/src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc index 6fb6e26631..27c289bd2a 100644 --- a/src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc +++ b/src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += spd_util.c diff --git a/src/mainboard/roda/rk886ex/Makefile.inc b/src/mainboard/roda/rk886ex/Makefile.inc index daa10244d0..c2b54c4ae3 100644 --- a/src/mainboard/roda/rk886ex/Makefile.inc +++ b/src/mainboard/roda/rk886ex/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-y += m3885.c diff --git a/src/mainboard/roda/rk886ex/cmos.layout b/src/mainboard/roda/rk886ex/cmos.layout index fd8c782493..755aad009f 100644 --- a/src/mainboard/roda/rk886ex/cmos.layout +++ b/src/mainboard/roda/rk886ex/cmos.layout @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/roda/rk9/Makefile.inc b/src/mainboard/roda/rk9/Makefile.inc index cbaa5a60f3..7d18e73bec 100644 --- a/src/mainboard/roda/rk9/Makefile.inc +++ b/src/mainboard/roda/rk9/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/roda/rk9/cmos.layout b/src/mainboard/roda/rk9/cmos.layout index c59f265827..2dce4640c9 100644 --- a/src/mainboard/roda/rk9/cmos.layout +++ b/src/mainboard/roda/rk9/cmos.layout @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/roda/rv11/Makefile.inc b/src/mainboard/roda/rv11/Makefile.inc index 8034588851..cb9c72573f 100644 --- a/src/mainboard/roda/rv11/Makefile.inc +++ b/src/mainboard/roda/rv11/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c diff --git a/src/mainboard/roda/rv11/cmos.layout b/src/mainboard/roda/rv11/cmos.layout index 85412562e8..ea36a26644 100644 --- a/src/mainboard/roda/rv11/cmos.layout +++ b/src/mainboard/roda/rv11/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index faea3430ec..0a96edf609 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/sandybridge diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index 2aee41e03f..988c2a64d5 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/sandybridge diff --git a/src/mainboard/samsung/lumpy/Makefile.inc b/src/mainboard/samsung/lumpy/Makefile.inc index 1bfe00e76b..74a635767e 100644 --- a/src/mainboard/samsung/lumpy/Makefile.inc +++ b/src/mainboard/samsung/lumpy/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-y += ec.c diff --git a/src/mainboard/samsung/lumpy/cmos.layout b/src/mainboard/samsung/lumpy/cmos.layout index 7b9835d0fb..4f80ef06e7 100644 --- a/src/mainboard/samsung/lumpy/cmos.layout +++ b/src/mainboard/samsung/lumpy/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/samsung/stumpy/Makefile.inc b/src/mainboard/samsung/stumpy/Makefile.inc index a49d03ba59..57ec1c5048 100644 --- a/src/mainboard/samsung/stumpy/Makefile.inc +++ b/src/mainboard/samsung/stumpy/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only romstage-y += chromeos.c diff --git a/src/mainboard/samsung/stumpy/cmos.layout b/src/mainboard/samsung/stumpy/cmos.layout index a441fb7994..8977a9acc8 100644 --- a/src/mainboard/samsung/stumpy/cmos.layout +++ b/src/mainboard/samsung/stumpy/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/sapphire/pureplatinumh61/cmos.layout b/src/mainboard/sapphire/pureplatinumh61/cmos.layout index 1c51b16786..06e9085e48 100644 --- a/src/mainboard/sapphire/pureplatinumh61/cmos.layout +++ b/src/mainboard/sapphire/pureplatinumh61/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/scaleway/tagada/Makefile.inc b/src/mainboard/scaleway/tagada/Makefile.inc index 340d8599a5..fe0fc795b6 100644 --- a/src/mainboard/scaleway/tagada/Makefile.inc +++ b/src/mainboard/scaleway/tagada/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/sifive/hifive-unleashed/Makefile.inc b/src/mainboard/sifive/hifive-unleashed/Makefile.inc index aee4c5f70d..02b8046030 100644 --- a/src/mainboard/sifive/hifive-unleashed/Makefile.inc +++ b/src/mainboard/sifive/hifive-unleashed/Makefile.inc @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only bootblock-y += memlayout.ld diff --git a/src/mainboard/supermicro/x10slm-f/cmos.layout b/src/mainboard/supermicro/x10slm-f/cmos.layout index 1137d0989b..65b1d9b830 100644 --- a/src/mainboard/supermicro/x10slm-f/cmos.layout +++ b/src/mainboard/supermicro/x10slm-f/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc index 0e5902ae2e..d64fcb35ec 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc +++ b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/mainboard/supermicro/x11-lga1151-series/cmos.layout b/src/mainboard/supermicro/x11-lga1151-series/cmos.layout index 09ef6bdb58..80f3f4e8bb 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/cmos.layout +++ b/src/mainboard/supermicro/x11-lga1151-series/cmos.layout @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- diff --git a/src/mainboard/ti/Kconfig b/src/mainboard/ti/Kconfig index 57dfa08740..53cab9ba8b 100644 --- a/src/mainboard/ti/Kconfig +++ b/src/mainboard/ti/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if VENDOR_TI diff --git a/src/mainboard/ti/beaglebone/Makefile.inc b/src/mainboard/ti/beaglebone/Makefile.inc index c11cde4e13..cf3fc5d79a 100644 --- a/src/mainboard/ti/beaglebone/Makefile.inc +++ b/src/mainboard/ti/beaglebone/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc index 1d97d5ea02..ca9096ca80 100644 --- a/src/northbridge/amd/agesa/Makefile.inc +++ b/src/northbridge/amd/agesa/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_NORTHBRIDGE_AMD_AGESA),y) diff --git a/src/northbridge/amd/agesa/family14/Makefile.inc b/src/northbridge/amd/agesa/family14/Makefile.inc index b069b9e2d1..adcb86b34f 100644 --- a/src/northbridge/amd/agesa/family14/Makefile.inc +++ b/src/northbridge/amd/agesa/family14/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only romstage-y += dimmSpd.c diff --git a/src/northbridge/amd/agesa/family15tn/Makefile.inc b/src/northbridge/amd/agesa/family15tn/Makefile.inc index 069780af73..a865929d87 100644 --- a/src/northbridge/amd/agesa/family15tn/Makefile.inc +++ b/src/northbridge/amd/agesa/family15tn/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only romstage-y += dimmSpd.c diff --git a/src/northbridge/amd/agesa/family16kb/Makefile.inc b/src/northbridge/amd/agesa/family16kb/Makefile.inc index b069b9e2d1..adcb86b34f 100644 --- a/src/northbridge/amd/agesa/family16kb/Makefile.inc +++ b/src/northbridge/amd/agesa/family16kb/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only romstage-y += dimmSpd.c diff --git a/src/northbridge/amd/pi/00630F01/Makefile.inc b/src/northbridge/amd/pi/00630F01/Makefile.inc index 160557262c..f7a402e78e 100644 --- a/src/northbridge/amd/pi/00630F01/Makefile.inc +++ b/src/northbridge/amd/pi/00630F01/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only romstage-y += dimmSpd.c diff --git a/src/northbridge/amd/pi/00660F01/Makefile.inc b/src/northbridge/amd/pi/00660F01/Makefile.inc index cfa918fc27..7fd37f2611 100644 --- a/src/northbridge/amd/pi/00660F01/Makefile.inc +++ b/src/northbridge/amd/pi/00660F01/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only romstage-y += dimmSpd.c diff --git a/src/northbridge/amd/pi/00730F01/Makefile.inc b/src/northbridge/amd/pi/00730F01/Makefile.inc index 4d43765e56..b97b335b70 100644 --- a/src/northbridge/amd/pi/00730F01/Makefile.inc +++ b/src/northbridge/amd/pi/00730F01/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only romstage-y += dimmSpd.c diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc index efe79c68c9..7c66b56168 100644 --- a/src/northbridge/amd/pi/Makefile.inc +++ b/src/northbridge/amd/pi/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_NORTHBRIDGE_AMD_PI),y) diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index 17e510822a..db9dc3f9ac 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_NORTHBRIDGE_INTEL_GM45),y) diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index 6eb6978310..8ef3079f51 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_NORTHBRIDGE_INTEL_HASWELL),y) diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index d1214308e0..8023d47614 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I945),y) diff --git a/src/northbridge/intel/ironlake/Makefile.inc b/src/northbridge/intel/ironlake/Makefile.inc index 43dd124ae5..e3d41f1aed 100644 --- a/src/northbridge/intel/ironlake/Makefile.inc +++ b/src/northbridge/intel/ironlake/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_NORTHBRIDGE_INTEL_IRONLAKE),y) diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index bd7d58958a..08e04f20e2 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_NORTHBRIDGE_INTEL_PINEVIEW),y) diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index e96510bc52..6ca0df29fe 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_NORTHBRIDGE_INTEL_X4X),y) diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index e794bf724f..bc1dc5ca9b 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_VBOOT_LIB),y) diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc index dd9f745f6d..89d8fb6eff 100644 --- a/src/soc/cavium/cn81xx/Makefile.inc +++ b/src/soc/cavium/cn81xx/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOC_CAVIUM_CN81XX),y) diff --git a/src/soc/cavium/common/Makefile.inc b/src/soc/cavium/common/Makefile.inc index 54b18e8788..3ca81e7896 100644 --- a/src/soc/cavium/common/Makefile.inc +++ b/src/soc/cavium/common/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOC_CAVIUM_COMMON),y) diff --git a/src/soc/intel/cannonlake/romstage/Makefile.inc b/src/soc/intel/cannonlake/romstage/Makefile.inc index 51e88323ee..261e5b352b 100644 --- a/src/soc/intel/cannonlake/romstage/Makefile.inc +++ b/src/soc/intel/cannonlake/romstage/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only romstage-y += ../../../../cpu/intel/car/romstage.c diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index c6b71dc4f4..105f866bf5 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOC_INTEL_DENVERTON_NS),y) diff --git a/src/soc/intel/icelake/romstage/Makefile.inc b/src/soc/intel/icelake/romstage/Makefile.inc index 2de1a57467..a1a6c6638d 100644 --- a/src/soc/intel/icelake/romstage/Makefile.inc +++ b/src/soc/intel/icelake/romstage/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only romstage-y += fsp_params.c diff --git a/src/soc/intel/jasperlake/romstage/Makefile.inc b/src/soc/intel/jasperlake/romstage/Makefile.inc index 2de1a57467..a1a6c6638d 100644 --- a/src/soc/intel/jasperlake/romstage/Makefile.inc +++ b/src/soc/intel/jasperlake/romstage/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only romstage-y += fsp_params.c diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index b49ee3e2b9..387884a2c9 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOC_INTEL_QUARK),y) diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 99f72bd429..8630acb4dd 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only romstage-y += car.c diff --git a/src/soc/intel/tigerlake/romstage/Makefile.inc b/src/soc/intel/tigerlake/romstage/Makefile.inc index 2de1a57467..a1a6c6638d 100644 --- a/src/soc/intel/tigerlake/romstage/Makefile.inc +++ b/src/soc/intel/tigerlake/romstage/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only romstage-y += fsp_params.c diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index f137313ded..86fdf1bfa3 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -1,6 +1,4 @@ -## ## SPDX-License-Identifier: GPL-2.0-only -## if SOC_INTEL_COOPERLAKE_SP diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index 4d283d6f71..6c0d6c05e5 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -1,6 +1,4 @@ -## ## SPDX-License-Identifier: GPL-2.0-only -## ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y) diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index 2c4235e5f5..7af0b582cb 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -1,6 +1,4 @@ -## ## SPDX-License-Identifier: GPL-2.0-only -## if SOC_INTEL_SKYLAKE_SP diff --git a/src/soc/intel/xeon_sp/skx/Makefile.inc b/src/soc/intel/xeon_sp/skx/Makefile.inc index 5c2242b300..773ced0fec 100644 --- a/src/soc/intel/xeon_sp/skx/Makefile.inc +++ b/src/soc/intel/xeon_sp/skx/Makefile.inc @@ -1,6 +1,4 @@ -## ## SPDX-License-Identifier: GPL-2.0-only -## ifeq ($(CONFIG_SOC_INTEL_SKYLAKE_SP),y) diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index fc99798ac8..871a68995d 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOC_MEDIATEK_MT8173),y) diff --git a/src/soc/nvidia/tegra124/lp0/Makefile b/src/soc/nvidia/tegra124/lp0/Makefile index 248c6ba980..68a3cb6da7 100644 --- a/src/soc/nvidia/tegra124/lp0/Makefile +++ b/src/soc/nvidia/tegra124/lp0/Makefile @@ -1,6 +1,3 @@ -################################################################################ -## -## ## SPDX-License-Identifier: GPL-2.0-only -include ../../../../../.xcompile diff --git a/src/soc/nvidia/tegra210/lp0/Makefile b/src/soc/nvidia/tegra210/lp0/Makefile index 248c6ba980..68a3cb6da7 100644 --- a/src/soc/nvidia/tegra210/lp0/Makefile +++ b/src/soc/nvidia/tegra210/lp0/Makefile @@ -1,6 +1,3 @@ -################################################################################ -## -## ## SPDX-License-Identifier: GPL-2.0-only -include ../../../../../.xcompile diff --git a/src/soc/qualcomm/ipq40xx/Makefile.inc b/src/soc/qualcomm/ipq40xx/Makefile.inc index f151b4d9fa..bd61a62a45 100644 --- a/src/soc/qualcomm/ipq40xx/Makefile.inc +++ b/src/soc/qualcomm/ipq40xx/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOC_QC_IPQ40XX),y) diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 4cba6b1c6a..c01486d3a8 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOC_QC_IPQ806X),y) diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index ee3d05142e..527c04d62b 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOC_ROCKCHIP_RK3288),y) diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc index 467ca54543..763e11a5d5 100644 --- a/src/soc/rockchip/rk3399/Makefile.inc +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOC_ROCKCHIP_RK3399),y) diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc index 333530a75e..734b4a258a 100644 --- a/src/soc/sifive/fu540/Makefile.inc +++ b/src/soc/sifive/fu540/Makefile.inc @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOC_SIFIVE_FU540),y) diff --git a/src/southbridge/amd/agesa/Makefile.inc b/src/southbridge/amd/agesa/Makefile.inc index 8f0e516e7a..21985561bd 100644 --- a/src/southbridge/amd/agesa/Makefile.inc +++ b/src/southbridge/amd/agesa/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += hudson diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc index 790b730473..f814729753 100644 --- a/src/southbridge/amd/cimx/Makefile.inc +++ b/src/southbridge/amd/cimx/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800 diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index cd502aa498..1ac69aede2 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only # SB800 Platform Files diff --git a/src/southbridge/amd/pi/Makefile.inc b/src/southbridge/amd/pi/Makefile.inc index 2640fc5bec..6bfa9740a5 100644 --- a/src/southbridge/amd/pi/Makefile.inc +++ b/src/southbridge/amd/pi/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += hudson diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 70e9a5a716..b3c48fa99c 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # CONFIG_HAVE_INTEL_FIRMWARE protects doing anything to the build. diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index 273305b661..df9a57f168 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_HAVE_INTEL_FIRMWARE),y) diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc index 0c9df06d5b..d7b23717ca 100644 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801DX),y) diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index c948034e58..7922dfc0be 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y) diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index 04488a086e..cbc1780f25 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801IX),y) diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index 88cd1ad275..b420fda143 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801JX),y) diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 2b2b41ca49..bd7f93c34b 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK),y) diff --git a/src/southbridge/ti/pci7420/Makefile.inc b/src/southbridge/ti/pci7420/Makefile.inc index 4f89e5ff1c..07794cfe7d 100644 --- a/src/southbridge/ti/pci7420/Makefile.inc +++ b/src/southbridge/ti/pci7420/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOUTHBRIDGE_TI_PCI7420),y) diff --git a/src/southbridge/ti/pcixx12/Makefile.inc b/src/southbridge/ti/pcixx12/Makefile.inc index 33339378db..337a42c133 100644 --- a/src/southbridge/ti/pcixx12/Makefile.inc +++ b/src/southbridge/ti/pcixx12/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOUTHBRIDGE_TI_PCIXX12),y) From 44e310bc6cffa0ee71bc137c2bd007aea87d0265 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 13 May 2020 10:12:34 +0200 Subject: [PATCH 098/405] mainboard/*/*/Kconfig*: Remove leading blank lines from SPDX header Change-Id: I7089b29e881d74d31477e2df1c5fa043fe353343 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41358 Reviewed-by: Wim Vervoorn Reviewed-by: Frans Hendriks Reviewed-by: Patrick Georgi Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/amd/gardenia/Kconfig | 3 --- src/mainboard/amd/inagua/Kconfig | 3 --- src/mainboard/amd/olivehill/Kconfig | 3 --- src/mainboard/amd/padmelon/Kconfig | 3 --- src/mainboard/amd/parmer/Kconfig | 3 --- src/mainboard/amd/persimmon/Kconfig | 3 --- src/mainboard/amd/south_station/Kconfig | 3 --- src/mainboard/amd/thatcher/Kconfig | 3 --- src/mainboard/amd/union_station/Kconfig | 3 --- src/mainboard/asrock/b75pro3-m/Kconfig | 3 --- src/mainboard/asrock/e350m1/Kconfig | 3 --- src/mainboard/asrock/g41c-gs/Kconfig | 3 --- src/mainboard/asrock/imb-a180/Kconfig | 3 --- src/mainboard/asus/f2a85-m/Kconfig | 3 --- src/mainboard/asus/p2b/Kconfig | 3 --- src/mainboard/asus/p5gc-mx/Kconfig | 3 --- src/mainboard/asus/p5qc/Kconfig | 3 --- src/mainboard/asus/p5ql-em/Kconfig | 2 -- src/mainboard/asus/p5qpl-am/Kconfig | 3 --- src/mainboard/asus/p8h61-m_pro/Kconfig | 3 --- src/mainboard/asus/p8z77-m_pro/Kconfig | 3 --- src/mainboard/asus/p8z77-m_pro/Kconfig.name | 3 --- src/mainboard/asus/p8z77-v_lx2/Kconfig | 3 --- src/mainboard/bap/ode_e20XX/Kconfig | 3 --- src/mainboard/bap/ode_e21XX/Kconfig | 3 --- src/mainboard/biostar/a68n_5200/Kconfig | 3 --- src/mainboard/biostar/am1ml/Kconfig | 3 --- src/mainboard/cavium/cn8100_sff_evb/Kconfig | 3 --- src/mainboard/elmex/pcm205400/Kconfig | 3 --- src/mainboard/elmex/pcm205401/Kconfig | 3 --- src/mainboard/emulation/qemu-aarch64/Kconfig | 3 --- src/mainboard/emulation/qemu-armv7/Kconfig | 3 --- src/mainboard/emulation/qemu-power8/Kconfig | 3 --- src/mainboard/emulation/qemu-riscv/Kconfig | 3 --- src/mainboard/emulation/spike-riscv/Kconfig | 3 --- src/mainboard/facebook/fbg1701/Kconfig | 3 --- src/mainboard/foxconn/d41s/Kconfig | 3 --- src/mainboard/foxconn/g41s-k/Kconfig | 3 --- src/mainboard/getac/p470/Kconfig | 3 --- src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig | 3 --- src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 3 --- src/mainboard/gigabyte/ga-h61m-series/Kconfig | 3 --- src/mainboard/gizmosphere/gizmo/Kconfig | 3 --- src/mainboard/gizmosphere/gizmo2/Kconfig | 3 --- src/mainboard/google/daisy/Kconfig | 3 --- src/mainboard/google/foster/Kconfig | 3 --- src/mainboard/google/gale/Kconfig | 3 --- src/mainboard/google/gru/Kconfig | 3 --- src/mainboard/google/kahlee/Kconfig | 3 --- src/mainboard/google/kukui/Kconfig | 3 --- src/mainboard/google/nyan/Kconfig | 3 --- src/mainboard/google/nyan_big/Kconfig | 3 --- src/mainboard/google/nyan_blaze/Kconfig | 3 --- src/mainboard/google/oak/Kconfig | 3 --- src/mainboard/google/peach_pit/Kconfig | 3 --- src/mainboard/google/smaug/Kconfig | 3 --- src/mainboard/google/storm/Kconfig | 3 --- src/mainboard/google/veyron/Kconfig | 3 --- src/mainboard/google/veyron_mickey/Kconfig | 3 --- src/mainboard/google/veyron_rialto/Kconfig | 3 --- src/mainboard/hp/abm/Kconfig | 3 --- src/mainboard/hp/pavilion_m6_1035dx/Kconfig | 3 --- src/mainboard/hp/snb_ivb_laptops/Kconfig | 3 --- src/mainboard/hp/snb_ivb_laptops/Kconfig.name | 3 --- src/mainboard/intel/d510mo/Kconfig | 3 --- src/mainboard/intel/d945gclf/Kconfig | 3 --- src/mainboard/intel/dg41wv/Kconfig | 3 --- src/mainboard/intel/dg43gt/Kconfig | 3 --- src/mainboard/intel/galileo/Kconfig | 3 --- src/mainboard/intel/galileo/Kconfig.name | 3 --- src/mainboard/intel/harcuvar/Kconfig | 3 --- src/mainboard/intel/saddlebrook/Kconfig | 3 --- src/mainboard/jetway/nf81-t56n-lf/Kconfig | 3 --- src/mainboard/lenovo/g505s/Kconfig | 3 --- src/mainboard/lenovo/thinkcentre_a58/Kconfig | 3 --- src/mainboard/lippert/frontrunner-af/Kconfig | 3 --- src/mainboard/lippert/toucan-af/Kconfig | 3 --- src/mainboard/msi/ms7721/Kconfig | 4 ---- src/mainboard/opencellular/elgon/Kconfig | 3 --- src/mainboard/pcengines/apu1/Kconfig | 3 --- src/mainboard/pcengines/apu2/Kconfig | 3 --- src/mainboard/portwell/m107/Kconfig | 3 --- src/mainboard/scaleway/tagada/Kconfig | 3 --- src/mainboard/sifive/hifive-unleashed/Kconfig | 2 -- src/mainboard/ti/beaglebone/Kconfig | 3 --- 85 files changed, 254 deletions(-) diff --git a/src/mainboard/amd/gardenia/Kconfig b/src/mainboard/amd/gardenia/Kconfig index 8a04fbe193..a77aa6907e 100644 --- a/src/mainboard/amd/gardenia/Kconfig +++ b/src/mainboard/amd/gardenia/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_AMD_GARDENIA diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index 19a9802653..a0d0434383 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_AMD_INAGUA diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index 3008637e01..3a0c98e050 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_AMD_OLIVEHILL diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig index a9fce4d4cc..428ea84cfe 100644 --- a/src/mainboard/amd/padmelon/Kconfig +++ b/src/mainboard/amd/padmelon/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_AMD_PADMELON diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index 5d34c43a38..204e4978e9 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_AMD_PARMER diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index 841015f45b..3c268f8f3e 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_AMD_PERSIMMON diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index 2037228afe..81b6dac8c5 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_AMD_SOUTHSTATION diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index 17af559ff3..c0cc7127d1 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_AMD_THATCHER diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index 3ba7928563..57eafebd64 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_AMD_UNIONSTATION diff --git a/src/mainboard/asrock/b75pro3-m/Kconfig b/src/mainboard/asrock/b75pro3-m/Kconfig index 8c27ddc339..577423c508 100644 --- a/src/mainboard/asrock/b75pro3-m/Kconfig +++ b/src/mainboard/asrock/b75pro3-m/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_ASROCK_B75PRO3_M diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 06e8aa700c..091d57a2bf 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_ASROCK_E350M1 diff --git a/src/mainboard/asrock/g41c-gs/Kconfig b/src/mainboard/asrock/g41c-gs/Kconfig index 6c0c8d2dd7..7ffe62f4d3 100644 --- a/src/mainboard/asrock/g41c-gs/Kconfig +++ b/src/mainboard/asrock/g41c-gs/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_ASROCK_G41C_GS || BOARD_ASROCK_G41C_GS_R2_0 || \ diff --git a/src/mainboard/asrock/imb-a180/Kconfig b/src/mainboard/asrock/imb-a180/Kconfig index 29e9cbd4e0..4d9b1e8639 100644 --- a/src/mainboard/asrock/imb-a180/Kconfig +++ b/src/mainboard/asrock/imb-a180/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_ASROCK_IMB_A180 diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index f4471a7f7d..8413cd3863 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO || BOARD_ASUS_F2A85_M_LE diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index f1fbe789dc..f21de714c8 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_ASUS_P2B || BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS || BOARD_ASUS_P2B_F || BOARD_ASUS_P2B_LS || BOARD_ASUS_P3B_F diff --git a/src/mainboard/asus/p5gc-mx/Kconfig b/src/mainboard/asus/p5gc-mx/Kconfig index 381e28bef9..550722b3b7 100644 --- a/src/mainboard/asus/p5gc-mx/Kconfig +++ b/src/mainboard/asus/p5gc-mx/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_ASUS_P5GC_MX diff --git a/src/mainboard/asus/p5qc/Kconfig b/src/mainboard/asus/p5qc/Kconfig index bf8b6abb32..b9feb45c80 100644 --- a/src/mainboard/asus/p5qc/Kconfig +++ b/src/mainboard/asus/p5qc/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_ASUS_P5QC || BOARD_ASUS_P5Q_PRO || BOARD_ASUS_P5QL_PRO || BOARD_ASUS_P5Q diff --git a/src/mainboard/asus/p5ql-em/Kconfig b/src/mainboard/asus/p5ql-em/Kconfig index a7c0617b86..1aafb7ffb2 100644 --- a/src/mainboard/asus/p5ql-em/Kconfig +++ b/src/mainboard/asus/p5ql-em/Kconfig @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_ASUS_P5QL_EM diff --git a/src/mainboard/asus/p5qpl-am/Kconfig b/src/mainboard/asus/p5qpl-am/Kconfig index 2ca937db96..4c4381abe0 100644 --- a/src/mainboard/asus/p5qpl-am/Kconfig +++ b/src/mainboard/asus/p5qpl-am/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_ASUS_P5QPL_AM || BOARD_ASUS_P5G41T_M_LX diff --git a/src/mainboard/asus/p8h61-m_pro/Kconfig b/src/mainboard/asus/p8h61-m_pro/Kconfig index bc8c5acde3..05bb00d5ff 100644 --- a/src/mainboard/asus/p8h61-m_pro/Kconfig +++ b/src/mainboard/asus/p8h61-m_pro/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_ASUS_P8H61_M_PRO diff --git a/src/mainboard/asus/p8z77-m_pro/Kconfig b/src/mainboard/asus/p8z77-m_pro/Kconfig index 8d9bf15ddc..5973e3a21b 100644 --- a/src/mainboard/asus/p8z77-m_pro/Kconfig +++ b/src/mainboard/asus/p8z77-m_pro/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_ASUS_P8Z77_M_PRO diff --git a/src/mainboard/asus/p8z77-m_pro/Kconfig.name b/src/mainboard/asus/p8z77-m_pro/Kconfig.name index ed02ef1954..372ec4a7da 100644 --- a/src/mainboard/asus/p8z77-m_pro/Kconfig.name +++ b/src/mainboard/asus/p8z77-m_pro/Kconfig.name @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only config BOARD_ASUS_P8Z77_M_PRO diff --git a/src/mainboard/asus/p8z77-v_lx2/Kconfig b/src/mainboard/asus/p8z77-v_lx2/Kconfig index 46a99e7390..e49f118641 100644 --- a/src/mainboard/asus/p8z77-v_lx2/Kconfig +++ b/src/mainboard/asus/p8z77-v_lx2/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_ASUS_P8Z77_V_LX2 diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index bd61105d94..3503e65cef 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_ODE_E20XX diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig index 171929ce77..a454e8ac5a 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig +++ b/src/mainboard/bap/ode_e21XX/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only config BOARD_ODE_E21XX diff --git a/src/mainboard/biostar/a68n_5200/Kconfig b/src/mainboard/biostar/a68n_5200/Kconfig index 75c05f7270..506d6ba67a 100644 --- a/src/mainboard/biostar/a68n_5200/Kconfig +++ b/src/mainboard/biostar/a68n_5200/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_BIOSTAR_A68N5200 diff --git a/src/mainboard/biostar/am1ml/Kconfig b/src/mainboard/biostar/am1ml/Kconfig index 5240ca8f7b..de2b85d66d 100644 --- a/src/mainboard/biostar/am1ml/Kconfig +++ b/src/mainboard/biostar/am1ml/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_BIOSTAR_AM1ML diff --git a/src/mainboard/cavium/cn8100_sff_evb/Kconfig b/src/mainboard/cavium/cn8100_sff_evb/Kconfig index 90866d3e9d..1c3d2ec215 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/Kconfig +++ b/src/mainboard/cavium/cn8100_sff_evb/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_CAVIUM_CN8100_SFF_EVB diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig index 9e14c2bf8c..ba7aa5b695 100644 --- a/src/mainboard/elmex/pcm205400/Kconfig +++ b/src/mainboard/elmex/pcm205400/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_ELMEX_PCM205400 diff --git a/src/mainboard/elmex/pcm205401/Kconfig b/src/mainboard/elmex/pcm205401/Kconfig index f7117f3ba6..fbb8e9e44f 100644 --- a/src/mainboard/elmex/pcm205401/Kconfig +++ b/src/mainboard/elmex/pcm205401/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_ELMEX_PCM205401 diff --git a/src/mainboard/emulation/qemu-aarch64/Kconfig b/src/mainboard/emulation/qemu-aarch64/Kconfig index 95fc47bf2f..b8896d28d1 100644 --- a/src/mainboard/emulation/qemu-aarch64/Kconfig +++ b/src/mainboard/emulation/qemu-aarch64/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-or-later # Emulation for QEMU 2.8 ARM Virtual Machine (alias of virt-2.8) diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index f3dc02f699..4af58434bc 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # Emulation for ARM Ltd Versatile Express Cortex-A9 diff --git a/src/mainboard/emulation/qemu-power8/Kconfig b/src/mainboard/emulation/qemu-power8/Kconfig index 1ed253de06..aa3aceb367 100644 --- a/src/mainboard/emulation/qemu-power8/Kconfig +++ b/src/mainboard/emulation/qemu-power8/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # To execute, do: diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index 30d0ec1cdd..66aa599864 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # To execute, do: diff --git a/src/mainboard/emulation/spike-riscv/Kconfig b/src/mainboard/emulation/spike-riscv/Kconfig index dbae761d2f..c46a04781c 100644 --- a/src/mainboard/emulation/spike-riscv/Kconfig +++ b/src/mainboard/emulation/spike-riscv/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_EMULATION_SPIKE_RISCV diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index 7b37ad57c8..ca19e0582c 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_FACEBOOK_FBG1701 diff --git a/src/mainboard/foxconn/d41s/Kconfig b/src/mainboard/foxconn/d41s/Kconfig index d5870723d6..a272d1e898 100644 --- a/src/mainboard/foxconn/d41s/Kconfig +++ b/src/mainboard/foxconn/d41s/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_FOXCONN_D41S diff --git a/src/mainboard/foxconn/g41s-k/Kconfig b/src/mainboard/foxconn/g41s-k/Kconfig index 4ed741d59b..c8cd1839ce 100644 --- a/src/mainboard/foxconn/g41s-k/Kconfig +++ b/src/mainboard/foxconn/g41s-k/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_FOXCONN_G41S_K || BOARD_FOXCONN_G41M diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index e7986ce347..283ff65759 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_GETAC_P470 diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig index 703c4511d8..8709083c88 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_GIGABYTE_GA_945GCM_S2L || BOARD_GIGABYTE_GA_945GCM_S2C diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index ca526e93ac..fa6783d1f7 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_GIGABYTE_GA_G41M_ES2L diff --git a/src/mainboard/gigabyte/ga-h61m-series/Kconfig b/src/mainboard/gigabyte/ga-h61m-series/Kconfig index e7e0436b7a..05c59d5258 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/Kconfig +++ b/src/mainboard/gigabyte/ga-h61m-series/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_GIGABYTE_GA_H61M_S2PV || BOARD_GIGABYTE_GA_H61M_DS2V || BOARD_GIGABYTE_GA_H61MA_D3V diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index d5dabffd52..7c667b527d 100644 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_GIZMOSPHERE_GIZMO diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index 761c4443a7..7a02ec851b 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_GIZMOSPHERE_GIZMO2 diff --git a/src/mainboard/google/daisy/Kconfig b/src/mainboard/google/daisy/Kconfig index 0b09f9d6e2..659e3303aa 100644 --- a/src/mainboard/google/daisy/Kconfig +++ b/src/mainboard/google/daisy/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_GOOGLE_DAISY diff --git a/src/mainboard/google/foster/Kconfig b/src/mainboard/google/foster/Kconfig index a7a638385f..61c445c4e1 100644 --- a/src/mainboard/google/foster/Kconfig +++ b/src/mainboard/google/foster/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_GOOGLE_FOSTER diff --git a/src/mainboard/google/gale/Kconfig b/src/mainboard/google/gale/Kconfig index 2e3ba840e6..214a18e128 100644 --- a/src/mainboard/google/gale/Kconfig +++ b/src/mainboard/google/gale/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_GOOGLE_GALE diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index d559a9ab98..cf226b4268 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only config BOARD_GOOGLE_GRU_COMMON # Umbrella option to be selected by variant boards. diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 4e4402ce9b..07eb585eff 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only config BOARD_GOOGLE_BASEBOARD_KAHLEE diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 71bc2c4541..4c8ebbfcf4 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # Umbrella option to be selected by variant boards. diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index 974cebbca8..56ec39806e 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_GOOGLE_NYAN diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig index 820faa6953..7c65595150 100644 --- a/src/mainboard/google/nyan_big/Kconfig +++ b/src/mainboard/google/nyan_big/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_GOOGLE_NYAN_BIG diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig index a29c1e3ffc..59f7912c13 100644 --- a/src/mainboard/google/nyan_blaze/Kconfig +++ b/src/mainboard/google/nyan_blaze/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_GOOGLE_NYAN_BLAZE diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index 9b1365768d..d8986c63c9 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only config BOARD_GOOGLE_OAK_COMMON diff --git a/src/mainboard/google/peach_pit/Kconfig b/src/mainboard/google/peach_pit/Kconfig index 207862a382..e3da4b98e3 100644 --- a/src/mainboard/google/peach_pit/Kconfig +++ b/src/mainboard/google/peach_pit/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_GOOGLE_PEACH_PIT diff --git a/src/mainboard/google/smaug/Kconfig b/src/mainboard/google/smaug/Kconfig index 1b18593665..ef619c4182 100644 --- a/src/mainboard/google/smaug/Kconfig +++ b/src/mainboard/google/smaug/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_GOOGLE_SMAUG diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig index df06b2bdc9..e17109c702 100644 --- a/src/mainboard/google/storm/Kconfig +++ b/src/mainboard/google/storm/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_GOOGLE_STORM diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig index 9093f81522..1d3496cd6d 100644 --- a/src/mainboard/google/veyron/Kconfig +++ b/src/mainboard/google/veyron/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only config BOARD_GOOGLE_VEYRON # dummy option to be selected by variant boards diff --git a/src/mainboard/google/veyron_mickey/Kconfig b/src/mainboard/google/veyron_mickey/Kconfig index b065a21140..b958c06474 100644 --- a/src/mainboard/google/veyron_mickey/Kconfig +++ b/src/mainboard/google/veyron_mickey/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_GOOGLE_VEYRON_MICKEY diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index 397cd681dc..b5f6b2d266 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_GOOGLE_VEYRON_RIALTO diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig index f4afb20a8c..ce8ecee5a8 100644 --- a/src/mainboard/hp/abm/Kconfig +++ b/src/mainboard/hp/abm/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_HP_ABM diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index 6a18d23f51..77c929f29d 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_HP_PAVILION_M6_1035DX diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig b/src/mainboard/hp/snb_ivb_laptops/Kconfig index 4822c4d92d..c4cd3a4b59 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only config BOARD_HP_SNB_IVB_LAPTOPS diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name index 791e07bc6f..c01555fd13 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only config BOARD_HP_2570P diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig index 80eafa9863..be0190f84b 100644 --- a/src/mainboard/intel/d510mo/Kconfig +++ b/src/mainboard/intel/d510mo/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_INTEL_D510MO diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index d1ef90a67f..c8c7808e2f 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_INTEL_D945GCLF diff --git a/src/mainboard/intel/dg41wv/Kconfig b/src/mainboard/intel/dg41wv/Kconfig index 4b62186441..9948638713 100644 --- a/src/mainboard/intel/dg41wv/Kconfig +++ b/src/mainboard/intel/dg41wv/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_INTEL_DG41WV diff --git a/src/mainboard/intel/dg43gt/Kconfig b/src/mainboard/intel/dg43gt/Kconfig index 0004ea979c..d56a05569d 100644 --- a/src/mainboard/intel/dg43gt/Kconfig +++ b/src/mainboard/intel/dg43gt/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_INTEL_DG43GT diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index d35047b054..6fee2f3443 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_INTEL_GALILEO diff --git a/src/mainboard/intel/galileo/Kconfig.name b/src/mainboard/intel/galileo/Kconfig.name index 5806722a26..61ea9c3186 100644 --- a/src/mainboard/intel/galileo/Kconfig.name +++ b/src/mainboard/intel/galileo/Kconfig.name @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only config BOARD_INTEL_GALILEO diff --git a/src/mainboard/intel/harcuvar/Kconfig b/src/mainboard/intel/harcuvar/Kconfig index 085b0b3cf5..d110c281a2 100644 --- a/src/mainboard/intel/harcuvar/Kconfig +++ b/src/mainboard/intel/harcuvar/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_INTEL_HARCUVAR diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index 1db0777396..f94cd54fd5 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_INTEL_SKLSDLBRK diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index c71ae801b1..442d097062 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_JETWAY_NF81_T56N_LF diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 72da01f0fd..65201ab4c3 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_LENOVO_G505S diff --git a/src/mainboard/lenovo/thinkcentre_a58/Kconfig b/src/mainboard/lenovo/thinkcentre_a58/Kconfig index 98fdc6b926..2ccfab1bd3 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/Kconfig +++ b/src/mainboard/lenovo/thinkcentre_a58/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_LENOVO_THINKCENTRE_A58 diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index e98add82a9..80b517212a 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_LIPPERT_FRONTRUNNER_AF diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index 9a896680b6..102b1d7bc7 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_LIPPERT_TOUCAN_AF diff --git a/src/mainboard/msi/ms7721/Kconfig b/src/mainboard/msi/ms7721/Kconfig index d2583f95c9..fe7c9edad7 100644 --- a/src/mainboard/msi/ms7721/Kconfig +++ b/src/mainboard/msi/ms7721/Kconfig @@ -1,7 +1,3 @@ -# -# - -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_MSI_MS7721 diff --git a/src/mainboard/opencellular/elgon/Kconfig b/src/mainboard/opencellular/elgon/Kconfig index 79a1851458..2e9e01824c 100644 --- a/src/mainboard/opencellular/elgon/Kconfig +++ b/src/mainboard/opencellular/elgon/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_OPENCELLULAR_ELGON diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index fc476df6cf..f2f3b08d84 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_PCENGINES_APU1 diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 2c1f4f6aae..f0e53c6deb 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 || \ diff --git a/src/mainboard/portwell/m107/Kconfig b/src/mainboard/portwell/m107/Kconfig index ac825d2f31..f813b8e500 100644 --- a/src/mainboard/portwell/m107/Kconfig +++ b/src/mainboard/portwell/m107/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_PORTWELL_M107 diff --git a/src/mainboard/scaleway/tagada/Kconfig b/src/mainboard/scaleway/tagada/Kconfig index 66a0cfc848..34473a8a18 100644 --- a/src/mainboard/scaleway/tagada/Kconfig +++ b/src/mainboard/scaleway/tagada/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_SCALEWAY_TAGADA diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig b/src/mainboard/sifive/hifive-unleashed/Kconfig index 01689cd3de..e678fbdf62 100644 --- a/src/mainboard/sifive/hifive-unleashed/Kconfig +++ b/src/mainboard/sifive/hifive-unleashed/Kconfig @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only if BOARD_SIFIVE_HIFIVE_UNLEASHED diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig index 8a6bb1e54e..7399f22693 100644 --- a/src/mainboard/ti/beaglebone/Kconfig +++ b/src/mainboard/ti/beaglebone/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only if BOARD_TI_BEAGLEBONE From b3162b5a382995e048c33c35590abc93e1ac212d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 13 May 2020 10:26:30 +0200 Subject: [PATCH 099/405] mainboard/*/*/*.cb: Remove leading blank lines from SPDX header Change-Id: Ia0dbf7b946d42bda11b904a9caff5a402b553b33 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41359 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- src/mainboard/amd/gardenia/devicetree.cb | 3 --- src/mainboard/amd/inagua/devicetree.cb | 3 --- src/mainboard/amd/olivehill/devicetree.cb | 3 --- src/mainboard/amd/padmelon/devicetree.cb | 3 --- src/mainboard/amd/parmer/devicetree.cb | 3 --- src/mainboard/amd/persimmon/devicetree.cb | 3 --- src/mainboard/amd/south_station/devicetree.cb | 3 --- src/mainboard/amd/thatcher/devicetree.cb | 3 --- src/mainboard/amd/union_station/devicetree.cb | 3 --- src/mainboard/aopen/dxplplusu/devicetree.cb | 3 --- src/mainboard/apple/macbook21/devicetree.cb | 3 --- src/mainboard/asrock/e350m1/devicetree.cb | 3 --- src/mainboard/asrock/h110m/devicetree.cb | 3 --- src/mainboard/asrock/imb-a180/devicetree.cb | 3 --- src/mainboard/asus/am1i-a/devicetree.cb | 3 --- src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb | 3 --- src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb | 3 --- src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb | 3 --- src/mainboard/asus/p5gc-mx/devicetree.cb | 3 --- src/mainboard/asus/p8h61-m_pro/devicetree.cb | 3 --- src/mainboard/asus/p8z77-m_pro/devicetree.cb | 3 --- src/mainboard/asus/p8z77-v_lx2/devicetree.cb | 3 --- src/mainboard/bap/ode_e20XX/devicetree.cb | 3 --- src/mainboard/bap/ode_e21XX/devicetree.cb | 3 --- src/mainboard/biostar/a68n_5200/devicetree.cb | 3 --- src/mainboard/biostar/am1ml/devicetree.cb | 3 --- src/mainboard/cavium/cn8100_sff_evb/devicetree.cb | 3 --- src/mainboard/compulab/intense_pc/devicetree.cb | 2 -- src/mainboard/elmex/pcm205400/devicetree.cb | 3 --- src/mainboard/emulation/qemu-aarch64/devicetree.cb | 3 --- src/mainboard/emulation/qemu-armv7/devicetree.cb | 3 --- src/mainboard/emulation/qemu-power8/devicetree.cb | 3 --- src/mainboard/emulation/qemu-riscv/devicetree.cb | 3 --- src/mainboard/emulation/spike-riscv/devicetree.cb | 3 --- src/mainboard/getac/p470/devicetree.cb | 3 --- src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb | 3 --- src/mainboard/gizmosphere/gizmo/devicetree.cb | 3 --- src/mainboard/gizmosphere/gizmo2/devicetree.cb | 3 --- src/mainboard/google/daisy/devicetree.cb | 3 --- src/mainboard/google/foster/devicetree.cb | 3 --- src/mainboard/google/gale/devicetree.cb | 3 --- src/mainboard/google/gru/devicetree.cb | 3 --- src/mainboard/google/gru/devicetree.scarlet.cb | 3 --- src/mainboard/google/kukui/devicetree.cb | 3 --- src/mainboard/google/nyan/devicetree.cb | 3 --- src/mainboard/google/nyan_big/devicetree.cb | 3 --- src/mainboard/google/nyan_blaze/devicetree.cb | 3 --- src/mainboard/google/oak/devicetree.cb | 3 --- src/mainboard/google/peach_pit/devicetree.cb | 3 --- src/mainboard/google/smaug/devicetree.cb | 3 --- src/mainboard/google/storm/devicetree.cb | 3 --- src/mainboard/google/veyron/devicetree.cb | 3 --- src/mainboard/google/veyron_mickey/devicetree.cb | 3 --- src/mainboard/google/veyron_rialto/devicetree.cb | 3 --- src/mainboard/hp/abm/devicetree.cb | 3 --- src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb | 3 --- src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb | 3 --- src/mainboard/hp/z220_sff_workstation/devicetree.cb | 3 --- src/mainboard/intel/d945gclf/devicetree.cb | 3 --- src/mainboard/intel/galileo/devicetree.cb | 3 --- src/mainboard/intel/harcuvar/devicetree.cb | 3 --- src/mainboard/intel/saddlebrook/devicetree.cb | 3 --- src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 3 --- src/mainboard/lenovo/g505s/devicetree.cb | 3 --- src/mainboard/lenovo/t410/devicetree.cb | 3 --- src/mainboard/lenovo/t60/devicetree.cb | 3 --- src/mainboard/lenovo/x201/devicetree.cb | 3 --- src/mainboard/lenovo/x60/devicetree.cb | 3 --- src/mainboard/lippert/frontrunner-af/devicetree.cb | 3 --- src/mainboard/lippert/toucan-af/devicetree.cb | 3 --- src/mainboard/msi/ms7721/devicetree.cb | 3 --- src/mainboard/opencellular/elgon/devicetree.cb | 3 --- src/mainboard/packardbell/ms2290/devicetree.cb | 3 --- src/mainboard/pcengines/apu1/devicetree.cb | 3 --- src/mainboard/roda/rk886ex/devicetree.cb | 3 --- src/mainboard/scaleway/tagada/devicetree.cb | 3 --- src/mainboard/sifive/hifive-unleashed/devicetree.cb | 2 -- src/mainboard/ti/beaglebone/devicetree.cb | 3 --- 78 files changed, 232 deletions(-) diff --git a/src/mainboard/amd/gardenia/devicetree.cb b/src/mainboard/amd/gardenia/devicetree.cb index eeda8a22ef..fc7bde527f 100644 --- a/src/mainboard/amd/gardenia/devicetree.cb +++ b/src/mainboard/amd/gardenia/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip soc/amd/stoneyridge diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb index 499d8a90cd..d5a4e45415 100644 --- a/src/mainboard/amd/inagua/devicetree.cb +++ b/src/mainboard/amd/inagua/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/amd/olivehill/devicetree.cb b/src/mainboard/amd/olivehill/devicetree.cb index b13c938b93..05dc7234b4 100644 --- a/src/mainboard/amd/olivehill/devicetree.cb +++ b/src/mainboard/amd/olivehill/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/amd/padmelon/devicetree.cb b/src/mainboard/amd/padmelon/devicetree.cb index 266bdddee3..87d2b1ae04 100644 --- a/src/mainboard/amd/padmelon/devicetree.cb +++ b/src/mainboard/amd/padmelon/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip soc/amd/stoneyridge diff --git a/src/mainboard/amd/parmer/devicetree.cb b/src/mainboard/amd/parmer/devicetree.cb index 08a6a7ff29..1d11eef6b0 100644 --- a/src/mainboard/amd/parmer/devicetree.cb +++ b/src/mainboard/amd/parmer/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb index 39a78218ff..5670118ac5 100644 --- a/src/mainboard/amd/persimmon/devicetree.cb +++ b/src/mainboard/amd/persimmon/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/amd/south_station/devicetree.cb b/src/mainboard/amd/south_station/devicetree.cb index 193626e25c..1f898d55e4 100644 --- a/src/mainboard/amd/south_station/devicetree.cb +++ b/src/mainboard/amd/south_station/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/amd/thatcher/devicetree.cb b/src/mainboard/amd/thatcher/devicetree.cb index 8eae6c4913..3f7b190689 100644 --- a/src/mainboard/amd/thatcher/devicetree.cb +++ b/src/mainboard/amd/thatcher/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/amd/union_station/devicetree.cb b/src/mainboard/amd/union_station/devicetree.cb index e4a06935ef..185369a3d5 100644 --- a/src/mainboard/amd/union_station/devicetree.cb +++ b/src/mainboard/amd/union_station/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/aopen/dxplplusu/devicetree.cb b/src/mainboard/aopen/dxplplusu/devicetree.cb index f83008365e..166be3d786 100644 --- a/src/mainboard/aopen/dxplplusu/devicetree.cb +++ b/src/mainboard/aopen/dxplplusu/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/e7505 diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 8ed1b78837..bcce778cb1 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/i945 diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb index 26e63b337a..c1740dce2b 100644 --- a/src/mainboard/asrock/e350m1/devicetree.cb +++ b/src/mainboard/asrock/e350m1/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 301f01f400..9ff8ceb62d 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/intel/skylake diff --git a/src/mainboard/asrock/imb-a180/devicetree.cb b/src/mainboard/asrock/imb-a180/devicetree.cb index 9f3e1e00b2..cd959034c2 100644 --- a/src/mainboard/asrock/imb-a180/devicetree.cb +++ b/src/mainboard/asrock/imb-a180/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/asus/am1i-a/devicetree.cb b/src/mainboard/asus/am1i-a/devicetree.cb index 6c9c535f7e..be9ce8a87d 100644 --- a/src/mainboard/asus/am1i-a/devicetree.cb +++ b/src/mainboard/asus/am1i-a/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb index e6a373db5c..08a74e8ac7 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb index c9fa7bb552..bc0dc42de4 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index 5ea55b40a3..2aa2d89b08 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb index a059feacab..4c26925838 100644 --- a/src/mainboard/asus/p5gc-mx/devicetree.cb +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/i945 diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb index 8d4f8c6c17..b318573b40 100644 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/sandybridge diff --git a/src/mainboard/asus/p8z77-m_pro/devicetree.cb b/src/mainboard/asus/p8z77-m_pro/devicetree.cb index 19e6ac408c..90feb7ac6c 100644 --- a/src/mainboard/asus/p8z77-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8z77-m_pro/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/sandybridge diff --git a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb index 5d1a54c15d..8f51e15a09 100644 --- a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb +++ b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/sandybridge diff --git a/src/mainboard/bap/ode_e20XX/devicetree.cb b/src/mainboard/bap/ode_e20XX/devicetree.cb index 94fa43f2ac..7fc7055cf0 100644 --- a/src/mainboard/bap/ode_e20XX/devicetree.cb +++ b/src/mainboard/bap/ode_e20XX/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/bap/ode_e21XX/devicetree.cb b/src/mainboard/bap/ode_e21XX/devicetree.cb index 56c2b6978e..56acc20a82 100644 --- a/src/mainboard/bap/ode_e21XX/devicetree.cb +++ b/src/mainboard/bap/ode_e21XX/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/pi/00730F01/root_complex diff --git a/src/mainboard/biostar/a68n_5200/devicetree.cb b/src/mainboard/biostar/a68n_5200/devicetree.cb index edbe1dee26..a5ae59f136 100644 --- a/src/mainboard/biostar/a68n_5200/devicetree.cb +++ b/src/mainboard/biostar/a68n_5200/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/biostar/am1ml/devicetree.cb b/src/mainboard/biostar/am1ml/devicetree.cb index 27ed2f236a..c8d8d8f702 100644 --- a/src/mainboard/biostar/am1ml/devicetree.cb +++ b/src/mainboard/biostar/am1ml/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb b/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb index 679a114e83..ef8ac04556 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb +++ b/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/cavium/cn81xx diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index 64c049b73b..414c410b10 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/sandybridge # FIXME: check gfx diff --git a/src/mainboard/elmex/pcm205400/devicetree.cb b/src/mainboard/elmex/pcm205400/devicetree.cb index 403bff0823..bce8a2224a 100644 --- a/src/mainboard/elmex/pcm205400/devicetree.cb +++ b/src/mainboard/elmex/pcm205400/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/emulation/qemu-aarch64/devicetree.cb b/src/mainboard/emulation/qemu-aarch64/devicetree.cb index 36a16da2c2..533e451cbb 100644 --- a/src/mainboard/emulation/qemu-aarch64/devicetree.cb +++ b/src/mainboard/emulation/qemu-aarch64/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-or-later # This file exists only to avoid a compile error. It needs a devicetree.cb that is not empty. diff --git a/src/mainboard/emulation/qemu-armv7/devicetree.cb b/src/mainboard/emulation/qemu-armv7/devicetree.cb index e40ebe0adc..18ec632d22 100644 --- a/src/mainboard/emulation/qemu-armv7/devicetree.cb +++ b/src/mainboard/emulation/qemu-armv7/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only # TODO fill with Versatile Express board data in QEMU. diff --git a/src/mainboard/emulation/qemu-power8/devicetree.cb b/src/mainboard/emulation/qemu-power8/devicetree.cb index 401e818d68..075d6c0111 100644 --- a/src/mainboard/emulation/qemu-power8/devicetree.cb +++ b/src/mainboard/emulation/qemu-power8/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip cpu/qemu-power8 diff --git a/src/mainboard/emulation/qemu-riscv/devicetree.cb b/src/mainboard/emulation/qemu-riscv/devicetree.cb index 7b5a397f57..2b0d520b2b 100644 --- a/src/mainboard/emulation/qemu-riscv/devicetree.cb +++ b/src/mainboard/emulation/qemu-riscv/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/ucb/riscv diff --git a/src/mainboard/emulation/spike-riscv/devicetree.cb b/src/mainboard/emulation/spike-riscv/devicetree.cb index 7b5a397f57..2b0d520b2b 100644 --- a/src/mainboard/emulation/spike-riscv/devicetree.cb +++ b/src/mainboard/emulation/spike-riscv/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/ucb/riscv diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index 64251aff14..230cad4f27 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/i945 diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index 090c533068..d6f1f5329b 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/i945 diff --git a/src/mainboard/gizmosphere/gizmo/devicetree.cb b/src/mainboard/gizmosphere/gizmo/devicetree.cb index e11a3d8d71..33415f9b97 100644 --- a/src/mainboard/gizmosphere/gizmo/devicetree.cb +++ b/src/mainboard/gizmosphere/gizmo/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/gizmosphere/gizmo2/devicetree.cb b/src/mainboard/gizmosphere/gizmo2/devicetree.cb index 71c66d9a22..2897193795 100644 --- a/src/mainboard/gizmosphere/gizmo2/devicetree.cb +++ b/src/mainboard/gizmosphere/gizmo2/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/google/daisy/devicetree.cb b/src/mainboard/google/daisy/devicetree.cb index 83199ec9e6..26a4d230ec 100644 --- a/src/mainboard/google/daisy/devicetree.cb +++ b/src/mainboard/google/daisy/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/samsung/exynos5250 diff --git a/src/mainboard/google/foster/devicetree.cb b/src/mainboard/google/foster/devicetree.cb index 83bc760b65..cfa99b4998 100644 --- a/src/mainboard/google/foster/devicetree.cb +++ b/src/mainboard/google/foster/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/nvidia/tegra210 diff --git a/src/mainboard/google/gale/devicetree.cb b/src/mainboard/google/gale/devicetree.cb index 0ced64cc59..759e255398 100644 --- a/src/mainboard/google/gale/devicetree.cb +++ b/src/mainboard/google/gale/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/qualcomm/ipq40xx diff --git a/src/mainboard/google/gru/devicetree.cb b/src/mainboard/google/gru/devicetree.cb index c0f623b4c3..cddc3f28e5 100644 --- a/src/mainboard/google/gru/devicetree.cb +++ b/src/mainboard/google/gru/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/rockchip/rk3399 diff --git a/src/mainboard/google/gru/devicetree.scarlet.cb b/src/mainboard/google/gru/devicetree.scarlet.cb index 142b4f1792..ac4908114a 100644 --- a/src/mainboard/google/gru/devicetree.scarlet.cb +++ b/src/mainboard/google/gru/devicetree.scarlet.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/rockchip/rk3399 diff --git a/src/mainboard/google/kukui/devicetree.cb b/src/mainboard/google/kukui/devicetree.cb index a4f7a81b6a..8efab953d9 100644 --- a/src/mainboard/google/kukui/devicetree.cb +++ b/src/mainboard/google/kukui/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/mediatek/mt8183 diff --git a/src/mainboard/google/nyan/devicetree.cb b/src/mainboard/google/nyan/devicetree.cb index 161b016874..e81b4d7a21 100644 --- a/src/mainboard/google/nyan/devicetree.cb +++ b/src/mainboard/google/nyan/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/nvidia/tegra124 diff --git a/src/mainboard/google/nyan_big/devicetree.cb b/src/mainboard/google/nyan_big/devicetree.cb index 161b016874..e81b4d7a21 100644 --- a/src/mainboard/google/nyan_big/devicetree.cb +++ b/src/mainboard/google/nyan_big/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/nvidia/tegra124 diff --git a/src/mainboard/google/nyan_blaze/devicetree.cb b/src/mainboard/google/nyan_blaze/devicetree.cb index 161b016874..e81b4d7a21 100644 --- a/src/mainboard/google/nyan_blaze/devicetree.cb +++ b/src/mainboard/google/nyan_blaze/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/nvidia/tegra124 diff --git a/src/mainboard/google/oak/devicetree.cb b/src/mainboard/google/oak/devicetree.cb index 84a5ef748b..f021ab2670 100644 --- a/src/mainboard/google/oak/devicetree.cb +++ b/src/mainboard/google/oak/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/mediatek/mt8173 diff --git a/src/mainboard/google/peach_pit/devicetree.cb b/src/mainboard/google/peach_pit/devicetree.cb index 1cfa95917b..636a845748 100644 --- a/src/mainboard/google/peach_pit/devicetree.cb +++ b/src/mainboard/google/peach_pit/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/samsung/exynos5420 diff --git a/src/mainboard/google/smaug/devicetree.cb b/src/mainboard/google/smaug/devicetree.cb index eb2420f34a..247085cd84 100644 --- a/src/mainboard/google/smaug/devicetree.cb +++ b/src/mainboard/google/smaug/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/nvidia/tegra210 diff --git a/src/mainboard/google/storm/devicetree.cb b/src/mainboard/google/storm/devicetree.cb index 8074b78d9d..f81e69672e 100644 --- a/src/mainboard/google/storm/devicetree.cb +++ b/src/mainboard/google/storm/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/qualcomm/ipq806x diff --git a/src/mainboard/google/veyron/devicetree.cb b/src/mainboard/google/veyron/devicetree.cb index be71ef6ec3..ab47f10829 100644 --- a/src/mainboard/google/veyron/devicetree.cb +++ b/src/mainboard/google/veyron/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/rockchip/rk3288 diff --git a/src/mainboard/google/veyron_mickey/devicetree.cb b/src/mainboard/google/veyron_mickey/devicetree.cb index dfc09bfd42..a540bc47fb 100644 --- a/src/mainboard/google/veyron_mickey/devicetree.cb +++ b/src/mainboard/google/veyron_mickey/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/rockchip/rk3288 diff --git a/src/mainboard/google/veyron_rialto/devicetree.cb b/src/mainboard/google/veyron_rialto/devicetree.cb index a66d82daa2..fb6dfd9f81 100644 --- a/src/mainboard/google/veyron_rialto/devicetree.cb +++ b/src/mainboard/google/veyron_rialto/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/rockchip/rk3288 diff --git a/src/mainboard/hp/abm/devicetree.cb b/src/mainboard/hp/abm/devicetree.cb index 6cb4e87251..7f7ea270f3 100644 --- a/src/mainboard/hp/abm/devicetree.cb +++ b/src/mainboard/hp/abm/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index fa580ea92b..7bd312803e 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/sandybridge diff --git a/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb b/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb index a8c3034fd6..5496a8a3f9 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb +++ b/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb index 7512a10e01..263d595d0e 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/sandybridge diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index ad871e7051..669122fb5c 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/i945 diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb index 0ed46f1943..4a806431ab 100644 --- a/src/mainboard/intel/galileo/devicetree.cb +++ b/src/mainboard/intel/galileo/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/intel/quark diff --git a/src/mainboard/intel/harcuvar/devicetree.cb b/src/mainboard/intel/harcuvar/devicetree.cb index 7ba8598ea9..57e25bc35f 100644 --- a/src/mainboard/intel/harcuvar/devicetree.cb +++ b/src/mainboard/intel/harcuvar/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/intel/denverton_ns diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 78098aedbf..f4ccb1bd5a 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/intel/skylake diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb index 3e03e293e5..f2342510f8 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb +++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb index 5666f72d96..4b4df367b1 100644 --- a/src/mainboard/lenovo/g505s/devicetree.cb +++ b/src/mainboard/lenovo/g505s/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index ee1b6140dd..2de774d4b7 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/ironlake diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index db1fa9b4f7..7709a87949 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/i945 diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 74e752a2ca..d374cec1a0 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/ironlake diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index e92d74141d..9c06b365f4 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/i945 diff --git a/src/mainboard/lippert/frontrunner-af/devicetree.cb b/src/mainboard/lippert/frontrunner-af/devicetree.cb index 36545122ea..421b28621d 100644 --- a/src/mainboard/lippert/frontrunner-af/devicetree.cb +++ b/src/mainboard/lippert/frontrunner-af/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/lippert/toucan-af/devicetree.cb b/src/mainboard/lippert/toucan-af/devicetree.cb index 981f3dde92..54445ef894 100644 --- a/src/mainboard/lippert/toucan-af/devicetree.cb +++ b/src/mainboard/lippert/toucan-af/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/msi/ms7721/devicetree.cb b/src/mainboard/msi/ms7721/devicetree.cb index 763766ea33..6d2c1a486a 100644 --- a/src/mainboard/msi/ms7721/devicetree.cb +++ b/src/mainboard/msi/ms7721/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/opencellular/elgon/devicetree.cb b/src/mainboard/opencellular/elgon/devicetree.cb index 16b341affb..998e8f49ea 100644 --- a/src/mainboard/opencellular/elgon/devicetree.cb +++ b/src/mainboard/opencellular/elgon/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/cavium/cn81xx diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index bb6ffea099..50e648f28f 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/ironlake diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 4892669d7b..f8efc24242 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 7b2d5bdeec..b19b7af62e 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/i945 diff --git a/src/mainboard/scaleway/tagada/devicetree.cb b/src/mainboard/scaleway/tagada/devicetree.cb index 4b17a16692..e9932a3153 100644 --- a/src/mainboard/scaleway/tagada/devicetree.cb +++ b/src/mainboard/scaleway/tagada/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip soc/intel/denverton_ns diff --git a/src/mainboard/sifive/hifive-unleashed/devicetree.cb b/src/mainboard/sifive/hifive-unleashed/devicetree.cb index 015ae447ba..796c232c2d 100644 --- a/src/mainboard/sifive/hifive-unleashed/devicetree.cb +++ b/src/mainboard/sifive/hifive-unleashed/devicetree.cb @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only chip soc/sifive/fu540 diff --git a/src/mainboard/ti/beaglebone/devicetree.cb b/src/mainboard/ti/beaglebone/devicetree.cb index 7a97cf1109..dd999b4870 100644 --- a/src/mainboard/ti/beaglebone/devicetree.cb +++ b/src/mainboard/ti/beaglebone/devicetree.cb @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only chip cpu/ti/am335x From 2b79203bdbccb3e807fa59acc9f7b841ca747e69 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 13 May 2020 14:08:24 +0200 Subject: [PATCH 100/405] x86/include/arch/mmio.h: Convert to 96 characters line length Change-Id: I93d0ef6db417904c345fe7b76730bcb70ba25089 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41361 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/arch/x86/include/arch/mmio.h | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/src/arch/x86/include/arch/mmio.h b/src/arch/x86/include/arch/mmio.h index c6cfbeaa9c..c2aa0fb910 100644 --- a/src/arch/x86/include/arch/mmio.h +++ b/src/arch/x86/include/arch/mmio.h @@ -5,50 +5,42 @@ #include -static __always_inline uint8_t read8( - const volatile void *addr) +static __always_inline uint8_t read8(const volatile void *addr) { return *((volatile uint8_t *)(addr)); } -static __always_inline uint16_t read16( - const volatile void *addr) +static __always_inline uint16_t read16(const volatile void *addr) { return *((volatile uint16_t *)(addr)); } -static __always_inline uint32_t read32( - const volatile void *addr) +static __always_inline uint32_t read32(const volatile void *addr) { return *((volatile uint32_t *)(addr)); } -static __always_inline uint64_t read64( - const volatile void *addr) +static __always_inline uint64_t read64(const volatile void *addr) { return *((volatile uint64_t *)(addr)); } -static __always_inline void write8(volatile void *addr, - uint8_t value) +static __always_inline void write8(volatile void *addr, uint8_t value) { *((volatile uint8_t *)(addr)) = value; } -static __always_inline void write16(volatile void *addr, - uint16_t value) +static __always_inline void write16(volatile void *addr, uint16_t value) { *((volatile uint16_t *)(addr)) = value; } -static __always_inline void write32(volatile void *addr, - uint32_t value) +static __always_inline void write32(volatile void *addr, uint32_t value) { *((volatile uint32_t *)(addr)) = value; } -static __always_inline void write64(volatile void *addr, - uint64_t value) +static __always_inline void write64(volatile void *addr, uint64_t value) { *((volatile uint64_t *)(addr)) = value; } From d13bd05b7a94fc4744cba1a94280797f7c1ce3cd Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 22 Apr 2020 16:39:20 +0200 Subject: [PATCH 101/405] nb/intel: Const'ify pci_devfn_t devices Change-Id: Ib470523200929868280f57bb0cc82b038d2fedf6 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40610 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/e7505/memmap.c | 4 ++-- src/northbridge/intel/gm45/iommu.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index 92b2ae7740..b1ac3d1124 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -12,7 +12,7 @@ void *cbmem_top_chipset(void) { - pci_devfn_t mch = PCI_DEV(0, 0, 0); + const pci_devfn_t mch = PCI_DEV(0, 0, 0); uintptr_t tolm; /* This is at 128 MiB boundary. */ @@ -26,7 +26,7 @@ void northbridge_write_smram(u8 smram); void northbridge_write_smram(u8 smram) { - pci_devfn_t mch = PCI_DEV(0, 0, 0); + const pci_devfn_t mch = PCI_DEV(0, 0, 0); pci_write_config8(mch, SMRAMC, smram); } diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 422655409a..0d106b8e27 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -33,7 +33,7 @@ void init_iommu() /* clear GTT */ u16 gtt = pci_read_config16(PCI_DEV(0, 0, 0), D0F0_GGC); if (gtt & 0x400) { /* VT mode */ - pci_devfn_t igd = PCI_DEV(0, 2, 0); + const pci_devfn_t igd = PCI_DEV(0, 2, 0); /* setup somewhere */ u8 cmd = pci_read_config8(igd, PCI_COMMAND); @@ -52,7 +52,7 @@ void init_iommu() if (stepping == STEPPING_B3) { MCHBAR8(0xffc) |= 1 << 4; - pci_devfn_t peg = PCI_DEV(0, 1, 0); + const pci_devfn_t peg = PCI_DEV(0, 1, 0); /* FIXME: proper test? */ if (pci_read_config8(peg, PCI_CLASS_REVISION) != 0xff) { int val = pci_read_config32(peg, 0xfc) | (1 << 15); From 8e66124240cb18ecdbca669dee94c5bf04a38364 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 2 May 2020 19:02:53 +0200 Subject: [PATCH 102/405] nb/intel/sandybridge: Add and use BROADCAST_CH for IOSAV We have a single IOSAV sequence that is broadcast across all channels. Introduce the BROADCAST_CH macro, so that we can use the per-channel register definitions. Treating all IOSAV sequence writes the same eases the refactoring done in subsequent commits. Also, drop the broadcast register definitions for the IOSAV commands, as they are now obsolete. Line length limits are not for review. Breaking the lines unnecessarily complicates search and replace operations, and wil be taken care of in subsequent commits. Tested with BUILD_TIMELESS=1, ASUS P8Z77-V LX2 remains unchanged. Change-Id: I2dbb100fcad68d128e92b1bc9321fc1e53b748c9 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40976 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/mchbar_regs.h | 12 ++++++------ .../intel/sandybridge/raminit_common.c | 16 ++++++++-------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/northbridge/intel/sandybridge/mchbar_regs.h b/src/northbridge/intel/sandybridge/mchbar_regs.h index 74377b247b..286b55657f 100644 --- a/src/northbridge/intel/sandybridge/mchbar_regs.h +++ b/src/northbridge/intel/sandybridge/mchbar_regs.h @@ -209,6 +209,12 @@ #define CRCOMPOFST2 0x3714 /* CMD DRV, SComp and Static Leg controls */ +/* + * The register bank that would correspond to Channel 3 are actually "broadcast" registers. + * They can be used to write values to all channels. Use this macro instead of a literal '3'. + */ +#define BROADCAST_CH 3 + /* MC per-channel registers */ #define TC_DBP_ch(ch) Cx(0x4000, ch) /* Timings: BIN */ #define TC_RAP_ch(ch) Cx(0x4004, ch) /* Timings: Regular access */ @@ -315,12 +321,6 @@ #define IOSAV_By_BW_SERROR_C(y) Ly(0x4d40, y) /* IOSAV Bytelane Bit-wise error */ -#define IOSAV_n_SP_CMD_ADDR(n) Ly(0x4e00, n) /* Sub-sequence special command address */ -#define IOSAV_n_ADDR_UPDATE(n) Ly(0x4e10, n) /* Address update after command execution */ -#define IOSAV_n_SP_CMD_CTRL(n) Ly(0x4e20, n) /* Command signals in sub-sequence command */ -#define IOSAV_n_SUBSEQ_CTRL(n) Ly(0x4e30, n) /* Sub-sequence command parameter control */ -#define IOSAV_n_ADDRESS_LFSR(n) Ly(0x4e40, n) /* 23-bit LFSR value of the sequence */ - #define PM_THML_STAT 0x4e80 /* Thermal status of each rank */ #define IOSAV_SEQ_CTL 0x4e84 /* IOSAV sequence level control */ #define IOSAV_DATA_CTL 0x4e88 /* Data control in IOSAV mode */ diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 05cffd3fd8..ab3386bebb 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -808,16 +808,16 @@ void dram_mrscommands(ramctr_timing *ctrl) } /* DRAM command NOP (without ODT nor chip selects) */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL(0)) = IOSAV_NOP & NO_RANKSEL & ~(0xff << 8); - MCHBAR32(IOSAV_n_SUBSEQ_CTRL(0)) = 0xf1001; - MCHBAR32(IOSAV_n_SP_CMD_ADDR(0)) = 0x60002; - MCHBAR32(IOSAV_n_ADDR_UPDATE(0)) = 0; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(BROADCAST_CH, 0)) = IOSAV_NOP & NO_RANKSEL & ~(0xff << 8); + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(BROADCAST_CH, 0)) = 0xf1001; + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(BROADCAST_CH, 0)) = 0x60002; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(BROADCAST_CH, 0)) = 0; /* DRAM command ZQCL */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL(1)) = IOSAV_ZQCS; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL(1)) = 0x1901001; - MCHBAR32(IOSAV_n_SP_CMD_ADDR(1)) = 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPDATE(1)) = 0x288; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(BROADCAST_CH, 1)) = IOSAV_ZQCS; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(BROADCAST_CH, 1)) = 0x1901001; + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(BROADCAST_CH, 1)) = 0x60400; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(BROADCAST_CH, 1)) = 0x288; /* Execute command queue on all channels. Do it four times. */ MCHBAR32(IOSAV_SEQ_CTL) = (1 << 18) | 4; From ca00dec624b4763464f98127f2a262b1d0b8f272 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 2 May 2020 15:04:00 +0200 Subject: [PATCH 103/405] nb/intel/sandybridge: Program IOSAV with macros This is a temporary solution to simplify refactoring verification. Programming a subsequence involves writing a group of four registers. Abstract this into a "program subsequence" operation. This eliminates register write noise, which should improve the readability of the code. To replace the register writes with assignments to struct fields, we would need to have the values as parameters of a single macro. So, unroll SUBSEQ_CTRL and SP_CMD_ADDR into parameters of IOSAV_SUBSEQUENCE. Line length limits are not for review. Breaking the lines unnecessarily complicates search and replace operations, and wil be taken care of in subsequent commits. Tested with BUILD_TIMELESS=1, ASUS P8Z77-V LX2 remains unchanged. Change-Id: I23f7706ba8a87c1c26f9d40a50b6d47dcf95106a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40971 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- .../intel/sandybridge/mchbar_regs.h | 39 + .../intel/sandybridge/raminit_common.c | 717 +++++++++--------- 2 files changed, 408 insertions(+), 348 deletions(-) diff --git a/src/northbridge/intel/sandybridge/mchbar_regs.h b/src/northbridge/intel/sandybridge/mchbar_regs.h index 286b55657f..9867e807a6 100644 --- a/src/northbridge/intel/sandybridge/mchbar_regs.h +++ b/src/northbridge/intel/sandybridge/mchbar_regs.h @@ -158,6 +158,45 @@ * */ +/* Temporary IOSAV register macros to verifiably split bitfields */ +#define SUBSEQ_CTRL(reps, gap, post, dir) (((reps) << 0) | \ + ((gap) << 10) | \ + ((post) << 16) | \ + ((dir) << 26)) + +#define SSQ_NA 0 /* Non-data */ +#define SSQ_RD 1 /* Read */ +#define SSQ_WR 2 /* Write */ +#define SSQ_RW 3 /* Read and write */ + +#define SP_CMD_ADDR(addr, rowbits, bank, rank) (((addr) << 0) | \ + ((rowbits) << 16) | \ + ((bank) << 20) | \ + ((rank) << 24)) + +#define ADDR_UPDATE(addr_1, addr_8, bank, rank, wrap, lfsr, rate, xors) (((addr_1) << 0) | \ + ((addr_8) << 1) | \ + ((bank) << 2) | \ + ((rank) << 3) | \ + ((wrap) << 5) | \ + ((lfsr) << 10) | \ + ((rate) << 12) | \ + ((xors) << 16)) + +/* Marker macro for IOSAV_n_ADDR_UPDATE */ +#define ADDR_UPDATE_NONE 0 + +/* Only programming the wraparound without any triggers is suspicious */ +#define ADDR_UPDATE_WRAP(wrap) ((wrap) << 5) + +#define IOSAV_SUBSEQUENCE(ch, n, sp_cmd_ctrl, reps, gap, post, dir, addr, rowbits, bank, rank, addr_update) \ + do { \ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(ch, n)) = sp_cmd_ctrl; \ + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(ch, n)) = SUBSEQ_CTRL(reps, gap, post, dir); \ + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(ch, n)) = SP_CMD_ADDR(addr, rowbits, bank, rank); \ + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(ch, n)) = addr_update; \ + } while (0) + /* Indexed register helper macros */ #define Gz(r, z) ((r) + ((z) << 8)) #define Ly(r, y) ((r) + ((y) << 2)) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index ab3386bebb..6c31ad362f 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -572,10 +572,11 @@ static void write_reset(ramctr_timing *ctrl) slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; /* DRAM command ZQCS */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ZQCS & NO_RANKSEL; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x80c01; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_ZQCS & NO_RANKSEL, + 1, 3, 8, SSQ_NA, + 0, 6, 0, slotrank, + ADDR_UPDATE_NONE); /* * Execute command queue - why is bit 22 set here?! @@ -664,25 +665,25 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, } /* DRAM command MRS */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_MRS & NO_RANKSEL; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x41001; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = - val | 0x60000 | (reg << 20) | (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_MRS & NO_RANKSEL, + 1, 4, 4, SSQ_NA, + val, 6, reg, slotrank, + ADDR_UPDATE_NONE); /* DRAM command MRS */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_MRS; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x41001; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = - val | 0x60000 | (reg << 20) | (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; + IOSAV_SUBSEQUENCE(channel, 1, + IOSAV_MRS, + 1, 4, 4, SSQ_NA, + val, 6, reg, slotrank, + ADDR_UPDATE_NONE); /* DRAM command MRS */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_MRS & NO_RANKSEL; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = - val | 0x60000 | (reg << 20) | (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; + IOSAV_SUBSEQUENCE(channel, 2, + IOSAV_MRS & NO_RANKSEL, + 1, 4, ctrl->tMOD, SSQ_NA, + val, 6, reg, slotrank, + ADDR_UPDATE_NONE); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(3); @@ -808,16 +809,18 @@ void dram_mrscommands(ramctr_timing *ctrl) } /* DRAM command NOP (without ODT nor chip selects) */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(BROADCAST_CH, 0)) = IOSAV_NOP & NO_RANKSEL & ~(0xff << 8); - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(BROADCAST_CH, 0)) = 0xf1001; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(BROADCAST_CH, 0)) = 0x60002; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(BROADCAST_CH, 0)) = 0; + IOSAV_SUBSEQUENCE(BROADCAST_CH, 0, + IOSAV_NOP & NO_RANKSEL & ~(0xff << 8), + 1, 4, 15, SSQ_NA, + 2, 6, 0, 0, + ADDR_UPDATE_NONE); /* DRAM command ZQCL */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(BROADCAST_CH, 1)) = IOSAV_ZQCS; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(BROADCAST_CH, 1)) = 0x1901001; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(BROADCAST_CH, 1)) = 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(BROADCAST_CH, 1)) = 0x288; + IOSAV_SUBSEQUENCE(BROADCAST_CH, 1, + IOSAV_ZQCS, + 1, 4, 400, SSQ_NA, + 1024, 6, 0, 0, + ADDR_UPDATE(0, 0, 0, 1, 20, 0, 0, 0)); /* Execute command queue on all channels. Do it four times. */ MCHBAR32(IOSAV_SEQ_CTL) = (1 << 18) | 4; @@ -841,10 +844,11 @@ void dram_mrscommands(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command ZQCS */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ZQCS & NO_RANKSEL; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x659001; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_ZQCS & NO_RANKSEL, + 1, 36, 101, SSQ_NA, + 0, 6, 0, slotrank, + ADDR_UPDATE_WRAP(31)); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); @@ -1008,29 +1012,33 @@ static void test_timA(ramctr_timing *ctrl, int channel, int slotrank) write MR3 MPR enable in this mode only RD and RDA are allowed all reads return a predefined pattern */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_MRS; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = (0xc01 | (ctrl->tMOD << 16)); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x360004; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_MRS, + 1, 3, ctrl->tMOD, SSQ_NA, + 4, 6, 3, slotrank, + ADDR_UPDATE_NONE); /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_RD; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4040c01; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; + IOSAV_SUBSEQUENCE(channel, 1, + IOSAV_RD, + 1, 3, 4, SSQ_RD, + 0, 0, 0, slotrank, + ADDR_UPDATE_NONE); /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x100f | ((ctrl->CAS + 36) << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; + IOSAV_SUBSEQUENCE(channel, 2, + IOSAV_RD, + 15, 4, ctrl->CAS + 36, SSQ_NA, + 0, 6, 0, slotrank, + ADDR_UPDATE_NONE); /* DRAM command MRS write MR3 MPR disable */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_MRS; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x360000; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; + IOSAV_SUBSEQUENCE(channel, 3, + IOSAV_MRS, + 1, 3, ctrl->tMOD, SSQ_NA, + 0, 6, 3, slotrank, + ADDR_UPDATE_NONE); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -1292,10 +1300,11 @@ int read_training(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command PREA */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_PRE; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tRP << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_PRE, + 1, 3, ctrl->tRP, SSQ_NA, + 1024, 6, 0, slotrank, + ADDR_UPDATE_NONE); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); @@ -1392,30 +1401,32 @@ static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ACT; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = - (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | 4 | (ctrl->tRCD << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | (6 << 16); - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x244; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_ACT, + 4, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), ctrl->tRCD, SSQ_NA, + 0, 6, 0, slotrank, + ADDR_UPDATE(0, 0, 1, 0, 18, 0, 0, 0)); /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_NOP; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x8041001; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 8; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x3e0; + IOSAV_SUBSEQUENCE(channel, 1, + IOSAV_NOP, + 1, 4, 4, SSQ_WR, + 8, 0, 0, slotrank, + ADDR_UPDATE_WRAP(31)); /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_WR; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x80411f4; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x242; + IOSAV_SUBSEQUENCE(channel, 2, + IOSAV_WR, + 500, 4, 4, SSQ_WR, + 0, 0, 0, slotrank, + ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_NOP; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = - 0x08000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 8; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0x3e0; + IOSAV_SUBSEQUENCE(channel, 3, + IOSAV_NOP, + 1, 3, ctrl->CWL + ctrl->tWTR + 5, SSQ_WR, + 8, 0, 0, slotrank, + ADDR_UPDATE_WRAP(31)); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -1423,30 +1434,32 @@ static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command PREA */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_PRE; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tRP << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x240; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_PRE, + 1, 3, ctrl->tRP, SSQ_NA, + 1024, 6, 0, slotrank, + ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_ACT; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = - (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) | 8 | (ctrl->CAS << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x244; + IOSAV_SUBSEQUENCE(channel, 1, + IOSAV_ACT, + 8, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), ctrl->CAS, SSQ_NA, + 0, 6, 0, slotrank, + ADDR_UPDATE(0, 0, 1, 0, 18, 0, 0, 0)); /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = - 0x40011f4 | (MAX(ctrl->tRTP, 8) << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x242; + IOSAV_SUBSEQUENCE(channel, 2, + IOSAV_RD, + 500, 4, MAX(ctrl->tRTP, 8), SSQ_RD, + 0, 0, 0, slotrank, + ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); /* DRAM command PREA */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_PRE; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tRP << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0x240; + IOSAV_SUBSEQUENCE(channel, 3, + IOSAV_PRE, + 1, 3, ctrl->tRP, SSQ_NA, + 1024, 6, 0, slotrank, + ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -1482,10 +1495,11 @@ static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command PREA */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_PRE; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tRP << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x240; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_PRE, + 1, 3, ctrl->tRP, SSQ_NA, + 1024, 6, 0, slotrank, + ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); @@ -1588,35 +1602,33 @@ static void precharge(ramctr_timing *ctrl) write MR3 MPR enable in this mode only RD and RDA are allowed all reads return a predefined pattern */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_MRS; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = - 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = - (slotrank << 24) | 0x360004; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_MRS, + 1, 3, ctrl->tMOD, SSQ_NA, + 4, 6, 3, slotrank, + ADDR_UPDATE_NONE); /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_RD; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4041003; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; + IOSAV_SUBSEQUENCE(channel, 1, + IOSAV_RD, + 3, 4, 4, SSQ_RD, + 0, 0, 0, slotrank, + ADDR_UPDATE_NONE); /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = - 0x1001 | ((ctrl->CAS + 8) << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = - (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; + IOSAV_SUBSEQUENCE(channel, 2, + IOSAV_RD, + 1, 4, ctrl->CAS + 8, SSQ_NA, + 0, 6, 0, slotrank, + ADDR_UPDATE_NONE); /* DRAM command MRS * write MR3 MPR disable */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_MRS; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = - 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = - (slotrank << 24) | 0x360000; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; + IOSAV_SUBSEQUENCE(channel, 3, + IOSAV_MRS, + 1, 3, ctrl->tMOD, SSQ_NA, + 0, 6, 3, slotrank, + ADDR_UPDATE_NONE); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -1637,35 +1649,33 @@ static void precharge(ramctr_timing *ctrl) * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_MRS; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = - 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = - (slotrank << 24) | 0x360004; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_MRS, + 1, 3, ctrl->tMOD, SSQ_NA, + 4, 6, 3, slotrank, + ADDR_UPDATE_NONE); /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_RD; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4041003; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; + IOSAV_SUBSEQUENCE(channel, 1, + IOSAV_RD, + 3, 4, 4, SSQ_RD, + 0, 0, 0, slotrank, + ADDR_UPDATE_NONE); /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = - 0x1001 | ((ctrl->CAS + 8) << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = - (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; + IOSAV_SUBSEQUENCE(channel, 2, + IOSAV_RD, + 1, 4, ctrl->CAS + 8, SSQ_NA, + 0, 6, 0, slotrank, + ADDR_UPDATE_NONE); /* DRAM command MRS * write MR3 MPR disable */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_MRS; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = - 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = - (slotrank << 24) | 0x360000; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; + IOSAV_SUBSEQUENCE(channel, 3, + IOSAV_MRS, + 1, 3, ctrl->tMOD, SSQ_NA, + 0, 6, 3, slotrank, + ADDR_UPDATE_NONE); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -1682,17 +1692,18 @@ static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_NOP; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = - 0x8000c01 | ((ctrl->CWL + ctrl->tWLO) << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = 8 | (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_NOP, + 1, 3, ctrl->CWL + ctrl->tWLO, SSQ_WR, + 8, 0, 0, slotrank, + ADDR_UPDATE_NONE); /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_NOP_ALT; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4000c01 | ((ctrl->CAS + 38) << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 4; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; + IOSAV_SUBSEQUENCE(channel, 1, + IOSAV_NOP_ALT, + 1, 3, ctrl->CAS + 38, SSQ_RD, + 4, 0, 0, slotrank, + ADDR_UPDATE_NONE); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(2); @@ -1791,29 +1802,32 @@ static void adjust_high_timB(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ACT; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tRCD << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_ACT, + 1, 3, ctrl->tRCD, SSQ_NA, + 0, 6, 0, slotrank, + ADDR_UPDATE_NONE); /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_NOP; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x8040c01; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 0x8; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x3e0; + IOSAV_SUBSEQUENCE(channel, 1, + IOSAV_NOP, + 1, 3, 4, SSQ_WR, + 8, 0, 0, slotrank, + ADDR_UPDATE_WRAP(31)); /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_WR; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x8041003; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x3e2; + IOSAV_SUBSEQUENCE(channel, 2, + IOSAV_WR, + 3, 4, 4, SSQ_WR, + 0, 0, 0, slotrank, + ADDR_UPDATE(0, 1, 0, 0, 31, 0, 0, 0)); /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_NOP; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = - 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x8; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0x3e0; + IOSAV_SUBSEQUENCE(channel, 3, + IOSAV_NOP, + 1, 3, ctrl->CWL + ctrl->tWTR + 5, SSQ_WR, + 8, 0, 0, slotrank, + ADDR_UPDATE_WRAP(31)); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -1821,24 +1835,27 @@ static void adjust_high_timB(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command PREA */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_PRE; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | ((ctrl->tRP) << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x240; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_PRE, + 1, 3, ctrl->tRP, SSQ_NA, + 1024, 6, 0, slotrank, + ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_ACT; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0xc01 | ((ctrl->tRCD) << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; + IOSAV_SUBSEQUENCE(channel, 1, + IOSAV_ACT, + 1, 3, ctrl->tRCD, SSQ_NA, + 0, 6, 0, slotrank, + ADDR_UPDATE_NONE); /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD | (3 << 16); - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x4000c01 | ((ctrl->tRP + - ctrl->timings[channel][slotrank].roundtrip_latency + - ctrl->timings[channel][slotrank].io_latency) << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60008; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; + IOSAV_SUBSEQUENCE(channel, 2, + IOSAV_RD | (3 << 16), + 1, 3, ctrl->tRP + + ctrl->timings[channel][slotrank].roundtrip_latency + + ctrl->timings[channel][slotrank].io_latency, SSQ_RD, + 8, 6, 0, slotrank, + ADDR_UPDATE_NONE); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(3); @@ -1870,10 +1887,11 @@ static void write_op(ramctr_timing *ctrl, int channel) slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ZQCS */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ZQCS & NO_RANKSEL; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x41001; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_ZQCS & NO_RANKSEL, + 1, 4, 4, SSQ_NA, + 0, 6, 0, slotrank, + ADDR_UPDATE_WRAP(31)); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); @@ -1948,10 +1966,11 @@ int write_training(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command ZQCS */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ZQCS & NO_RANKSEL; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x659001; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_ZQCS & NO_RANKSEL, + 1, 36, 101, SSQ_NA, + 0, 6, 0, 0, + ADDR_UPDATE_WRAP(31)); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); @@ -2017,35 +2036,36 @@ static int test_320c(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ACT; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = - ((MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) - | 8 | (ctrl->tRCD << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = - (slotrank << 24) | ctr | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x244; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_ACT, + 8, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), ctrl->tRCD, SSQ_NA, + ctr, 6, 0, slotrank, + ADDR_UPDATE(0, 0, 1, 0, 18, 0, 0, 0)); /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_WR; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = - 0x8001020 | ((ctrl->CWL + ctrl->tWTR + 8) << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x20e42; + IOSAV_SUBSEQUENCE(channel, 1, + IOSAV_WR, + 32, 4, ctrl->CWL + ctrl->tWTR + 8, SSQ_WR, + 0, 0, 0, slotrank, + ADDR_UPDATE(0, 1, 0, 0, 18, 3, 0, 2)); + MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1)) = 0x389abcd; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = - 0x4001020 | (MAX(ctrl->tRTP, 8) << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x20e42; + IOSAV_SUBSEQUENCE(channel, 2, + IOSAV_RD, + 32, 4, MAX(ctrl->tRTP, 8), SSQ_RD, + 0, 0, 0, slotrank, + ADDR_UPDATE(0, 1, 0, 0, 18, 3, 0, 2)); + MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 2)) = 0x389abcd; /* DRAM command PRE */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_PRE; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xf1001; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0x240; + IOSAV_SUBSEQUENCE(channel, 3, + IOSAV_PRE, + 1, 4, 15, SSQ_NA, + 1024, 6, 0, slotrank, + ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -2108,10 +2128,11 @@ static void reprogram_320c(ramctr_timing *ctrl) slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ZQCS */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ZQCS & NO_RANKSEL; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x41001; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_ZQCS & NO_RANKSEL, + 1, 4, 4, SSQ_NA, + 0, 6, 0, slotrank, + ADDR_UPDATE_WRAP(31)); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); @@ -2129,10 +2150,11 @@ static void reprogram_320c(ramctr_timing *ctrl) slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ZQCS */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ZQCS & NO_RANKSEL; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x41001; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_ZQCS & NO_RANKSEL, + 1, 4, 4, SSQ_NA, + 0, 6, 0, slotrank, + ADDR_UPDATE_WRAP(31)); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); @@ -2293,29 +2315,33 @@ static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, i write MR3 MPR enable in this mode only RD and RDA are allowed all reads return a predefined pattern */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_MRS; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x360004; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_MRS, + 1, 3, ctrl->tMOD, SSQ_NA, + 4, 6, 3, slotrank, + ADDR_UPDATE_NONE); /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_RD; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x40411f4; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; + IOSAV_SUBSEQUENCE(channel, 1, + IOSAV_RD, + 500, 4, 4, SSQ_RD, + 0, 0, 0, slotrank, + ADDR_UPDATE_NONE); /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; + IOSAV_SUBSEQUENCE(channel, 2, + IOSAV_RD, + 1, 4, ctrl->CAS + 8, SSQ_NA, + 0, 6, 0, slotrank, + ADDR_UPDATE_NONE); /* DRAM command MRS MR3 disable MPR */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_MRS; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x360000; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; + IOSAV_SUBSEQUENCE(channel, 3, + IOSAV_MRS, + 1, 3, ctrl->tMOD, SSQ_NA, + 0, 6, 3, slotrank, + ADDR_UPDATE_NONE); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -2378,35 +2404,33 @@ int discover_edges(ramctr_timing *ctrl) write MR3 MPR enable in this mode only RD and RDA are allowed all reads return a predefined pattern */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_MRS; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = - 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = - (slotrank << 24) | 0x360004; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_MRS, + 1, 3, ctrl->tMOD, SSQ_NA, + 4, 6, 3, slotrank, + ADDR_UPDATE_NONE); /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_RD; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4041003; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; + IOSAV_SUBSEQUENCE(channel, 1, + IOSAV_RD, + 3, 4, 4, SSQ_RD, + 0, 0, 0, slotrank, + ADDR_UPDATE_NONE); /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = - 0x1001 | ((ctrl->CAS + 8) << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = - (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; + IOSAV_SUBSEQUENCE(channel, 2, + IOSAV_RD, + 1, 4, ctrl->CAS + 8, SSQ_NA, + 0, 6, 0, slotrank, + ADDR_UPDATE_NONE); /* DRAM command MRS * MR3 disable MPR */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_MRS; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = - 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = - (slotrank << 24) | 0x360000; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; + IOSAV_SUBSEQUENCE(channel, 3, + IOSAV_MRS, + 1, 3, ctrl->tMOD, SSQ_NA, + 0, 6, 3, slotrank, + ADDR_UPDATE_NONE); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -2431,36 +2455,33 @@ int discover_edges(ramctr_timing *ctrl) write MR3 MPR enable in this mode only RD and RDA are allowed all reads return a predefined pattern */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_MRS; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = - 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = - (slotrank << 24) | 0x360004; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_MRS, + 1, 3, ctrl->tMOD, SSQ_NA, + 4, 6, 3, slotrank, + ADDR_UPDATE_NONE); /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_RD; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4041003; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = - (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; + IOSAV_SUBSEQUENCE(channel, 1, + IOSAV_RD, + 3, 4, 4, SSQ_RD, + 0, 0, 0, slotrank, + ADDR_UPDATE_NONE); /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = - 0x1001 | ((ctrl->CAS + 8) << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = - (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; + IOSAV_SUBSEQUENCE(channel, 2, + IOSAV_RD, + 1, 4, ctrl->CAS + 8, SSQ_NA, + 0, 6, 0, slotrank, + ADDR_UPDATE_NONE); /* DRAM command MRS * MR3 disable MPR */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_MRS; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = - 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = - (slotrank << 24) | 0x360000; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; + IOSAV_SUBSEQUENCE(channel, 3, + IOSAV_MRS, + 1, 3, ctrl->tMOD, SSQ_NA, + 0, 6, 3, slotrank, + ADDR_UPDATE_NONE); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -2563,37 +2584,32 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotr wait_for_iosav(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ACT; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = - 0x4 | (ctrl->tRCD << 16) | - (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = - (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x240; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_ACT, + 4, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), ctrl->tRCD, SSQ_NA, + 0, 6, 0, slotrank, + ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_WR; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x8005020 | - ((ctrl->tWTR + ctrl->CWL + 8) << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = - slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x242; + IOSAV_SUBSEQUENCE(channel, 1, + IOSAV_WR, + 32, 20, ctrl->tWTR + ctrl->CWL + 8, SSQ_WR, + 0, 0, 0, slotrank, + ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = - 0x4005020 | (MAX(ctrl->tRTP, 8) << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = - slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x242; + IOSAV_SUBSEQUENCE(channel, 2, + IOSAV_RD, + 32, 20, MAX(ctrl->tRTP, 8), SSQ_RD, + 0, 0, 0, slotrank, + ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); /* DRAM command PRE */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_PRE; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = - 0xc01 | (ctrl->tRP << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = - (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; + IOSAV_SUBSEQUENCE(channel, 3, + IOSAV_PRE, + 1, 3, ctrl->tRP, SSQ_NA, + 1024, 6, 0, slotrank, + ADDR_UPDATE_NONE); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -2692,30 +2708,32 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ACT; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = - (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | (ctrl->tRCD << 16) | 4; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x0244; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_ACT, + 4, MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD), ctrl->tRCD, SSQ_NA, + 0, 6, 0, slotrank, + ADDR_UPDATE(0, 0, 1, 0, 18, 0, 0, 0)); /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_WR; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = - 0x80011e0 | ((ctrl->tWTR + ctrl->CWL + 8) << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x242; + IOSAV_SUBSEQUENCE(channel, 1, + IOSAV_WR, + 480, 4, ctrl->tWTR + ctrl->CWL + 8, SSQ_WR, + 0, 0, 0, slotrank, + ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x40011e0 | (MAX(ctrl->tRTP, 8) << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x242; + IOSAV_SUBSEQUENCE(channel, 2, + IOSAV_RD, + 480, 4, MAX(ctrl->tRTP, 8), SSQ_RD, + 0, 0, 0, slotrank, + ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); /* DRAM command PRE */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_PRE; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0x1001 | (ctrl->tRP << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; + IOSAV_SUBSEQUENCE(channel, 3, + IOSAV_PRE, + 1, 4, ctrl->tRP, SSQ_NA, + 1024, 6, 0, slotrank, + ADDR_UPDATE_NONE); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -2907,28 +2925,32 @@ int channel_test(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ACT; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x0028a004; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = 0x00060000 | (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x00000244; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_ACT, + 4, 40, 40, SSQ_NA, + 0, 6, 0, slotrank, + ADDR_UPDATE(0, 0, 1, 0, 18, 0, 0, 0)); /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_WR; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x08281064; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x00000242; + IOSAV_SUBSEQUENCE(channel, 1, + IOSAV_WR, + 100, 4, 40, SSQ_WR, + 0, 0, 0, slotrank, + ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_RD; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x04281064; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x00000242; + IOSAV_SUBSEQUENCE(channel, 2, + IOSAV_RD, + 100, 4, 40, SSQ_RD, + 0, 0, 0, slotrank, + ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); /* DRAM command PRE */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = IOSAV_PRE; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0x00280c01; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = 0x00060400 | (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0x00000240; + IOSAV_SUBSEQUENCE(channel, 3, + IOSAV_PRE, + 1, 3, 40, SSQ_NA, + 1024, 6, 0, slotrank, + ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -2955,26 +2977,25 @@ void channel_scrub(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ACT; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = - (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) - | 1 | (ctrl->tRCD << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = - row | 0x00060000 | (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x00000241; + IOSAV_SUBSEQUENCE(channel, 0, + IOSAV_ACT, + 1, MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD), ctrl->tRCD, SSQ_NA, + row, 6, 0, slotrank, + ADDR_UPDATE(1, 0, 0, 0, 18, 0, 0, 0)); /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_WR; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x08281081; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = row | (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x00000242; + IOSAV_SUBSEQUENCE(channel, 1, + IOSAV_WR, + 129, 4, 40, SSQ_WR, + row, 0, 0, slotrank, + ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); /* DRAM command PRE */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_PRE; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x00280c01; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = - 0x00060400 | (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x00000240; + IOSAV_SUBSEQUENCE(channel, 2, + IOSAV_PRE, + 1, 3, 40, SSQ_NA, + 1024, 6, 0, slotrank, + ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); /* execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(3); From 6aa7cca8158227019c845752b0481e0c66b4eb29 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 2 May 2020 19:38:34 +0200 Subject: [PATCH 104/405] nb/intel/sandybridge: Use or-based logic for RANKSEL NO_RANKSEL was introduced because it appeared less often and it did not cause any lines to become too long. To simplify macro transmutation, add the RANKSEL opposite and keep NO_RANKSEL as a no-op to ease replacement. Line length limits are not for review. Breaking the lines unnecessarily complicates search and replace operations, and wil be taken care of in subsequent commits. Tested with BUILD_TIMELESS=1, ASUS P8Z77-V LX2 remains unchanged. Change-Id: I5d7aad59fc79840da7de2e9421b84834a6024eb9 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40977 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- .../intel/sandybridge/raminit_common.c | 126 +++++++++--------- .../intel/sandybridge/raminit_common.h | 19 +-- 2 files changed, 73 insertions(+), 72 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 6c31ad362f..dac34a4a34 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -673,7 +673,7 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, /* DRAM command MRS */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_MRS, + IOSAV_MRS | RANKSEL, 1, 4, 4, SSQ_NA, val, 6, reg, slotrank, ADDR_UPDATE_NONE); @@ -817,7 +817,7 @@ void dram_mrscommands(ramctr_timing *ctrl) /* DRAM command ZQCL */ IOSAV_SUBSEQUENCE(BROADCAST_CH, 1, - IOSAV_ZQCS, + IOSAV_ZQCS | RANKSEL, 1, 4, 400, SSQ_NA, 1024, 6, 0, 0, ADDR_UPDATE(0, 0, 0, 1, 20, 0, 0, 0)); @@ -1013,21 +1013,21 @@ static void test_timA(ramctr_timing *ctrl, int channel, int slotrank) in this mode only RD and RDA are allowed all reads return a predefined pattern */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_MRS, + IOSAV_MRS | RANKSEL, 1, 3, ctrl->tMOD, SSQ_NA, 4, 6, 3, slotrank, ADDR_UPDATE_NONE); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_RD, + IOSAV_RD | RANKSEL, 1, 3, 4, SSQ_RD, 0, 0, 0, slotrank, ADDR_UPDATE_NONE); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD, + IOSAV_RD | RANKSEL, 15, 4, ctrl->CAS + 36, SSQ_NA, 0, 6, 0, slotrank, ADDR_UPDATE_NONE); @@ -1035,7 +1035,7 @@ static void test_timA(ramctr_timing *ctrl, int channel, int slotrank) /* DRAM command MRS write MR3 MPR disable */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_MRS, + IOSAV_MRS | RANKSEL, 1, 3, ctrl->tMOD, SSQ_NA, 0, 6, 3, slotrank, ADDR_UPDATE_NONE); @@ -1301,7 +1301,7 @@ int read_training(ramctr_timing *ctrl) /* DRAM command PREA */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_PRE, + IOSAV_PRE | RANKSEL, 1, 3, ctrl->tRP, SSQ_NA, 1024, 6, 0, slotrank, ADDR_UPDATE_NONE); @@ -1402,28 +1402,28 @@ static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) /* DRAM command ACT */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ACT, + IOSAV_ACT | RANKSEL, 4, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), ctrl->tRCD, SSQ_NA, 0, 6, 0, slotrank, ADDR_UPDATE(0, 0, 1, 0, 18, 0, 0, 0)); /* DRAM command NOP */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_NOP, + IOSAV_NOP | RANKSEL, 1, 4, 4, SSQ_WR, 8, 0, 0, slotrank, ADDR_UPDATE_WRAP(31)); /* DRAM command WR */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_WR, + IOSAV_WR | RANKSEL, 500, 4, 4, SSQ_WR, 0, 0, 0, slotrank, ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); /* DRAM command NOP */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_NOP, + IOSAV_NOP | RANKSEL, 1, 3, ctrl->CWL + ctrl->tWTR + 5, SSQ_WR, 8, 0, 0, slotrank, ADDR_UPDATE_WRAP(31)); @@ -1435,28 +1435,28 @@ static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) /* DRAM command PREA */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_PRE, + IOSAV_PRE | RANKSEL, 1, 3, ctrl->tRP, SSQ_NA, 1024, 6, 0, slotrank, ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); /* DRAM command ACT */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_ACT, + IOSAV_ACT | RANKSEL, 8, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), ctrl->CAS, SSQ_NA, 0, 6, 0, slotrank, ADDR_UPDATE(0, 0, 1, 0, 18, 0, 0, 0)); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD, + IOSAV_RD | RANKSEL, 500, 4, MAX(ctrl->tRTP, 8), SSQ_RD, 0, 0, 0, slotrank, ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); /* DRAM command PREA */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_PRE, + IOSAV_PRE | RANKSEL, 1, 3, ctrl->tRP, SSQ_NA, 1024, 6, 0, slotrank, ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); @@ -1496,7 +1496,7 @@ static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) /* DRAM command PREA */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_PRE, + IOSAV_PRE | RANKSEL, 1, 3, ctrl->tRP, SSQ_NA, 1024, 6, 0, slotrank, ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); @@ -1603,21 +1603,21 @@ static void precharge(ramctr_timing *ctrl) in this mode only RD and RDA are allowed all reads return a predefined pattern */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_MRS, + IOSAV_MRS | RANKSEL, 1, 3, ctrl->tMOD, SSQ_NA, 4, 6, 3, slotrank, ADDR_UPDATE_NONE); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_RD, + IOSAV_RD | RANKSEL, 3, 4, 4, SSQ_RD, 0, 0, 0, slotrank, ADDR_UPDATE_NONE); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD, + IOSAV_RD | RANKSEL, 1, 4, ctrl->CAS + 8, SSQ_NA, 0, 6, 0, slotrank, ADDR_UPDATE_NONE); @@ -1625,7 +1625,7 @@ static void precharge(ramctr_timing *ctrl) /* DRAM command MRS * write MR3 MPR disable */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_MRS, + IOSAV_MRS | RANKSEL, 1, 3, ctrl->tMOD, SSQ_NA, 0, 6, 3, slotrank, ADDR_UPDATE_NONE); @@ -1650,21 +1650,21 @@ static void precharge(ramctr_timing *ctrl) * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_MRS, + IOSAV_MRS | RANKSEL, 1, 3, ctrl->tMOD, SSQ_NA, 4, 6, 3, slotrank, ADDR_UPDATE_NONE); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_RD, + IOSAV_RD | RANKSEL, 3, 4, 4, SSQ_RD, 0, 0, 0, slotrank, ADDR_UPDATE_NONE); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD, + IOSAV_RD | RANKSEL, 1, 4, ctrl->CAS + 8, SSQ_NA, 0, 6, 0, slotrank, ADDR_UPDATE_NONE); @@ -1672,7 +1672,7 @@ static void precharge(ramctr_timing *ctrl) /* DRAM command MRS * write MR3 MPR disable */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_MRS, + IOSAV_MRS | RANKSEL, 1, 3, ctrl->tMOD, SSQ_NA, 0, 6, 3, slotrank, ADDR_UPDATE_NONE); @@ -1693,14 +1693,14 @@ static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command NOP */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_NOP, + IOSAV_NOP | RANKSEL, 1, 3, ctrl->CWL + ctrl->tWLO, SSQ_WR, 8, 0, 0, slotrank, ADDR_UPDATE_NONE); /* DRAM command NOP */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_NOP_ALT, + IOSAV_NOP_ALT | RANKSEL, 1, 3, ctrl->CAS + 38, SSQ_RD, 4, 0, 0, slotrank, ADDR_UPDATE_NONE); @@ -1803,28 +1803,28 @@ static void adjust_high_timB(ramctr_timing *ctrl) /* DRAM command ACT */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ACT, + IOSAV_ACT | RANKSEL, 1, 3, ctrl->tRCD, SSQ_NA, 0, 6, 0, slotrank, ADDR_UPDATE_NONE); /* DRAM command NOP */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_NOP, + IOSAV_NOP | RANKSEL, 1, 3, 4, SSQ_WR, 8, 0, 0, slotrank, ADDR_UPDATE_WRAP(31)); /* DRAM command WR */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_WR, + IOSAV_WR | RANKSEL, 3, 4, 4, SSQ_WR, 0, 0, 0, slotrank, ADDR_UPDATE(0, 1, 0, 0, 31, 0, 0, 0)); /* DRAM command NOP */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_NOP, + IOSAV_NOP | RANKSEL, 1, 3, ctrl->CWL + ctrl->tWTR + 5, SSQ_WR, 8, 0, 0, slotrank, ADDR_UPDATE_WRAP(31)); @@ -1836,14 +1836,14 @@ static void adjust_high_timB(ramctr_timing *ctrl) /* DRAM command PREA */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_PRE, + IOSAV_PRE | RANKSEL, 1, 3, ctrl->tRP, SSQ_NA, 1024, 6, 0, slotrank, ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); /* DRAM command ACT */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_ACT, + IOSAV_ACT | RANKSEL, 1, 3, ctrl->tRCD, SSQ_NA, 0, 6, 0, slotrank, ADDR_UPDATE_NONE); @@ -2037,14 +2037,14 @@ static int test_320c(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command ACT */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ACT, + IOSAV_ACT | RANKSEL, 8, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), ctrl->tRCD, SSQ_NA, ctr, 6, 0, slotrank, ADDR_UPDATE(0, 0, 1, 0, 18, 0, 0, 0)); /* DRAM command WR */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_WR, + IOSAV_WR | RANKSEL, 32, 4, ctrl->CWL + ctrl->tWTR + 8, SSQ_WR, 0, 0, 0, slotrank, ADDR_UPDATE(0, 1, 0, 0, 18, 3, 0, 2)); @@ -2053,7 +2053,7 @@ static int test_320c(ramctr_timing *ctrl, int channel, int slotrank) /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD, + IOSAV_RD | RANKSEL, 32, 4, MAX(ctrl->tRTP, 8), SSQ_RD, 0, 0, 0, slotrank, ADDR_UPDATE(0, 1, 0, 0, 18, 3, 0, 2)); @@ -2062,7 +2062,7 @@ static int test_320c(ramctr_timing *ctrl, int channel, int slotrank) /* DRAM command PRE */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_PRE, + IOSAV_PRE | RANKSEL, 1, 4, 15, SSQ_NA, 1024, 6, 0, slotrank, ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); @@ -2316,21 +2316,21 @@ static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, i in this mode only RD and RDA are allowed all reads return a predefined pattern */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_MRS, + IOSAV_MRS | RANKSEL, 1, 3, ctrl->tMOD, SSQ_NA, 4, 6, 3, slotrank, ADDR_UPDATE_NONE); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_RD, + IOSAV_RD | RANKSEL, 500, 4, 4, SSQ_RD, 0, 0, 0, slotrank, ADDR_UPDATE_NONE); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD, + IOSAV_RD | RANKSEL, 1, 4, ctrl->CAS + 8, SSQ_NA, 0, 6, 0, slotrank, ADDR_UPDATE_NONE); @@ -2338,7 +2338,7 @@ static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, i /* DRAM command MRS MR3 disable MPR */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_MRS, + IOSAV_MRS | RANKSEL, 1, 3, ctrl->tMOD, SSQ_NA, 0, 6, 3, slotrank, ADDR_UPDATE_NONE); @@ -2405,21 +2405,21 @@ int discover_edges(ramctr_timing *ctrl) in this mode only RD and RDA are allowed all reads return a predefined pattern */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_MRS, + IOSAV_MRS | RANKSEL, 1, 3, ctrl->tMOD, SSQ_NA, 4, 6, 3, slotrank, ADDR_UPDATE_NONE); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_RD, + IOSAV_RD | RANKSEL, 3, 4, 4, SSQ_RD, 0, 0, 0, slotrank, ADDR_UPDATE_NONE); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD, + IOSAV_RD | RANKSEL, 1, 4, ctrl->CAS + 8, SSQ_NA, 0, 6, 0, slotrank, ADDR_UPDATE_NONE); @@ -2427,7 +2427,7 @@ int discover_edges(ramctr_timing *ctrl) /* DRAM command MRS * MR3 disable MPR */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_MRS, + IOSAV_MRS | RANKSEL, 1, 3, ctrl->tMOD, SSQ_NA, 0, 6, 3, slotrank, ADDR_UPDATE_NONE); @@ -2456,21 +2456,21 @@ int discover_edges(ramctr_timing *ctrl) in this mode only RD and RDA are allowed all reads return a predefined pattern */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_MRS, + IOSAV_MRS | RANKSEL, 1, 3, ctrl->tMOD, SSQ_NA, 4, 6, 3, slotrank, ADDR_UPDATE_NONE); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_RD, + IOSAV_RD | RANKSEL, 3, 4, 4, SSQ_RD, 0, 0, 0, slotrank, ADDR_UPDATE_NONE); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD, + IOSAV_RD | RANKSEL, 1, 4, ctrl->CAS + 8, SSQ_NA, 0, 6, 0, slotrank, ADDR_UPDATE_NONE); @@ -2478,7 +2478,7 @@ int discover_edges(ramctr_timing *ctrl) /* DRAM command MRS * MR3 disable MPR */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_MRS, + IOSAV_MRS | RANKSEL, 1, 3, ctrl->tMOD, SSQ_NA, 0, 6, 3, slotrank, ADDR_UPDATE_NONE); @@ -2585,28 +2585,28 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotr /* DRAM command ACT */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ACT, + IOSAV_ACT | RANKSEL, 4, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), ctrl->tRCD, SSQ_NA, 0, 6, 0, slotrank, ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); /* DRAM command WR */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_WR, + IOSAV_WR | RANKSEL, 32, 20, ctrl->tWTR + ctrl->CWL + 8, SSQ_WR, 0, 0, 0, slotrank, ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD, + IOSAV_RD | RANKSEL, 32, 20, MAX(ctrl->tRTP, 8), SSQ_RD, 0, 0, 0, slotrank, ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); /* DRAM command PRE */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_PRE, + IOSAV_PRE | RANKSEL, 1, 3, ctrl->tRP, SSQ_NA, 1024, 6, 0, slotrank, ADDR_UPDATE_NONE); @@ -2709,28 +2709,28 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) /* DRAM command ACT */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ACT, + IOSAV_ACT | RANKSEL, 4, MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD), ctrl->tRCD, SSQ_NA, 0, 6, 0, slotrank, ADDR_UPDATE(0, 0, 1, 0, 18, 0, 0, 0)); /* DRAM command WR */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_WR, + IOSAV_WR | RANKSEL, 480, 4, ctrl->tWTR + ctrl->CWL + 8, SSQ_WR, 0, 0, 0, slotrank, ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD, + IOSAV_RD | RANKSEL, 480, 4, MAX(ctrl->tRTP, 8), SSQ_RD, 0, 0, 0, slotrank, ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); /* DRAM command PRE */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_PRE, + IOSAV_PRE | RANKSEL, 1, 4, ctrl->tRP, SSQ_NA, 1024, 6, 0, slotrank, ADDR_UPDATE_NONE); @@ -2926,28 +2926,28 @@ int channel_test(ramctr_timing *ctrl) /* DRAM command ACT */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ACT, + IOSAV_ACT | RANKSEL, 4, 40, 40, SSQ_NA, 0, 6, 0, slotrank, ADDR_UPDATE(0, 0, 1, 0, 18, 0, 0, 0)); /* DRAM command WR */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_WR, + IOSAV_WR | RANKSEL, 100, 4, 40, SSQ_WR, 0, 0, 0, slotrank, ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD, + IOSAV_RD | RANKSEL, 100, 4, 40, SSQ_RD, 0, 0, 0, slotrank, ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); /* DRAM command PRE */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_PRE, + IOSAV_PRE | RANKSEL, 1, 3, 40, SSQ_NA, 1024, 6, 0, slotrank, ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); @@ -2978,21 +2978,21 @@ void channel_scrub(ramctr_timing *ctrl) /* DRAM command ACT */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ACT, + IOSAV_ACT | RANKSEL, 1, MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD), ctrl->tRCD, SSQ_NA, row, 6, 0, slotrank, ADDR_UPDATE(1, 0, 0, 0, 18, 0, 0, 0)); /* DRAM command WR */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_WR, + IOSAV_WR | RANKSEL, 129, 4, 40, SSQ_WR, row, 0, 0, slotrank, ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); /* DRAM command PRE */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_PRE, + IOSAV_PRE | RANKSEL, 1, 3, 40, SSQ_NA, 1024, 6, 0, slotrank, ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 4c97bfe6d4..55b3fc5d5b 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -25,15 +25,16 @@ #define NUM_SLOTS 2 #define NUM_LANES 9 -#define NO_RANKSEL (~(1 << 16)) -#define IOSAV_MRS (0x1f000) -#define IOSAV_PRE (0x1f002) -#define IOSAV_ZQCS (0x1f003) -#define IOSAV_ACT (0x1f006) -#define IOSAV_RD (0x1f105) -#define IOSAV_NOP_ALT (0x1f107) -#define IOSAV_WR (0x1f201) -#define IOSAV_NOP (0x1f207) +#define NO_RANKSEL (~0) +#define RANKSEL (1 << 16) +#define IOSAV_MRS (0xf000) +#define IOSAV_PRE (0xf002) +#define IOSAV_ZQCS (0xf003) +#define IOSAV_ACT (0xf006) +#define IOSAV_RD (0xf105) +#define IOSAV_NOP_ALT (0xf107) +#define IOSAV_WR (0xf201) +#define IOSAV_NOP (0xf207) /* FIXME: Vendor BIOS uses 64 but our algorithms are less performant and even 1 seems to be enough in practice. */ From 33e19ac6199fcd19da98ac70208581b107bf2cde Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 12 May 2020 20:11:12 +0200 Subject: [PATCH 105/405] Documentation: Fix 4.12 release notes, improve checklist Since I seem to forget to remove "Upcoming" in the release notes every single time, and others might as well, fix it here and also tell future release managers to take care of that. Change-Id: I8ffe34f25e954621bdd635e115a8b1a914df9c27 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/41337 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- Documentation/releases/checklist.md | 3 +++ Documentation/releases/coreboot-4.12-relnotes.md | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md index ea05c2036a..a80fd85804 100644 --- a/Documentation/releases/checklist.md +++ b/Documentation/releases/checklist.md @@ -67,6 +67,9 @@ be more frequent than was needed, so we scaled it back to twice a year. ask for testing. - [ ] Test the commit selected for release. - [ ] Update release notes with actual commit id, push to repo. +- [ ] Create new release notes doc template for the next version. +- [ ] Fill in the release date, remove "Upcoming release" and other filler + from the current release notes. - [ ] Run release script. - [ ] Run vboot_list script. - [ ] Test the release from the actual release tarballs. diff --git a/Documentation/releases/coreboot-4.12-relnotes.md b/Documentation/releases/coreboot-4.12-relnotes.md index aca3dd5cb3..1850ac8b4c 100644 --- a/Documentation/releases/coreboot-4.12-relnotes.md +++ b/Documentation/releases/coreboot-4.12-relnotes.md @@ -1,5 +1,5 @@ -Upcoming release - coreboot 4.12 -================================ +coreboot 4.12 +============= coreboot 4.12 was released on May 12th, 2020. From d906b21e2e1b5b4d5c1290436d4eaf1d5bc27070 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Mon, 11 May 2020 23:43:40 +0200 Subject: [PATCH 106/405] util/release: Improve reporting of required tools genrelnotes checks for cloc, git and rename but only reported about needing the first two, so mention `rename` in missing message. Change-Id: If91d759fc68760fd89b98756ac5b19ac3589c197 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/41338 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- util/release/genrelnotes | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/release/genrelnotes b/util/release/genrelnotes index 5803f8cfed..54933b0a59 100755 --- a/util/release/genrelnotes +++ b/util/release/genrelnotes @@ -16,7 +16,7 @@ if ! ( git --version && cloc --version && rename --version ) > /dev/null 2>&1 then - echo "ERROR: cloc or git is not installed. Exiting" + echo "ERROR: cloc, git or rename is not installed. Exiting" exit 1 fi From 81a30ec3a72bf948ac17bc145bd9f7cda3884ad4 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Mon, 11 May 2020 23:47:12 +0200 Subject: [PATCH 107/405] util/release: Check that HEAD isn't used as reference genrelnotes moves the tree between commits and so a relative location like HEAD isn't stable. Since I ran into the HEAD issue while preparing for two consecutive releases, let's guard against it. Change-Id: I70c6812cdfe0d0671b3d653744a062d9920a2394 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/41339 Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- util/release/genrelnotes | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/util/release/genrelnotes b/util/release/genrelnotes index 54933b0a59..5bd1a965e5 100755 --- a/util/release/genrelnotes +++ b/util/release/genrelnotes @@ -47,6 +47,11 @@ if [ "$1" == "--help" ] || [ -z "$1" ] || [ -z "$2" ]; then else OLD_GIT_VERSION="$1" NEW_GIT_VERSION="$2" + if [ "$OLD_GIT_VERSION" = "HEAD" -o "$NEW_GIT_VERSION" = "HEAD" ]; then + echo "Error: using HEAD as a reference doesn't work" + echo + exit 1 + fi TOTAL_COMMITS=$(git log --pretty=oneline \ "${OLD_GIT_VERSION}..${NEW_GIT_VERSION}" 2>/dev/null | wc -l) fi From 9e9f301b5878d269b7d6b6490279586fe533040a Mon Sep 17 00:00:00 2001 From: John Zhao Date: Wed, 13 May 2020 09:53:24 -0700 Subject: [PATCH 108/405] soc/intel/tigerlake: Fix wrong operation region for CPU to PCH method CPU to PCH method refers to PCH ACPI operation region which was wrongly defined as SystemIO. This causes ACPI AE_LIMIT error from PM _DSW method. Change the operation region from SystemIO to SystemMemory to resolve this execution failure. BUG=b:140290596 TEST=Built and booted to kernel. _DSW method executes successfully without ACPI AE_LIMIT error. Signed-off-by: John Zhao Change-Id: I3965c3d891f7d3cf4a448edc0c3f7e7749a905a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41365 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/soc/intel/tigerlake/acpi/tcss.asl | 6 +++--- src/soc/intel/tigerlake/acpi/tcss_pcierp.asl | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index ce97782b93..7d586dd11e 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -45,10 +45,10 @@ Scope (\_SB) } /* - * Define PCH ACPIBASE I/O as an ACPI operating region. The base address can be + * Define PCH ACPIBASE as an ACPI operating region. The base address can be * found in Device 31, Function 2, Offset 40h. */ - OperationRegion (PMIO, SystemIO, PCH_PWRM_BASE_ADDRESS, 0x80) + OperationRegion (PMIO, SystemMemory, PCH_PWRM_BASE_ADDRESS, 0x80) Field (PMIO, ByteAcc, NoLock, Preserve) { Offset(0x6C), /* 0x6C, General Purpose Event 0 Status [127:96] */ , 19, @@ -74,7 +74,7 @@ Scope (\_SB) */ Method (C2PM, 4, NotSerialized) { - Local0 = 0x1 << Arg3 + Local0 = 1 << Arg3 /* This method is used to enable/disable wake from Tcss Device (WKEN). */ If (Arg0 && Arg1) { /* If entering Sx and enabling wake, need to enable WAKE capability. */ diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl index 2b5531fc2a..a7eafa40bf 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl @@ -64,7 +64,7 @@ Field (PXCS, AnyAcc, NoLock, WriteAsZeros) */ Method (_DSM, 4, Serialized) { - return (Buffer() {0x00}) + Return (Buffer() {0x00}) } Device (PXSX) From 022d935919e13e5ae0408348328387cd7ece7e66 Mon Sep 17 00:00:00 2001 From: Shaunak Saha Date: Tue, 12 May 2020 10:37:59 -0700 Subject: [PATCH 109/405] mb/ripto: Update ALC5682 headset interrupt configurations As per schematics configure headset interrupt as edge both for ripto and volteer baseboard. BUG=b:147085988 BRANCH=none TEST=Build and boot ripto board. Test that jack functionality is working fine and also confirm with evtest. Signed-off-by: Shaunak Saha Change-Id: I8e1625140ccf55db8cb0fe3c039f1c31c01069b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41335 Tested-by: build bot (Jenkins) Reviewed-by: Sathyanarayana Nujella Reviewed-by: Duncan Laurie Reviewed-by: Srinidhi N Kaushik --- src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 2 +- src/mainboard/google/volteer/variants/baseboard/gpio.c | 2 +- src/mainboard/google/volteer/variants/malefor/gpio.c | 2 +- src/mainboard/google/volteer/variants/ripto/gpio.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index b68966331c..273b7a8ccc 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -243,7 +243,7 @@ chip soc/intel/tigerlake register "hid" = ""10EC5682"" register "name" = ""RT58"" register "desc" = ""Realtek RT5682"" - register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_F8_IRQ)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" # Set the jd_src to RT5668_JD1 for jack detection register "property_count" = "1" register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index bff7e3c3ad..2ca59aa29d 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -260,7 +260,7 @@ static const struct pad_config gpio_table[] = { /* F7 : GPPF7_STRAP */ PAD_NC(GPP_F7, NONE), /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ - PAD_CFG_GPI_APIC(GPP_F8, UP_20K, DEEP, EDGE_BOTH, INVERT), + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), /* F9 : Reserved ==> NC */ PAD_NC(GPP_F9, NONE), /* F10 : GPPF10_STRAP */ diff --git a/src/mainboard/google/volteer/variants/malefor/gpio.c b/src/mainboard/google/volteer/variants/malefor/gpio.c index f02eb09118..bd66acd57c 100644 --- a/src/mainboard/google/volteer/variants/malefor/gpio.c +++ b/src/mainboard/google/volteer/variants/malefor/gpio.c @@ -255,7 +255,7 @@ static const struct pad_config gpio_table[] = { /* F7 : GPPF7_STRAP */ PAD_NC(GPP_F7, NONE), /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ - PAD_CFG_GPI_APIC(GPP_F8, UP_20K, DEEP, EDGE_BOTH, INVERT), + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), /* F9 : Reserved ==> NC */ /* F10 : GPPF10_STRAP */ PAD_NC(GPP_F10, DN_20K), diff --git a/src/mainboard/google/volteer/variants/ripto/gpio.c b/src/mainboard/google/volteer/variants/ripto/gpio.c index b9041ed263..9a7ca94ebe 100644 --- a/src/mainboard/google/volteer/variants/ripto/gpio.c +++ b/src/mainboard/google/volteer/variants/ripto/gpio.c @@ -255,7 +255,7 @@ static const struct pad_config gpio_table[] = { /* F7 : GPPF7_STRAP */ PAD_NC(GPP_F7, DN_20K), /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ - PAD_CFG_GPI_APIC(GPP_F8, UP_20K, DEEP, EDGE_BOTH, INVERT), + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), /* F9 : Reserved ==> NC */ /* F10 : GPPF10_STRAP */ PAD_NC(GPP_F10, DN_20K), From 8f694dd51f54c84a23251aeb175cb822da46cc9b Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Wed, 13 May 2020 13:20:53 -0600 Subject: [PATCH 110/405] arch/x86/early_ram.ld: Add vboot work buffer This is required to enable VBOOT_STARTS_IN_BOOTBLOCK and VBOOT_SEPARATE_VERSTAGE for picasso. BUG=b:147042464 TEST=Boot verstage on picasso Signed-off-by: Raul E Rangel Change-Id: Ic3e261a6919a78760d567be9cc684494a5aeab6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/41366 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/arch/x86/early_ram.ld | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/early_ram.ld b/src/arch/x86/early_ram.ld index cbf573f180..82bd775e9c 100644 --- a/src/arch/x86/early_ram.ld +++ b/src/arch/x86/early_ram.ld @@ -23,7 +23,7 @@ _FMAP_SIZE = 0; * The stack area is not shared between stages, but is defined here for * convenience. */ -. = CONFIG_X86_RESET_VECTOR - ARCH_STACK_ALIGN_SIZE - _STACK_SIZE - _CONSOLE_SIZE - _TIMESTAMPS_SIZE - _FMAP_SIZE; +. = CONFIG_X86_RESET_VECTOR - ARCH_STACK_ALIGN_SIZE - _STACK_SIZE - _CONSOLE_SIZE - _TIMESTAMPS_SIZE - _FMAP_SIZE - VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE; _ = ASSERT(. > _eprogram, "Not enough room for .earlyram.data. Try increasing C_ENV_BOOTBLOCK_SIZE, or decreasing either EARLYRAM_BSP_STACK_SIZE or PRERAM_CBMEM_CONSOLE_SIZE."); @@ -37,6 +37,11 @@ _ = ASSERT(. > _eprogram, "Not enough room for .earlyram.data. Try increasing C_ #if !CONFIG(NO_FMAP_CACHE) FMAP_CACHE(., FMAP_SIZE) #endif + + #if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) + ALIGN_COUNTER(16); + VBOOT2_WORK(., VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) + #endif } _ = ASSERT(. <= CONFIG_X86_RESET_VECTOR, "Earlyram data regions don't fit below the reset vector!"); From 5f52c0e91fc4ea545b6920157af7508b4a69a718 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Wed, 13 May 2020 13:22:48 -0600 Subject: [PATCH 111/405] soc/amd/picasso: Set VERSTAGE_ADDR for picasso By default ROMSTAGE_ADDR and VERSTAGE_ADDR are set to 0x2000000. This causes problems in a non-xip environment because when verstage loads romstage, it overrides it's memory. So pick a different offset for verstage. BUG=b:147042464 TEST=Boot verstage on trembyle and see OS boot. Signed-off-by: Raul E Rangel Change-Id: I2464db6f3769bd23d250588b341d1c9e44f10d21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41367 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index b065e2fcfd..4795211dc6 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -81,6 +81,10 @@ config MMCONF_BUS_NUMBER int default 64 +config VERSTAGE_ADDR + hex + default 0x4000000 + config VGA_BIOS_ID string default "1002,15d8" From 4fafd412090d7de9a2ec6232ed22bbb1b1ce5dde Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Thu, 7 May 2020 15:32:39 +0530 Subject: [PATCH 112/405] soc/intel/common: add processor power limits control support Add processor power limits control support under common code. BRANCH=None BUG=None TEST=Built and checked this entry on Volteer system, cat /sys/class/powercap/intel-rapl/intel-rapl\:0/* Change-Id: I41fd95949aa2b02828aa2d13d29b962cb579904a Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/39346 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../block/include/intelblocks/power_limit.h | 41 ++++ .../intel/common/block/power_limit/Kconfig | 5 + .../common/block/power_limit/Makefile.inc | 1 + .../common/block/power_limit/power_limit.c | 198 ++++++++++++++++++ 4 files changed, 245 insertions(+) create mode 100644 src/soc/intel/common/block/include/intelblocks/power_limit.h create mode 100644 src/soc/intel/common/block/power_limit/Kconfig create mode 100644 src/soc/intel/common/block/power_limit/Makefile.inc create mode 100644 src/soc/intel/common/block/power_limit/power_limit.c diff --git a/src/soc/intel/common/block/include/intelblocks/power_limit.h b/src/soc/intel/common/block/include/intelblocks/power_limit.h new file mode 100644 index 0000000000..2fa25de5be --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/power_limit.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SOC_INTEL_COMMON_BLOCK_POWER_LIMIT_H_ +#define _SOC_INTEL_COMMON_BLOCK_POWER_LIMIT_H_ + +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 + +#define MSR_VR_CURRENT_CONFIG 0x601 +#define MSR_PL3_CONTROL 0x615 +#define MSR_PLATFORM_POWER_LIMIT 0x65c + +/* Default power limit value in secs */ +#define MOBILE_SKU_PL1_TIME_SEC 28 + +struct soc_power_limits_config { + /* PL1 Override value in Watts */ + uint16_t tdp_pl1_override; + /* PL2 Override value in Watts */ + uint16_t tdp_pl2_override; + /* SysPL2 Value in Watts */ + uint16_t tdp_psyspl2; + /* SysPL3 Value in Watts */ + uint16_t tdp_psyspl3; + /* SysPL3 window size */ + uint32_t tdp_psyspl3_time; + /* SysPL3 duty cycle */ + uint32_t tdp_psyspl3_dutycycle; + /* PL4 Value in Watts */ + uint16_t tdp_pl4; + /* Estimated maximum platform power in Watts */ + uint16_t psys_pmax; +}; + +/* Configure power limits for turbo mode */ +void set_power_limits(u8 power_limit_1_time, + struct soc_power_limits_config *config); + +#endif /* _SOC_INTEL_COMMON_BLOCK_POWER_LIMIT_H_ */ diff --git a/src/soc/intel/common/block/power_limit/Kconfig b/src/soc/intel/common/block/power_limit/Kconfig new file mode 100644 index 0000000000..5b2b34885f --- /dev/null +++ b/src/soc/intel/common/block/power_limit/Kconfig @@ -0,0 +1,5 @@ +config SOC_INTEL_COMMON_BLOCK_POWER_LIMIT + bool + default n + help + This option allows to configure processor power limit values. diff --git a/src/soc/intel/common/block/power_limit/Makefile.inc b/src/soc/intel/common/block/power_limit/Makefile.inc new file mode 100644 index 0000000000..83c41a7ba7 --- /dev/null +++ b/src/soc/intel/common/block/power_limit/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT) += power_limit.c diff --git a/src/soc/intel/common/block/power_limit/power_limit.c b/src/soc/intel/common/block/power_limit/power_limit.c new file mode 100644 index 0000000000..2ac82b3d3d --- /dev/null +++ b/src/soc/intel/common/block/power_limit/power_limit.c @@ -0,0 +1,198 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include + +/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ +static const u8 power_limit_time_sec_to_msr[] = { + [0] = 0x00, + [1] = 0x0a, + [2] = 0x0b, + [3] = 0x4b, + [4] = 0x0c, + [5] = 0x2c, + [6] = 0x4c, + [7] = 0x6c, + [8] = 0x0d, + [10] = 0x2d, + [12] = 0x4d, + [14] = 0x6d, + [16] = 0x0e, + [20] = 0x2e, + [24] = 0x4e, + [28] = 0x6e, + [32] = 0x0f, + [40] = 0x2f, + [48] = 0x4f, + [56] = 0x6f, + [64] = 0x10, + [80] = 0x30, + [96] = 0x50, + [112] = 0x70, + [128] = 0x11, +}; + +/* Convert POWER_LIMIT_1_TIME MSR value to seconds */ +static const u8 power_limit_time_msr_to_sec[] = { + [0x00] = 0, + [0x0a] = 1, + [0x0b] = 2, + [0x4b] = 3, + [0x0c] = 4, + [0x2c] = 5, + [0x4c] = 6, + [0x6c] = 7, + [0x0d] = 8, + [0x2d] = 10, + [0x4d] = 12, + [0x6d] = 14, + [0x0e] = 16, + [0x2e] = 20, + [0x4e] = 24, + [0x6e] = 28, + [0x0f] = 32, + [0x2f] = 40, + [0x4f] = 48, + [0x6f] = 56, + [0x10] = 64, + [0x30] = 80, + [0x50] = 96, + [0x70] = 112, + [0x11] = 128, +}; + +/* + * Configure processor power limits if possible + * This must be done AFTER set of BIOS_RESET_CPL + */ +void set_power_limits(u8 power_limit_1_time, + struct soc_power_limits_config *conf) +{ + msr_t msr = rdmsr(MSR_PLATFORM_INFO); + msr_t limit; + unsigned int power_unit; + unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1; + u8 power_limit_1_val; + + if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) + power_limit_1_time = + ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; + + if (!(msr.lo & PLATFORM_INFO_SET_TDP)) + return; + + /* Get units */ + msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = 1 << (msr.lo & 0xf); + + /* Get power defaults for this SKU */ + msr = rdmsr(MSR_PKG_POWER_SKU); + tdp = msr.lo & 0x7fff; + min_power = (msr.lo >> 16) & 0x7fff; + max_power = msr.hi & 0x7fff; + max_time = (msr.hi >> 16) & 0x7f; + + printk(BIOS_INFO, "CPU TDP = %u Watts\n", tdp / power_unit); + + if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) + power_limit_1_time = power_limit_time_msr_to_sec[max_time]; + + if (min_power > 0 && tdp < min_power) + tdp = min_power; + + if (max_power > 0 && tdp > max_power) + tdp = max_power; + + power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; + + /* Set long term power limit to TDP */ + limit.lo = 0; + tdp_pl1 = ((conf->tdp_pl1_override == 0) ? + tdp : (conf->tdp_pl1_override * power_unit)); + printk(BIOS_INFO, "CPU PL1 = %u Watts\n", tdp_pl1 / power_unit); + limit.lo |= (tdp_pl1 & PKG_POWER_LIMIT_MASK); + + /* Set PL1 Pkg Power clamp bit */ + limit.lo |= PKG_POWER_LIMIT_CLAMP; + + limit.lo |= PKG_POWER_LIMIT_EN; + limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << + PKG_POWER_LIMIT_TIME_SHIFT; + + /* Set short term power limit to 1.25 * TDP if no config given */ + limit.hi = 0; + tdp_pl2 = (conf->tdp_pl2_override == 0) ? + (tdp * 125) / 100 : (conf->tdp_pl2_override * power_unit); + printk(BIOS_INFO, "CPU PL2 = %u Watts\n", tdp_pl2 / power_unit); + limit.hi |= (tdp_pl2) & PKG_POWER_LIMIT_MASK; + limit.hi |= PKG_POWER_LIMIT_CLAMP; + limit.hi |= PKG_POWER_LIMIT_EN; + + /* Power limit 2 time is only programmable on server SKU */ + wrmsr(MSR_PKG_POWER_LIMIT, limit); + + /* Set PL2 power limit values in MCHBAR and disable PL1 */ + MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo & (~(PKG_POWER_LIMIT_EN)); + MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi; + + /* Set PsysPl2 */ + if (conf->tdp_psyspl2) { + limit = rdmsr(MSR_PLATFORM_POWER_LIMIT); + limit.hi = 0; + printk(BIOS_INFO, "CPU PsysPL2 = %u Watts\n", + conf->tdp_psyspl2); + limit.hi |= (conf->tdp_psyspl2 * power_unit) & + PKG_POWER_LIMIT_MASK; + limit.hi |= PKG_POWER_LIMIT_CLAMP; + limit.hi |= PKG_POWER_LIMIT_EN; + wrmsr(MSR_PLATFORM_POWER_LIMIT, limit); + } + + /* Set PsysPl3 */ + if (conf->tdp_psyspl3) { + limit = rdmsr(MSR_PL3_CONTROL); + limit.lo = 0; + printk(BIOS_INFO, "CPU PsysPL3 = %u Watts\n", + conf->tdp_psyspl3); + limit.lo |= (conf->tdp_psyspl3 * power_unit) & + PKG_POWER_LIMIT_MASK; + /* Enable PsysPl3 */ + limit.lo |= PKG_POWER_LIMIT_EN; + /* set PsysPl3 time window */ + limit.lo |= (conf->tdp_psyspl3_time & + PKG_POWER_LIMIT_TIME_MASK) << + PKG_POWER_LIMIT_TIME_SHIFT; + /* set PsysPl3 duty cycle */ + limit.lo |= (conf->tdp_psyspl3_dutycycle & + PKG_POWER_LIMIT_DUTYCYCLE_MASK) << + PKG_POWER_LIMIT_DUTYCYCLE_SHIFT; + wrmsr(MSR_PL3_CONTROL, limit); + } + + /* Set Pl4 */ + if (conf->tdp_pl4) { + limit = rdmsr(MSR_VR_CURRENT_CONFIG); + limit.lo = 0; + printk(BIOS_INFO, "CPU PL4 = %u Watts\n", conf->tdp_pl4); + limit.lo |= (conf->tdp_pl4 * power_unit) & + PKG_POWER_LIMIT_MASK; + wrmsr(MSR_VR_CURRENT_CONFIG, limit); + } + + /* Set DDR RAPL power limit by copying from MMIO to MSR */ + msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO); + msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI); + wrmsr(MSR_DDR_RAPL_LIMIT, msr); + + /* Use nominal TDP values for CPUs with configurable TDP */ + if (cpu_config_tdp_levels()) { + limit.hi = 0; + limit.lo = cpu_get_tdp_nominal_ratio(); + wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); + } +} From e8d1bef8cbd78c00065381848030655d34d0ecd3 Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Fri, 8 May 2020 21:31:44 +0530 Subject: [PATCH 113/405] jasperlake: update processor power limits configuration Update processor power limit configuration parameters based on common code base support for Intel Jasperlake SoC based platforms. BRANCH=None BUG=None TEST=Built for jasperlake system Change-Id: I9b725d041dcb8847f83ec103e58b9571b4c596ac Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/41237 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/jasperlake/Kconfig | 2 ++ src/soc/intel/jasperlake/chip.h | 6 ++++-- src/soc/intel/jasperlake/include/soc/cpu.h | 3 --- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 41905c5008..47766ede75 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -16,6 +16,7 @@ config CPU_SPECIFIC_OPTIONS select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select COMMON_FADT + select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_M_XIP select GENERIC_GPIO_LIB @@ -50,6 +51,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_SMM + select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 7a6a7fd0dd..d8ea560dfa 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +27,9 @@ struct soc_intel_jasperlake_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; + /* Common struct containing power limits configuration information */ + struct soc_power_limits_config power_limits_config; + /* Gpio group routed to each dword of the GPE0 block. Values are * of the form PMC_GPP_[A:U] or GPD. */ uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ @@ -145,8 +149,6 @@ struct soc_intel_jasperlake_config { /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* PL2 Override value in Watts */ - uint32_t tdp_pl2_override; /* Intel Speed Shift Technology */ uint8_t speed_shift_enable; diff --git a/src/soc/intel/jasperlake/include/soc/cpu.h b/src/soc/intel/jasperlake/include/soc/cpu.h index 58e9a8f590..1e5332de51 100644 --- a/src/soc/intel/jasperlake/include/soc/cpu.h +++ b/src/soc/intel/jasperlake/include/soc/cpu.h @@ -30,7 +30,4 @@ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ (IRTL_1024_NS >> 10)) -/* Configure power limits for turbo mode */ -void set_power_limits(u8 power_limit_1_time); - #endif From d0ded1652927016677e366e2cc8a112a60db251a Mon Sep 17 00:00:00 2001 From: Paul Ma Date: Fri, 8 May 2020 14:28:25 +0800 Subject: [PATCH 114/405] soc/mediatek: dsi: adjust hfp_byte and hbp_byte if too small If panel has too small hfp or hbp, hfp_byte or hbp_byte may become very small value or negative value. When very small value or negative value is used, the panel will be scrolling or distorted. This patch adjusts their values so that they are greater than the minimum value and keep total of them unchanged. DSI transfer HBP or HFP, There are some extra packet. ex. packet header(4byte) and eof(2byte) and (next)hs packet header(4 byte). the hfp_byte = HFP * BPP - packet header(4byte) and eof(2byte) and (next)hs packet header(4 byte). So the min hfp_byte is 2 when HFP = 4. This is equivalent to the Linux kernel DSI change in: https://chromium-review.googlesource.com/c/chromiumos/third_party/ kernel/+/2186872 BUG=b:144824303 BRANCH=kukui TEST=boot damu board with panel CMN N120ACA-EA1 (12" panel and its hbp only 6), the panel can display without scrolling or distortions. Signed-off-by: Paul Ma Change-Id: I608c01d41ae93c8d5094647bbf3e0ae4a23d814c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41163 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/soc/mediatek/common/dsi.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 3b9acd0ddc..73dacef33b 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -10,6 +10,9 @@ #include #include +#define MIN_HFP_BYTE 2 +#define MIN_HBP_BYTE 2 + static unsigned int mtk_dsi_get_bits_per_pixel(u32 format) { switch (format) { @@ -165,8 +168,8 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes, u32 hsync_active_byte; u32 hbp; u32 hfp; - u32 hbp_byte; - u32 hfp_byte; + s32 hbp_byte; + s32 hfp_byte; u32 vbp_byte; u32 vfp_byte; u32 bytes_per_pixel; @@ -215,6 +218,21 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes, "the panel may not work properly.\n"); } + if (hfp_byte + hbp_byte < MIN_HFP_BYTE + MIN_HBP_BYTE) { + printk(BIOS_ERR, "Calculated hfp_byte and hbp_byte are too small, " + "the panel may not work properly.\n"); + } else if (hfp_byte < MIN_HFP_BYTE) { + printk(BIOS_NOTICE, "Calculated hfp_byte is too small, " + "adjust it to the minimum value.\n"); + hbp_byte -= MIN_HFP_BYTE - hfp_byte; + hfp_byte = MIN_HFP_BYTE; + } else if (hbp_byte < MIN_HBP_BYTE) { + printk(BIOS_NOTICE, "Calculated hbp_byte is too small, " + "adjust it to the minimum value.\n"); + hfp_byte -= MIN_HBP_BYTE - hbp_byte; + hbp_byte = MIN_HBP_BYTE; + } + write32(&dsi0->dsi_hsa_wc, hsync_active_byte); write32(&dsi0->dsi_hbp_wc, hbp_byte); write32(&dsi0->dsi_hfp_wc, hfp_byte); From 544cc834700590c6c804150f1db81ee31a3bbd30 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Thu, 7 May 2020 13:21:36 +0200 Subject: [PATCH 115/405] mb/facebookmonolith: Update root port settings Update monolith root port settings to match those of the original BIOS. MaxPayload is set to 256 bytes, ASPM is disabled and LTR and Advanced Error reporting are enabled. BUG=N/A TEST=tested on facebook monolith Change-Id: Idf6e706d45cf1ea1aee4a75a6d0eb130b21db927 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/41172 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/mainboard/facebook/monolith/devicetree.cb | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 45829aac1f..102450a77a 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -161,6 +161,14 @@ chip soc/intel/skylake register "PcieRpEnable[2]" = "1" # Disable CLKREQ# register "PcieRpClkReqSupport[2]" = "0" + # Set MaxPayload to 256 bytes + register "PcieRpMaxPayload[2]" = "RpMaxPayload_256" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[2]" = "1" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[2]" = "1" + # Disable Aspm + register "PcieRpAspm[2]" = "AspmDisabled" # PCIE Port 4 disabled # PCIE Port 5 x1 -> MODULE i219 @@ -168,6 +176,14 @@ chip soc/intel/skylake # PCIE Port 6 x1 -> BASEBOARD x1 i210 : Mapped to PCIe 4 on the baseboard register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "0" + # Set MaxPayload to 256 bytes + register "PcieRpMaxPayload[5]" = "RpMaxPayload_256" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[5]" = "1" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[5]" = "1" + # Disable Aspm + register "PcieRpAspm[5]" = "AspmDisabled" # PCIE Port 7 Disabled # PCIE Port 8 Disabled @@ -178,6 +194,14 @@ chip soc/intel/skylake register "PcieRpClkReqSupport[8]" = "0" # Use Hot Plug subsystem register "PcieRpHotPlug[8]" = "1" + # Set MaxPayload to 256 bytes + register "PcieRpMaxPayload[8]" = "RpMaxPayload_256" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[8]" = "1" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[8]" = "1" + # Disable Aspm + register "PcieRpAspm[8]" = "AspmDisabled" # USB 2.0 Enable all ports register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C Port 2 From 30e9149c4fd716a8213cf0b5383774eecdb81829 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Fri, 1 May 2020 13:50:08 +0200 Subject: [PATCH 116/405] soc/intel/common/block/smbus: Use i2c read eeprom to speedup SPD read Reading the SPD using the SMBUS routines takes a long time because each byte or word is access seperately. Allow using the i2c read eeprom routines to read the SPD. By doing this the start address is only sent once per page. The time required to read a DDR4 SPD is reduced from 200 msec to 50 msec. BUG=N/A TEST=tested on facebook monolith Change-Id: I44e18b8ba72e1b2321f83402a6a055e2be6f940c Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/40942 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/soc/intel/common/block/smbus/smbuslib.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c index 5441b06219..a1a88180f2 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.c +++ b/src/soc/intel/common/block/smbus/smbuslib.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include "smbuslib.h" @@ -46,14 +47,23 @@ static int get_spd(u8 *spd, u8 addr) addr << 1); return -1; } - smbus_read_spd(spd, addr); + + if (do_i2c_eeprom_read(SMBUS_IO_BASE, addr, 0, SPD_PAGE_LEN, spd) == SMBUS_ERROR) { + printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n"); + smbus_read_spd(spd, addr); + } /* Check if module is DDR4, DDR4 spd is 512 byte. */ if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 && CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) { /* Switch to page 1 */ do_smbus_write_byte(SMBUS_IO_BASE, SPD_PAGE_1, 0, 0); - smbus_read_spd(spd + SPD_PAGE_LEN, addr); + + if (do_i2c_eeprom_read(SMBUS_IO_BASE, addr, 0, SPD_PAGE_LEN, + spd + SPD_PAGE_LEN) == SMBUS_ERROR) { + printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n"); + smbus_read_spd(spd + SPD_PAGE_LEN, addr); + } /* Restore to page 0 */ do_smbus_write_byte(SMBUS_IO_BASE, SPD_PAGE_0, 0, 0); } From 0aad0531dcbdd0628f9d16e27e34abb3f6e183aa Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 29 Apr 2020 07:26:25 +0200 Subject: [PATCH 117/405] util/autoport/bd82x6x.go: Drop unused includes Change-Id: Ifc0bf18dedc112e346062e0e0e988ac102991bb8 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40826 Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- util/autoport/bd82x6x.go | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 9f37aeef4f..4a724418af 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -294,21 +294,12 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) { sb := Create(ctx, "early_init.c") defer sb.Close() Add_gpl(sb) - sb.WriteString(`/* FIXME: Check if all includes are needed. */ + sb.WriteString(` -#include -#include -#include -#include -#include -#include -#include -#include #include #include #include #include -#include `) sb.WriteString("const struct southbridge_usb_port mainboard_usb_ports[] = {\n") From 19c2ce7639d55908d210782ae5a0315396cc7eaf Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 14 May 2020 08:32:33 +0200 Subject: [PATCH 118/405] Remove new additions of "this file is part of" lines Change-Id: I96dfa5b531842afcf774dd33c2dfa532b5d329c6 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41395 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: EricR Lai --- src/lib/spd_cache.c | 1 - src/soc/amd/picasso/include/soc/acp.h | 1 - src/soc/amd/picasso/include/soc/reset.h | 1 - 3 files changed, 3 deletions(-) diff --git a/src/lib/spd_cache.c b/src/lib/spd_cache.c index 71dfaf1024..be36141e26 100644 --- a/src/lib/spd_cache.c +++ b/src/lib/spd_cache.c @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ #include #include diff --git a/src/soc/amd/picasso/include/soc/acp.h b/src/soc/amd/picasso/include/soc/acp.h index e7ec17ca38..8825da8f6c 100644 --- a/src/soc/amd/picasso/include/soc/acp.h +++ b/src/soc/amd/picasso/include/soc/acp.h @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ #ifndef __PI_PICASSO_ACP_H__ #define __PI_PICASSO_ACP_H__ diff --git a/src/soc/amd/picasso/include/soc/reset.h b/src/soc/amd/picasso/include/soc/reset.h index 5fc549f203..bb2ee84e03 100644 --- a/src/soc/amd/picasso/include/soc/reset.h +++ b/src/soc/amd/picasso/include/soc/reset.h @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ #ifndef __PI_PICASSO_RESET_H__ #define __PI_PICASSO_RESET_H__ From 97c5464443306f26b61cec3a0f50108a5c06b7ef Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Sun, 10 May 2020 01:24:11 +0530 Subject: [PATCH 119/405] skylake: update processor power limits configuration Update processor power limit configuration parameters based on common code base support for Intel Skylake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on nami system Change-Id: Idc82f3d2f805b92fb3005d2f49098e55cb142e45 Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/41238 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/51nb/x210/devicetree.cb | 7 +- src/mainboard/asrock/h110m/devicetree.cb | 4 +- src/mainboard/google/eve/devicetree.cb | 6 +- src/mainboard/google/fizz/mainboard.c | 7 +- .../fizz/variants/baseboard/devicetree.cb | 6 +- .../fizz/variants/karma/overridetree.cb | 4 +- src/mainboard/google/glados/devicetree.cb | 4 +- .../glados/variants/caroline/overridetree.cb | 4 +- .../glados/variants/cave/overridetree.cb | 4 +- .../glados/variants/chell/overridetree.cb | 4 +- .../glados/variants/glados/overridetree.cb | 4 +- .../google/poppy/variants/atlas/devicetree.cb | 8 +- .../google/poppy/variants/atlas/mainboard.c | 5 +- .../poppy/variants/baseboard/devicetree.cb | 6 +- .../google/poppy/variants/nami/devicetree.cb | 4 +- .../google/poppy/variants/nami/mainboard.c | 6 +- .../poppy/variants/nautilus/devicetree.cb | 6 +- .../poppy/variants/nocturne/devicetree.cb | 8 +- .../poppy/variants/nocturne/mainboard.c | 5 +- .../poppy/variants/rammus/devicetree.cb | 6 +- .../poppy/variants/soraka/devicetree.cb | 6 +- .../kblrvp/variants/rvp11/overridetree.cb | 4 +- .../kblrvp/variants/rvp8/overridetree.cb | 4 +- src/mainboard/intel/kunimitsu/devicetree.cb | 4 +- src/mainboard/intel/saddlebrook/devicetree.cb | 4 +- src/mainboard/libretrend/lt1000/devicetree.cb | 4 +- src/mainboard/purism/librem_skl/devicetree.cb | 4 +- .../razer/blade_stealth_kbl/devicetree.cb | 7 +- src/soc/intel/skylake/Kconfig | 1 + src/soc/intel/skylake/chip.c | 9 +- src/soc/intel/skylake/chip.h | 25 +-- src/soc/intel/skylake/cpu.c | 190 ------------------ src/soc/intel/skylake/include/soc/cpu.h | 3 - src/soc/intel/skylake/systemagent.c | 8 +- 34 files changed, 121 insertions(+), 260 deletions(-) diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index e453aa432f..b610904a9e 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -118,10 +118,11 @@ chip soc/intel/skylake register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) # PL1 override 25W - register "tdp_pl1_override" = "25" - # PL2 override 44W - register "tdp_pl2_override" = "44" + register "power_limits_config" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 44, + }" # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 9ff8ceb62d..254eff853c 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -247,7 +247,9 @@ chip soc/intel/skylake register "PcieRpHotPlug[6]" = "1" # PL2 override 91W - register "tdp_pl2_override" = "91" + register "power_limits_config" = "{ + .tdp_pl2_override = 91, + }" # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 564b45dfc6..3b1f22c8c1 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -250,8 +250,10 @@ chip soc/intel/skylake register "speed_shift_enable" = "1" register "dptf_enable" = "1" - register "tdp_pl1_override" = "7" - register "tdp_pl2_override" = "15" + register "power_limits_config" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 15, + }" register "tcc_offset" = "10" device cpu_cluster 0 on diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 6627c47481..c86be82c68 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -99,7 +100,7 @@ static uint8_t board_sku_id(void) * | n (U22) | 29 | .9n | .9n | x(43) | * +-------------+-----+---------+---------+-------+ */ -static void mainboard_set_power_limits(config_t *conf) +static void mainboard_set_power_limits(struct soc_power_limits_config *conf) { enum usb_chg_type type; u32 watts; @@ -215,9 +216,11 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(struct device *dev) { + struct soc_power_limits_config *soc_conf; config_t *conf = config_of_soc(); - mainboard_set_power_limits(conf); + soc_conf = &conf->power_limits_config; + mainboard_set_power_limits(soc_conf); dev->ops->init = mainboard_init; dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index f02accec71..b8455fe9e9 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -325,8 +325,10 @@ chip soc/intel/skylake }" register "speed_shift_enable" = "1" - register "tdp_psyspl2" = "90" - register "psys_pmax" = "120" + register "power_limits_config" = "{ + .tdp_psyspl2 = 90, + .psys_pmax = 120, + }" register "tcc_offset" = "6" # TCC of 94C device cpu_cluster 0 on diff --git a/src/mainboard/google/fizz/variants/karma/overridetree.cb b/src/mainboard/google/fizz/variants/karma/overridetree.cb index f978240323..bfa260e9e9 100644 --- a/src/mainboard/google/fizz/variants/karma/overridetree.cb +++ b/src/mainboard/google/fizz/variants/karma/overridetree.cb @@ -17,7 +17,9 @@ chip soc/intel/skylake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Side register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card reader - register "psys_pmax" = "151" + register "power_limits_config" = "{ + .psys_pmax = 151, + }" device domain 0 on device pci 14.0 on diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 4e85e21111..f7be80d460 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -99,7 +99,9 @@ chip soc/intel/skylake register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # PL2 override 25W - register "tdp_pl2_override" = "25" + register "power_limits_config" = "{ + .tdp_pl2_override = 25, + }" # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" diff --git a/src/mainboard/google/glados/variants/caroline/overridetree.cb b/src/mainboard/google/glados/variants/caroline/overridetree.cb index ce364801ca..7bee2e2a48 100644 --- a/src/mainboard/google/glados/variants/caroline/overridetree.cb +++ b/src/mainboard/google/glados/variants/caroline/overridetree.cb @@ -25,7 +25,9 @@ chip soc/intel/skylake register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty # PL2 override 15W - register "tdp_pl2_override" = "15" + register "power_limits_config" = "{ + .tdp_pl2_override = 15, + }" # Send an extra VR mailbox command for the supported MPS IMVP8 model register "SendVrMbxCmd" = "1" diff --git a/src/mainboard/google/glados/variants/cave/overridetree.cb b/src/mainboard/google/glados/variants/cave/overridetree.cb index ae32b3dabf..9aeb78afa7 100644 --- a/src/mainboard/google/glados/variants/cave/overridetree.cb +++ b/src/mainboard/google/glados/variants/cave/overridetree.cb @@ -18,7 +18,9 @@ chip soc/intel/skylake register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A Port 2 # PL2 override 15W - register "tdp_pl2_override" = "15" + register "power_limits_config" = "{ + .tdp_pl2_override = 15, + }" # Send an extra VR mailbox command for the supported MPS IMVP8 model register "SendVrMbxCmd" = "1" diff --git a/src/mainboard/google/glados/variants/chell/overridetree.cb b/src/mainboard/google/glados/variants/chell/overridetree.cb index c6ccd208aa..ad3ae391c7 100644 --- a/src/mainboard/google/glados/variants/chell/overridetree.cb +++ b/src/mainboard/google/glados/variants/chell/overridetree.cb @@ -16,7 +16,9 @@ chip soc/intel/skylake register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD # PL2 override 15W - register "tdp_pl2_override" = "15" + register "power_limits_config" = "{ + .tdp_pl2_override = 15, + }" # Send an extra VR mailbox command for the supported MPS IMVP8 model register "SendVrMbxCmd" = "1" diff --git a/src/mainboard/google/glados/variants/glados/overridetree.cb b/src/mainboard/google/glados/variants/glados/overridetree.cb index 1bc69abb17..c510e920a0 100644 --- a/src/mainboard/google/glados/variants/glados/overridetree.cb +++ b/src/mainboard/google/glados/variants/glados/overridetree.cb @@ -18,7 +18,9 @@ chip soc/intel/skylake register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 2 # PL2 override 15W - register "tdp_pl2_override" = "15" + register "power_limits_config" = "{ + .tdp_pl2_override = 15, + }" # Send an extra VR mailbox command for the supported MPS IMVP8 model register "SendVrMbxCmd" = "1" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index b7ab523877..ce943c486c 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -70,9 +70,11 @@ chip soc/intel/skylake register "PmTimerDisabled" = "1" register "speed_shift_enable" = "1" - register "tdp_pl1_override" = "7" - register "tdp_pl2_override" = "15" - register "psys_pmax" = "45" + register "power_limits_config" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 15, + .psys_pmax = 45, + }" register "tcc_offset" = "10" register "pirqa_routing" = "PCH_IRQ11" diff --git a/src/mainboard/google/poppy/variants/atlas/mainboard.c b/src/mainboard/google/poppy/variants/atlas/mainboard.c index 7974a289d3..ea7ee8fdc4 100644 --- a/src/mainboard/google/poppy/variants/atlas/mainboard.c +++ b/src/mainboard/google/poppy/variants/atlas/mainboard.c @@ -5,6 +5,7 @@ #include #include #include +#include #define PL2_AML 18 #define PL2_KBL 15 @@ -25,8 +26,10 @@ static uint32_t get_pl2(void) /* Override dev tree settings per board */ void variant_devtree_update(void) { + struct soc_power_limits_config *soc_conf; config_t *cfg = config_of_soc(); + soc_conf = &cfg->power_limits_config; /* Update PL2 based on CPU */ - cfg->tdp_pl2_override = get_pl2(); + soc_conf->tdp_pl2_override = get_pl2(); } diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 77725349e7..0f3cc0443f 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -267,9 +267,11 @@ chip soc/intel/skylake }" register "speed_shift_enable" = "1" - register "psys_pmax" = "45" # PL2 override 15W for KBL-Y - register "tdp_pl2_override" = "15" + register "power_limits_config" = "{ + .tdp_pl2_override = 15, + .psys_pmax = 45, + }" register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index e4d148c3e2..4fa41c55ca 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -288,7 +288,9 @@ chip soc/intel/skylake register "speed_shift_enable" = "1" register "tcc_offset" = "3" # TCC of 97C - register "psys_pmax" = "101" + register "power_limits_config" = "{ + .psys_pmax = 101, + }" device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index 648e0d0647..8d5d0c482b 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -279,8 +280,11 @@ void variant_devtree_update(void) break; } + struct soc_power_limits_config *soc_conf; + soc_conf = &cfg->power_limits_config; + /* Update PL2 based on SKU. */ - cfg->tdp_pl2_override = get_pl2(pl2_id); + soc_conf->tdp_pl2_override = get_pl2(pl2_id); /* Overwrite settings for different projects based on OEM ID*/ oem_index = find_sku_mapping(read_oem_id()); diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index c3404bf4f8..c55562d0ec 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -288,9 +288,11 @@ chip soc/intel/skylake }" register "speed_shift_enable" = "1" - register "psys_pmax" = "45" # PL2 override 15W for KBL-Y - register "tdp_pl2_override" = "15" + register "power_limits_config" = "{ + .tdp_pl2_override = 15, + .psys_pmax = 45, + }" register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 96fcc39e65..8819350dce 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -66,9 +66,11 @@ chip soc/intel/skylake # Set speed_shift_enable to 1 to enable P-States, and 0 to disable register "speed_shift_enable" = "1" - register "tdp_pl1_override" = "7" - register "tdp_pl2_override" = "18" - register "psys_pmax" = "45" + register "power_limits_config" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 18, + .psys_pmax = 45, + }" register "tcc_offset" = "10" register "pirqa_routing" = "PCH_IRQ11" diff --git a/src/mainboard/google/poppy/variants/nocturne/mainboard.c b/src/mainboard/google/poppy/variants/nocturne/mainboard.c index 8d72144f9b..1482b3458f 100644 --- a/src/mainboard/google/poppy/variants/nocturne/mainboard.c +++ b/src/mainboard/google/poppy/variants/nocturne/mainboard.c @@ -5,6 +5,7 @@ #include #include #include +#include /* PL2 limit in watts for AML and KBL */ #define PL2_AML 18 @@ -26,8 +27,10 @@ static uint32_t get_pl2(void) /* Override dev tree settings per board */ void variant_devtree_update(void) { + struct soc_power_limits_config *soc_conf; config_t *cfg = config_of_soc(); + soc_conf = &cfg->power_limits_config; /* Update PL2 based on CPU */ - cfg->tdp_pl2_override = get_pl2(); + soc_conf->tdp_pl2_override = get_pl2(); } diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 65578708ad..de7023dacb 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -246,9 +246,11 @@ chip soc/intel/skylake }" register "speed_shift_enable" = "1" - register "psys_pmax" = "45" # PL2 override 18W for AML-Y - register "tdp_pl2_override" = "18" + register "power_limits_config" = "{ + .tdp_pl2_override = 18, + .psys_pmax = 45, + }" register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 146d8d2c19..8c22adea2f 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -268,9 +268,11 @@ chip soc/intel/skylake }" register "speed_shift_enable" = "1" - register "psys_pmax" = "45" # PL2 override 15W for KBL-Y - register "tdp_pl2_override" = "15" + register "power_limits_config" = "{ + .tdp_pl2_override = 15, + .psys_pmax = 45, + }" register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index 436a4ed7d4..fa502834af 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -111,7 +111,9 @@ chip soc/intel/skylake }" # PL2 override 60W - register "tdp_pl2_override" = "60" + register "power_limits_config" = "{ + .tdp_pl2_override = 60, + }" # Power Limit Related register "PowerLimit4" = "0" diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 46d7929d21..91abfe6f03 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -156,7 +156,9 @@ chip soc/intel/skylake }" # PL2 override 25W - register "tdp_pl2_override" = "25" + register "power_limits_config" = "{ + .tdp_pl2_override = 25, + }" # Use default SD card detect GPIO configuration #register "sdcard_cd_gpio_default" = "GPP_D10" diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index ab306149de..acd197bff4 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -166,7 +166,9 @@ chip soc/intel/skylake }" # PL2 override 25W - register "tdp_pl2_override" = "25" + register "power_limits_config" = "{ + .tdp_pl2_override = 25, + }" # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index f4ccb1bd5a..4811a41491 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -213,7 +213,9 @@ chip soc/intel/skylake }" # PL2 override 25W - register "tdp_pl2_override" = "25" + register "power_limits_config" = "{ + .tdp_pl2_override = 25, + }" # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index f54b877f18..95874bb5fa 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -171,7 +171,9 @@ chip soc/intel/skylake register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # F_USB3 header # PL2 override 25W - register "tdp_pl2_override" = "25" + register "power_limits_config" = "{ + .tdp_pl2_override = 25, + }" # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 854f5db48a..a439e02689 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -168,7 +168,9 @@ chip soc/intel/skylake register "PcieRpEnable[8]" = "1" # PL2 override 25W - register "tdp_pl2_override" = "25" + register "power_limits_config" = "{ + .tdp_pl2_override = 25, + }" # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index b55ef41f2d..7d54d33d8e 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -170,10 +170,11 @@ chip soc/intel/skylake register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # TODO Unknown. Maybe USBC? # PL1 override 25W - register "tdp_pl1_override" = "25" - # PL2 override 44W - register "tdp_pl2_override" = "44" + register "power_limits_config" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 44, + }" # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 0a5daeaa82..55437f356e 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -73,6 +73,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET + select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index ce566cf7b5..b14bb72a7b 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -124,10 +125,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) config = config_of_soc(); mainboard_silicon_init_params(params); + + struct soc_power_limits_config *soc_confg; + config_t *confg = config_of_soc(); + soc_confg = &confg->power_limits_config; /* Set PsysPmax if it is available from DT */ - if (config->psys_pmax) { + if (soc_confg->psys_pmax) { /* PsysPmax is in unit of 1/8 Watt */ - tconfig->PsysPmax = config->psys_pmax * 8; + tconfig->PsysPmax = soc_confg->psys_pmax * 8; printk(BIOS_DEBUG, "psys_pmax = %d\n", tconfig->PsysPmax); } diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index eb6cf9d7bc..92cd1bad85 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -33,6 +34,9 @@ struct soc_intel_skylake_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; + /* Common struct containing power limits configuration information */ + struct soc_power_limits_config power_limits_config; + /* IGD panel configuration */ unsigned int gpu_pp_up_delay_ms; unsigned int gpu_pp_down_delay_ms; @@ -100,27 +104,6 @@ struct soc_intel_skylake_config { /* Package PL4 power limit in Watts */ u32 PowerLimit4; - /* PL2 Override value in Watts */ - u32 tdp_pl2_override; - /* PL1 Override value in Watts */ - u32 tdp_pl1_override; - - /* SysPL2 Value in Watts */ - u32 tdp_psyspl2; - - /* SysPL3 Value in Watts */ - u32 tdp_psyspl3; - /* SysPL3 window size */ - u32 tdp_psyspl3_time; - /* SysPL3 duty cycle */ - u32 tdp_psyspl3_dutycycle; - - /* PL4 Value in Watts */ - u32 tdp_pl4; - - /* Estimated maximum platform power in Watts */ - u16 psys_pmax; - /* Whether to ignore VT-d support of the SKU */ int ignore_vtd; diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 1aba7f6a47..28572e5948 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -30,196 +30,6 @@ #include "chip.h" -/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ -static const u8 power_limit_time_sec_to_msr[] = { - [0] = 0x00, - [1] = 0x0a, - [2] = 0x0b, - [3] = 0x4b, - [4] = 0x0c, - [5] = 0x2c, - [6] = 0x4c, - [7] = 0x6c, - [8] = 0x0d, - [10] = 0x2d, - [12] = 0x4d, - [14] = 0x6d, - [16] = 0x0e, - [20] = 0x2e, - [24] = 0x4e, - [28] = 0x6e, - [32] = 0x0f, - [40] = 0x2f, - [48] = 0x4f, - [56] = 0x6f, - [64] = 0x10, - [80] = 0x30, - [96] = 0x50, - [112] = 0x70, - [128] = 0x11, -}; - -/* Convert POWER_LIMIT_1_TIME MSR value to seconds */ -static const u8 power_limit_time_msr_to_sec[] = { - [0x00] = 0, - [0x0a] = 1, - [0x0b] = 2, - [0x4b] = 3, - [0x0c] = 4, - [0x2c] = 5, - [0x4c] = 6, - [0x6c] = 7, - [0x0d] = 8, - [0x2d] = 10, - [0x4d] = 12, - [0x6d] = 14, - [0x0e] = 16, - [0x2e] = 20, - [0x4e] = 24, - [0x6e] = 28, - [0x0f] = 32, - [0x2f] = 40, - [0x4f] = 48, - [0x6f] = 56, - [0x10] = 64, - [0x30] = 80, - [0x50] = 96, - [0x70] = 112, - [0x11] = 128, -}; - -/* - * Configure processor power limits if possible - * This must be done AFTER set of BIOS_RESET_CPL - */ -void set_power_limits(u8 power_limit_1_time) -{ - msr_t msr = rdmsr(MSR_PLATFORM_INFO); - msr_t limit; - unsigned int power_unit; - unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1; - u8 power_limit_1_val; - - config_t *conf = config_of_soc(); - - if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) - power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; - - if (!(msr.lo & PLATFORM_INFO_SET_TDP)) - return; - - /* Get units */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 1 << (msr.lo & 0xf); - - /* Get power defaults for this SKU */ - msr = rdmsr(MSR_PKG_POWER_SKU); - tdp = msr.lo & 0x7fff; - min_power = (msr.lo >> 16) & 0x7fff; - max_power = msr.hi & 0x7fff; - max_time = (msr.hi >> 16) & 0x7f; - - printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); - - if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) - power_limit_1_time = power_limit_time_msr_to_sec[max_time]; - - if (min_power > 0 && tdp < min_power) - tdp = min_power; - - if (max_power > 0 && tdp > max_power) - tdp = max_power; - - power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; - - /* Set long term power limit to TDP */ - limit.lo = 0; - tdp_pl1 = ((conf->tdp_pl1_override == 0) ? - tdp : (conf->tdp_pl1_override * power_unit)); - limit.lo |= (tdp_pl1 & PKG_POWER_LIMIT_MASK); - - /* Set PL1 Pkg Power clamp bit */ - limit.lo |= PKG_POWER_LIMIT_CLAMP; - - limit.lo |= PKG_POWER_LIMIT_EN; - limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << - PKG_POWER_LIMIT_TIME_SHIFT; - - /* Set short term power limit to 1.25 * TDP if no config given */ - limit.hi = 0; - tdp_pl2 = (conf->tdp_pl2_override == 0) ? - (tdp * 125) / 100 : (conf->tdp_pl2_override * power_unit); - printk(BIOS_DEBUG, "CPU PL2 = %u Watts\n", tdp_pl2 / power_unit); - limit.hi |= (tdp_pl2) & PKG_POWER_LIMIT_MASK; - limit.hi |= PKG_POWER_LIMIT_CLAMP; - limit.hi |= PKG_POWER_LIMIT_EN; - - /* Power limit 2 time is only programmable on server SKU */ - wrmsr(MSR_PKG_POWER_LIMIT, limit); - - /* Set PL2 power limit values in MCHBAR and disable PL1 */ - MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo & (~(PKG_POWER_LIMIT_EN)); - MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi; - - /* Set PsysPl2 */ - if (conf->tdp_psyspl2) { - limit = rdmsr(MSR_PLATFORM_POWER_LIMIT); - limit.hi = 0; - printk(BIOS_DEBUG, "CPU PsysPL2 = %u Watts\n", - conf->tdp_psyspl2); - limit.hi |= (conf->tdp_psyspl2 * power_unit) & - PKG_POWER_LIMIT_MASK; - limit.hi |= PKG_POWER_LIMIT_CLAMP; - limit.hi |= PKG_POWER_LIMIT_EN; - - wrmsr(MSR_PLATFORM_POWER_LIMIT, limit); - } - - /* Set PsysPl3 */ - if (conf->tdp_psyspl3) { - limit = rdmsr(MSR_PL3_CONTROL); - limit.lo = 0; - printk(BIOS_DEBUG, "CPU PsysPL3 = %u Watts\n", - conf->tdp_psyspl3); - limit.lo |= (conf->tdp_psyspl3 * power_unit) & - PKG_POWER_LIMIT_MASK; - /* Enable PsysPl3 */ - limit.lo |= PKG_POWER_LIMIT_EN; - /* set PsysPl3 time window */ - limit.lo |= (conf->tdp_psyspl3_time & - PKG_POWER_LIMIT_TIME_MASK) << - PKG_POWER_LIMIT_TIME_SHIFT; - /* set PsysPl3 duty cycle */ - limit.lo |= (conf->tdp_psyspl3_dutycycle & - PKG_POWER_LIMIT_DUTYCYCLE_MASK) << - PKG_POWER_LIMIT_DUTYCYCLE_SHIFT; - wrmsr(MSR_PL3_CONTROL, limit); - } - - /* Set Pl4 */ - if (conf->tdp_pl4) { - limit = rdmsr(MSR_VR_CURRENT_CONFIG); - limit.lo = 0; - printk(BIOS_DEBUG, "CPU PL4 = %u Watts\n", - conf->tdp_pl4); - limit.lo |= (conf->tdp_pl4 * power_unit) & - PKG_POWER_LIMIT_MASK; - wrmsr(MSR_VR_CURRENT_CONFIG, limit); - } - - /* Set DDR RAPL power limit by copying from MMIO to MSR */ - msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO); - msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI); - wrmsr(MSR_DDR_RAPL_LIMIT, msr); - - /* Use nominal TDP values for CPUs with configurable TDP */ - if (cpu_config_tdp_levels()) { - limit.hi = 0; - limit.lo = cpu_get_tdp_nominal_ratio(); - wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); - } -} - static void configure_thermal_target(void) { config_t *conf = config_of_soc(); diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index 43710b6b98..740b3d3fb0 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -34,9 +34,6 @@ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ (IRTL_1024_NS >> 10)) -/* Configure power limits for turbo mode */ -void set_power_limits(u8 power_limit_1_time); - /* CPU identification */ u32 cpu_family_model(void); u32 cpu_stepping(void); diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index a4d7330a47..8e58bf6669 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -60,6 +61,9 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) */ void soc_systemagent_init(struct device *dev) { + struct soc_power_limits_config *soc_config; + config_t *config; + /* Enable Power Aware Interrupt Routing */ enable_power_aware_intr(); @@ -68,7 +72,9 @@ void soc_systemagent_init(struct device *dev) /* Configure turbo power limits 1ms after reset complete bit */ mdelay(1); - set_power_limits(28); + config = config_of_soc(); + soc_config = &config->power_limits_config; + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); } int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base, From e88f0311beec6d0df671819d892d4635e1aed2c8 Mon Sep 17 00:00:00 2001 From: Marco Chen Date: Thu, 30 Apr 2020 14:40:18 +0800 Subject: [PATCH 120/405] mb/google/dedede: update SPD name based on DRAM characteristic The index of DRAM_STRAPS indicates to a specific DRAM characteristic instead of a DRAM part number therefore update the existing DRAM SPD binary to the naming by DRAM characteristic. BUG=b:152019429 BRANCH=None TEST=build the image and verify that coreboot log shows the correct SPD info Change-Id: I8ffcf156f37a465209740c5e2a34effb5f1f5d5c Signed-off-by: Marco Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/40906 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- ...2GB.spd.hex => SPD_LPDDR4X_200b_8Gb_4267_DDP_1x16.spd.hex} | 0 src/mainboard/google/dedede/variants/waddledee/Makefile.inc | 4 ++-- src/mainboard/google/dedede/variants/waddledoo/Makefile.inc | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) rename src/mainboard/google/dedede/spd/{Micron_MT53E512M32D2NP_2GB.spd.hex => SPD_LPDDR4X_200b_8Gb_4267_DDP_1x16.spd.hex} (100%) diff --git a/src/mainboard/google/dedede/spd/Micron_MT53E512M32D2NP_2GB.spd.hex b/src/mainboard/google/dedede/spd/SPD_LPDDR4X_200b_8Gb_4267_DDP_1x16.spd.hex similarity index 100% rename from src/mainboard/google/dedede/spd/Micron_MT53E512M32D2NP_2GB.spd.hex rename to src/mainboard/google/dedede/spd/SPD_LPDDR4X_200b_8Gb_4267_DDP_1x16.spd.hex diff --git a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc index 6101f1583d..dfb97bae95 100644 --- a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later -SPD_SOURCES = Micron_MT53E512M32D2NP_2GB #0b0000 -SPD_SOURCES += empty #0b0001 +SPD_SOURCES = SPD_LPDDR4X_200b_8Gb_4267_DDP_1x16 #0b0000 +SPD_SOURCES += empty #0b0001 romstage-y += memory.c diff --git a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc index c0553b55f0..922c314ee3 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later -SPD_SOURCES = empty #0b0000 -SPD_SOURCES += Micron_MT53E512M32D2NP_2GB #0b0001 +SPD_SOURCES = empty #0b0000 +SPD_SOURCES += SPD_LPDDR4X_200b_8Gb_4267_DDP_1x16 #0b0001 romstage-y += memory.c From 54b706e6545781a6ffe353b64a3718b798f771ff Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Thu, 14 May 2020 13:58:01 +0800 Subject: [PATCH 121/405] soc/intel/tigerlake: Add PchHdaIDispCodecDisconnect override This is a missing config override in fspm_upd. iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. BUG=b:156447983 TEST=None Signed-off-by: Eric Lai Change-Id: Ifbbc22d14e06713009c550cbe8a7292de64e1fdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/41394 Reviewed-by: Kane Chen Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/chip.h | 1 + src/soc/intel/tigerlake/romstage/fsp_params.c | 1 + 2 files changed, 2 insertions(+) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index e6e106df94..c98fb667cc 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -95,6 +95,7 @@ struct soc_intel_tigerlake_config { uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]; uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS]; uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS]; + uint8_t PchHdaIDispCodecDisconnect; /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 6f0f06de6c..a444623fa5 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -159,6 +159,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable; + m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect; memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable, sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); memcpy(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable, From 4d4424658f7db51dea4d29febd20f1be7b8f4cf4 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Thu, 14 May 2020 14:49:52 +0800 Subject: [PATCH 122/405] mb/google/deltaur: Update audio setting Deltaur uses HDA codec so we need to set iDisplay Audio Codec disconnection and enable HdaAudioLink, otherwise the HDA codec won't respond to commands to execute HDA verbs. BUG=b:156447983 TEST=No timeout error when run "devbeep" in CLI. Signed-off-by: Eric Lai Change-Id: I15d2895866abcf68963c9732ed5d05f32096fc92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41397 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/deltaur/variants/baseboard/devicetree.cb | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 028b022a1b..370ebb75d6 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -126,7 +126,8 @@ chip soc/intel/tigerlake # HD Audio register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHdaEnable" = "0" + register "PchHdaAudioLinkHdaEnable" = "1" + register "PchHdaIDispCodecDisconnect" = "1" register "PchHdaAudioLinkDmicEnable[0]" = "1" register "PchHdaAudioLinkDmicEnable[1]" = "1" register "PchHdaAudioLinkSspEnable[0]" = "1" From 7ff5f28228a5199e97bb812b048457d111266a3e Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Thu, 14 May 2020 17:07:21 +0800 Subject: [PATCH 123/405] mb/google/deltaur: Add audio verb table Add audio verb table provided by vendor. BUG=b:156447983 TEST=Have beep sound when run "devbeep" in CLI. Signed-off-by: Eric Lai Change-Id: I807d84de1677459ea027e645488f485b0ac7b2ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/41401 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/deltaur/Kconfig | 1 + src/mainboard/google/deltaur/Makefile.inc | 1 + src/mainboard/google/deltaur/hda_verb.c | 3 + .../baseboard/include/baseboard/hda_verb.h | 196 ++++++++++++++++++ 4 files changed, 201 insertions(+) create mode 100644 src/mainboard/google/deltaur/hda_verb.c create mode 100644 src/mainboard/google/deltaur/variants/baseboard/include/baseboard/hda_verb.h diff --git a/src/mainboard/google/deltaur/Kconfig b/src/mainboard/google/deltaur/Kconfig index a9197f0f42..ddcdb26551 100644 --- a/src/mainboard/google/deltaur/Kconfig +++ b/src/mainboard/google/deltaur/Kconfig @@ -17,6 +17,7 @@ config BOARD_GOOGLE_BASEBOARD_DELTAUR select SOC_INTEL_TIGERLAKE select SYSTEM_TYPE_LAPTOP select MAINBOARD_USES_IFD_GBE_REGION if BOARD_GOOGLE_DELTAN + select SOC_INTEL_COMMON_BLOCK_HDA_VERB if BOARD_GOOGLE_BASEBOARD_DELTAUR diff --git a/src/mainboard/google/deltaur/Makefile.inc b/src/mainboard/google/deltaur/Makefile.inc index ab22a36d9f..5881615cc6 100644 --- a/src/mainboard/google/deltaur/Makefile.inc +++ b/src/mainboard/google/deltaur/Makefile.inc @@ -11,6 +11,7 @@ romstage-y += ec.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += mainboard.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-y += ec.c diff --git a/src/mainboard/google/deltaur/hda_verb.c b/src/mainboard/google/deltaur/hda_verb.c new file mode 100644 index 0000000000..ca2d06d8e2 --- /dev/null +++ b/src/mainboard/google/deltaur/hda_verb.c @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "baseboard/hda_verb.h" diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/hda_verb.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/hda_verb.h new file mode 100644 index 0000000000..671b0ed2c5 --- /dev/null +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/hda_verb.h @@ -0,0 +1,196 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_HDA_VERB_H +#define MAINBOARD_HDA_VERB_H + +#include + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0236, // Codec Vendor / Device ID: Realtek ALC3204 + 0xffffffff, // Subsystem ID + 0x0000002b, // Number of jacks (NID entries) + /* Rest Codec First */ + AZALIA_RESET(0x1), + /* HDA Codec Subsystem ID Verb-table + HDA Codec Subsystem ID : 0x10280A20 */ + 0x00172020, + 0x0017210A, + 0x00172228, + 0x00172310, + /* Pin Widget Verb-table */ + /* Widget node 0x01 : Widget Reset */ + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + /* Pin widget 0x12 - DMIC1-2 */ + 0x01271C40, + 0x01271D01, + 0x01271EA6, + 0x01271F90, + /* Pin widget 0x13 - DMIC3-4 */ + 0x01371C00, + 0x01371D00, + 0x01371E00, + 0x01371F40, + /* Pin widget 0x14 - FRONT (Port-D) */ + 0x01471C10, + 0x01471D01, + 0x01471E17, + 0x01471F90, + /* Pin widget 0x18 - MIC1 */ + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + /* Pin widget 0x19 - MIC2 (Port-F) */ + 0x01971CF0, + 0x01971D11, + 0x01971E11, + 0x01971F41, + /* Pin widget 0x1A - LINE1 (Port-C) */ + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + /* Pin widget 0x1B - LINE2 (Port-E) */ + 0x01B71CF0, + 0x01B71D11, + 0x01B71E11, + 0x01B71F41, + /* Pin widget 0x1D - BEEP-IN */ + 0x01D71C01, + 0x01D71D00, + 0x01D71E70, + 0x01D71F40, + /* Pin widget 0x1E - S/PDIF-OUT1 (Define special SKU for driver) */ + 0x01E71CF2, + 0x01E71D12, + 0x01E71E12, + 0x01E71F42, + /* Pin widget 0x21 - HP-OUT (Port-I) */ + 0x02171C20, + 0x02171D10, + 0x02171E21, + 0x02171F02, + + /* RESET to D0 */ + 0x00170500, + 0x00170500, + 0x00170500, + 0x00170500, + /* RESET Register */ + 0x0205001A, + 0x02048003, + 0x0205001A, + 0x0204C003, + /* ALC3204 default-1(Class D RESET) */ + 0x0205003C, + 0x02040354, + 0x0205003C, + 0x02040314, + /* ALC3204 default-2 */ + 0x02050040, + 0x02049800, + 0x02050034, + 0x0204023C, + /* ALC3204 Speaker output power - 4 ohm 2W (+12dB gain) + + Combo Jack TRS setting */ + 0x02050038, + 0x02043901, + 0x02050045, + 0x0204C489, + /* H/W AGC setting-1 */ + 0x02050016, + 0x02040C50, + 0x02050012, + 0x0204EBC2, + /* H/W AGC setting-2 */ + 0x02050013, + 0x0204401D, + 0x02050016, + 0x02044E50, + /* Zero data + EAPD to verb-control */ + 0x02050037, + 0x0204FE15, + 0x02050010, + 0x02040020, + /* Zero data */ + 0x02050030, + 0x02048000, + 0x02050030, + 0x02048000, + /* ALC3204 default-3 */ + 0x05750003, + 0x05740DA3, + 0x02050046, + 0x02040004, + /* ALC3204 default-4 */ + 0x0205001B, + 0x02040A4B, + 0x02050008, + 0x02046A6C, + /* JD1 */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + /* Microphone + Array MIC security Disable +ADC clock Enable */ + 0x0205000D, + 0x0204A020, + 0x02050005, + 0x02040700, + /* Speaker Enable */ + 0x0205000C, + 0x020401EF, + 0x0205000C, + 0x020401EF, + /* EQ Bypass + EQ HPF cutoff 250Hz */ + 0x05350000, + 0x0534201A, + 0x0535001d, + 0x05340800, + /* EQ-2 */ + 0x0535001e, + 0x05340800, + 0x05350003, + 0x05341EF8, + /* EQ-3 */ + 0x05350004, + 0x05340000, + 0x05450000, + 0x05442000, + /* EQ-4 */ + 0x0545001d, + 0x05440800, + 0x0545001e, + 0x05440800, + /* EQ-5 */ + 0x05450003, + 0x05441EF8, + 0x05450004, + 0x05440000, + /* EQ Update */ + 0x05350000, + 0x0534E01A, + 0x05350000, + 0x0534E01A, +}; + +const u32 pc_beep_verbs[] = { + /* PCBeep pass through to NID14 for ePSA test-1 */ + 0x02050036, + 0x02047717, + 0x02050036, + 0x02047717, + /* PCBeep pass through to NID14 for ePSA test-2 */ + 0x01470740, + 0x0143B000, + 0x01470C02, + 0x01470C02, +}; + +AZALIA_ARRAY_SIZES; + +#endif From 2abe9cf2d7bc067d07e35f214930a2fb8047d194 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Fri, 15 May 2020 15:20:03 +0800 Subject: [PATCH 124/405] mb/google/deltaur: Remove DSP setting Deltaur does not use DSP so remove the DSP setting. BUG=b:155360937 TEST=Recording and playing are working fine in OS. Signed-off-by: Eric Lai Change-Id: I01c076806448fc73980ec02e7558ccf082723d92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41423 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../google/deltaur/variants/baseboard/devicetree.cb | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 370ebb75d6..b2062cbd07 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -125,13 +125,8 @@ chip soc/intel/tigerlake }" # HD Audio - register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "1" register "PchHdaIDispCodecDisconnect" = "1" - register "PchHdaAudioLinkDmicEnable[0]" = "1" - register "PchHdaAudioLinkDmicEnable[1]" = "1" - register "PchHdaAudioLinkSspEnable[0]" = "1" - register "PchHdaAudioLinkSspEnable[1]" = "1" # TCSS USB3 register "TcssXhciEn" = "1" From ed3496730322286370b956e3eeb038ee56a41c74 Mon Sep 17 00:00:00 2001 From: Krishna Prasad Bhat Date: Tue, 21 Apr 2020 19:09:43 +0530 Subject: [PATCH 125/405] soc/intel/jasperlake: Add function to display ME firmware status info Add function to display ME Host Firmware Status registers. Make use of print_me_fw_version() from CSE lib to print ME firmware version information. Add manufacturing mode field in HFSTS1 register for JSL in place of, spi_protection_mode in TGL. BUG=None BRANCH=None TEST=Build and boot jslrvp. In coreboot logs, ME info can be seen. ME: Version: 13.5.0.7049 ME: HFSTS1 : 0x90006255 ME: HFSTS2 : 0x82100136 ME: HFSTS3 : 0x00000020 ME: HFSTS4 : 0x00004800 ME: HFSTS5 : 0x00000000 ME: HFSTS6 : 0x00400006 ME: Manufacturing Mode : YES ME: FW Partition Table : OK ME: Bringup Loader Failure : NO ME: Firmware Init Complete : YES ME: Boot Options Present : NO ME: Update In Progress : NO ME: D0i3 Support : YES ME: Low Power State Enabled : NO ME: CPU Replaced : YES ME: CPU Replacement Valid : YES ME: Current Working State : 5 ME: Current Operation State : 1 ME: Current Operation Mode : 0 ME: Error Code : 6 ME: CPU Debug Disabled : YES ME: TXT Support : NO Change-Id: Ic6b1c9410db8f06ac24fd997772b2ede04264bee Signed-off-by: Krishna Prasad Bhat Reviewed-on: https://review.coreboot.org/c/coreboot/+/40570 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/soc/intel/jasperlake/Makefile.inc | 1 + src/soc/intel/jasperlake/include/soc/me.h | 132 +++++++++++++++++----- src/soc/intel/jasperlake/me.c | 71 ++++++++++++ 3 files changed, 178 insertions(+), 26 deletions(-) create mode 100644 src/soc/intel/jasperlake/me.c diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 4a65adc111..c5ad4d2095 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -44,6 +44,7 @@ ramstage-y += reset.c ramstage-y += smmrelocate.c ramstage-y += systemagent.c ramstage-y += sd.c +ramstage-y += me.c smm-y += gpio.c smm-y += p2sb.c diff --git a/src/soc/intel/jasperlake/include/soc/me.h b/src/soc/intel/jasperlake/include/soc/me.h index a4ede83903..73196905f8 100644 --- a/src/soc/intel/jasperlake/include/soc/me.h +++ b/src/soc/intel/jasperlake/include/soc/me.h @@ -5,39 +5,119 @@ /* ME Host Firmware Status register 1 */ union me_hfsts1 { - u32 data; + uint32_t data; struct { - u32 working_state: 4; - u32 spi_protection_mode: 1; - u32 fpt_bad: 1; - u32 operation_state: 3; - u32 fw_init_complete: 1; - u32 ft_bup_ld_flr: 1; - u32 update_in_progress: 1; - u32 error_code: 4; - u32 operation_mode: 4; - u32 reset_count: 4; - u32 boot_options_present: 1; - u32 invoke_enhance_dbg_mode: 1; - u32 bist_test_state: 1; - u32 bist_reset_request: 1; - u32 current_power_source: 2; - u32 reserved: 1; - u32 d0i3_support_valid: 1; + uint32_t working_state: 4; + uint32_t mfg_mode: 1; + uint32_t fpt_bad: 1; + uint32_t operation_state: 3; + uint32_t fw_init_complete: 1; + uint32_t ft_bup_ld_flr: 1; + uint32_t update_in_progress: 1; + uint32_t error_code: 4; + uint32_t operation_mode: 4; + uint32_t reset_count: 4; + uint32_t boot_options_present: 1; + uint32_t reserved1: 1; + uint32_t bist_test_state: 1; + uint32_t bist_reset_request: 1; + uint32_t current_power_source: 2; + uint32_t reserved: 1; + uint32_t d0i3_support_valid: 1; + } __packed fields; +}; + +/* Host Firmware Status Register 2 */ +union me_hfsts2 { + uint32_t data; + struct { + uint32_t nftp_load_failure : 1; + uint32_t icc_prog_status : 2; + uint32_t invoke_mebx : 1; + uint32_t cpu_replaced : 1; + uint32_t rsvd0 : 1; + uint32_t mfs_failure : 1; + uint32_t warm_reset_rqst : 1; + uint32_t cpu_replaced_valid : 1; + uint32_t low_power_state : 1; + uint32_t me_power_gate : 1; + uint32_t ipu_needed : 1; + uint32_t forced_safe_boot : 1; + uint32_t rsvd1 : 2; + uint32_t listener_change : 1; + uint32_t status_data : 8; + uint32_t current_pmevent : 4; + uint32_t phase : 4; } __packed fields; }; /* ME Host Firmware Status Register 3 */ union me_hfsts3 { - u32 data; + uint32_t data; struct { - u32 reserved_0: 4; - u32 fw_sku: 3; - u32 reserved_7: 2; - u32 reserved_9: 2; - u32 resered_11: 3; - u32 resered_14: 16; - u32 reserved_30: 2; + uint32_t reserved_0: 4; + uint32_t fw_sku: 3; + uint32_t reserved: 25; + } __packed fields; +}; + +/* Host Firmware Status Register 4 */ +union me_hfsts4 { + uint32_t data; + struct { + uint32_t rsvd0 : 9; + uint32_t enforcement_flow : 1; + uint32_t sx_resume_type : 1; + uint32_t rsvd1 : 1; + uint32_t tpms_disconnected : 1; + uint32_t rvsd2 : 1; + uint32_t fwsts_valid : 1; + uint32_t boot_guard_self_test : 1; + uint32_t rsvd3 : 16; + } __packed fields; +}; + +/* Host Firmware Status Register 5 */ +union me_hfsts5 { + uint32_t data; + struct { + uint32_t acm_active : 1; + uint32_t valid : 1; + uint32_t result_code_source : 1; + uint32_t error_status_code : 5; + uint32_t acm_done_sts : 1; + uint32_t timeout_count : 7; + uint32_t scrtm_indicator : 1; + uint32_t inc_boot_guard_acm : 4; + uint32_t inc_key_manifest : 4; + uint32_t inc_boot_policy : 4; + uint32_t rsvd0 : 2; + uint32_t start_enforcement : 1; + } __packed fields; +}; + +/* Host Firmware Status Register 6 */ +union me_hfsts6 { + uint32_t data; + struct { + uint32_t force_boot_guard_acm : 1; + uint32_t cpu_debug_disable : 1; + uint32_t bsp_init_disable : 1; + uint32_t protect_bios_env : 1; + uint32_t rsvd0 : 2; + uint32_t error_enforce_policy : 2; + uint32_t measured_boot : 1; + uint32_t verified_boot : 1; + uint32_t boot_guard_acmsvn : 4; + uint32_t kmsvn : 4; + uint32_t bpmsvn : 4; + uint32_t key_manifest_id : 4; + uint32_t boot_policy_status : 1; + uint32_t error : 1; + uint32_t boot_guard_disable : 1; + uint32_t fpf_disable : 1; + uint32_t fpf_soc_lock : 1; + uint32_t txt_support : 1; } __packed fields; }; #endif /* _JASPERLAKE_ME_H_ */ diff --git a/src/soc/intel/jasperlake/me.c b/src/soc/intel/jasperlake/me.c new file mode 100644 index 0000000000..c8496f9645 --- /dev/null +++ b/src/soc/intel/jasperlake/me.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include + +static void dump_me_status(void *unused) +{ + union me_hfsts1 hfsts1; + union me_hfsts2 hfsts2; + union me_hfsts3 hfsts3; + union me_hfsts4 hfsts4; + union me_hfsts5 hfsts5; + union me_hfsts6 hfsts6; + + if (!is_cse_enabled()) + return; + + hfsts1.data = me_read_config32(PCI_ME_HFSTS1); + hfsts2.data = me_read_config32(PCI_ME_HFSTS2); + hfsts3.data = me_read_config32(PCI_ME_HFSTS3); + hfsts4.data = me_read_config32(PCI_ME_HFSTS4); + hfsts5.data = me_read_config32(PCI_ME_HFSTS5); + hfsts6.data = me_read_config32(PCI_ME_HFSTS6); + + printk(BIOS_DEBUG, "ME: HFSTS1 : 0x%08X\n", hfsts1.data); + printk(BIOS_DEBUG, "ME: HFSTS2 : 0x%08X\n", hfsts2.data); + printk(BIOS_DEBUG, "ME: HFSTS3 : 0x%08X\n", hfsts3.data); + printk(BIOS_DEBUG, "ME: HFSTS4 : 0x%08X\n", hfsts4.data); + printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", hfsts5.data); + printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", hfsts6.data); + + printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", + hfsts1.fields.mfg_mode ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", + hfsts1.fields.fpt_bad ? "BAD" : "OK"); + printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", + hfsts1.fields.ft_bup_ld_flr ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", + hfsts1.fields.fw_init_complete ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", + hfsts1.fields.boot_options_present ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", + hfsts1.fields.update_in_progress ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: D0i3 Support : %s\n", + hfsts1.fields.d0i3_support_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n", + hfsts2.fields.low_power_state ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replaced : %s\n", + hfsts2.fields.cpu_replaced ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replacement Valid : %s\n", + hfsts2.fields.cpu_replaced_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Current Working State : %u\n", + hfsts1.fields.working_state); + printk(BIOS_DEBUG, "ME: Current Operation State : %u\n", + hfsts1.fields.operation_state); + printk(BIOS_DEBUG, "ME: Current Operation Mode : %u\n", + hfsts1.fields.operation_mode); + printk(BIOS_DEBUG, "ME: Error Code : %u\n", + hfsts1.fields.error_code); + printk(BIOS_DEBUG, "ME: CPU Debug Disabled : %s\n", + hfsts6.fields.cpu_debug_disable ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: TXT Support : %s\n", + hfsts6.fields.txt_support ? "YES" : "NO"); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, dump_me_status, NULL); From 8eaa5dc684f778dcfff73630c0d914162f0a243f Mon Sep 17 00:00:00 2001 From: John Su Date: Fri, 8 May 2020 17:29:48 +0800 Subject: [PATCH 126/405] mb/google/hatch: Add Mushu variant specific DPTF parameters The change applies the DPTF parameters received from thermal team. 1. Set PL1 Max to 25W 2. Set PL2 Max to 44W 3. Update Temp sensor parameters BUG=b:152011093 BRANCH=none TEST=build and verified by thermal team Signed-off-by: John Su Change-Id: I225897832b02f9de6221053b68fbdba30f8b199a Reviewed-on: https://review.coreboot.org/c/coreboot/+/41165 Reviewed-by: Shelley Chen Reviewed-by: Paul Menzel Reviewed-by: EricR Lai Tested-by: build bot (Jenkins) --- .../mushu/include/variant/acpi/dptf.asl | 134 +++++++++++++++++- .../hatch/variants/mushu/overridetree.cb | 3 + 2 files changed, 136 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl index fd3b5cfb4e..505a11f377 100644 --- a/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl @@ -1,3 +1,135 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ -#include +#define DPTF_CPU_PASSIVE 93 +#define DPTF_CPU_CRITICAL 99 +#define DPTF_CPU_ACTIVE_AC0 85 +#define DPTF_CPU_ACTIVE_AC1 70 +#define DPTF_CPU_ACTIVE_AC2 65 +#define DPTF_CPU_ACTIVE_AC3 60 +#define DPTF_CPU_ACTIVE_AC4 50 +#define DPTF_CPU_ACTIVE_AC5 40 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 90 +#define DPTF_TSR0_CRITICAL 99 +#define DPTF_TSR0_ACTIVE_AC0 80 +#define DPTF_TSR0_ACTIVE_AC1 70 +#define DPTF_TSR0_ACTIVE_AC2 65 +#define DPTF_TSR0_ACTIVE_AC3 60 +#define DPTF_TSR0_ACTIVE_AC4 55 +#define DPTF_TSR0_ACTIVE_AC5 50 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_PASSIVE 90 +#define DPTF_TSR1_CRITICAL 99 +#define DPTF_TSR1_ACTIVE_AC0 80 +#define DPTF_TSR1_ACTIVE_AC1 70 +#define DPTF_TSR1_ACTIVE_AC2 65 +#define DPTF_TSR1_ACTIVE_AC3 60 +#define DPTF_TSR1_ACTIVE_AC4 55 +#define DPTF_TSR1_ACTIVE_AC5 50 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "dGPU" +#define DPTF_TSR2_PASSIVE 93 +#define DPTF_TSR2_CRITICAL 99 +#define DPTF_TSR2_ACTIVE_AC0 85 +#define DPTF_TSR2_ACTIVE_AC1 70 +#define DPTF_TSR2_ACTIVE_AC2 65 +#define DPTF_TSR2_ACTIVE_AC3 60 +#define DPTF_TSR2_ACTIVE_AC4 50 +#define DPTF_TSR2_ACTIVE_AC5 40 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 77, 71, 68, 65, 59, 55, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 77, 71, 68, 65, 59, 55, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 77, 71, 68, 65, 59, 55, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 77, 71, 68, 65, 59, 55, 0, + 0, 0, 0 + } +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 10, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on TSR0 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 10, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on TSR1 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 10, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on dGPU (TSR2) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 10, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 15000, /* PowerLimitMinimum */ + 25000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 500 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 25000, /* PowerLimitMinimum */ + 44000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 500 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index 0c8cb5369e..7bd1fac4e8 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -24,6 +24,9 @@ chip soc/intel/cannonlake register "FastPkgCRampDisableGt" = "1" register "FastPkgCRampDisableSa" = "1" + register "tdp_pl1_override" = "25" + register "tdp_pl2_override" = "44" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | From 1fb15b0ac56644cfe095ebb94fcddaa2c92bd1c1 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 12 May 2020 10:50:46 +0200 Subject: [PATCH 127/405] mb/facebook/fbg1701: Remove direct 'include ' Don't directly include . All code using GPIO features should always and only include , which should indirectly include the SoC-specific . Change-Id: Id2663398b9f069ab1f60d63016ea7aa080f66d20 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41321 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Wim Vervoorn --- src/mainboard/facebook/fbg1701/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/facebook/fbg1701/gpio.c b/src/mainboard/facebook/fbg1701/gpio.c index dc4d3894d3..cb1d2cb86c 100644 --- a/src/mainboard/facebook/fbg1701/gpio.c +++ b/src/mainboard/facebook/fbg1701/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { From 71a9a7c70f152e054294495a37f2c02b6b77cd84 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 12 May 2020 10:52:19 +0200 Subject: [PATCH 128/405] mb/portwell/m107: Remove direct 'include ' Don't directly include . All code using GPIO features should always and only include , which should indirectly include the SoC-specific . Change-Id: I78f1e250570f1b395c61115d4a872b24b3d58f69 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41323 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Wim Vervoorn --- src/mainboard/portwell/m107/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/portwell/m107/gpio.c b/src/mainboard/portwell/m107/gpio.c index dc4d3894d3..cb1d2cb86c 100644 --- a/src/mainboard/portwell/m107/gpio.c +++ b/src/mainboard/portwell/m107/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { From fa42d568a00e5daadd35722790c529539227130e Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Fri, 8 May 2020 22:18:09 +0530 Subject: [PATCH 129/405] broadwell: update processor power limits configuration Update processor power limit configuration parameters based on common code base support for Intel Broadwell SoC based platforms. BRANCH=None BUG=None TEST=Build for broadwell based platform Change-Id: I97e38a533e74a122b6809e20a10f6e425827ab9c Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/41234 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/broadwell/Kconfig | 5 +- src/soc/intel/broadwell/acpi.c | 1 + src/soc/intel/broadwell/chip.h | 1 + src/soc/intel/broadwell/cpu.c | 143 +----------------- src/soc/intel/broadwell/include/soc/cpu.h | 4 - src/soc/intel/broadwell/include/soc/msr.h | 10 +- .../intel/broadwell/include/soc/soc_chip.h | 20 +++ src/soc/intel/broadwell/systemagent.c | 5 +- 8 files changed, 33 insertions(+), 156 deletions(-) create mode 100644 src/soc/intel/broadwell/include/soc/soc_chip.h diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 20219d3939..67f7563a92 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT + select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER @@ -34,10 +35,12 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select TSC_MONOTONIC_TIMER select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_CPU + select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select HAVE_SPI_CONSOLE_SUPPORT - select CPU_INTEL_COMMON select INTEL_GMA_ACPI select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 588eb0c336..316b85a1e5 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -24,6 +24,7 @@ #include #include #include +#include /* * List of supported C-states in this processor. Only the ULT parts support C8, diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 46d895f7ef..45f91d8aef 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -4,6 +4,7 @@ #define _SOC_INTEL_BROADWELL_CHIP_H_ #include +#include #include struct soc_intel_broadwell_config { diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index fb4fecbd3d..1923301aa2 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -25,64 +26,6 @@ #include #include -/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ -static const u8 power_limit_time_sec_to_msr[] = { - [0] = 0x00, - [1] = 0x0a, - [2] = 0x0b, - [3] = 0x4b, - [4] = 0x0c, - [5] = 0x2c, - [6] = 0x4c, - [7] = 0x6c, - [8] = 0x0d, - [10] = 0x2d, - [12] = 0x4d, - [14] = 0x6d, - [16] = 0x0e, - [20] = 0x2e, - [24] = 0x4e, - [28] = 0x6e, - [32] = 0x0f, - [40] = 0x2f, - [48] = 0x4f, - [56] = 0x6f, - [64] = 0x10, - [80] = 0x30, - [96] = 0x50, - [112] = 0x70, - [128] = 0x11, -}; - -/* Convert POWER_LIMIT_1_TIME MSR value to seconds */ -static const u8 power_limit_time_msr_to_sec[] = { - [0x00] = 0, - [0x0a] = 1, - [0x0b] = 2, - [0x4b] = 3, - [0x0c] = 4, - [0x2c] = 5, - [0x4c] = 6, - [0x6c] = 7, - [0x0d] = 8, - [0x2d] = 10, - [0x4d] = 12, - [0x6d] = 14, - [0x0e] = 16, - [0x2e] = 20, - [0x4e] = 24, - [0x6e] = 28, - [0x0f] = 32, - [0x2f] = 40, - [0x4f] = 48, - [0x6f] = 56, - [0x10] = 64, - [0x30] = 80, - [0x50] = 96, - [0x70] = 112, - [0x11] = 128, -}; - /* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly * when a core is woken up. */ @@ -288,90 +231,6 @@ static void configure_pch_power_sharing(void) RCBA32(PMSYNC_CONFIG2) = pmsync2; } -int cpu_config_tdp_levels(void) -{ - msr_t platform_info; - - /* Bits 34:33 indicate how many levels supported */ - platform_info = rdmsr(MSR_PLATFORM_INFO); - return (platform_info.hi >> 1) & 3; -} - -/* - * Configure processor power limits if possible - * This must be done AFTER set of BIOS_RESET_CPL - */ -void set_power_limits(u8 power_limit_1_time) -{ - msr_t msr = rdmsr(MSR_PLATFORM_INFO); - msr_t limit; - unsigned int power_unit; - unsigned int tdp, min_power, max_power, max_time; - u8 power_limit_1_val; - - if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) - power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; - - if (!(msr.lo & PLATFORM_INFO_SET_TDP)) - return; - - /* Get units */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 2 << ((msr.lo & 0xf) - 1); - - /* Get power defaults for this SKU */ - msr = rdmsr(MSR_PKG_POWER_SKU); - tdp = msr.lo & 0x7fff; - min_power = (msr.lo >> 16) & 0x7fff; - max_power = msr.hi & 0x7fff; - max_time = (msr.hi >> 16) & 0x7f; - - printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); - - if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) - power_limit_1_time = power_limit_time_msr_to_sec[max_time]; - - if (min_power > 0 && tdp < min_power) - tdp = min_power; - - if (max_power > 0 && tdp > max_power) - tdp = max_power; - - power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; - - /* Set long term power limit to TDP */ - limit.lo = 0; - limit.lo |= tdp & PKG_POWER_LIMIT_MASK; - limit.lo |= PKG_POWER_LIMIT_EN; - limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << - PKG_POWER_LIMIT_TIME_SHIFT; - - /* Set short term power limit to 1.25 * TDP */ - limit.hi = 0; - limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; - limit.hi |= PKG_POWER_LIMIT_EN; - /* Power limit 2 time is only programmable on server SKU */ - - wrmsr(MSR_PKG_POWER_LIMIT, limit); - - /* Set power limit values in MCHBAR as well */ - MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo; - MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi; - - /* Set DDR RAPL power limit by copying from MMIO to MSR */ - msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO); - msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI); - wrmsr(MSR_DDR_RAPL_LIMIT, msr); - - /* Use nominal TDP values for CPUs with configurable TDP */ - if (cpu_config_tdp_levels()) { - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - limit.hi = 0; - limit.lo = msr.lo & 0xff; - wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); - } -} - static void configure_c_states(void) { msr_t msr; diff --git a/src/soc/intel/broadwell/include/soc/cpu.h b/src/soc/intel/broadwell/include/soc/cpu.h index 02605851ce..9167736c00 100644 --- a/src/soc/intel/broadwell/include/soc/cpu.h +++ b/src/soc/intel/broadwell/include/soc/cpu.h @@ -37,10 +37,6 @@ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ (IRTL_1024_NS >> 10)) -/* Configure power limits for turbo mode */ -void set_power_limits(u8 power_limit_1_time); -int cpu_config_tdp_levels(void); - /* CPU identification */ u32 cpu_family_model(void); u32 cpu_stepping(void); diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index 250f0f8336..1e47b4429e 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -3,6 +3,8 @@ #ifndef _BROADWELL_MSR_H_ #define _BROADWELL_MSR_H_ +#include + #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_CORE_THREAD_COUNT 0x35 #define MSR_PLATFORM_INFO 0xce @@ -45,14 +47,6 @@ #define IRTL_RESPONSE_MASK (0x3ff) #define MSR_COUNTER_24_MHZ 0x637 -/* long duration in low dword, short duration in high dword */ -#define MSR_PKG_POWER_LIMIT 0x610 -#define PKG_POWER_LIMIT_MASK 0x7fff -#define PKG_POWER_LIMIT_EN (1 << 15) -#define PKG_POWER_LIMIT_CLAMP (1 << 16) -#define PKG_POWER_LIMIT_TIME_SHIFT 17 -#define PKG_POWER_LIMIT_TIME_MASK 0x7f - #define MSR_VR_CURRENT_CONFIG 0x601 #define MSR_VR_MISC_CONFIG 0x603 #define MSR_PKG_POWER_SKU_UNIT 0x606 diff --git a/src/soc/intel/broadwell/include/soc/soc_chip.h b/src/soc/intel/broadwell/include/soc/soc_chip.h new file mode 100644 index 0000000000..ff77168e0a --- /dev/null +++ b/src/soc/intel/broadwell/include/soc/soc_chip.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_BROADWELL_SOC_CHIP_H_ +#define _SOC_BROADWELL_SOC_CHIP_H_ + +#include "../../chip.h" + +#endif /* _SOC_BROADWELL_SOC_CHIP_H_ */ diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index d5d234d540..b75c4fe7de 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -404,6 +405,7 @@ static void systemagent_read_resources(struct device *dev) static void systemagent_init(struct device *dev) { + struct soc_power_limits_config *config; u8 bios_reset_cpl, pair; /* Enable Power Aware Interrupt Routing */ @@ -423,7 +425,8 @@ static void systemagent_init(struct device *dev) /* Configure turbo power limits 1ms after reset complete bit */ mdelay(1); - set_power_limits(28); + config = config_of_soc(); + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, config); } static struct device_operations systemagent_ops = { From 979e80dc47d4f6bd1c1333c79ef59706d6c9403b Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Fri, 15 May 2020 11:28:24 -0600 Subject: [PATCH 130/405] device/pci_device: Remove useless pci_bus_ops_pci The struct (formerly assigned to default_pci_ops_bus.ops_pci) only contained a NULL (well, 0) pointer for the set_subsystem callback, but usage of that callback is guarded with NULL checks when it is used, therefore it can be removed. TEST=still compiles Change-Id: I3943c8ae73b95e744a317264d7ceb8929cb28341 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/41432 Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/device/pci_device.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 05848717e2..689325d2a9 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -770,17 +770,12 @@ struct device_operations default_pci_ops_dev = { }; /** Default device operations for PCI bridges */ -static struct pci_operations pci_bus_ops_pci = { - .set_subsystem = 0, -}; - struct device_operations default_pci_ops_bus = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, .scan_bus = pci_scan_bridge, .reset_bus = pci_bus_reset, - .ops_pci = &pci_bus_ops_pci, }; /** From 68975b15cf51902d8dbd5b868b23011c9ee58ac9 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 15 May 2020 18:12:35 +0200 Subject: [PATCH 131/405] soc/amd/picasso: only link soc_util in ramstage No code that was or will be upstreamed uses functionality from soc_util in romstage, so only compile and link it for ramstage. This also allows to fix the SoC type detection in a follow-up patch using information that FPS-M will be providing in a HOB. BUG=b:153779573 Change-Id: If96e53608eadd562f6de5a0c370b89e84e43d049 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/41430 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Aaron Durbin --- src/soc/amd/picasso/Makefile.inc | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index e015fbe057..a82a227c15 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -29,7 +29,6 @@ romstage-$(CONFIG_PICASSO_UART) += uart.c romstage-y += tsc_freq.c romstage-y += southbridge.c romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c -romstage-y += soc_util.c romstage-y += psp.c romstage-y += mtrr.c romstage-y += config.c From f39dab1b953077ebcc3652bc126196cfaec2672c Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Wed, 13 May 2020 16:46:57 -0600 Subject: [PATCH 132/405] soc/amd/picasso: Switch to using amd_blobs BUG=b:147042464 TEST=build trembyle and boot to OS Signed-off-by: Raul E Rangel Change-Id: Ie6ac8b0701ac27733dd9724873664f5f17fcfa29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41435 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Furquan Shaikh --- src/soc/amd/picasso/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 4795211dc6..7173b6c06f 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -94,7 +94,7 @@ config VGA_BIOS_ID config VGA_BIOS_FILE string - default "3rdparty/blobs/soc/amd/picasso/PicassoGenericVbios.bin" + default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" config S3_VGA_ROM_RUN bool @@ -297,7 +297,7 @@ comment "AMD Firmware Directory Table set to location for 16MB ROM" config AMD_PUBKEY_FILE string - default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyRV.bin" + default "3rdparty/amd_blobs/picasso/PSP/AmdPubKeyRV.bin" config PSP_APCB_FILE string @@ -383,7 +383,7 @@ config HAVE_PSP_WHITELIST_FILE config PSP_WHITELIST_FILE string "Debug whitelist file name" depends on HAVE_PSP_WHITELIST_FILE - default "3rdparty/blobs/soc/amd/picasso/PSP/wtl-rvn.sbin" + default "3rdparty/amd_blobs/picasso/PSP/wtl-rvn.sbin" config PSP_UNLOCK_SECURE_DEBUG bool "Unlock secure debug" From 7f5f9331d1c8bc6012b4179018079e1b6aedc665 Mon Sep 17 00:00:00 2001 From: Philipp Bartsch Date: Fri, 15 May 2020 07:17:46 +0200 Subject: [PATCH 133/405] util/cbfstool: fix buffer over-read Fix unterminated array. When looking for a type not specified in filetypes (cbfs.h:204), the loop in lookup_name_by_type (cbfs_image.c:60) will run into a buffer over-read. Found-by: AFL++ 2.64d rev 1317433 Signed-off-by: Philipp Bartsch Change-Id: Ib82bb92e82b09fa1e26b9ca34529ec7b98e8f7b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41421 Reviewed-by: Julius Werner Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- util/cbfstool/cbfs.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index 421f0bc703..e58dfae009 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -210,7 +210,8 @@ static struct typedesc_t filetypes[] unused = { {CBFS_COMPONENT_EFI, "efi"}, {CBFS_COMPONENT_STRUCT, "struct"}, {CBFS_COMPONENT_DELETED, "deleted"}, - {CBFS_COMPONENT_NULL, "null"} + {CBFS_COMPONENT_NULL, "null"}, + {0, NULL} }; static const struct typedesc_t types_cbfs_hash[] unused = { From d7b9e363e3ec09eb5e2977d16085fdb3cd1334ce Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Wed, 13 May 2020 13:07:23 -0700 Subject: [PATCH 134/405] vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3163 Update FSP headers for Tiger Lake platform generated based FSP version 3163, which includes below additional UPDs: FSPM: TcssDma0En TcssDma1En FSPS: PchFivrExtV1p05RailEnabledStates PchFivrExtV1p05RailSupportedVoltageStates PchFivrExtVnnRailEnabledStates PchFivrExtVnnRailSupportedVoltageStates PchFivrExtVnnRailSxVoltage PchFivrExtV1p05RailIccMaximum CstateLatencyControl5TimeUnit VmdEnable BUG=none BRANCH=none TEST=build and boot ripto/volteer Signed-off-by: Srinidhi N Kaushik Change-Id: Icc893073629df59aef60162bed126d1f4b936e90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41377 Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) --- .../intel/fsp/fsp2_0/tigerlake/FspmUpd.h | 16 +- .../intel/fsp/fsp2_0/tigerlake/FspsUpd.h | 148 +++++++++++++----- 2 files changed, 126 insertions(+), 38 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index aa59bbf11d..ac56ad5644 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -777,9 +777,21 @@ typedef struct { **/ UINT8 TcssXdciEn; -/** Offset 0x05BC - Reserved +/** Offset 0x05BC - TCSS DMA0 Enable + Set TCSS DMA0. 0:Disabled 1:Enabled + $EN_DIS **/ - UINT8 Reserved29[4]; + UINT8 TcssDma0En; + +/** Offset 0x05BD - TCSS DMA1 Enable + Set TCSS DMA1. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssDma1En; + +/** Offset 0x05BE - Reserved +**/ + UINT8 Reserved29[2]; /** Offset 0x05C0 - Early Command Training Enables/Disable Early Command Training diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index 6b1217e63a..34f36898af 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -325,7 +325,45 @@ typedef struct { /** Offset 0x0370 - Reserved **/ - UINT8 Reserved10[73]; + UINT8 Reserved10[58]; + +/** Offset 0x03AA - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states + Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 +**/ + UINT8 PchFivrExtV1p05RailEnabledStates; + +/** Offset 0x03AB - Mask to enable the platform configuration of external V1p05 VR rail + External V1P05 Rail Supported Configuration +**/ + UINT8 PchFivrExtV1p05RailSupportedVoltageStates; + +/** Offset 0x03AC - Reserved +**/ + UINT8 Reserved11[3]; + +/** Offset 0x03AF - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states + Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 +**/ + UINT8 PchFivrExtVnnRailEnabledStates; + +/** Offset 0x03B0 - Mask to enable the platform configuration of external Vnn VR rail + External Vnn Rail Supported Configuration +**/ + UINT8 PchFivrExtVnnRailSupportedVoltageStates; + +/** Offset 0x03B1 - Reserved +**/ + UINT8 Reserved12[5]; + +/** Offset 0x03B6 - External Vnn Voltage Value that will be used in Sx states + Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments + (0=0mV, 1=2.5mV, 2=5mV...) +**/ + UINT16 PchFivrExtVnnRailSxVoltage; + +/** Offset 0x03B8 - Reserved +**/ + UINT8 Reserved13; /** Offset 0x03B9 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX @@ -341,7 +379,7 @@ typedef struct { /** Offset 0x03BB - Reserved **/ - UINT8 Reserved11; + UINT8 Reserved14; /** Offset 0x03BC - Transition time in microseconds from Off (0V) to High Current Mode Voltage This field has 1us resolution. When value is 0 Transition to 0V is disabled. @@ -350,7 +388,16 @@ typedef struct { /** Offset 0x03BE - Reserved **/ - UINT8 Reserved12[38]; + UINT8 Reserved15[20]; + +/** Offset 0x03D2 - External V1P05 Icc Max Value + Granularity of this setting is 1mA and maximal possible value is 500mA +**/ + UINT16 PchFivrExtV1p05RailIccMaximum; + +/** Offset 0x03D4 - Reserved +**/ + UINT8 Reserved16[16]; /** Offset 0x03E4 - CNVi Configuration This option allows for automatic detection of Connectivity Solution. [Auto Detection] @@ -373,7 +420,7 @@ typedef struct { /** Offset 0x03E7 - Reserved **/ - UINT8 Reserved13; + UINT8 Reserved17; /** Offset 0x03E8 - CNVi RF_RESET pin muxing Select CNVi RF_RESET# pin depending on board routing. TGP-LP: GPP_A8 = 0x2942E408(default) @@ -390,7 +437,7 @@ typedef struct { /** Offset 0x03F0 - Reserved **/ - UINT8 Reserved14[14]; + UINT8 Reserved18[14]; /** Offset 0x03FE - HECI3 state The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. @@ -401,7 +448,7 @@ typedef struct { /** Offset 0x03FF - Reserved **/ - UINT8 Reserved15[141]; + UINT8 Reserved19[141]; /** Offset 0x048C - CdClock Frequency selection 0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: @@ -426,7 +473,7 @@ typedef struct { /** Offset 0x048F - Reserved **/ - UINT8 Reserved16; + UINT8 Reserved20; /** Offset 0x0490 - TypeC port GPIO setting GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined @@ -437,7 +484,7 @@ typedef struct { /** Offset 0x04B0 - Reserved **/ - UINT8 Reserved17[8]; + UINT8 Reserved21[8]; /** Offset 0x04B8 - Enable D3 Cold in TCSS This policy will enable/disable D3 cold support in IOM @@ -447,7 +494,17 @@ typedef struct { /** Offset 0x04B9 - Reserved **/ - UINT8 Reserved18[21]; + UINT8 Reserved22[8]; + +/** Offset 0x04C1 - Enable VMD controller + Enable/disable to VMD controller.0: Disable(Default); 1: Enable + $EN_DIS +**/ + UINT8 VmdEnable; + +/** Offset 0x04C2 - Reserved +**/ + UINT8 Reserved23[12]; /** Offset 0x04CE - TCSS Aux Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides @@ -461,7 +518,7 @@ typedef struct { /** Offset 0x04D2 - Reserved **/ - UINT8 Reserved19[2]; + UINT8 Reserved24[2]; /** Offset 0x04D4 - ITBT Root Port Enable ITBT Root Port Enable, 0:Disable, 1:Enable @@ -471,7 +528,7 @@ typedef struct { /** Offset 0x04D8 - Reserved **/ - UINT8 Reserved20[11]; + UINT8 Reserved25[11]; /** Offset 0x04E3 - Enable/Disable PTM This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports @@ -481,7 +538,7 @@ typedef struct { /** Offset 0x04E7 - Reserved **/ - UINT8 Reserved21[194]; + UINT8 Reserved26[194]; /** Offset 0x05A9 - Skip Multi-Processor Initialization When this is skipped, boot loader must initialize processors before SilicionInit @@ -492,7 +549,7 @@ typedef struct { /** Offset 0x05AA - Reserved **/ - UINT8 Reserved22[10]; + UINT8 Reserved27[10]; /** Offset 0x05B4 - CpuMpPpi Optional pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. @@ -503,7 +560,7 @@ typedef struct { /** Offset 0x05B8 - Reserved **/ - UINT8 Reserved23[46]; + UINT8 Reserved28[46]; /** Offset 0x05E6 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. @@ -513,7 +570,7 @@ typedef struct { /** Offset 0x05E7 - Reserved **/ - UINT8 Reserved24[36]; + UINT8 Reserved29[36]; /** Offset 0x060B - Enable PCH ISH SPI Cs0 pins assigned Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. @@ -522,7 +579,7 @@ typedef struct { /** Offset 0x060C - Reserved **/ - UINT8 Reserved25[2]; + UINT8 Reserved30[2]; /** Offset 0x060E - Enable PCH ISH SPI pins assigned Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. @@ -546,7 +603,7 @@ typedef struct { /** Offset 0x061C - Reserved **/ - UINT8 Reserved26[2]; + UINT8 Reserved31[2]; /** Offset 0x061E - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region @@ -557,7 +614,7 @@ typedef struct { /** Offset 0x061F - Reserved **/ - UINT8 Reserved27[2]; + UINT8 Reserved32[2]; /** Offset 0x0621 - RTC Cmos Memory Lock Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper @@ -568,7 +625,7 @@ typedef struct { /** Offset 0x0622 - Reserved **/ - UINT8 Reserved28[24]; + UINT8 Reserved33[24]; /** Offset 0x063A - Enable PCIE RP Pm Sci Indicate whether the root port power manager SCI is enabled. @@ -577,7 +634,7 @@ typedef struct { /** Offset 0x0652 - Reserved **/ - UINT8 Reserved29[24]; + UINT8 Reserved34[24]; /** Offset 0x066A - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management. @@ -591,7 +648,7 @@ typedef struct { /** Offset 0x069A - Reserved **/ - UINT8 Reserved30[168]; + UINT8 Reserved35[168]; /** Offset 0x0742 - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. @@ -606,7 +663,7 @@ typedef struct { /** Offset 0x075B - Reserved **/ - UINT8 Reserved31[5]; + UINT8 Reserved36[5]; /** Offset 0x0760 - Touch Host Controller Port 1 Assignment Assign THC Port 1 @@ -616,7 +673,7 @@ typedef struct { /** Offset 0x0761 - Reserved **/ - UINT8 Reserved32[79]; + UINT8 Reserved37[79]; /** Offset 0x07B0 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is @@ -637,7 +694,7 @@ typedef struct { /** Offset 0x07F8 - Reserved **/ - UINT8 Reserved33[79]; + UINT8 Reserved38[79]; /** Offset 0x0847 - PCH Pm WoW lan Enable Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. @@ -660,7 +717,7 @@ typedef struct { /** Offset 0x084A - Reserved **/ - UINT8 Reserved34[16]; + UINT8 Reserved39[16]; /** Offset 0x085A - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. @@ -670,7 +727,7 @@ typedef struct { /** Offset 0x085B - Reserved **/ - UINT8 Reserved35[50]; + UINT8 Reserved40[50]; /** Offset 0x088D - Enable SATA Port DmVal DITO multiplier. Default is 15. @@ -679,7 +736,7 @@ typedef struct { /** Offset 0x0895 - Reserved **/ - UINT8 Reserved36; + UINT8 Reserved41; /** Offset 0x0896 - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. @@ -688,7 +745,7 @@ typedef struct { /** Offset 0x08A6 - Reserved **/ - UINT8 Reserved37[72]; + UINT8 Reserved42[72]; /** Offset 0x08EE - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. @@ -702,7 +759,7 @@ typedef struct { /** Offset 0x0908 - Reserved **/ - UINT8 Reserved38[16]; + UINT8 Reserved43[16]; /** Offset 0x0918 - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time @@ -722,7 +779,7 @@ typedef struct { /** Offset 0x091A - Reserved **/ - UINT8 Reserved39[3]; + UINT8 Reserved44[3]; /** Offset 0x091D - Hybrid Storage Detection and Configuration Mode Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. @@ -733,7 +790,16 @@ typedef struct { /** Offset 0x091E - Reserved **/ - UINT8 Reserved40[434]; + UINT8 Reserved45[96]; + +/** Offset 0x097E - USB2 Port Reset Message Enable + 0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message +**/ + UINT8 PortResetMessageEnable[16]; + +/** Offset 0x098E - Reserved +**/ + UINT8 Reserved46[322]; /** Offset 0x0AD0 - RpPtmBytes **/ @@ -741,7 +807,7 @@ typedef struct { /** Offset 0x0AD4 - Reserved **/ - UINT8 Reserved41[101]; + UINT8 Reserved47[101]; /** Offset 0x0B39 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, @@ -759,7 +825,17 @@ typedef struct { /** Offset 0x0B3A - Reserved **/ - UINT8 Reserved42[260]; + UINT8 Reserved48[80]; + +/** Offset 0x0B8A - TimeUnit for C-State Latency Control5 + TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns + , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns +**/ + UINT8 CstateLatencyControl5TimeUnit; + +/** Offset 0x0B8B - Reserved +**/ + UINT8 Reserved49[179]; /** Offset 0x0C3E - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. @@ -781,7 +857,7 @@ typedef struct { /** Offset 0x0C41 - Reserved **/ - UINT8 Reserved43; + UINT8 Reserved50; /** Offset 0x0C42 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. @@ -795,7 +871,7 @@ typedef struct { /** Offset 0x0CA2 - Reserved **/ - UINT8 Reserved44[269]; + UINT8 Reserved51[269]; /** Offset 0x0DAF - LpmStateEnableMask **/ @@ -803,7 +879,7 @@ typedef struct { /** Offset 0x0DB0 - Reserved **/ - UINT8 Reserved45[224]; + UINT8 Reserved52[224]; } FSP_S_CONFIG; /** Fsp S UPD Configuration From 7a05e6e2ad75dc1e28a50f3f309d8e7aecaf2526 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Wed, 13 May 2020 15:40:07 -0700 Subject: [PATCH 135/405] soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En This adds FSP UPD TcssDma0En and TcssDma1En for configuration. BUG=:b:146624360 TEST=Built and booted on Volteer. Signed-off-by: John Zhao Change-Id: I04af970f74ab9dfe84f9c0c09ec2098e0093fa57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41383 Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro --- src/soc/intel/tigerlake/chip.h | 6 +++++- src/soc/intel/tigerlake/include/soc/pci_devs.h | 16 +++++++++++++--- src/soc/intel/tigerlake/romstage/fsp_params.c | 6 +++++- 3 files changed, 23 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index c98fb667cc..3047037183 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -213,10 +213,14 @@ struct soc_intel_tigerlake_config { FORCE_ENABLE, } CnviBtAudioOffload; - /* Tcss */ + /* Tcss USB */ uint8_t TcssXhciEn; uint8_t TcssXdciEn; + /* Tcss DMA */ + uint8_t TcssDma0En; + uint8_t TcssDma1En; + /* * SOC Aux orientation override: * This is a bitfield that corresponds to up to 4 TCSS ports on TGL. diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index 683172f346..d76c4a105b 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -30,6 +30,10 @@ #define SA_DEVFN_DPTF PCI_DEVFN(SA_DEV_SLOT_DPTF, 0) #define SA_DEV_DPTF PCI_DEV(0, SA_DEV_SLOT_DPTF, 0) +#define SA_DEV_SLOT_IPU 0x05 +#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) +#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) + #define SA_DEV_SLOT_TBT 0x07 #define SA_DEVFN_TBT0 PCI_DEVFN(SA_DEV_SLOT_TBT, 0) #define SA_DEVFN_TBT1 PCI_DEVFN(SA_DEV_SLOT_TBT, 1) @@ -40,9 +44,15 @@ #define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) #define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) -#define SA_DEV_SLOT_IPU 0x05 -#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) -#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) +#define SA_DEV_SLOT_TCSS 0x0d +#define SA_DEVFN_TCSS_XHCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 0) +#define SA_DEVFN_TCSS_XDCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 1) +#define SA_DEVFN_TCSS_DMA0 PCI_DEVFN(SA_DEV_SLOT_TCSS, 2) +#define SA_DEVFN_TCSS_DMA1 PCI_DEVFN(SA_DEV_SLOT_TCSS, 3) +#define SA_DEV_TCSS_XHCI PCI_DEV(0, SA_DEV_SLOT_TCSS, 0) +#define SA_DEV_TCSS_XDCI PCI_DEV(0, SA_DEV_SLOT_TCSS, 1) +#define SA_DEV_TCSS_DMA0 PCI_DEV(0, SA_DEV_SLOT_TCSS, 2) +#define SA_DEV_TCSS_DMA1 PCI_DEV(0, SA_DEV_SLOT_TCSS, 3) /* PCH Devices */ #define PCH_DEV_SLOT_SIO0 0x10 diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index a444623fa5..ede5059a5e 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -111,10 +111,14 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Image clock: disable all clocks for bypassing FSP pin mux */ memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn)); - /* Tcss */ + /* Tcss USB */ m_cfg->TcssXhciEn = config->TcssXhciEn; m_cfg->TcssXdciEn = config->TcssXdciEn; + /* TCSS DMA */ + m_cfg->TcssDma0En = config->TcssDma0En; + m_cfg->TcssDma1En = config->TcssDma1En; + /* USB4/TBT */ dev = pcidev_path_on_root(SA_DEVFN_TBT0); if (dev) From cabcfe276c655ece78bec43ce238c2264d7e7823 Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Thu, 14 May 2020 10:24:24 +0800 Subject: [PATCH 136/405] libpayload: Fix definitions of minimum integer values Fix incorrectly defined constants INT16_MIN, INT32_MIN and INT64_MIN, which recursively call themselves. BRANCH=none BUG=none TEST=emerge-nami libpayload Change-Id: I1fa8402d318393de2e02f1e632ab78b6ec0768e8 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/41391 Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Reviewed-by: Hung-Te Lin Reviewed-by: Joel Kitching Tested-by: build bot (Jenkins) --- payloads/libpayload/include/stdint.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/include/stdint.h b/payloads/libpayload/include/stdint.h index 1b2b97e7c1..3cb494a7f6 100644 --- a/payloads/libpayload/include/stdint.h +++ b/payloads/libpayload/include/stdint.h @@ -45,9 +45,9 @@ typedef long ptrdiff_t; #define INT64_MAX (9223372036854775807LL) #define INT8_MIN (-INT8_MAX - 1) -#define INT16_MIN (-INT16_MIN - 1) -#define INT32_MIN (-INT32_MIN - 1) -#define INT64_MIN (-INT64_MIN - 1) +#define INT16_MIN (-INT16_MAX - 1) +#define INT32_MIN (-INT32_MAX - 1) +#define INT64_MIN (-INT64_MAX - 1) #define UINT8_MAX (255) #define UINT16_MAX (65535) From 02043c995b0a767854d0a04e5d17e7576895e8fb Mon Sep 17 00:00:00 2001 From: Bill XIE Date: Thu, 14 May 2020 16:28:37 +0800 Subject: [PATCH 137/405] 3rdparty/libgfxinit: Update submodule pointer, again 6b95507ec5b087658178a325bdc68570bc48bb20 has mistakenly reverted the submodule pointer of 3rdparty/libgfxinit to cdbfce27, canceling c844d14ca5081b2cb2f1036bdf0c2112405342d1. This commit sets it back, recovering c844d14c. Change-Id: Ib594e40a39ea83dd2238becb287f2516e7c54046 Signed-off-by: Bill XIE Reviewed-on: https://review.coreboot.org/c/coreboot/+/41400 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- 3rdparty/libgfxinit | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index cdbfce2757..2e87c0d40a 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit cdbfce275777f2fd142e3a3c73469807a4c40207 +Subproject commit 2e87c0d40a387c5b1f1afd3ce61ecdc7dad0e3e8 From 82fb12ccec969a2bcc75c930aaa6d903322fefe4 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 17 May 2020 16:41:22 +0200 Subject: [PATCH 138/405] mb/google/{parrot,stout}: Remove unused 'include ' Change-Id: I7c6f47f03f1c83658f4364f81f6436d7b2f4f377 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41486 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/parrot/smihandler.c | 1 - src/mainboard/google/stout/ec.c | 1 - 2 files changed, 2 deletions(-) diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index 1934625ae1..a71b2a30df 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include "ec.h" diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index f568116e17..d80e225609 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -9,7 +9,6 @@ #include #include #include -#include #include "ec.h" void stout_ec_init(void) From 5dd76fd4cc9028f6fc3ab973dda4719abe54da39 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 11 May 2020 20:36:31 +0200 Subject: [PATCH 139/405] src: Remove unused 'include ' Change-Id: Iad5540e791075270453a136a058823c28647f93a Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41245 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Wim Vervoorn --- src/arch/riscv/fit_payload.c | 1 - src/mainboard/facebook/monolith/ramstage.c | 1 - src/security/intel/stm/StmPlatformSmm.c | 1 - src/soc/intel/denverton_ns/memmap.c | 1 - 4 files changed, 4 deletions(-) diff --git a/src/arch/riscv/fit_payload.c b/src/arch/riscv/fit_payload.c index 32090889fd..2e676c799d 100644 --- a/src/arch/riscv/fit_payload.c +++ b/src/arch/riscv/fit_payload.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/facebook/monolith/ramstage.c b/src/mainboard/facebook/monolith/ramstage.c index c3c51a88c1..3ad0a174ec 100644 --- a/src/mainboard/facebook/monolith/ramstage.c +++ b/src/mainboard/facebook/monolith/ramstage.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c index 1f57b50f6d..1d21bf7af2 100644 --- a/src/security/intel/stm/StmPlatformSmm.c +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -9,7 +9,6 @@ #include #include -#include #include #include diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index 51b19ce575..f607d0f0df 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -10,7 +10,6 @@ #include #include #include -#include /* Returns base of requested region encoded in the system agent. */ static inline uintptr_t system_agent_region_base(size_t reg) From f836a234e211266d1feffd5f406a692ac0fba164 Mon Sep 17 00:00:00 2001 From: Rob Barnes Date: Fri, 27 Mar 2020 01:13:21 -0600 Subject: [PATCH 140/405] util/apcb: Add apcb_edit tool On the Picasso architecture, the PSP is responsible for setting up DRAM before releasing the x86. The APCB (AGESA PSP Configuration Block) contains multiple SPDs and the GPIO numbers used to select the correct SPD. Since the source to build the APCBs is not public, it can't be built as part of the coreboot build. To work around this problem, we use a template APCB and inject the relevant information. BUG=b:147042464 Signed-off-by: Rob Barnes Change-Id: I88a09743f8e8a184c47071ee5e417f5b6bdb7467 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2123799 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41380 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Furquan Shaikh --- util/apcb/README | 3 + util/apcb/apcb_edit.py | 185 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 188 insertions(+) create mode 100644 util/apcb/README create mode 100755 util/apcb/apcb_edit.py diff --git a/util/apcb/README b/util/apcb/README new file mode 100644 index 0000000000..a765f4d9bd --- /dev/null +++ b/util/apcb/README @@ -0,0 +1,3 @@ +The necessary tools for building APCBs are not available for use by coreboot. +This tool allows patching an existing APCB binary with specific SPDs +and GPIO selection pins. diff --git a/util/apcb/apcb_edit.py b/util/apcb/apcb_edit.py new file mode 100755 index 0000000000..4a7e683ebe --- /dev/null +++ b/util/apcb/apcb_edit.py @@ -0,0 +1,185 @@ +#! /usr/bin/env python + +# Script for editing APCB binaries, such as injecting SPDs and GPIO +# configurations. + +import sys +import re +import argparse +from collections import namedtuple +from struct import * + +GPIO_MAGIC = bytes.fromhex('fadeddad' * 3) +SPD_MAGIC = bytes.fromhex('f005ba110000') +EMPTY_SPD = b'\x00' * 512 + +spd_ssp_struct_fmt = '??B?IIBBBxIIBBBx' +spd_ssp_struct = namedtuple( + 'spd_ssp_struct', 'SpdValid, DimmPresent, \ + PageAddress, NvDimmPresent, \ + DramManufacturersIDCode, Address, \ + SpdMuxPresent, MuxI2CAddress, MuxChannel, \ + Technology, Package, SocketNumber, \ + ChannelNumber, DimmNumber') + + +def parseargs(): + parser = argparse.ArgumentParser(description='Inject SPDs and SPD GPIO \ + selection pins into APCB binaries') + parser.add_argument( + 'apcb_in', + nargs='?', + type=argparse.FileType('rb'), + default=sys.stdin, + help='APCB input file') + parser.add_argument( + 'apcb_out', + nargs='?', + type=argparse.FileType('wb'), + default=sys.stdout, + help='APCB output file') + parser.add_argument( + '--spd_0_0', + type=argparse.FileType('r'), + help='SPD input file for channel 0, dimm 0') + parser.add_argument( + '--spd_0_1', + type=argparse.FileType('r'), + help='SPD input file for channel 0, dimm 1') + parser.add_argument( + '--spd_1_0', + type=argparse.FileType('r'), + help='SPD input file for channel 1, dimm 0') + parser.add_argument( + '--spd_1_1', + type=argparse.FileType('r'), + help='SPD input file for channel 1, dimm 1') + parser.add_argument( + '--hex', + action='store_true', + help='SPD input file is hex encoded, binary otherwise') + parser.add_argument( + '--board_id_gpio0', + type=int, + required=True, + nargs=3, + help='Board ID GPIO 0: NUMBER IO_MUX BANK_CTRL') + parser.add_argument( + '--board_id_gpio1', + type=int, + required=True, + nargs=3, + help='Board ID GPIO 1: NUMBER IO_MUX BANK_CTRL') + parser.add_argument( + '--board_id_gpio2', + type=int, + required=True, + nargs=3, + help='Board ID GPIO 2: NUMBER IO_MUX BANK_CTRL') + parser.add_argument( + '--board_id_gpio3', + type=int, + required=True, + nargs=3, + help='Board ID GPIO 3: NUMBER IO_MUX BANK_CTRL') + return parser.parse_args() + + +def chksum(data): + sum = 0 + for b in data[:16] + data[17:]: + sum = (sum + b) & 0xff + return (0x100 - sum) & 0xff + + +def inject(orig, insert, offset): + return b''.join([orig[:offset], insert, orig[offset + len(insert):]]) + + +def main(): + args = parseargs() + + print("Reading input APCB from %s\n" % (args.apcb_in.name)) + + apcb = args.apcb_in.read() + + orig_apcb_len = len(apcb) + + gpio_offset = apcb.find(GPIO_MAGIC) + assert gpio_offset > 0, "GPIO magic number not found" + print('GPIO magic number found at offset 0x%x\n' % gpio_offset) + gpio_array = (args.board_id_gpio0 + args.board_id_gpio1 + + args.board_id_gpio2 + args.board_id_gpio3) + print('Writing SPD GPIO array %s\n' % gpio_array) + apcb = inject(apcb, pack('BBBBBBBBBBBB', *gpio_array), gpio_offset) + + spd_offset = 0 + while True: + spd_offset = apcb.find(SPD_MAGIC, spd_offset) + if spd_offset < 0: + break + + spd_ssp_offset = spd_offset - calcsize(spd_ssp_struct_fmt) + spd_ssp_bytes = apcb[spd_ssp_offset:spd_offset] + spd_ssp = spd_ssp_struct._make( + unpack(spd_ssp_struct_fmt, spd_ssp_bytes)) + + assert spd_ssp.DimmNumber >= 0 and spd_ssp.DimmNumber <= 1, \ + "Unexpected dimm number found in APCB" + assert spd_ssp.ChannelNumber >= 0 and spd_ssp.ChannelNumber <= 1, \ + "Unexpected channel number found in APCB" + + print("Found SPD magic number with channel %d and dimm %d " + "at offset 0x%x\n" % (spd_ssp.ChannelNumber, spd_ssp.DimmNumber, + spd_offset)) + + dimm_channel = (spd_ssp.ChannelNumber, spd_ssp.DimmNumber) + spd = None + if dimm_channel == (0, 0) and args.spd_0_0: + spd = args.spd_0_0.read() + elif dimm_channel == (0, 1) and args.spd_0_1: + spd = args.spd_0_1.read() + elif dimm_channel == (1, 0) and args.spd_1_0: + spd = args.spd_1_0.read() + elif dimm_channel == (1, 1) and args.spd_1_1: + spd = args.spd_1_0.read() + + if spd: + if args.hex: + spd = re.sub(r'#.*', '', spd) + spd = re.sub(r'\s+', '', spd) + spd = bytes.fromhex(spd) + else: + spd = spd.encode() + + assert len(spd) == 512, \ + "Expected SPD to be 512 bytes, got %d" % len(spd) + + print("Enabling channel %d, dimm %d and injecting SPD\n" % + (spd_ssp.ChannelNumber, spd_ssp.DimmNumber)) + spd_ssp = spd_ssp._replace(SpdValid=True, DimmPresent=True) + + else: + print("Disabling channel %d, dimm %d and clearing SPD\n" % + (spd_ssp.ChannelNumber, spd_ssp.DimmNumber)) + spd_ssp = spd_ssp._replace(SpdValid=False, DimmPresent=False) + spd = EMPTY_SPD + + apcb = inject(apcb, pack(spd_ssp_struct_fmt, *spd_ssp), spd_ssp_offset) + apcb = inject(apcb, spd, spd_offset) + + spd_offset += 512 + + print("Fixing checksum and writing to %s\n" % (args.apcb_out.name)) + + apcb = inject(apcb, bytes([chksum(apcb)]), 16) + + assert chksum(apcb) == apcb[16], "Checksum is invalid" + assert orig_apcb_len == len(apcb), \ + "The size of the APCB binary changed, this should not happen." + + args.apcb_out.write(apcb) + + +if __name__ == "__main__": + main() From cbaa835f211eb04ba6eb5e9c3c0095534e93a100 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Wed, 13 May 2020 14:01:09 -0600 Subject: [PATCH 141/405] soc/amd/picasso/Makefile: Use apcb_tool to generate APCBs from SPDs BUG=b:147042464 TEST=Boot trembyle to OS Signed-off-by: Rob Barnes Signed-off-by: Raul E Rangel Change-Id: Ife48d5268230f70c6a6f4a56c1f0d05b6c924891 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41381 Reviewed-by: Furquan Shaikh Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- Documentation/soc/amd/family17h.md | 45 +++++++++++++++++++ src/soc/amd/picasso/Kconfig | 30 ------------- src/soc/amd/picasso/Makefile.inc | 72 +++++++++++++++++++++--------- 3 files changed, 97 insertions(+), 50 deletions(-) diff --git a/Documentation/soc/amd/family17h.md b/Documentation/soc/amd/family17h.md index b917c94526..23088cd12b 100755 --- a/Documentation/soc/amd/family17h.md +++ b/Documentation/soc/amd/family17h.md @@ -237,6 +237,51 @@ Picasso's FSP is compatible with rev. 2.0 of the External Architecture Specification. Deviations, e.g., no FSP-T support, shall be published in an Integration Guide. +## APCB setup + +APCBs are used to provide the PSP with SPD information and optionally a set of +GPIOs to use for selecting which SPD to load. + +### Prebuilt +The picasso `Makefile` expects APCBs to be located in +`3rdparty/blobs/mainboard/$(MAINBOARDDIR)`. If you have a pre-built binary just +add the following to your mainboard's Makefile. + +``` +# i.e., 3rdparty/blobs/mainboard/amd/mandolin/APCB_mandolin.bin +APCB_SOURCES = mandolin +``` + +### Generating APCBs +If you have a template APCB file, the `apcb_edit` tool can be used to inject the +SPD and GPIOs used to select the correct slot. Entries should match this +pattern `{NAME}_x{1,2}`. There should be a matching SPD hex file in +`SPD_SOURCES_DIR` matching the pattern `{NAME}.spd.hex`. +The `_x{1,2}` suffix denotes single or dual channel. Up to 16 slots can be used. +If a slot is empty, the special empty keyword can be used. This will generate +an APCB with an empty SPD. + +``` +APCB_SOURCES = hynix-HMA851S6CJR6N-VK_x1 # 0b0000 +APCB_SOURCES += hynix-HMAA1GS6CMR6N-VK_x2 # 0b0001 +APCB_SOURCES += empty # 0b0010 +APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0011 +``` + +#### APCB Board ID GPIO configuration. +The GPIOs determine which memory SPD will be used during boot. +``` +# APCB_BOARD_ID_GPIO[0-3] = GPIO_NUMBER GPIO_IO_MUX GPIO_BANK_CTL +# GPIO_NUMBER: FCH GPIO number +# GPIO_IO_MUX: Value write to IOMUX to configure this GPIO +# GPIO_BANK_CTL: Value write to GPIOBankCtl[23:16] to configure this GPIO + +APCB_BOARD_ID_GPIO0 = 121 1 0 +APCB_BOARD_ID_GPIO1 = 120 1 0 +APCB_BOARD_ID_GPIO2 = 131 3 0 +APCB_BOARD_ID_GPIO3 = 116 1 0 +``` + ## Footnotes 1. *AMD Platform Security Processor BIOS Architecture Design Guide diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 7173b6c06f..48e1cc2e6b 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -299,36 +299,6 @@ config AMD_PUBKEY_FILE string default "3rdparty/amd_blobs/picasso/PSP/AmdPubKeyRV.bin" -config PSP_APCB_FILE - string - help - The name of the AGESA Parameter Customization Block. This image is - instance ID 0 in the PSP's BIOS Directory Table. - -config PSP_APCB1_FILE - string - help - If specified, this image is instance ID 1 in the PSP's BIOS - Directory Table. - -config PSP_APCB2_FILE - string - help - If specified, this image is instance ID 2 in the PSP's BIOS - Directory Table. - -config PSP_APCB3_FILE - string - help - If specified, this image is instance ID 3 in the PSP's BIOS - Directory Table. - -config PSP_APCB4_FILE - string - help - If specified, this image is instance ID 4 in the PSP's BIOS - Directory Table. - config PSP_APOB_DESTINATION hex default 0x9f00000 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index a82a227c15..6fc834e56b 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -78,6 +78,8 @@ CPPFLAGS_common += -I$(src)/soc/amd/picasso/include CPPFLAGS_common += -I$(src)/soc/amd/picasso/acpi CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/picasso +MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR) + # ROMSIG Normally At ROMBASE + 0x20000 # Overridden by CONFIG_AMD_FWM_POSITION_INDEX # +-----------+---------------+----------------+------------+ @@ -175,11 +177,7 @@ endif # # type = 0x60 -PSP_APCB0_FILE=$(call strip_quotes, $(CONFIG_PSP_APCB_FILE)) -PSP_APCB1_FILE=$(call strip_quotes, $(CONFIG_PSP_APCB1_FILE)) -PSP_APCB2_FILE=$(call strip_quotes, $(CONFIG_PSP_APCB2_FILE)) -PSP_APCB3_FILE=$(call strip_quotes, $(CONFIG_PSP_APCB3_FILE)) -PSP_APCB4_FILE=$(call strip_quotes, $(CONFIG_PSP_APCB4_FILE)) +PSP_APCB_FILES=$(foreach f, $(APCB_SOURCES), $(obj)/APCB_$(f).bin) # type = 0x61 PSP_APOB_BASE=$(CONFIG_PSP_APOB_DESTINATION) @@ -257,11 +255,10 @@ OPT_ABL6_FILE=$(call add_opt_prefix, $(PSP_ABL6_FILE), --abl-image) OPT_ABL7_FILE=$(call add_opt_prefix, $(PSP_ABL7_FILE), --abl-image) OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) -OPT_PSP_APCB0_FILE=$(call add_opt_prefix, $(PSP_APCB0_FILE), --instance 0 --apcb) -OPT_PSP_APCB1_FILE=$(call add_opt_prefix, $(PSP_APCB1_FILE), --instance 1 --apcb) -OPT_PSP_APCB2_FILE=$(call add_opt_prefix, $(PSP_APCB2_FILE), --instance 2 --apcb) -OPT_PSP_APCB3_FILE=$(call add_opt_prefix, $(PSP_APCB3_FILE), --instance 3 --apcb) -OPT_PSP_APCB4_FILE=$(call add_opt_prefix, $(PSP_APCB4_FILE), --instance 4 --apcb) +OPT_PSP_APCB_FILES=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \ + $(call add_opt_prefix, $(word $(i), $(PSP_APCB_FILES)), \ + --instance $(shell printf "%x" $$(($(i)-1))) --apcb )) + OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) @@ -281,15 +278,53 @@ OPT_PSP_UCODE_FILE2=$(call add_opt_prefix, $(PSP_UCODE_FILE2), --instance 1 --uc OPT_PSP_UCODE_FILE3=$(call add_opt_prefix, $(PSP_UCODE_FILE3), --instance 2 --ucode) OPT_MP2CFG_FILE=$(call add_opt_prefix, $(PSP_MP2CFG_FILE), --mp2-config) +# Copy prebuild APCBs if they exist +$(obj)/APCB_%.bin: $(MAINBOARD_BLOBS_DIR)/APCB_%.bin + cp $< $@ + +# APCB binary with magic numbers to be replaced by apcb_edit tool +APCB_MAGIC_BLOB:=$(MAINBOARD_BLOBS_DIR)/APCB_magic.bin + +$(obj)/APCB_empty.bin: $(APCB_MAGIC_BLOB) $(APCB_EDIT_TOOL) + $(APCB_EDIT_TOOL) \ + $(APCB_MAGIC_BLOB) \ + $@ \ + --board_id_gpio0 $(APCB_BOARD_ID_GPIO0) \ + --board_id_gpio1 $(APCB_BOARD_ID_GPIO1) \ + --board_id_gpio2 $(APCB_BOARD_ID_GPIO2) \ + --board_id_gpio3 $(APCB_BOARD_ID_GPIO3) + +$(obj)/APCB_%_x1.bin: $$(SPD_SOURCES_DIR)/%.spd.hex \ + $(APCB_EDIT_TOOL) \ + $(APCB_MAGIC_BLOB) + $(APCB_EDIT_TOOL) \ + $(APCB_MAGIC_BLOB) \ + $@ \ + --hex \ + --spd_0_0 $< \ + --board_id_gpio0 $(APCB_BOARD_ID_GPIO0) \ + --board_id_gpio1 $(APCB_BOARD_ID_GPIO1) \ + --board_id_gpio2 $(APCB_BOARD_ID_GPIO2) \ + --board_id_gpio3 $(APCB_BOARD_ID_GPIO3) + +$(obj)/APCB_%_x2.bin: $$(SPD_SOURCES_DIR)/%.spd.hex \ + $(APCB_EDIT_TOOL) \ + $(APCB_MAGIC_BLOB) + $(APCB_EDIT_TOOL) \ + $(APCB_MAGIC_BLOB) \ + $@ \ + --hex \ + --spd_0_0 $< \ + --spd_1_0 $< \ + --board_id_gpio0 $(APCB_BOARD_ID_GPIO0) \ + --board_id_gpio1 $(APCB_BOARD_ID_GPIO1) \ + --board_id_gpio2 $(APCB_BOARD_ID_GPIO2) \ + --board_id_gpio3 $(APCB_BOARD_ID_GPIO3) + $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PSPBTLDR_FILE)) \ $(call strip_quotes, $(PSPSCUREOS_FILE)) \ $(call strip_quotes, $(PSP_SEC_DBG_KEY_FILE)) \ - $(call strip_quotes, $(PSP_APCB0_FILE)) \ - $(call strip_quotes, $(PSP_APCB1_FILE)) \ - $(call strip_quotes, $(PSP_APCB2_FILE)) \ - $(call strip_quotes, $(PSP_APCB3_FILE)) \ - $(call strip_quotes, $(PSP_APCB4_FILE)) \ $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ $(call strip_quotes, $(PSP_PMUI_FILE1)) \ $(call strip_quotes, $(PSP_PMUI_FILE2)) \ @@ -322,6 +357,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call_strip_quotes, $(PSP_S0I3_FILE)) \ $(call_strip_quotes, $(PSP_IKEK_FILE)) \ $(call_strip_quotes, $(PSP_SEC_DEBUG_FILE)) \ + $$(PSP_APCB_FILES) \ $(AMDFWTOOL) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" @@ -334,11 +370,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(OPT_SMUFW2_SUB2_FILE) \ $(OPT_SMUFW1_SUB1_FILE) \ $(OPT_SMUFW2_SUB1_FILE) \ - $(OPT_PSP_APCB0_FILE) \ - $(OPT_PSP_APCB1_FILE) \ - $(OPT_PSP_APCB2_FILE) \ - $(OPT_PSP_APCB3_FILE) \ - $(OPT_PSP_APCB4_FILE) \ + $(OPT_PSP_APCB_FILES) \ $(OPT_APOB_ADDR) \ $(OPT_APOBNV_ADDR) \ $(OPT_APOBNV_SIZE) \ From f769ee3e1b060ff94f8f087a810fb2c83e4e99fe Mon Sep 17 00:00:00 2001 From: Bill XIE Date: Thu, 14 May 2020 17:25:37 +0800 Subject: [PATCH 142/405] mb/lenovo/{x230, t430s}: add H8_HAS_PRIMARY_FN_KEYS for {x230s, t431s} X230s and T431s have keyboard similar to the one found on t440p, so H8_HAS_PRIMARY_FN_KEYS and related cmos options may apply to them. Tested on both X230s and T431s. Change-Id: I234820b92093acdd64ff60cae39015547b6e981e Signed-off-by: Bill XIE Reviewed-on: https://review.coreboot.org/c/coreboot/+/41403 Reviewed-by: Alexander Couzens Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/t430s/Kconfig | 1 + src/mainboard/lenovo/t430s/cmos.default | 1 + src/mainboard/lenovo/t430s/cmos.layout | 1 + src/mainboard/lenovo/x230/Kconfig | 1 + src/mainboard/lenovo/x230/cmos.default | 1 + src/mainboard/lenovo/x230/cmos.layout | 1 + 6 files changed, 6 insertions(+) diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index 15b0912d44..81b87c8ba0 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS select EC_LENOVO_PMH7 select EC_LENOVO_H8 select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_PRIMARY_FN_KEYS if BOARD_LENOVO_T431S select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default index 3e1f130ce4..a30c90dc1f 100644 --- a/src/mainboard/lenovo/t430s/cmos.default +++ b/src/mainboard/lenovo/t430s/cmos.default @@ -15,3 +15,4 @@ trackpoint=Enable backlight=Both enable_dual_graphics=Disable usb_always_on=Disable +f1_to_f12_as_primary=Enable diff --git a/src/mainboard/lenovo/t430s/cmos.layout b/src/mainboard/lenovo/t430s/cmos.layout index 451bf7daf0..1697806aa3 100644 --- a/src/mainboard/lenovo/t430s/cmos.layout +++ b/src/mainboard/lenovo/t430s/cmos.layout @@ -56,6 +56,7 @@ entries 419 2 e 12 usb_always_on 421 1 e 9 sata_mode 422 2 e 10 backlight +424 1 e 1 f1_to_f12_as_primary # coreboot config options: cpu #424 8 r 0 unused diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 454b589b76..577136d103 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS select EC_LENOVO_PMH7 select EC_LENOVO_H8 select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_HAS_PRIMARY_FN_KEYS if BOARD_LENOVO_X230S select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_12288 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T select BOARD_ROMSIZE_KB_16384 if BOARD_LENOVO_X230S diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default index 979f132863..5c19d0f4a5 100644 --- a/src/mainboard/lenovo/x230/cmos.default +++ b/src/mainboard/lenovo/x230/cmos.default @@ -14,3 +14,4 @@ sticky_fn=Disable trackpoint=Enable backlight=Both usb_always_on=Disable +f1_to_f12_as_primary=Enable diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout index 314e4de089..6a6cdd537b 100644 --- a/src/mainboard/lenovo/x230/cmos.layout +++ b/src/mainboard/lenovo/x230/cmos.layout @@ -56,6 +56,7 @@ entries 419 2 e 12 usb_always_on 421 1 e 9 sata_mode 422 2 e 10 backlight +424 1 e 1 f1_to_f12_as_primary # coreboot config options: cpu #424 8 r 0 unused From b74f45e9c4ae7bb504986298df8da89b6f017e65 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 11 May 2020 19:59:14 +0200 Subject: [PATCH 143/405] src: Remove unused 'include ' Unused includes found using following commande: diff <(git grep -l '#include ' -- src/) <(git grep -l 'memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|atol\|strrchr\|skip_atoi\|STRINGIFY' -- src/) |grep -v vendorcode |grep '<' Change-Id: Ibaeec213b6019dfa9c45e3424b38af0e094d0c51 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41242 Tested-by: build bot (Jenkins) Reviewed-by: Wim Vervoorn --- src/arch/x86/bootblock_normal.c | 1 - src/drivers/pc80/rtc/mc146818rtc.c | 1 - src/drivers/spi/adesto.c | 1 - src/drivers/spi/amic.c | 1 - src/drivers/spi/atmel.c | 1 - src/drivers/spi/eon.c | 1 - src/drivers/spi/gigadevice.c | 1 - src/drivers/spi/macronix.c | 1 - src/drivers/spi/spansion.c | 1 - src/drivers/spi/sst.c | 1 - src/drivers/spi/stmicro.c | 1 - src/drivers/spi/winbond.c | 1 - src/mainboard/asus/p5ql-em/acpi_tables.c | 1 - src/mainboard/google/dedede/board_info.c | 1 - src/mainboard/google/kukui/panel_anx7625.c | 1 - src/mainboard/google/octopus/mainboard.c | 1 - src/mainboard/intel/tglrvp/romstage_fsp_params.c | 1 - src/mainboard/lenovo/t400/acpi_tables.c | 1 - src/mainboard/lenovo/x200/acpi_tables.c | 1 - src/mainboard/roda/rk9/acpi_tables.c | 1 - src/security/tpm/tspi/tspi.c | 1 - src/security/vboot/secdata_tpm.c | 1 - src/soc/intel/cannonlake/bootblock/report_platform.c | 1 - src/soc/intel/common/block/cse/cse_lite.c | 1 - src/soc/intel/common/block/cse/disable_heci.c | 1 - src/soc/intel/common/block/smbus/smbuslib.c | 1 - src/soc/qualcomm/sc7180/qupv3_i2c.c | 1 - 27 files changed, 27 deletions(-) diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c index 1fb3692ddb..3fbdbec2cd 100644 --- a/src/arch/x86/bootblock_normal.c +++ b/src/arch/x86/bootblock_normal.c @@ -4,7 +4,6 @@ #include #include #include -#include static const char *get_fallback(const char *stagelist) { diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 832d4fda2f..79bb5eb34a 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c index 1006de730a..6538905681 100644 --- a/src/drivers/spi/adesto.c +++ b/src/drivers/spi/adesto.c @@ -7,7 +7,6 @@ #include #include -#include #include #include diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c index 2929e85b8a..5e74616c88 100644 --- a/src/drivers/spi/amic.c +++ b/src/drivers/spi/amic.c @@ -4,7 +4,6 @@ #include #include #include -#include #include "spi_flash_internal.h" diff --git a/src/drivers/spi/atmel.c b/src/drivers/spi/atmel.c index 448f9062bd..4dcc5b5bcf 100644 --- a/src/drivers/spi/atmel.c +++ b/src/drivers/spi/atmel.c @@ -4,7 +4,6 @@ #include #include #include -#include #include "spi_flash_internal.h" diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index 6db2cd1f49..1212c6b607 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -4,7 +4,6 @@ #include #include #include -#include #include "spi_flash_internal.h" diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index d1ab1a698a..6c5a167dee 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -4,7 +4,6 @@ #include #include #include -#include #include "spi_flash_internal.h" diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index 9f918341b7..f3f7e2d24b 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -4,7 +4,6 @@ #include #include #include -#include #include "spi_flash_internal.h" diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index fe55fe4652..fe0e265cd9 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -4,7 +4,6 @@ #include #include #include -#include #include "spi_flash_internal.h" diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 2d107dcee5..887380fdeb 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -8,7 +8,6 @@ #include #include #include -#include #include "spi_flash_internal.h" diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index 3477789942..4cd8c1b9a3 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -4,7 +4,6 @@ #include #include #include -#include #include "spi_flash_internal.h" diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index c2b81f5388..d8d3cdc855 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/asus/p5ql-em/acpi_tables.c b/src/mainboard/asus/p5ql-em/acpi_tables.c index abb544e9a9..b65ca71789 100644 --- a/src/mainboard/asus/p5ql-em/acpi_tables.c +++ b/src/mainboard/asus/p5ql-em/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include diff --git a/src/mainboard/google/dedede/board_info.c b/src/mainboard/google/dedede/board_info.c index 38d722c16c..3289cb4ecf 100644 --- a/src/mainboard/google/dedede/board_info.c +++ b/src/mainboard/google/dedede/board_info.c @@ -4,7 +4,6 @@ #include #include #include -#include int board_info_get_fw_config(uint32_t *fw_config) { diff --git a/src/mainboard/google/kukui/panel_anx7625.c b/src/mainboard/google/kukui/panel_anx7625.c index 5685661445..cae9edc041 100644 --- a/src/mainboard/google/kukui/panel_anx7625.c +++ b/src/mainboard/google/kukui/panel_anx7625.c @@ -6,7 +6,6 @@ #include #include #include -#include #include "panel.h" diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index b7f45f6d40..e6dbd0330b 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c index bf223824fc..d4433a1d66 100644 --- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/lenovo/t400/acpi_tables.c b/src/mainboard/lenovo/t400/acpi_tables.c index 98eddc5660..91cf2c37ed 100644 --- a/src/mainboard/lenovo/t400/acpi_tables.c +++ b/src/mainboard/lenovo/t400/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/lenovo/x200/acpi_tables.c b/src/mainboard/lenovo/x200/acpi_tables.c index 98eddc5660..91cf2c37ed 100644 --- a/src/mainboard/lenovo/x200/acpi_tables.c +++ b/src/mainboard/lenovo/x200/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/roda/rk9/acpi_tables.c b/src/mainboard/roda/rk9/acpi_tables.c index 82b257628c..7cc2468b05 100644 --- a/src/mainboard/roda/rk9/acpi_tables.c +++ b/src/mainboard/roda/rk9/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 144e3c31a0..6ef01383ce 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 6a4dc712e2..d350b38262 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -7,7 +7,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index fe52de1d95..b29cf7dd9e 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -11,7 +11,6 @@ #include #include #include -#include #define BIOS_SIGN_ID 0x8B diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 9e154f453b..b985a94628 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -4,7 +4,6 @@ #include #include #include -#include /* Converts bp index to boot partition string */ #define GET_BP_STR(bp_index) (bp_index ? "RW" : "RO") diff --git a/src/soc/intel/common/block/cse/disable_heci.c b/src/soc/intel/common/block/cse/disable_heci.c index e27783a6a7..664a2f7b30 100644 --- a/src/soc/intel/common/block/cse/disable_heci.c +++ b/src/soc/intel/common/block/cse/disable_heci.c @@ -10,7 +10,6 @@ #include #include #include -#include #define CSME0_FBE 0xf #define CSME0_BAR 0x0 diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c index a1a88180f2..8f337c1c1d 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.c +++ b/src/soc/intel/common/block/smbus/smbuslib.c @@ -4,7 +4,6 @@ #include #include #include -#include #include "smbuslib.h" static void update_spd_len(struct spd_block *blk) diff --git a/src/soc/qualcomm/sc7180/qupv3_i2c.c b/src/soc/qualcomm/sc7180/qupv3_i2c.c index 7dea694060..b80c3dfcbb 100644 --- a/src/soc/qualcomm/sc7180/qupv3_i2c.c +++ b/src/soc/qualcomm/sc7180/qupv3_i2c.c @@ -10,7 +10,6 @@ #include #include #include -#include static void i2c_clk_configure(unsigned int bus, enum i2c_speed speed) { From 15fd30f0407f64684c975405888534dbd4be5ebf Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 16 May 2020 00:52:31 +0200 Subject: [PATCH 144/405] soc/amd/picasso/romstage: add missing types.h include Change-Id: I26f15e7bd2f65e94ed1c2771bd8504114bfcda48 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/41446 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/picasso/romstage.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index a9ee5a5b12..f038456b29 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "chip.h" #include From ed03371e76239dae16b6397efef4814f8c30451e Mon Sep 17 00:00:00 2001 From: Chris Wang Date: Fri, 14 Feb 2020 18:24:54 +0800 Subject: [PATCH 145/405] soc/amd/picasso: add telemetry setting Add telemetry setting for SDLE testing BUG=b:147570294 TEST=Build Morphius and check the setting was been applied Signed-off-by: Chris Wang Signed-off-by: Felix Held Change-Id: If4bb75eeaaa68b2c5a6a36c28c34fb338be65851 Reviewed-on: https://chromium-review.googlesource.com/2056885 Reviewed-by: Martin Roth Reviewed-by: Matt Papageorge Tested-by: Martin Roth Reviewed-on: https://review.coreboot.org/c/coreboot/+/41447 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Angel Pons --- src/soc/amd/picasso/chip.h | 4 ++++ src/soc/amd/picasso/romstage.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 8d4e0d3875..80cb1ceab2 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -72,6 +72,10 @@ struct soc_amd_picasso_config { uint8_t core_dldo_bypass; uint8_t min_soc_vid_offset; uint8_t aclk_dpm0_freq_400MHz; + uint32_t telemetry_vddcr_vdd_slope; + uint32_t telemetry_vddcr_vdd_offset; + uint32_t telemetry_vddcr_soc_slope; + uint32_t telemetry_vddcr_soc_offset; enum { SD_EMMC_DISABLE, diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index f038456b29..e6bc5c9c8f 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -74,6 +74,10 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->core_dldo_bypass = config->core_dldo_bypass; mcfg->min_soc_vid_offset = config->min_soc_vid_offset; mcfg->aclk_dpm0_freq_400MHz = config->aclk_dpm0_freq_400MHz; + mcfg->telemetry_vddcr_vdd_slope = config->telemetry_vddcr_vdd_slope; + mcfg->telemetry_vddcr_vdd_offset = config->telemetry_vddcr_vdd_offset; + mcfg->telemetry_vddcr_soc_slope = config->telemetry_vddcr_soc_slope; + mcfg->telemetry_vddcr_soc_offset = config->telemetry_vddcr_soc_offset; } asmlinkage void car_stage_entry(void) From 21744811bb7638830a7ca495694d295acbadc150 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 4 May 2020 17:44:04 -0700 Subject: [PATCH 146/405] tests: Add wrapper header and fix --gc-sections requires a few standard headers to be explicitly included before itself or it will throw compilation errors. Having to always include these headers in the right order in every test is cumbersome. Instead, this patch encapsulates the problem in a new header that all tests should include (instead of directly). Also fix --gc-sections in the test framework which needs to be passed for linking, not for compiling. Signed-off-by: Julius Werner Change-Id: I4284d74c8673708e21a5266eb42f7b9ae19a1b12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41045 Tested-by: build bot (Jenkins) Reviewed-by: Jan Dabros Reviewed-by: Paul Fagerburg --- tests/Makefile.inc | 13 +++++++------ tests/device/i2c-test.c | 8 ++------ tests/include/tests/test.h | 18 ++++++++++++++++++ tests/lib/string-test.c | 6 +----- 4 files changed, 28 insertions(+), 17 deletions(-) create mode 100644 tests/include/tests/test.h diff --git a/tests/Makefile.inc b/tests/Makefile.inc index debb2f9868..9ee27cd831 100644 --- a/tests/Makefile.inc +++ b/tests/Makefile.inc @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only +testsrc = $(top)/tests testobj = $(obj)/tests TEST_DEFAULT_CONFIG = $(top)/configs/config.emulation_qemu_x86_i440fx @@ -10,12 +11,12 @@ TEST_KCONFIG_DEPENDENCIES := $(testobj)/auto.conf.cmd TEST_KCONFIG_SPLITCONFIG := $(testobj)/config TEST_KCONFIG_TRISTATE := $(testobj)/tristate.conf -TEST_CFLAGS = -include$(src)/include/kconfig.h \ - -include$(src)/commonlib/bsd/include/commonlib/bsd/compiler.h \ - -include $(src)/include/rules.h \ +TEST_CFLAGS = -include $(src)/include/kconfig.h \ + -include $(src)/commonlib/bsd/include/commonlib/bsd/compiler.h \ + -include $(src)/include/rules.h # Include generic test mock headers, before original ones -TEST_CFLAGS += -Itests/include/mocks +TEST_CFLAGS += -I$(testsrc)/include/mocks -I$(testsrc)/include TEST_CFLAGS += -I$(src)/include -I$(src)/commonlib/include \ -I$(src)/commonlib/bsd/include -I$(src)/arch/x86/include \ @@ -24,10 +25,10 @@ TEST_CFLAGS += -I$(src)/include -I$(src)/commonlib/include \ TEST_CFLAGS += -I$(dir $(TEST_KCONFIG_AUTOHEADER)) TEST_CFLAGS += -std=gnu11 -Os -ffunction-sections -fdata-sections \ - -Wl,--gc-sections -fno-builtin + -fno-builtin # Link against Cmocka -TEST_LDFLAGS = -lcmocka +TEST_LDFLAGS = -lcmocka -Wl,--gc-sections # Extra attributes for unit tests, declared per test attributes:= srcs cflags mocks stage diff --git a/tests/device/i2c-test.c b/tests/device/i2c-test.c index 9303456261..acf7b0741d 100644 --- a/tests/device/i2c-test.c +++ b/tests/device/i2c-test.c @@ -1,12 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include -#include -#include -#include -#include - #include +#include +#include /* Simulate two i2c devices, both on bus 0, each with three uint8_t regs implemented. */ diff --git a/tests/include/tests/test.h b/tests/include/tests/test.h new file mode 100644 index 0000000000..b4e0dd2b5e --- /dev/null +++ b/tests/include/tests/test.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef _TESTS_TEST_H +#define _TESTS_TEST_H + +/* + * Standard test header that should be included in all tests. For now it just encapsulates the + * include dependencies for Cmocka. Test-specific APIs that are so generic we would want them + * available everywhere could also be added here. + */ + +#include +#include +#include +#include + +#endif /* _TESTS_TEST_H */ diff --git a/tests/lib/string-test.c b/tests/lib/string-test.c index 513b395283..08f4177ef6 100644 --- a/tests/lib/string-test.c +++ b/tests/lib/string-test.c @@ -1,11 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include -#include -#include -#include - #include +#include /* * Important note: In every particular test, don't use any string-related From 254003740674a72ac794c984200666517109adb8 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 4 May 2020 17:46:31 -0700 Subject: [PATCH 147/405] tests: Add region-test for rdev API This patch adds a basic test for the common region and region_device APIs, sanity checking the basic functions and things like overflow-handling. There is certainly more that could be added here, but it's a start. Signed-off-by: Julius Werner Change-Id: I4932402f54768557e5b22b16e66220bd90ddebfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/41046 Reviewed-by: Aaron Durbin Reviewed-by: Jan Dabros Tested-by: build bot (Jenkins) --- tests/Makefile.inc | 3 +- tests/commonlib/Makefile.inc | 7 + tests/commonlib/region-test.c | 404 ++++++++++++++++++++++++++++++++++ 3 files changed, 412 insertions(+), 2 deletions(-) create mode 100644 tests/commonlib/Makefile.inc create mode 100644 tests/commonlib/region-test.c diff --git a/tests/Makefile.inc b/tests/Makefile.inc index 9ee27cd831..be32434e83 100644 --- a/tests/Makefile.inc +++ b/tests/Makefile.inc @@ -24,8 +24,7 @@ TEST_CFLAGS += -I$(src)/include -I$(src)/commonlib/include \ # Path for Kconfig autoheader TEST_CFLAGS += -I$(dir $(TEST_KCONFIG_AUTOHEADER)) -TEST_CFLAGS += -std=gnu11 -Os -ffunction-sections -fdata-sections \ - -fno-builtin +TEST_CFLAGS += -std=gnu11 -Os -ffunction-sections -fdata-sections -fno-builtin # Link against Cmocka TEST_LDFLAGS = -lcmocka -Wl,--gc-sections diff --git a/tests/commonlib/Makefile.inc b/tests/commonlib/Makefile.inc new file mode 100644 index 0000000000..ce3499cb2b --- /dev/null +++ b/tests/commonlib/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. + +tests-y += region-test + +region-test-srcs += tests/commonlib/region-test.c +region-test-srcs += src/commonlib/region.c diff --git a/tests/commonlib/region-test.c b/tests/commonlib/region-test.c new file mode 100644 index 0000000000..2c960e099a --- /dev/null +++ b/tests/commonlib/region-test.c @@ -0,0 +1,404 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include + +/* We'd like to test overflow conditions, but for tests size_t is dependent on the HOSTCC + architecture. We use this to normalize the available address space to [VAL(0x0):VAL(0xf)). */ +#define VAL(v) ((size_t)(v##ULL << (sizeof(size_t) * 8 - 4))) + +static void test_region(void **state) +{ + /* Self-test: make sure VAL() overflow works as intended. */ + assert_true(VAL(5) + VAL(10) > VAL(10)); + assert_true(VAL(7) + VAL(10) < VAL(10)); + + struct region outer = { .offset = VAL(2), .size = VAL(4) }; + assert_int_equal(region_offset(&outer), VAL(2)); + assert_int_equal(region_sz(&outer), VAL(4)); + assert_int_equal(region_end(&outer), VAL(6)); + + struct region inner = { .offset = VAL(3), .size = VAL(2) }; + assert_true(region_is_subregion(&outer, &inner)); + + struct region touching_bottom = { .offset = VAL(2), .size = VAL(1) }; + assert_true(region_is_subregion(&outer, &touching_bottom)); + + struct region touching_top = { .offset = VAL(5), .size = VAL(1) }; + assert_true(region_is_subregion(&outer, &touching_top)); + + struct region overlap_bottom = { .offset = VAL(1), .size = VAL(2) }; + assert_false(region_is_subregion(&outer, &overlap_bottom)); + + struct region overlap_top = { .offset = VAL(5), .size = VAL(2) }; + assert_false(region_is_subregion(&outer, &overlap_top)); + + struct region below = { .offset = 0, .size = VAL(1) }; + assert_false(region_is_subregion(&outer, &below)); + + struct region above = { .offset = VAL(0xf), .size = VAL(1) }; + assert_false(region_is_subregion(&outer, &above)); +} + +static void *mock_mmap(const struct region_device *rdev, size_t offset, size_t size) +{ + check_expected_ptr(rdev); + check_expected(offset); + check_expected(size); + + return mock_ptr_type(void *); +} + +static int mock_unmap(const struct region_device *rdev, void *mapping) +{ + check_expected_ptr(rdev); + check_expected_ptr(mapping); + + return mock(); +} + +static ssize_t mock_readat(const struct region_device *rdev, void *buffer, + size_t offset, size_t size) +{ + check_expected_ptr(rdev); + check_expected_ptr(buffer); + check_expected(offset); + check_expected(size); + + ssize_t ret = mock(); + if (!ret) + return size; +} + +static ssize_t mock_writeat(const struct region_device *rdev, const void *buffer, + size_t offset, size_t size) +{ + check_expected_ptr(rdev); + check_expected_ptr(buffer); + check_expected(offset); + check_expected(size); + + ssize_t ret = mock(); + if (!ret) + return size; +} + +static ssize_t mock_eraseat(const struct region_device *rdev, size_t offset, size_t size) +{ + check_expected_ptr(rdev); + check_expected(offset); + check_expected(size); + + ssize_t ret = mock(); + if (!ret) + return size; +} + +struct region_device_ops mock_rdev_ops = { + .mmap = mock_mmap, + .munmap = mock_unmap, + .readat = mock_readat, + .writeat = mock_writeat, + .eraseat = mock_eraseat, +}; + +struct region_device mock_rdev = REGION_DEV_INIT(&mock_rdev_ops, 0, ~(size_t)0); +void *mmap_result = (void *)0x12345678; +const size_t mock_size = 256; +u8 mock_buffer[256]; + +static void test_rdev_basics(void **state) +{ + assert_int_equal(region_device_offset(&mock_rdev), 0); + assert_int_equal(region_device_sz(&mock_rdev), ~(size_t)0); + assert_int_equal(region_device_end(&mock_rdev), ~(size_t)0); +} + +/* + * This function sets up defaults for the mock_rdev_ops functions so we don't have to explicitly + * mock every parameter every time. cmocka doesn't really work well for this sort of use case + * and won't let you override these anymore once they're set (because these are stored as + * queues, not stacks, and once you store an "infinite" element the test can never proceed + * behind it), so tests will always have to enqueue any custom values they may need for the rest + * of the test function before calling this. + */ +static void rdev_mock_defaults(void) +{ + will_return_maybe(mock_mmap, mmap_result); + will_return_maybe(mock_unmap, 0); + will_return_maybe(mock_readat, 0); + will_return_maybe(mock_writeat, 0); + will_return_maybe(mock_eraseat, 0); + + expect_value_count(mock_mmap, rdev, &mock_rdev, -2); + expect_value_count(mock_unmap, rdev, &mock_rdev, -2); + expect_value_count(mock_readat, rdev, &mock_rdev, -2); + expect_value_count(mock_writeat, rdev, &mock_rdev, -2); + expect_value_count(mock_eraseat, rdev, &mock_rdev, -2); + + expect_value_count(mock_readat, buffer, &mock_buffer, -2); + expect_value_count(mock_writeat, buffer, &mock_buffer, -2); + + expect_value_count(mock_mmap, offset, 0, -2); + expect_value_count(mock_readat, offset, 0, -2); + expect_value_count(mock_writeat, offset, 0, -2); + expect_value_count(mock_eraseat, offset, 0, -2); + + expect_value_count(mock_mmap, size, mock_size, -2); + expect_value_count(mock_readat, size, mock_size, -2); + expect_value_count(mock_writeat, size, mock_size, -2); + expect_value_count(mock_eraseat, size, mock_size, -2); + + expect_value_count(mock_unmap, mapping, mmap_result, -2); +} + +static void test_rdev_success(void **state) +{ + struct region_device child; + + expect_value(mock_mmap, size, region_device_sz(&mock_rdev)); + + rdev_mock_defaults(); + + assert_ptr_equal(rdev_mmap_full(&mock_rdev), mmap_result); + + assert_ptr_equal(rdev_mmap(&mock_rdev, 0, mock_size), mmap_result); + assert_int_equal(rdev_munmap(&mock_rdev, mmap_result), 0); + assert_int_equal(rdev_readat(&mock_rdev, mock_buffer, 0, mock_size), mock_size); + assert_int_equal(rdev_writeat(&mock_rdev, mock_buffer, 0, mock_size), mock_size); + assert_int_equal(rdev_eraseat(&mock_rdev, 0, mock_size), mock_size); +} + +static void test_rdev_failure(void **state) +{ + will_return(mock_mmap, NULL); + will_return(mock_unmap, -1); + will_return(mock_readat, -1); + will_return(mock_writeat, -1); + will_return(mock_eraseat, -1); + + rdev_mock_defaults(); + + assert_null(rdev_mmap(&mock_rdev, 0, mock_size)); + assert_int_equal(rdev_munmap(&mock_rdev, mmap_result), -1); + assert_int_equal(rdev_readat(&mock_rdev, mock_buffer, 0, mock_size), -1); + assert_int_equal(rdev_writeat(&mock_rdev, mock_buffer, 0, mock_size), -1); + assert_int_equal(rdev_eraseat(&mock_rdev, 0, mock_size), -1); +} + +static void test_rdev_wrap(void **state) +{ + struct region_device child; + const size_t offs = VAL(0xf); + const size_t wrap_size = VAL(2); + /* Known API limitation -- can't exactly touch address space limit from below. */ + const size_t fit_size = VAL(1) - 1; + + /* For the 'wrap' cases, the underlying rdev_ops aren't even called, so only add + expectations for the 'fit' cases. */ + expect_value(mock_mmap, offset, offs); + expect_value(mock_readat, offset, offs); + expect_value(mock_writeat, offset, offs); + expect_value(mock_eraseat, offset, offs); + + expect_value(mock_mmap, size, fit_size); + expect_value(mock_readat, size, fit_size); + expect_value(mock_writeat, size, fit_size); + expect_value(mock_eraseat, size, fit_size); + + rdev_mock_defaults(); + + /* Accesses to regions that wrap around the end of the address space should fail. */ + assert_null(rdev_mmap(&mock_rdev, offs, wrap_size)); + assert_int_equal(rdev_readat(&mock_rdev, mock_buffer, offs, wrap_size), -1); + assert_int_equal(rdev_writeat(&mock_rdev, mock_buffer, offs, wrap_size), -1); + assert_int_equal(rdev_eraseat(&mock_rdev, offs, wrap_size), -1); + assert_int_equal(rdev_chain(&child, &mock_rdev, offs, wrap_size), -1); + + /* Just barely touching the end of the address space (and the rdev) should be fine. */ + assert_ptr_equal(rdev_mmap(&mock_rdev, offs, fit_size), mmap_result); + assert_int_equal(rdev_readat(&mock_rdev, mock_buffer, offs, fit_size), fit_size); + assert_int_equal(rdev_writeat(&mock_rdev, mock_buffer, offs, fit_size), fit_size); + assert_int_equal(rdev_eraseat(&mock_rdev, offs, fit_size), fit_size); + assert_int_equal(rdev_chain(&child, &mock_rdev, offs, fit_size), 0); +} + +static void test_rdev_chain(void **state) +{ + struct region_device child; + const size_t child_offs = VAL(2); + const size_t child_size = VAL(4); + const size_t offs = VAL(1); + const size_t ovrflw_size = child_size - offs + 1; + + /* The mock_size test is the only one that will go through to underlying rdev_ops. */ + expect_value(mock_mmap, offset, child_offs + offs); + expect_value(mock_readat, offset, child_offs + offs); + expect_value(mock_writeat, offset, child_offs + offs); + expect_value(mock_eraseat, offset, child_offs + offs); + + rdev_mock_defaults(); + + /* First a quick test for rdev_chain_full(). */ + assert_int_equal(rdev_chain_full(&child, &mock_rdev), 0); + assert_int_equal(region_device_sz(&child), region_device_sz(&mock_rdev)); + assert_int_equal(region_device_offset(&child), region_device_offset(&mock_rdev)); + assert_int_equal(rdev_relative_offset(&mock_rdev, &child), 0); + + /* Remaining tests use rdev chained to [child_offs:child_size) subregion. */ + assert_int_equal(rdev_chain(&child, &mock_rdev, child_offs, child_size), 0); + assert_int_equal(region_device_sz(&child), child_size); + assert_int_equal(region_device_offset(&child), child_offs); + assert_int_equal(region_device_end(&child), child_offs + child_size); + assert_int_equal(rdev_relative_offset(&mock_rdev, &child), child_offs); + assert_int_equal(rdev_relative_offset(&child, &mock_rdev), -1); + + /* offs + mock_size < child_size, so will succeed. */ + assert_ptr_equal(rdev_mmap(&child, offs, mock_size), mmap_result); + assert_int_equal(rdev_munmap(&child, mmap_result), 0); + assert_int_equal(rdev_readat(&child, mock_buffer, offs, mock_size), mock_size); + assert_int_equal(rdev_writeat(&child, mock_buffer, offs, mock_size), mock_size); + assert_int_equal(rdev_eraseat(&child, offs, mock_size), mock_size); + + /* offs + ovrflw_size > child_size, so will fail. */ + assert_null(rdev_mmap(&child, offs, ovrflw_size)); + assert_int_equal(rdev_readat(&child, mock_buffer, offs, ovrflw_size), -1); + assert_int_equal(rdev_writeat(&child, mock_buffer, offs, ovrflw_size), -1); + assert_int_equal(rdev_eraseat(&child, offs, ovrflw_size), -1); + + /* Using child_size as offset, the start of the area will already be out of range. */ + assert_null(rdev_mmap(&child, child_size, mock_size)); + assert_int_equal(rdev_readat(&child, mock_buffer, child_size, mock_size), -1); + assert_int_equal(rdev_writeat(&child, mock_buffer, child_size, mock_size), -1); + assert_int_equal(rdev_eraseat(&child, child_size, mock_size), -1); +} + +static void test_rdev_double_chain(void **state) +{ + struct region_device first, second; + const size_t first_offs = VAL(2); + const size_t first_size = VAL(6); + const size_t second_offs = VAL(2); + const size_t second_size = VAL(2); + const size_t offs = VAL(1); + const size_t ovrflw_size = second_size - offs + 1; + + /* The mock_size test is the only one that will go through to underlying rdev_ops. */ + expect_value(mock_mmap, offset, first_offs + second_offs + offs); + expect_value(mock_readat, offset, first_offs + second_offs + offs); + expect_value(mock_writeat, offset, first_offs + second_offs + offs); + expect_value(mock_eraseat, offset, first_offs + second_offs + offs); + + rdev_mock_defaults(); + + /* First, chain an rdev to root over [first_offs:first_size). */ + assert_int_equal(rdev_chain(&first, &mock_rdev, first_offs, first_size), 0); + + /* Trying to chain a second to first beyond its end should fail. */ + assert_int_equal(rdev_chain(&second, &first, second_offs, first_size), -1); + + /* Chain second to first at [second_offs:second_size). */ + assert_int_equal(rdev_chain(&second, &first, second_offs, second_size), 0); + assert_int_equal(rdev_relative_offset(&first, &second), second_offs); + assert_int_equal(rdev_relative_offset(&mock_rdev, &second), first_offs + second_offs); + + /* offs + mock_size < second_size, so will succeed. */ + assert_ptr_equal(rdev_mmap(&second, offs, mock_size), mmap_result); + assert_int_equal(rdev_munmap(&second, mmap_result), 0); + assert_int_equal(rdev_readat(&second, mock_buffer, offs, mock_size), mock_size); + assert_int_equal(rdev_writeat(&second, mock_buffer, offs, mock_size), mock_size); + assert_int_equal(rdev_eraseat(&second, offs, mock_size), mock_size); + + /* offs + ovrflw_size > second_size, so will fail. */ + assert_null(rdev_mmap(&second, offs, ovrflw_size)); + assert_int_equal(rdev_readat(&second, mock_buffer, offs, ovrflw_size), -1); + assert_int_equal(rdev_writeat(&second, mock_buffer, offs, ovrflw_size), -1); + assert_int_equal(rdev_eraseat(&second, offs, ovrflw_size), -1); + + /* offs + second_size + offs way out of range. */ + assert_null(rdev_mmap(&second, second_size + offs, mock_size)); + assert_int_equal(rdev_readat(&second, mock_buffer, second_size + offs, mock_size), -1); + assert_int_equal(rdev_writeat(&second, mock_buffer, second_size + offs, mock_size), -1); + assert_int_equal(rdev_eraseat(&second, second_size + offs, mock_size), -1); +} + +static void test_mem_rdev(void **state) +{ + const size_t size = 256; + u8 backing[size]; + u8 scratch[size]; + int i; + struct mem_region_device mem = MEM_REGION_DEV_RW_INIT(backing, size); + + /* Test writing to and reading from full mapping. */ + memset(backing, 0xa5, size); + u8 *mapping = rdev_mmap_full(&mem.rdev); + assert_non_null(mapping); + for (i = 0; i < size; i++) + assert_int_equal(mapping[i], 0xa5); + memset(mapping, 0x5a, size); + for (i = 0; i < size; i++) + assert_int_equal(backing[i], 0x5a); + assert_int_equal(rdev_munmap(&mem.rdev, mapping), 0); + + /* Test read/write/erase of single bytes. */ + for (i = 0; i < size; i++) { + u8 val = i + 0xaa; + scratch[0] = val; + assert_int_equal(rdev_writeat(&mem.rdev, &scratch, i, 1), 1); + assert_int_equal(backing[i], val); + assert_int_equal(scratch[0], val); + val = i + 0x55; + backing[i] = val; + assert_int_equal(rdev_readat(&mem.rdev, &scratch, i, 1), 1); + assert_int_equal(scratch[0], val); + assert_int_equal(backing[i], val); + assert_int_equal(rdev_eraseat(&mem.rdev, i, 1), 1); + assert_int_equal(backing[i], 0); + } + + /* Test read/write/erase of larger chunk. */ + size_t offs = 0x47; + size_t chunk = 0x72; + memset(backing, 0, size); + memset(scratch, 0, size); + memset(scratch + offs, 0x39, chunk); + assert_int_equal(rdev_writeat(&mem.rdev, scratch + offs, offs, chunk), chunk); + assert_memory_equal(backing, scratch, size); + memset(backing, 0, size); + assert_int_equal(rdev_readat(&mem.rdev, scratch + offs, offs, chunk), chunk); + assert_memory_equal(backing, scratch, size); + memset(scratch + offs + 1, 0, chunk - 1); + assert_int_equal(rdev_eraseat(&mem.rdev, offs + 1, chunk - 1), chunk - 1); + assert_memory_equal(backing, scratch, size); + + /* Test mapping of larger chunk. */ + memset(backing, 0, size); + mapping = rdev_mmap(&mem.rdev, offs, chunk); + assert_non_null(mapping); + memset(scratch, 0x93, size); + memcpy(mapping, scratch, chunk); + memset(scratch, 0, size); + memset(scratch + offs, 0x93, chunk); + assert_memory_equal(backing, scratch, size); + assert_int_equal(rdev_munmap(&mem.rdev, mapping), 0); + assert_memory_equal(backing, scratch, size); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(test_region), + cmocka_unit_test(test_rdev_basics), + cmocka_unit_test(test_rdev_success), + cmocka_unit_test(test_rdev_failure), + cmocka_unit_test(test_rdev_wrap), + cmocka_unit_test(test_rdev_chain), + cmocka_unit_test(test_rdev_double_chain), + cmocka_unit_test(test_mem_rdev), + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} From fb6606b8dbf9711c86872e75ce472a98ffe1ba2d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 1 May 2020 22:41:13 +0200 Subject: [PATCH 148/405] nb/intel/sandybridge: Correct IOSAV register notes The IOSAV register descriptions are plagued with errors and nonsense. Using `git blame` to find the culprit... Zoinks! Turns out it was me! Rewrite the comment so that the difference between a sub-sequence and a command is clear. Also, expand the descriptions that could be ambiguous and fix some insane blunders. CKE and ODT fields are per DIMM and rank! As per review comments, also invert the order of bitfield value ranges. Change-Id: Ie384304c565f962fe58baa231c15109eb3d284aa Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40952 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Paul Menzel --- .../intel/sandybridge/mchbar_regs.h | 136 +++++++++++------- 1 file changed, 83 insertions(+), 53 deletions(-) diff --git a/src/northbridge/intel/sandybridge/mchbar_regs.h b/src/northbridge/intel/sandybridge/mchbar_regs.h index 9867e807a6..ba0f7d5952 100644 --- a/src/northbridge/intel/sandybridge/mchbar_regs.h +++ b/src/northbridge/intel/sandybridge/mchbar_regs.h @@ -4,75 +4,100 @@ #define __SANDYBRIDGE_MCHBAR_REGS_H__ /* - * ### IOSAV command queue notes ### + * ### IOSAV memory controller interface poking state machine notes ### * - * Intel provides a command queue of depth four. - * Every command is configured by using multiple MCHBAR registers. - * On executing the command queue, you have to specify its depth (number of commands). + * IOSAV brings batch processing to memory training algorithms. * - * The macros for these registers can take some integer parameters, within these bounds: - * channel: [0..1] - * index: [0..3] - * lane: [0..8] + * The hardware is capable of executing a sequence of DRAM commands, + * which can be composed of up to four sub-sequences. * - * Note that these ranges are 'closed': both endpoints are included. + * A sub-sequence (from now on, subseq) consists of executing the same + * DRAM command for a configurable number of times, with adjustable + * delay between the commands, as well as an address auto-increment + * value, which is added after a given number of command executions. + * + * There are four groups of registers in MCHBAR, one for each subseq. + * When firing up IOSAV, one needs to specify the number of subseqs it + * should use. + * + * The macros for these registers can take some integer parameters. + * Valid values are: + * channel: 0..1 or 3 to broadcast to all channels. + * index: 0..3 + * lane: 0..8 + * + * These ranges are inclusive: both upper and lower bounds are valid. * * * - * ### Register description ### + * ### Register descriptions ### * * IOSAV_n_SP_CMD_ADDR_ch(channel, index) - * Sub-sequence command addresses. Controls the address, bank address and slotrank signals. + * Configures the row/column, bank and rank addresses. When a subseq + * begins to execute, the address fields define the address of the + * first command in the subseq. The address is updated after each + * command as configured in the "IOSAV_n_ADDR_UPDATE" registers, + * and the updated address is then written back into this register. * * Bitfields: - * [0..15] Row / Column Address. - * [16..18] The result of (10 + [16..18]) is the number of valid row bits. - * Note: Value 1 is not implemented. Not that it really matters, though. - * Value 7 is reserved, as the hardware does not support it. - * [20..22] Bank Address. - * [24..25] Rank select. Let's call it "ranksel", as it is mentioned later. + * [15..0] Row / Column Address. Defines the ADDR pins when + * issuing a DRAM command. + * + * [18..16] The number of valid row bits is this value, plus 10. + * Note: Value 1 is not implemented. + * Value 7 is unsupported, and thus reserved. + * + * [22..20] Bank select. + * [25..24] Rank select. It is later referred to as "ranksel". * * IOSAV_n_ADDR_UPDATE_ch(channel, index) - * How the address shall be updated after executing the sub-sequence command. + * How the address updates after executing a command in the subseq. * * Bitfields: - * [0] Increment CAS/RAS by 1. - * [1] Increment CAS/RAS by 8. + * [0] Increment row/column address by 1. + * [1] Increment row/column address by 8. * [2] Increment bank select by 1. - * [3..4] Increment rank select by 1, 2 or 3. - * [5..9] Known as "addr_wrap". Address bits will wrap around the [addr_wrap..0] range. - * [10..11] LFSR update: + * [4..3] Increment rank select by 1, 2 or 3. + * [9..5] Known as "addr_wrap", it limits the address increments. + * Address bits will wrap around the [addr_wrap..0] range. + * + * [11..10] LFSR update: * 00: Do not use the LFSR function. * 01: Undefined, treat as Reserved. * 10: Apply LFSR on the [addr_wrap..0] bit range. * 11: Apply LFSR on the [addr_wrap..3] bit range. * - * [12..15] Update rate. The number of command runs between address updates. For example: + * [15..12] Update rate. The number of command runs between address updates. For example: * 0: Update every command run. * 1: Update every second command run. That is, half of the command rate. * N: Update after N command runs without updates. * - * [16..17] LFSR behavior on the deselect cycles (when no sub-seq command is issued): + * [17..16] LFSR behavior on the deselect cycles (when no subseq command is issued): * 0: No change w.r.t. the last issued command. * 1: LFSR XORs with address & command (excluding CS), but does not update. * 2: LFSR XORs with address & command (excluding CS), and updates. * * IOSAV_n_SP_CMD_CTRL_ch(channel, index) - * Special command control register. Controls the DRAM command signals. + * Configures how the DRAM command lines will be driven in each + * command of the subseq. * * Bitfields: - * [0] !RAS signal. - * [1] !CAS signal. - * [2] !WE signal. - * [4..7] CKE, per rank and channel. - * [8..11] ODT, per rank and channel. - * [12..15] Chip select, per rank and channel. It works as follows: + * [0] !RAS signal (as driven electrically). + * [1] !CAS signal (as driven electrically). + * [2] !WE signal (as driven electrically). + * + * [4] CKE, for DIMM 0 Rank 0. + * [5] CKE, for DIMM 0 Rank 1. + * [6] CKE, for DIMM 1 Rank 0. + * [7] CKE, for DIMM 1 Rank 1. + * [11..8] ODT, per DIMM & Rank (same encoding as CKE). + * [15..12] Chip select, per DIMM and Rank. It works as follows: * * entity CS_BLOCK is * port ( * MODE : in std_logic; -- Mode select at [16] * RANKSEL : in std_logic_vector(0 to 3); -- Decoded "ranksel" value - * CS_CTL : in std_logic_vector(0 to 3); -- Chip select control at [12..15] + * CS_CTL : in std_logic_vector(0 to 3); -- Chip select control at [15..12] * CS_Q : out std_logic_vector(0 to 3) -- CS signals * ); * end entity CS_BLOCK; @@ -90,41 +115,45 @@ * [17] Auto Precharge. Only valid when using 10 row bits! * * IOSAV_n_SUBSEQ_CTRL_ch(channel, index) - * Sub-sequence parameters. Controls repetititons, delays and data orientation. + * The parameters of the subseq: number of repetitions of the command, + * the delay between command executions, wait cycles after completing + * this subseq and before the next one, and the data direction of the + * command (read, write, neither, or both read and write). * * Bitfields: - * [0..8] Number of repetitions of the sub-sequence command. - * [10..14] Gap, number of clock-cycles to wait before sending the next command. - * [16..24] Number of clock-cycles to idle between sub-sequence commands. - * [26..27] The direction of the data. - * 00: None, does not handle data + * [8..0] Number of repetitions of the DRAM command in this subseq. + * [14..10] Number of DCLK cycles to wait between two successive DRAM commands. + * [24..16] Number of DCLK cycles to idle after this subseq and before the next subseq. + * [27..26] The direction of the data: + * 00: None (non-data command) * 01: Read * 10: Write * 11: Read & Write * * IOSAV_n_ADDRESS_LFSR_ch(channel, index) - * 23-bit LFSR state register. It is written into the LFSR when the sub-sequence is loaded, - * and then read back from the LFSR when the sub-sequence is done. + * 23-bit LFSR state. It is written into the LFSR when the subseq is + * loaded, and then read back from the LFSR when the subseq is done. * * Bitfields: - * [0..22] LFSR state. + * [22..0] LFSR state. * * IOSAV_SEQ_CTL_ch(channel) - * Control the sequence level in IOSAV: number of sub-sequences, iterations, maintenance... + * IOSAV full sequence settings: number of subseqs, iterations, stop + * on error, maintenance cycles... * * Bitfields: - * [0..7] Number of full sequence executions. When this field becomes non-zero, then the + * [7..0] Number of full sequence executions. When this field becomes non-zero, then the * sequence starts running immediately. This value is decremented after completing * a full sequence iteration. When it is zero, the sequence is done. No decrement * is done if this field is set to 0xff. This is the "infinite repeat" mode, and * it is manually aborted by clearing this field. * - * [8..16] Number of wait cycles after each sequence iteration. This wait's purpose is to + * [16..8] Number of wait cycles after each sequence iteration. This wait's purpose is to * allow performing maintenance in infinite loops. When non-zero, RCOMP, refresh * and ZQXS operations can take place. * * [17] Stop-on-error mode: Whether to stop sequence execution when an error occurs. - * [18..19] Number of sub-sequences. The programmed value is the index of the last sub-seq. + * [19..18] Number of subseqs. The programmed value is the index of the last valid subseq. * [20] If set, keep refresh disabled until the next sequence execution. * DANGER: Refresh must be re-enabled within the (9 * tREFI) period! * @@ -132,20 +161,22 @@ * bit [20] is also set, or was set on the previous sequence. This bit exists so * that the sequence machine can be used as a timer without affecting the memory. * - * [23] If set, a output pin is asserted on the first detected error. This output can - * be used as a trigger for an oscilloscope or a logic analyzer, which is handy. + * [23] If set, an output pin is asserted on the first detected error. This output can + * be used as a trigger for an oscilloscope or a logic analyzer, which is pretty + * useful for debugging (if you have the equipment and know where this pin is). * * IOSAV_DATA_CTL_ch(channel) * Data-related controls in IOSAV mode. * * Bitfields: - * [0..7] WDB (Write Data Buffer) pattern length: [0..7] = (length / 8) - 1; - * [8..15] WDB read pointer. Points at the data used for IOSAV write transactions. - * [16..23] Comparison pointer. Used to compare data from IOSAV read transactions. + * [7..0] WDB (Write Data Buffer) pattern length: [7..0] = (length / 8) - 1; + * [15..8] WDB read pointer. Points at the data used for IOSAV write transactions. + * [23..16] Comparison pointer. Used to compare data from IOSAV read transactions. * [24] If set, increment pointers only when micro-breakpoint is active. * * IOSAV_STATUS_ch(channel) - * State of the IOSAV sequence machine. Should be polled after sending an IOSAV sequence. + * Provides feedback on the state of the IOSAV sequence machine. + * Should be polled after submitting an IOSAV sequence for execution. * * Bitfields: * [0] IDLE: IOSAV is sleeping. @@ -155,7 +186,6 @@ * [4] PANIC: The refresh machine issued a Panic Refresh, and IOSAV was aborted. * [5] RCOMP: RComp failure. Unused, consider Reserved. * [6] Cleared with a new sequence, and set when done and refresh counter is drained. - * */ /* Temporary IOSAV register macros to verifiably split bitfields */ From aae16330695ab1a3a3ed1a9068dc25bba00997fe Mon Sep 17 00:00:00 2001 From: harshit Date: Tue, 12 May 2020 12:55:39 +0530 Subject: [PATCH 149/405] security/tpm/tspi: Fix handling of white space delimited list The current implementation uses strcmp() without splitting the list and therefore returns false even when the string pointed to by 'name' is a part of 'whitelist'. The patch fixes this problem. Also, update help text of CONFIG_TPM_MEASURED_BOOT_RUNTIME_DATA to space delimited list to align it with the other lists we use. Change-Id: Ifd285162ea6e562a5bb18325a1b767ac2e4276f3 Signed-off-by: Harshit Sharma Reviewed-on: https://review.coreboot.org/c/coreboot/+/41280 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Werner Zeh --- src/security/tpm/Kconfig | 2 +- src/security/tpm/tspi/crtm.c | 9 +++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index 6741614bb0..b6a7781d9a 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -112,6 +112,6 @@ config TPM_MEASURED_BOOT_RUNTIME_DATA depends on TPM_MEASURED_BOOT help Runtime data whitelist of cbfs filenames. Needs to be a - comma separated list + space delimited list endmenu # Trusted Platform Module (tpm) diff --git a/src/security/tpm/tspi/crtm.c b/src/security/tpm/tspi/crtm.c index 8bcc01bcbb..49daeb009b 100644 --- a/src/security/tpm/tspi/crtm.c +++ b/src/security/tpm/tspi/crtm.c @@ -88,17 +88,18 @@ static bool is_runtime_data(const char *name) const char *whitelist = CONFIG_TPM_MEASURED_BOOT_RUNTIME_DATA; size_t whitelist_len = sizeof(CONFIG_TPM_MEASURED_BOOT_RUNTIME_DATA) - 1; size_t name_len = strlen(name); - int i; + const char *end; if (!whitelist_len || !name_len) return false; - for (i = 0; (i + name_len) <= whitelist_len; i++) { - if (!strcmp(whitelist + i, name)) + while ((end = strchr(whitelist, ' '))) { + if (end - whitelist == name_len && !strncmp(whitelist, name, name_len)) return true; + whitelist = end + 1; } - return false; + return !strcmp(whitelist, name); } uint32_t tspi_measure_cbfs_hook(struct cbfsf *fh, const char *name) From 14ea2fc90cb4cb183b63cd8edd68c3168b398ce2 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 13 May 2020 21:46:46 +0200 Subject: [PATCH 150/405] nb/intel/sandybridge: Do not hardcode resource indices Other northbridges use an index variable to assign monotonically incrementing values to each resource. Do it here as well. Change-Id: I8719a1a5973a10531cf11b3307652212cb3d4895 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41375 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/northbridge/intel/sandybridge/northbridge.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index c1cdea5428..ce28c05fd4 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -135,6 +135,7 @@ static void mc_read_resources(struct device *dev) uint32_t tseg_base, uma_size, tolud; uint16_t ggc; unsigned long long tomk; + unsigned long index = 3; pci_dev_read_resources(dev); @@ -238,9 +239,9 @@ static void mc_read_resources(struct device *dev) printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10); /* Report the memory regions */ - ram_resource(dev, 3, 0, legacy_hole_base_k); - ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k, - (tomk - (legacy_hole_base_k + legacy_hole_size_k))); + ram_resource(dev, index++, 0, legacy_hole_base_k); + ram_resource(dev, index++, legacy_hole_base_k + legacy_hole_size_k, + (tomk - (legacy_hole_base_k + legacy_hole_size_k))); /* * If >= 4GB installed, then memory from TOLUD to 4GB is remapped above TOM. @@ -248,11 +249,11 @@ static void mc_read_resources(struct device *dev) */ touud >>= 10; /* Convert to KB */ if (touud > 4096 * 1024) { - ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024)); + ram_resource(dev, index++, 4096 * 1024, touud - (4096 * 1024)); printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", (touud >> 10) - 4096); } - add_fixed_resources(dev, 6); + add_fixed_resources(dev, index++); } static void northbridge_dmi_init(struct device *dev) From 5f0e8d84626902b1e48ab619319ab1c6eb9579a4 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Tue, 5 May 2020 16:01:07 -0400 Subject: [PATCH 151/405] superio/winbond/w83977tf: Fix iasl warning The common PnP serial port DSDT code is intentionally included twice for two serial ports with different LDNs. Undefine LDN and the PM register name before redefining for second serial port so iasl doesn't complain. Change-Id: I031905479c66698fb01da028e3f37d923396d2d9 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/41095 Reviewed-by: Patrick Georgi Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/superio/winbond/w83977tf/acpi/superio.asl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/superio/winbond/w83977tf/acpi/superio.asl b/src/superio/winbond/w83977tf/acpi/superio.asl index cd514d07df..6e37a5bbc1 100644 --- a/src/superio/winbond/w83977tf/acpi/superio.asl +++ b/src/superio/winbond/w83977tf/acpi/superio.asl @@ -350,6 +350,8 @@ Device (ECP) #define SUPERIO_UART_LDN W83977TF_SP1 #define SUPERIO_UART_PM_REG UAPW #include + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_PM_REG #endif #ifdef SUPERIO_SHOW_UARTB From 86abc8dff0bf1a2e97daaccfeca27260dba4eb63 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 18 May 2020 17:09:01 +0200 Subject: [PATCH 152/405] soc/amd/picasso/romstage: removed unused include Change-Id: I550599ae5ef9875ce820a4534d21439ff2027585 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/41513 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/picasso/romstage.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index e6bc5c9c8f..a2ca055525 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include From 4480dc1ca1fd6982a3b4cbc6cf1531992f517fb2 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 29 Apr 2020 11:56:02 -0700 Subject: [PATCH 153/405] device: Add definitions for SoundWire specification This header implements structures to describe the properties defined in the SoundWire Discovery and Configuration Specification Version 1.0. By itself this just provides the property definitions, it is then used by the code that generates ACPI device properties and by the controller and codec drivers. A new header for MIPI vendor/device IDs is also added, with the MIPI Alliance board members added by default. This will be used in the same way as pci_ids.h to track devices added to coreboot. BUG=b:146482091 Signed-off-by: Duncan Laurie Change-Id: Ie9901d26d1efe68edad7c049c98a976c4e4f06f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40883 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/include/device/mipi_ids.h | 21 ++ src/include/device/soundwire.h | 429 +++++++++++++++++++++++++++++++++ 2 files changed, 450 insertions(+) create mode 100644 src/include/device/mipi_ids.h create mode 100644 src/include/device/soundwire.h diff --git a/src/include/device/mipi_ids.h b/src/include/device/mipi_ids.h new file mode 100644 index 0000000000..2e0254c0b7 --- /dev/null +++ b/src/include/device/mipi_ids.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* + * MIPI Alliance Manufacturer IDs from https://mid.mipi.org + */ + +#ifndef __DEVICE_MIPI_IDS_H__ +#define __DEVICE_MIPI_IDS_H__ + +/* Board Members */ +#define MIPI_MFG_ID_INTEL 0x0105 +#define MIPI_MFG_ID_QUALCOMM 0x0217 +#define MIPI_MFG_ID_BOSCH 0x03b8 +#define MIPI_MFG_ID_SAMSUNG 0x010b +#define MIPI_MFG_ID_ST_MICRO 0x0104 +#define MIPI_MFG_ID_SYNOPSYS 0x0148 +#define MIPI_MFG_ID_TI 0x0102 +#define MIPI_MFG_ID_TOSHIBA 0x0126 + +#endif /* __DEVICE_MIPI_IDS_H__ */ diff --git a/src/include/device/soundwire.h b/src/include/device/soundwire.h new file mode 100644 index 0000000000..85e3186219 --- /dev/null +++ b/src/include/device/soundwire.h @@ -0,0 +1,429 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This header implements structures to describe the properties defined in the + * SoundWire Discovery and Configuration (DisCo) Specification Version 1.0. + * + * This is available for non-members after providing a name and email address at + * https://resources.mipi.org/disco_soundwire + * + * The structure members mirror the property names defined in the specification, + * with the exception that '-' is transformed into '_' for compatible naming. + * + * See Documentation/drivers/soundwire.md for more information. + */ + +#ifndef __DEVICE_SOUNDWIRE_H__ +#define __DEVICE_SOUNDWIRE_H__ + +#include +#include + +/** + * enum soundwire_limits - Limits on number of SoundWire devices in topology. + * @SOUNDWIRE_MAX: Maximum value for lists of configuration values in SoundWire devices. + * @SOUNDWIRE_MIN_DPN: Data Port minimum value. DPn range is 1-14. + * @SOUNDWIRE_MAX_DPN: Data Port maximum value. DPn range is 1-14. + * @SOUNDWIRE_MAX_SLAVE: Maximum number of slave devices that can be attached to one master. + * @SOUNDWIRE_MAX_LINK: Maximum number of master link devices that can be on one controller. + * @SOUNDWIRE_MAX_LANE: Maximum number of lanes in a multi-lane slave device. + * @SOUNDWIRE_MAX_MODE: Maximum number of Audio or Bulk Register Access modes. + */ +enum soundwire_limits { + SOUNDWIRE_MAX = 32, + SOUNDWIRE_MIN_DPN = 1, + SOUNDWIRE_MAX_DPN = 14, + SOUNDWIRE_MAX_SLAVE = 11, + SOUNDWIRE_MAX_LINK = 8, + SOUNDWIRE_MAX_LANE = 8, + SOUNDWIRE_MAX_MODE = 4 +}; + +/** + * enum soundwire_sw_version - Versions of SoundWire Discovery and Configuration Specification. + * @SOUNDWIRE_SW_VERSION_1_0: DisCo Specification Version 1.0 released November 2016. + */ +enum soundwire_sw_version { + SOUNDWIRE_SW_VERSION_1_0 = 0x00010000 +}; + +/** + * enum soundwire_version - Versions of SoundWire Specification supported by a device. + * @SOUNDWIRE_VERSION_1_0: SoundWire Specification Version 1.0 released January 2015. + * @SOUNDWIRE_VERSION_1_1: SoundWire Specification Version 1.1 released June 2016. + * @SOUNDWIRE_VERSION_1_2: SoundWire Specification Version 1.2 released April 2019. + */ +enum soundwire_version { + SOUNDWIRE_VERSION_1_0 = 1, + SOUNDWIRE_VERSION_1_1, + SOUNDWIRE_VERSION_1_2 +}; + +/** + * enum mipi_class - MIPI class encoding. + * @MIPI_CLASS_NONE: No further class decoding. + * @MIPI_CLASS_SDCA: Device implements SoundWire Device Class for Audio (SDCA). + * + * 0x02-0x7F: Reserved + * 0x80-0xFF: MIPI Alliance extended device class + */ +enum mipi_class { + MIPI_CLASS_NONE, + MIPI_CLASS_SDCA +}; + +/** + * struct soundwire_address - SoundWire Device Address Encoding. + * @version: SoundWire specification version from &enum soundwire_version. + * @link_id: Zero-based SoundWire master link id. + * @unique_id: Unique ID for multiple slave devices on the same bus. + * @manufacturer_id: Manufacturer ID from include/device/mipi_ids.h. + * @part_id: Vendor defined part ID. + * @class: MIPI class encoding in &enum mipi_class. + */ +struct soundwire_address { + enum soundwire_version version; + uint8_t link_id; + uint8_t unique_id; + uint16_t manufacturer_id; + uint16_t part_id; + enum mipi_class class; +}; + +/** + * struct soundwire_link - SoundWire master device properties. + * @clock_stop_mode0_supported: %true if clock stop mode0 is supported by this device. + * @clock_stop_mode1_supported: %true if clock stop mode1 is supported by this device. + * @max_clock_frequency: Maximum bus clock for this device in Hz. + * @supported_clock_gears_count: Number of entries in supported_clock_gears. + * @supported_clock_gears: One entry for each supported clock gear. + * @clock_frequencies_supported_count: Number of entries in clock_frequencies_supported. + * @clock_frequencies_supported: One entry for each clock frequency supported in Hz. + * @default_frame_rate: Controller default frame rate in Hz. + * @default_frame_row_size: Number of rows between 48-256. + * @default_frame_col_size: Number of columns: 2, 4, 8, 16. + * @dynamic_frame_shape: %true if bus driver may change frame shape dynamically. + * @command_error_threshold: Number of times that software may retry sending a command. + */ +struct soundwire_link { + bool clock_stop_mode0_supported; + bool clock_stop_mode1_supported; + unsigned int max_clock_frequency; + size_t supported_clock_gears_count; + unsigned int supported_clock_gears[SOUNDWIRE_MAX]; + size_t clock_frequencies_supported_count; + uint64_t clock_frequencies_supported[SOUNDWIRE_MAX]; + unsigned int default_frame_rate; + unsigned int default_frame_row_size; + unsigned int default_frame_col_size; + bool dynamic_frame_shape; + unsigned int command_error_threshold; +}; + +/** + * struct soundwire_controller - SoundWire controller properties. + * @master_count: Number of masters present on this device. + * @master_list: One entry for each master device. + */ +struct soundwire_controller { + unsigned int master_list_count; + struct soundwire_link master_list[SOUNDWIRE_MAX_LINK]; +}; + +/* SoundWire port bitmask, used for slave source/sink port list property. */ +#define SOUNDWIRE_PORT(port) BIT(port) + +/** + * struct soundwire_slave - SoundWire slave device properties. + * @wake_up_unavailable: Wake from this device is not supported or allowed. + * @test_mode_supported: %true if test mode is supported by this device. + * @clock_stop_mode1_supported: %true if clock stop mode1 is supported by this device. + * @simplified_clockstopprepare_sm_supported: %true if slave only supports the simplified + * clock stop prepare state machine and will + * always be ready for a stop clock transition. + * @clockstopprepare_timeout: Slave-specific timeout in milliseconds. + * @clockstopprepare_hard_reset_behavior: %true when slave keeps the status of the + * StopClockPrepare state machine after exit from + * mode1 and must be de-prepared by software. + * @slave_channelprepare_timeout: Slave-specific timeout in milliseconds. + * @highPHY_capable: %true if device is HighPHY capable. + * @paging_supported: %true if device implements paging registers. + * @bank_delay_supported: %true if device implements bank delay/bridge registers. + * @port15_read_behavior: %true if device supports read to Port15 alias. + * @master_count: Number of master links present on this slave. + * @source_port_list: Bitmap identifying supported source ports, starting at bit 1. + * @sink_port_list: Bitmap identifying supported sink ports, starting at bit 1. + */ +struct soundwire_slave { + bool wake_up_unavailable; + bool test_mode_supported; + bool clock_stop_mode1_supported; + bool simplified_clockstopprepare_sm_supported; + unsigned int clockstopprepare_timeout; + bool clockstopprepare_hard_reset_behavior; + unsigned int slave_channelprepare_timeout; + bool highPHY_capable; + bool paging_supported; + bool bank_delay_supported; + bool port15_read_behavior; + size_t master_count; + uint32_t source_port_list; + uint32_t sink_port_list; +}; + +/** + * enum soundwire_multilane_dir - Direction of lane in slave multilane device. + * @MASTER_LANE: Lane is connected to a master device. + * @SLAVE_LINK: Lane is connected to a slave device. + */ +enum soundwire_multilane_dir { + MASTER_LANE, + SLAVE_LINK, +}; + +/** + * struct soundwire_multilane_map - Pair a soundwire lane with direction. + * @lane: Slave device lane number. + * @direction: Direction of the slave lane. + * @connection: The connection that this lane makes. + */ +struct soundwire_multilane_map { + unsigned int lane; + enum soundwire_multilane_dir direction; + union lane_type { + unsigned int master_lane; + unsigned int slave_link; + } connection; +}; + +/** + * struct soundwire_multilane - Multi-Lane SoundWire slave device. + * @lane_mapping_count: Number of entries in lane_mapping. + * @lane_mapping: One entry for each lane that is connected to lanes on a master device or + * slave devices via a slave link. Lane 0 is always connected to the master + * and entry 0 in this array is ignored. + * @lane_bus_holder_count: Number of entries in lane_bus_holder. + * @lane_bus_holder: One entry for each lane, %true if the device behaves as a bus holder. + */ +struct soundwire_multilane { + size_t lane_mapping_count; + struct soundwire_multilane_map lane_mapping[SOUNDWIRE_MAX_LANE]; + size_t lane_bus_holder_count; + bool lane_bus_holder[SOUNDWIRE_MAX_LANE]; +}; + +/** + * enum soundwire_prepare_channel_behavior - Specifies the dependencies between the + * Channel Prepare sequence and bus clock config. + * @CHANNEL_PREPARE_ANY_FREQUENCY: Channel Prepare can happen at any bus clock rate. + * @CHANNEL_PREPARE_SUPPORTED_FREQUENCY: Channel Prepare sequence shall happen only after + * the bus clock is changed to a supported frequency. + */ +enum soundwire_prepare_channel_behavior { + CHANNEL_PREPARE_ANY_FREQUENCY, + CHANNEL_PREPARE_SUPPORTED_FREQUENCY +}; + +/** + * struct soundwire_audio_mode - Properties for each supported Audio Mode. + * @sdw_name: SoundWire device name for this audio mode device instance. + * @max_bus_frequency: Maximum bus frequency of this mode in Hz. + * @min_bus_frequency: Minimum bus frequency of this mode in Hz. + * @bus_frequency_configs_count: Number of entries in bus_frequency_configs. + * @bus_frequency_configs: One entry for each supported bus frequency, + * if not all values in min to max range are valid. + * @max_sampling_frequency: Maximum sampling frequency of this mode in Hz. + * @min_sampling_frequency: Minimum sampling frequency of this mode in Hz. + * @sampling_frequency_configs_count: Number of entries in sampling_frequency_configs. + * @sampling_frequency_configs: One entry for each supported sampling frequency, + * if not all values in min to max range are valid. + * @prepare_channel_behavior: Dependencies between Channel Prepare and bus clock. + * @glitchless_transitions: Bitmap describing possible glitchless transitions from this audio + * mode to another audio mode. Not used for only one mode. + */ +struct soundwire_audio_mode { + unsigned int max_bus_frequency; + unsigned int min_bus_frequency; + size_t bus_frequency_configs_count; + uint64_t bus_frequency_configs[SOUNDWIRE_MAX]; + unsigned int max_sampling_frequency; + unsigned int min_sampling_frequency; + size_t sampling_frequency_configs_count; + uint64_t sampling_frequency_configs[SOUNDWIRE_MAX]; + enum soundwire_prepare_channel_behavior prepare_channel_behavior; + uint32_t glitchless_transitions; +}; + +/* Type of SoundWire Data Port supported for this device. */ +enum soundwire_data_port_type { + FULL_DATA_PORT, + SIMPLIFIED_DATA_PORT, + REDUCED_DATA_PORT +}; + +/* Number of samples that can be grouped together (0-based count). */ +enum soundwire_block_group_count { + BLOCK_GROUP_COUNT_1, + BLOCK_GROUP_COUNT_2, + BLOCK_GROUP_COUNT_3, + BLOCK_GROUP_COUNT_4 +}; + +/* Bitmap identifying the types of modes supported. */ +enum soundwire_mode_bitmap { + MODE_ISOCHRONOUS = BIT(0), + MODE_TX_CONTROLLED = BIT(1), + MODE_RX_CONTROLLED = BIT(2), + MODE_FULL_ASYNCHRONOUS = BIT(3) +}; + +/* Bitmap identifying the encoding schemes supported. */ +enum soundwire_port_encoding_bitmap { + ENCODE_TWOS_COMPLEMENT = BIT(0), + ENCODE_SIGN_MAGNITUDE = BIT(1), + ENCODE_IEEE_32BIT_FP = BIT(2) +}; + +/** + * struct soundwire_dpn - Configuration properties for SoundWire DPn Data Ports. + * @port_max_wordlength: Maximum number of bits in a Payload Channel Sample. (1-64) + * @port_min_wordlength: Minimum number of bits in a Payload Channel Sample. (1-64) + * @port_wordlength_configs_count: Number of entries in port_wordlength_configs. + * @port_wordlength_configs: One entry for each supported wordlength. + * Used if only specific wordlength values are allowed. + * @data_port_type: Type of data port from &enum soundwire_data_port_type. + * @max_grouping_supported: 0-based maximum number of samples that can be grouped for + * %FULL_DATA_PORT. The %SIMPLIFIED_DATA_PORT and %REDUCED_DATA_PORT + * require 4 samples in a group. + * @simplified_channelprepare_sm: %true if the channel prepare sequence is not required, + * and the Port Ready interrupt is not supported. + * @port_channelprepare_timeout: Port-specific timeout value in milliseconds. + * @imp_def_dpn_interrupts_supported: Bitmap for support of implementation-defined interrupts. + * @min_channel_number: Minimum channel number supported. + * @max_channel_number: Maximum channel number supported. + * @channel_number_list_count: Number of entries in channel_number_list. + * @channel_number_list: One entry for each available channel number. + * Used if only specific channels are available. + * @channel_combination_list_count: Number of entries in channel_combination_list. + * @channel_combination_list: One bitmap entry for each valid channel combination. + * @modes_supported: Bitmap identifying the types of modes supported by the device. + * @max_async_buffer: Number of samples that this port can buffer in asynchronous modes. + * Only required if the slave implements buffer larger than required. + * @block_packing_mode: %true if BlockPackingMode may be configured as BlockPerPort or + * BlocKPerChannel. %false if BlockPackingMode must be BlockPerPort. + * @port_encoding_type: Bitmap describing the types of Payload Channel Sample encoding + * schemes implemented by this port. + * @port_audio_mode_count: Number of entries in audio_mode_list. + * @port_audio_mode_list: One entry for each supported audio mode id. + */ +struct soundwire_dpn { + unsigned int port_max_wordlength; + unsigned int port_min_wordlength; + size_t port_wordlength_configs_count; + uint64_t port_wordlength_configs[SOUNDWIRE_MAX]; + enum soundwire_data_port_type data_port_type; + enum soundwire_block_group_count max_grouping_supported; + bool simplified_channelprepare_sm; + unsigned int port_channelprepare_timeout; + uint32_t imp_def_dpn_interrupts_supported; + unsigned int min_channel_number; + unsigned int max_channel_number; + size_t channel_number_list_count; + uint64_t channel_number_list[SOUNDWIRE_MAX]; + size_t channel_combination_list_count; + uint64_t channel_combination_list[SOUNDWIRE_MAX]; + enum soundwire_mode_bitmap modes_supported; + unsigned int max_async_buffer; + bool block_packing_mode; + uint32_t port_encoding_type; + size_t port_audio_mode_count; + unsigned int port_audio_mode_list[SOUNDWIRE_MAX_MODE]; +}; + +/** + * struct soundwire_bra_mode - Bulk Register Access mode properties. + * @max_bus_frequency: Maximum bus frequency of this mode in Hz. + * @min_bus_frequency: Minimum bus frequency of this mode in Hz. + * @bus_frequency_configs_count: Number of entries in bus_frequency_configs. + * @bus_frequency_configs: One entry for each supported bus frequency, + * Used if not all values in min to max range are valid. + * @max_data_per_frame: Maximum data bytes per frame, excluding header, CRC, and footer. + * @min_us_between_transactions: Amount of delay in uS required between transactions. + * @max_bandwidth: Maximum bandwidth in bytes per second that can be written/read. + * @block_alignment: Size of basic block in bytes. + */ +struct soundwire_bra_mode { + unsigned int max_bus_frequency; + unsigned int min_bus_frequency; + size_t bus_frequency_configs_count; + uint64_t bus_frequency_configs[SOUNDWIRE_MAX]; + unsigned int max_data_per_frame; + unsigned int min_us_between_transactions; + unsigned int max_bandwidth; + unsigned int block_alignment; +}; + +/** + * struct soundwire_dp0 - Configuration properties for SoundWire DP0 Data Port. + * @port_max_wordlength: Maximum number of bits in a Payload Channel Sample. (1-64) + * @port_min_wordlength: Minimum number of bits in a Payload Channel Sample. (1-64) + * @port_wordlength_configs_count: Number of entries in port_wordlength_configs. + * @port_wordlength_configs: One entry for each supported wordlength. + * Used if only specific wordlength values are allowed. + * @bra_flow_controlled: Used if the slave can result in an OK_NotReady response. + * @bra_imp_def_response_supported: %true if implementation defined response is supported. + * @bra_role_supported: %true if the slave supports initiating BRA transactions. + * @simplified_channel_prepare_sm: %true if the channel prepare sequence is not required, + * and the Port Ready interrupt is not supported. + * @imp_def_dp0_interrupts_supported: If set, each bit corresponds to support for + * implementation-defined interrupts ImpDef. + * @imp_def_bpt_supported: %true if implementation defined Payload Type is supported. + * @bra_mode_count: Number of entries in bra_mode_list. + * @bra_mode_list: One entry for each supported Bulk Register Access mode id. + */ +struct soundwire_dp0 { + unsigned int port_max_wordlength; + unsigned int port_min_wordlength; + size_t port_wordlength_configs_count; + uint64_t port_wordlength_configs[SOUNDWIRE_MAX]; + bool bra_flow_controlled; + bool bra_imp_def_response_supported; + bool bra_role_supported; + bool simplified_channel_prepare_sm; + unsigned int imp_def_dp0_interrupts_supported; + bool imp_def_bpt_supported; + size_t bra_mode_count; + unsigned int bra_mode_list[SOUNDWIRE_MAX_MODE]; +}; + +/** + * struct soundwire_dpn_entry - Full duplex data port properties for DPn 1-14. + * @port: DPn data port number, starting at 1. + * @source: Source data port properties. (optional) + * @sink: Sink data port properties. (optional) + */ +struct soundwire_dpn_entry { + size_t port; + struct soundwire_dpn *source; + struct soundwire_dpn *sink; +}; + +/** + * struct soundwire_codec - Contains all configuration for a SoundWire codec slave device. + * @slave: Properties for slave device. + * @audio_mode: Properties for audio modes used by DPn data ports 1-14. + * @dpn: Properties for DPn data ports 1-14. + * @dp0_bra_mode: Properties for Bulk Register Access mode for data port 0. (optional) + * @dp0: Properties for data port 0. (optional) + * @multilane: Properties for slave multilane device. (optional) + */ +struct soundwire_codec { + struct soundwire_slave *slave; + struct soundwire_audio_mode *audio_mode[SOUNDWIRE_MAX_MODE]; + struct soundwire_dpn_entry dpn[SOUNDWIRE_MAX_DPN - SOUNDWIRE_MIN_DPN]; + struct soundwire_bra_mode *dp0_bra_mode[SOUNDWIRE_MAX_MODE]; + struct soundwire_dp0 *dp0; + struct soundwire_multilane *multilane; +}; + +#endif /* __DEVICE_SOUNDWIRE_H__ */ From bf213087057f61b37d9586414e47a8cf2cfc23a1 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 18 May 2020 20:27:04 +0200 Subject: [PATCH 154/405] soc/amd/picasso/soc_util: add socket type detection and printing Change-Id: I643a4c5f8a42a5fb0603a1a049545b57d16493a6 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/41517 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/include/soc/soc_util.h | 8 ++++++ src/soc/amd/picasso/soc_util.c | 33 ++++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/src/soc/amd/picasso/include/soc/soc_util.h b/src/soc/amd/picasso/include/soc/soc_util.h index 9d769b9417..8e2c598630 100644 --- a/src/soc/amd/picasso/include/soc/soc_util.h +++ b/src/soc/amd/picasso/include/soc/soc_util.h @@ -1,5 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +enum socket_type { + SOCKET_FP5 = 0, + SOCKET_AM4 = 2, + SOCKET_FT5 = 3, +}; + +void print_socket_type(void); + int soc_is_pollock(void); int soc_is_dali(void); int soc_is_picasso(void); diff --git a/src/soc/amd/picasso/soc_util.c b/src/soc/amd/picasso/soc_util.c index 94ebb6b066..a70d833d80 100644 --- a/src/soc/amd/picasso/soc_util.c +++ b/src/soc/amd/picasso/soc_util.c @@ -1,8 +1,41 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include +#include + +#define SOCKET_TYPE_SHIFT 28 +#define SOCKET_TYPSE_MASK (0xf << SOCKET_TYPE_SHIFT) + +static enum socket_type get_socket_type(void) +{ + uint32_t ebx = cpuid_ebx(0x80000001); + ebx = (ebx & SOCKET_TYPSE_MASK) >> SOCKET_TYPE_SHIFT; + return (enum socket_type)ebx; +} + +void print_socket_type(void) +{ + enum socket_type socket = get_socket_type(); + + printk(BIOS_INFO, "Socket type: "); + + switch (socket) { + case SOCKET_FP5: + printk(BIOS_INFO, "FP5\n"); + break; + case SOCKET_AM4: + printk(BIOS_INFO, "AM4\n"); + break; + case SOCKET_FT5: + printk(BIOS_INFO, "FT5\n"); + break; + default: + printk(BIOS_INFO, "unknown\n"); + } +} int soc_is_pollock(void) { From f36c38355b45a03b5ad009fae965024e2bfe5c90 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 18 May 2020 20:43:49 +0200 Subject: [PATCH 155/405] soc/amd/picasso/soc_util: use socket type detection Remove the Kconfig options for per board socket type selection and use the runtime detection instead. Change-Id: I82cf922661c24e2a529fa4927893727b643660e3 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/41518 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Kconfig | 10 ---------- src/soc/amd/picasso/soc_util.c | 6 +++--- 2 files changed, 3 insertions(+), 13 deletions(-) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 48e1cc2e6b..71630b8d9e 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -53,16 +53,6 @@ config CPU_SPECIFIC_OPTIONS select UDK_2017_BINDING select HAVE_CF9_RESET -config AMD_FP5 - def_bool y if !AMD_FT5 - help - The FP5 package supports higher-wattage parts and dual channel DDR4 memory. - -config AMD_FT5 - def_bool n - help - The FT5 package supports low-power parts and single-channel DDR4 memory. - config PRERAM_CBMEM_CONSOLE_SIZE hex default 0x1600 diff --git a/src/soc/amd/picasso/soc_util.c b/src/soc/amd/picasso/soc_util.c index a70d833d80..f82811053c 100644 --- a/src/soc/amd/picasso/soc_util.c +++ b/src/soc/amd/picasso/soc_util.c @@ -39,7 +39,7 @@ void print_socket_type(void) int soc_is_pollock(void) { - return soc_is_zen_plus() && CONFIG(AMD_FT5); + return soc_is_zen_plus() && get_socket_type() == SOCKET_FT5; } /* @@ -48,12 +48,12 @@ int soc_is_pollock(void) */ int soc_is_dali(void) { - return soc_is_raven2() && CONFIG(AMD_FP5); + return soc_is_raven2() && get_socket_type() == SOCKET_FP5; } int soc_is_picasso(void) { - return soc_is_zen_plus() && CONFIG(AMD_FP5); + return soc_is_zen_plus() && get_socket_type() == SOCKET_FP5; } int soc_is_raven2(void) From 839f668d89e8cfb6fcd3aeaa21148d7644cb040e Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Mon, 9 Mar 2020 14:05:49 -0600 Subject: [PATCH 156/405] soc/amd/picasso/acpi: Move _PIC method to root namespace The _PIC method sets the interrupt model (PIC or APIC). It needs to be defined at the root level for the kernel to find it. Previously this method was never getting called, so we were always stuck in APIC mode. BUG=b:139429446, b:147042464 BRANCH=none TEST=Saw the method getting called [ 1.251774] ACPI Debug: "PIC MODE: 0000000000000001" Change-Id: Idd5e9646df8d56e7cbec2be8b4016c36d81e5fb8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2095682 Signed-off-by: Raul E Rangel Reviewed-on: https://review.coreboot.org/c/coreboot/+/41437 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/amd/picasso/acpi/pci_int.asl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/amd/picasso/acpi/pci_int.asl b/src/soc/amd/picasso/acpi/pci_int.asl index 0f3d882a8b..f89a14e795 100644 --- a/src/soc/amd/picasso/acpi/pci_int.asl +++ b/src/soc/amd/picasso/acpi/pci_int.asl @@ -103,12 +103,13 @@ P3PR, 1, } - Method(_PIC, 0x01, NotSerialized) + Method(\_PIC, 0x01, NotSerialized) { If (Arg0) { \_SB.CIRQ() } + printf("PIC MODE: %o", Arg0) Store(Arg0, PMOD) } From 28d4275622dd66132b2849c09b33684dd6553ff1 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Mon, 9 Mar 2020 13:50:31 -0600 Subject: [PATCH 157/405] soc/amd/picasso/acpi: Improve PCI Interrupt Link Devices The PCI interrupt devices were only partially implemented. * Lacked support for _DIS to disable the bus. Something the kernel does while booting. * Lacked support for APIC vs PIC. This means the devices can only be used when using the PIC. By looking at the PMOD variable we can handle both PIC and APIC. This means we can stop hard coding the PCI interrupt numbers in the ACPI tables. * I removed INT[E-H] since they are not used. BUG=b:139429446, b:147042464 BRANCH=none TEST=Boot with both the APIC and PIC and saw that the link devices work as expected: PIC MODE: [ 1.959345] ACPI: PCI Interrupt Link [IRQA] (IRQs 1 3 4 5 *6 7 8 9 10 11 12 14 15) [ 2.007344] ACPI: PCI Interrupt Link [IRQB] (IRQs 1 3 4 5 *6 7 8 9 10 11 12 14 15) [ 2.056344] ACPI: PCI Interrupt Link [IRQC] (IRQs 1 3 4 5 6 7 8 9 10 11 12 *14 15) [ 2.104344] ACPI: PCI Interrupt Link [IRQD] (IRQs 1 3 4 5 6 7 8 9 10 11 12 14 *15) [ 13.752676] PCI Interrupt Link [IRQA] enabled at IRQ 6 [ 13.816755] PCI Interrupt Link [IRQD] enabled at IRQ 15 [ 27.788798] PCI Interrupt Link [IRQB] enabled at IRQ 6 [ 27.852873] PCI Interrupt Link [IRQC] enabled at IRQ 14 APIC MODE: [ 19.311764] ACPI: PCI Interrupt Link [IRQA] (IRQs *16 17 18 19 20 21 22 23) [ 19.374765] ACPI: PCI Interrupt Link [IRQB] (IRQs 16 *17 18 19 20 21 22 23) [ 19.438770] ACPI: PCI Interrupt Link [IRQC] (IRQs 16 17 *18 19 20 21 22 23) [ 19.501764] ACPI: PCI Interrupt Link [IRQD] (IRQs 16 17 18 *19 20 21 22 23) [ 34.719072] PCI Interrupt Link [IRQA] enabled at IRQ 23 [ 34.798994] PCI Interrupt Link [IRQD] enabled at IRQ 22 [ 66.469510] PCI Interrupt Link [IRQB] enabled at IRQ 21 [ 66.542395] PCI Interrupt Link [IRQC] enabled at IRQ 20 Change-Id: I1bb84813b65c89b4b5479602be3e9a9fedb7333d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2095683 Signed-off-by: Raul E Rangel Reviewed-on: https://review.coreboot.org/c/coreboot/+/41438 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/amd/picasso/acpi/northbridge.asl | 78 ++--- src/soc/amd/picasso/acpi/pci_int.asl | 427 +++++------------------ src/soc/amd/picasso/acpi/pcie.asl | 27 +- 3 files changed, 140 insertions(+), 392 deletions(-) diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl index 3227c7137a..f2a709f384 100644 --- a/src/soc/amd/picasso/acpi/northbridge.asl +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -18,60 +18,38 @@ Method(_STA, 0, NotSerialized) Return(0x0B) /* Status is visible */ } +/* PCI Routing Table */ +Name(PR0, Package(){ + /* Bus 0, Dev 0x00 - F2: IOMMU */ + Package() { 0x0000FFFF, 0, INTA, 0 }, + Package() { 0x0000FFFF, 0, INTB, 0 }, + Package() { 0x0000FFFF, 0, INTC, 0 }, + Package() { 0x0000FFFF, 0, INTD, 0 }, + + /* Bus 0, Dev 0x01 - F[1-7]: GPP PCI Bridges */ + Package() { 0x0001FFFF, 0, INTA, 0 }, + Package() { 0x0001FFFF, 1, INTB, 0 }, + Package() { 0x0001FFFF, 2, INTC, 0 }, + Package() { 0x0001FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 0x08 - F[1:PCI Bridge to Bus A, 2: PCI Bridge to Bus B] */ + Package() { 0x0008FFFF, 0, INTA, 0 }, + Package() { 0x0008FFFF, 1, INTB, 0 }, + Package() { 0x0008FFFF, 2, INTC, 0 }, + Package() { 0x0008FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 0x14 - F[0:SMBus 3:LPC] */ + Package() { 0x0014FFFF, 0, INTA, 0 }, + Package() { 0x0014FFFF, 1, INTB, 0 }, + Package() { 0x0014FFFF, 2, INTC, 0 }, + Package() { 0x0014FFFF, 3, INTD, 0 }, +}) + Method(_PRT,0, NotSerialized) { - If(PMOD) - { - Return(APR0) /* APIC mode */ - } - Return (PR0) /* PIC Mode */ + Return(PR0) } Device(AMRT) { Name(_ADR, 0x00000000) } /* end AMRT */ - -/* Gpp 0 */ -Device(PBR4) { - Name(_ADR, 0x00020001) - Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR4 */ - -/* Gpp 1 */ -Device(PBR5) { - Name(_ADR, 0x00020002) - Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR5 */ - -/* Gpp 2 */ -Device(PBR6) { - Name(_ADR, 0x00020003) - Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR6 */ - -/* Gpp 3 */ -Device(PBR7) { - Name(_ADR, 0x00020004) - Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR7 */ - -/* Gpp 4 */ -Device(PBR8) { - Name(_ADR, 0x00020005) - Method(_PRT,0) { - If(PMOD){ Return(APS8) } /* APIC mode */ - Return (PS8) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR8 */ diff --git a/src/soc/amd/picasso/acpi/pci_int.asl b/src/soc/amd/picasso/acpi/pci_int.asl index f89a14e795..bd72b22b47 100644 --- a/src/soc/amd/picasso/acpi/pci_int.asl +++ b/src/soc/amd/picasso/acpi/pci_int.asl @@ -116,342 +116,101 @@ Method(CIRQ, 0x00, NotSerialized){ } - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} + /* PIC Possible Resource Values */ + Name(IRQP, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveLow, Exclusive, , , PIC){ + 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15 + } }) - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} + /* IO-APIC Possible Resource Values */ + Name(IRQI, ResourceTemplate() { + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , APIC) { + 16, 17, 18, 19, 20, 21, 22, 23 + } }) - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) +#define PCI_LINK(DEV_NAME, PIC_REG, APIC_REG) \ + Device(DEV_NAME) { \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, 1) \ +\ + Method(_STA, 0) { \ + If (PMOD) { \ + local0=APIC_REG \ + } Else { \ + local0=PIC_REG \ + } \ +\ + If (local0 != 0x1f) { \ + printf("PCI: \\_SB.%s._STA: %o, Enabled", #DEV_NAME, local0) \ + /* Present, Enabled, Functional */ \ + Return(0x0b) \ + } else { \ + printf("PCI: \\_SB.%s._STA: %o, Disabled", #DEV_NAME, local0) \ + /* Present, Functional */ \ + Return(0x09) \ + } \ + } \ +\ + Method(_DIS ,0) { \ + If(PMOD) { \ + printf("PCI: \\_SB.%s._DIS APIC", #DEV_NAME) \ + APIC_REG=0x1f \ + } Else { \ + printf("PCI: \\_SB.%s._DIS PIC", #DEV_NAME) \ + PIC_REG=0x1f \ + } \ + } \ +\ + Method(_PRS ,0) { \ + If(PMOD) { \ + printf("PCI: \\_SB.%s._PRS => APIC", #DEV_NAME) \ + Return(IRQI) \ + } Else { \ + printf("PCI: \\_SB.%s._PRS => PIC", #DEV_NAME) \ + Return(IRQP) \ + } \ + } \ +\ + Method(_CRS ,0) { \ + local0=ResourceTemplate(){ \ + Interrupt ( \ + ResourceConsumer, \ + Level, \ + ActiveLow, \ + Exclusive, , , NUMB) \ + { 0 } \ + } \ + CreateDWordField(local0, NUMB._INT, IRQN) \ + If(PMOD) { \ + printf("PCI: \\_SB.%s._CRS APIC: %o", #DEV_NAME, APIC_REG) \ + IRQN=APIC_REG \ + } Else { \ + printf("PCI: \\_SB.%s._CRS PIC: %o", #DEV_NAME, PIC_REG) \ + IRQN=PIC_REG \ + } \ + If (IRQN == 0x1f) { \ + Return(ResourceTemplate(){}) \ + } Else { \ + Return(local0) \ + } \ + } \ +\ + Method(_SRS, 1) { \ + CreateWordField(ARG0, 0x5, IRQN) \ +\ + If(PMOD) { \ + printf("PCI: \\_SB.%s._SRS APIC: %o", #DEV_NAME, IRQN) \ + APIC_REG=IRQN \ + } Else { \ + printf("PCI: \\_SB.%s._SRS PIC: %o", #DEV_NAME, IRQN) \ + PIC_REG=IRQN \ + } \ + } \ + } - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PIRA) { - Return(0x0b) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRA, IRQN) - Return(IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_SRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRA) - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PIRB) { - Return(0x0b) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRB, IRQN) - Return(IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRB) - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PIRC) { - Return(0x0b) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRC, IRQN) - Return(IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRC) - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIRD) { - Return(0x0b) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRD, IRQN) - Return(IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRD) - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PIRE) { - Return(0x0b) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRE, IRQN) - Return(IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRE) - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PIRF) { - Return(0x0b) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRF, IRQN) - Return(IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRF) - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PIRG) { - Return(0x0b) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRG, IRQN) - Return(IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRG) - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PIRH) { - Return(0x0b) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRH, IRQN) - Return(IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRH) - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ +PCI_LINK(INTA, PIRA, IORA) +PCI_LINK(INTB, PIRB, IORB) +PCI_LINK(INTC, PIRC, IORC) +PCI_LINK(INTD, PIRD, IORD) diff --git a/src/soc/amd/picasso/acpi/pcie.asl b/src/soc/amd/picasso/acpi/pcie.asl index ecb54b9e16..2bbfec56e4 100644 --- a/src/soc/amd/picasso/acpi/pcie.asl +++ b/src/soc/amd/picasso/acpi/pcie.asl @@ -7,14 +7,25 @@ PRQD, 0x00000008, /* Offset: 1h */ } IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PIRA, 0x00000008, /* Index 0 */ - PIRB, 0x00000008, /* Index 1 */ - PIRC, 0x00000008, /* Index 2 */ - PIRD, 0x00000008, /* Index 3 */ - PIRE, 0x00000008, /* Index 4 */ - PIRF, 0x00000008, /* Index 5 */ - PIRG, 0x00000008, /* Index 6 */ - PIRH, 0x00000008, /* Index 7 */ + PIRA, 0x00000008, /* Index 0: INTA */ + PIRB, 0x00000008, /* Index 1: INTB */ + PIRC, 0x00000008, /* Index 2: INTC */ + PIRD, 0x00000008, /* Index 3: INTD */ + PIRE, 0x00000008, /* Index 4: INTE */ + PIRF, 0x00000008, /* Index 5: INTF */ + PIRG, 0x00000008, /* Index 6: INTG */ + PIRH, 0x00000008, /* Index 7: INTH */ + + /* IO-APIC IRQs */ + Offset (0x80), + IORA, 0x00000008, /* Index 0x80: INTA */ + IORB, 0x00000008, /* Index 0x81: INTB */ + IORC, 0x00000008, /* Index 0x82: INTC */ + IORD, 0x00000008, /* Index 0x83: INTD */ + IORE, 0x00000008, /* Index 0x84: INTE */ + IORF, 0x00000008, /* Index 0x85: INTF */ + IORG, 0x00000008, /* Index 0x86: INTG */ + IORH, 0x00000008, /* Index 0x87: INTH */ } /* PCI Error control register */ From 49b09a06a912952ec7a3063660370bdf732e4f48 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Thu, 20 Feb 2020 13:54:06 -0700 Subject: [PATCH 158/405] soc/amd/picasso: Add Kconfig option for the PSP bootloader filename Add option to change bootloader file. BUG=b:149934526 TEST=Change option and verify new bootloader file is used. Using the amd_blobs I can only boot using PspBootLoader_test_RV_dbg.sbin. Change-Id: Ib6597f7d4ffa0d48aead6974bd7111c987418f20 Signed-off-by: Martin Roth Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2067598 Signed-off-by: Raul E Rangel Reviewed-on: https://review.coreboot.org/c/coreboot/+/41436 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/amd/picasso/Kconfig | 12 +++++++++++- src/soc/amd/picasso/Makefile.inc | 8 ++++---- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 71630b8d9e..2578b468aa 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -341,10 +341,20 @@ config HAVE_PSP_WHITELIST_FILE If unsure, answer 'n' config PSP_WHITELIST_FILE - string "Debug whitelist file name" + string "Debug whitelist file path" depends on HAVE_PSP_WHITELIST_FILE default "3rdparty/amd_blobs/picasso/PSP/wtl-rvn.sbin" +config PSP_BOOTLOADER_FILE + string "Specify the PSP Bootloader file path" + default "3rdparty/amd_blobs/picasso/PSP/PspBootLoader_WL_RV.sbin" if HAVE_PSP_WHITELIST_FILE + default "3rdparty/amd_blobs/picasso/PSP/PspBootLoader_prod_RV.sbin" + help + Supply the name of the PSP bootloader file. + + Note that this option may conflict with the whitelist file if a + different PSP bootloader binary is specified. + config PSP_UNLOCK_SECURE_DEBUG bool "Unlock secure debug" default n diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 6fc834e56b..ef2b6b199e 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -105,11 +105,11 @@ PICASSO_FWM_POSITION=$(call int-add, \ FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) # type = 0x1 -ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) -PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_WL_RV.sbin -else -PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_RV.sbin +ifeq ($(CONFIG_PSP_BOOTLOADER_FILE),) +$(error CONFIG_PSP_BOOTLOADER_FILE was not defined) endif +PSPBTLDR_FILE=$(realpath $(call strip_quotes, $(CONFIG_PSP_BOOTLOADER_FILE))) +$(info Adding PSP $(shell md5sum $(PSPBTLDR_FILE))) # types = 0x8 and 0x12 PSP_SMUFW1_SUB1_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmwareRV2.csbin From eb72487784b19b77288dd7d589c0ffcc388dda33 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Tue, 16 Jul 2019 15:46:35 -0600 Subject: [PATCH 159/405] soc/amd/picasso: Add pcie root complex driver * Declare memory and reserved areas using HOBs for regions above top of low memory. * Copy northbridge_fill_ssdt_generator from stoneyridge. BUG=b:147042464 TEST=Boot trembyle and see PCI resources in the log: PCI: 00:00.0 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 2 PCI: 00:00.0 resource base 100000 size cd700000 align 0 gran 0 limit 0 flags e0004200 index 3 PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:00.0 resource base ce000000 size 2000000 align 0 gran 0 limit 0 flags f0004200 index 4 PCI: 00:00.0 resource base 100000000 size 12f340000 align 0 gran 0 limit 0 flags e0004200 index 5 PCI: 00:00.0 resource base 22f340000 size cc0000 align 0 gran 0 limit 0 flags f0004200 index 6 PCI: 00:00.0 resource base cd800000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 7 PCI: 00:00.0 resource base cd7fe000 size 2000 align 0 gran 0 limit 0 flags f0004200 index 8 PCI: 00:00.0 resource base cc7fe000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index 9 PCI: 00:00.0 resource base 1090000 size b0000 align 0 gran 0 limit 0 flags f0004200 index a Change-Id: I44a4a97765151fbcfe4c5d8de200e3e015aaaf2e Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/34424 Reviewed-by: Furquan Shaikh Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Makefile.inc | 1 + src/soc/amd/picasso/root_complex.c | 95 ++++++++++++++++++++++++++++++ 2 files changed, 96 insertions(+) create mode 100644 src/soc/amd/picasso/root_complex.c diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index ef2b6b199e..ed94cfb63a 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -44,6 +44,7 @@ ramstage-y += i2c.c ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += data_fabric_util.c +ramstage-y += root_complex.c ramstage-y += mca.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += gpio.c diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c new file mode 100644 index 0000000000..f621eeaf31 --- /dev/null +++ b/src/soc/amd/picasso/root_complex.c @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void read_resources(struct device *dev) +{ + uint32_t mem_usable = (uintptr_t)cbmem_top(); + unsigned int idx = 0; + const struct hob_header *hob = fsp_get_hob_list(); + const struct hob_resource *res; + + /* 0x0 - 0x9ffff */ + ram_resource(dev, idx++, 0, 0xa0000 / KiB); + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB); + + /* 0xc0000 - 0xfffff: Option ROM */ + reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); + + /* 1MB to top of low usable RAM */ + ram_resource(dev, idx++, 1 * MiB / KiB, (mem_usable - 1 * MiB) / KiB); + + mmconf_resource(dev, MMIO_CONF_BASE); + + if (!hob) { + printk(BIOS_ERR, "Error: %s incomplete because no HOB list was found\n", + __func__); + return; + } + + for (; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = fsp_next_hob(hob)) { + + if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR) + continue; + + res = fsp_hob_header_to_resource(hob); + + if (res->type == EFI_RESOURCE_SYSTEM_MEMORY && res->addr < mem_usable) + continue; /* 0 through low usable was set above */ + if (res->type == EFI_RESOURCE_MEMORY_MAPPED_IO) + continue; /* Done separately */ + + if (res->type == EFI_RESOURCE_SYSTEM_MEMORY) + ram_resource(dev, idx++, res->addr / KiB, res->length / KiB); + else if (res->type == EFI_RESOURCE_MEMORY_RESERVED) + reserved_ram_resource(dev, idx++, res->addr / KiB, res->length / KiB); + else + printk(BIOS_ERR, "Error: failed to set resources for type %d\n", + res->type); + } +} + +/* Used by \_SB.PCI0._CRS */ +static void root_complex_fill_ssdt(const struct device *device) +{ + msr_t msr; + + acpigen_write_scope(acpi_device_scope(device)); + + msr = rdmsr(TOP_MEM); + acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_pop_len(); +} + +static struct device_operations root_complex_operations = { + .read_resources = read_resources, + .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt = root_complex_fill_ssdt, +}; + +static const struct pci_driver family17_root_complex __pci_driver = { + .ops = &root_complex_operations, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB, +}; From 5434deaf2a32e12c8b640fc80486b72d13408c01 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 18 May 2020 12:35:18 -0700 Subject: [PATCH 160/405] soc/intel/common/block/acpi: Fix error in shift operation for GPCL CB:41454 updated northbridge.asl to ASL2.0 syntax. During this, GPCL was incorrectly updated to use << (ShiftLeft) instead of >> (ShiftRight). This change fixes the error in GPCL by updating it to use >> (ShiftRight). TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for hatch. Change-Id: I36469cb3b0bcc595acf0e43808d6a574986cad68 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41519 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/acpi/acpi/northbridge.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index 53b21881ae..bac059076a 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -229,7 +229,7 @@ Method (GPCB, 0, Serialized) /* Get PCIe Length */ Method (GPCL, 0, Serialized) { - Local0 = 0x10000000 << \_SB.PCI0.MCHC.PXSZ + Local0 = 0x10000000 >> \_SB.PCI0.MCHC.PXSZ Return (Local0) } From c336130c4467a94929c71a9cff1c28c2159ef21b Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 16 May 2020 21:38:33 -0700 Subject: [PATCH 161/405] soc/intel/skylake: Update systemagent.asl to ASL2.0 This change updates systemagent.asl to use ASL2.0 syntax. This increases the readability of the ASL code. TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for soraka. Change-Id: If8d8dd50af9a79d30f54e98f7f2fe7ce49188763 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41480 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/skylake/acpi/systemagent.asl | 42 +++++++++++----------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl index 6ea782b23f..b2e691ddf8 100644 --- a/src/soc/intel/skylake/acpi/systemagent.asl +++ b/src/soc/intel/skylake/acpi/systemagent.asl @@ -188,30 +188,30 @@ Method (_CRS, 0, Serialized) * Fix up PCI memory region * Start with Top of Lower Usable DRAM */ - Store (\_SB.PCI0.MCHC.TLUD, Local0) - Store (\_SB.PCI0.MCHC.MEBA, Local1) + Local0 = \_SB.PCI0.MCHC.TLUD + Local1 = \_SB.PCI0.MCHC.MEBA /* Check if ME base is equal */ - If (LEqual (Local0, Local1)) { + If (Local0 == Local1) { /* Use Top Of Memory instead */ - Store (\_SB.PCI0.MCHC.TOM, Local0) + Local0 = \_SB.PCI0.MCHC.TOM } Store (Local0, PMIN) - Add (Subtract (PMAX, PMIN), 1, PLEN) + PLEN = (PMAX - PMIN) + 1 /* Patch PM02 range based on Memory Size */ - If (LEqual (A4GS, 0)) { + If (A4GS == 0) { CreateQwordField (MCRS, PM02._LEN, MSEN) - Store (0, MSEN) + MSEN = 0 } Else { CreateQwordField (MCRS, PM02._MIN, MMIN) CreateQwordField (MCRS, PM02._MAX, MMAX) CreateQwordField (MCRS, PM02._LEN, MLEN) /* Set 64bit MMIO resource base and length */ - Store (A4GS, MLEN) - Store (A4GB, MMIN) - Subtract (Add (MMIN, MLEN), 1, MMAX) + MLEN = A4GS + MMIN = A4GB + MMAX = (MMIN + MLEN) - 1 } Return (MCRS) @@ -220,35 +220,35 @@ Method (_CRS, 0, Serialized) /* Get MCH BAR */ Method (GMHB, 0, Serialized) { - ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, Local0) + Local0 = \_SB.PCI0.MCHC.MHBR << 15 Return (Local0) } /* Get EP BAR */ Method (GEPB, 0, Serialized) { - ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, Local0) + Local0 = \_SB.PCI0.MCHC.EPBR << 12 Return (Local0) } /* Get PCIe BAR */ Method (GPCB, 0, Serialized) { - ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, Local0) + Local0 = \_SB.PCI0.MCHC.PXBR << 26 Return (Local0) } /* Get PCIe Length */ Method (GPCL, 0, Serialized) { - ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, Local0) + Local0 = 0x10000000 >> \_SB.PCI0.MCHC.PXSZ Return (Local0) } /* Get DMI BAR */ Method (GDMB, 0, Serialized) { - ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, Local0) + Local0 = \_SB.PCI0.MCHC.DIBR << 12 Return (Local0) } @@ -296,22 +296,22 @@ Device (PDRC) }) CreateDwordField (BUF0, MCHB._BAS, MBR0) - Store (\_SB.PCI0.GMHB (), MBR0) + MBR0 = \_SB.PCI0.GMHB () CreateDwordField (BUF0, DMIB._BAS, DBR0) - Store (\_SB.PCI0.GDMB (), DBR0) + DBR0 = \_SB.PCI0.GDMB () CreateDwordField (BUF0, EGPB._BAS, EBR0) - Store (\_SB.PCI0.GEPB (), EBR0) + EBR0 = \_SB.PCI0.GEPB () CreateDwordField (BUF0, PCIX._BAS, XBR0) - Store (\_SB.PCI0.GPCB (), XBR0) + XBR0 = \_SB.PCI0.GPCB () CreateDwordField (BUF0, PCIX._LEN, XSZ0) - Store (\_SB.PCI0.GPCL (), XSZ0) + XSZ0 = \_SB.PCI0.GPCL () CreateDwordField (BUF0, FIOH._BAS, FBR0) - Subtract(0x100000000, CONFIG_ROM_SIZE, FBR0) + FBR0 = 0x100000000 - CONFIG_ROM_SIZE Return (BUF0) } From 01750ef8d725895f984c0ae373bab83a925130f0 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 16 May 2020 21:41:35 -0700 Subject: [PATCH 162/405] soc/intel/skylake: Mask lower 20 bits of TOLUD and TOLM in systemagent.asl Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and 1 lock bit. If lock bit is set, then systemagent.asl would end up reporting the base address of low MMIO incorrectly i.e. off by 1. This change masks the lower 20 bits of TOLUD and TOM registers when exposing it in the ACPI tables to ensure that the base address of low MMIO region is reported correctly. Change-Id: I2ff7a30fabb7f77d13acadec1e6e4cb3a45b6139 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41470 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/skylake/acpi/systemagent.asl | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl index b2e691ddf8..962d9ef879 100644 --- a/src/soc/intel/skylake/acpi/systemagent.asl +++ b/src/soc/intel/skylake/acpi/systemagent.asl @@ -187,14 +187,20 @@ Method (_CRS, 0, Serialized) /* * Fix up PCI memory region * Start with Top of Lower Usable DRAM + * Lower 20 bits of TOLUD register need to be masked since they contain lock and + * reserved bits. */ - Local0 = \_SB.PCI0.MCHC.TLUD + Local0 = \_SB.PCI0.MCHC.TLUD & (0xfff << 20) Local1 = \_SB.PCI0.MCHC.MEBA /* Check if ME base is equal */ If (Local0 == Local1) { - /* Use Top Of Memory instead */ - Local0 = \_SB.PCI0.MCHC.TOM + /* + * Use Top Of Memory instead + * Lower 20 bits of TOM register need to be masked since they contain lock and + * reserved bits. + */ + Local0 = \_SB.PCI0.MCHC.TOM & (0x7ffff << 20) } Store (Local0, PMIN) From 6dc858a01ffceb897b597607f2004b9aad2f0ae7 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 16 May 2020 21:44:51 -0700 Subject: [PATCH 163/405] soc/intel/broadwell: Update systemagent.asl to ASL2.0 syntax This change updates systemagent.asl to use ASL2.0 syntax. This increases the readability of the ASL code. TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for auron. Change-Id: I479bb6cb7ed4c9265325c7c8621f03454f21f467 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41481 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons --- src/soc/intel/broadwell/acpi/systemagent.asl | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/soc/intel/broadwell/acpi/systemagent.asl b/src/soc/intel/broadwell/acpi/systemagent.asl index c73322ff81..74a25c15fb 100644 --- a/src/soc/intel/broadwell/acpi/systemagent.asl +++ b/src/soc/intel/broadwell/acpi/systemagent.asl @@ -147,18 +147,18 @@ Method (_CRS, 0, Serialized) // Fix up PCI memory region // Start with Top of Lower Usable DRAM - Store (^MCHC.TLUD, Local0) - Store (^MCHC.MEBA, Local1) + Local0 = ^MCHC.TLUD + Local1 = ^MCHC.MEBA // Check if ME base is equal - If (LEqual (Local0, Local1)) { + If (Local0 == Local1) { // Use Top Of Memory instead - Store (^MCHC.TOM, Local0) + Local0 = ^MCHC.TOM } - Store (Local0, PMIN) - Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) - Add(Subtract(PMAX, PMIN), 1, PLEN) + PMIN = Local0 + PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1 + PLEN = (PMAX - PMIN) + 1 Return (MCRS) } From 66b9c0efb52f8953e52add59c70646fa1ce1b867 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 16 May 2020 21:46:41 -0700 Subject: [PATCH 164/405] soc/intel/broadwell: Mask lower 20 bits of TOLUD and TOLM in systemagent.asl Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and 1 lock bit. If lock bit is set, then systemagent.asl would end up reporting the base address of low MMIO incorrectly i.e. off by 1. This change masks the lower 20 bits of TOLUD and TOM registers when exposing it in the ACPI tables to ensure that the base address of low MMIO region is reported correctly. Change-Id: I11b3ef8deda21930998471ab6e712da4c62f5b02 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41471 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/broadwell/acpi/systemagent.asl | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/broadwell/acpi/systemagent.asl b/src/soc/intel/broadwell/acpi/systemagent.asl index 74a25c15fb..258e6e7e7a 100644 --- a/src/soc/intel/broadwell/acpi/systemagent.asl +++ b/src/soc/intel/broadwell/acpi/systemagent.asl @@ -147,13 +147,17 @@ Method (_CRS, 0, Serialized) // Fix up PCI memory region // Start with Top of Lower Usable DRAM - Local0 = ^MCHC.TLUD + // Lower 20 bits of TOLUD register need to be masked since they contain lock and + // reserved bits. + Local0 = ^MCHC.TLUD & (0xfff << 20) Local1 = ^MCHC.MEBA // Check if ME base is equal If (Local0 == Local1) { // Use Top Of Memory instead - Local0 = ^MCHC.TOM + // Lower 20 bits of TOM register need to be masked since they contain lock and + // reserved bits. + Local0 = ^MCHC.TOM & (0x7ffff << 20) } PMIN = Local0 From 64e15aac1b003ffde8db9969657a21f54f6c20f2 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Wed, 29 Apr 2020 13:32:32 +1000 Subject: [PATCH 165/405] mb/google/hatch: Fix Puff variants rom size from 32768 -> 16384 KB Originally variants make use of a 32MB chip whereas now they use a 16MB SPI flash. Allow for the coordination of dealing with the transition between phases. V.2: Leave Puff alone at the moment due to the complexity of coordination. BUG=b:153682192 BRANCH=none TEST=none Change-Id: Ic336168ea1a0055c30f718f5540209d2cf69d029 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/40897 Reviewed-by: Sam McNally Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/Kconfig | 4 ++++ src/mainboard/google/hatch/Kconfig.name | 20 ++++++++++++++++++-- 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 8404eaa3f7..fc4424bd47 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -106,11 +106,13 @@ config MAINBOARD_PART_NUMBER default "Akemi" if BOARD_GOOGLE_AKEMI default "Dratini" if BOARD_GOOGLE_DRATINI default "Duffy" if BOARD_GOOGLE_DUFFY + default "Duffy" if BOARD_GOOGLE_DUFFY_LEGACY default "Hatch" if BOARD_GOOGLE_HATCH default "Helios" if BOARD_GOOGLE_HELIOS default "Helios_Diskswap" if BOARD_GOOGLE_HELIOS_DISKSWAP default "Jinlon" if BOARD_GOOGLE_JINLON default "Kaisa" if BOARD_GOOGLE_KAISA + default "Kaisa" if BOARD_GOOGLE_KAISA_LEGACY default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU default "Mushu" if BOARD_GOOGLE_MUSHU @@ -134,11 +136,13 @@ config VARIANT_DIR default "akemi" if BOARD_GOOGLE_AKEMI default "dratini" if BOARD_GOOGLE_DRATINI default "duffy" if BOARD_GOOGLE_DUFFY + default "duffy" if BOARD_GOOGLE_DUFFY_LEGACY default "hatch" if BOARD_GOOGLE_HATCH default "helios" if BOARD_GOOGLE_HELIOS default "helios" if BOARD_GOOGLE_HELIOS_DISKSWAP default "jinlon" if BOARD_GOOGLE_JINLON default "kaisa" if BOARD_GOOGLE_KAISA + default "kaisa" if BOARD_GOOGLE_KAISA_LEGACY default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU default "mushu" if BOARD_GOOGLE_MUSHU diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 6465854104..798438fd0e 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -10,10 +10,18 @@ config BOARD_GOOGLE_DRATINI select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 +config BOARD_GOOGLE_DUFFY_LEGACY + bool "-> Duffy Legacy (32MB)" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_32768 + select ROMSTAGE_SPD_SMBUS + select SPD_READ_BY_WORD + select VBOOT_EC_EFS + config BOARD_GOOGLE_DUFFY bool "-> Duffy" select BOARD_GOOGLE_BASEBOARD_HATCH - select BOARD_ROMSIZE_KB_32768 + select BOARD_ROMSIZE_KB_16384 select ROMSTAGE_SPD_SMBUS select SPD_READ_BY_WORD select VBOOT_EC_EFS @@ -29,10 +37,18 @@ config BOARD_GOOGLE_JINLON select BOARD_ROMSIZE_KB_16384 select DRIVERS_GFX_GENERIC +config BOARD_GOOGLE_KAISA_LEGACY + bool "-> Kaisa Legacy (32MB)" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_32768 + select ROMSTAGE_SPD_SMBUS + select SPD_READ_BY_WORD + select VBOOT_EC_EFS + config BOARD_GOOGLE_KAISA bool "-> Kaisa" select BOARD_GOOGLE_BASEBOARD_HATCH - select BOARD_ROMSIZE_KB_32768 + select BOARD_ROMSIZE_KB_16384 select ROMSTAGE_SPD_SMBUS select SPD_READ_BY_WORD select VBOOT_EC_EFS From 736024afdb9b89006a006996e6ed62bccc338c11 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Sun, 17 May 2020 22:10:53 +0200 Subject: [PATCH 166/405] Documentation: Encourage documentation with code changes The resource allocator woes post-4.12 release showed room for improvement on both discussion and documentation. To encourage this (and encourage reviewers to look out for issues in that space), extend the review guidelines so that they encourage to more clearly document the reason for a change with the change (commit message or our documentation) and also to loop in the mailing list. Change-Id: I1962dba3fe7e1a01fa4c8b0058297c7d050cb7b7 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/41493 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans Reviewed-by: Paul Menzel --- .../getting_started/gerrit_guidelines.md | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/getting_started/gerrit_guidelines.md b/Documentation/getting_started/gerrit_guidelines.md index 735ba3ba3d..59f675a2ff 100644 --- a/Documentation/getting_started/gerrit_guidelines.md +++ b/Documentation/getting_started/gerrit_guidelines.md @@ -254,6 +254,23 @@ commit message itself: The script 'util/gitconfig/rebase.sh' can be used to help automate this. Other tags such as 'Commit-Queue' can simply be removed. +* Check if there's documentation that needs to be updated to remain current +after your change. If there's no documentation for the part of coreboot +you're working on, consider adding some. + +* When contributing a significant change to core parts of the code base (such +as the boot state machine or the resource allocator), or when introducing +a new way of doing something that you think is worthwhile to apply across +the tree (e.g. board variants), please bring up your design on the [mailing +list](../community/forums.md). When changing behavior substantially, an +explanation of what changes and why may be useful to have, either in the +commit message or, if the discussion of the subject matter needs way more +space, in the documentation. Since "what we did in the past and why it isn't +appropriate anymore" isn't the most useful reading several years down the road, +such a description could be put into the release notes for the next version +(that you can find in Documentation/releases/) where it will inform people +now without cluttering up the regular documentation, and also gives a nice +shout-out to your contribution by the next release. Expectations contributors should have ------------------------------------- From 030037d3e92bd11a7a5062fb024fdbae9aa68622 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 19 May 2020 10:04:10 +0200 Subject: [PATCH 167/405] superio/winbond/w83977tf: Scope UART configuration defines more locally By undefining the configuration after use we're sure that nobody else comes to depend on it without us noticing. Change-Id: I7c5cfd58be643d6431989fc69cf3b397920590b9 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/41530 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/superio/winbond/w83977tf/acpi/superio.asl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/superio/winbond/w83977tf/acpi/superio.asl b/src/superio/winbond/w83977tf/acpi/superio.asl index 6e37a5bbc1..bd085e10cd 100644 --- a/src/superio/winbond/w83977tf/acpi/superio.asl +++ b/src/superio/winbond/w83977tf/acpi/superio.asl @@ -358,6 +358,8 @@ Device (ECP) #define SUPERIO_UART_LDN W83977TF_SP2 #define SUPERIO_UART_PM_REG UBPW #include + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_PM_REG #endif /* From 40d00ddcf2bac3d1f5f512a1ea0cc34089245d75 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Mon, 18 May 2020 12:36:35 +0800 Subject: [PATCH 168/405] mb/google/deltaur: Add low power idle table Add low power idle table to notify EC system is entering s0ix. BUG=none TEST=Power button and keyboard backlight are off when suspending. Signed-off-by: Eric Lai Change-Id: Icf4dffe2bd289c15854bbad914c3b34b307254ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/41494 Reviewed-by: Tim Wawrzynczak Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/google/deltaur/dsdt.asl | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/deltaur/dsdt.asl b/src/mainboard/google/deltaur/dsdt.asl index b439d06793..fe86e15b45 100644 --- a/src/mainboard/google/deltaur/dsdt.asl +++ b/src/mainboard/google/deltaur/dsdt.asl @@ -34,6 +34,9 @@ DefinitionBlock( /* VPD support */ #include + /* Low power idle table */ + #include + /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { From 8952de55cb4949969b09219fdf6b9b14f3b59b0c Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Mon, 18 May 2020 15:01:06 +0900 Subject: [PATCH 169/405] driver/i2c/max98390: Fix build error related to max98390 driver Fix coreboot build error with adding this driver BUG=b:149443429 BRANCH=None TEST=built without errors Signed-off-by: Seunghwan Kim Change-Id: I2d76ec72ca6ae9ac54ab05f15ea92beb645acd5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41496 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Furquan Shaikh --- src/drivers/i2c/max98390/max98390.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/drivers/i2c/max98390/max98390.c b/src/drivers/i2c/max98390/max98390.c index c8d7699d0b..24c500bd2e 100644 --- a/src/drivers/i2c/max98390/max98390.c +++ b/src/drivers/i2c/max98390/max98390.c @@ -15,7 +15,7 @@ #define MAX98390_DP_INT(key, val) acpi_dp_add_integer(dp, "maxim," key, (val)) -static void max98390_fill_ssdt(struct device *dev) +static void max98390_fill_ssdt(const struct device *dev) { struct drivers_i2c_max98390_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); @@ -86,7 +86,7 @@ static struct device_operations max98390_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .acpi_name = max98390_acpi_name, - .acpi_fill_ssdt_generator = max98390_fill_ssdt, + .acpi_fill_ssdt = max98390_fill_ssdt, }; static void max98390_enable(struct device *dev) From a2789328f77c5b47006f4a48f59f278e699821dc Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Mon, 18 May 2020 11:00:04 +0530 Subject: [PATCH 170/405] soc/intel/common/acpi: Remove gpio community range Remove hardcoded gpio community range, since it might differ across the SOCs. Change-Id: I79c10669f6096537d466d1abd356d58a50fcb8f5 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/41500 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Karthik Ramasubramanian --- src/soc/intel/common/acpi/gpio.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/common/acpi/gpio.asl b/src/soc/intel/common/acpi/gpio.asl index cac3449352..dbfa7af980 100644 --- a/src/soc/intel/common/acpi/gpio.asl +++ b/src/soc/intel/common/acpi/gpio.asl @@ -3,7 +3,7 @@ /* * Configure GPIO Power Management bits * - * Arg0: GPIO community (0-5) + * Arg0: GPIO community index * Arg1: PM bits in MISCCFG */ Method (CGPM, 2, Serialized) From 88712991ba390c309b4586864aa04a9680fd8320 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Mon, 18 May 2020 11:11:19 +0530 Subject: [PATCH 171/405] soc/intel/jasperlake: Add ACPI method to get GPIO PCR PID Add method acpi method GPID to return the GPIO PCR port ID. This method is further planned to be used for GPIO power management configuration. TEST=Build waddledoo board Change-Id: Ic45b40bbe39e303cddcc82e0e848786b7311ab64 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/41501 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/soc/intel/jasperlake/acpi/gpio.asl | 34 ++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/src/soc/intel/jasperlake/acpi/gpio.asl b/src/soc/intel/jasperlake/acpi/gpio.asl index d8326c7789..60951f0b6b 100644 --- a/src/soc/intel/jasperlake/acpi/gpio.asl +++ b/src/soc/intel/jasperlake/acpi/gpio.asl @@ -6,6 +6,8 @@ #include #include "gpio_op.asl" +#include + Device (GPIO) { Name (_HID, CROS_GPIO_NAME) @@ -103,3 +105,35 @@ Method (GADD, 1, NotSerialized) Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16) Return (Local2) } + +/* + * Return PCR Port ID of GPIO Communities + * + * Arg0: GPIO Community (0-5) + */ +Method (GPID, 1, Serialized) +{ + Switch (ToInteger (Arg0)) + { + Case (0) { + Local0 = PID_GPIOCOM0 + } + Case (1) { + Local0 = PID_GPIOCOM1 + } + Case (2) { + Local0 = PID_GPIOCOM2 + } + Case (4) { + Local0 = PID_GPIOCOM4 + } + Case (5) { + Local0 = PID_GPIOCOM5 + } + Default { + Return (0) + } + } + + Return (Local0) +} From 38c308515c4a983f361d287a3cbeec3ee36c52ae Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Mon, 18 May 2020 17:46:14 +0800 Subject: [PATCH 172/405] mb/google/deltaur: Add tcss.asl Add tcss.asl to support TCSS power management. For the detail please refer cb:39785. BUG=none TEST=Check TBT PCIe root ports: 00:07.0/00:07.1/00:07.2/00:07.3 /sys/bus/pci/devices/bus:device:func/power suspend and active time can increase. Signed-off-by: Eric Lai Change-Id: I432f3d6643de13b08c07e47f799c0ecdfe047de6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41506 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/deltaur/dsdt.asl | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/deltaur/dsdt.asl b/src/mainboard/google/deltaur/dsdt.asl index fe86e15b45..fac58bdf42 100644 --- a/src/mainboard/google/deltaur/dsdt.asl +++ b/src/mainboard/google/deltaur/dsdt.asl @@ -25,6 +25,7 @@ DefinitionBlock( { #include #include + #include } } From af417b4143a689546b43ba106c2bd4a7d02053dc Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Mon, 18 May 2020 12:41:28 +0800 Subject: [PATCH 173/405] mb/google/deltaur: Remove WLAN PCIE setting Deltaur uses CNVi WLAN module, this setting is not required. BUG=none TEST=WiFi is functional in OS. Signed-off-by: Eric Lai Change-Id: Idb23e271074c8d1e111c559695d4169af5e0d3cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/41495 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../google/deltaur/variants/baseboard/devicetree.cb | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index b2062cbd07..7350319b22 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -51,11 +51,6 @@ chip soc/intel/tigerlake register "usb3_ports[2]" = "USB3_PORT_EMPTY" register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN - # PCIe root port 6 (WLAN), clock 1 - register "PcieRpEnable[5]" = "1" - register "PcieClkSrcUsage[1]" = "5" - register "PcieClkSrcClkReq[1]" = "1" - # PCIe root port 7 (Card Reader), clock 4 register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[4]" = "6" @@ -286,7 +281,7 @@ chip soc/intel/tigerlake device pci 1c.2 off end # PCIe Root Port #3 () device pci 1c.3 off end # PCIe Root Port #4 (WWAN) device pci 1c.4 on end # PCIe Root Port #5 (LTE) - device pci 1c.5 on end # PCIe Root Port #6 (WiFi) + device pci 1c.5 off end # PCIe Root Port #6 (WiFi) device pci 1c.6 on end # PCIe Root Port #7 (Card reader) device pci 1c.7 on chip drivers/net From b9907042d424ba6b974574240c20a40fb23b3509 Mon Sep 17 00:00:00 2001 From: Caveh Jalali Date: Tue, 5 May 2020 20:47:21 -0700 Subject: [PATCH 174/405] mb/google/volteer: Enable EARLY_EC_SYNC This enables EC software sync in romstage. BUG=b:148259137 TEST=verified EC is updated in romstage using coreboot serial console logs. Change-Id: Ibb97c1d57220f7fd74131a5aee450b1ab4b1c982 Signed-off-by: Caveh Jalali Reviewed-on: https://review.coreboot.org/c/coreboot/+/41078 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index de77633153..f6ff42c652 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -30,6 +30,7 @@ config CHROMEOS select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH + select VBOOT_EARLY_EC_SYNC config DIMM_SPD_SIZE int From 71d365d4583064da85e3f6544e2fbd385cf1e8b3 Mon Sep 17 00:00:00 2001 From: Brandon Breitenstein Date: Mon, 6 Apr 2020 15:31:34 -0700 Subject: [PATCH 175/405] soc/tigerlake: Add devicetree configurability for IomTypeCPortPadCfg In order for the SOC to be able to control the Aux line orientation for Type-C ports that do not have a retimer, the IomTypeCPortPadCfg UPD needs to be configurable through devicetree to correctly set the GPIO pins that the SOC should use to flip orientation. BUG=b:145220205 BRANCH=NONE TEST=booted Volteer proto 2 and verified that the AUX channels flip when the cable is flipped Change-Id: I2e48adb624c7922170eafb8dfcaed680f008936e Signed-off-by: Brandon Breitenstein Reviewed-on: https://review.coreboot.org/c/coreboot/+/40244 Reviewed-by: Caveh Jalali Reviewed-by: Nick Vaccaro Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/chip.h | 13 +++++++++++++ src/soc/intel/tigerlake/fsp_params.c | 2 +- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 3047037183..a32cebe594 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -221,6 +221,19 @@ struct soc_intel_tigerlake_config { uint8_t TcssDma0En; uint8_t TcssDma1En; + /* + * IOM Port Config + * If a port orientation needs to be controlled by the SOC this setting must be + * updated to reflect the correct GPIOs being used for the SOC port flipping. + * There are 4 ports each with a pair of GPIOs for Pull Up and Pull Down + * 0,1 are pull up and pull down for port 0 + * 2,3 are pull up and pull down for port 1 + * 4,5 are pull up and pull down for port 2 + * 6,7 are pull up and pull down for port 3 + * values to be programmed correspond to the GPIO family and offsets + */ + uint32_t IomTypeCPortPadCfg[8]; + /* * SOC Aux orientation override: * This is a bitfield that corresponds to up to 4 TCSS ports on TGL. diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 73c41c8519..cf106cbe16 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -103,7 +103,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->TcssAuxOri = config->TcssAuxOri; for (i = 0; i < 8; i++) - params->IomTypeCPortPadCfg[i] = 0x09000000; + params->IomTypeCPortPadCfg[i] = config->IomTypeCPortPadCfg[i]; /* Chipset Lockdown */ if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { From b7911c8e98f493d29acedaf1542f98ad76700f00 Mon Sep 17 00:00:00 2001 From: Brandon Breitenstein Date: Mon, 6 Apr 2020 15:34:19 -0700 Subject: [PATCH 176/405] mainboard/volteer: Update Aux settings for Port 0 On Volteer port 0 (MB PORT) does not have a retimer so the port needs to be configured for the SOC to handle Aux orientation flipping. This requires 2 changes setting the TcssAuxOri UPD to 1 for port 0 (Bit 0) and configuring AUXP and AUXN GPIOs to Native Function 6 so SOC can control the orientation BUG=b:145220205 BRANCH=NONE TEST=booted Volteer proto 2 and verified that the AUX channels flip when the cable is flipped Change-Id: Ic81adc24d10322cc305bf0fa4c38514468ea0942 Signed-off-by: Brandon Breitenstein Reviewed-on: https://review.coreboot.org/c/coreboot/+/40245 Tested-by: build bot (Jenkins) Reviewed-by: Caveh Jalali Reviewed-by: Wonkyu Kim --- .../google/volteer/variants/baseboard/devicetree.cb | 11 ++++++++++- .../google/volteer/variants/baseboard/gpio.c | 4 ++-- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 273b7a8ccc..fa99de8c8f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -125,7 +125,16 @@ chip soc/intel/tigerlake # TCSS USB3 register "TcssXhciEn" = "1" - register "TcssAuxOri" = "0" + register "TcssAuxOri" = "1" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + register "IomTypeCPortPadCfg[2]" = "0x0" + register "IomTypeCPortPadCfg[3]" = "0x0" + register "IomTypeCPortPadCfg[4]" = "0x0" + register "IomTypeCPortPadCfg[5]" = "0x0" + register "IomTypeCPortPadCfg[6]" = "0x0" + register "IomTypeCPortPadCfg[7]" = "0x0" + # DP port register "DdiPortAConfig" = "1" # eDP diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index 2ca59aa29d..8cbda1c0cb 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -215,13 +215,13 @@ static const struct pad_config gpio_table[] = { /* E9 : USB2_OC0# ==> USB_C1_OC_ODL */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* E10 : SPI1_CS# ==> USB_C0_AUXP_DC */ - PAD_CFG_GPO(GPP_E10, 0, DEEP), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF6), /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ PAD_CFG_GPI(GPP_E11, NONE, DEEP), /* E12 : SPI1_MISO_IO1 ==> NOT USED */ PAD_NC(GPP_E12, NONE), /* E13 : SPI1_MOSI_IO0 ==> USB_C0_AUXN_DC */ - PAD_CFG_GPO(GPP_E13, 0, DEEP), + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF6), /* E14 : DDPC_HPDA ==> SOC_EDP_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ From 425d8640fa3d8e4a43bd9f2cc8f8fd7fedf675c3 Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Fri, 8 May 2020 21:01:31 +0530 Subject: [PATCH 177/405] icelake: remove unused processor power limits configuration Remove unused processor power limit configuration parameter and function call based on common code base support for Intel Icelake SoC based platform. BRANCH=None BUG=None TEST=Built for icelake based dragonegg board. Change-Id: Id8923f2c176092b6f7acfbfb079587f88258dce8 Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/41236 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/icelake/chip.h | 2 -- src/soc/intel/icelake/include/soc/cpu.h | 3 --- 2 files changed, 5 deletions(-) diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index d67a70c3dc..2b190cd5df 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -171,8 +171,6 @@ struct soc_intel_icelake_config { /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* PL2 Override value in Watts */ - uint32_t tdp_pl2_override; /* Intel Speed Shift Technology */ uint8_t speed_shift_enable; /* Enable VR specific mailbox command diff --git a/src/soc/intel/icelake/include/soc/cpu.h b/src/soc/intel/icelake/include/soc/cpu.h index e0f3e52a1a..a23133367e 100644 --- a/src/soc/intel/icelake/include/soc/cpu.h +++ b/src/soc/intel/icelake/include/soc/cpu.h @@ -30,7 +30,4 @@ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ (IRTL_1024_NS >> 10)) -/* Configure power limits for turbo mode */ -void set_power_limits(u8 power_limit_1_time); - #endif From d2132469ae86d7287576a2ba3211cdbfeb572703 Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Fri, 15 May 2020 15:55:37 +0530 Subject: [PATCH 178/405] tigerlake: update processor power limits configuration Update processor power limit configuration parameters based on common code base support for Intel Tigerlake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on volteer system Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/39345 Reviewed-by: Wonkyu Kim Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/Kconfig | 1 + src/soc/intel/tigerlake/chip.h | 7 +++++-- src/soc/intel/tigerlake/include/soc/cpu.h | 3 --- src/soc/intel/tigerlake/systemagent.c | 12 ++++++++++++ 4 files changed, 18 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index a690acf9dc..a55b543100 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -53,6 +53,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_CAR + select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index a32cebe594..2e3591f4a6 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +27,9 @@ struct soc_intel_tigerlake_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; + /* Common struct containing power limits configuration information */ + struct soc_power_limits_config power_limits_config; + /* Gpio group routed to each dword of the GPE0 block. Values are * of the form PMC_GPP_[A:U] or GPD. */ uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ @@ -144,8 +148,7 @@ struct soc_intel_tigerlake_config { /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* PL2 Override value in Watts */ - uint32_t tdp_pl2_override; + /* Intel Speed Shift Technology */ uint8_t speed_shift_enable; diff --git a/src/soc/intel/tigerlake/include/soc/cpu.h b/src/soc/intel/tigerlake/include/soc/cpu.h index fb3441db8c..28dfb386c9 100644 --- a/src/soc/intel/tigerlake/include/soc/cpu.h +++ b/src/soc/intel/tigerlake/include/soc/cpu.h @@ -24,7 +24,4 @@ /* Common Timer Copy (CTC) frequency - 38.4MHz. */ #define CTC_FREQ 38400000 -/* Configure power limits for turbo mode */ -void set_power_limits(u8 power_limit_1_time); - #endif diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index 4cdca50410..977c6674e7 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -7,10 +7,13 @@ */ #include +#include #include #include +#include #include #include +#include #include /* @@ -60,9 +63,18 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) */ void soc_systemagent_init(struct device *dev) { + struct soc_power_limits_config *soc_config; + config_t *config; + /* Enable Power Aware Interrupt Routing */ enable_power_aware_intr(); /* Enable BIOS Reset CPL */ enable_bios_reset_cpl(); + + /* Configure turbo power limits 1ms after reset complete bit */ + mdelay(1); + config = config_of_soc(); + soc_config = &config->power_limits_config; + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); } From 17118a833a2df130ed24c2547ca903cac9fac0e0 Mon Sep 17 00:00:00 2001 From: Daniel Kang Date: Thu, 7 May 2020 17:41:22 -0700 Subject: [PATCH 179/405] mb/google/volteer: Fix camera dsdt config for ov2740 Link frequency and a format was not correct for volteer proto 2 ov2740 user-facing camera. The link frequency is calculated in the following way. (max frame width * max frame height * max fps * data format in bps / number of lanes / data rate) + max 35% of overhead For ov2740, (1920 * 1080 * 60 * 10 / 2 / 2) = 311Mhz. 360Mhz after adding 18% of overhead. BUG=b:148428976 BRANCH=none TEST=Build and boot volteer proto 2 board. Start a camera app and check user-facing camera functionalities. Signed-off-by: Daniel Kang Change-Id: I3b51826e123dec394c1b4eb9a1c5b64b8b11459e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41157 Reviewed-by: Paul Menzel Reviewed-by: Dossym Nurmukhanov Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- .../variants/baseboard/include/baseboard/acpi/mipi_camera.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl index 92c0339050..777ab7aa74 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl @@ -124,7 +124,7 @@ Scope (\_SB.PCI0.IPU0) Package (0x02) { "data-lanes", - Package (0x04) + Package (0x02) { One, 0x02 @@ -582,7 +582,7 @@ Scope (\_SB.PCI0.I2C2) "link-frequencies", Package (0x01) { - 0xABA9500 + 0x15752A00 } }, Package (0x02) From dbcf7b16219df0c04401b8fcd6a780174a7df305 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Wed, 13 May 2020 16:15:08 -0600 Subject: [PATCH 180/405] device/pci_device: Add notion of "hidden" PCI devices On some SoCs, there are PCI devices that may get hidden from PCI enumeration by platform firmware. Because the Vendor ID reads back as 0xffffffff, it appears that there is no PCI device located at that BDF. However, because the device does exist, designers may wish to hang its PCI resources off of a real __pci_driver, as well as have it participate in ACPI table generation. This patch extends the semantics of the 'hidden' keyword in devicetree.cb. If a device now uses 'hidden' instead of 'on', then it will be assumed during PCI enumeration that the device indeed does exist, and it will not be removed as a "leftover device." This allows child devices to be enumerated correctly and also PCI resources can be designated from the {read,set}_resources callbacks. It should be noted that as of this commit, there are precisely 0 devices using 'hidden' in their devicetree.cb files, so this should be a safe thing to do. Later patches will begin moving PCI resources from random places (typically hung off of fixed SA and LPC) into the PMC device (procedure will vary per- platform). Change-Id: I16c2d3e1d1433343e63dfc16856cff69cd815e2a Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/41384 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/device/pci_device.c | 63 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 61 insertions(+), 2 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 689325d2a9..5f50a31460 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -778,6 +778,13 @@ struct device_operations default_pci_ops_bus = { .reset_bus = pci_bus_reset, }; +/** Default device operations for PCI devices marked 'hidden' */ +static struct device_operations default_hidden_pci_ops_dev = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .scan_bus = scan_static_bus, +}; + /** * Check for compatibility to route legacy VGA cycles through a bridge. * @@ -1146,6 +1153,46 @@ unsigned int pci_match_simple_dev(struct device *dev, pci_devfn_t sdev) dev->path.pci.devfn == PCI_DEV2DEVFN(sdev); } +/** + * PCI devices that are marked as "hidden" do not get probed. However, the same + * initialization logic is still performed as if it were. This is useful when + * devices would like to be described in the devicetree.cb file, and/or present + * static PCI resources to the allocator, but the platform firmware hides the + * device (makes the device invisible to PCI enumeration) before PCI enumeration + * takes place. + * + * The expected semantics of PCI devices marked as 'hidden': + * 1) The device is actually present under the specified BDF + * 2) The device config space can still be accessed somehow, but the Vendor ID + * indicates there is no device there (it reads as 0xffffffff). + * 3) The device may still consume PCI resources. Typically, these would have + * been hardcoded elsewhere. + * + * @param dev Pointer to the device structure. + */ +static void pci_scan_hidden_device(struct device *dev) +{ + if (dev->chip_ops && dev->chip_ops->enable_dev) + dev->chip_ops->enable_dev(dev); + + /* + * If chip_ops->enable_dev did not set dev->ops, then set to a default + * .ops, because PCI enumeration is effectively being skipped, therefore + * no PCI driver will bind to this device. However, children may want to + * be enumerated, so this provides scan_static_bus for the .scan_bus + * callback. + */ + if (dev->ops == NULL) + dev->ops = &default_hidden_pci_ops_dev; + + if (dev->ops->enable) + dev->ops->enable(dev); + + /* Display the device almost as if it were probed normally */ + printk(BIOS_DEBUG, "%s [0000/%04x] hidden%s\n", dev_path(dev), + dev->device, dev->ops ? "" : " No operations"); +} + /** * Scan a PCI bus. * @@ -1190,6 +1237,14 @@ void pci_scan_bus(struct bus *bus, unsigned int min_devfn, /* First thing setup the device structure. */ dev = pci_scan_get_dev(bus, devfn); + /* Devices marked 'hidden' do not get probed */ + if (dev && dev->hidden) { + pci_scan_hidden_device(dev); + + /* Skip pci_probe_dev, go to next devfn */ + continue; + } + /* See if a device is present and setup the device structure. */ dev = pci_probe_dev(dev, bus, devfn); @@ -1213,8 +1268,12 @@ void pci_scan_bus(struct bus *bus, unsigned int min_devfn, prev = &bus->children; for (dev = bus->children; dev; dev = dev->sibling) { - /* If we read valid vendor id, it is not leftover device. */ - if (dev->vendor != 0) { + /* + * The device is only considered leftover if it is not hidden + * and it has a Vendor ID of 0 (the default for a device that + * could not be probed). + */ + if (dev->vendor != 0 || dev->hidden) { prev = &dev->sibling; continue; } From 6d20d0c1400a07b8ca3d709693263dbc45ca564f Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Wed, 13 May 2020 17:00:33 -0600 Subject: [PATCH 181/405] soc/intel/tigerlake: Move PMC PCI resources under PMC device Historically in coreboot, the PMC's fixed PCI resources were described by the System Agent (the MMIO resource), and eSPI/LPC (the I/O resource). This patch moves both of those to a new Intel SoC-specific function, soc_pmc_read_resources(). On TGL, this new function takes care of providing the MMIO and I/O resources for the PMC. BUG=b:156388055 TEST=verified on volteer that the resource allocator is aware of and does not touch these two resources: ("PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1") Also verify that the MEM resource is described in the coreboot table: ("BIOS-e820: [mem 0x00000000fe000000-0x00000000fe00ffff] reserved") Verified the memory range is also untouchable from Linux: ("system 00:00: [mem 0xfe000000-0xffffffff] could not be reserved") Change-Id: Ia7c6ae849aefaf549fb682416a87320907fb3fe3 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/41385 Reviewed-by: Duncan Laurie Reviewed-by: Furquan Shaikh Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- .../deltaur/variants/baseboard/devicetree.cb | 2 +- .../volteer/variants/baseboard/devicetree.cb | 10 +++--- .../tglrvp/variants/tglrvp_up3/devicetree.cb | 2 +- .../tglrvp/variants/tglrvp_up4/devicetree.cb | 2 +- src/soc/intel/tigerlake/chip.c | 9 +++++- src/soc/intel/tigerlake/espi.c | 17 ---------- src/soc/intel/tigerlake/include/soc/pmc.h | 4 +++ src/soc/intel/tigerlake/pmc.c | 31 +++++++++++++------ src/soc/intel/tigerlake/systemagent.c | 11 ------- 9 files changed, 42 insertions(+), 46 deletions(-) diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 7350319b22..8d847f73fc 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -305,7 +305,7 @@ chip soc/intel/tigerlake end end # eSPI device pci 1f.1 off end # P2SB - device pci 1f.2 on end # PMC + device pci 1f.2 hidden end # PMC device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI Flash Controller diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index fa99de8c8f..5d5dcc4b70 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -370,7 +370,7 @@ chip soc/intel/tigerlake register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)" device spi 0 on end end - end # GSPI0 0xA0AA + end # GSPI0 0xA0AA device pci 1e.3 on chip drivers/spi/acpi register "name" = ""CRFP"" @@ -380,14 +380,14 @@ chip soc/intel/tigerlake register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_C20)" device spi 0 on end end # FPMCU - end # GSPI1 0xA0AB + end # GSPI1 0xA0AB device pci 1f.0 on chip ec/google/chromeec device pnp 0c09.0 on end end - end # eSPI 0xA080 - A09F + end # eSPI 0xA080 - A09F device pci 1f.1 off end # P2SB 0xA0A0 - device pci 1f.2 on end # PMC 0xA0A1 + device pci 1f.2 hidden end # PMC 0xA0A1 device pci 1f.3 on chip drivers/generic/max98357a register "hid" = ""MX98357A"" @@ -395,7 +395,7 @@ chip soc/intel/tigerlake register "sdmode_delay" = "5" device generic 0 on end end - end # Intel HD audio 0xA0C8-A0CF + end # Intel HD audio 0xA0C8-A0CF device pci 1f.4 off end # SMBus 0xA0A3 device pci 1f.5 on end # SPI 0xA0A4 device pci 1f.6 off end # GbE 0x15E1/0x15E2 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 82f358e8b6..045dc89e4d 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -243,7 +243,7 @@ chip soc/intel/tigerlake device pci 1e.3 off end # GSPI1 0xA0AB device pci 1f.0 on end # eSPI 0xA080 - A09F device pci 1f.1 on end # P2SB 0xA0A0 - device pci 1f.2 on end # PMC 0xA0A1 + device pci 1f.2 hidden end # PMC 0xA0A1 device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF device pci 1f.4 on end # SMBus 0xA0A3 device pci 1f.5 on end # SPI 0xA0A4 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index fec2fefa16..83b6c0ae0c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -239,7 +239,7 @@ chip soc/intel/tigerlake device pci 1e.3 off end # GSPI1 0xA0AB device pci 1f.0 on end # eSPI 0xA080 - A09F device pci 1f.1 on end # P2SB 0xA0A0 - device pci 1f.2 on end # PMC 0xA0A1 + device pci 1f.2 hidden end # PMC 0xA0A1 device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF device pci 1f.4 on end # SMBus 0xA0A3 device pci 1f.5 on end # SPI 0xA0A4 diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index c1764cde93..a923074acc 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -151,11 +152,17 @@ static struct device_operations cpu_bus_ops = { static void soc_enable(struct device *dev) { - /* Set the operations if it is a special bus type */ + /* + * Set the operations if it is a special bus type or a hidden PCI + * device. + */ if (dev->path.type == DEVICE_PATH_DOMAIN) dev->ops = &pci_domain_ops; else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) dev->ops = &cpu_bus_ops; + else if (dev->path.type == DEVICE_PATH_PCI && + dev->path.pci.devfn == PCH_DEVFN_PMC) + dev->ops = &pmc_ops; } struct chip_operations soc_intel_tigerlake_ops = { diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index ed8481a389..8cc83036d5 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -197,21 +197,4 @@ void lpc_soc_init(struct device *dev) soc_mirror_dmi_pcr_io_dec(); } -/* Fill up ESPI IO resource structure inside SoC directory */ -void pch_lpc_soc_fill_io_resources(struct device *dev) -{ - /* - * PMC pci device gets hidden from PCI bus due to Silicon - * policy hence bind ACPI BASE aka ABASE (offset 0x20) with - * ESPI IO resources to ensure that ABASE falls under PCI reserved - * IO memory range. - * - * Note: Don't add any more resource with same offset 0x20 - * under this device space. - */ - pch_lpc_add_new_resource(dev, PCI_BASE_ADDRESS_4, - ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, IORESOURCE_IO | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED); -} - #endif diff --git a/src/soc/intel/tigerlake/include/soc/pmc.h b/src/soc/intel/tigerlake/include/soc/pmc.h index 3b58a74b6d..0f72833fbe 100644 --- a/src/soc/intel/tigerlake/include/soc/pmc.h +++ b/src/soc/intel/tigerlake/include/soc/pmc.h @@ -3,6 +3,10 @@ #ifndef _SOC_TIGERLAKE_PMC_H_ #define _SOC_TIGERLAKE_PMC_H_ +#include + +extern struct device_operations pmc_ops; + /* PCI Configuration Space (D31:F2): PMC */ #define PWRMBASE 0x10 #define ABASE 0x20 diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 136f1030a3..fa59d467e2 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -75,7 +75,7 @@ static void config_deep_sx(uint32_t deepsx_config) write32(pmcbase + DSX_CFG, reg); } -static void pmc_init(void *unused) +static void pmc_init(struct device *dev) { const config_t *config = config_of_soc(); @@ -91,11 +91,24 @@ static void pmc_init(void *unused) config_deep_sx(config->deep_sx_config); } -/* -* Initialize PMC controller. -* -* PMC controller gets hidden from PCI bus during FSP-Silicon init call. -* Hence PCI enumeration can't be used to initialize bus device and -* allocate resources. -*/ -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pmc_init, NULL); +static void soc_pmc_read_resources(struct device *dev) +{ + struct resource *res; + + /* Add the fixed MMIO resource */ + mmio_resource(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB); + + /* Add the fixed I/O resource */ + res = new_resource(dev, 1); + res->base = (resource_t)ACPI_BASE_ADDRESS; + res->size = (resource_t)ACPI_BASE_SIZE; + res->limit = res->base + res->size - 1; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +struct device_operations pmc_ops = { + .read_resources = soc_pmc_read_resources, + .set_resources = noop_set_resources, + .enable = pmc_init, + .scan_bus = scan_static_bus, +}; diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index 977c6674e7..8c0a42a71a 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -32,17 +32,6 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, - /* - * PMC pci device gets hidden from PCI bus due to Silicon - * policy hence binding PMCBAR aka PWRMBASE (offset 0x10) with - * SA resources to ensure that PMCBAR falls under PCI reserved - * memory range. - * - * Note: Don't add any more resource with same offset 0x10 - * under this device space. - */ - { PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE, - "PMCBAR" }, }; sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, From 2c26108208e4aa48de21be576ab6cad9286d7934 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Thu, 14 May 2020 13:24:21 -0600 Subject: [PATCH 182/405] soc/intel/tigerlake: Move pmc_soc_set_afterg3_en to pmutil pmc.c was included in the SMM object, but only needed the one function, pmc_soc_set_afterg3_en. pmutil.c was already doing power management- related functionality, and was included in SMM, so moving pmc_soc_set_afterg3_en to pmutil.c allows pmc.c to be removed from the SMM build. Change-Id: I87f65fd10d35f1f75516e804501d5319b81a0383 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/41407 Reviewed-by: Furquan Shaikh Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/Makefile.inc | 1 - src/soc/intel/tigerlake/pmc.c | 17 ----------------- src/soc/intel/tigerlake/pmutil.c | 17 +++++++++++++++++ 3 files changed, 17 insertions(+), 18 deletions(-) diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index f62bfaf38c..51422f9c64 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -47,7 +47,6 @@ ramstage-y += me.c smm-y += gpio.c smm-y += p2sb.c -smm-y += pmc.c smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index fa59d467e2..2d30424cd0 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -17,23 +17,6 @@ #include #include -/* - * Set which power state system will be after reapplying - * the power (from G3 State) - */ -void pmc_soc_set_afterg3_en(const bool on) -{ - uint8_t reg8; - uint8_t *const pmcbase = pmc_mmio_regs(); - - reg8 = read8(pmcbase + GEN_PMCON_A); - if (on) - reg8 &= ~SLEEP_AFTER_POWER_FAIL; - else - reg8 |= SLEEP_AFTER_POWER_FAIL; - write8(pmcbase + GEN_PMCON_A, reg8); -} - static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) { uint32_t reg; diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index bd6a46c788..befc4fc48b 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -275,3 +275,20 @@ uint16_t get_pmbase(void) { return (uint16_t) ACPI_BASE_ADDRESS; } + +/* + * Set which power state system will be after reapplying + * the power (from G3 State) + */ +void pmc_soc_set_afterg3_en(const bool on) +{ + uint8_t reg8; + uint8_t *const pmcbase = pmc_mmio_regs(); + + reg8 = read8(pmcbase + GEN_PMCON_A); + if (on) + reg8 &= ~SLEEP_AFTER_POWER_FAIL; + else + reg8 |= SLEEP_AFTER_POWER_FAIL; + write8(pmcbase + GEN_PMCON_A, reg8); +} From efaf1b32ba1eb69b8968de7e0f67e8fc66fca0d5 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 14 May 2020 16:37:46 +0200 Subject: [PATCH 183/405] drivers/emulation/qemu/bochs: Rewrite driver Support MMIO mapped BOCHS interface supported since qemu 3.0. This allows to use multiple virtual GPUs by specifying: qemu -device bochs-display -device bochs-display ... Tested on qemu. std, qxl, vmware and multiple bochs displays are working fine. Change-Id: Ib0eba4815942625ce4859946efccca500301bb65 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/41406 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Himanshu Sahdev Reviewed-by: Gerd Hoffmann --- src/drivers/emulation/qemu/bochs.c | 114 +++++++++++++++++++---------- 1 file changed, 76 insertions(+), 38 deletions(-) diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index 6372404021..5a6603ee1e 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -40,66 +41,103 @@ static int width = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES; static int height = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES; -static void bochs_write(int index, int val) +static void bochs_write(struct resource *res, int index, int val) { - outw(index, VBE_DISPI_IOPORT_INDEX); - outw(val, VBE_DISPI_IOPORT_DATA); + if (res->flags & IORESOURCE_IO) { + outw(index, res->base); + outw(val, res->base + 1); + } else { + write16(res2mmio(res, 0x500 + index * 2, 0), val); + } } -static int bochs_read(int index) +static int bochs_read(struct resource *res, int index) { - outw(index, VBE_DISPI_IOPORT_INDEX); - return inw(VBE_DISPI_IOPORT_DATA); + if (res->flags & IORESOURCE_IO) { + outw(index, res->base); + return inw(res->base + 1); + } else { + return read16(res2mmio(res, 0x500 + index * 2, 0)); + } } +static void bochs_vga_write(struct resource *res, int index, uint8_t val) +{ + if (res->flags & IORESOURCE_IO) + outb(val, index + 0x3c0); + else + write8(res2mmio(res, (0x400 - 0x3c0) + index, 0), val); +} + +static struct resource res_legacy = { + VBE_DISPI_IOPORT_INDEX, + VBE_DISPI_IOPORT_DATA - VBE_DISPI_IOPORT_INDEX, + VBE_DISPI_IOPORT_DATA, + NULL, + IORESOURCE_IO, + 0, + 1, + 1 +}; + static void bochs_init_linear_fb(struct device *dev) { struct edid edid; + struct resource *res_fb, *res_io; int id, mem, bar; - u32 addr; + + res_fb = probe_resource(dev, PCI_BASE_ADDRESS_0); + if (res_fb && res_fb->flags & IORESOURCE_MEM) { + /* qemu -vga {std,qxl} */ + bar = 0; + } else { + res_fb = probe_resource(dev, PCI_BASE_ADDRESS_1); + if (res_fb && res_fb->flags & IORESOURCE_MEM) { + /* qemu -vga vmware */ + bar = 1; + } else { + printk(BIOS_ERR, "%s: Not bochs compatible\n", dev_name(dev)); + return; + } + } + + /* MMIO bar supported since qemu 3.0+ */ + res_io = probe_resource(dev, PCI_BASE_ADDRESS_2); + if (((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) || + !res_io || !(res_io->flags & IORESOURCE_MEM)) { + printk(BIOS_DEBUG, "QEMU VGA: Using legacy VGA\n"); + res_io = &res_legacy; + } else { + printk(BIOS_DEBUG, "QEMU VGA: Using I/O bar at %llx\n", res_io->base); + } /* bochs dispi detection */ - id = bochs_read(VBE_DISPI_INDEX_ID); + id = bochs_read(res_io, VBE_DISPI_INDEX_ID); if ((id & 0xfff0) != VBE_DISPI_ID0) { printk(BIOS_DEBUG, "QEMU VGA: bochs dispi: ID mismatch.\n"); return; } - mem = bochs_read(VBE_DISPI_INDEX_VIDEO_MEMORY_64K) * 64 * 1024; - - /* find lfb pci bar */ - addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0); - if ((addr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) { - /* qemu -vga {std,qxl} */ - bar = 0; - } else { - /* qemu -vga vmware */ - addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1); - bar = 1; - } - addr &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - - if (!addr) - return; + mem = bochs_read(res_io, VBE_DISPI_INDEX_VIDEO_MEMORY_64K) * 64 * 1024; printk(BIOS_DEBUG, "QEMU VGA: bochs dispi interface found, " "%d MiB video memory\n", mem / (1024 * 1024)); - printk(BIOS_DEBUG, "QEMU VGA: framebuffer @ %x (pci bar %d)\n", - addr, bar); + printk(BIOS_DEBUG, "QEMU VGA: framebuffer @ %llx (pci bar %d)\n", + res_fb->base, bar); /* setup video mode */ - bochs_write(VBE_DISPI_INDEX_ENABLE, 0); - bochs_write(VBE_DISPI_INDEX_BANK, 0); - bochs_write(VBE_DISPI_INDEX_BPP, 32); - bochs_write(VBE_DISPI_INDEX_XRES, width); - bochs_write(VBE_DISPI_INDEX_YRES, height); - bochs_write(VBE_DISPI_INDEX_VIRT_WIDTH, width); - bochs_write(VBE_DISPI_INDEX_VIRT_HEIGHT, height); - bochs_write(VBE_DISPI_INDEX_X_OFFSET, 0); - bochs_write(VBE_DISPI_INDEX_Y_OFFSET, 0); - bochs_write(VBE_DISPI_INDEX_ENABLE, + bochs_write(res_io, VBE_DISPI_INDEX_ENABLE, 0); + bochs_write(res_io, VBE_DISPI_INDEX_BANK, 0); + bochs_write(res_io, VBE_DISPI_INDEX_BPP, 32); + bochs_write(res_io, VBE_DISPI_INDEX_XRES, width); + bochs_write(res_io, VBE_DISPI_INDEX_YRES, height); + bochs_write(res_io, VBE_DISPI_INDEX_VIRT_WIDTH, width); + bochs_write(res_io, VBE_DISPI_INDEX_VIRT_HEIGHT, height); + bochs_write(res_io, VBE_DISPI_INDEX_X_OFFSET, 0); + bochs_write(res_io, VBE_DISPI_INDEX_Y_OFFSET, 0); + bochs_write(res_io, VBE_DISPI_INDEX_ENABLE, VBE_DISPI_ENABLED | VBE_DISPI_LFB_ENABLED); - outb(0x20, 0x3c0); /* disable blanking */ + bochs_vga_write(res_io, 0, 0x20); /* disable blanking */ /* setup coreboot framebuffer */ edid.mode.ha = width; @@ -107,7 +145,7 @@ static void bochs_init_linear_fb(struct device *dev) edid.panel_bits_per_color = 8; edid.panel_bits_per_pixel = 24; edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); - set_vbe_mode_info_valid(&edid, addr); + set_vbe_mode_info_valid(&edid, res_fb->base); } static void bochs_init_text_mode(struct device *dev) From 062646670fe0b750e1c8398321c21054e30ff054 Mon Sep 17 00:00:00 2001 From: Huayang Duan Date: Mon, 20 Apr 2020 19:33:28 +0800 Subject: [PATCH 184/405] soc/mediatek/mt8183: Set CA and DQ vref range to correct value The CA vref should alway select range[1]. But in fast calibration flow, we missed the range selection and caused the CA vref to use the range[0] value. The DQ vref should select correct range that corresponds to current frequency, that is for 1600Mbps, 2400Mbps to select range[1], for 3200Mbps and 3600Mbps to select range[0]. Refer to the 'JESD209-4 - Low Power Double Data Rate 4X(LPDDR4X).pdf', used MR12 to set Vref(CA) levels, used MR14 to set VREF(DQ) levels. MR12 range[0] values from 15.0% to 44.9%, range[1] values from 32.9% to 62.9%, MR14 range[0] and range[1] values same as MR12. BUG=b:153614919 BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: Ie7680b1bf0c29c946d18e3b27626ce6f31c4216b Signed-off-by: Huayang Duan Reviewed-on: https://review.coreboot.org/c/coreboot/+/40525 Reviewed-by: Hung-Te Lin Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8183/dramc_init_setting.c | 7 +++++-- src/soc/mediatek/mt8183/dramc_pi_calibration_api.c | 9 +++++---- src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h | 4 ++-- 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index 2440814f1d..6f7ae37743 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -1218,8 +1218,8 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group, (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) | (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28)); clrbits32(&ch[0].ao.shu[0].selph_ca5, 0x7 << 8); - clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0); - clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1); + clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_3200); + clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_3200); for (size_t rank = 0; rank < 2; rank++) { clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[0], @@ -1373,6 +1373,9 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group, setbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 12) | (0x1 << 13)); clrbits32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0); + /* The default dramc init settings were tuned at frequency of 3200Mbps. + For other frequencies uses dramc_setting_DDRxxx() to overwrite + the default settings. */ switch (freq_group) { case LP4X_DDR1600: dramc_setting_DDR1600(); diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 7242dd3ce8..aac6d17ed6 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -220,9 +220,7 @@ static void dramc_write_leveling(u8 chn, u8 rank, u8 freq_group, { dramc_auto_refresh_switch(chn, false); - if (rank == RANK_0 && (freq_group == LP4X_DDR3600 || - freq_group == LP4X_DDR1600 || - freq_group == LP4X_DDR2400)) + if (rank == RANK_0) write_leveling_move_dqs_instead_of_clk(chn); SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], @@ -265,8 +263,11 @@ static void dramc_cmd_bus_training(u8 chn, u8 rank, u8 freq_group, SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], SHU1_R0_CA_CMD9_RG_RK0_ARPI_CS, cs_dly); + final_vref |= (1 << 6); + /* CBT set vref */ dramc_mode_reg_write_by_rank(chn, rank, 12, final_vref); + dramc_dbg("final_vref: %#x\n", final_vref); } static void dramc_read_dbi_onoff(size_t chn, bool on) @@ -1822,7 +1823,7 @@ static u8 dramc_window_perbit_cal(u8 chn, u8 rank, u8 freq_group, vref_end = vref_begin + 1; dramc_dbg("bypass RX vref: %d\n", vref_begin); } else if (type == TX_WIN_DQ_ONLY) { - vref_begin = params->tx_vref[chn][rank]; + vref_begin = params->tx_vref[chn][rank] | (vref_range << 6); vref_end = vref_begin + 1; dramc_dbg("bypass TX vref: %d\n", vref_begin); } diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 07b50d6585..66433602c5 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -74,12 +74,12 @@ enum { DQ_DIV_MASK = BIT(DQ_DIV_SHIFT) - 1, OEN_SHIFT = 16, - SELPH_DQS0 = _SELPH_DQS_BITS(0x3, 0x3), - SELPH_DQS1 = _SELPH_DQS_BITS(0x4, 0x1), SELPH_DQS0_1600 = _SELPH_DQS_BITS(0x2, 0x1), SELPH_DQS1_1600 = _SELPH_DQS_BITS(0x1, 0x6), SELPH_DQS0_2400 = _SELPH_DQS_BITS(0x3, 0x2), SELPH_DQS1_2400 = _SELPH_DQS_BITS(0x1, 0x6), + SELPH_DQS0_3200 = _SELPH_DQS_BITS(0x3, 0x3), + SELPH_DQS1_3200 = _SELPH_DQS_BITS(0x5, 0x2), SELPH_DQS0_3600 = _SELPH_DQS_BITS(0x4, 0x3), SELPH_DQS1_3600 = _SELPH_DQS_BITS(0x1, 0x6), }; From 32585de39ea15b4192e213b7cfcf46485bfd0d2f Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 18 May 2020 13:21:44 -0700 Subject: [PATCH 185/405] soc/intel/tigerlake: Add TCSS devices to soc_acpi_name() Add ACPI device names for TCSS devices which were not already defined which match those declared in the DSDT at acpi/tcss.asl. Change-Id: I6a79da7dd78c73345986c12d6ffe467cd4322e05 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/41520 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/tigerlake/chip.c | 76 +++++++++++++++++++--------------- 1 file changed, 42 insertions(+), 34 deletions(-) diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index a923074acc..00db2a41a4 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -58,41 +58,49 @@ const char *soc_acpi_name(const struct device *dev) return NULL; switch (dev->path.pci.devfn) { - case SA_DEVFN_ROOT: return "MCHC"; - case PCH_DEVFN_ISH: return "ISHB"; - case PCH_DEVFN_XHCI: return "XHCI"; - case PCH_DEVFN_I2C0: return "I2C0"; - case PCH_DEVFN_I2C1: return "I2C1"; - case PCH_DEVFN_I2C2: return "I2C2"; - case PCH_DEVFN_I2C3: return "I2C3"; - case PCH_DEVFN_I2C4: return "I2C4"; - case PCH_DEVFN_I2C5: return "I2C5"; - case PCH_DEVFN_SATA: return "SATA"; - case PCH_DEVFN_PCIE1: return "RP01"; - case PCH_DEVFN_PCIE2: return "RP02"; - case PCH_DEVFN_PCIE3: return "RP03"; - case PCH_DEVFN_PCIE4: return "RP04"; - case PCH_DEVFN_PCIE5: return "RP05"; - case PCH_DEVFN_PCIE6: return "RP06"; - case PCH_DEVFN_PCIE7: return "RP07"; - case PCH_DEVFN_PCIE8: return "RP08"; - case PCH_DEVFN_PCIE9: return "RP09"; - case PCH_DEVFN_PCIE10: return "RP10"; - case PCH_DEVFN_PCIE11: return "RP11"; - case PCH_DEVFN_PCIE12: return "RP12"; - case PCH_DEVFN_PMC: return "PMC"; - case PCH_DEVFN_UART0: return "UAR0"; - case PCH_DEVFN_UART1: return "UAR1"; - case PCH_DEVFN_UART2: return "UAR2"; - case PCH_DEVFN_GSPI0: return "SPI0"; - case PCH_DEVFN_GSPI1: return "SPI1"; - case PCH_DEVFN_GSPI2: return "SPI2"; - case PCH_DEVFN_GSPI3: return "SPI3"; + case SA_DEVFN_ROOT: return "MCHC"; + case SA_DEVFN_TCSS_XHCI: return "TXHC"; + case SA_DEVFN_TCSS_XDCI: return "TXDC"; + case SA_DEVFN_TCSS_DMA0: return "TDM0"; + case SA_DEVFN_TCSS_DMA1: return "TDM1"; + case SA_DEVFN_TBT0: return "TRP0"; + case SA_DEVFN_TBT1: return "TRP1"; + case SA_DEVFN_TBT2: return "TRP2"; + case SA_DEVFN_TBT3: return "TRP3"; + case PCH_DEVFN_ISH: return "ISHB"; + case PCH_DEVFN_XHCI: return "XHCI"; + case PCH_DEVFN_I2C0: return "I2C0"; + case PCH_DEVFN_I2C1: return "I2C1"; + case PCH_DEVFN_I2C2: return "I2C2"; + case PCH_DEVFN_I2C3: return "I2C3"; + case PCH_DEVFN_I2C4: return "I2C4"; + case PCH_DEVFN_I2C5: return "I2C5"; + case PCH_DEVFN_SATA: return "SATA"; + case PCH_DEVFN_PCIE1: return "RP01"; + case PCH_DEVFN_PCIE2: return "RP02"; + case PCH_DEVFN_PCIE3: return "RP03"; + case PCH_DEVFN_PCIE4: return "RP04"; + case PCH_DEVFN_PCIE5: return "RP05"; + case PCH_DEVFN_PCIE6: return "RP06"; + case PCH_DEVFN_PCIE7: return "RP07"; + case PCH_DEVFN_PCIE8: return "RP08"; + case PCH_DEVFN_PCIE9: return "RP09"; + case PCH_DEVFN_PCIE10: return "RP10"; + case PCH_DEVFN_PCIE11: return "RP11"; + case PCH_DEVFN_PCIE12: return "RP12"; + case PCH_DEVFN_PMC: return "PMC"; + case PCH_DEVFN_UART0: return "UAR0"; + case PCH_DEVFN_UART1: return "UAR1"; + case PCH_DEVFN_UART2: return "UAR2"; + case PCH_DEVFN_GSPI0: return "SPI0"; + case PCH_DEVFN_GSPI1: return "SPI1"; + case PCH_DEVFN_GSPI2: return "SPI2"; + case PCH_DEVFN_GSPI3: return "SPI3"; /* Keeping ACPI device name coherent with ec.asl */ - case PCH_DEVFN_ESPI: return "LPCB"; - case PCH_DEVFN_HDA: return "HDAS"; - case PCH_DEVFN_SMBUS: return "SBUS"; - case PCH_DEVFN_GBE: return "GLAN"; + case PCH_DEVFN_ESPI: return "LPCB"; + case PCH_DEVFN_HDA: return "HDAS"; + case PCH_DEVFN_SMBUS: return "SBUS"; + case PCH_DEVFN_GBE: return "GLAN"; } return NULL; From 7d6bc60db9427f029f990002870e40541601a209 Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Fri, 8 May 2020 19:22:07 +0530 Subject: [PATCH 186/405] tigerlake: enable DPTF functionality for volteer Enable DPTF functionality for volteer platform BRANCH=None BUG=b:149722146 TEST=Built and tested on volteer system Change-Id: I385fb409ccd291d97369295ff99f21c9430880f9 Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/41427 Reviewed-by: Wonkyu Kim Reviewed-by: Caveh Jalali Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/dsdt.asl | 11 ++ .../volteer/variants/baseboard/devicetree.cb | 10 ++ .../baseboard/include/baseboard/acpi/dptf.asl | 131 ++++++++++++++++++ .../halvor/include/variant/acpi/dptf.asl | 3 + .../malefor/include/variant/acpi/dptf.asl | 3 + .../ripto/include/variant/acpi/dptf.asl | 3 + .../trondo/include/variant/acpi/dptf.asl | 3 + src/soc/intel/common/acpi/dptf.asl | 32 +++++ src/soc/intel/tigerlake/fsp_params.c | 3 + 9 files changed, 199 insertions(+) create mode 100644 src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl create mode 100644 src/mainboard/google/volteer/variants/halvor/include/variant/acpi/dptf.asl create mode 100644 src/mainboard/google/volteer/variants/malefor/include/variant/acpi/dptf.asl create mode 100644 src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl create mode 100644 src/mainboard/google/volteer/variants/trondo/include/variant/acpi/dptf.asl create mode 100644 src/soc/intel/common/acpi/dptf.asl diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index ddbc10f4e4..fa39e79e8e 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -52,6 +52,17 @@ DefinitionBlock( #include } + /* Dynamic Platform Thermal Framework */ + Scope (\_SB) + { + /* Per board variant specific definitions. */ + #include + /* Include soc specific DPTF changes */ + #include + /* Include common dptf ASL files */ + #include + } + #include #if CONFIG(VARIANT_HAS_MIPI_CAMERA) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 5d5dcc4b70..25b42c74f7 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -170,6 +170,16 @@ chip soc/intel/tigerlake # Enable S0ix register "s0ix_enable" = "1" + # Enable DPTF + register "dptf_enable" = "1" + + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 60, + }" + + register "Device4Enable" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl new file mode 100644 index 0000000000..cef895b59f --- /dev/null +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 105 +#define DPTF_CPU_ACTIVE_AC0 85 +#define DPTF_CPU_ACTIVE_AC1 80 +#define DPTF_CPU_ACTIVE_AC2 75 +#define DPTF_CPU_ACTIVE_AC3 70 +#define DPTF_CPU_ACTIVE_AC4 65 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 75 +#define DPTF_TSR0_ACTIVE_AC0 50 +#define DPTF_TSR0_ACTIVE_AC1 47 +#define DPTF_TSR0_ACTIVE_AC2 45 +#define DPTF_TSR0_ACTIVE_AC3 42 +#define DPTF_TSR0_ACTIVE_AC4 39 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 75 +#define DPTF_TSR1_ACTIVE_AC0 50 +#define DPTF_TSR1_ACTIVE_AC1 47 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 39 + +#define DPTF_TSR2_SENSOR_ID 1 +#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor 3" +#define DPTF_TSR2_PASSIVE 65 +#define DPTF_TSR2_CRITICAL 75 +#define DPTF_TSR2_ACTIVE_AC0 50 +#define DPTF_TSR2_ACTIVE_AC1 47 +#define DPTF_TSR2_ACTIVE_AC2 45 +#define DPTF_TSR2_ACTIVE_AC3 42 +#define DPTF_TSR2_ACTIVE_AC4 39 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + } +}) + + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on TSR0 sensor */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on TSR2 sensor */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 60000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/volteer/variants/halvor/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/halvor/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..189cafea4c --- /dev/null +++ b/src/mainboard/google/volteer/variants/halvor/include/variant/acpi/dptf.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/volteer/variants/malefor/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/malefor/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..189cafea4c --- /dev/null +++ b/src/mainboard/google/volteer/variants/malefor/include/variant/acpi/dptf.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..189cafea4c --- /dev/null +++ b/src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/volteer/variants/trondo/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/trondo/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..189cafea4c --- /dev/null +++ b/src/mainboard/google/volteer/variants/trondo/include/variant/acpi/dptf.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/soc/intel/common/acpi/dptf.asl b/src/soc/intel/common/acpi/dptf.asl new file mode 100644 index 0000000000..bd6d63ef40 --- /dev/null +++ b/src/soc/intel/common/acpi/dptf.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define DPTF_CPU_DEVICE TCPU +#define DPTF_CPU_ADDR 0x00040000 + +#ifndef DPTF_CPU_PASSIVE +#define DPTF_CPU_PASSIVE 80 +#endif + +#ifndef DPTF_CPU_CRITICAL +#define DPTF_CPU_CRITICAL 90 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC0 +#define DPTF_CPU_ACTIVE_AC0 90 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC1 +#define DPTF_CPU_ACTIVE_AC1 80 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC2 +#define DPTF_CPU_ACTIVE_AC2 70 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC3 +#define DPTF_CPU_ACTIVE_AC3 60 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC4 +#define DPTF_CPU_ACTIVE_AC4 50 +#endif diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index cf106cbe16..0c67105300 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -193,6 +193,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable); params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable); + /* Enable TCPU for processor thermal control */ + params->Device4Enable = config->Device4Enable; + /* LAN */ dev = pcidev_path_on_root(PCH_DEVFN_GBE); if (!dev) From 8d002f515db89f7a02a22f670e285128917110d1 Mon Sep 17 00:00:00 2001 From: Jeff Chase Date: Wed, 25 Mar 2020 22:07:00 -0400 Subject: [PATCH 187/405] mb/google/endeavour: chrontel: fix interrupt and compat string The devicetree declares the chrontel interrupt as GpioInt so the GPIO needs to be configured as such instead of routing directly to APIC. Also update the compatible string to conform to kernel standards. BUG=b:146576073 TEST=install ch7322 driver; send commands using cec-ctl and verify that the interrupt handler is called. Change-Id: I737d951db135c53deb0f3cb956f0d0f275082251 Signed-off-by: Jeff Chase Reviewed-on: https://review.coreboot.org/c/coreboot/+/41185 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel --- src/mainboard/google/fizz/variants/endeavour/gpio.c | 4 ++-- src/mainboard/google/fizz/variants/endeavour/overridetree.cb | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/fizz/variants/endeavour/gpio.c b/src/mainboard/google/fizz/variants/endeavour/gpio.c index 0915c3eb7d..432a180362 100644 --- a/src/mainboard/google/fizz/variants/endeavour/gpio.c +++ b/src/mainboard/google/fizz/variants/endeavour/gpio.c @@ -27,9 +27,9 @@ static const struct pad_config gpio_table[] = { /* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */ /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ISH_GP0 */ PAD_CFG_GPI_APIC(GPP_A18, NONE, DEEP), /* 7322_INTO */ +/* ISH_GP0 */ PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, LEVEL), /* 7322_INTO */ /* ISH_GP1 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_A19, 1, DEEP, NONE), /* 7322_OE */ -/* ISH_GP2 */ PAD_CFG_GPI_APIC(GPP_A20, NONE, DEEP), /* 7322_INTO */ +/* ISH_GP2 */ PAD_CFG_GPI_INT(GPP_A20, NONE, PLTRST, LEVEL), /* 7322_INTO */ /* ISH_GP3 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_A21, 1, DEEP, NONE), /* 7322_OE */ /* ISH_GP4 */ PAD_CFG_NC(GPP_A22), /* ISH_GP5 */ PAD_CFG_NC(GPP_A23), diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb index 861e1b194a..1d837934ac 100644 --- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb +++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb @@ -137,7 +137,7 @@ chip soc/intel/skylake register "hid" = "ACPI_DT_NAMESPACE_HID" register "desc" = ""Chrontel 7322"" register "uid" = "1" - register "compat_string" = ""chrontel,7322"" + register "compat_string" = ""chrontel,ch7322"" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_HIGH(GPP_A18)" device i2c 75 on end end @@ -145,7 +145,7 @@ chip soc/intel/skylake register "hid" = "ACPI_DT_NAMESPACE_HID" register "desc" = ""Chrontel 7322"" register "uid" = "2" - register "compat_string" = ""chrontel,7322"" + register "compat_string" = ""chrontel,ch7322"" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_HIGH(GPP_A20)" device i2c 76 on end end From 9bafc49c5ab2d0aeafe7fae9538781a41eb7a08c Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Mon, 18 May 2020 23:33:28 +0200 Subject: [PATCH 188/405] drivers/intel/gma: License libgfxinit glue code under GPL v2 Change-Id: I7a78e16512369cbaada4399dbb855ade358ff046 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/41521 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Aaron Durbin Reviewed-by: Jacob Garber --- src/drivers/intel/gma/gma-gfx_init.ads | 2 ++ src/drivers/intel/gma/gma.adb | 2 ++ src/drivers/intel/gma/gma.ads | 2 ++ src/drivers/intel/gma/hires_fb/gma-gfx_init.adb | 2 ++ src/drivers/intel/gma/text_fb/gma-gfx_init.adb | 2 ++ 5 files changed, 10 insertions(+) diff --git a/src/drivers/intel/gma/gma-gfx_init.ads b/src/drivers/intel/gma/gma-gfx_init.ads index 7c96f9adf7..84c4a5b6db 100644 --- a/src/drivers/intel/gma/gma-gfx_init.ads +++ b/src/drivers/intel/gma/gma-gfx_init.ads @@ -1,3 +1,5 @@ +-- SPDX-License-Identifier: GPL-2.0-only + with Interfaces.C; with HW; diff --git a/src/drivers/intel/gma/gma.adb b/src/drivers/intel/gma/gma.adb index 10885e6e09..43fc7b28a7 100644 --- a/src/drivers/intel/gma/gma.adb +++ b/src/drivers/intel/gma/gma.adb @@ -1,3 +1,5 @@ +-- SPDX-License-Identifier: GPL-2.0-only + with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/drivers/intel/gma/gma.ads b/src/drivers/intel/gma/gma.ads index 0b4b66bde7..e83fff4936 100644 --- a/src/drivers/intel/gma/gma.ads +++ b/src/drivers/intel/gma/gma.ads @@ -1,3 +1,5 @@ +-- SPDX-License-Identifier: GPL-2.0-only + with Interfaces.C; with HW.GFX.EDID; diff --git a/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb b/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb index 1393784d7b..92d3a16963 100644 --- a/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb +++ b/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb @@ -1,3 +1,5 @@ +-- SPDX-License-Identifier: GPL-2.0-only + with CB.Config; use CB; diff --git a/src/drivers/intel/gma/text_fb/gma-gfx_init.adb b/src/drivers/intel/gma/text_fb/gma-gfx_init.adb index 038b76b26a..04ef30a465 100644 --- a/src/drivers/intel/gma/text_fb/gma-gfx_init.adb +++ b/src/drivers/intel/gma/text_fb/gma-gfx_init.adb @@ -1,3 +1,5 @@ +-- SPDX-License-Identifier: GPL-2.0-only + with HW.GFX; with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; From bba5bfc7d26ca8e9de56b4160e3d1980d6b3be7c Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 18 May 2020 11:29:44 -0500 Subject: [PATCH 189/405] 3rdparty/libgfxinit: Update submodule pointer Update libgfxinit submodule pointer to pull in handling for presence straps bypass and some minor cleanup. Signed-off-by: Matt DeVillier Change-Id: Id4a903383f32f352aa3595bd72bc5f6f0777171c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41515 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- 3rdparty/libgfxinit | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index 2e87c0d40a..8fc8e49a93 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit 2e87c0d40a387c5b1f1afd3ce61ecdc7dad0e3e8 +Subproject commit 8fc8e49a932c7a011429b333765c6b0ed09cd742 From dd467bfc14aa5e1d27e87814588a871fec6aa51f Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 14 May 2020 17:45:29 -0500 Subject: [PATCH 190/405] drivers/intel/gma: Add override for presence straps A handful of boards do not properly implement the presence straps, leading libgfxinit to fail to detect an attached display. Add an override, defaulting to N, which can be set for affected boards. Add a section to the documentation detailing the option and its usage. Signed-off-by: Matt DeVillier Change-Id: I43c61d67147878887658b23d90fb1c0b91e7a2af Reviewed-on: https://review.coreboot.org/c/coreboot/+/41416 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- Documentation/gfx/libgfxinit.md | 27 ++++++++++++++++++++++----- src/drivers/intel/gma/Kconfig | 7 +++++++ 2 files changed, 29 insertions(+), 5 deletions(-) diff --git a/Documentation/gfx/libgfxinit.md b/Documentation/gfx/libgfxinit.md index bb4528b958..40f194a4eb 100644 --- a/Documentation/gfx/libgfxinit.md +++ b/Documentation/gfx/libgfxinit.md @@ -88,11 +88,28 @@ know through which interface the EDID can be queried: select GFX_GMA_ANALOG_I2C_HDMI_C # or select GFX_GMA_ANALOG_I2C_HDMI_D -Beside Kconfig options, *libgfxinit* needs to know which ports are -implemented on a board and should be probed for displays. The mapping -between the physical ports and these entries depends on the hardware -implementation and can be recovered by testing or studying the output -of `intelvbttool` or `intel_vbt_decode`. +*libgfxinit* needs to know which ports are implemented on a board +and should be probed for displays. There are two mechanisms to +constrain the list of ports to probe, 1. port presence straps on +the mainboard, and 2. a list of ports provided by *coreboot* (see +below). + +Presence straps are configured via the state of certains pins of +the chipset at reset time. They are documented in the chipset's +datasheets. By default, *libgfxinit* honors these straps for +safety. However, some boards don't implement the straps correctly. +If ports are not strapped as implemented by error, one can select +an option to ignore the straps: + + select GFX_GMA_IGNORE_PRESENCE_STRAPS + +In the opposite case, that ports are strapped as implemented, +but are actually unconnected, one has to make sure that the +list of ports in *coreboot* omits them. + +The mapping between the physical ports and these entries depends on +the hardware implementation and can be recovered by testing or +studying the output of `intelvbttool` or `intel_vbt_decode`. Each board has to implement the package `GMA.Mainboard` with a list: ports : HW.GFX.GMA.Display_Probing.Port_List; diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index ad44a2f480..635de1c87a 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -127,4 +127,11 @@ config GFX_GMA_ANALOG_I2C_PORT digital displays. In that case, the EDID for a VGA display has to be read over the I2C interface of the coupled digital port. +config GFX_GMA_IGNORE_PRESENCE_STRAPS + def_bool n + help + libgfxinit uses the GPU presence straps to determine if a display port + is present/enabled. Select this option if a board doesn't correctly implement + these straps, causing libgfxinit to fail to detect an attached panel. + endif From f572d5ed0b022afe9e18500ab05081ab4bc64379 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 14 May 2020 17:47:26 -0500 Subject: [PATCH 191/405] mb/purism/librem_skl: select GFX_GMA_IGNORE_PRESENCE_STRAPS Some Librem 13v4's don't have the presence straps connected, leading libgfxinit to fail to init the internal display. Select GFX_GMA_IGNORE_PRESENCE_STRAPS since all SKL/KBL Librems have an internal display so there's no adverse effect. Signed-off-by: Matt DeVillier Change-Id: Ib9d281b7d495c4f9a5c6fc5fdb8042b0fcbda745 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41417 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/mainboard/purism/librem_skl/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index 9760a2f9e7..c86ebf18e9 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -2,6 +2,7 @@ config BOARD_PURISM_BASEBOARD_LIBREM_SKL def_bool n select BOARD_ROMSIZE_KB_16384 select DRIVERS_GENERIC_CBFS_SERIAL + select GFX_GMA_IGNORE_PRESENCE_STRAPS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_GMA_HAVE_VBT From 238b10a5f7fb3ca6c4aca37a14f34cafa4306ddf Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 19 May 2020 14:32:07 -0700 Subject: [PATCH 192/405] google/trogdor: Fix ram_code and sku_id strappings I'm not quite sure what happened when we first added the code for Trogdor strappings but something clearly seems to be wrong. First of all, on newer schematics the RAM_ID_1 pin is actually pin 19, not pin 91. It only used to be 91 on rev0. Whether that was an intentional change or someone just swapped the digits on accident at some point, we're not quite sure anymore, but it seems to be 19 going forward so that is what we should be programming. (ram_code wasn't used for anything on Trogdor rev0 so we don't care about adding backwards-compatibility for that.) The sku_id pins are also somewhat out of whack: first of all, a new SKU_ID_2 pin was added for rev1 that wasn't there on rev0. Second, SKU_ID_0 is not GPIO_114. In fact, it has never been GPIO_114. I have no idea how that number got there. Anyway, fix it. (Like with the ram_code, SKU IDs were also not used for rev0 so we won't make this backwards-compatible.) Signed-off-by: Julius Werner Change-Id: Ia14ec74ec2f16ce2661f89d0d597a5477297ab69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41545 Tested-by: build bot (Jenkins) Reviewed-by: Philip Chen --- src/mainboard/google/trogdor/boardid.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/trogdor/boardid.c b/src/mainboard/google/trogdor/boardid.c index 20aa543244..c1a48925fa 100644 --- a/src/mainboard/google/trogdor/boardid.c +++ b/src/mainboard/google/trogdor/boardid.c @@ -19,7 +19,7 @@ uint32_t ram_code(void) { static uint32_t id = UNDEFINED_STRAPPING_ID; - const gpio_t pins[] = {[2] = GPIO(13), [1] = GPIO(91), [0] = GPIO(29)}; + const gpio_t pins[] = {[2] = GPIO(13), [1] = GPIO(19), [0] = GPIO(29)}; if (id == UNDEFINED_STRAPPING_ID) id = gpio_base2_value(pins, ARRAY_SIZE(pins)); @@ -31,7 +31,7 @@ uint32_t sku_id(void) { static uint32_t id = UNDEFINED_STRAPPING_ID; - const gpio_t pins[] = {[1] = GPIO(90), [0] = GPIO(114)}; + const gpio_t pins[] = {[2] = GPIO(20), [1] = GPIO(90), [0] = GPIO(105)}; if (id == UNDEFINED_STRAPPING_ID) id = gpio_base2_value(pins, ARRAY_SIZE(pins)); From cfd78b1500bed6d3d410f984450c45f28b700aa2 Mon Sep 17 00:00:00 2001 From: Bill XIE Date: Mon, 18 May 2020 16:34:37 +0800 Subject: [PATCH 193/405] Revert "mainboard/lenovo/x230: Add ThinkPad x230s as a variant" This reverts commit 6b95507ec5b087658178a325bdc68570bc48bb20, in order to recommit and review it again. Change-Id: Id4ddf99200f77016a48d02a8421d080cea492aae Signed-off-by: Bill XIE Reviewed-on: https://review.coreboot.org/c/coreboot/+/41504 Reviewed-by: Alexander Couzens Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- Documentation/mainboard/index.md | 1 - .../mainboard/lenovo/Ivy_Bridge_series.md | 2 +- Documentation/mainboard/lenovo/x230s.md | 15 -- .../mainboard/lenovo/x230s_bc_removed.jpg | Bin 42564 -> 0 bytes src/mainboard/lenovo/x230/Kconfig | 24 +- src/mainboard/lenovo/x230/Kconfig.name | 3 - src/mainboard/lenovo/x230/Makefile.inc | 12 +- src/mainboard/lenovo/x230/board_info.txt | 1 - .../lenovo/x230/{variants/x230 => }/data.vbt | Bin src/mainboard/lenovo/x230/devicetree.cb | 8 +- .../x230/{variants/x230 => }/early_init.c | 0 .../{variants/x230 => }/gma-mainboard.ads | 0 .../lenovo/x230/{variants/x230 => }/gpio.c | 0 src/mainboard/lenovo/x230/hda_verb.c | 83 ++++++- .../lenovo/x230/variants/x230/board_info.txt | 7 - .../lenovo/x230/variants/x230/hda_verb.c | 82 ------- .../lenovo/x230/variants/x230/overridetree.cb | 15 -- .../lenovo/x230/variants/x230s/board_info.txt | 7 - .../lenovo/x230/variants/x230s/data.vbt | Bin 4280 -> 0 bytes .../lenovo/x230/variants/x230s/early_init.c | 49 ---- .../x230/variants/x230s/gma-mainboard.ads | 22 -- .../lenovo/x230/variants/x230s/gpio.c | 212 ------------------ .../lenovo/x230/variants/x230s/hda_verb.c | 33 --- .../x230/variants/x230s/overridetree.cb | 36 --- 24 files changed, 100 insertions(+), 512 deletions(-) delete mode 100644 Documentation/mainboard/lenovo/x230s.md delete mode 100644 Documentation/mainboard/lenovo/x230s_bc_removed.jpg rename src/mainboard/lenovo/x230/{variants/x230 => }/data.vbt (100%) rename src/mainboard/lenovo/x230/{variants/x230 => }/early_init.c (100%) rename src/mainboard/lenovo/x230/{variants/x230 => }/gma-mainboard.ads (100%) rename src/mainboard/lenovo/x230/{variants/x230 => }/gpio.c (100%) delete mode 100644 src/mainboard/lenovo/x230/variants/x230/board_info.txt delete mode 100644 src/mainboard/lenovo/x230/variants/x230/hda_verb.c delete mode 100644 src/mainboard/lenovo/x230/variants/x230/overridetree.cb delete mode 100644 src/mainboard/lenovo/x230/variants/x230s/board_info.txt delete mode 100644 src/mainboard/lenovo/x230/variants/x230s/data.vbt delete mode 100644 src/mainboard/lenovo/x230/variants/x230s/early_init.c delete mode 100644 src/mainboard/lenovo/x230/variants/x230s/gma-mainboard.ads delete mode 100644 src/mainboard/lenovo/x230/variants/x230s/gpio.c delete mode 100644 src/mainboard/lenovo/x230/variants/x230s/hda_verb.c delete mode 100644 src/mainboard/lenovo/x230/variants/x230s/overridetree.cb diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index b9fc68d052..584deb42ee 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -102,7 +102,6 @@ The boards in this section are not real mainboards, but emulators. - [W530](lenovo/w530.md) - [T430 / T530 / X230 / W530 common](lenovo/Ivy_Bridge_series.md) - [T431s](lenovo/t431s.md) -- [X230s](lenovo/x230s.md) - [Internal flashing](lenovo/ivb_internal_flashing.md) ### Haswell series diff --git a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md index 5f151663c4..f4f0efff6c 100644 --- a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md +++ b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md @@ -1,6 +1,6 @@ # Lenovo Ivy Bridge series -This information is valid for all supported models, except T430s, [T431s](t431s.md) and [X230s](x230s.md). +This information is valid for all supported models, except T430s and T431s. ## Flashing coreboot ```eval_rst diff --git a/Documentation/mainboard/lenovo/x230s.md b/Documentation/mainboard/lenovo/x230s.md deleted file mode 100644 index e42d75e974..0000000000 --- a/Documentation/mainboard/lenovo/x230s.md +++ /dev/null @@ -1,15 +0,0 @@ -# Lenovo X230s - -## Disassembly Instructions - -You must remove the following parts to access the SPI flash chip: - -![x230s_bc_removed](x230s_bc_removed.jpg) - -* Base cover - -Its [Hardware Maintenance Manual](https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/x230s_hmm_en_0c10860_01.pdf) could be used as a guidance of disassembly. - -The SPI flash chip (W25Q128.V in thr form of SOIC-8 for mine) is located at the circled place. Unlike [most Ivy Bridge ThinkPads](Ivy_Bridge_series.md), X230s has a single 16MiB SPI flash chip. - -The general [flashing tutorial](../../flash_tutorial/index.md) has more details. diff --git a/Documentation/mainboard/lenovo/x230s_bc_removed.jpg b/Documentation/mainboard/lenovo/x230s_bc_removed.jpg deleted file mode 100644 index 1735e8100b82acbaeb56a8b4428b106408bd4b47..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 42564 zcmbrlWmKIp*EV<#dT@7#;_hA?io3hR!Ci|L*Wz+;clQD<-s0}=QrwCU&nq+E{F)z= z>^sTIT3N};j$Hf7zTcPLR{;_L1f>6e;k^%l0Rs90|3L#N0YD4@6b9gZ06+`?0AYbZ zAmINFP|z^2KsW$A=zRqM`tSO?VARu|?a%7*Rpr%#Fq+OqTpQ(IHH5f5OQz=UoZ~d7 z9_XY8E~@QFp6+lc!ZNm_NSvOd7yM}K#Hj2++Bq*?X-H=Lu~UUTD=7HmN0W9k zOD%SXIOz^{(ii(V2F7!AMVc)-Hl;&IR>h{k(P956jz?-Hiwz^#3(@?mr}U)fkG=;=tp@2X@JSzZ{rEiSNys1(Mj6B7)S zNE6A+J|cM(#!hR+ns(0mN(|?C_qRYDJ6TbfO5qn(Dw6nSWd_*k-;+DpgljDe{;XXzK5%f}RcaPf{vB?^J3N&J=EK z@2{D2=MOUbYqS=s51Q|GgE(qhrkPZo6tnLpgo3jat5=f`VN_WPLz?AN+u1TR@%L6F zHMl%&MdTnR2b9p7WvQ1Xd+~TAC&&Z5m7PjJZj!w za~m;z$ms7HrYzjv?1LV@*lZJ4&=bk)+qpL^8ZLX_+(mhL85=$rb2{d(fPwK4XznAO zmV)j;?(CaTaHp442Dm_uO_m$h!*MkFZ&h?{bSzru=#Qvm)0N|mePV!^P})xMXvEl*?RifWqXZ7oSj z$Ar>WV?0sO$;}m=;PtwxB5!Z#8tDWrGd1dQk`^PwZD*;xM};^G!web4wBA9J&7IWd z^akRXwJC%x0RzqJ78A4yDYc&J(h)J9TJjl9`w{8?mxE_V<040<+nb(8mOg_3Pl;e| z06Ek>VcN(WWzT<KLMXGZg#=8+to;q3s_3XPfiWd zVVkY-T$#U=AvWiU_EWQQBn`2~m*=z@nJoW_x@z)i;vrH`JPDdmV&2cw$0@(W7`APt z+|j8ne62l)4uJ!(L6`CgY7}<^u zVb8dTK=TN;e*w7r7I|K1<)bk9@rkhy^o}OTaFd#gA zT3khkr_#0S54`)v7dMv*RWiu0Px|iw$s0btF7mmN?}O#H4wdr5FPEqG5DmS3^N4AK zcmV-bzAV|#nVIeDX0pfU!mVD;&y1*N1J(HSvA1N_H?fC4uXm|ND@r&o!nMTaNX2_;W;^yKr>t)4I;0O-;N0UR7PDuDBV0jM zti*2kq;6vs;e5Iv>n5?!T5h zf)1Li__&c7|34vIRpJPEtb1A00{7)7vS_?gS*|YVwZeG^^T~Vq>lj#X(@mCxELApp z29u+YoJ9vD@UN=M$B>JE_&wCzkpJ%Z0 zU9SciS9^B%FXtZ}$HZQaT9%pT*nE%D8bd?Fy^UWdv^`QYuKl*ghW7Q@^aFRt!c+*+ zx7Hp0hb3s*l2jy}CNotyay<`m)|xA}-$IWhCJ)aXX#WTtol+E5?IjxsptBygZ20H& zObtFRRz=cRA*&gL( z9>ZUn zjn>kCeAlHeuZ!#4s|H$qX0Tlhf}z)81>?;1W8I@|_ttN0r7_C;KicA68vZ6-Aw6vt zz8sVNnThdb`qSuez&x;?kEZ=Ky=`SuaD|DDsY*;y_LMGl8AHgoTv4t)bY}S88uuzg zYxGDtdkKNiiPitHmID@^o{XsN#IlGdDeJ6oT}uuhKap-TbTq|Y%8F-rA9fFjqC6!c zz;@1nNX-vbTgdVRYx53(irEm}{EH2&-0A$$q@b=+V<8iNQS@0Y+kU}I?95o0z43$) z*rJLfnQ~zRXC%~Xax3COAy=11Sj&xBY$LD|V)=C{P>4Uvh{133v#)H6M~EbGN!&~y zgRBM?Lgl1gPARl(X_ACNlIiemzb3ZePKoJfCl`(MazEoSwM6M3as@!Obfq=Q%rTyE zFD^v&$QmK1wYD;Aiby9!UhnMCJ$|H0iA5P5J6%D#_81n|EZgVuOq0bGlgWRU4FKkd;U+&gSe|&=Zg}FQL zetfHU{j&bm!oNYCrx&F~oEDaZ=oPL9J~2?gEi5-X)9wo(v9XL?-*4VXDHk#e868e= z28Q6{m$p4Hm6#`pL=f5lfWg^w#*LkIkbKCcYcvcOdp)H=E0jf2Ev7ikl1iP_|EHRu z{-dVeAY^<%FAAFtRuBM=%>+PhlF?S7TuaMOnD(6lz{M@7nW?wXx+CUFZ-QzqSKR}JRKTDtfJrtR`-Mz<4>-utv?AZeGaQcO zwp)a^_cnodX6G+@CNvZa8`fib=)8`P7+i?q}L#IXXf7 z52cAe1uN2+c@HMFIjR&^VSwsKKFzDe2_N&$_czU5lzprq{ zpL^^LHypEOP0n^~mgVY8C`d?5Oz&&>VhwZF<-ek0e@v_mW>>4!@6YRAp@7~`a3R`< z_>jJB?$=%!sZ&OxZfUc`aXzU9(eB8G4!WGkcY`B521BfBv*ggroU}VUnl#Cf8>Y zo^ga2SA*OGo;o%1WrEB{Y9Cv`~k!H(iUX7#w0+VwjiV`Ahs`5Xp@hL_&r;3{aT=d-L!-JtqF?W&qD77Nu|k=% z6ixOUhN>euKD|XbZXx4%G7s`Hr^QDWyAmayRJsptre6|f?r7uL=h8RQRP{rqp;6yj zPN%%hA;PlCx#=+~9x0xvUavvAl4DV;vD%xjD&wvj;H9n@NP>9>w0wSfzU)>VZ_kRf zm%;VmNXJUkJx55tvX1?CvU+5)nEyMnCx5n|So|gnEa%XDfW0*|8QC~v)5T}Uz62MK z!6$h~%<$wrJH)19xi<&TQNoUZN+rEoY&B2NBxkP<;W`*m3{8;IWs8$XG*w4TCj4GC zUWTC>x}Y=CC8*Ii&*!={Nl+GV{SmDOmQs#Z@}n8Kwa{+Y%jR1Wb)`z=;%jNMX5!4o zM%_WL5jtLkl)2Cj?U&Whi4sId_uKw&f} z7$KaNkZ4MrRKj5Z&!Vm*tRgGJW^1o}IQp~+D=eaS%ub5mxA}6Nl(ilFFvC$6)W3s? zQVygu5VMu~!RVJr9^8ATxq&ILVK;|2uTtZkm8Plh6rSm332c$A6<|-PWGBt&Uj-tAWg1TG~yOb)R|0wEJKU?GTXVQJI-f0 zJ@fcGl!PrU5YgmEgnLV_oGne`>_RJ4k?{FSV>Fl6gauL|(xrIKmwodAxUyQk2t;-M zr8j!Nu8`M8H>})$qP_#%2~_*(8J^lCdDz1e`crz+jzl_rFS9FUR7XB=`#14YbKD^< zz8F@-xsjc08Bj~uAP(2b&L%3=@k{c$O&hStuQPtzv1sc*t-5kG_8DuxATMHQa2u@? zWDJ;xr6pi_JdbOF=O?%WcXGVOEHjP={5~6euAX`aba+1a3%~SGJ(uMf;Uy36GknK3 zSU70DyZs$UW8uoApADbC&#R^7VOjrA$9GoiP$6RBaMyWbr`X>kYus|IBc0=hKBem& z@WuVm$H#@^V@vN3w5Owc*|ZDwmNK*3xF7syNWA%}mB?pImXj3M#GzbT2Z+$}|85Tx zlyYusUuo+C%97?faG%F8RVyX6}%QF6W%)>FSZ%Lo>OF+ke0pZ>6?f^L7JT|IR}5~= zs5^$q!y+!}J&LmP|D4l(uVVTHNgMoUI$`$Ib#BNi>`ZHO9LGfL#k&a68S;24bXp zDuL7VSsTKFkr7-<_bfo0t~+}<{W}h(L#q!puf(!i9WtJ#2+VE7nk4Ov-d1kPcpYjy zvX+6B#ts0?RUX~ia2GY=9H_^B?iif;wQ6u4!+ZJ}l_n}z3jaluoJ)A1fo2aiLLF*V z*49Q+xb$Xrs}qQIqIvQQL3tIyxJ$9*vo;PIc#XR`-JIRFwaVm<&eWV4Cj>z;=elw4 zFVNCHLqR0OuW;USDwo1j7ADEj*GPreBUW+CHXyxuqoh>4o8YH3w-n9JZ9+$wke_JV zCl-|Xi0UG7$P7#y;$}seCXMlgIvosd*xA$;MQpcRz&OCVzw_>*+V^^2hUQSXk#|~b;mEXJ7uT&+Ukwzz-S{ z@gQ^nbp2xG($BbKai=Y}GSuWtPF*LAQ-~o{7&Vy#mv%d`Vl7zYw!IMGYwDRv68@ro zI-NW)K3jI z;56AY`>K08=mQRb@?4dwJU(+I?-p*lEM-lES97xc58lf9g}h+AUH8k54Kq4V?6<@K z1PU*jHlwPY;f291riv-h<%kycFI$ckr4c8x9&bkpS!F%<#ayPgR*Bzjk!tyVocN)x z8`@rT$yZU2bDEDURcX0Q3a_gn3>o{Jl^gT=mH$`X1TK5h2-|kpH}`-s(aOrs0rDDu z-$qX4g&YpDj>(T6;BUtkOA2sNtRA?E?zFcojodrw9GxMGEf86rB!O}si1poIcOa@3 zGWltYf}Y(x43x2!j%e4Ashe#hPmF>|Q2F7{aatr*mxhr0R6G{;w-hZa)dQQr}kv-){^0(?~45H#Bp08#wCs}nv*SB?E*xW zF&JhtLm6-nzr>-w;keGAk_0W{w3JeQ?PgtN$K_pBN3^5QACR6+u35^A!Kcp*)#AgZ zt^4cLue!Ei$H5up8U`}N`LNipQZdA%OYaZ_eD{^m(Ik#VCZGWMeb|su^1~bs^&TFsVy; zXQfC)ifJLqPY!Lh^9KXifpJOJaXg^?=Dt}o?;Y>tfmC&ehE&`k71v4!*(Uix&X`x4 z_7xaq^#ZD0xu_~X&FyjO5y4t@>P&>Bu?0#4!%9FaC-(=IHD%;_kf?4JhZ+m*YL8N3 zG*Wl`^Mk=l!yG--WO&3c+rP5uPq{m{{yA=Dl;3EM<+nK8!!JD{>QLLIwm$920&W6s zF68AQh!wW~h0Xg_t#%X#1yJ@S%ykFl(s5p?MQpQqXCW~RyQ*nx9ggnp>6kmVeBhL+ z&zh&R?u`it1k$F6|_p0UFFJBzAPO>eg`b5LR+3QmkT$wB0(Wv2OsVg z6U!m&&E`tcEhQU^oZ4A=r4gant&hlYE)4>kLR((@zpRr}44z2&N zb^eo^u$I(~)}h$(3#qEhf^-#(7;aKou-BxQDa882_u02QF!}t51aO2!ne2HO#k;TufkRX+JUFf(73DN`}(x89SspID>x?-i^}xnXgRmJkkQS7`IU1tQ&~Q>E)^ zX2lqS7s27EZV`Cq_}L9|kIeZ86e`>iAgDxdC_5zT-~4KsYAIiLY$u3eYu|RABFck8 zTCqjBw4UvFk{mv*$TlfCFs;ZoH`!XvjJH7S*pOWL^6s}we9dvTzb>n*b)5y$iB>;yEUXE%-{$0|87eeB>BuvI#j@g4sKTsW|(KbDMvB8@z!YA4DaHZXlw z6`q2fH&{^jCn)WB!gvPcPFsV6eMFA8z!4#%W{tQ$AV*v&cj7{WYG$>limLu&wiA~e zODMxTj)@u(`%-O9io3L*5X7K?XiF_HuUNUt16_{WUHflWu(avJEHx}y`4BJpW`is< zsn|m^nR<706c`8Dqd@$*;Zms0qGw1Ql8R8tS<#uBfm`cOYBZbWro;FkZ}}pu4%pYo$heA;Vj&gk;ZNc$gkGh% z+=@bbxQhE&(N!9AiH5BKirWeiaLr&BK$2CfD}4|M2LL~+=h=32nmNoh2&1+CLf}D@ z{SKuW4VmPrw*I}IpAzr>J2e0j;E46QY|LEQw*9N4JYbnpW4l4yyHYnK+Mlni7;M@M zzKz2hQY+_@0cVR)Y>o!Vu7YeY2i%I7Wze{%?zNme?} zvbVwB=e@G@ul)nq2&;5+zcS(=8aBnyJ`xY zWjH;X?7X#2czvRmYk1dNckh?7=L(+VziA;)qQ$jX!^YxtacIjq!A-ush>6(DEyF() zY=>ZNmo87LU)K~r-RjXlpQ*-Ytk9YH*)FzU`1Y-6t}&-diaCs=syo-n>ZJ--+TwiP zDN-*{@k7)qgN&>Rg!$%RmXeyZB1 z4NW(!V5_mMz{mRH9&v#3#`_j#T&CtbqBUlCk(f0SV>K{tS>)c(t zB3CQEFRXk5%t`Y{Lp#@_Q5=`_<|Zn2KQ3L5_$Q1JZS)RA%)OGon%#sFm$ofl8ei2B zNisxz@Iwy#hqJl9%0kMI2#1i#N4Q)MS?%ZwO=l;g5_gWQ*}lWjC&rn@xmuoZ=U?bf znr!m^@%V4VVI|0j+3i2R*0=FA8=2WK5WNHH**S4Dnm?GZ)$z8E&9dUq{A-K` ziy(GDo~cp(Q=@X*=e1|IMg#d@p=;yqwySB(r}3@X930as>w={X;KpaYs@Cx94~uog z`h)L?a$%uSr%%jOIIyzhqMXeWL{t1Kc(|5xJ;|&_XCH2CrI&(344}~dl=*GE^}l;t zv2C`(f@b6VFR^XmsToBG?Q51@BH_p{h#DLx7WZ>P81JHF zm4T}1YnPt9vWhch$yUs%FlO4a;>c$jM{fX0hR6L|iHW6a!1&$qE4NrmIWuuj_C~ZR zkz*gW&Wmb^**vn=_Pm>~D156823>;EX0(OZ7fhhs7;fBx+#_EhvwolA>Y#cyNF22~ zJEU=$y*dl=R&v8O5;I6V0MHCLYfQ%+LM_Ubxzz-u@l8{_b&pLq_zH2Vle1pu=qNHKJ?9d zbY^2GFbt6;x`gZj_BLg0Mxm?A_B19MC-3Yjai#{GOo9 zLVuPCBCKe?2uC}e^EIvd`^`mH?V`EGcMPJ=oihWeKIca@*z*5=sibmtP)#GP3IY&P=%Gx@ zp}@E(;62g?G1-TZUyD<6a8qof2iG-dDA6=V^9jHv37DAi9hCpdVUz0U=%JAqkgMLN zq*EIIQG-cL0>W3&Dv(Mvm=l=Z$1&mDg1~8C5l*VvTN)?XlP}FGNlyCx;oP`ZdI3bnc2-RAl~TJV*v_5{mX=SI&<9kZ zF9ZO@9sw6h;L>GMBc;WoW-{oAzK5l!xJhBdxJ^vt4A66 zwk;IhRHnoZ>fj6A+uL(%Cg=LYT~Wj`Pc$(%>m&BM)AVDI%{dxutH7J@=Pa7L_MM8f zrkv*;@M-AbZSI!{m+$w{z2M(bj_y?GXphO)5;Xxu36z?NB`W0T-+#8*6d~MaO?UH$ z_V0jrC?l0?u$W2hXbAtf38u9L%pG&77hnNQ%#}j(46LsdQXQ9M~!2x(BFpLnu^&D@NpWaBLg- z)6j&zBV6{sE1k~pRV;j1`U{-?k(j%-=;Gs?IKmGUZ=b}Kwy(~WREKfj7!}Zojt;Cm zamS}tE+i*vY_6~us}^fEy^!sk^!?d0DwTZ_Z&BB~L*y@ba)ffZ{gIY~*vq2lCl>~~ zuOPtE#9t7Q9_6ph=B*NmmhUdi3Pe_6|eRl*R0e_WyAMVdV*AKC0crkBDRw9%5)@L1>y zTP?(G4SrR2>9*uvzkh~hdk3ihRq*or!@YZhW@&AFUw*$8rS!X{C=%hRX}})D8;T{4 zAEjl%QIx%N)Z3LF&c(CgIIYs6YFl?S$0kHbJC;n&0l}d8(_gNditjnoQb;IcfDx&u z;T|I>&W}gjE`C9c)HCObW=Z^QS<-VWvKxam01U6-TL=%va5T2XSiPZ2b$Zr5e^zLJTS!&(!v9D%O{tL# z%&3uo2QEM=A9zYny4TCmMqc9;Q4h1u%S&;uU2YVGWWMXQ+oA}Yj@}8hp^SDbPD8uy z_(GScm9zG?S6&L_GVA_Kk-Nix9Q%!^<KEUFMViZa5)^;T zQA`j`+YnNEfoPF`VD(}&%u`tKlb-zW^ zNF?cKt^h%bR*H{?_+D5vvk{1+zjefYR}d1KEf^QFl%^G3Y258{6h_3mS`y%9Sbo;D z4j`;IotS_Hsj~>ERCaD#)R(BQs8#_Pr+8`ku=s&Y<%iHkz@0p5Iwa~&M64+us^e*E z7|UTRQkpqGS*S0KwSi&!Q!|dB-1tfw^gCv`xpT#F^iYwISPikNNhq;tYPop#12mIt zk_nlXKV<=bp}_V^QFWlI13}(vEi7az#ridYC-&ddgG0GG3%t8R5y2;1mAicUqX7HI zpmpvZo&^Y{zR;(5?6E$W31>y}(f#Y~2I&fE|Gj*s!dg4tW_!(4Z7tkGkh3ZVx4C47 zl+UylCbpB<@J;_qyH0`z{NJgnjVubpDc+3j8{D=U{S`X+p-*mgT;Grw8_2Lj1-5KzF*LMz)F(1r z^QIqz2+UC#==WeAjB={CEQPU?RJsZ6Ya{fkFcA}=L;Ag$Ftq+poF}so zG))q-?FAzRHDBbV)YI5@$1;nrMtC->nPQSV7P8^@kB-FBQ=weom!v?2q*8dRqfl!> z#wsCivXjtftLD9HRsB?qq&M@S*l78|3H`3Q*jN3)5UyDV?2KcMY#$nFN=YSxp{xhJ zxEqq~gW$~+ANOVx{w&yiJ6(S-DLeg(XGQ~frn4A57S{z{mVtx)Q_!+xp^A_xaSozZ zY%^mgl>{_9)ghgjT9*NAR-QHiO4Exu9=!pKdwGVc}ydDK%ZJ+t;I6nt>!a?D&;tI98x1 zB|a|NTxN!Hh3y}A1g$8%K;{&dgko6Zk&b6&XF3?YwqKGyju=PZ0g6EGU;JAbK0w&O zr=m{cc*>rF@5=zj4ajCa0?Sy5SiL1DFBW;PIgwAhUDCobES7L|M7neUm`!VVZ{^&QOR$Tytt40;9P z6xG35%K%wtd4ShPN1zx}v+oWxiQY+dD2P2JTG44ayU=X2EVy-%w?9d-ZONS&h(UtM z;~O@e+bwu|lFOjN#X$O17&Jb)cRqsb`X&t}`{_g##Ti+K|)IA-%b=IRbrrSgon>i5`V{|PITOOByc=f=al2+2)hY!by`l--AG_Z#R0;?C*h9?= z0&*^NbMFUqFYKjyu9+W_e|pZHoN*U&lv8%z*9?O_mAT#lUgP-F+~B$@6caC;vI-*f zrs6FM1N9<4Dgxg7P*o`$lGVOg<~CSAzyooBgw|A;~<{QN&|F8PA*-f=6YgYN{?PERY>aDM0r0htgFrps|U{hgX zSWQLzaALqR?VmvOWooBs>%`JscO0V_g7>w-UJCkMrT$%rLF+N~28%@sK(Wn{grTUQ z*HTrwH1(~JA$&f^E6bFfyKO~*_rE@{>F*59SaQ7XcOoTyI`9x2i>9@*h~sURY$|9ewG2(BJwf~Wa&pnBTXIY4@`;j4gkZw z1KQA?o>h2X%Sj(rg1h_}cwa03M;_@m_rt(F&G6;tdV*?E=Lxo0>!dR@(p+Evl)zi) zJ_;9q*=`V|Sc=N5I#+G?(-G(QE(f(a65~+M6jp;ITu~Cs?G^D*=+HFv5TUk$+R0f! zNFo2P0y7DQBvbUili>VY*a%O;HbFMH1f-+z7@Iq0^*7z#ts%}#p|pxyGA!NdS_4yA zz4R4Mlb53r82o8H)baYXw4oPCxsOS7W$@KgukiFR4ky!`QxGk+9xQE--O!jRL_Wg6 z$5)a__0~#Yf>8lTv*9dQupCcMl{+3?A@#um%w=24)zk|~6hz@YQ5Qh(fK$ZAm=oP0 z?$faEr4zb%-F0Ebnk(`=Ng@|8a(Y-uVR>s@chSwvnt}YYMX95j7dg?mvr_*{MALD!Ro*Sfl5}cEbXdqN^hqo(O?c zo}{5cB}2i@HMR)=mK!4)e~D_{FfjpC^L0plxm+ciok-zpCRovS`W=A!lH9`G^>cgk zjHY$-h4Zy`N&&O%ZQ`uWqx#^8FkMr_PC4+_sEA-1VDqA8ToX_kzpSz_eRXm~67AU3 zT`8dpl9{g(yJ}>apIwb^B0=mEr@-)~yp=i%l{)Ub{aev@nY(eR?657|7JB~>QV7`4 zWE(2c3$1&~wLxYa@Xs8UrKGl+#h0rN)$RkT$Y|lP#;wjrw^V&*xNFe{?RWE#-JurB zw8$2{1HM0VeusW5SV6ZBeFt=%(xQkAexOy=<65|e8vh@f-vU)9QJo0}07Q(;M(NE$ z&=&R@3Rzn)7Lbgg`X9W4^JoJ$u~u1xF!?0eg6r_DzGQ!E?A*-p#pWKgn*H8J77_xN z^`<{AIvwE)OOb$q*W=@Tp|X^n1pG=y&`|J*w|w4}VI4!smB*{iQ059t8X3lB)VHOz z4fG)48tKi5$(G;$*2t$9e>)9D@D*6$GHo2`c2BR&N%d-?e$%_3z-Z*UoN82o75fs6 zZjMYYArrcYVeg;-eOZrh$Th=9Z0fAiPG^9Q2a6Oko)Jk7!q8z;aQ@CrQ3xM}5Z1N2 zm(N*_juGarq7o$lHI@SqP82HpjGsY#w5QIVU{)nMq~_))g|G~Fp(TMhImI@8LyGJ2 zJIlL=s5scPmYt;5;4%7%JLjLc2mYp70yMO*%fr`DN;?)>s8~)VkEUs6hPs-ZcL3|& z-4o<^rs?Oh_LKW42T%WEi8x_7=89YJnLnvF@v)adV7FMb&)@g=F@kaxh(gl1o>mlnu`XH@Nz37P%eW z(Bb6!EYbcCkc8kfd)z0SC%oL>pH3kp%^pCAZ(%AWQ> zQ*lcYt@C1t{E}8H#qn)dUEmUtrVM$u$YeRq1Q`S)y=gp9%;0K1x(1 zUZO1Wk{o=g`5ocdxJd9Y7y zoM3_9AyO!HSpuVB41M|rl&?OqD75{+ao?4h<9_}gn%*)lAln&d0eIufXDSOSc7+l^ zi(|NL-8`ag{S-5t6*%Mwpb4 zbZd8ggd@T`;5Ams{AcR4YGih@!D3&bST+^?khDq-_XW?FW)~LdenUERrATMu^n4X& zpMTN`k!2?3;-nbpu&T-#Y1PRmk@-j8gBv8Jwo5xQXuI=sEc|_X@+1p<7p;kx zl-NThZ*kLQ`OiHZ$)5}e?OQp9z6IPaTIkM}+VNc}MY#(J$6i+7MpwDFNdWj{VOPcf zDop6y((0VOs4{QoG<-fdqeB}PX`_VxCOt?AW6e?`HyM}t{d8!U3o?7>JU*7}(NM(0 zg~Z1^q4kEPeZy=%6g1f_{0^8UU2%H{lnOT+LZj>HfT)Bg$oR7V<`?P{{NU9-3B#b( zYsp%E15WNLFFMj)P9!O|HazP(hiQ>*56CbOD2YmfWw ziSWXQ{V*?!@RvSK5DdkOZ4Efyqe)o0rSj|U%1YJ|l3QjD@Hp3li{^BP`BmEGan_?O zx23*t6K{Y87*PDiY-h@2>D5JZHFslr3I?5LuGe?5wPfdVhcT14AJ| zQYxp57yf>eEhvW-fcB5ENk6Vt*bN6?+~^wElnGjGfk~Jqh;RBEhQ- zoE3tUUCe?#X;P?1OXXGn-2e6o@Jliam-fJGmS~+Oo*ccPuE%++E5lxr z?7q_T^7E~oMJ5?gh@BQ_`PP?mmti5WDvz8*)yYhYe2M9E?xJn#;;FH!`$!z?x^NrP z%VMHwzmff|eg_=e38$<(-R3oL>hq)x)CaR8%2feSGiX}>a-H*OFGM^U@&)1m^Htc~ z!!Q74s7J~V`VDp*yk-kTkOn(c#TcExF?!DnEw4K*ofFTkHC9bMXH`0HSIU9jXUbmQ zWdhex-NfAXw+Sg486yF>f5n<#sLaB8J<~A$Vr$r{7Bj5=EJ0qrX*Q)Vl1jw-6C_Ti zUSk-A0+r;au+}A-fB=Uem$7z`v_0XE;z#5L8^Nzd*V{b+DAD3 zk+z9t;C_E8mxccASouL|Zg>4gY7wPMgmUtC#`D{JmGEu@_&W8I#=>O;kPF1Q;o|D* zg6B~t=}eU3#K4={RdWd5(7Fi{1G+-(!TzR*-wHZ!GehrV9vFiy3$R2`2! zF0eLG@%WReQUZexf`x^JS=bjV=h=t2hK;&1(4`pq(%dSZ@TL-%)0DPy|B@+27bRyA zH3<5j)F7w>5G3&eBLApBmnivg)~5fD2QU;2-2dZP|M52@1-qE4>7`3>VgY(X@AmW+ zIh*MJI{u1Kh|?H>#wvJ!cIZyH_1qUNOvmmL4FCMOdDZMynYl%~UKU~?7h-_I)iRxY2=4(O}ih>)^9ZW=7^+ zRLU1!L8&C0ae{%UV8IP6w}9FmM?r{%>(}c$13taTz9yz!tpRNT%{TB>mDPX@XvZgc9ak zg1Zz{O@O%HC&GlT@(uW{XaQsjV{Vl-3(gY!+_)YeA6^m5ncZ{3#cqP^j_}2X4Az<6 zmAL984+X>?Q(`cWLy>N{>XWe$~BE}s{5_vaKUfY5cj5L z!yll~>XiZ?;~nIMfj%2`U{Y)cU*1r)URFE(8ihE7m@aShS*2Yke_1m6Zrw}>AYnbyMCx*|dZ2>BZ z`DU|)<7i;Xi=Ymcv&ceheh!xD6A5(zN)zqnDjEiG_N{S~{gDWZJjI4w%7Dj+CZ>hj za@c$cpVeV?xC5!ItQszW-v~n+_({0_z(}%3Qe$L*pMu2N^A;d*BAC33@ocDIWVODN zs$pnMMXVGasx1RdAGECP8%&*jCED^JbRIJj=phovhi@iOTBTo2BL`jk2jhb}En%{+ zs`;ALp^7a1%!fFyC3#Vx?=b*6>^K^`Ski2XvBYNMi`n@gfxo{{ouL|;1KaU|nSB$g zqH3)ANd_Ii`g(%~(g@oXg8=H>&(ctKvAD;XPvWHtO64gwbO_HuhF?CBEJ})MG5n>d z-ReibAPWWoB3Inh9?;F_X<+*OyNWT&n50>C%_k8wQ&kSJ9WlAH^YM+ywNjpn$fh%V zrk#NfHgJz(2l*ppyM1q&2n88TK`vaDaIECx=mqhwY?v8pI%O`!#iG35!9vW#=d>@Z zXvz1GM-EsWLij%t9fxd<11UfQUoUYjs9+7NsF4B-I8ki@V>wVUy$m$^`lB5xzNwII zZ=|Ek^#eQ9mFB{2&LpZqK5X=W@j$)JdN!i;7epq7<}g>gD;yZY5sI&Kjl$?dhA$)J z{3FirMtpqGjqtSb1JLM_gE+8TN|RquXK2;{8uxhljJw$S+_;p^;Y)TI`pPQhbX)+l zf$P7pX6?!R08j1H6asG6dTixl$1Y6_nIdd#c#gdE&Y`Cf#M+}PkoGPhxSOXc13^pw z>N%+W{wM9zF1 zWp5w5kAxzE&Y~!*HvAk`dfVw`NG@`2-R5r6}K7%GL@I+Tl`CBFepx zB}wwhp=d_GZ8TUy+e85r`HJSJ(2|&<{&)gU3R(v3SNP@$p!D!_tg(am(&EM|Q%wH- z!Uw_IBmuvo526oXlw(MDYlnQ%Wg1{HDJ|T(LC*yDur~nNI0puPpqZsyg%|8&G;+eDZDjow!^PGWVo@jX(nqTz9Vv!7=5?%`W z&~Fgk2gT;2Uoi$iToo5{O1sT}oXO&xK=Q!BYua_IpVe<;(BZ=%c7COt@7t;0-ze~Q zL8+9F0Rziqh3rVtbba-nL-yIRq7$jPXe%E_MF`C^vAGx%M@mT_VQ*G+kTi;jB7vWz{IGEkn(xOK=OjA`A{y=ExNz5p#%Uz z1k^xomEwwC0Kz8uWh!N%OQ!lc7^euhG23wG{mM%0sP$RvIyQ)$M-M2#=Zx9N)Owdu zwDBflzOne%S~q!)60Jk|BL6k|8Io6M_hqMTpOZZB>)ko;;y>?|oSet;p$WI=&GOC2 zo~_wY-PScLF`=bcC(}oUkT{mezX$A7xYi?Ok08jLFDiT}6qkWqYXRPfmOXPgpp}@~ zM$CDucLdcr4@pUx&z}bFcm7HVVT1%;kV>ZBs3SWOT(KdG%Jo7t@G-xpF$LK=xf;*L zAc@W&DW3iOrfUM*3R+W%Vk!ex2U`JCGt~3W?5$k#a{>Wv~@9 ziol$b{J(fQ^KhvC_y3<+jb)gz@5Vm%v1T`8C(9@bNn^=gS<7yQvF};3#n>g;A}VFg zQW6r9WXYOD5*6NGpX>Tvzw0{Z&vTtW&beN%`+hwi&*zQeL+g*jD+S@=YnHO~`hn>#Lm?fy1WAtj zyUhMO8S}PkfcG#b`@E_3qqx-l{LP+2xJT5y$=71J^lRZtHEJ@6epBXvK zWm>8C5P`4OWVHng-;7P!EF_VT>_J)wJxw<6x3 ziqj4L2Ut7@zq)5)KZbSm#Q0hWIElrJ=ZlvTibY6(yq{51MLVrG6!=$=C(DGd7T9%@ z4}ae$E-zS)93hV|Hqx5qwSNK#haPk;_+}*Fy5a(Lm zNr%cP^v2*{sO;w-KatKOZkL0dw!ddJNyc0hg?&xJ9E8y;_nMaP5 zZ)JqR0cXp*!@}3(SO3gW`PtC;k>m&sj#VY4w)pr_o^y(2}g%okrKv#&g%bm)fB?rn^elK z^jMzQ0%{-!-9n8`1_3dc!JYv1mCEOO0 zSLW}IJ{IZCp+VcuLGo78Bi|3Vp89jBfreiBiJQx>-VFs#F+5`o--`MEvU#ykFv0?1@ z*kuj{Ni2oWuney-kCWo0VI>ad;<1?93}c2suMMlvv?`t#SWZ+oZCzlz2m9v+?ODkC zVC^ns5hl#QApKye$yQTYZ0uL>mHu5-8$#Zw;!_S8{h)+_&eT_{A&RK}ER0@noD|)! z5JqKZ$w3f!x+mMpdevv+hIvY1Wi30VVw=gF%=7Vtn-8ZzpEY;B4*Hfd&r(bELq59Z# zzH?D~yd3#sCKiBQtz$+WtYNY*8pbZVnvT=gridA3{R<#qh`t}Z!nFda_%`Cl?%;L) zikhI*jB7VM5jiHyuB#vpm#nx@#Ya!glTBgz9_d$t=Zbr>jT%rQfX=f?cG4o z6xiqrGwrA`(y{c`lifT8^?R}?{`*(kVm~a}RqnK67cRMYDL=Xqe4Ih!>BHU|J!OCy z88Q^3sMZ6qxhy;biljex5shEopmS}~(-5KBI zUSYYRxC)WTt;8uBPjSG=j7l-r!;fnWu5IJY(berEr~b6@8uo~8TWlXBjlQVLK4y@KpB>Z&dwDCV|!fK2YmF3Cf z$(!(xa7HW`#1nAX48-xJWG!d$vsv14$L+!N(SmfQBF2NcDM$LlQ^D~(44fjBCg^rr zs%9lyKCeyB2$BlD2nD)|)6^?SX{H;mNxt|9MD~S3G>8%Ux#D}f*cE;o^s^8u%45GS zy6mfImf;PO6NcZ*l92P4g!t4`>46hWw#itWP?QOgQe`ecwCwm~FK~kLikJ9>xJtOu zPDXYCr3V3bk(pk8C!d$gQxsVU1#5ZQgOm%0oKouX-@YwmJ&BV$9%UwS<`ZQv^vFm4 z@PS<@;y0;;y?OH{w7|H&+>5~Sx6hgM?6+J0!AT#us!sqL_u~A?r}&lu!T8r;ZH7FF zq2D&DZe?|lQ5hnp1K~)}fjoTs-rn970Iw5ye2hsJH~R0oiW^~-zF~`ZyCPghfJF$W zQ@b7mV9Q~ZnUl~mCVG=Qcu@NA^U(qIZlsWV+wlpRMd-nGc*=vIYGAU#z|k-o4qkjS zI-p9D(n9}8Spc}TVcC;k_JT)YeExojM_*zWpRiecDVw} zFI~0AG*>1K2sl&q(V|k6CB=T!l0l(dr}XP~^baD=9-Qg3*I9s~^Jly~SwqSZ%d)V) z?zzF5b;~OmgR(cCK00ItNZ`_H5C9|7_`6V!7}s34hfgy*D*qw3$s`3~MJwXtn;08g zC-ri^$Ekm=PIZhgvrbR@T9icd}Rzi%Rz%6g3TnzW!Po(bg6X znyL(XdF3@H(1}R#$heK*45j=QyrB=fq^c-8>xfcefZzBsOto6AB=11FU;_z*ZVBx_ zao2CwqY65iQNub%inB|gKQPP9heu4pWAY8c^uZJW8F;*3g*L!> zq$k~{aK$GH_?*uUH z?X=3z=S<37eG&CDDaQ2|sA6=X$M#pE5@y74O9M>TKII2>R6rCa4f<=+g&y-NC7_bg z4DFmIA&C~Pe-sLR%wB(mV75irc)GO9CI+#&(W zcmx?=m*>!W|9Rgk#5O>)~z$P}0O;GWUBHjBg zSi#r0L+X=SnS08z#7YL1=Xb~fQWx@QAfl`aA7g>-MO>Yh6A56#_da!@XOB-KRMvei zKR}Q#QF!&u0Ol$dG1Eq~_w?@lzE_Jnv^hK$6P|j>S_-s*AJow?_e&p(?j|w0&-eaD z-H@OrVIPmCrDoG*7a6V6xI47}SkzSW*1z)nGnlZPm5`@6)j=L)-oE?#Qu|hhc54sI zxGb96rJ_FR?xSfhk;8eno3CmRHL{ktD!3P8!%)|SN!~ZgLxpo0hLG3KN~pg?c+*zy zS=qQ5tETg+TS;b7q`9S$@)8!Xup}?-Q6?H)Z{_O_efQiOw;}wxD{o;HI=cS>1@_P^ zX+lV1J3_+`|4VeySntC_5I9NlCo_%HCy7(GQBigQtX=JfFYR>GU5-_WaG@uyJ9k%r zE^Q1S4$2i!M)zOr&0uXR9h2%8e^{KnMf@_~a$ItLvV^R=5NBK1Q9j4Vvv=oQ6bm*N z=8=Ic?h-SceT1iA}101f8agC_H_XkjdU%Ms z0JVBxLBTZ5o~}Uwvs?r$r8JJ7uQF%E=jn&Q8oil=?=kqTrdSF0h<)V-cg@}@JZP_1 zpt4eH9<0uYX+X;gW7n=YXLIiIh$Y728FHH&>6upewgbq2JD-G5>>zRWYY~R>FKF{5 zOyChmBdYE)>a8EzxKpTXJFrnOYf+~4+#!^n)+2mvK3XCt#{k`)M|{3gkOmlp46h+O zFCutBXQF%0Fj)Gsm}nAK1hah2i-5u;_7AHqD&}(d>t%r+HuKrX6v)uZ!Cp-PG-ug49ZT6rj=YkJn zACX&<^)y&M<=QW@iwl^MgU&?4@S=wY0y6R(L$3wge2o7hm~%VQKpOS_$zOe|?-g`O zE_1xJX#l)J{)G`3j7{_ZahbnXNU=)dE?8ZX+b8J1M=6%Fuyajp^>O*zar72Mxro_&kx@+Ldk(ZM8 zPpb#Ff2ef~Xv7H;T@P+IOFUN0rPyT#{;T}R_#!YJZeOY(qVpCStf)b64u%_)xEMu+ zpktdR>Gl!fiet@BoH6YEgjljOCZrburp^7OxtzgNpBc3xISLEn_?v1q`z z@j?~QH+vsz_VwZt-R8l$=4|o~z^B8r&R(w16heldfu`W*v(8bL&JQ`C70 zp1%qTEeJSh}#@nEg&~d4pW`w^4d@ z*i38cF=EcjdY5?Nnl}m_h=b?G!e$#7xtwZlksFF$zFZPc?`Qxu%fQ|+Ib?a?Bg;eP zpOb8WAA3POn^*Uy(PDs8+^yXESR-2koyAgo54~y0Bi7V}Q#ZR8YQp_aGTniHFE;%~ z;rlv&{%g2;C$%UmNMUYhQP%v6%C|lNY{`4~jjlJsX8-Z=SYaBeG=4+Ad2D_%& zyAq_X9**B5R+SgRMxM##TjVZiOF4?O2+FgzuQ1)U}(JFMgl5C`TIECUiUs(?vlpwoO=m)AFYr zZ}-pifRHuNZJz37be3RM2bI~tC?PfM$Yn9_x-YO4P_nO(wtZ?Z;$`{*#3m>w7FzQGzu*9G5>L_61i z0j8#_%Mhgj0p?MMOeT3kbsA*Xm{24XxSd9_(qNg%b$TPjCpMkNW>|Iu;@=7qN&9*r zZF4E&)u->KDt2s(QH$nAeho}l=`^g?-s)CYU2@(d`UixFj9-1ak+2dHidMH(J7^Zm z{q#j^3@(y$x%Xm&sM$z>cmEv9)K-kJEcK{uFMqeREZ4x;JJRzIdKwtRqem^9N7c`W zZ8=~>l37cc!u|u2Rj#;24!sW> zycLs|`&h|Lr0KTZ)N4h~(1TfO25CI4xASwlKRMydXQF!7;fA#B>rv&-v@F|Y4&o)G zE^|gg>xP^We|4z!wo6RXMV<#z5(FQ&vJWC?X@DFM&@9Xigc$aXvr=qy66tSyoq3r> z8%~)BQe+(GFR}{tGU@tK&|%zXrw0EUAk4?~=187I!^u+dsXUFP4mX67MbVpKV)}P{ zz|-Eoplr#^H^*xwAJmwMGscx&vqHcr%;Vb*LS;S)aWL8|!pWO-1JcF{ismgrI1lvI zKeB%OkrF=P+%5h~+Y=w2f_TY{zU=lXN)m3;am4qT^zwAgqxcK<=+?efi+bJRakQ`Xw@1n*_+8zBODKoah2BYy>SvmUIcCZ(k7>k#4_^7cOzlDBKKx>pAUd`hb#Y;Q1H5Ef}NZSN)&NjP6{k zFWnVWnSCBrPR@Q-ysBZQ{}6mfzf%DpS96xr`k{zfO|)VCkAQ?|CCUk8Ei9e^;2k0` z!nO9qNjyVyC-wVRaajy^z868WI0eP8f0Hqhgh7V7jN}{GUX_+cO4H)GDbengQ{&EK z>V9~(E@|sWKraSXuJ-z8@i%pJE49ESXK=m^iu(qKN;q2rq$0a$W?Iqhw-J{ZB@5DG6t8oHnWlSf59Y-h| z6rPrSSp*?dN1&u#hCp}qW7F5H!>~(v6tal^jU|G@mcQ-BO=$uhMM#;hNr8)5IdTlK zLAs`*UsFkcdDeEq?uqDer>&g=aPXQ9X&5Gm8!?zh0*vFJy+LT09_Zwj6cx4tGj)pPIHGL0=m!W4 z%w=Ulv2dDFbM{sLmfM-6f?Amas!;;cKJFc%RPn(RkxnmpBfA}qoOXs1uf^sih<6J6 zU~`{bT{I{Q3DVO;DdVA-!Tv@LDmW@O5^u&RVcJPzvJt&*7P8t8qq2|7e@IFHnIPbn zJTDh$qar1**E#lm52YtILmGE{mzO+_s@l`L>ETovcabg_(|PiyGp` zzt;;_W4oknP#4C0KVG^O%btZas$o?JrJh{&vANE(G zbiR~zCSSVFy>j!YmqQ$!k4F5IDG4x>W-0{zGXe<^;*enh8)-;>QzK~G}N1KfpFhpOv66n6Oc&LyWLjB;XyNQNQn7X8$_ZCwPUUgLxI zgVtR>n!ZLSy%A)UKB+!Qf>Oce6gq~sto8*FwQ`#D8f|)cF+pVMawALNZoo-#6VvQo zVKo&zvZ2M$!+IXp++(*<%S}Sjk7)~vC7NEEi3-k3$rbiW61iro?dH=&yP%vRcxR=yA7a*Uj&82LQuG2Yv)ric0Fe zKfW9D;CAt~$#hppJ#0&8O z^A&aZ>pK?+E-B=6-2k#Vg(gaKagNrC`$0Z<$EGLDIc;}2Vui7)(Pn^iczWYo2W#n` z7h4ZLn4lXvdE}kov|O&$WEu1)uHx@ZOu*86Q}rL%nATb_jDb7}F@&qziLpO+*KGJ< z{mNEt7tG*p9<`s}3+hjT9L6~6KNhqY_)#Mw%X1W?uB((hZ|-nAcb4roTd1*Gwc*_R zCYy6%mW92`&kO^ut}Dbm{(>0w^zF6!Q0-lKrQKs&^wI98;Nm_-p}bS2Y1hAcb@;tY zhagdJ^Xz?_{f18uyK6Hx{w+uSj8i2YzL%7%3^AGp!{*~p6@*H0ty!Lv! zx4=0FH06goW{w5-d;W0|5?qSD<^_AKz4~L z45Y^U1Cl1IX-F3pdW0eB#pZ8OMPc67P#53#{Pde&-Q1iT`=$IxRQaR$w$r1Itl%#! z>zgZ!@!grT;@|vEJAKi6`!70qf0HDNXJGQI!4IF*or{NG{J5>I-*P{^SG8RfbX`O9 zb$HJ^(u-psPXKPQw3ebOD9f_cA9C~`kN^esDLLM3Dm?i$6M|!(WAlciq@UPA6D~+r zCsy~V-Wc~OT%po@Qv~cf*K_B>3ZzI=Gq2P;W2n@Qp<)~tC62Y^ZQu!cyHMC>_Um06KF{kTLA!Q)FEV&_Zr&HoU@tu@t(aOIf4zBHt+z@CDlUIXRi(+SyC8!D zY}h2Xz2GJ@a8|j2q2~_pwwf=--q4Wp3r)3@ECVwevM8ysyPmtU2~lO zJN7;AuPce)=~F4*EZGDvCd@s}0L=45G7m7v$Y`;lFg6q1CY*f1qFT6*3c8n`t4yl# z76Z9jsoI}^H0YaN*B6)OS1-Z^DiCS&0rwOKA4(;sUOh4QJbZCodBrrY`%M)mS#cs3 zPRH5)D(rz?D=px~xw()$a;i|v*54(;=YMluiyk!Ao(bNrObAx#-pHi#4L1gaEzY6q zdeD^Pmu=}G%^#+Y7a5s~(@{lxjz>3+{L-d^mH#E5cvAFg$n9H&XMdf;oS)DPRmG&l z_T6G(^r*N1Q~NE4WA9ttnb4`D%(}G?|CI6Hj*mF!kNW6>XvAJle8#`R{>?+Cv^i+| zO*Qf$?GI;K+$B#V{%0+{oquUn!v6Posgmem6n&lZ5B;ZD(32})L0szhbRN0-%6n;) zzkO^!ccAwYiTUwo4P{-*bJyz2{Zd!hfnJwBVtjJv;M1jZm$%>lKG`p< zrtE)GbS5#ioD@}7_=MA6HKUN#xqqIUE3RgRomQrWzopPoJHTb3UGg|ez9Lhi8Er!% zj#k#g_UBBsJ0+Ekvi=8@%N)}m_v#gtjaq-DKL)7?Kn;W^g|jwM!-h&p*HL?Ae}{(u z1A2gALe~Etj@y8q;uANZJj}7~0#LwR6VJo4dqyBjo)O4r2r?Xeh9I9siTp23OGU5Vdb3DPys7$X{CJ zSl8(p_-Tc9nH?PU?(6S4tq=13WQ|OYnKemb#=lhj6r+KUInYbDRxgz+D&pMQV!9wRRQf zHtp>F!R^#}5Rl-j>8o-ur%I%_I4sla4a2-kpZ9pyJPoYR%I}j|{`zkKH6Ll%y&H3# zToZkn4J%U%Vljvh6~eWhmZ6F7^%fU!H0;{za6zSpV2wAQv>RnvzuhQDR_Ms1ps={< zEVgMN{F@>-^UA|VZl6K(w{ntDgvm2vD^*QIMnAK0&gj8#u-UYLrFw`HDWT^Y;On2m ztrfKiK(p_BYga_+zYXAE)FwfURvtB?{O%mTO|87P?YO$Pr%+q~NgUu^{&Q^ykd|HM zSMQS_TA6}Hn%J?M>SgKq^FP-q)b7-WO_vC{F>(OYxI5pbm`ar%CSG0U@@yKSaw(Js z*-j`8G&=PtLN$I_7&Hw`WCl=ehJ+rs0sEyb8g_eMLT}U#;m^Yq@_r@G zJ|b9V7QA)k_1+uL+xOozX!&+y+0>(>8FbA3Ii@U5dG?z_#=txOM^RBG`8r7}pLIRP zd4)4)ytetD&3t`hC@Z+0d;P^=Al;hgsj=o(W#h3ZQ~JL$qPZt3gXjAgwvdtCKnHc$#>oty*sJ2{5EI-7d0`5c&`4d ze23rVW#dyq?Zf5D-tJ)ryFt2A=GNGRTM?UWT)O+t_X|@JtA(bFGlWL+5*rKSJiq@f z{2P-4(-Yd(8vV7y_xJ4NE-B7WZm5AdAf+_XSXR|aE{LPRi{upk9bqu2;uw&?$n@+6 zG(%UbZ>SlMQvFxVqfa#_njjk;uUQA|CpA3up^Dn+$;Lg>RcvzybOU)gsZ$Qe4E6{M6 z`w5qmVO2yh37h_`oQ+QrKr^IFQThOUw5ETcMlh|%^P}g>-G?tKk=jWY=$`BvyBP}n z)71wtH-|-zj@>GVy2aZa(4g>R3)0yA@z24j@zdIqGX#t0cacZeE4QYk4v$P@jO!bg zGIe&o^;)lKsSJEZmF6$n@chJ-eaCm;^vh~VKJ9E~!XnlNh7`d49ULYoi z>Gax}kx*ju+uss(&sude<1enKOP+p>jc&^;fZ@l%27gTi;HG};rH5k!e_#Id!-E(~ z8|fdaMsS8psPgG_>KlY=MejZKr7a~M!jcAGDV&Eh#Zw%C=!l+HTl|=DV=l z*Ji#**jND6VsNjF)ZY#2g2{v(K6$47LiO~il8{sAaVT}}AgyV}Nf$1o(Lm>N8P25e zuyns=!}nnM#jC-e#3(_&gaqZ4vt>70yyx1&5*~c6rIgLz)CRMWWI0UIGh~pe%1bB* zoeuquX~%50oj%3!w19?H!~r1mx9_ri?cNgIfh5Nk{N5zksOWM`*q)Czw)mkjMZ-$e z6FZXa-;juV%ZgOdOAz9yzKYN*GFL6BW$EM(wK4~-#Z7jhm4_CB(vo7F7sVfUVe>5m zv42y$lz`coE22Z>@27_a|KRt9izgT}%yq$*Ee@E!C515oN7=q9Wf#6Iq<4_J$xqfL zYn*mj;uA}8F&B{xnJld6zU@6v`uwUqHaWT6C0gVJ^{1JUKp_5npmo;Gu6Iw|xF_Fm z_R- z$%fo+wfcD}ct?pp{fsh1)@u2oPL9Qu?!Dt!Nqa*v#*w*yyLinhxn!2sv;v$mRr zw{A;RAE7Q|+}6jkG}bzj!|z(Q=l3xm`{^~kIkS)S*R@%c_3;*CZQcZ$ zHut;zJCB~LS_q{am+LAr(RozHr2caOKquiVjA9~kYGgc!#AXfMG6bHO^3B#6mXp>) zmTlL{wIU%jee74d%_^S${3I)sM63o%z3%h(ToD87UdBxwI-XQlvY$|M%3;QWcjURL1c1n1gvFXO2(TVfSEk;+W- z7lK`B1g@uX28-BVJ0P%txU!GD^$Q_iXo=~LMUj*XYArjB3n{?-ZvY(!UckG z007sjUf7RxPJF%$Y{fQqDPfhr6WKoRQwNKve&DS9J zqX=Dy$d8bXp;iOar+ zOmJk1@XYHCEq&rP0Dj624Ch-};XjwbFV$#$3}5TKpQ!Wm+Z4%;SDAW!{t`O+RYYUc~8ce2z^IS$)0{ees2?nLO|%^_U+L$r2=m5%(-TrE|tO z#>~4CD5>7D5%b&}#cz8S!Qg+X4$g57r1kaRCvsJElSBZlvs~`(iSMoH_qbF4`aOeC zdB6R)f2ZXEVmy-bU%x{y-o>5T_riyB2C`}UQ!7XyVAN}ZZ>m}ln7NayFB0N051NMk z=3>$%;wCpt;_UzEPBf@v&UV+jsavrwH4oZEzuxNOC~kUoko4wlP;5~|ejriuTxO&P zxNBWs{YKZTU$=?MPZ_%fC%Qhact!_+^i&ara%Kpgu!D?`x$%d*)#^sLZwv)nFf=;xmf^rIx{W;NkJIpU2QRk zAZF_U-oj^>{tU#V1XcO>5WUP^=eEtWD*wC-+zQn_T;mH4oo;^N~^qxFLj} zg5p;zIQ;kQvTppH1K`Grk0H_Rc+g5Zo_K7G~HGI;4fVEd#$Vt3>1)EnJl)-ye?@KA} zZ5Pr)m#s$=>A0&m=1)lzT0T?5lTmmQd6KaT%JrEEq@jOB_ADpM5A8E|+(%QrXl-NX zxX!37HOOxPp1DZMAB7&t3F)VVUUOzi2ULbUFKjYEz&fF9^wsy)62oV z`{sj(uPA`WXBP&IZ)s4vk5L_6f}7juM;e2}zWe)0eb2{(Cr{MVv>#tLBW5+P!Jeep`{n7-0j@zg%L9H@~5zYIADz`1PGq?mYLT%%9E-zIlkn}j!i z7qdx*MKeBq>Q(~d-Vi7i7{%()onw4_R`4Wp#okIi)bSWl*L2=DQ_;W&GCXwHH=L!K z0+X1J+ht!j3z(dR$wfR)GSs*ueKRaKA?nd$=EJk(L`J?bFJGV~cn{ z^nU>2o}=ri_jsS%2~mKuqr1h}QVaVc;&PY&ck_oB%;!Suy?b*(oBmhCnRgYqttYX? zTCBwp2qH8*gpnN6!RV7PD$7TwFTUzFW%6Yxk%`GYUj_v?TcXSp?yF{5zhc14uGnEw zKD|R=;)QxlBUTMfv7dzaCysTc@q7z=o`_fCth`vWYU6Pa$hQA}QqiS;vaM+IrNCHx zg=MxZzO|5Nj_mexqZi#;M`+TA3XXqaNaVJJbldGo;cspXwqUqz3=y&T>SMC8(3XfV zO`;~~B}akN1hh;T@1lQ}D8z45)(P;OBIr9&7R~r2NdkooMa zyG1}b5m14_tha?D>>JF7_4Ct6zE7~I%)8*NX>RStk@VgRrU!J3SlK$uD6k(8^tjO9 z|MN2KPQV^7dz_{TR89i|muTDsA2XvEekFw@c-5G86{{KZp5n4bkLdT#Cf-UJit1PQHR3760iVV3YfGjqF}YN4){5(gb>Dz3@q2Cl*CZx zAOQbK*c-TfsGe-UD){~55(C1d*jnI5`yOdnDR2mD&m6Dva8XfSUUCaM55gh9#E&=Qmm$7d^>Z!AYLq7pQzuzCA)Fa&NAZ63 zfVsxB+pv=^1+ORGt29WnrG%Ks0greQ$-$o4Z(gaH&wNr0@!t`2jD#B|iEZ|%bO`DH+snMuq#L7@i zbJQ`Hv8lL~_ZhTiQ20rS&U@ChTXELNik`oE zb@6Xj{ztc}@lz~QpMkxpiiiCXxP0XFu2Pzb?A<>(1tD2kj1nNo16IS-k6(TL2|nR6 z^KEw%Us%4&#;ai&dYa#=3XjGmK3|&$0{%cP6&A-$`eqiAcV{In~Jy{;yGXS_^eg?sPDI4Z5VhWmIP`gpl ziNp~TkR9`MFW@ffPAyvxL`}sSm3$Q3MaQuFa14!y^+z? zZ~tiRig7l#wrH@9DR~LWk-r+9e0um1OHljM)aWJRx3JfF_q{}T@B94zpHdqxljUcl z-BA89bZ)B#VA`l@mx@3u`P|35s+p~@H#4aR8k~WcOg!m=;;lz2>f)$*xWcR0uGTku z^|nMVEKek^j?sigAMV7+4poYUs%7lbL}&()$iy^ga9|YsD7vL-GM>r4gPeaHniCB1 zxOZvwY+QCt7sEZXXhJ$NQ}3f?z-7UVj=C>nLbPL1`NA=1t+a)kN;Ki;6%tyoj+jvz5;-(yeQ=df8)p zz|~Cx$6D$LVBm+dew^?&qs$pSm4yGgAsJMZ9^B$ceRZSHAw|+mw%QJO2EiZ< zhfbR=#gZY&J{kYy+qNVSseb(alD|+3hz{Lj#zay5=R!en+>iecXnhb>tzkiO2vf-Q^s9phG<(3JT@}1l-JUqXm zlx&V-_abSD@+MoN#!_C0RfY=eZ4}he;V*e_-RxgN7Uv@KidiD4dTT2nfg(b>SiGn| z%arGi$9n%;qB`LeaPa$a_@I?fy;r| z&r^i7z&gkfIu^*+2Og2(u^5^14enQAOGW|@#`pB+MAAmuyJXMkV{{fA%1{@{-Kok?N(&YrA#541N8#ZNPqmn?4Hlw zy(U`kM62Jt?VaSuZWLK?DM@pW<69pYkVT>1NE`x&NxR=fU4(ysSCV6bZo9-?f_H7v z(FDiS&oTNkiCVqoAi_27Vzzrtwgmg53||iK=`j@%>i(EL^(Thc;KQp$un|&X2pp_=&K4AF&;ZDObyc;VgZEN-3%=Nd ztPD8PS3X0R*UDvO-+N>s8Lp346ATr}=$aC5fBJ=-_-oTWQFgYk*#d!D8aUa#au|s<)#^2>xRr1 z5JAkZ6(@Fr$1r6c$lYK)Lu>T;hh_wE9DX--GX)*unD}hTv$;4MRq%KG4ZFasaSG@$BnLPdu`MZt4aZ$EH#(9ruOWa@&~Z;DD{p6yr~yF^_hX9D}f`eUf)HN*Qo zya45RJkRew>g(>n(}?b#MU{6|yy{_j`&$Coly6=3C6wO=v7!dzlo^D%>i~|=NR!-l zKA=vK*^PSnrkdFSzai^a*#y>N37d*2E1M-sqGgd=fY-Te1^R)k7e!zG#Uk9ey)NyJ zT2TegSt~tZyel}wZrtfkVDV>L65v;E^4!px$OQ}rQV)L8 zY6p1X*KFcEGM7OPrA^%+cFyq7bEh_(Vmem1Tc!}^)eEkHQ2|T+54mr3c0F(}QGnSX zm|1a$uRk{nBGRBmk5(-Om1C{MV_#ogS^)P+p&pZ}!jmi*tO(87UJy{YFe?qc9f$?V zSHJPObk0wM2+H|M^)aYb=grh%wo-|g(lO=V6_w`OPMT01g!M~CU;4FbA94CHL6X%{ z$N!Aa1>ZuH-DRYA8rNF_dc%wJpsRyc3InET*|>Yahw`)W89~vOrjf{@$XFvBL^Rv4 ze^H}}MWiH63i#-zG7!$j68xKnz~VV60%KR z6H)_u`!gY(6*w?T?*5NSE+&@If+nfNH}D5n92Q~4`&jZHZo)M{>H71WMRxKy>sY^> zNgl}PsdAG(M)jrtmA0Csgt$6Vx{yu3O8M^Xq|cz4!}6pSvbgPMA6`8AVl$MvO)a@T ztK!yNh$Ab|)K6!@K|q=5=soO)6qy!05s&OV51v=p7G)UMl}m)UD+*67N~1V%vZ)9r z>dO3Lr~17wiE0M2(d7KsP8Jj6yePM|B%9q{-i=-TTMTHV;H0O)p@0X+U6?UH(;p3K zIvE~#NtTLERe!Sb(7wi*s3;53N6K6YU7h~<>oA}i1uAdmm}U3>zW^sB*xL_&B+QjF zfg(AAYgh~cRISJZ5FogdU~GwF_8N7?2OKAo-De$qll} z-@TmWX9}o4+)_JqgN??`K%Ibq0T+TmF`I%|dD!F~v_|kA+%L&K@5U~$*=P@;=YoKV zO-g90Q~(-evTEdo;bO16ZoCKJDYHa?xDx^Zt8ttH@C_AbY4iGoATR^H@~NyDEnmbA zSZEsiPacd2g@(idvFj^|MagH z;s&bGtbZW5-VNB$VeL?9tKJo48w|S29LRm>d<>c)e;O9i5$|tC@N&egNMIVMNWmYH zzl(;f1wRwOl6l~iFLh3+4`@E&SDq7Vo)QGw1BGl2ApvwJq%~x?dw~FK8@OSP0VqOH z6jK2W3kZ2uO&luf3v}vH#|_2^vw1I@oDuJ=;CvR>x@(0d0GJKoq6t1PMr>(PYOH5K z3x{B&UDWl=W*{&T5CQ-o17HOK0}+V2xe|$E^^WBrkxpQ|#-hkD0_+s*6w(^vfKc_8 zE4>w55onEqe0Xk^Fon`a*0|&;v}^moE(jSQ0!Nx;mu@B_9ZwW~W(`TIY&;-HIHAf+ zcj1VF?vU&WsNea#>#OeNEVWDr_^N4=Y4<~5G;>3-do2AfjjO1Xbw&kaW!@=4> zgg81lLQ!yAGxSJsfXYcqUV~BM)A_vD%f$XJ#MBsaF(3wSADAL00K>S}8)rAF0tJNi zDjkb%fIXH?!hlrr=weq2SVoTO1TADiB8KJj2xynhH8}ndU@=G~xWj{C)B~y&>5laz&N549P6F*2D@Xk}ViPwI7bhZ7DPC!OEo9Jc_^KPO~j{{W4d81Rp=f|`%u1p~xT#0Vq;M!*a- z@a>NFI-VOLk>Ssx^HJjj9@o6bM*d*OQG7@%_bwcPVro=JLHB(G00(FU>1SXetbLDx zO+)sBpGE@As_h+&!H&y#=)i++LtpH+gaRC+tfAEb1wR*9OBiW`SaenQ^&UTlTIVi0>$9Sqvu0}{%-#OsT4+Ld~2t6;7jm)QK@Mf16gDM zh%B#UmNK|>JQzdCk+521Yl9)C<=oXArAxz-vG#i50#e5tbV=UwfbhV9-wo zr~oJfWuPA^0-b?HPoPUj7;Fo)^gMD@Vw_~KKk!jftPfd(=%z&C1a^D6ckqfm5CjnN zM{GzJ6leNE06!)WHva&T3pXomfEJ*K!sigg7cK?}!o(G}b^C>^&H=zt z1~ue?XYdXlsP4TAH#hV-TnDDwa7HUa3;TvjXkNbH%|#GF10j|D2vSG@3|m4~X@PQp z+@qnO%yIy&LH0C>*>hRzgO z?e!v@P!+Ohy%uf0)j{~O~*mA8ep^WSc9Yp3_bATFMmiGz({nBX>E3=lx?jBBhJM-4tN=lLI)s_-r6*FG_mtIAX3 z;@DK~dK!l{!cpP%rdt5278wAuAmu4)%W^2L2$N@E2NxS4bl{Z=xIh}64^fxN)2L~X zLV!Y8b=*HN!H-a0O3xe7#sp(r-khNb1B<*bhybhrn@-pWWWfXm(_mersLTMF28YBY zp_P#SPrRgTXocQl_UWI@47A22u+l18a$ELw^s`hd0egDC~n#Aqxvr z)r@~K93W=^kt6^D$N>hyuv_fTi;M#FBM^g~JwS7jS4(wvk-&2qKoE#f>v{~lcwHv8 zs;o(o`q-7LN&o=ReLmurwqi!2Zvp~?FyCW_lOPHR6Ahhi0C8juz_3Y9g4PngTECD; zwha&n0j2Br3@)gVFK`?NP$^ITz8so4mLU$%13B7a=gws!FftG#HFgp#cE>0QAOwIQ zgR;Vj(|{Bn8arAD52@nH#xUc~fPi29$Fk0cf0)%!20#`J>fPchRNsng z50rtq9NhRvaCqP3f71T|uaYWwV%P!|=naRn6!5JFJo}Oh$m@dm_z*a$iJc@t1wqCx zuBmYv?%XDTHS;=RzvG9SQRKs9zw{{Ys~PSE2EvWiggpa~opY8=o-B&ZNZ zTqQu_SvaRC7->boc2T1b0%;H!I*P~ukOxqC{!BduS3nXMARZGj$bCXlnnw*8{Od3| z>$Ct!3=7G?XC^0X?+V5k#t5(j6@fx9L+miI-6Q}A17q$u2m^8sra)wT0H^PSC6Z_| zXiyxd!b6ohGmSOn3ck@vs>>?}={OvD_FmogWi_Y^IIW_jnF1fhg(CTZ4!XD~AS3(S{d8~yk)X;p1cXadTEKz^MTn{c z^Q$EWKhri+b?w){ zD^S3NeseVlei?V31#!s;{5I6o9`*x%OD;sypIeGsQ0^GLmP_N1RKAtWj*a4^N$4%g z5<)-?AX7&MU(AD~uIdd7ja~Cu%xgWQYBVC^#COTj(}VhDlYg(jZR zePnzp%t)NXRw<#RQB*KNbrMC7)evLz&|upT(8vbSMC?t))=r?~>-7%UCsHAkW{nrz zAcEPNAou}x#?1bqGfe^{kU+#R5~!#_t>6(Tk*W@?46Yyu0AM&D-?(qe76Ty3;gU!N zrq;9|2?&zKg~=lG2+Cg_AY_tRVES2tART~7H46d8)z)tX#|VJj#CGDp4#qSheyzzy z1`5ES~N~>`5 zhXu0adKnnM@upD&!pf7urxURi__7|S`~m%hZ7=+HM2HmOz`S1yM5C3k(=?i1?8dej z4u=Va_Sz#L5&!`Z4=8c2@Pi>cUBFu?gZ<+k=W=5^pVTwh zhzJkM{{SQi0=1a~!O8<73>7M|1m#c~7Y&<`6rYj95Nd6pkvnfuv2+MU0wasyxD$#( zJw-4OhcF*fuyZE(g&+ZfbSZSa5f!Q+7(RuVf^-{(0Q&b00s&+REL{_1H+hKizkUf| z0s%*f2T{DULi4SiG_4@AwWKH-=LkWK5BLgD3N2kqnBv)B+8EKFk8kLY55*Ed@h2Ai zuIn7OC>s9fuLOy?B9@(>s0rPVwxkFW&)Jp>JMf#w31~3g_z#!~-)REIdh>*KqrlI^ zgMtIkR>_SZ01!HkR=@*Y1#wOQ1FkTin9LgMXajNZ>-qlR4-Jw&Pwosri8en}1|V4^ zEY}&=FpUxymqa{&9`{0EXt+i>AytJB!6Fa>TFFGTLI7G{#1KtDy=ay`2!%338|$p= z!W4W?kGwD&3}Ilym$f!-!OdZVES!o3OgB$L0F4gBZ~>KAI~|(8a6mf~cCSyB05bG9 zWuM9-8GE|g4QQj*(u5csrc4mgdkqKy5d>EQRSO{!^m*e^;m{C2$ZO)OQrWCFLTlkU zNG<~$LGsWNK%e0i0EP1N+AC4kC=sapSKKPHwom}c4?2DmV1Yct)j}T7t)v!l$oB?6 zvzO->Y3=(!3;j6c6{f9R@c2%pD)j>bcD5hPKx?Bd{{UZ@2SNfufRKp2mHLUlo_hPs zbws6iAQ+;o-lI@r-#@5Qm`FWefY}5Ep_F4&Lv;j;{-0+fluyh469f~}hdiImB!qw? zo?I1*f-0FL4VWTsatr)!Hg{H1DqhM{!z{*y&3Cz+d!}NUY#NT03}~gwNiT!8}og_5Fr3T1Y{k=B12;mR55d% z1A4;OECAH|7y*pym|(a=KsNy1Dh%#y?qdzzeZoKpC9_%qNpWxD0s{;rL{U1pfVjhu z6tYAK97nVS^^*uW0yB`YUO{XDt1N;66axp01AvFPc_PDjxH1AH?3p7tcIj z^FWnNePWXI#_mkm_{tmvCB}_D0l@fF^rOMa{{TY?v+4ei{9tc8@<|M5* zXKN(5U~yR$`9t9Y1(ZewmROLT0%5hBfMAi6f>mlF42GDxI?-H_5g{{9g|~tfCOR}{uJ9~N zFboZVox>*hK)Dr0Yk&ujVLKmKGMgp5x*r&f&9t@>tx(l)K-eGw(uh5wCBM(1DFuKK zBCIEwj0j|dptlRuASw-(nUgymB8_M=zcdb##|Typc`SV)5P!)qK`{Yx8iIk7m^Mlt zg$M~_&`cU}gtStM_^;!}So*!<7?#9Y<$Z}vS0@?Bl<@vB?j(-A`iRocqs~~YDOZ4F z9tr&U$wc)g7x2ggR4bOB;!4^{xAr&#&&`m{JEkrXg9d<459?f05lx={S$H1zfioAB-yRw(81^SOmBQo zxGboE5<3fzxH3hJ$7Pg+?OZ}boDhT)HKulgXj}u1kT3BdWI(Q))Hm_GM2_VW!N&FS zlnvqQsnDOPLF0UUA!k$S1_>sftF#@mSh``#9{&K-5Pvxb@B|wVLwGEvb`rxw z8wdbGhELo8Xozh98$bryn1xpH3dXSwnEXHj6|dkx1<=WYHX40E2GIwNzYu{`AORX0 zN@uNN4-pTz0J`Z-L|CYW*G>=~I&gr+3>bx0znB2J8fYbrfuP|O5dwzqRZDV*O?^*X z_j2=^B|f*Pr{EJ$FF*gp06`G|0RjUA1_lQP1P1^B000020RRya0}vq-A~I1i1VUnR zAW}h+VS+F-fugc;((n``!c+1EKw}j{bCaRL;{VzJ2mt{B0Y3n;AJ==FEr!b>)`wOe zq7EHNQ@zO5V-$_{K(*WXquO|tM@WC$V_g@C;yKmgJV%JI-1l_M3&`FDMoJ=lbXRt zBbvY^m|B3U%%U?Rg_Qb`{)F^cBB=^FFZ<t5kxAG+9jgVA)tP+E$Y%0fPtS*(ESaPoSrLM7PeCpm3nFOY2k!wcy%uf#C8H-4XsNdRuhu+q#$Q31o5gspcCHq7Y>Mk>DXZmT1IpwbR;8-dT*DPe!VDJiSG@aQNu#Q; zP#@c-IeJec!?9AudwP+~_PALFt7>SEM#Lzt%ez)5eXC{Nkz(p+5v$5LjS>r+!s9bb z5~Os6lo4{QQpL6|E-1bBL(a(DtyLDvb!QQMeioI%RiVt0My{136PTs2DN_oXKNCyD zY)}h9&cp!B72Y681l8t9`vHxE!rnWd9K&gQU@@LBJBumLG42$Urum_(gQV^k7h+b`O5 zX^j!eH!hRQgcZD6AqwH$-!MOf!I#Ar^?^2)OyQRgRGOU0ab#FqBBVE{%G1=~R^>nS`bu zDQq756Ti)tosn^|I*?BH4x%TMf@)-Nsp)kSMbP#^(SOAEnxRUW93rcfN3`l!ty47R z;&gZF^gp@!m>N{3Cku#NfC5MYB9fL-8EsWnaf7L(Hv7FweOl~rgdt&cY?*9Dxh`~9 z@`IxGqTdL;<9Dk{nBr9`$%sYK%gx%CqUzJd9WG`gmRGwZv;bGKFaF(K&ZrXMiBt|A z*M)}ZT>k*eBkxl{r6iQ%HSWY+LMG;MObAa7P5yVr)lE zCZs7I7fmD)6ulEJl*H62ni>*CDrsiy_Io~ysr>y(+|q%?lKf=6x_TnFxjyh zZAUa7@m#lb3#L+=;g{_^Q7z*gY3Kg{QP#e#PdbeB{eOE^f=5$@(TfF&N2OvV&X=+V zs}B{P_Z3GNwEDQBtR{7+1#}t6qB=5{N9?>U*(>0oRa%LghFux7olk0gYqhweidi2~ z4({tz&`@TZON5Y6+50H>UfIhj3O;oJ;LW#I^5@1h))ol z<*m+I+~uvzPAl4X$4H!<#c%(_074M}0RjU92nPlP1O@{D000020RR#a10o?1QWG*l zF$7|AQIcVTAfiDdvJ`>B1@iDSaX?ej24j)pFhfvtgOmT-00;pB0RcY%{{Wyz^2IOM zlm7sAc+bN>4BX#GW)^O;*9p))As3pYS``QX0A-e2xele-Luh)!^J3vni8wo42=jfe z2b+1efZ%zzn|ZbAdA9?Bz~OMXTnpfxu?=F;$?s(Mo>n8;>|iw%G)$gwHU9wmQ+c7Q zcofNXhg<&uAmwp2MMYGd>5c9O1A)n0)y>}LjrUngeP0@GTlhi|og$#Z(1ARzkX> z=Y--S{uFk#k|xRX!V7y z$u(Ic&IVBRoMY&-cksUc65=kgG#(eISASI z6tss#Z42H$_xEk;g-zPI2~(?PpysKGLL?=mBa|#cB9jnA5lPNp>i(ucEBJU}WkM3V z`!N$8<8w{U5BXt)h7!(aGNQ?JR3g>U$#NbUI0qzJfL^L1tq~BeO<0<<0fd$ps4Ool zR$WmMH9^_U6U~BZi$p}&lJKKMeJ^e@k|K0r>#^N3RNED&56F!CgmQGD zWJ@{Of-NgiI*2BMu#Z)O%ynHUaNaD@1r&uZOGG-P(OR**%dkX!;%bv{qeW(siivDi zG|*)zuGNXEsv^qu$zZ)XE<*EfHq|giOgeCvV^XU$OHzkRRn@IhnhOIZ0aaVnUr%le ztIhP5CZ5a96B=r2As1Jbg%YNHD5H{DPH3t7z1j#ZV=0WdVPilzno&%ulZr3YBD6fuSeRK-1E&53`0LhRvpnIpCMcud7|7`PIZW z4|R%Qzo>tmVq-$0-l9-t5ZP%=GQ6$?U4^pMt1PJ)%3@dA$`Tx*A+qG`lJn(tpEIUvk&=kSMP?z2 z5z@02n@*I}`ppq|nIfQ(L#j+G9EQ;jwv#pXLPj*kp%hk1nENsvA{e!vX)c{wa>}*t z!xxq2llheRbgg+_YUETZYr_;IJ!nU&>H#9bqE5J&1X^MGYK0l3%a~bHG`y2q9U*l6Ia;Kd=)K+>Q%!7YDIh9>O3O#();snk_XbQFWn-?+BZ@kSR@2p|jnG ztrMV!rwKy~N|f@X>eLu2Ae8cWoD7F}Q;Jt1S+%S9T&d-=+AtK-)J-C5QBf5LbBPQ( zu?|TIYQkO8(I>yrBpL@0kkpD8cz+XB%pf4^3`G<8gUKH=q-Rzw9WE#BKf`|8{3r1h zCn*n^)2mR-MNm-{)-{N!`XM?O$(GknI;E4%Wr3koP?VJ-^178qlA2`r*v$;-EP8#5w8@?Y39Z*ZYx@&tkpYa_eDggv-KQy;i%UcwR;@! zsED+c7to^mUD!*7_g{Ap&Wrs>-e=2!1aPTeAuh2CTO_GF(avsL9G%eUmo#5XrFkIA zaY8P=DwK#~URX<3FQuoWRJkxzVftO%C4`;+o(;Y;8fid^D^QU|oEXE!Vyy}+&VHHn=GfhI0ppSj-p#GW}8xJvD2+erB7!}X|8S^TUNMoT{DMm zrmOf}SrtMg$}f8gd&nrHYYBN;?-Y|-e62T_l4(k!rjL8wVNz%&i7C2Q(>#8DAD@LT z^?x>>yHOGeZJQcm6NMzzKhFf%jFwdidI~QysIid}q?K)CxQJnr${ihF#KV1(Bttdf z{{T~|yp=(a*`AhBH5>XBTI`dCZk05srF^9AB^=CFd2MM#>7=QTVEs;9GN?y1*ebv$6xLE0xwu$@B_Tygj3Q8xS&Nn3 zE0SIm!{+DPjmsxz3!U8#=QL + +const u32 cim_verb_data[] = { + /* --- Codec #0 --- */ + 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269VC */ + 0x17aa21fa, /* Subsystem ID */ + 19, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x17aa21fa), + + /* Ext. Microphone Connector: External,Right; MicIn,3.5mm; Black,JD; DA,Seq */ + AZALIA_PIN_CFG(0, 0x0a, 0x04a11020), + + /* Headphones Connector: External,Right; HP,3.5mm; Black,JD; DA,Seq */ + AZALIA_PIN_CFG(0, 0x0b, 0x0421101f), + + /* Not connected: N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq */ + AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0), + + /* Internal Speakers Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq */ + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + + /* Not connected */ + AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0), + + /* Internal Microphone: Fixed,Int,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq */ + AZALIA_PIN_CFG(0, 0x11, 0xd5a30140), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x03211020), + AZALIA_PIN_CFG(0, 0x18, 0x03a11830), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40138205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* Misc entries */ + 0x01970804, + 0x01870803, + 0x01470740, + 0x00970640, + + 0x00370680, + 0x00270680, + 0x01470c02, + 0x01570c02, + + /* ALC coefficients. */ + /* 08 */ + 0x02050008, + 0x02040700, + /* 18 */ + 0x02050018, + 0x02045184, + /* 1c */ + 0x0205001c, + 0x02042800, + + 0x01870724, /* Enable Vrefout for mic */ + 0x00170500, /* Set power state to D0 */ + + /* --- Codec #3 --- */ + 0x80862806, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[] = { + 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/x230/variants/x230/board_info.txt b/src/mainboard/lenovo/x230/variants/x230/board_info.txt deleted file mode 100644 index 22281e6aa8..0000000000 --- a/src/mainboard/lenovo/x230/variants/x230/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: laptop -Board name: ThinkPad X230 -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: n -Release year: 2012 diff --git a/src/mainboard/lenovo/x230/variants/x230/hda_verb.c b/src/mainboard/lenovo/x230/variants/x230/hda_verb.c deleted file mode 100644 index 05fb3fd775..0000000000 --- a/src/mainboard/lenovo/x230/variants/x230/hda_verb.c +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Bits 31:28 - Codec Address */ -/* Bits 27:20 - NID */ -/* Bits 19:8 - Verb ID */ -/* Bits 7:0 - Payload */ - -#include - -const u32 cim_verb_data[] = { - /* --- Codec #0 --- */ - 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269VC */ - 0x17aa21fa, /* Subsystem ID */ - 19, /* Number of 4 dword sets */ - AZALIA_SUBVENDOR(0, 0x17aa21fa), - - /* Ext. Microphone Connector: External,Right; MicIn,3.5mm; Black,JD; DA,Seq */ - AZALIA_PIN_CFG(0, 0x0a, 0x04a11020), - - /* Headphones Connector: External,Right; HP,3.5mm; Black,JD; DA,Seq */ - AZALIA_PIN_CFG(0, 0x0b, 0x0421101f), - - /* Not connected: N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq */ - AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0), - - /* Internal Speakers Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq */ - AZALIA_PIN_CFG(0, 0x0d, 0x90170110), - - /* Not connected */ - AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0), - - /* Internal Microphone: Fixed,Int,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq */ - AZALIA_PIN_CFG(0, 0x11, 0xd5a30140), - AZALIA_PIN_CFG(0, 0x12, 0x90a60140), - AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x15, 0x03211020), - AZALIA_PIN_CFG(0, 0x18, 0x03a11830), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1d, 0x40138205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), - - /* Misc entries */ - 0x01970804, - 0x01870803, - 0x01470740, - 0x00970640, - - 0x00370680, - 0x00270680, - 0x01470c02, - 0x01570c02, - - /* ALC coefficients. */ - /* 08 */ - 0x02050008, - 0x02040700, - /* 18 */ - 0x02050018, - 0x02045184, - /* 1c */ - 0x0205001c, - 0x02042800, - - 0x01870724, /* Enable Vrefout for mic */ - 0x00170500, /* Set power state to D0 */ - - /* --- Codec #3 --- */ - 0x80862806, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - AZALIA_SUBVENDOR(3, 0x80860101), - AZALIA_PIN_CFG(3, 0x05, 0x18560010), - AZALIA_PIN_CFG(3, 0x06, 0x18560020), - AZALIA_PIN_CFG(3, 0x07, 0x18560030), -}; - -const u32 pc_beep_verbs[] = { - 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ -}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/x230/variants/x230/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb deleted file mode 100644 index 8f1a97d9dd..0000000000 --- a/src/mainboard/lenovo/x230/variants/x230/overridetree.cb +++ /dev/null @@ -1,15 +0,0 @@ -chip northbridge/intel/sandybridge - device domain 0x0 on - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "docking_supported" = "1" - device pci 1c.2 on - smbios_slot_desc "7" "3" "ExpressCard Slot" "8" - end # PCIe Port #3 (expresscard) - device pci 1f.0 on # LPC bridge - chip ec/lenovo/h8 - register "eventa_enable" = "0x01" - end - end # LPC Controller - end - end -end diff --git a/src/mainboard/lenovo/x230/variants/x230s/board_info.txt b/src/mainboard/lenovo/x230/variants/x230s/board_info.txt deleted file mode 100644 index 67b229455a..0000000000 --- a/src/mainboard/lenovo/x230/variants/x230s/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: laptop -Board name: ThinkPad X230s -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: n -Release year: 2013 diff --git a/src/mainboard/lenovo/x230/variants/x230s/data.vbt b/src/mainboard/lenovo/x230/variants/x230s/data.vbt deleted file mode 100644 index 42b0394daa90ec9b812d11b61284b91e8f09ef73..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 4280 zcmdT`U2GIp6h3!mc4u~WW_LO*uq?E>AmA1$oi4RPt#P{ju?zj#{!kY}q=j9OSfG@j zKtg2HiX|Gdi3U-T?3;x6P-8-TQHc-Os3F7$G(;j29}GUo14d(z_1u}+rM6f$5+dH& zZ_c@A&i&@zbMHB`i~3`Iw6`->9q*4-b#%qz?JYC~27IJ_kN4><7Vqla*xcCHxG~n= z)wG7b2eV;JyLAm9MM#+%t$B1se8-;jP^71l_73hy9oRIoEwwdW9pC3_G|?2Njhi>8 zhtea1d(tV|+y7J}Wwfds+q-QjMLYLy-;^Gyr;KZ3&$_`KIE2>JE?-egsj;fsc&s{V z)I?FQtzWUKenp)sH@7r(btK~LjeYU1PTJK&o8!HWy}d0RvG#Q|(bLrykH!01npL@J z=kS4%ZCjt+LnBR`;3d&;zF=g9DK+Bh^sdzjB|+LPX$9@&>pEmvh#1~|)0 z0!D;*K;%v0`!fp7g6S1F9|4(@6hYz%=OKbh1V7)GC+}Dz%xC2AoPb zBv~NAx&3Z*DM0oz((|m(nLtqh2yk%#G>x1oV}|Ty5x~RjqDClTirvs*!gk0Tm?V@d zbkX6`9USa;6`a6*=On{al}RDyo`7g@xCO(8N^w{7l>~VKOlZa{E85LGL#_ZAr>R55vveQhz`Wl zh(W}2h`oqIh$D#C5$__rd*Nn|vjDddn?+n%;z-a0I9dtT3Drv^U73)yuBdr-9agZ)mV^tsbRDNEOA^|3-HS;Di6Q$69FHPh2Hh> zytfL1uL2(R`__DR0W6wc8wCwmeK7$f47~+Jz*PW|fS5q>hlz-f1dvciBLx$69AYwm zfq)=^VA{h8O9tl=B_N?E{v_sa+Jx+p!%W#z3XC5gAx{ayZMwo}3aykvkSp}=sFa-q zZ`gSvHr&wzjsNA7*=umwyj{hl!rF|{06=?dVq;=(M|!ApaC^GQ&YU(#%>}a&mKdS2 zI%mBhV<{Z(2E#OlOC3wasp|b#y2DG%0(FOYC*DfkArIJ* zMvY|bd_&F4P6L24Hv)6v54`3=hOo_J*92~#b1lR3kk`V&#`!3DYRbE+ZDNAp$8THs3IR%=qHMPL6I*h6jWVT<@qX&sd}F(Kcmu7RX?W6S(Tns z^>0=As!FAR9uCNh0(5mi-w=?u1n6r4{bWEs6``jvouEkL!PzAz{+3#v=63l?{U zSS5JW@jyu<3Lc6ir`Yla(NKDV594=tdL;1-Ivb-D_ z#tWO$?*ZOnFlLy;Sb6`|1k5&;%&vp7cQk+y%MB+F@NcES7#e0=#q=a(IpyTfeowe4 zhW)fVteILNjae?*C0!|wVS3s#2Cp3l(>q?o9Hy5ERt4 -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 3, 0 }, - { 1, 3, 1 }, - { 0, 1, 3 }, - { 1, 3, -1 }, - { 0, 1, 2 }, - { 0, 1, -1 }, - { 0, 1, -1 }, - { 0, 1, -1 }, - { 0, 1, -1 }, - { 0, 1, 5 }, - { 1, 1, -1 }, - { 0, 1, -1 }, - { 1, 3, -1 }, - { 1, 1, -1 }, -}; - -void bootblock_mainboard_early_init(void) -{ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); -} - -/* FIXME: Put proper SPD map here. */ -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x52, id_only); - read_spd(&spd[2], 0x51, id_only); - read_spd(&spd[3], 0x53, id_only); -} diff --git a/src/mainboard/lenovo/x230/variants/x230s/gma-mainboard.ads b/src/mainboard/lenovo/x230/variants/x230s/gma-mainboard.ads deleted file mode 100644 index fb75293b81..0000000000 --- a/src/mainboard/lenovo/x230/variants/x230s/gma-mainboard.ads +++ /dev/null @@ -1,22 +0,0 @@ --- SPDX-License-Identifier: GPL-2.0-or-later - -with HW.GFX.GMA; -with HW.GFX.GMA.Display_Probing; - -use HW.GFX.GMA; -use HW.GFX.GMA.Display_Probing; - -private package GMA.Mainboard is - - ports : constant Port_List := - (DP1, - DP2, - DP3, - HDMI1, - HDMI2, - HDMI3, - Analog, - EDP, - others => Disabled); - -end GMA.Mainboard; diff --git a/src/mainboard/lenovo/x230/variants/x230s/gpio.c b/src/mainboard/lenovo/x230/variants/x230s/gpio.c deleted file mode 100644 index a216c6bab0..0000000000 --- a/src/mainboard/lenovo/x230/variants/x230s/gpio.c +++ /dev/null @@ -1,212 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -static const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, - .gpio1 = GPIO_MODE_GPIO, - .gpio2 = GPIO_MODE_GPIO, - .gpio3 = GPIO_MODE_GPIO, - .gpio4 = GPIO_MODE_GPIO, - .gpio5 = GPIO_MODE_GPIO, - .gpio6 = GPIO_MODE_GPIO, - .gpio7 = GPIO_MODE_GPIO, - .gpio8 = GPIO_MODE_GPIO, - .gpio9 = GPIO_MODE_NATIVE, - .gpio10 = GPIO_MODE_GPIO, - .gpio11 = GPIO_MODE_NATIVE, - .gpio12 = GPIO_MODE_NATIVE, - .gpio13 = GPIO_MODE_GPIO, - .gpio14 = GPIO_MODE_NATIVE, - .gpio15 = GPIO_MODE_GPIO, - .gpio16 = GPIO_MODE_GPIO, - .gpio17 = GPIO_MODE_GPIO, - .gpio18 = GPIO_MODE_NATIVE, - .gpio19 = GPIO_MODE_GPIO, - .gpio20 = GPIO_MODE_NATIVE, - .gpio21 = GPIO_MODE_GPIO, - .gpio22 = GPIO_MODE_GPIO, - .gpio23 = GPIO_MODE_NATIVE, - .gpio24 = GPIO_MODE_GPIO, - .gpio25 = GPIO_MODE_NATIVE, - .gpio26 = GPIO_MODE_GPIO, - .gpio27 = GPIO_MODE_GPIO, - .gpio28 = GPIO_MODE_GPIO, - .gpio29 = GPIO_MODE_GPIO, - .gpio30 = GPIO_MODE_NATIVE, - .gpio31 = GPIO_MODE_NATIVE, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_INPUT, - .gpio1 = GPIO_DIR_INPUT, - .gpio2 = GPIO_DIR_INPUT, - .gpio3 = GPIO_DIR_INPUT, - .gpio4 = GPIO_DIR_INPUT, - .gpio5 = GPIO_DIR_INPUT, - .gpio6 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_OUTPUT, - .gpio10 = GPIO_DIR_OUTPUT, - .gpio13 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_OUTPUT, - .gpio16 = GPIO_DIR_INPUT, - .gpio17 = GPIO_DIR_INPUT, - .gpio19 = GPIO_DIR_INPUT, - .gpio21 = GPIO_DIR_INPUT, - .gpio22 = GPIO_DIR_OUTPUT, - .gpio24 = GPIO_DIR_OUTPUT, - .gpio26 = GPIO_DIR_INPUT, - .gpio27 = GPIO_DIR_INPUT, - .gpio28 = GPIO_DIR_OUTPUT, - .gpio29 = GPIO_DIR_OUTPUT, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio8 = GPIO_LEVEL_LOW, - .gpio10 = GPIO_LEVEL_HIGH, - .gpio15 = GPIO_LEVEL_LOW, - .gpio22 = GPIO_LEVEL_HIGH, - .gpio24 = GPIO_LEVEL_LOW, - .gpio28 = GPIO_LEVEL_LOW, - .gpio29 = GPIO_LEVEL_HIGH, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_reset = { - .gpio24 = GPIO_RESET_RSMRST, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio1 = GPIO_INVERT, - .gpio6 = GPIO_INVERT, - .gpio13 = GPIO_INVERT, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_blink = { -}; - -static const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_NATIVE, - .gpio33 = GPIO_MODE_GPIO, - .gpio34 = GPIO_MODE_GPIO, - .gpio35 = GPIO_MODE_GPIO, - .gpio36 = GPIO_MODE_GPIO, - .gpio37 = GPIO_MODE_GPIO, - .gpio38 = GPIO_MODE_GPIO, - .gpio39 = GPIO_MODE_GPIO, - .gpio40 = GPIO_MODE_NATIVE, - .gpio41 = GPIO_MODE_NATIVE, - .gpio42 = GPIO_MODE_NATIVE, - .gpio43 = GPIO_MODE_GPIO, - .gpio44 = GPIO_MODE_GPIO, - .gpio45 = GPIO_MODE_GPIO, - .gpio46 = GPIO_MODE_NATIVE, - .gpio47 = GPIO_MODE_GPIO, - .gpio48 = GPIO_MODE_GPIO, - .gpio49 = GPIO_MODE_GPIO, - .gpio50 = GPIO_MODE_GPIO, - .gpio51 = GPIO_MODE_GPIO, - .gpio52 = GPIO_MODE_GPIO, - .gpio53 = GPIO_MODE_GPIO, - .gpio54 = GPIO_MODE_GPIO, - .gpio55 = GPIO_MODE_GPIO, - .gpio56 = GPIO_MODE_GPIO, - .gpio57 = GPIO_MODE_GPIO, - .gpio58 = GPIO_MODE_NATIVE, - .gpio59 = GPIO_MODE_NATIVE, - .gpio60 = GPIO_MODE_NATIVE, - .gpio61 = GPIO_MODE_NATIVE, - .gpio62 = GPIO_MODE_NATIVE, - .gpio63 = GPIO_MODE_NATIVE, -}; - -static const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio33 = GPIO_DIR_OUTPUT, - .gpio34 = GPIO_DIR_INPUT, - .gpio35 = GPIO_DIR_INPUT, - .gpio36 = GPIO_DIR_INPUT, - .gpio37 = GPIO_DIR_INPUT, - .gpio38 = GPIO_DIR_INPUT, - .gpio39 = GPIO_DIR_INPUT, - .gpio43 = GPIO_DIR_OUTPUT, - .gpio44 = GPIO_DIR_INPUT, - .gpio45 = GPIO_DIR_INPUT, - .gpio47 = GPIO_DIR_INPUT, - .gpio48 = GPIO_DIR_INPUT, - .gpio49 = GPIO_DIR_INPUT, - .gpio50 = GPIO_DIR_INPUT, - .gpio51 = GPIO_DIR_OUTPUT, - .gpio52 = GPIO_DIR_OUTPUT, - .gpio53 = GPIO_DIR_OUTPUT, - .gpio54 = GPIO_DIR_INPUT, - .gpio55 = GPIO_DIR_OUTPUT, - .gpio56 = GPIO_DIR_INPUT, - .gpio57 = GPIO_DIR_INPUT, -}; - -static const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio33 = GPIO_LEVEL_HIGH, - .gpio43 = GPIO_LEVEL_HIGH, - .gpio51 = GPIO_LEVEL_HIGH, - .gpio52 = GPIO_LEVEL_HIGH, - .gpio53 = GPIO_LEVEL_HIGH, - .gpio55 = GPIO_LEVEL_HIGH, -}; - -static const struct pch_gpio_set2 pch_gpio_set2_reset = { -}; - -static const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_GPIO, - .gpio65 = GPIO_MODE_GPIO, - .gpio66 = GPIO_MODE_GPIO, - .gpio67 = GPIO_MODE_GPIO, - .gpio68 = GPIO_MODE_GPIO, - .gpio69 = GPIO_MODE_GPIO, - .gpio70 = GPIO_MODE_GPIO, - .gpio71 = GPIO_MODE_GPIO, - .gpio72 = GPIO_MODE_NATIVE, - .gpio73 = GPIO_MODE_NATIVE, - .gpio74 = GPIO_MODE_NATIVE, - .gpio75 = GPIO_MODE_NATIVE, -}; - -static const struct pch_gpio_set3 pch_gpio_set3_direction = { - .gpio64 = GPIO_DIR_INPUT, - .gpio65 = GPIO_DIR_INPUT, - .gpio66 = GPIO_DIR_INPUT, - .gpio67 = GPIO_DIR_INPUT, - .gpio68 = GPIO_DIR_INPUT, - .gpio69 = GPIO_DIR_INPUT, - .gpio70 = GPIO_DIR_INPUT, - .gpio71 = GPIO_DIR_INPUT, -}; - -static const struct pch_gpio_set3 pch_gpio_set3_level = { -}; - -static const struct pch_gpio_set3 pch_gpio_set3_reset = { -}; - -const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .blink = &pch_gpio_set1_blink, - .invert = &pch_gpio_set1_invert, - .reset = &pch_gpio_set1_reset, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - .reset = &pch_gpio_set2_reset, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - .reset = &pch_gpio_set3_reset, - }, -}; diff --git a/src/mainboard/lenovo/x230/variants/x230s/hda_verb.c b/src/mainboard/lenovo/x230/variants/x230s/hda_verb.c deleted file mode 100644 index 77919041e5..0000000000 --- a/src/mainboard/lenovo/x230/variants/x230s/hda_verb.c +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -const u32 cim_verb_data[] = { - 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ - 0x17aa2209, /* Subsystem ID */ - 11, /* Number of 4 dword sets */ - AZALIA_SUBVENDOR(0, 0x17aa2209), - AZALIA_PIN_CFG(0, 0x12, 0x90a60140), - AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x15, 0x03211020), - AZALIA_PIN_CFG(0, 0x17, 0x40008000), - AZALIA_PIN_CFG(0, 0x18, 0x03a11030), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1d, 0x40f38205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), - - 0x80862806, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - AZALIA_SUBVENDOR(3, 0x80860101), - AZALIA_PIN_CFG(3, 0x05, 0x18560010), - AZALIA_PIN_CFG(3, 0x06, 0x58560020), - AZALIA_PIN_CFG(3, 0x07, 0x58560030), - -}; - -const u32 pc_beep_verbs[0] = {}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb deleted file mode 100644 index ed1dd3c3b4..0000000000 --- a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb +++ /dev/null @@ -1,36 +0,0 @@ -chip northbridge/intel/sandybridge - # Enable DisplayPort Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "4" - register "gpu_dp_c_hotplug" = "4" - register "gpu_dp_d_hotplug" = "4" - - # Enable Panel as eDP and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_backlight_off_delay" = "1" # 0.1ms - register "gpu_panel_power_backlight_on_delay" = "1" # 0.1ms - register "gpu_panel_power_down_delay" = "500" # 50ms - register "gpu_panel_power_up_delay" = "2000" # 200ms - - device domain 0x0 on - subsystemid 0x17aa 0x2209 inherit - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" - # X230s does not support docking - register "docking_supported" = "0" - register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - # Enable SATA ports 0 (HDD bay) & 1 (WWAN M.2 SATA) - register "sata_port_map" = "0x3" - - device pci 1f.0 on # LPC bridge - chip ec/lenovo/h8 # - register "config1" = "0x05" - register "config3" = "0xc4" - register "event5_enable" = "0x3c" - register "evente_enable" = "0x1d" - # X230s only has BT on wlan card - register "has_bdc_detection" = "0" - end - end # LPC Controller - end - end -end From ebf1932f23dcacf995064cf1c790568b6914f99a Mon Sep 17 00:00:00 2001 From: Bill XIE Date: Mon, 18 May 2020 21:22:50 +0800 Subject: [PATCH 194/405] mb/lenovo/x230: Turn X230 into a variant Other variants would be added later. Change-Id: Ic6af14f0aa7a6f7378048f3c38d5713c18950366 Signed-off-by: Bill XIE Reviewed-on: https://review.coreboot.org/c/coreboot/+/41509 Reviewed-by: Alexander Couzens Reviewed-by: Nico Huber Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/x230/Kconfig | 8 ++ src/mainboard/lenovo/x230/Makefile.inc | 12 +-- src/mainboard/lenovo/x230/board_info.txt | 1 + src/mainboard/lenovo/x230/devicetree.cb | 7 +- src/mainboard/lenovo/x230/hda_verb.c | 83 +----------------- .../lenovo/x230/variants/x230/board_info.txt | 7 ++ .../lenovo/x230/{ => variants/x230}/data.vbt | Bin .../x230/{ => variants/x230}/early_init.c | 0 .../{ => variants/x230}/gma-mainboard.ads | 0 .../lenovo/x230/{ => variants/x230}/gpio.c | 0 .../lenovo/x230/variants/x230/hda_verb.c | 82 +++++++++++++++++ .../lenovo/x230/variants/x230/overridetree.cb | 15 ++++ 12 files changed, 121 insertions(+), 94 deletions(-) create mode 100644 src/mainboard/lenovo/x230/variants/x230/board_info.txt rename src/mainboard/lenovo/x230/{ => variants/x230}/data.vbt (100%) rename src/mainboard/lenovo/x230/{ => variants/x230}/early_init.c (100%) rename src/mainboard/lenovo/x230/{ => variants/x230}/gma-mainboard.ads (100%) rename src/mainboard/lenovo/x230/{ => variants/x230}/gpio.c (100%) create mode 100644 src/mainboard/lenovo/x230/variants/x230/hda_verb.c create mode 100644 src/mainboard/lenovo/x230/variants/x230/overridetree.cb diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 7d563efb2b..37b264dab2 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -50,11 +50,19 @@ config MAINBOARD_DIR string default "lenovo/x230" +config VARIANT_DIR + string + default "x230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T + config MAINBOARD_PART_NUMBER string default "ThinkPad X230" if BOARD_LENOVO_X230 default "ThinkPad X230t" if BOARD_LENOVO_X230T +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc index 991eadbff2..5316d24d88 100644 --- a/src/mainboard/lenovo/x230/Makefile.inc +++ b/src/mainboard/lenovo/x230/Makefile.inc @@ -1,9 +1,9 @@ ## SPDX-License-Identifier: GPL-2.0-only smm-y += smihandler.c -bootblock-y += gpio.c -romstage-y += gpio.c - -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -bootblock-y += early_init.c -romstage-y += early_init.c +bootblock-y += variants/$(VARIANT_DIR)/early_init.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c +romstage-y += variants/$(VARIANT_DIR)/early_init.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads diff --git a/src/mainboard/lenovo/x230/board_info.txt b/src/mainboard/lenovo/x230/board_info.txt index 09ddde1f85..505c59a58b 100644 --- a/src/mainboard/lenovo/x230/board_info.txt +++ b/src/mainboard/lenovo/x230/board_info.txt @@ -1,4 +1,5 @@ Category: laptop +Board name: ThinkPad X230 baseboard ROM package: SOIC-8 ROM protocol: SPI ROM socketed: n diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index e34734c4c3..3a8e5fe852 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -58,8 +58,6 @@ chip northbridge/intel/sandybridge register "gen2_dec" = "0x0c15e1" register "gen4_dec" = "0x0c06a1" - register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" - register "xhci_switchable_ports" = "0xf" register "superspeed_capable_ports" = "0xf" register "xhci_overcurrent_mapping" = "0x4000201" @@ -89,9 +87,7 @@ chip northbridge/intel/sandybridge end end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on - smbios_slot_desc "7" "3" "ExpressCard Slot" "8" - end # PCIe Port #3 (expresscard) + device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 @@ -136,7 +132,6 @@ chip northbridge/intel/sandybridge register "event7_enable" = "0x01" register "event8_enable" = "0x7b" register "event9_enable" = "0xff" - register "eventa_enable" = "0x01" register "eventb_enable" = "0x00" register "eventc_enable" = "0xff" register "eventd_enable" = "0xff" diff --git a/src/mainboard/lenovo/x230/hda_verb.c b/src/mainboard/lenovo/x230/hda_verb.c index 05fb3fd775..2997587d82 100644 --- a/src/mainboard/lenovo/x230/hda_verb.c +++ b/src/mainboard/lenovo/x230/hda_verb.c @@ -1,82 +1 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Bits 31:28 - Codec Address */ -/* Bits 27:20 - NID */ -/* Bits 19:8 - Verb ID */ -/* Bits 7:0 - Payload */ - -#include - -const u32 cim_verb_data[] = { - /* --- Codec #0 --- */ - 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269VC */ - 0x17aa21fa, /* Subsystem ID */ - 19, /* Number of 4 dword sets */ - AZALIA_SUBVENDOR(0, 0x17aa21fa), - - /* Ext. Microphone Connector: External,Right; MicIn,3.5mm; Black,JD; DA,Seq */ - AZALIA_PIN_CFG(0, 0x0a, 0x04a11020), - - /* Headphones Connector: External,Right; HP,3.5mm; Black,JD; DA,Seq */ - AZALIA_PIN_CFG(0, 0x0b, 0x0421101f), - - /* Not connected: N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq */ - AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0), - - /* Internal Speakers Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq */ - AZALIA_PIN_CFG(0, 0x0d, 0x90170110), - - /* Not connected */ - AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0), - - /* Internal Microphone: Fixed,Int,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq */ - AZALIA_PIN_CFG(0, 0x11, 0xd5a30140), - AZALIA_PIN_CFG(0, 0x12, 0x90a60140), - AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x15, 0x03211020), - AZALIA_PIN_CFG(0, 0x18, 0x03a11830), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1d, 0x40138205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), - - /* Misc entries */ - 0x01970804, - 0x01870803, - 0x01470740, - 0x00970640, - - 0x00370680, - 0x00270680, - 0x01470c02, - 0x01570c02, - - /* ALC coefficients. */ - /* 08 */ - 0x02050008, - 0x02040700, - /* 18 */ - 0x02050018, - 0x02045184, - /* 1c */ - 0x0205001c, - 0x02042800, - - 0x01870724, /* Enable Vrefout for mic */ - 0x00170500, /* Set power state to D0 */ - - /* --- Codec #3 --- */ - 0x80862806, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - AZALIA_SUBVENDOR(3, 0x80860101), - AZALIA_PIN_CFG(3, 0x05, 0x18560010), - AZALIA_PIN_CFG(3, 0x06, 0x18560020), - AZALIA_PIN_CFG(3, 0x07, 0x18560030), -}; - -const u32 pc_beep_verbs[] = { - 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ -}; - -AZALIA_ARRAY_SIZES; +/* dummy */ diff --git a/src/mainboard/lenovo/x230/variants/x230/board_info.txt b/src/mainboard/lenovo/x230/variants/x230/board_info.txt new file mode 100644 index 0000000000..22281e6aa8 --- /dev/null +++ b/src/mainboard/lenovo/x230/variants/x230/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board name: ThinkPad X230 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2012 diff --git a/src/mainboard/lenovo/x230/data.vbt b/src/mainboard/lenovo/x230/variants/x230/data.vbt similarity index 100% rename from src/mainboard/lenovo/x230/data.vbt rename to src/mainboard/lenovo/x230/variants/x230/data.vbt diff --git a/src/mainboard/lenovo/x230/early_init.c b/src/mainboard/lenovo/x230/variants/x230/early_init.c similarity index 100% rename from src/mainboard/lenovo/x230/early_init.c rename to src/mainboard/lenovo/x230/variants/x230/early_init.c diff --git a/src/mainboard/lenovo/x230/gma-mainboard.ads b/src/mainboard/lenovo/x230/variants/x230/gma-mainboard.ads similarity index 100% rename from src/mainboard/lenovo/x230/gma-mainboard.ads rename to src/mainboard/lenovo/x230/variants/x230/gma-mainboard.ads diff --git a/src/mainboard/lenovo/x230/gpio.c b/src/mainboard/lenovo/x230/variants/x230/gpio.c similarity index 100% rename from src/mainboard/lenovo/x230/gpio.c rename to src/mainboard/lenovo/x230/variants/x230/gpio.c diff --git a/src/mainboard/lenovo/x230/variants/x230/hda_verb.c b/src/mainboard/lenovo/x230/variants/x230/hda_verb.c new file mode 100644 index 0000000000..05fb3fd775 --- /dev/null +++ b/src/mainboard/lenovo/x230/variants/x230/hda_verb.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Bits 31:28 - Codec Address */ +/* Bits 27:20 - NID */ +/* Bits 19:8 - Verb ID */ +/* Bits 7:0 - Payload */ + +#include + +const u32 cim_verb_data[] = { + /* --- Codec #0 --- */ + 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269VC */ + 0x17aa21fa, /* Subsystem ID */ + 19, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x17aa21fa), + + /* Ext. Microphone Connector: External,Right; MicIn,3.5mm; Black,JD; DA,Seq */ + AZALIA_PIN_CFG(0, 0x0a, 0x04a11020), + + /* Headphones Connector: External,Right; HP,3.5mm; Black,JD; DA,Seq */ + AZALIA_PIN_CFG(0, 0x0b, 0x0421101f), + + /* Not connected: N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq */ + AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0), + + /* Internal Speakers Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq */ + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + + /* Not connected */ + AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0), + + /* Internal Microphone: Fixed,Int,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq */ + AZALIA_PIN_CFG(0, 0x11, 0xd5a30140), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x03211020), + AZALIA_PIN_CFG(0, 0x18, 0x03a11830), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40138205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* Misc entries */ + 0x01970804, + 0x01870803, + 0x01470740, + 0x00970640, + + 0x00370680, + 0x00270680, + 0x01470c02, + 0x01570c02, + + /* ALC coefficients. */ + /* 08 */ + 0x02050008, + 0x02040700, + /* 18 */ + 0x02050018, + 0x02045184, + /* 1c */ + 0x0205001c, + 0x02042800, + + 0x01870724, /* Enable Vrefout for mic */ + 0x00170500, /* Set power state to D0 */ + + /* --- Codec #3 --- */ + 0x80862806, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[] = { + 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/x230/variants/x230/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb new file mode 100644 index 0000000000..5f2f3a58d5 --- /dev/null +++ b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb @@ -0,0 +1,15 @@ +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + device pci 1c.2 on + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" + end # PCIe Port #3 (expresscard) + device pci 1f.0 on # LPC bridge + chip ec/lenovo/h8 + register "eventa_enable" = "0x01" + end + end # LPC Controller + end + end +end From e8189b74261f28293b650fd9a45e7b3a225990a9 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 29 Apr 2020 12:09:32 -0700 Subject: [PATCH 195/405] acpi/soundwire: Add functions to generate SoundWire properties This change uses the previously added SoundWire definitions to provide functions that generate ACPI Device Properties for SoundWire controllers and codecs. A SoundWire controller driver should populate `struct soundwire_controller` and pass it to soundwire_gen_controller(). This will add all of the defined master links provided by the controller. A SoundWire codec driver should populate the necessary members in struct soundwire_codec and pass it to soundwire_gen_codec(). Several properties are optional and depend on whether the codec itself supports certain features and behaviors. The goal of this interface is to handle all of the properties defined in the SoundWire Discovery and Configuration Specification Version 1.0 so that controller and codec drivers do not need to all have code for writing standard properties. Both of these functions also provide a callback method for adding custom properties that are not defined by the SoundWire DisCo Specification. These properties may be required by OS drivers but are outside of the scope of the SoundWire specification itself. This code is tested with controller, codec, and mainboard implementations in subsequent commits. BUG=b:146482091 Signed-off-by: Duncan Laurie Change-Id: Ib185eaacf3c4914087497ed65479a772c155502b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40884 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/acpi/Makefile.inc | 1 + src/acpi/soundwire.c | 429 ++++++++++++++++++++++++++++++ src/include/acpi/acpi_soundwire.h | 45 ++++ 3 files changed, 475 insertions(+) create mode 100644 src/acpi/soundwire.c create mode 100644 src/include/acpi/acpi_soundwire.h diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc index 72fee4608e..5e83bc5678 100644 --- a/src/acpi/Makefile.inc +++ b/src/acpi/Makefile.inc @@ -9,6 +9,7 @@ ramstage-y += acpigen_ps2_keybd.c ramstage-y += device.c ramstage-y += pld.c ramstage-y += sata.c +ramstage-y += soundwire.c ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/acpi_tables.c),) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c diff --git a/src/acpi/soundwire.c b/src/acpi/soundwire.c new file mode 100644 index 0000000000..1151a181c1 --- /dev/null +++ b/src/acpi/soundwire.c @@ -0,0 +1,429 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Specification-defined prefix for SoundWire properties. */ +#define SDW_PFX "mipi-sdw-" + +/* Generate SoundWire property for integer. */ +#define SDW_INT(__key, __val) \ + acpi_dp_add_integer(dsd, SDW_PFX __key, __val) + +/* Generate SoundWire property for integer array. */ +#define SDW_INT_ARRAY(__key, __val) \ + acpi_dp_add_integer_array(dsd, SDW_PFX __key, __val, __val##_count) + +/** + * struct soundwire_name_map - Map ACPI name to SoundWire property name. + * @acpi_name: ACPI compatible name string. + * @sdw_name: MIPI SoundWire property name string. + */ +struct soundwire_name_map { + const char *acpi_name; + const char *sdw_name; +}; + +static const struct soundwire_name_map bra_mode_names[] = { + { "BRA0", SDW_PFX "port-bra-mode-0" }, + { "BRA1", SDW_PFX "port-bra-mode-1" }, + { "BRA2", SDW_PFX "port-bra-mode-2" }, + { "BRA3", SDW_PFX "port-bra-mode-3" }, +}; + +static const struct soundwire_name_map audio_mode_names[] = { + { "MOD0", SDW_PFX "port-audio-mode-0" }, + { "MOD1", SDW_PFX "port-audio-mode-1" }, + { "MOD2", SDW_PFX "port-audio-mode-2" }, + { "MOD3", SDW_PFX "port-audio-mode-3" }, +}; + +static const struct soundwire_name_map dpn_source_names[] = { + { "DP0", SDW_PFX "dp-0-subproperties" }, + { "SRC1", SDW_PFX "dp-1-source-subproperties" }, + { "SRC2", SDW_PFX "dp-2-source-subproperties" }, + { "SRC3", SDW_PFX "dp-3-source-subproperties" }, + { "SRC4", SDW_PFX "dp-4-source-subproperties" }, + { "SRC5", SDW_PFX "dp-5-source-subproperties" }, + { "SRC6", SDW_PFX "dp-6-source-subproperties" }, + { "SRC7", SDW_PFX "dp-7-source-subproperties" }, + { "SRC8", SDW_PFX "dp-8-source-subproperties" }, + { "SRC9", SDW_PFX "dp-9-source-subproperties" }, + { "SRCA", SDW_PFX "dp-10-source-subproperties" }, + { "SRCB", SDW_PFX "dp-11-source-subproperties" }, + { "SRCC", SDW_PFX "dp-12-source-subproperties" }, + { "SRCD", SDW_PFX "dp-13-source-subproperties" } +}; + +static const struct soundwire_name_map dpn_sink_names[] = { + { "DP0", SDW_PFX "dp-0-subproperties" }, + { "SNK1", SDW_PFX "dp-1-sink-subproperties" }, + { "SNK2", SDW_PFX "dp-2-sink-subproperties" }, + { "SNK3", SDW_PFX "dp-3-sink-subproperties" }, + { "SNK4", SDW_PFX "dp-4-sink-subproperties" }, + { "SNK5", SDW_PFX "dp-5-sink-subproperties" }, + { "SNK6", SDW_PFX "dp-6-sink-subproperties" }, + { "SNK7", SDW_PFX "dp-7-sink-subproperties" }, + { "SNK8", SDW_PFX "dp-8-sink-subproperties" }, + { "SNK9", SDW_PFX "dp-9-sink-subproperties" }, + { "SNKA", SDW_PFX "dp-10-sink-subproperties" }, + { "SNKB", SDW_PFX "dp-11-sink-subproperties" }, + { "SNKC", SDW_PFX "dp-12-sink-subproperties" }, + { "SNKD", SDW_PFX "dp-13-sink-subproperties" } +}; + +static const struct soundwire_name_map link_names[] = { + { "LNK0", SDW_PFX "link-0-subproperties" }, + { "LNK1", SDW_PFX "link-1-subproperties" }, + { "LNK2", SDW_PFX "link-2-subproperties" }, + { "LNK3", SDW_PFX "link-3-subproperties" }, + { "LNK4", SDW_PFX "link-4-subproperties" }, + { "LNK5", SDW_PFX "link-5-subproperties" }, + { "LNK6", SDW_PFX "link-6-subproperties" }, + { "LNK7", SDW_PFX "link-7-subproperties" } +}; + +static const char * const multilane_names[] = { + SDW_PFX "lane-1-mapping", + SDW_PFX "lane-2-mapping", + SDW_PFX "lane-3-mapping", + SDW_PFX "lane-4-mapping", + SDW_PFX "lane-5-mapping", + SDW_PFX "lane-6-mapping", + SDW_PFX "lane-7-mapping", + SDW_PFX "lane-8-mapping" +}; + +static const char * const multilane_master_lane_names[] = { + SDW_PFX "master-lane-1", + SDW_PFX "master-lane-2", + SDW_PFX "master-lane-3", + SDW_PFX "master-lane-4", + SDW_PFX "master-lane-5", + SDW_PFX "master-lane-6", + SDW_PFX "master-lane-7", + SDW_PFX "master-lane-8" +}; + +static const char * const multilane_slave_link_names[] = { + SDW_PFX "slave-link-A", + SDW_PFX "slave-link-B", + SDW_PFX "slave-link-C", + SDW_PFX "slave-link-D", + SDW_PFX "slave-link-E", + SDW_PFX "slave-link-F", + SDW_PFX "slave-link-G", + SDW_PFX "slave-link-I" +}; + +static const char * const multilane_bus_holder_names[] = { + SDW_PFX "lane-1-bus-holder", + SDW_PFX "lane-2-bus-holder", + SDW_PFX "lane-3-bus-holder", + SDW_PFX "lane-4-bus-holder", + SDW_PFX "lane-5-bus-holder", + SDW_PFX "lane-6-bus-holder", + SDW_PFX "lane-7-bus-holder", + SDW_PFX "lane-8-bus-holder" +}; + +static void soundwire_gen_interface_revision(struct acpi_dp *dsd) +{ + acpi_dp_add_integer(dsd, SDW_PFX "sw-interface-revision", SOUNDWIRE_SW_VERSION_1_0); +} + +static void soundwire_gen_slave(struct acpi_dp *dsd, const struct soundwire_slave *prop) +{ + soundwire_gen_interface_revision(dsd); + SDW_INT("wake-up-unavailable", prop->wake_up_unavailable); + SDW_INT("test-mode-supported", prop->test_mode_supported); + SDW_INT("clock-stop-mode1-supported", prop->clock_stop_mode1_supported); + + /* Clock Stop Prepare Timeout only used without simplified Clock Stop Prepare. */ + SDW_INT("simplified-clockstopprepare-sm-supported", + prop->simplified_clockstopprepare_sm_supported); + if (!prop->simplified_clockstopprepare_sm_supported) + SDW_INT("clockstopprepare-timeout", prop->clockstopprepare_timeout); + + SDW_INT("clockstopprepare-hard-reset-behavior", + prop->clockstopprepare_hard_reset_behavior); + SDW_INT("slave-channelprepare-timeout", prop->slave_channelprepare_timeout); + SDW_INT("highPHY-capable", prop->highPHY_capable); + SDW_INT("paging-supported", prop->paging_supported); + SDW_INT("bank-delay-supported", prop->bank_delay_supported); + SDW_INT("port15-read-behavior", prop->port15_read_behavior); + SDW_INT("master-count", prop->master_count); + SDW_INT("source-port-list", prop->source_port_list); + SDW_INT("sink-port-list", prop->sink_port_list); +} + +static void soundwire_gen_multilane(struct acpi_dp *dsd, const struct soundwire_multilane *prop) +{ + size_t i; + + soundwire_gen_interface_revision(dsd); + + /* Fill out multilane map based on master/slave links. */ + for (i = 0; i < prop->lane_mapping_count && i < SOUNDWIRE_MAX_LANE; i++) { + const struct soundwire_multilane_map *map = &prop->lane_mapping[i]; + const char *name; + + /* Get the name of this connection */ + if (map->direction == MASTER_LANE) + name = multilane_master_lane_names[map->connection.master_lane]; + else + name = multilane_slave_link_names[map->connection.slave_link]; + + acpi_dp_add_string(dsd, multilane_names[map->lane], name); + } + + /* Add bus holder properties. */ + for (i = 0; i < prop->lane_bus_holder_count; i++) + acpi_dp_add_integer(dsd, multilane_bus_holder_names[i], + prop->lane_bus_holder[i]); +} + +static void soundwire_gen_link(struct acpi_dp *dsd, const struct soundwire_link *prop) +{ + SDW_INT("clock-stop-mode0-supported", prop->clock_stop_mode0_supported); + SDW_INT("clock-stop-mode1-supported", prop->clock_stop_mode1_supported); + if (prop->clock_frequencies_supported_count > 0 && + prop->clock_frequencies_supported_count < SOUNDWIRE_MAX) { + SDW_INT_ARRAY("clock-frequencies-supported", + prop->clock_frequencies_supported); + } + SDW_INT("default-frame-rate", prop->default_frame_rate); + SDW_INT("default-frame-row-size", prop->default_frame_row_size); + SDW_INT("default-frame-col-size", prop->default_frame_col_size); + SDW_INT("dynamic-frame-shape", prop->dynamic_frame_shape); + SDW_INT("command-error-threshold", prop->command_error_threshold); +} + +static void soundwire_gen_bra_mode(struct acpi_dp *dsd, const struct soundwire_bra_mode *prop) +{ + /* Bus frequency configs used if min/max not supported. */ + if (prop->bus_frequency_configs_count > 0 && + prop->bus_frequency_configs_count < SOUNDWIRE_MAX) { + SDW_INT_ARRAY("bra-mode-bus-frequency-configs", prop->bus_frequency_configs); + } else { + SDW_INT("bra-mode-min-bus-frequency", prop->min_bus_frequency); + SDW_INT("bra-mode-max-bus-frequency", prop->max_bus_frequency); + } + SDW_INT("bra-mode-max-data-per-frame", prop->max_data_per_frame); + SDW_INT("bra-mode-min-us-between-transactions", prop->min_us_between_transactions); +} + +static void soundwire_gen_audio_mode(struct acpi_dp *dsd, + const struct soundwire_audio_mode *prop) +{ + /* Bus frequency configs used if min/max not supported. */ + if (prop->bus_frequency_configs_count > 0 && + prop->bus_frequency_configs_count < SOUNDWIRE_MAX) { + SDW_INT_ARRAY("audio-mode-bus-frequency-configs", prop->bus_frequency_configs); + } else { + SDW_INT("audio-mode-min-bus-frequency", prop->min_bus_frequency); + SDW_INT("audio-mode-max-bus-frequency", prop->max_bus_frequency); + } + + /* Sampling frequency configs used if min/max not supported. */ + if (prop->sampling_frequency_configs_count > 0 && + prop->sampling_frequency_configs_count < SOUNDWIRE_MAX) { + SDW_INT_ARRAY("audio-mode-sampling-frequency-configs", + prop->sampling_frequency_configs); + } else { + SDW_INT("audio-mode-max-sampling-frequency", prop->max_sampling_frequency); + SDW_INT("audio-mode-min-sampling-frequency", prop->min_sampling_frequency); + } + + SDW_INT("audio-mode-prepare-channel-behavior", prop->prepare_channel_behavior); + SDW_INT("audio-mode-glitchless-transitions", prop->glitchless_transitions); +} + +static void soundwire_gen_dp0(struct acpi_dp *dsd, const struct soundwire_dp0 *prop) +{ + size_t i; + + /* Max wordlength configs used if min/max not supported. */ + if (prop->port_wordlength_configs_count > 0 && + prop->port_wordlength_configs_count < SOUNDWIRE_MAX) { + SDW_INT_ARRAY("port-wordlength-configs", prop->port_wordlength_configs); + } else { + SDW_INT("port-max-wordlength", prop->port_max_wordlength); + SDW_INT("port-min-wordlength", prop->port_min_wordlength); + } + SDW_INT("bra-flow-controlled", prop->bra_flow_controlled); + SDW_INT("bra-imp-def-response-supported", prop->bra_imp_def_response_supported); + SDW_INT("bra-role-supported", prop->bra_role_supported); + SDW_INT("simplified-channel-prepare-sm", prop->simplified_channel_prepare_sm); + SDW_INT("imp-def-dp0-interrupts-supported", prop->imp_def_dp0_interrupts_supported); + SDW_INT("imp-def-bpt-supported", prop->imp_def_bpt_supported); + + /* Add bulk register access mode property pointers. */ + for (i = 0; i < prop->bra_mode_count && i < SOUNDWIRE_MAX_MODE; i++) { + struct acpi_dp *bra = acpi_dp_new_table(bra_mode_names[i].acpi_name); + acpi_dp_add_child(dsd, bra_mode_names[i].sdw_name, bra); + } +} + +static void soundwire_gen_dpn(struct acpi_dp *dsd, const struct soundwire_dpn *prop) +{ + size_t i; + + SDW_INT("data-port-type", prop->data_port_type); + SDW_INT("max-grouping-supported", prop->max_grouping_supported); + SDW_INT("imp-def-dpn-interrupts-supported", prop->imp_def_dpn_interrupts_supported); + SDW_INT("modes-supported", prop->modes_supported); + SDW_INT("max-async-buffer", prop->max_async_buffer); + SDW_INT("block-packing-mode", prop->block_packing_mode); + SDW_INT("port-encoding-type", prop->port_encoding_type); + + /* Max wordlength configs used if min/max not supported. */ + if (prop->port_wordlength_configs_count > 0 && + prop->port_wordlength_configs_count < SOUNDWIRE_MAX) { + SDW_INT_ARRAY("port-wordlength-configs", prop->port_wordlength_configs); + } else { + SDW_INT("port-max-wordlength", prop->port_max_wordlength); + SDW_INT("port-min-wordlength", prop->port_min_wordlength); + } + + /* Channel Prepare Timeout only used without simplified Channel Prepare. */ + SDW_INT("simplified-channelprepare-sm", prop->simplified_channelprepare_sm); + if (!prop->simplified_channelprepare_sm) + SDW_INT("port-channelprepare-timeout", prop->port_channelprepare_timeout); + + /* Channel number list used if min/max not supported. */ + if (prop->channel_number_list_count > 0 && + prop->channel_number_list_count < SOUNDWIRE_MAX) { + SDW_INT_ARRAY("channel-number-list", prop->channel_number_list); + } else { + SDW_INT("min-channel-number", prop->min_channel_number); + SDW_INT("max-channel-number", prop->max_channel_number); + } + if (prop->channel_combination_list_count > 0 && + prop->channel_combination_list_count < SOUNDWIRE_MAX) { + SDW_INT_ARRAY("channel-combination-list", prop->channel_combination_list); + } + + /* Add reference to Audio Mode properties. */ + for (i = 0; i < prop->port_audio_mode_count && i < SOUNDWIRE_MAX_MODE; i++) { + struct acpi_dp *am = acpi_dp_new_table(audio_mode_names[i].acpi_name); + acpi_dp_add_child(dsd, audio_mode_names[i].sdw_name, am); + } +} + +void soundwire_gen_controller(struct acpi_dp *dsd, const struct soundwire_controller *prop, + soundwire_link_prop_cb link_prop_cb) +{ + size_t i; + + soundwire_gen_interface_revision(dsd); + SDW_INT("master-count", prop->master_list_count); + + /* Generate properties for each master link on the controller. */ + for (i = 0; i < prop->master_list_count && i < SOUNDWIRE_MAX_LINK; i++) { + struct acpi_dp *link = acpi_dp_new_table(link_names[i].acpi_name); + soundwire_gen_link(link, &prop->master_list[i]); + + /* Callback for custom link properties from the controller. */ + if (link_prop_cb) + link_prop_cb(link, i, prop); + acpi_dp_add_child(dsd, link_names[i].sdw_name, link); + } +} + +void soundwire_gen_codec(struct acpi_dp *dsd, const struct soundwire_codec *codec, + soundwire_dp_prop_cb dp_prop_cb) +{ + const struct soundwire_dpn_entry *entry; + const struct soundwire_name_map *name; + size_t i; + + /* Generate slave properties for this codec. */ + soundwire_gen_slave(dsd, codec->slave); + + /* Generate properties for multilane config, if provided. */ + if (codec->multilane) + soundwire_gen_multilane(dsd, codec->multilane); + + /* Generate properties for data port 0, if provided. */ + if (codec->dp0) { + struct acpi_dp *dp0; + + /* First generate any Bulk Register Access mode properties. */ + for (i = 0; i < SOUNDWIRE_MAX_MODE; i++) { + const struct soundwire_bra_mode *prop = codec->dp0_bra_mode[i]; + struct acpi_dp *bra; + + /* Stop processing at the first undefined BRA mode. */ + if (!prop) + break; + name = &bra_mode_names[i]; + bra = acpi_dp_new_table(name->acpi_name); + soundwire_gen_bra_mode(bra, prop); + acpi_dp_add_child(dsd, name->sdw_name, bra); + } + + name = &dpn_source_names[0]; + dp0 = acpi_dp_new_table(name->acpi_name); + soundwire_gen_dp0(dp0, codec->dp0); + + /* Callback for custom properties from the codec. */ + if (dp_prop_cb) + dp_prop_cb(dp0, 0, codec); + acpi_dp_add_child(dsd, name->sdw_name, dp0); + } + + /* + * First generate audio modes for the data ports. This results in unnecessary + * (but harmless) references to the audio modes at the codec level, but it allows + * the data ports to use these objects without duplication. + */ + for (i = 0; i < SOUNDWIRE_MAX_MODE; i++) { + const struct soundwire_audio_mode *prop = codec->audio_mode[i]; + struct acpi_dp *am; + + /* Stop processing at the first undefined audio mode. */ + if (!prop) + break; + name = &audio_mode_names[i]; + am = acpi_dp_new_table(name->acpi_name); + soundwire_gen_audio_mode(am, prop); + acpi_dp_add_child(dsd, name->sdw_name, am); + } + + /* Now generate properties for source/slave on each defined data port. */ + for (entry = codec->dpn; entry; entry++) { + struct acpi_dp *dpn; + + /* Stop processing at the first invalid data port. */ + if (entry->port < SOUNDWIRE_MIN_DPN || entry->port > SOUNDWIRE_MAX_DPN) + break; + + if (entry->source) { + name = &dpn_source_names[entry->port]; + dpn = acpi_dp_new_table(name->acpi_name); + soundwire_gen_dpn(dpn, entry->source); + + /* Callback for custom properties from the codec. */ + if (dp_prop_cb) + dp_prop_cb(dpn, entry->port, codec); + acpi_dp_add_child(dsd, name->sdw_name, dpn); + } + if (entry->sink) { + name = &dpn_sink_names[entry->port]; + dpn = acpi_dp_new_table(name->acpi_name); + soundwire_gen_dpn(dpn, entry->sink); + + /* Callback for custom properties from the codec. */ + if (dp_prop_cb) + dp_prop_cb(dpn, entry->port, codec); + acpi_dp_add_child(dsd, name->sdw_name, dpn); + } + } +} diff --git a/src/include/acpi/acpi_soundwire.h b/src/include/acpi/acpi_soundwire.h new file mode 100644 index 0000000000..50c088afce --- /dev/null +++ b/src/include/acpi/acpi_soundwire.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ACPI_ACPI_SOUNDWIRE_H__ +#define __ACPI_ACPI_SOUNDWIRE_H__ + +#include +#include + +/** + * soundwire_dp_prop_cb() - Callback to add custom data port properties. + * @dsd: ACPI Device Property handle for this data port. + * @port_id: Data Port ID from 0-14. + * @codec: Properties that were passed to soundwire_gen_codec(). + */ +typedef void soundwire_dp_prop_cb(struct acpi_dp *dsd, unsigned int port_id, + const struct soundwire_codec *codec); + +/** + * soundwire_gen_codec() - Generate SoundWire properties for codec device. + * @dsd: ACPI Device Property handle. + * @prop: Properties for codec which includes all other properties. + * @dp_prop_cb: Callback to allow custom codec properties. + */ +void soundwire_gen_codec(struct acpi_dp *dsd, const struct soundwire_codec *codec, + soundwire_dp_prop_cb dp_prop_cb); + +/** + * soundwire_link_prop_cb() - Callback to add custom link properties. + * @dsd: ACPI Device Property handle for master link. + * @link_id: Link number for this master. + * @controller: Properties that were passed to soundwire_gen_controller(). + */ +typedef void soundwire_link_prop_cb(struct acpi_dp *dsd, unsigned int link_id, + const struct soundwire_controller *controller); + +/** + * soundwire_gen_controller() - Generate SoundWire properties for master links. + * @dsd: ACPI Device Property handle for controller. + * @prop: Properties for controller which includes all other properties. + * @link_prop_cb: Callback to allow custom link properties. + */ +void soundwire_gen_controller(struct acpi_dp *dsd, const struct soundwire_controller *prop, + soundwire_link_prop_cb link_prop_cb); + +#endif /* __ACPI_ACPI_SOUNDWIRE_H__ */ From 08a942fd32d23b940b8671e35e94f88062d7859f Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 29 Apr 2020 12:13:14 -0700 Subject: [PATCH 196/405] acpi/device: Add a helper function to write SoundWire _ADR This change adds a help function to write a SoundWire ACPI address object that conforms to the SoundWire DisCo Specification Version 1.0 The SoundWire address structure is defined in include/device/soundwire.h and provides the properties that are used to form the _ADR object. BUG=b:146482091 Signed-off-by: Duncan Laurie Change-Id: I6efbf52ce20b53f96d69efe2bf004b98dbe06552 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40885 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/acpi/acpigen.c | 28 ++++++++++++++++++++++++++++ src/include/acpi/acpigen.h | 2 ++ 2 files changed, 30 insertions(+) diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 08f482d2a2..793841cc5b 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -18,6 +18,7 @@ #include #include #include +#include static char *gencurrent; @@ -1885,3 +1886,30 @@ void acpigen_write_ADR_pci_device(const struct device *dev) assert(dev->path.type == DEVICE_PATH_PCI); acpigen_write_ADR_pci_devfn(dev->path.pci.devfn); } + +/** + * acpigen_write_ADR_soundwire_device() - SoundWire ACPI Device Address Encoding. + * @address: SoundWire device address properties. + * + * From SoundWire Discovery and Configuration Specification Version 1.0 Table 3. + * + * 63..52 - Reserved (0) + * 51..48 - Zero-based SoundWire Link ID, relative to the immediate parent. + * Used when a Controller has multiple master devices, each producing a + * separate SoundWire Link. Set to 0 for single-link controllers. + * 47..0 - SoundWire Device ID Encoding from specification version 1.2 table 88 + * 47..44 - SoundWire specification version that this device supports + * 43..40 - Unique ID for multiple devices + * 39..24 - MIPI standard manufacturer code + * 23..08 - Vendor defined part ID + * 07..00 - MIPI class encoding + */ +void acpigen_write_ADR_soundwire_device(const struct soundwire_address *address) +{ + acpigen_write_ADR((((uint64_t)address->link_id & 0xf) << 48) | + (((uint64_t)address->version & 0xf) << 44) | + (((uint64_t)address->unique_id & 0xf) << 40) | + (((uint64_t)address->manufacturer_id & 0xffff) << 24) | + (((uint64_t)address->part_id & 0xffff) << 8) | + (((uint64_t)address->class & 0xff))); +} diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index 895433546e..a99489de1f 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -374,6 +374,8 @@ void acpigen_write_pld(const struct acpi_pld *pld); void acpigen_write_ADR(uint64_t adr); void acpigen_write_ADR_pci_devfn(pci_devfn_t devfn); void acpigen_write_ADR_pci_device(const struct device *dev); +struct soundwire_address; +void acpigen_write_ADR_soundwire_device(const struct soundwire_address *address); /* * Generate ACPI AML code for _DSM method. * This function takes as input uuid for the device, set of callbacks and From 10f55a2c9d1073f8facf90b6b2c4b3b87615e951 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 29 Apr 2020 12:17:54 -0700 Subject: [PATCH 197/405] soc/intel/tigerlake: Make audio devices scan the bus The audio devices are currently set to enable static devices at their own level, but in order to supported nested SoundWire devices these drivers must instead use scan_static_bus. Without this change the device tree code will not look at children of these devices. After this change the audio device can have nested devices: device pci 1f.3 on chip drivers/intel/soundwire device generic 0 on end end end BUG=b:146482091 Signed-off-by: Duncan Laurie Change-Id: Ibb716fbd9ffdc45f2c4bbe5e81f420ec2b13483c Reviewed-on: https://review.coreboot.org/c/coreboot/+/40886 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/common/block/dsp/dsp.c | 2 +- src/soc/intel/common/block/hda/hda.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 5181d0b062..2360d7d07f 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -9,7 +9,7 @@ static struct device_operations dsp_dev_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .ops_pci = &pci_dev_ops_pci, - .scan_bus = enable_static_devices, + .scan_bus = scan_static_bus, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 916775fc4b..c84415fb60 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -54,7 +54,7 @@ static struct device_operations hda_ops = { .init = hda_init, #endif .ops_pci = &pci_dev_ops_pci, - .scan_bus = enable_static_devices, + .scan_bus = scan_static_bus }; static const unsigned short pci_device_ids[] = { From 5b01f2bf0c4f61718c0df73e0c834adadd2a20e5 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 20 May 2020 16:01:43 +0200 Subject: [PATCH 198/405] soc/amd/picasso/southbridge: add missing soc/i2c.h include soc/i2c.h gets included indirectly via chip.h and removing the chip.h in 73716d0e924080ea32274a265a8de04e009c3676 broke the build. chip.h got added back, but including soc/i2c.h directly fixes the underlying issue. Change-Id: Ic84f7b6b4447b7c335a51dc604daf8924851e555 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/41557 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Furquan Shaikh --- src/soc/amd/picasso/southbridge.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 2261a30921..123eca772a 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include From 5640cfdc92b6cfbbeb9f0583a56ebbfaea3b34f7 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 20 May 2020 01:25:46 +0200 Subject: [PATCH 199/405] soc/amd/picasso/include/soc_util: add include guards Change-Id: I2de16eaa88baace28afa30345b7762353a48ab87 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/41558 Reviewed-by: Angel Pons Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/include/soc/soc_util.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/soc/amd/picasso/include/soc/soc_util.h b/src/soc/amd/picasso/include/soc/soc_util.h index 8e2c598630..9077195a88 100644 --- a/src/soc/amd/picasso/include/soc/soc_util.h +++ b/src/soc/amd/picasso/include/soc/soc_util.h @@ -1,5 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __PICASSO_SOC_UTIL_H__ +#define __PICASSO_SOC_UTIL_H__ + enum socket_type { SOCKET_FP5 = 0, SOCKET_AM4 = 2, @@ -13,3 +16,5 @@ int soc_is_dali(void); int soc_is_picasso(void); int soc_is_raven2(void); int soc_is_zen_plus(void); + +#endif /* __PICASSO_SOC_UTIL_H__ */ From 368873ced315fb00b1052b5e5633d2d157a8f0a1 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 20 May 2020 02:42:41 +0200 Subject: [PATCH 200/405] soc/amd/picasso/soc_util: change return type of soc_is_* All callers just check for zero/non-zero. Change-Id: I795763ce882d879d12c97b71e7a0b35423378c36 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/41559 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Raul Rangel --- src/soc/amd/picasso/include/soc/soc_util.h | 12 +++++++----- src/soc/amd/picasso/soc_util.c | 10 +++++----- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/src/soc/amd/picasso/include/soc/soc_util.h b/src/soc/amd/picasso/include/soc/soc_util.h index 9077195a88..6515761a8a 100644 --- a/src/soc/amd/picasso/include/soc/soc_util.h +++ b/src/soc/amd/picasso/include/soc/soc_util.h @@ -3,6 +3,8 @@ #ifndef __PICASSO_SOC_UTIL_H__ #define __PICASSO_SOC_UTIL_H__ +#include + enum socket_type { SOCKET_FP5 = 0, SOCKET_AM4 = 2, @@ -11,10 +13,10 @@ enum socket_type { void print_socket_type(void); -int soc_is_pollock(void); -int soc_is_dali(void); -int soc_is_picasso(void); -int soc_is_raven2(void); -int soc_is_zen_plus(void); +bool soc_is_pollock(void); +bool soc_is_dali(void); +bool soc_is_picasso(void); +bool soc_is_raven2(void); +bool soc_is_zen_plus(void); #endif /* __PICASSO_SOC_UTIL_H__ */ diff --git a/src/soc/amd/picasso/soc_util.c b/src/soc/amd/picasso/soc_util.c index f82811053c..89aa0a40ff 100644 --- a/src/soc/amd/picasso/soc_util.c +++ b/src/soc/amd/picasso/soc_util.c @@ -37,7 +37,7 @@ void print_socket_type(void) } } -int soc_is_pollock(void) +bool soc_is_pollock(void) { return soc_is_zen_plus() && get_socket_type() == SOCKET_FT5; } @@ -46,23 +46,23 @@ int soc_is_pollock(void) * TODO: This detection works for the Dali SKUs used in Chrome-devices, but fails for other * Dali SKUs, since other Dali SKUs have a Zen+ CPUID and not a Raven2 one. */ -int soc_is_dali(void) +bool soc_is_dali(void) { return soc_is_raven2() && get_socket_type() == SOCKET_FP5; } -int soc_is_picasso(void) +bool soc_is_picasso(void) { return soc_is_zen_plus() && get_socket_type() == SOCKET_FP5; } -int soc_is_raven2(void) +bool soc_is_raven2(void) { /* mask lower model number nibble and stepping */ return cpuid_eax(1) >> 8 == RAVEN2_CPUID >> 8; } -int soc_is_zen_plus(void) +bool soc_is_zen_plus(void) { /* mask lower model number nibble and stepping */ return cpuid_eax(1) >> 8 == PICASSO_CPUID >> 8; From b768723c72b326b24703a8e67764c995711050d9 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Mon, 20 Jan 2020 19:56:30 -0700 Subject: [PATCH 201/405] soc/amd/picasso: Add APOB NV back for non-S3 New information indicates the PSP expects the APOB NV region populated for all types of boot, and this is not a feature only used for S3. Switch over to using the MRC_CACHE flash region. Remove the Kconfig symbols for the APOB_NV base and size. Override the MRC_CACHE_SETTINGS_CACHE_SIZE to ensure the default maintains the minimum required size. Use the generated (or mainboard-specified) fmap.fmd file as an input for amdfwtool and properly match the flash region. Change the original naming for the APOB destination, which matched the PSP spec's field name, to PSP_APOB_DESTINATION. This should be more intuitive for a source code reader. The APOB address is the location in DRAM where the PSP puts its output block. BUG=b:147042464, b:153675914 TEST=Boot trembyle Original-Change-Id: Ia5ba8646deec2bd282df930f471738723063eef8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2080375 Original-Change-Id: I972d66f1817f86ff0b689f011c0c44c3fe7c8ef7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2053312 Signed-off-by: Marshall Dawson Change-Id: I4550766ece462b65a6bfe6f1b747343e08e53fe5 Signed-off-by: Raul E Rangel Reviewed-on: https://review.coreboot.org/c/coreboot/+/38703 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/amd/picasso/Kconfig | 22 +++++++++++----------- src/soc/amd/picasso/Makefile.inc | 32 +++++++++++++++++++++----------- 2 files changed, 32 insertions(+), 22 deletions(-) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 2578b468aa..ce1f0743f5 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -51,6 +51,7 @@ config CPU_SPECIFIC_OPTIONS select PLATFORM_USES_FSP2_0 select FSP_USES_CB_STACK select UDK_2017_BINDING + select CACHE_MRC_SETTINGS select HAVE_CF9_RESET config PRERAM_CBMEM_CONSOLE_SIZE @@ -289,24 +290,23 @@ config AMD_PUBKEY_FILE string default "3rdparty/amd_blobs/picasso/PSP/AmdPubKeyRV.bin" -config PSP_APOB_DESTINATION +config PSP_APOB_DRAM_ADDRESS hex default 0x9f00000 help Location in DRAM where the PSP will copy the AGESA PSP Output Block. -config PSP_APOB_NV_ADDRESS - hex "Base address of APOB NV" +# This value is currently the same as the default defined in +# drivers/mrc_cache/Kconfig. We do this in in case the default +# changes. The PSP requires this value to be 64KiB. +config MRC_SETTINGS_CACHE_SIZE + hex + default 0x10000 help - Location in flash where the PSP can find the S3 restore information. - Place this on a boundary that the flash device can erase. - -config PSP_APOB_NV_SIZE - hex "Size of APOB NV to be reserved" - help - Size of the S3 restore information. Make this a multiple of the - size the flash device can erase. + Size of flash area used to save APOB NV data which occupies the + RW_MRC_CACHE region. Make this granularity the flash device can + erase. config USE_PSPSCUREOS bool diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index ed94cfb63a..e1416bcddd 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -181,7 +181,7 @@ endif PSP_APCB_FILES=$(foreach f, $(APCB_SOURCES), $(obj)/APCB_$(f).bin) # type = 0x61 -PSP_APOB_BASE=$(CONFIG_PSP_APOB_DESTINATION) +PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) # type = 0x62 PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img @@ -192,11 +192,18 @@ PSP_BIOSBIN_SIZE=$(CONFIG_C_ENV_BOOTBLOCK_SIZE) # This address must match the BOOTBLOCK logic in arch/x86/memlayout.ld. PSP_BIOSBIN_DEST=$(shell printf "%x" $(call int-subtract, $(call int-add, $(CONFIG_X86_RESET_VECTOR) 0x10) $(PSP_BIOSBIN_SIZE))) -# type = 0x63 -ifeq ($(CONFIG_HAVE_ACPI_RESUME),y) -PSP_APOBNV_BASE=$(CONFIG_PSP_APOB_NV_ADDRESS) -PSP_APOBNV_SIZE=$(CONFIG_PSP_APOB_NV_SIZE) -endif +# type = 0x63 - construct APOB NV base/size from flash map +# TODO(b/157068645): Add ability to fmaptool to extract offsets and sizes +# This code currently assumes the following FMAP structure. If +# the UNIFIED_MRC_CACHE region is present, it must have a 0 offset. +# FLASH@* { +# BIOS@* { +# RW_MRC_CACHE@* { +_FLASH_BASE=$(call int-subtract, 0x100000000 $(CONFIG_ROM_SIZE)) +_GET_FLASH_BASE=grep "FLASH" | sed 's/.*FLASH@//' | sed 's/ .*//' +_GET_BIOS_REG_BASE=grep "BIOS" | sed 's/.*BIOS@//' | sed 's/ .*//' +_GET_APOBNV_BASE=grep "RW_MRC_CACHE" | sed 's/.*@//' | sed 's/ .*//' +_GET_APOBNV_SIZE=grep "RW_MRC_CACHE" | sed 's/.*@//' | sed 's/.* //' # type2 = 0x64, 0x65 PSP_PMUI_FILE1=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_1D_Ddr4_Udimm_Imem.csbin @@ -264,8 +271,6 @@ OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) -OPT_APOBNV_ADDR=$(call add_opt_prefix, $(PSP_APOBNV_BASE), --apob-nv-base) -OPT_APOBNV_SIZE=$(call add_opt_prefix, $(PSP_APOBNV_SIZE), --apob-nv-size) OPT_PSP_PMUI_FILE1=$(call add_opt_prefix, $(PSP_PMUI_FILE1), --subprogram 0 --instance 1 --pmu-inst) OPT_PSP_PMUI_FILE2=$(call add_opt_prefix, $(PSP_PMUI_FILE2), --subprogram 0 --instance 4 --pmu-inst) OPT_PSP_PMUI_FILE3=$(call add_opt_prefix, $(PSP_PMUI_FILE3), --subprogram 1 --instance 1 --pmu-inst) @@ -359,7 +364,8 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call_strip_quotes, $(PSP_IKEK_FILE)) \ $(call_strip_quotes, $(PSP_SEC_DEBUG_FILE)) \ $$(PSP_APCB_FILES) \ - $(AMDFWTOOL) + $(AMDFWTOOL) \ + $(obj)/fmap.fmd rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ @@ -373,8 +379,12 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(OPT_SMUFW2_SUB1_FILE) \ $(OPT_PSP_APCB_FILES) \ $(OPT_APOB_ADDR) \ - $(OPT_APOBNV_ADDR) \ - $(OPT_APOBNV_SIZE) \ + --apob-nv-size $(shell printf "0x%x" \ + $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_SIZE))) \ + --apob-nv-base $(shell printf "0x%x" $(call int-add, \ + $(shell cat $(obj)/fmap.fmd | $(_GET_FLASH_BASE)) \ + $(shell cat $(obj)/fmap.fmd | $(_GET_BIOS_REG_BASE)) \ + $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_BASE)))) \ $(OPT_PSP_BIOSBIN_FILE) \ $(OPT_PSP_BIOSBIN_DEST) \ $(OPT_PSP_BIOSBIN_SIZE) \ From 7ed04e460d4e3e99af82c4bb445e4e1b3ac1dd47 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Wed, 20 May 2020 13:52:32 -0600 Subject: [PATCH 202/405] vc/amd/fsp/picasso: Rename the fsp_ddi and fsp_pcie descriptors This change was missed when I ported over fsp_params.c. BUG=b:157140753 TEST=Boot trembyle to OS Fixes: 89e51e61781 ("soc/amd/picasso: Allow mainboard to provide pci ddi descriptors") Signed-off-by: Raul E Rangel Change-Id: Icdb6aebe5a3be7174170bdf37a1f379f02dcc5a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41579 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Reviewed-by: Felix Held --- src/vendorcode/amd/fsp/picasso/platform_descriptors.h | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h index 890804f85e..021558d600 100644 --- a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h +++ b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h @@ -101,17 +101,15 @@ typedef enum { MAX_CONNECTOR_TYPE // Not valid value, used to verify input } pcie_connector_type; -/* DDI Descriptor: used for configuring display outputs */ +/* Picasso DDI Descriptor: used for configuring display outputs */ typedef struct __packed { uint8_t connector_type; uint8_t aux_index; uint8_t hdp_index; uint8_t reserved; -} fsp_ddi_descriptor; +} picasso_fsp_ddi_descriptor; -/* PCIe Descriptor: used for assigning lanes, bifurcation and other settings */ -/* Since the code will always be compiled as little endian, using a bitfield struct should be - safe here. */ +/* Picasso PCIe Descriptor: used for assigning lanes, bifurcation and other settings */ typedef struct __packed { uint8_t engine_type; uint8_t start_lane; // Start lane of the pci device @@ -139,6 +137,6 @@ typedef struct __packed { unsigned int channel_type :3; unsigned int turn_off_unused_lanes :1; uint8_t reserved[4]; -} fsp_pcie_descriptor; +} picasso_fsp_pcie_descriptor; #endif /* __PI_PICASSO_PLATFORM_DESCRIPTORS_H__ */ From b631d07494805d7e3c7729ebd12c25f2166ff550 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 2 May 2020 20:00:32 +0200 Subject: [PATCH 203/405] nb/intel/sandybridge: Refactor IOSAV_SUBSEQUENCE again To replace the register writes with assignments to struct fields, we would need to have the values as parameters of a single macro. So, split the raw value of `IOSAV_n_SP_CMD_CTRL_ch` in two parts. Note that the single command that sets bit 17 is likely wrong, but it will be fixed after refactoring. For now, we'll treat it as part of `ranksel`. Move the parameters of `ADDR_UPDATE` into the top-level IOSAV macro. Hopefully, this will be enough to replace the underlying implementation. Line length limits are not for review. Breaking the lines unnecessarily complicates search and replace operations, and wil be taken care of in subsequent commits. Tested with BUILD_TIMELESS=1, ASUS P8Z77-V LX2 remains unchanged. Change-Id: I404edbd5d90ddc2a6993f39f552480d1ef24e153 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40978 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Arthur Heymans --- .../intel/sandybridge/mchbar_regs.h | 12 +- .../intel/sandybridge/raminit_common.c | 292 +++++++++--------- .../intel/sandybridge/raminit_common.h | 2 - 3 files changed, 149 insertions(+), 157 deletions(-) diff --git a/src/northbridge/intel/sandybridge/mchbar_regs.h b/src/northbridge/intel/sandybridge/mchbar_regs.h index ba0f7d5952..446861b4b7 100644 --- a/src/northbridge/intel/sandybridge/mchbar_regs.h +++ b/src/northbridge/intel/sandybridge/mchbar_regs.h @@ -213,18 +213,12 @@ ((rate) << 12) | \ ((xors) << 16)) -/* Marker macro for IOSAV_n_ADDR_UPDATE */ -#define ADDR_UPDATE_NONE 0 - -/* Only programming the wraparound without any triggers is suspicious */ -#define ADDR_UPDATE_WRAP(wrap) ((wrap) << 5) - -#define IOSAV_SUBSEQUENCE(ch, n, sp_cmd_ctrl, reps, gap, post, dir, addr, rowbits, bank, rank, addr_update) \ +#define IOSAV_SUBSEQUENCE(ch, n, cmd, ranksel, reps, gap, post, dir, addr, rowbits, bank, rank, addr_1, addr_8, upd_bank, upd_rank, wrap, lfsr, rate, xors) \ do { \ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(ch, n)) = sp_cmd_ctrl; \ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(ch, n)) = (cmd) | ((ranksel) << 16); \ MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(ch, n)) = SUBSEQ_CTRL(reps, gap, post, dir); \ MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(ch, n)) = SP_CMD_ADDR(addr, rowbits, bank, rank); \ - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(ch, n)) = addr_update; \ + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(ch, n)) = ADDR_UPDATE(addr_1, addr_8, upd_bank, upd_rank, wrap, lfsr, rate, xors); \ } while (0) /* Indexed register helper macros */ diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index dac34a4a34..ae8fa5f459 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -573,10 +573,10 @@ static void write_reset(ramctr_timing *ctrl) /* DRAM command ZQCS */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ZQCS & NO_RANKSEL, + IOSAV_ZQCS, 0, 1, 3, 8, SSQ_NA, 0, 6, 0, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* * Execute command queue - why is bit 22 set here?! @@ -666,24 +666,24 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, /* DRAM command MRS */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_MRS & NO_RANKSEL, + IOSAV_MRS, 0, 1, 4, 4, SSQ_NA, val, 6, reg, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* DRAM command MRS */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_MRS | RANKSEL, + IOSAV_MRS, 1, 1, 4, 4, SSQ_NA, val, 6, reg, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* DRAM command MRS */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_MRS & NO_RANKSEL, + IOSAV_MRS, 0, 1, 4, ctrl->tMOD, SSQ_NA, val, 6, reg, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(3); @@ -810,17 +810,17 @@ void dram_mrscommands(ramctr_timing *ctrl) /* DRAM command NOP (without ODT nor chip selects) */ IOSAV_SUBSEQUENCE(BROADCAST_CH, 0, - IOSAV_NOP & NO_RANKSEL & ~(0xff << 8), + IOSAV_NOP & ~(0xff << 8), 0, 1, 4, 15, SSQ_NA, 2, 6, 0, 0, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* DRAM command ZQCL */ IOSAV_SUBSEQUENCE(BROADCAST_CH, 1, - IOSAV_ZQCS | RANKSEL, + IOSAV_ZQCS, 1, 1, 4, 400, SSQ_NA, 1024, 6, 0, 0, - ADDR_UPDATE(0, 0, 0, 1, 20, 0, 0, 0)); + 0, 0, 0, 1, 20, 0, 0, 0); /* Execute command queue on all channels. Do it four times. */ MCHBAR32(IOSAV_SEQ_CTL) = (1 << 18) | 4; @@ -845,10 +845,10 @@ void dram_mrscommands(ramctr_timing *ctrl) /* DRAM command ZQCS */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ZQCS & NO_RANKSEL, + IOSAV_ZQCS, 0, 1, 36, 101, SSQ_NA, 0, 6, 0, slotrank, - ADDR_UPDATE_WRAP(31)); + 0, 0, 0, 0, 31, 0, 0, 0); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); @@ -1013,32 +1013,32 @@ static void test_timA(ramctr_timing *ctrl, int channel, int slotrank) in this mode only RD and RDA are allowed all reads return a predefined pattern */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_MRS | RANKSEL, + IOSAV_MRS, 1, 1, 3, ctrl->tMOD, SSQ_NA, 4, 6, 3, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_RD | RANKSEL, + IOSAV_RD, 1, 1, 3, 4, SSQ_RD, 0, 0, 0, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD | RANKSEL, + IOSAV_RD, 1, 15, 4, ctrl->CAS + 36, SSQ_NA, 0, 6, 0, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* DRAM command MRS write MR3 MPR disable */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_MRS | RANKSEL, + IOSAV_MRS, 1, 1, 3, ctrl->tMOD, SSQ_NA, 0, 6, 3, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -1301,10 +1301,10 @@ int read_training(ramctr_timing *ctrl) /* DRAM command PREA */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_PRE | RANKSEL, + IOSAV_PRE, 1, 1, 3, ctrl->tRP, SSQ_NA, 1024, 6, 0, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); @@ -1402,31 +1402,31 @@ static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) /* DRAM command ACT */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ACT | RANKSEL, + IOSAV_ACT, 1, 4, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), ctrl->tRCD, SSQ_NA, 0, 6, 0, slotrank, - ADDR_UPDATE(0, 0, 1, 0, 18, 0, 0, 0)); + 0, 0, 1, 0, 18, 0, 0, 0); /* DRAM command NOP */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_NOP | RANKSEL, + IOSAV_NOP, 1, 1, 4, 4, SSQ_WR, 8, 0, 0, slotrank, - ADDR_UPDATE_WRAP(31)); + 0, 0, 0, 0, 31, 0, 0, 0); /* DRAM command WR */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_WR | RANKSEL, + IOSAV_WR, 1, 500, 4, 4, SSQ_WR, 0, 0, 0, slotrank, - ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); + 0, 1, 0, 0, 18, 0, 0, 0); /* DRAM command NOP */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_NOP | RANKSEL, + IOSAV_NOP, 1, 1, 3, ctrl->CWL + ctrl->tWTR + 5, SSQ_WR, 8, 0, 0, slotrank, - ADDR_UPDATE_WRAP(31)); + 0, 0, 0, 0, 31, 0, 0, 0); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -1435,31 +1435,31 @@ static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) /* DRAM command PREA */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_PRE | RANKSEL, + IOSAV_PRE, 1, 1, 3, ctrl->tRP, SSQ_NA, 1024, 6, 0, slotrank, - ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); + 0, 0, 0, 0, 18, 0, 0, 0); /* DRAM command ACT */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_ACT | RANKSEL, + IOSAV_ACT, 1, 8, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), ctrl->CAS, SSQ_NA, 0, 6, 0, slotrank, - ADDR_UPDATE(0, 0, 1, 0, 18, 0, 0, 0)); + 0, 0, 1, 0, 18, 0, 0, 0); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD | RANKSEL, + IOSAV_RD, 1, 500, 4, MAX(ctrl->tRTP, 8), SSQ_RD, 0, 0, 0, slotrank, - ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); + 0, 1, 0, 0, 18, 0, 0, 0); /* DRAM command PREA */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_PRE | RANKSEL, + IOSAV_PRE, 1, 1, 3, ctrl->tRP, SSQ_NA, 1024, 6, 0, slotrank, - ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); + 0, 0, 0, 0, 18, 0, 0, 0); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -1496,10 +1496,10 @@ static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) /* DRAM command PREA */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_PRE | RANKSEL, + IOSAV_PRE, 1, 1, 3, ctrl->tRP, SSQ_NA, 1024, 6, 0, slotrank, - ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); + 0, 0, 0, 0, 18, 0, 0, 0); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); @@ -1603,32 +1603,32 @@ static void precharge(ramctr_timing *ctrl) in this mode only RD and RDA are allowed all reads return a predefined pattern */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_MRS | RANKSEL, + IOSAV_MRS, 1, 1, 3, ctrl->tMOD, SSQ_NA, 4, 6, 3, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_RD | RANKSEL, + IOSAV_RD, 1, 3, 4, 4, SSQ_RD, 0, 0, 0, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD | RANKSEL, + IOSAV_RD, 1, 1, 4, ctrl->CAS + 8, SSQ_NA, 0, 6, 0, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* DRAM command MRS * write MR3 MPR disable */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_MRS | RANKSEL, + IOSAV_MRS, 1, 1, 3, ctrl->tMOD, SSQ_NA, 0, 6, 3, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -1650,32 +1650,32 @@ static void precharge(ramctr_timing *ctrl) * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_MRS | RANKSEL, + IOSAV_MRS, 1, 1, 3, ctrl->tMOD, SSQ_NA, 4, 6, 3, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_RD | RANKSEL, + IOSAV_RD, 1, 3, 4, 4, SSQ_RD, 0, 0, 0, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD | RANKSEL, + IOSAV_RD, 1, 1, 4, ctrl->CAS + 8, SSQ_NA, 0, 6, 0, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* DRAM command MRS * write MR3 MPR disable */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_MRS | RANKSEL, + IOSAV_MRS, 1, 1, 3, ctrl->tMOD, SSQ_NA, 0, 6, 3, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -1693,17 +1693,17 @@ static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command NOP */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_NOP | RANKSEL, + IOSAV_NOP, 1, 1, 3, ctrl->CWL + ctrl->tWLO, SSQ_WR, 8, 0, 0, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* DRAM command NOP */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_NOP_ALT | RANKSEL, + IOSAV_NOP_ALT, 1, 1, 3, ctrl->CAS + 38, SSQ_RD, 4, 0, 0, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(2); @@ -1803,31 +1803,31 @@ static void adjust_high_timB(ramctr_timing *ctrl) /* DRAM command ACT */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ACT | RANKSEL, + IOSAV_ACT, 1, 1, 3, ctrl->tRCD, SSQ_NA, 0, 6, 0, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* DRAM command NOP */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_NOP | RANKSEL, + IOSAV_NOP, 1, 1, 3, 4, SSQ_WR, 8, 0, 0, slotrank, - ADDR_UPDATE_WRAP(31)); + 0, 0, 0, 0, 31, 0, 0, 0); /* DRAM command WR */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_WR | RANKSEL, + IOSAV_WR, 1, 3, 4, 4, SSQ_WR, 0, 0, 0, slotrank, - ADDR_UPDATE(0, 1, 0, 0, 31, 0, 0, 0)); + 0, 1, 0, 0, 31, 0, 0, 0); /* DRAM command NOP */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_NOP | RANKSEL, + IOSAV_NOP, 1, 1, 3, ctrl->CWL + ctrl->tWTR + 5, SSQ_WR, 8, 0, 0, slotrank, - ADDR_UPDATE_WRAP(31)); + 0, 0, 0, 0, 31, 0, 0, 0); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -1836,26 +1836,26 @@ static void adjust_high_timB(ramctr_timing *ctrl) /* DRAM command PREA */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_PRE | RANKSEL, + IOSAV_PRE, 1, 1, 3, ctrl->tRP, SSQ_NA, 1024, 6, 0, slotrank, - ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); + 0, 0, 0, 0, 18, 0, 0, 0); /* DRAM command ACT */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_ACT | RANKSEL, + IOSAV_ACT, 1, 1, 3, ctrl->tRCD, SSQ_NA, 0, 6, 0, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD | (3 << 16), + IOSAV_RD, 3, 1, 3, ctrl->tRP + ctrl->timings[channel][slotrank].roundtrip_latency + ctrl->timings[channel][slotrank].io_latency, SSQ_RD, 8, 6, 0, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(3); @@ -1888,10 +1888,10 @@ static void write_op(ramctr_timing *ctrl, int channel) /* DRAM command ZQCS */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ZQCS & NO_RANKSEL, + IOSAV_ZQCS, 0, 1, 4, 4, SSQ_NA, 0, 6, 0, slotrank, - ADDR_UPDATE_WRAP(31)); + 0, 0, 0, 0, 31, 0, 0, 0); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); @@ -1967,10 +1967,10 @@ int write_training(ramctr_timing *ctrl) /* DRAM command ZQCS */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ZQCS & NO_RANKSEL, + IOSAV_ZQCS, 0, 1, 36, 101, SSQ_NA, 0, 6, 0, 0, - ADDR_UPDATE_WRAP(31)); + 0, 0, 0, 0, 31, 0, 0, 0); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); @@ -2037,35 +2037,35 @@ static int test_320c(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command ACT */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ACT | RANKSEL, + IOSAV_ACT, 1, 8, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), ctrl->tRCD, SSQ_NA, ctr, 6, 0, slotrank, - ADDR_UPDATE(0, 0, 1, 0, 18, 0, 0, 0)); + 0, 0, 1, 0, 18, 0, 0, 0); /* DRAM command WR */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_WR | RANKSEL, + IOSAV_WR, 1, 32, 4, ctrl->CWL + ctrl->tWTR + 8, SSQ_WR, 0, 0, 0, slotrank, - ADDR_UPDATE(0, 1, 0, 0, 18, 3, 0, 2)); + 0, 1, 0, 0, 18, 3, 0, 2); MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1)) = 0x389abcd; /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD | RANKSEL, + IOSAV_RD, 1, 32, 4, MAX(ctrl->tRTP, 8), SSQ_RD, 0, 0, 0, slotrank, - ADDR_UPDATE(0, 1, 0, 0, 18, 3, 0, 2)); + 0, 1, 0, 0, 18, 3, 0, 2); MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 2)) = 0x389abcd; /* DRAM command PRE */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_PRE | RANKSEL, + IOSAV_PRE, 1, 1, 4, 15, SSQ_NA, 1024, 6, 0, slotrank, - ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); + 0, 0, 0, 0, 18, 0, 0, 0); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -2129,10 +2129,10 @@ static void reprogram_320c(ramctr_timing *ctrl) /* DRAM command ZQCS */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ZQCS & NO_RANKSEL, + IOSAV_ZQCS, 0, 1, 4, 4, SSQ_NA, 0, 6, 0, slotrank, - ADDR_UPDATE_WRAP(31)); + 0, 0, 0, 0, 31, 0, 0, 0); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); @@ -2151,10 +2151,10 @@ static void reprogram_320c(ramctr_timing *ctrl) /* DRAM command ZQCS */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ZQCS & NO_RANKSEL, + IOSAV_ZQCS, 0, 1, 4, 4, SSQ_NA, 0, 6, 0, slotrank, - ADDR_UPDATE_WRAP(31)); + 0, 0, 0, 0, 31, 0, 0, 0); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); @@ -2316,32 +2316,32 @@ static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, i in this mode only RD and RDA are allowed all reads return a predefined pattern */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_MRS | RANKSEL, + IOSAV_MRS, 1, 1, 3, ctrl->tMOD, SSQ_NA, 4, 6, 3, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_RD | RANKSEL, + IOSAV_RD, 1, 500, 4, 4, SSQ_RD, 0, 0, 0, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD | RANKSEL, + IOSAV_RD, 1, 1, 4, ctrl->CAS + 8, SSQ_NA, 0, 6, 0, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* DRAM command MRS MR3 disable MPR */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_MRS | RANKSEL, + IOSAV_MRS, 1, 1, 3, ctrl->tMOD, SSQ_NA, 0, 6, 3, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -2405,32 +2405,32 @@ int discover_edges(ramctr_timing *ctrl) in this mode only RD and RDA are allowed all reads return a predefined pattern */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_MRS | RANKSEL, + IOSAV_MRS, 1, 1, 3, ctrl->tMOD, SSQ_NA, 4, 6, 3, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_RD | RANKSEL, + IOSAV_RD, 1, 3, 4, 4, SSQ_RD, 0, 0, 0, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD | RANKSEL, + IOSAV_RD, 1, 1, 4, ctrl->CAS + 8, SSQ_NA, 0, 6, 0, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* DRAM command MRS * MR3 disable MPR */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_MRS | RANKSEL, + IOSAV_MRS, 1, 1, 3, ctrl->tMOD, SSQ_NA, 0, 6, 3, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -2456,32 +2456,32 @@ int discover_edges(ramctr_timing *ctrl) in this mode only RD and RDA are allowed all reads return a predefined pattern */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_MRS | RANKSEL, + IOSAV_MRS, 1, 1, 3, ctrl->tMOD, SSQ_NA, 4, 6, 3, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_RD | RANKSEL, + IOSAV_RD, 1, 3, 4, 4, SSQ_RD, 0, 0, 0, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD | RANKSEL, + IOSAV_RD, 1, 1, 4, ctrl->CAS + 8, SSQ_NA, 0, 6, 0, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* DRAM command MRS * MR3 disable MPR */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_MRS | RANKSEL, + IOSAV_MRS, 1, 1, 3, ctrl->tMOD, SSQ_NA, 0, 6, 3, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -2585,31 +2585,31 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotr /* DRAM command ACT */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ACT | RANKSEL, + IOSAV_ACT, 1, 4, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), ctrl->tRCD, SSQ_NA, 0, 6, 0, slotrank, - ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); + 0, 0, 0, 0, 18, 0, 0, 0); /* DRAM command WR */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_WR | RANKSEL, + IOSAV_WR, 1, 32, 20, ctrl->tWTR + ctrl->CWL + 8, SSQ_WR, 0, 0, 0, slotrank, - ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); + 0, 1, 0, 0, 18, 0, 0, 0); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD | RANKSEL, + IOSAV_RD, 1, 32, 20, MAX(ctrl->tRTP, 8), SSQ_RD, 0, 0, 0, slotrank, - ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); + 0, 1, 0, 0, 18, 0, 0, 0); /* DRAM command PRE */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_PRE | RANKSEL, + IOSAV_PRE, 1, 1, 3, ctrl->tRP, SSQ_NA, 1024, 6, 0, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -2709,31 +2709,31 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) /* DRAM command ACT */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ACT | RANKSEL, + IOSAV_ACT, 1, 4, MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD), ctrl->tRCD, SSQ_NA, 0, 6, 0, slotrank, - ADDR_UPDATE(0, 0, 1, 0, 18, 0, 0, 0)); + 0, 0, 1, 0, 18, 0, 0, 0); /* DRAM command WR */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_WR | RANKSEL, + IOSAV_WR, 1, 480, 4, ctrl->tWTR + ctrl->CWL + 8, SSQ_WR, 0, 0, 0, slotrank, - ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); + 0, 1, 0, 0, 18, 0, 0, 0); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD | RANKSEL, + IOSAV_RD, 1, 480, 4, MAX(ctrl->tRTP, 8), SSQ_RD, 0, 0, 0, slotrank, - ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); + 0, 1, 0, 0, 18, 0, 0, 0); /* DRAM command PRE */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_PRE | RANKSEL, + IOSAV_PRE, 1, 1, 4, ctrl->tRP, SSQ_NA, 1024, 6, 0, slotrank, - ADDR_UPDATE_NONE); + 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -2926,31 +2926,31 @@ int channel_test(ramctr_timing *ctrl) /* DRAM command ACT */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ACT | RANKSEL, + IOSAV_ACT, 1, 4, 40, 40, SSQ_NA, 0, 6, 0, slotrank, - ADDR_UPDATE(0, 0, 1, 0, 18, 0, 0, 0)); + 0, 0, 1, 0, 18, 0, 0, 0); /* DRAM command WR */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_WR | RANKSEL, + IOSAV_WR, 1, 100, 4, 40, SSQ_WR, 0, 0, 0, slotrank, - ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); + 0, 1, 0, 0, 18, 0, 0, 0); /* DRAM command RD */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD | RANKSEL, + IOSAV_RD, 1, 100, 4, 40, SSQ_RD, 0, 0, 0, slotrank, - ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); + 0, 1, 0, 0, 18, 0, 0, 0); /* DRAM command PRE */ IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_PRE | RANKSEL, + IOSAV_PRE, 1, 1, 3, 40, SSQ_NA, 1024, 6, 0, slotrank, - ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); + 0, 0, 0, 0, 18, 0, 0, 0); /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); @@ -2978,24 +2978,24 @@ void channel_scrub(ramctr_timing *ctrl) /* DRAM command ACT */ IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ACT | RANKSEL, + IOSAV_ACT, 1, 1, MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD), ctrl->tRCD, SSQ_NA, row, 6, 0, slotrank, - ADDR_UPDATE(1, 0, 0, 0, 18, 0, 0, 0)); + 1, 0, 0, 0, 18, 0, 0, 0); /* DRAM command WR */ IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_WR | RANKSEL, + IOSAV_WR, 1, 129, 4, 40, SSQ_WR, row, 0, 0, slotrank, - ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); + 0, 1, 0, 0, 18, 0, 0, 0); /* DRAM command PRE */ IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_PRE | RANKSEL, + IOSAV_PRE, 1, 1, 3, 40, SSQ_NA, 1024, 6, 0, slotrank, - ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); + 0, 0, 0, 0, 18, 0, 0, 0); /* execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(3); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 55b3fc5d5b..c544cdebaf 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -25,8 +25,6 @@ #define NUM_SLOTS 2 #define NUM_LANES 9 -#define NO_RANKSEL (~0) -#define RANKSEL (1 << 16) #define IOSAV_MRS (0xf000) #define IOSAV_PRE (0xf002) #define IOSAV_ZQCS (0xf003) From ad7040051982c986b8559e9cc107a96a017ac82b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 2 May 2020 22:51:58 +0200 Subject: [PATCH 204/405] nb/intel/sandybridge: Refactor IOSAV_RUN_ONCE Turn it into a macro that looks like a function, and add another, more generic `iosav_run_queue` that covers all current use-cases. They will be replaced with functions in a follow-up to preserve reproducibility. Tested with BUILD_TIMELESS=1, ASUS P8Z77-V LX2 remains unchanged. Change-Id: I07b260b5fb111c1408ff75316dc0735a9e642ac9 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40982 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- .../intel/sandybridge/raminit_common.c | 58 ++++++++++--------- 1 file changed, 31 insertions(+), 27 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index ae8fa5f459..96a6189118 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -18,7 +18,11 @@ /* FIXME: no support for 3-channel chipsets */ /* length: [1..4] */ -#define IOSAV_RUN_ONCE(length) ((((length) - 1) << 18) | 1) +/* FIXME: replace with proper functions later */ +#define iosav_run_queue(ch, loops, length, as_timer) \ + MCHBAR32(IOSAV_SEQ_CTL_ch(ch)) = ((loops) | (((length) - 1) << 18) | ((as_timer) << 22)) + +#define iosav_run_once(ch, length) iosav_run_queue(ch, 1, length, 0) static void sfence(void) { @@ -583,7 +587,7 @@ static void write_reset(ramctr_timing *ctrl) * * This is actually using the IOSAV state machine as a timer, so refresh is allowed. */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = (1 << 22) | IOSAV_RUN_ONCE(1); + iosav_run_queue(channel, 1, 1, true); wait_for_iosav(channel); } @@ -686,7 +690,7 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(3); + iosav_run_once(channel, 3); } static u32 make_mr0(ramctr_timing *ctrl, u8 rank) @@ -823,7 +827,7 @@ void dram_mrscommands(ramctr_timing *ctrl) 0, 0, 0, 1, 20, 0, 0, 0); /* Execute command queue on all channels. Do it four times. */ - MCHBAR32(IOSAV_SEQ_CTL) = (1 << 18) | 4; + iosav_run_queue(BROADCAST_CH, 4, 2, false); FOR_ALL_CHANNELS { /* Wait for ref drained */ @@ -851,7 +855,7 @@ void dram_mrscommands(ramctr_timing *ctrl) 0, 0, 0, 0, 31, 0, 0, 0); /* Execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); + iosav_run_once(channel, 1); /* Drain */ wait_for_iosav(channel); @@ -1041,7 +1045,7 @@ static void test_timA(ramctr_timing *ctrl, int channel, int slotrank) 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); + iosav_run_once(channel, 4); wait_for_iosav(channel); } @@ -1307,7 +1311,7 @@ int read_training(ramctr_timing *ctrl) 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); + iosav_run_once(channel, 1); MCHBAR32(GDCRTRAININGMOD) = (slotrank << 2) | 0x8001; @@ -1429,7 +1433,7 @@ static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) 0, 0, 0, 0, 31, 0, 0, 0); /* Execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); + iosav_run_once(channel, 4); wait_for_iosav(channel); @@ -1462,7 +1466,7 @@ static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) 0, 0, 0, 0, 18, 0, 0, 0); /* Execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); + iosav_run_once(channel, 4); wait_for_iosav(channel); } @@ -1502,7 +1506,7 @@ static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) 0, 0, 0, 0, 18, 0, 0, 0); /* Execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); + iosav_run_once(channel, 1); for (timC = 0; timC <= MAX_TIMC; timC++) { FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].timC = timC; @@ -1631,7 +1635,7 @@ static void precharge(ramctr_timing *ctrl) 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); + iosav_run_once(channel, 4); wait_for_iosav(channel); } @@ -1678,7 +1682,7 @@ static void precharge(ramctr_timing *ctrl) 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); + iosav_run_once(channel, 4); wait_for_iosav(channel); } @@ -1706,7 +1710,7 @@ static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(2); + iosav_run_once(channel, 2); wait_for_iosav(channel); @@ -1830,7 +1834,7 @@ static void adjust_high_timB(ramctr_timing *ctrl) 0, 0, 0, 0, 31, 0, 0, 0); /* Execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); + iosav_run_once(channel, 4); wait_for_iosav(channel); @@ -1858,7 +1862,7 @@ static void adjust_high_timB(ramctr_timing *ctrl) 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(3); + iosav_run_once(channel, 3); wait_for_iosav(channel); FOR_ALL_LANES { @@ -1894,7 +1898,7 @@ static void write_op(ramctr_timing *ctrl, int channel) 0, 0, 0, 0, 31, 0, 0, 0); /* Execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); + iosav_run_once(channel, 1); wait_for_iosav(channel); } @@ -1973,7 +1977,7 @@ int write_training(ramctr_timing *ctrl) 0, 0, 0, 0, 31, 0, 0, 0); /* Execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); + iosav_run_once(channel, 1); wait_for_iosav(channel); } @@ -2068,7 +2072,7 @@ static int test_320c(ramctr_timing *ctrl, int channel, int slotrank) 0, 0, 0, 0, 18, 0, 0, 0); /* Execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); + iosav_run_once(channel, 4); wait_for_iosav(channel); FOR_ALL_LANES { @@ -2135,7 +2139,7 @@ static void reprogram_320c(ramctr_timing *ctrl) 0, 0, 0, 0, 31, 0, 0, 0); /* Execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); + iosav_run_once(channel, 1); wait_for_iosav(channel); MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); @@ -2157,7 +2161,7 @@ static void reprogram_320c(ramctr_timing *ctrl) 0, 0, 0, 0, 31, 0, 0, 0); /* Execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); + iosav_run_once(channel, 1); wait_for_iosav(channel); } @@ -2344,7 +2348,7 @@ static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, i 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); + iosav_run_once(channel, 4); wait_for_iosav(channel); @@ -2433,7 +2437,7 @@ int discover_edges(ramctr_timing *ctrl) 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); + iosav_run_once(channel, 4); wait_for_iosav(channel); } @@ -2484,7 +2488,7 @@ int discover_edges(ramctr_timing *ctrl) 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); + iosav_run_once(channel, 4); wait_for_iosav(channel); } @@ -2612,7 +2616,7 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotr 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); + iosav_run_once(channel, 4); wait_for_iosav(channel); FOR_ALL_LANES { @@ -2736,7 +2740,7 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); + iosav_run_once(channel, 4); wait_for_iosav(channel); } @@ -2953,7 +2957,7 @@ int channel_test(ramctr_timing *ctrl) 0, 0, 0, 0, 18, 0, 0, 0); /* Execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); + iosav_run_once(channel, 4); wait_for_iosav(channel); FOR_ALL_LANES @@ -2998,7 +3002,7 @@ void channel_scrub(ramctr_timing *ctrl) 0, 0, 0, 0, 18, 0, 0, 0); /* execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(3); + iosav_run_once(channel, 3); wait_for_iosav(channel); } From e7afcd5391ac6cde9f2e8790be7418893228e5a3 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 2 May 2020 23:14:27 +0200 Subject: [PATCH 205/405] nb/intel/sandybridge: Replace macros with functions Turn `iosav_run_queue` and `iosav_run_once` into functions. Inlining them does not have any effect, as the resulting binary is identical. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I7844814eeedad9b1d24f833a77c90902fa926bfe Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40983 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/northbridge/intel/sandybridge/raminit_common.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 96a6189118..0f42b6f461 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -18,11 +18,15 @@ /* FIXME: no support for 3-channel chipsets */ /* length: [1..4] */ -/* FIXME: replace with proper functions later */ -#define iosav_run_queue(ch, loops, length, as_timer) \ - MCHBAR32(IOSAV_SEQ_CTL_ch(ch)) = ((loops) | (((length) - 1) << 18) | ((as_timer) << 22)) +static void iosav_run_queue(const int ch, const u8 loops, const u8 length, const u8 as_timer) +{ + MCHBAR32(IOSAV_SEQ_CTL_ch(ch)) = loops | ((length - 1) << 18) | (as_timer << 22); +} -#define iosav_run_once(ch, length) iosav_run_queue(ch, 1, length, 0) +static void iosav_run_once(const int ch, const u8 length) +{ + iosav_run_queue(ch, 1, length, 0); +} static void sfence(void) { From 2be59000874eef6829e279ac4f5ec02f35eadf4a Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 2 May 2020 22:15:03 +0200 Subject: [PATCH 206/405] nb/intel/sandybridge: Truncate IOSAV subseq gaps We set bit 15 of IOSAV_n_SUBSEQ_CTRL three times, but it is reserved. Since this bitfield is five bits wide, manually truncate the values so that bit 15 does not get set. Tested on Asus P8Z77-V LX2, still boots. Change-Id: Ib61b026b016b0d22e164f8817158ec5093f6bb9e Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40981 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/sandybridge/raminit_common.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 0f42b6f461..d66a0f0ed3 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -854,7 +854,7 @@ void dram_mrscommands(ramctr_timing *ctrl) /* DRAM command ZQCS */ IOSAV_SUBSEQUENCE(channel, 0, IOSAV_ZQCS, 0, - 1, 36, 101, SSQ_NA, + 1, 4, 101, SSQ_NA, 0, 6, 0, slotrank, 0, 0, 0, 0, 31, 0, 0, 0); @@ -1976,7 +1976,7 @@ int write_training(ramctr_timing *ctrl) /* DRAM command ZQCS */ IOSAV_SUBSEQUENCE(channel, 0, IOSAV_ZQCS, 0, - 1, 36, 101, SSQ_NA, + 1, 4, 101, SSQ_NA, 0, 6, 0, 0, 0, 0, 0, 0, 31, 0, 0, 0); @@ -2935,7 +2935,7 @@ int channel_test(ramctr_timing *ctrl) /* DRAM command ACT */ IOSAV_SUBSEQUENCE(channel, 0, IOSAV_ACT, 1, - 4, 40, 40, SSQ_NA, + 4, 8, 40, SSQ_NA, 0, 6, 0, slotrank, 0, 0, 1, 0, 18, 0, 0, 0); From d5b780c5b1a7f6d7f12d3305dcfd36413a429c39 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 2 May 2020 21:48:46 +0200 Subject: [PATCH 207/405] nb/intel/sandybridge: Redefine IOSAV_SUBSEQUENCE Instead of directly writing values to the IOSAV registers, use a struct and some helper functions to provide a cleaner interface for the IOSAV. Having IOSAV_SUBSEQUENCE refer to a static function is weird, but we will remove this macro in a follow-up that does not change the binary. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I73f13c18a739c5586a7415966f9017c2335fdfd1 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40980 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../intel/sandybridge/mchbar_regs.h | 37 ++++++++++-- .../intel/sandybridge/raminit_common.c | 17 +++++- .../intel/sandybridge/raminit_common.h | 57 +++++++++++++++++++ 3 files changed, 104 insertions(+), 7 deletions(-) diff --git a/src/northbridge/intel/sandybridge/mchbar_regs.h b/src/northbridge/intel/sandybridge/mchbar_regs.h index 446861b4b7..0edfd5354a 100644 --- a/src/northbridge/intel/sandybridge/mchbar_regs.h +++ b/src/northbridge/intel/sandybridge/mchbar_regs.h @@ -213,12 +213,37 @@ ((rate) << 12) | \ ((xors) << 16)) -#define IOSAV_SUBSEQUENCE(ch, n, cmd, ranksel, reps, gap, post, dir, addr, rowbits, bank, rank, addr_1, addr_8, upd_bank, upd_rank, wrap, lfsr, rate, xors) \ - do { \ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(ch, n)) = (cmd) | ((ranksel) << 16); \ - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(ch, n)) = SUBSEQ_CTRL(reps, gap, post, dir); \ - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(ch, n)) = SP_CMD_ADDR(addr, rowbits, bank, rank); \ - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(ch, n)) = ADDR_UPDATE(addr_1, addr_8, upd_bank, upd_rank, wrap, lfsr, rate, xors); \ +#define IOSAV_SUBSEQUENCE(ch, n, cmd, ranksel, reps, gap, post, dir, addr, row_bits, bank_addr, rank_addr, addr_1, addr_8, upd_bank, upd_rank, wrap, lfsr, rate, xors) \ + do { \ + const struct iosav_ssq ssq = { \ + .sp_cmd_ctrl = { \ + .command = cmd, \ + .ranksel_ap = ranksel, \ + }, \ + .subseq_ctrl = { \ + .cmd_executions = reps, \ + .cmd_delay_gap = gap, \ + .post_ssq_wait = post, \ + .data_direction = dir, \ + }, \ + .sp_cmd_addr = { \ + .address = addr, \ + .rowbits = row_bits, \ + .bank = bank_addr, \ + .rank = rank_addr, \ + }, \ + .addr_update = { \ + .inc_addr_1 = addr_1, \ + .inc_addr_8 = addr_8, \ + .inc_bank = upd_bank, \ + .inc_rank = upd_rank, \ + .addr_wrap = wrap, \ + .lfsr_upd = lfsr, \ + .upd_rate = rate, \ + .lfsr_xors = xors, \ + }, \ + }; \ + iosav_write_ssq(ch, n, &ssq); \ } while (0) /* Indexed register helper macros */ diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index d66a0f0ed3..c4bf5ff50e 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -17,10 +17,25 @@ /* FIXME: no support for 3-channel chipsets */ +/* Number of programmed IOSAV subsequences. */ +static unsigned int ssq_count = 0; + +static void iosav_write_ssq(const int ch, const int n, const struct iosav_ssq *ssq) +{ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(ch, ssq_count)) = ssq->sp_cmd_ctrl.raw; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(ch, ssq_count)) = ssq->subseq_ctrl.raw; + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(ch, ssq_count)) = ssq->sp_cmd_addr.raw; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(ch, ssq_count)) = ssq->addr_update.raw; + + ssq_count++; +} + /* length: [1..4] */ static void iosav_run_queue(const int ch, const u8 loops, const u8 length, const u8 as_timer) { - MCHBAR32(IOSAV_SEQ_CTL_ch(ch)) = loops | ((length - 1) << 18) | (as_timer << 22); + MCHBAR32(IOSAV_SEQ_CTL_ch(ch)) = loops | ((ssq_count - 1) << 18) | (as_timer << 22); + + ssq_count = 0; } static void iosav_run_once(const int ch, const u8 length) diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index c544cdebaf..6e76cbc0bb 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -34,6 +34,63 @@ #define IOSAV_WR (0xf201) #define IOSAV_NOP (0xf207) +struct iosav_ssq { + /* IOSAV_n_SP_CMD_CTRL */ + union { + struct { + u32 command : 16; + u32 ranksel_ap : 2; + u32 : 14; + }; + u32 raw; + } sp_cmd_ctrl; + + /* IOSAV_n_SUBSEQ_CTRL */ + union { + struct { + u32 cmd_executions : 9; + u32 : 1; + u32 cmd_delay_gap : 5; + u32 : 1; + u32 post_ssq_wait : 9; + u32 : 1; + u32 data_direction : 2; + u32 : 4; + }; + u32 raw; + } subseq_ctrl; + + /* IOSAV_n_SP_CMD_ADDR */ + union { + struct { + u32 address : 16; + u32 rowbits : 3; + u32 : 1; + u32 bank : 3; + u32 : 1; + u32 rank : 2; + u32 : 6; + }; + u32 raw; + } sp_cmd_addr; + + /* IOSAV_n_ADDR_UPDATE */ + union { + struct { + u32 inc_addr_1 : 1; + u32 inc_addr_8 : 1; + u32 inc_bank : 1; + u32 inc_rank : 2; + u32 addr_wrap : 5; + u32 lfsr_upd : 2; + u32 upd_rate : 4; + u32 lfsr_xors : 2; + u32 : 14; + }; + u32 raw; + } addr_update; +}; + /* FIXME: Vendor BIOS uses 64 but our algorithms are less performant and even 1 seems to be enough in practice. */ #define NUM_PATTERNS 4 From 38d901e88dcb6e8f20af3c66c69978732c2b71f1 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 2 May 2020 23:50:43 +0200 Subject: [PATCH 208/405] nb/intel/sandybridge: Drop unused parameters We now use a static variable to handle the sequence length. Tested on Asus P8Z77-V LX2, still boots. Change-Id: Id3115c14336ea128264bd3945a99c52b9796d115 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40984 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../intel/sandybridge/mchbar_regs.h | 2 +- .../intel/sandybridge/raminit_common.c | 61 +++++++++---------- 2 files changed, 31 insertions(+), 32 deletions(-) diff --git a/src/northbridge/intel/sandybridge/mchbar_regs.h b/src/northbridge/intel/sandybridge/mchbar_regs.h index 0edfd5354a..742c499433 100644 --- a/src/northbridge/intel/sandybridge/mchbar_regs.h +++ b/src/northbridge/intel/sandybridge/mchbar_regs.h @@ -243,7 +243,7 @@ .lfsr_xors = xors, \ }, \ }; \ - iosav_write_ssq(ch, n, &ssq); \ + iosav_write_ssq(ch, &ssq); \ } while (0) /* Indexed register helper macros */ diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index c4bf5ff50e..b5d337dc74 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -20,7 +20,7 @@ /* Number of programmed IOSAV subsequences. */ static unsigned int ssq_count = 0; -static void iosav_write_ssq(const int ch, const int n, const struct iosav_ssq *ssq) +static void iosav_write_ssq(const int ch, const struct iosav_ssq *ssq) { MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(ch, ssq_count)) = ssq->sp_cmd_ctrl.raw; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(ch, ssq_count)) = ssq->subseq_ctrl.raw; @@ -30,17 +30,16 @@ static void iosav_write_ssq(const int ch, const int n, const struct iosav_ssq *s ssq_count++; } -/* length: [1..4] */ -static void iosav_run_queue(const int ch, const u8 loops, const u8 length, const u8 as_timer) +static void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer) { MCHBAR32(IOSAV_SEQ_CTL_ch(ch)) = loops | ((ssq_count - 1) << 18) | (as_timer << 22); ssq_count = 0; } -static void iosav_run_once(const int ch, const u8 length) +static void iosav_run_once(const int ch) { - iosav_run_queue(ch, 1, length, 0); + iosav_run_queue(ch, 1, 0); } static void sfence(void) @@ -606,7 +605,7 @@ static void write_reset(ramctr_timing *ctrl) * * This is actually using the IOSAV state machine as a timer, so refresh is allowed. */ - iosav_run_queue(channel, 1, 1, true); + iosav_run_queue(channel, 1, 1); wait_for_iosav(channel); } @@ -709,7 +708,7 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ - iosav_run_once(channel, 3); + iosav_run_once(channel); } static u32 make_mr0(ramctr_timing *ctrl, u8 rank) @@ -846,7 +845,7 @@ void dram_mrscommands(ramctr_timing *ctrl) 0, 0, 0, 1, 20, 0, 0, 0); /* Execute command queue on all channels. Do it four times. */ - iosav_run_queue(BROADCAST_CH, 4, 2, false); + iosav_run_queue(BROADCAST_CH, 4, 0); FOR_ALL_CHANNELS { /* Wait for ref drained */ @@ -874,7 +873,7 @@ void dram_mrscommands(ramctr_timing *ctrl) 0, 0, 0, 0, 31, 0, 0, 0); /* Execute command queue */ - iosav_run_once(channel, 1); + iosav_run_once(channel); /* Drain */ wait_for_iosav(channel); @@ -1064,7 +1063,7 @@ static void test_timA(ramctr_timing *ctrl, int channel, int slotrank) 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ - iosav_run_once(channel, 4); + iosav_run_once(channel); wait_for_iosav(channel); } @@ -1330,7 +1329,7 @@ int read_training(ramctr_timing *ctrl) 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ - iosav_run_once(channel, 1); + iosav_run_once(channel); MCHBAR32(GDCRTRAININGMOD) = (slotrank << 2) | 0x8001; @@ -1452,7 +1451,7 @@ static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) 0, 0, 0, 0, 31, 0, 0, 0); /* Execute command queue */ - iosav_run_once(channel, 4); + iosav_run_once(channel); wait_for_iosav(channel); @@ -1485,7 +1484,7 @@ static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) 0, 0, 0, 0, 18, 0, 0, 0); /* Execute command queue */ - iosav_run_once(channel, 4); + iosav_run_once(channel); wait_for_iosav(channel); } @@ -1525,7 +1524,7 @@ static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) 0, 0, 0, 0, 18, 0, 0, 0); /* Execute command queue */ - iosav_run_once(channel, 1); + iosav_run_once(channel); for (timC = 0; timC <= MAX_TIMC; timC++) { FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].timC = timC; @@ -1654,7 +1653,7 @@ static void precharge(ramctr_timing *ctrl) 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ - iosav_run_once(channel, 4); + iosav_run_once(channel); wait_for_iosav(channel); } @@ -1701,7 +1700,7 @@ static void precharge(ramctr_timing *ctrl) 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ - iosav_run_once(channel, 4); + iosav_run_once(channel); wait_for_iosav(channel); } @@ -1729,7 +1728,7 @@ static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ - iosav_run_once(channel, 2); + iosav_run_once(channel); wait_for_iosav(channel); @@ -1853,7 +1852,7 @@ static void adjust_high_timB(ramctr_timing *ctrl) 0, 0, 0, 0, 31, 0, 0, 0); /* Execute command queue */ - iosav_run_once(channel, 4); + iosav_run_once(channel); wait_for_iosav(channel); @@ -1881,7 +1880,7 @@ static void adjust_high_timB(ramctr_timing *ctrl) 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ - iosav_run_once(channel, 3); + iosav_run_once(channel); wait_for_iosav(channel); FOR_ALL_LANES { @@ -1917,7 +1916,7 @@ static void write_op(ramctr_timing *ctrl, int channel) 0, 0, 0, 0, 31, 0, 0, 0); /* Execute command queue */ - iosav_run_once(channel, 1); + iosav_run_once(channel); wait_for_iosav(channel); } @@ -1996,7 +1995,7 @@ int write_training(ramctr_timing *ctrl) 0, 0, 0, 0, 31, 0, 0, 0); /* Execute command queue */ - iosav_run_once(channel, 1); + iosav_run_once(channel); wait_for_iosav(channel); } @@ -2091,7 +2090,7 @@ static int test_320c(ramctr_timing *ctrl, int channel, int slotrank) 0, 0, 0, 0, 18, 0, 0, 0); /* Execute command queue */ - iosav_run_once(channel, 4); + iosav_run_once(channel); wait_for_iosav(channel); FOR_ALL_LANES { @@ -2158,7 +2157,7 @@ static void reprogram_320c(ramctr_timing *ctrl) 0, 0, 0, 0, 31, 0, 0, 0); /* Execute command queue */ - iosav_run_once(channel, 1); + iosav_run_once(channel); wait_for_iosav(channel); MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); @@ -2180,7 +2179,7 @@ static void reprogram_320c(ramctr_timing *ctrl) 0, 0, 0, 0, 31, 0, 0, 0); /* Execute command queue */ - iosav_run_once(channel, 1); + iosav_run_once(channel); wait_for_iosav(channel); } @@ -2367,7 +2366,7 @@ static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, i 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ - iosav_run_once(channel, 4); + iosav_run_once(channel); wait_for_iosav(channel); @@ -2456,7 +2455,7 @@ int discover_edges(ramctr_timing *ctrl) 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ - iosav_run_once(channel, 4); + iosav_run_once(channel); wait_for_iosav(channel); } @@ -2507,7 +2506,7 @@ int discover_edges(ramctr_timing *ctrl) 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ - iosav_run_once(channel, 4); + iosav_run_once(channel); wait_for_iosav(channel); } @@ -2635,7 +2634,7 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotr 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ - iosav_run_once(channel, 4); + iosav_run_once(channel); wait_for_iosav(channel); FOR_ALL_LANES { @@ -2759,7 +2758,7 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) 0, 0, 0, 0, 0, 0, 0, 0); /* Execute command queue */ - iosav_run_once(channel, 4); + iosav_run_once(channel); wait_for_iosav(channel); } @@ -2976,7 +2975,7 @@ int channel_test(ramctr_timing *ctrl) 0, 0, 0, 0, 18, 0, 0, 0); /* Execute command queue */ - iosav_run_once(channel, 4); + iosav_run_once(channel); wait_for_iosav(channel); FOR_ALL_LANES @@ -3021,7 +3020,7 @@ void channel_scrub(ramctr_timing *ctrl) 0, 0, 0, 0, 18, 0, 0, 0); /* execute command queue */ - iosav_run_once(channel, 3); + iosav_run_once(channel); wait_for_iosav(channel); } From 3abd206d4f67fe8e25403b74fdd69a5a4392597f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 3 May 2020 00:25:02 +0200 Subject: [PATCH 209/405] nb/intel/sandybridge: Use the new IOSAV struct API Now that we have created the IOSAV API, we can put it to good use. Drop all the helper macros and replace them with struct constructs. Tested with BUILD_TIMELESS=1, ASUS P8Z77-V LX2 remains unchanged. Change-Id: Ib366e364df11c9bb240cdfbce418540ec715c634 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41003 Reviewed-by: Arthur Heymans Reviewed-by: Paul Menzel Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- .../intel/sandybridge/mchbar_regs.h | 58 - .../intel/sandybridge/raminit_common.c | 2138 +++++++++++++---- .../intel/sandybridge/raminit_common.h | 7 + 3 files changed, 1740 insertions(+), 463 deletions(-) diff --git a/src/northbridge/intel/sandybridge/mchbar_regs.h b/src/northbridge/intel/sandybridge/mchbar_regs.h index 742c499433..849a8927a6 100644 --- a/src/northbridge/intel/sandybridge/mchbar_regs.h +++ b/src/northbridge/intel/sandybridge/mchbar_regs.h @@ -188,64 +188,6 @@ * [6] Cleared with a new sequence, and set when done and refresh counter is drained. */ -/* Temporary IOSAV register macros to verifiably split bitfields */ -#define SUBSEQ_CTRL(reps, gap, post, dir) (((reps) << 0) | \ - ((gap) << 10) | \ - ((post) << 16) | \ - ((dir) << 26)) - -#define SSQ_NA 0 /* Non-data */ -#define SSQ_RD 1 /* Read */ -#define SSQ_WR 2 /* Write */ -#define SSQ_RW 3 /* Read and write */ - -#define SP_CMD_ADDR(addr, rowbits, bank, rank) (((addr) << 0) | \ - ((rowbits) << 16) | \ - ((bank) << 20) | \ - ((rank) << 24)) - -#define ADDR_UPDATE(addr_1, addr_8, bank, rank, wrap, lfsr, rate, xors) (((addr_1) << 0) | \ - ((addr_8) << 1) | \ - ((bank) << 2) | \ - ((rank) << 3) | \ - ((wrap) << 5) | \ - ((lfsr) << 10) | \ - ((rate) << 12) | \ - ((xors) << 16)) - -#define IOSAV_SUBSEQUENCE(ch, n, cmd, ranksel, reps, gap, post, dir, addr, row_bits, bank_addr, rank_addr, addr_1, addr_8, upd_bank, upd_rank, wrap, lfsr, rate, xors) \ - do { \ - const struct iosav_ssq ssq = { \ - .sp_cmd_ctrl = { \ - .command = cmd, \ - .ranksel_ap = ranksel, \ - }, \ - .subseq_ctrl = { \ - .cmd_executions = reps, \ - .cmd_delay_gap = gap, \ - .post_ssq_wait = post, \ - .data_direction = dir, \ - }, \ - .sp_cmd_addr = { \ - .address = addr, \ - .rowbits = row_bits, \ - .bank = bank_addr, \ - .rank = rank_addr, \ - }, \ - .addr_update = { \ - .inc_addr_1 = addr_1, \ - .inc_addr_8 = addr_8, \ - .inc_bank = upd_bank, \ - .inc_rank = upd_rank, \ - .addr_wrap = wrap, \ - .lfsr_upd = lfsr, \ - .upd_rate = rate, \ - .lfsr_xors = xors, \ - }, \ - }; \ - iosav_write_ssq(ch, &ssq); \ - } while (0) - /* Indexed register helper macros */ #define Gz(r, z) ((r) + ((z) << 8)) #define Ly(r, y) ((r) + ((y) << 2)) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index b5d337dc74..371527e9ef 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -594,11 +594,26 @@ static void write_reset(ramctr_timing *ctrl) slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; /* DRAM command ZQCS */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ZQCS, 0, - 1, 3, 8, SSQ_NA, - 0, 6, 0, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_ZQCS, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = 8, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* * Execute command queue - why is bit 22 set here?! @@ -687,25 +702,71 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, } /* DRAM command MRS */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_MRS, 0, - 1, 4, 4, SSQ_NA, - val, 6, reg, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 4, + .post_ssq_wait = 4, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = val, + .rowbits = 6, + .bank = reg, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command MRS */ - IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_MRS, 1, - 1, 4, 4, SSQ_NA, - val, 6, reg, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 4, + .post_ssq_wait = 4, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = val, + .rowbits = 6, + .bank = reg, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command MRS */ - IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_MRS, 0, - 1, 4, ctrl->tMOD, SSQ_NA, - val, 6, reg, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 4, + .post_ssq_wait = ctrl->tMOD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = val, + .rowbits = 6, + .bank = reg, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* Execute command queue */ iosav_run_once(channel); @@ -831,18 +892,53 @@ void dram_mrscommands(ramctr_timing *ctrl) } /* DRAM command NOP (without ODT nor chip selects) */ - IOSAV_SUBSEQUENCE(BROADCAST_CH, 0, - IOSAV_NOP & ~(0xff << 8), 0, - 1, 4, 15, SSQ_NA, - 2, 6, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_NOP & ~(0xff << 8), + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 4, + .post_ssq_wait = 15, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 2, + .rowbits = 6, + .bank = 0, + .rank = 0, + }, + }; + iosav_write_ssq(BROADCAST_CH, &ssq); + } /* DRAM command ZQCL */ - IOSAV_SUBSEQUENCE(BROADCAST_CH, 1, - IOSAV_ZQCS, 1, - 1, 4, 400, SSQ_NA, - 1024, 6, 0, 0, - 0, 0, 0, 1, 20, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_ZQCS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 4, + .post_ssq_wait = 400, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = 0, + }, + .addr_update = { + .inc_rank = 1, + .addr_wrap = 20, + }, + }; + iosav_write_ssq(BROADCAST_CH, &ssq); + } /* Execute command queue on all channels. Do it four times. */ iosav_run_queue(BROADCAST_CH, 4, 0); @@ -866,11 +962,29 @@ void dram_mrscommands(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command ZQCS */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ZQCS, 0, - 1, 4, 101, SSQ_NA, - 0, 6, 0, slotrank, - 0, 0, 0, 0, 31, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_ZQCS, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 4, + .post_ssq_wait = 101, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 31, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* Execute command queue */ iosav_run_once(channel); @@ -1030,37 +1144,106 @@ static void test_timA(ramctr_timing *ctrl, int channel, int slotrank) { wait_for_iosav(channel); - /* DRAM command MRS - write MR3 MPR enable - in this mode only RD and RDA are allowed - all reads return a predefined pattern */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_MRS, 1, - 1, 3, ctrl->tMOD, SSQ_NA, - 4, 6, 3, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + /* + * DRAM command MRS + * + * Write MR3 MPR enable. + * In this mode only RD and RDA are allowed, and all reads return a predefined pattern. + */ + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tMOD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 4, + .rowbits = 6, + .bank = 3, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command RD */ - IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_RD, 1, - 1, 3, 4, SSQ_RD, - 0, 0, 0, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = 4, + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command RD */ - IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD, 1, - 15, 4, ctrl->CAS + 36, SSQ_NA, - 0, 6, 0, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 15, + .cmd_delay_gap = 4, + .post_ssq_wait = ctrl->CAS + 36, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } - /* DRAM command MRS - write MR3 MPR disable */ - IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_MRS, 1, - 1, 3, ctrl->tMOD, SSQ_NA, - 0, 6, 3, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + /* + * DRAM command MRS + * + * Write MR3 MPR disable. + */ + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tMOD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 3, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* Execute command queue */ iosav_run_once(channel); @@ -1322,11 +1505,27 @@ int read_training(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command PREA */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_PRE, 1, - 1, 3, ctrl->tRP, SSQ_NA, - 1024, 6, 0, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tRP, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* Execute command queue */ iosav_run_once(channel); @@ -1423,32 +1622,110 @@ static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command ACT */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ACT, 1, - 4, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), ctrl->tRCD, SSQ_NA, - 0, 6, 0, slotrank, - 0, 0, 1, 0, 18, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_ACT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 4, + .cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), + .post_ssq_wait = ctrl->tRCD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_bank = 1, + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command NOP */ - IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_NOP, 1, - 1, 4, 4, SSQ_WR, - 8, 0, 0, slotrank, - 0, 0, 0, 0, 31, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_NOP, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 4, + .post_ssq_wait = 4, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 8, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 31, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command WR */ - IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_WR, 1, - 500, 4, 4, SSQ_WR, - 0, 0, 0, slotrank, - 0, 1, 0, 0, 18, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_WR, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 500, + .cmd_delay_gap = 4, + .post_ssq_wait = 4, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command NOP */ - IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_NOP, 1, - 1, 3, ctrl->CWL + ctrl->tWTR + 5, SSQ_WR, - 8, 0, 0, slotrank, - 0, 0, 0, 0, 31, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_NOP, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->CWL + ctrl->tWTR + 5, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 8, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 31, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* Execute command queue */ iosav_run_once(channel); @@ -1456,32 +1733,110 @@ static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command PREA */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_PRE, 1, - 1, 3, ctrl->tRP, SSQ_NA, - 1024, 6, 0, slotrank, - 0, 0, 0, 0, 18, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tRP, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command ACT */ - IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_ACT, 1, - 8, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), ctrl->CAS, SSQ_NA, - 0, 6, 0, slotrank, - 0, 0, 1, 0, 18, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_ACT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 8, + .cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), + .post_ssq_wait = ctrl->CAS, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_bank = 1, + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command RD */ - IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD, 1, - 500, 4, MAX(ctrl->tRTP, 8), SSQ_RD, - 0, 0, 0, slotrank, - 0, 1, 0, 0, 18, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 500, + .cmd_delay_gap = 4, + .post_ssq_wait = MAX(ctrl->tRTP, 8), + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command PREA */ - IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_PRE, 1, - 1, 3, ctrl->tRP, SSQ_NA, - 1024, 6, 0, slotrank, - 0, 0, 0, 0, 18, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tRP, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* Execute command queue */ iosav_run_once(channel); @@ -1517,11 +1872,30 @@ static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command PREA */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_PRE, 1, - 1, 3, ctrl->tRP, SSQ_NA, - 1024, 6, 0, slotrank, - 0, 0, 0, 0, 18, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tRP, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* Execute command queue */ iosav_run_once(channel); @@ -1620,37 +1994,107 @@ static void precharge(ramctr_timing *ctrl) FOR_ALL_POPULATED_RANKS { wait_for_iosav(channel); - /* DRAM command MRS - write MR3 MPR enable - in this mode only RD and RDA are allowed - all reads return a predefined pattern */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_MRS, 1, - 1, 3, ctrl->tMOD, SSQ_NA, - 4, 6, 3, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + /* + * DRAM command MRS + * + * Write MR3 MPR enable. + * In this mode only RD and RDA are allowed, + * and all reads return a predefined pattern. + */ + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tMOD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 4, + .rowbits = 6, + .bank = 3, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command RD */ - IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_RD, 1, - 3, 4, 4, SSQ_RD, - 0, 0, 0, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 3, + .cmd_delay_gap = 4, + .post_ssq_wait = 4, + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command RD */ - IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD, 1, - 1, 4, ctrl->CAS + 8, SSQ_NA, - 0, 6, 0, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 4, + .post_ssq_wait = ctrl->CAS + 8, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } - /* DRAM command MRS - * write MR3 MPR disable */ - IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_MRS, 1, - 1, 3, ctrl->tMOD, SSQ_NA, - 0, 6, 3, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + /* + * DRAM command MRS + * + * Write MR3 MPR disable. + */ + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tMOD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 3, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* Execute command queue */ iosav_run_once(channel); @@ -1667,37 +2111,108 @@ static void precharge(ramctr_timing *ctrl) FOR_ALL_POPULATED_RANKS { wait_for_iosav(channel); - /* DRAM command MRS - * write MR3 MPR enable - * in this mode only RD and RDA are allowed - * all reads return a predefined pattern */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_MRS, 1, - 1, 3, ctrl->tMOD, SSQ_NA, - 4, 6, 3, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + + /* + * DRAM command MRS + * + * Write MR3 MPR enable. + * In this mode only RD and RDA are allowed, + * and all reads return a predefined pattern. + */ + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tMOD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 4, + .rowbits = 6, + .bank = 3, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command RD */ - IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_RD, 1, - 3, 4, 4, SSQ_RD, - 0, 0, 0, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 3, + .cmd_delay_gap = 4, + .post_ssq_wait = 4, + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command RD */ - IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD, 1, - 1, 4, ctrl->CAS + 8, SSQ_NA, - 0, 6, 0, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 4, + .post_ssq_wait = ctrl->CAS + 8, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } - /* DRAM command MRS - * write MR3 MPR disable */ - IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_MRS, 1, - 1, 3, ctrl->tMOD, SSQ_NA, - 0, 6, 3, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + /* + * DRAM command MRS + * + * Write MR3 MPR disable. + */ + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tMOD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 3, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* Execute command queue */ iosav_run_once(channel); @@ -1714,18 +2229,50 @@ static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command NOP */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_NOP, 1, - 1, 3, ctrl->CWL + ctrl->tWLO, SSQ_WR, - 8, 0, 0, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_NOP, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->CWL + ctrl->tWLO, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 8, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command NOP */ - IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_NOP_ALT, 1, - 1, 3, ctrl->CAS + 38, SSQ_RD, - 4, 0, 0, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_NOP_ALT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->CAS + 38, + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 4, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* Execute command queue */ iosav_run_once(channel); @@ -1824,32 +2371,106 @@ static void adjust_high_timB(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command ACT */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ACT, 1, - 1, 3, ctrl->tRCD, SSQ_NA, - 0, 6, 0, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_ACT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tRCD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command NOP */ - IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_NOP, 1, - 1, 3, 4, SSQ_WR, - 8, 0, 0, slotrank, - 0, 0, 0, 0, 31, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_NOP, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = 4, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 8, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 31, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command WR */ - IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_WR, 1, - 3, 4, 4, SSQ_WR, - 0, 0, 0, slotrank, - 0, 1, 0, 0, 31, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_WR, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 3, + .cmd_delay_gap = 4, + .post_ssq_wait = 4, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 31, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command NOP */ - IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_NOP, 1, - 1, 3, ctrl->CWL + ctrl->tWTR + 5, SSQ_WR, - 8, 0, 0, slotrank, - 0, 0, 0, 0, 31, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_NOP, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->CWL + ctrl->tWTR + 5, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 8, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 31, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* Execute command queue */ iosav_run_once(channel); @@ -1857,27 +2478,78 @@ static void adjust_high_timB(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command PREA */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_PRE, 1, - 1, 3, ctrl->tRP, SSQ_NA, - 1024, 6, 0, slotrank, - 0, 0, 0, 0, 18, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tRP, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command ACT */ - IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_ACT, 1, - 1, 3, ctrl->tRCD, SSQ_NA, - 0, 6, 0, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_ACT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tRCD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command RD */ - IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD, 3, - 1, 3, ctrl->tRP + + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 3, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tRP + ctrl->timings[channel][slotrank].roundtrip_latency + - ctrl->timings[channel][slotrank].io_latency, SSQ_RD, - 8, 6, 0, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + ctrl->timings[channel][slotrank].io_latency, + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 8, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* Execute command queue */ iosav_run_once(channel); @@ -1909,11 +2581,29 @@ static void write_op(ramctr_timing *ctrl, int channel) slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ZQCS */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ZQCS, 0, - 1, 4, 4, SSQ_NA, - 0, 6, 0, slotrank, - 0, 0, 0, 0, 31, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_ZQCS, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 4, + .post_ssq_wait = 4, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 31, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* Execute command queue */ iosav_run_once(channel); @@ -1988,11 +2678,29 @@ int write_training(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command ZQCS */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ZQCS, 0, - 1, 4, 101, SSQ_NA, - 0, 6, 0, 0, - 0, 0, 0, 0, 31, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_ZQCS, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 4, + .post_ssq_wait = 101, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = 0, + }, + .addr_update = { + .addr_wrap = 31, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* Execute command queue */ iosav_run_once(channel); @@ -2058,36 +2766,120 @@ static int test_320c(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command ACT */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ACT, 1, - 8, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), ctrl->tRCD, SSQ_NA, - ctr, 6, 0, slotrank, - 0, 0, 1, 0, 18, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_ACT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 8, + .cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), + .post_ssq_wait = ctrl->tRCD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = ctr, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_bank = 1, + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command WR */ - IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_WR, 1, - 32, 4, ctrl->CWL + ctrl->tWTR + 8, SSQ_WR, - 0, 0, 0, slotrank, - 0, 1, 0, 0, 18, 3, 0, 2); - + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_WR, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 32, + .cmd_delay_gap = 4, + .post_ssq_wait = ctrl->CWL + ctrl->tWTR + 8, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + .lfsr_upd = 3, + .lfsr_xors = 2, + }, + }; + iosav_write_ssq(channel, &ssq); + } + /* FIXME: Hardcoded subsequence index */ MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1)) = 0x389abcd; /* DRAM command RD */ - IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD, 1, - 32, 4, MAX(ctrl->tRTP, 8), SSQ_RD, - 0, 0, 0, slotrank, - 0, 1, 0, 0, 18, 3, 0, 2); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 32, + .cmd_delay_gap = 4, + .post_ssq_wait = MAX(ctrl->tRTP, 8), + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + .lfsr_upd = 3, + .lfsr_xors = 2, + }, + }; + iosav_write_ssq(channel, &ssq); + } + /* FIXME: Hardcoded subsequence index */ MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 2)) = 0x389abcd; /* DRAM command PRE */ - IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_PRE, 1, - 1, 4, 15, SSQ_NA, - 1024, 6, 0, slotrank, - 0, 0, 0, 0, 18, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 4, + .post_ssq_wait = 15, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* Execute command queue */ iosav_run_once(channel); @@ -2150,11 +2942,29 @@ static void reprogram_320c(ramctr_timing *ctrl) slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ZQCS */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ZQCS, 0, - 1, 4, 4, SSQ_NA, - 0, 6, 0, slotrank, - 0, 0, 0, 0, 31, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_ZQCS, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 4, + .post_ssq_wait = 4, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 31, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* Execute command queue */ iosav_run_once(channel); @@ -2172,11 +2982,29 @@ static void reprogram_320c(ramctr_timing *ctrl) slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ZQCS */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ZQCS, 0, - 1, 4, 4, SSQ_NA, - 0, 6, 0, slotrank, - 0, 0, 0, 0, 31, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_ZQCS, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 4, + .post_ssq_wait = 4, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 31, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* Execute command queue */ iosav_run_once(channel); @@ -2333,37 +3161,107 @@ static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, i wait_for_iosav(channel); - /* DRAM command MRS - write MR3 MPR enable - in this mode only RD and RDA are allowed - all reads return a predefined pattern */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_MRS, 1, - 1, 3, ctrl->tMOD, SSQ_NA, - 4, 6, 3, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + /* + * DRAM command MRS + * + * Write MR3 MPR enable. + * In this mode only RD and RDA are allowed, + * and all reads return a predefined pattern. + */ + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tMOD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 4, + .rowbits = 6, + .bank = 3, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command RD */ - IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_RD, 1, - 500, 4, 4, SSQ_RD, - 0, 0, 0, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 500, + .cmd_delay_gap = 4, + .post_ssq_wait = 4, + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command RD */ - IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD, 1, - 1, 4, ctrl->CAS + 8, SSQ_NA, - 0, 6, 0, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 4, + .post_ssq_wait = ctrl->CAS + 8, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } - /* DRAM command MRS - MR3 disable MPR */ - IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_MRS, 1, - 1, 3, ctrl->tMOD, SSQ_NA, - 0, 6, 3, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + /* + * DRAM command MRS + * + * Write MR3 MPR disable. + */ + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tMOD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 3, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* Execute command queue */ iosav_run_once(channel); @@ -2421,38 +3319,107 @@ int discover_edges(ramctr_timing *ctrl) FOR_ALL_POPULATED_RANKS { wait_for_iosav(channel); - /* DRAM command MRS - MR3 enable MPR - write MR3 MPR enable - in this mode only RD and RDA are allowed - all reads return a predefined pattern */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_MRS, 1, - 1, 3, ctrl->tMOD, SSQ_NA, - 4, 6, 3, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + /* + * DRAM command MRS + * + * Write MR3 MPR enable. + * In this mode only RD and RDA are allowed, + * and all reads return a predefined pattern. + */ + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tMOD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 4, + .rowbits = 6, + .bank = 3, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command RD */ - IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_RD, 1, - 3, 4, 4, SSQ_RD, - 0, 0, 0, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 3, + .cmd_delay_gap = 4, + .post_ssq_wait = 4, + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command RD */ - IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD, 1, - 1, 4, ctrl->CAS + 8, SSQ_NA, - 0, 6, 0, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 4, + .post_ssq_wait = ctrl->CAS + 8, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } - /* DRAM command MRS - * MR3 disable MPR */ - IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_MRS, 1, - 1, 3, ctrl->tMOD, SSQ_NA, - 0, 6, 3, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + /* + * DRAM command MRS + * + * Write MR3 MPR disable. + */ + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tMOD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 3, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* Execute command queue */ iosav_run_once(channel); @@ -2472,38 +3439,107 @@ int discover_edges(ramctr_timing *ctrl) FOR_ALL_POPULATED_RANKS { wait_for_iosav(channel); - /* DRAM command MRS - MR3 enable MPR - write MR3 MPR enable - in this mode only RD and RDA are allowed - all reads return a predefined pattern */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_MRS, 1, - 1, 3, ctrl->tMOD, SSQ_NA, - 4, 6, 3, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + /* + * DRAM command MRS + * + * Write MR3 MPR enable. + * In this mode only RD and RDA are allowed, + * and all reads return a predefined pattern. + */ + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tMOD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 4, + .rowbits = 6, + .bank = 3, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command RD */ - IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_RD, 1, - 3, 4, 4, SSQ_RD, - 0, 0, 0, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 3, + .cmd_delay_gap = 4, + .post_ssq_wait = 4, + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command RD */ - IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD, 1, - 1, 4, ctrl->CAS + 8, SSQ_NA, - 0, 6, 0, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 4, + .post_ssq_wait = ctrl->CAS + 8, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } - /* DRAM command MRS - * MR3 disable MPR */ - IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_MRS, 1, - 1, 3, ctrl->tMOD, SSQ_NA, - 0, 6, 3, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + /* + * DRAM command MRS + * + * Write MR3 MPR disable. + */ + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tMOD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 3, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* Execute command queue */ iosav_run_once(channel); @@ -2606,32 +3642,109 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotr wait_for_iosav(channel); /* DRAM command ACT */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ACT, 1, - 4, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), ctrl->tRCD, SSQ_NA, - 0, 6, 0, slotrank, - 0, 0, 0, 0, 18, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_ACT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 4, + .cmd_delay_gap = MAX(ctrl->tRRD, + (ctrl->tFAW >> 2) + 1), + .post_ssq_wait = ctrl->tRCD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command WR */ - IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_WR, 1, - 32, 20, ctrl->tWTR + ctrl->CWL + 8, SSQ_WR, - 0, 0, 0, slotrank, - 0, 1, 0, 0, 18, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_WR, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 32, + .cmd_delay_gap = 20, + .post_ssq_wait = ctrl->tWTR + + ctrl->CWL + 8, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command RD */ - IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD, 1, - 32, 20, MAX(ctrl->tRTP, 8), SSQ_RD, - 0, 0, 0, slotrank, - 0, 1, 0, 0, 18, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 32, + .cmd_delay_gap = 20, + .post_ssq_wait = MAX(ctrl->tRTP, 8), + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command PRE */ - IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_PRE, 1, - 1, 3, ctrl->tRP, SSQ_NA, - 1024, 6, 0, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tRP, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* Execute command queue */ iosav_run_once(channel); @@ -2730,32 +3843,108 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* DRAM command ACT */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ACT, 1, - 4, MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD), ctrl->tRCD, SSQ_NA, - 0, 6, 0, slotrank, - 0, 0, 1, 0, 18, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_ACT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 4, + .cmd_delay_gap = MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD), + .post_ssq_wait = ctrl->tRCD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_bank = 1, + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command WR */ - IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_WR, 1, - 480, 4, ctrl->tWTR + ctrl->CWL + 8, SSQ_WR, - 0, 0, 0, slotrank, - 0, 1, 0, 0, 18, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_WR, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 480, + .cmd_delay_gap = 4, + .post_ssq_wait = ctrl->tWTR + ctrl->CWL + 8, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command RD */ - IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD, 1, - 480, 4, MAX(ctrl->tRTP, 8), SSQ_RD, - 0, 0, 0, slotrank, - 0, 1, 0, 0, 18, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 480, + .cmd_delay_gap = 4, + .post_ssq_wait = MAX(ctrl->tRTP, 8), + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command PRE */ - IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_PRE, 1, - 1, 4, ctrl->tRP, SSQ_NA, - 1024, 6, 0, slotrank, - 0, 0, 0, 0, 0, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 4, + .post_ssq_wait = ctrl->tRP, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* Execute command queue */ iosav_run_once(channel); @@ -2947,32 +4136,111 @@ int channel_test(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command ACT */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ACT, 1, - 4, 8, 40, SSQ_NA, - 0, 6, 0, slotrank, - 0, 0, 1, 0, 18, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_ACT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 4, + .cmd_delay_gap = 8, + .post_ssq_wait = 40, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_bank = 1, + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command WR */ - IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_WR, 1, - 100, 4, 40, SSQ_WR, - 0, 0, 0, slotrank, - 0, 1, 0, 0, 18, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_WR, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 100, + .cmd_delay_gap = 4, + .post_ssq_wait = 40, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command RD */ - IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_RD, 1, - 100, 4, 40, SSQ_RD, - 0, 0, 0, slotrank, - 0, 1, 0, 0, 18, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 100, + .cmd_delay_gap = 4, + .post_ssq_wait = 40, + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command PRE */ - IOSAV_SUBSEQUENCE(channel, 3, - IOSAV_PRE, 1, - 1, 3, 40, SSQ_NA, - 1024, 6, 0, slotrank, - 0, 0, 0, 0, 18, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = 40, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* Execute command queue */ iosav_run_once(channel); @@ -2999,25 +4267,85 @@ void channel_scrub(ramctr_timing *ctrl) wait_for_iosav(channel); /* DRAM command ACT */ - IOSAV_SUBSEQUENCE(channel, 0, - IOSAV_ACT, 1, - 1, MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD), ctrl->tRCD, SSQ_NA, - row, 6, 0, slotrank, - 1, 0, 0, 0, 18, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_ACT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = MAX((ctrl->tFAW >> 2) + 1, + ctrl->tRRD), + .post_ssq_wait = ctrl->tRCD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = row, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_1 = 1, + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command WR */ - IOSAV_SUBSEQUENCE(channel, 1, - IOSAV_WR, 1, - 129, 4, 40, SSQ_WR, - row, 0, 0, slotrank, - 0, 1, 0, 0, 18, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_WR, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 129, + .cmd_delay_gap = 4, + .post_ssq_wait = 40, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = row, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* DRAM command PRE */ - IOSAV_SUBSEQUENCE(channel, 2, - IOSAV_PRE, 1, - 1, 3, 40, SSQ_NA, - 1024, 6, 0, slotrank, - 0, 0, 0, 0, 18, 0, 0, 0); + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = 40, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } /* execute command queue */ iosav_run_once(channel); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 6e76cbc0bb..3f31950408 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -25,6 +25,7 @@ #define NUM_SLOTS 2 #define NUM_LANES 9 +/* IOSAV_n_SP_CMD_CTRL DRAM commands */ #define IOSAV_MRS (0xf000) #define IOSAV_PRE (0xf002) #define IOSAV_ZQCS (0xf003) @@ -34,6 +35,12 @@ #define IOSAV_WR (0xf201) #define IOSAV_NOP (0xf207) +/* IOSAV_n_SUBSEQ_CTRL data direction */ +#define SSQ_NA 0 /* Non-data */ +#define SSQ_RD 1 /* Read */ +#define SSQ_WR 2 /* Write */ +#define SSQ_RW 3 /* Read and write */ + struct iosav_ssq { /* IOSAV_n_SP_CMD_CTRL */ union { From 77f6627a199e145adc492207f8b4bb4df5388b2b Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Wed, 20 May 2020 14:27:27 -0600 Subject: [PATCH 210/405] ec/google/chromeec/i2c_tunnel: Fix missing const This was missed in the refactor. BUG=b:157140753 TEST=Built trembyle Signed-off-by: Raul E Rangel Change-Id: I150e0b8a806042ef8001805eaefbce71dc1be0e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41574 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c b/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c index 77f6fe11fe..ec8bdfc2bf 100644 --- a/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c +++ b/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c @@ -11,7 +11,7 @@ #define CROS_EC_I2C_TUNNEL_HID "GOOG0012" #define CROS_EC_I2C_TUNNEL_DDN "Cros EC I2C Tunnel" -static void crosec_i2c_tunnel_fill_ssdt(struct device *dev) +static void crosec_i2c_tunnel_fill_ssdt(const struct device *dev) { const char *scope = acpi_device_scope(dev); struct ec_google_chromeec_i2c_tunnel_config *cfg = dev->chip_info; From 4732f23a1f488c1fe31363a94ad990bc097547ae Mon Sep 17 00:00:00 2001 From: Yu-Hsuan Hsu Date: Wed, 15 Jan 2020 16:17:24 +0800 Subject: [PATCH 211/405] ec/google/chromeec/acpi: Add CROS EC CODEC device This is currently used by trembyle. Add it in a common location so other boards can use it. BUG=b:147200751 BRANCH=none TEST=Able to get ec codec on trembyle Change-Id: Ie21cd813b0e3129f1c61d2de199532b25d3c70fa Signed-off-by: Yu-Hsuan Hsu Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2000271 Reviewed-by: Raul E Rangel Reviewed-by: Martin Roth Commit-Queue: Martin Roth Tested-by: Martin Roth Reviewed-on: https://review.coreboot.org/c/coreboot/+/41575 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/ec/google/chromeec/acpi/codec.asl | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 src/ec/google/chromeec/acpi/codec.asl diff --git a/src/ec/google/chromeec/acpi/codec.asl b/src/ec/google/chromeec/acpi/codec.asl new file mode 100644 index 0000000000..14d8d0cab5 --- /dev/null +++ b/src/ec/google/chromeec/acpi/codec.asl @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (ECOD) +{ + Name (_HID, "GOOG0013") + Name (_UID, 1) + Name (_DDN, "CROS EC CODEC") +} From 5df9a04640cf6ab97fab06ac2822c9a2640325b2 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 15 Apr 2020 22:52:35 -0700 Subject: [PATCH 212/405] soc/amd/picasso/pci_devs: Update pci_devs.h with correct values This is a squash of the following commits. The original values were wrong, and had confusing naming. soc/amd/picasso: Get rid of *_DEVID from pci_devs.h Signed-off-by: Furquan Shaikh Original-Change-Id: I203449499840bf0a6df8bd879fb7d2e75a16b284 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2153714 src/amd/picasso: Update PCI bridge devices Orignal-Change-Id: I1fa9d52ce113eacdc5c9ba31ab46b6428a7d6ca9 Signed-off-by: Marshall Dawson Zork: Reorganizing ACPI and adding PCI bridge configs Signed-off-by: Pranay Shoroff Original-Change-Id: I1e2095567525f302dfd0bce8e39001250523180b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2063536 soc/amd/picasso: Fix soc_acpi_name() to use devfn instead of devid Signed-off-by: Furquan Shaikh Original-Change-Id: I2486e7e0059e0528f53d5a158c9328636563fe93 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2153712 BUG=b:147042464 TEST=Build trembyle and boot to OS Signed-off-by: Raul E Rangel Change-Id: I91bf7f9edcddf03027f8fdcaadf4e290ece10df5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41542 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Felix Held --- src/soc/amd/picasso/chip.c | 75 ++++++++---- src/soc/amd/picasso/include/soc/pci_devs.h | 136 +++++++++------------ 2 files changed, 107 insertions(+), 104 deletions(-) diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 5c5b79d136..26dcbfb9df 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -50,30 +51,58 @@ const char *soc_acpi_name(const struct device *dev) if (dev->path.type != DEVICE_PATH_PCI) return NULL; - switch (dev->path.pci.devfn) { - case PCIE0_DEVFN: - return "PBR4"; - case PCIE1_DEVFN: - return "PBR5"; - case PCIE2_DEVFN: - return "PBR6"; - case PCIE3_DEVFN: - return "PBR7"; - case PCIE4_DEVFN: - return "PBR8"; - case HDA1_DEVFN: - return "AZHD"; - case LPC_DEVFN: - return "LPCB"; - case SMBUS_DEVFN: - return "SBUS"; - case XHCI0_DEVFN: - return "XHC0"; - case XHCI1_DEVFN: - return "XHC1"; - default: - return NULL; + if (dev->bus->dev->path.type == DEVICE_PATH_DOMAIN) { + switch (dev->path.pci.devfn) { + case GNB_DEVFN: + return "GNB"; + case IOMMU_DEVFN: + return "IOMM"; + case PCIE_GPP_0_DEVFN: + return "PBR0"; + case PCIE_GPP_1_DEVFN: + return "PBR1"; + case PCIE_GPP_2_DEVFN: + return "PBR2"; + case PCIE_GPP_3_DEVFN: + return "PBR3"; + case PCIE_GPP_4_DEVFN: + return "PBR4"; + case PCIE_GPP_5_DEVFN: + return "PBR5"; + case PCIE_GPP_6_DEVFN: + return "PBR6"; + case PCIE_GPP_A_DEVFN: + return "PBRA"; + case PCIE_GPP_B_DEVFN: + return "PBRB"; + case LPC_DEVFN: + return "LPCB"; + case SMBUS_DEVFN: + return "SBUS"; + default: + printk(BIOS_WARNING, "Unknown root PCI device: dev: %d, fn: %d\n", + PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn)); + return NULL; + } } + + if (dev->bus->dev->path.type == DEVICE_PATH_PCI + && dev->bus->dev->path.pci.devfn == PCIE_GPP_A_DEVFN) { + switch (dev->path.pci.devfn) { + case XHCI0_DEVFN: + return "XHC0"; + case XHCI1_DEVFN: + return "XHC1"; + default: + printk(BIOS_WARNING, "Unknown Bus A PCI device: dev: %d, fn: %d\n", + PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn)); + return NULL; + } + } + + printk(BIOS_WARNING, "Unknown PCI device: dev: %d, fn: %d\n", + PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn)); + return NULL; }; struct device_operations pci_domain_ops = { diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index 282d86ce09..27334f1462 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -15,79 +15,78 @@ /* GNB Root Complex */ #define GNB_DEV 0x0 #define GNB_FUNC 0 -#define GNB_DEVID 0x1576 #define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC) #define SOC_GNB_DEV _SOC_DEV(GNB_DEV, GNB_FUNC) /* IOMMU */ #define IOMMU_DEV 0x0 #define IOMMU_FUNC 2 -#define IOMMU_DEVID 0x1577 #define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC) #define SOC_IOMMU_DEV _SOC_DEV(IOMMU_DEV, IOMMU_FUNC) -/* Internal Graphics */ -#define GFX_DEV 0x1 -#define GFX_FUNC 0 -#define GFX_DEVID 0x15d8 -#define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) -#define SOC_GFX_DEV _SOC_DEV(GFX_DEV, GFX_FUNC) +/* PCIe GPP Bridges 0 - 6 */ +#define PCIE_HOST_BRIDGE_06_DEV 0x1 -/* HD Audio 0 */ -#define HDA0_DEV 0x1 -#define HDA0_FUNC 1 -#define HDA0_DEVID 0x15b3 -#define HDA0_DEVFN PCI_DEVFN(HDA0_DEV, HDA0_FUNC) -#define SOC_HDA0_DEV _SOC_DEV(HDA0_DEV, HDA0_FUNC) +#define PCIE_GPP_0_FUNC 1 +#define PCIE_GPP_0_DEVFN PCI_DEVFN(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_0_FUNC) +#define SOC_GPP_0_DEV _SOC_DEV(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_0_FUNC) -/* Host Bridge */ -#define HOST_DEV 0x2 -#define HOST_FUNC 0 -#define HOST_DEVID 0x157b -#define HOST_DEVFN PCI_DEVFN(HOST_DEV, HOST_FUNC) -#define SOC_HOST_DEV _SOC_DEV(HOST_DEV, HOST_FUNC) +#define PCIE_GPP_1_FUNC 2 +#define PCIE_GPP_1_DEVFN PCI_DEVFN(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_1_FUNC) +#define SOC_GPP_1_DEV _SOC_DEV(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_1_FUNC) -/* PCIe GPP Bridge 0 */ -#define PCIE0_DEV 0x2 -#define PCIE0_FUNC 1 -#define PCIE0_DEVID 0x157c -#define PCIE0_DEVFN PCI_DEVFN(PCIE0_DEV, PCIE0_FUNC) -#define SOC_PCIE0_DEV _SOC_DEV(PCIE0_DEV, PCIE0_FUNC) +#define PCIE_GPP_2_FUNC 3 +#define PCIE_GPP_2_DEVFN PCI_DEVFN(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_2_FUNC) +#define SOC_GPP_2_DEV _SOC_DEV(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_2_FUNC) -/* PCIe GPP Bridge 1 */ -#define PCIE1_DEV 0x2 -#define PCIE1_FUNC 2 -#define PCIE1_DEVID 0x157c -#define PCIE1_DEVFN PCI_DEVFN(PCIE1_DEV, PCIE1_FUNC) -#define SOC_PCIE1_DEV _SOC_DEV(PCIE1_DEV, PCIE1_FUNC) +#define PCIE_GPP_3_FUNC 4 +#define PCIE_GPP_3_DEVFN PCI_DEVFN(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_3_FUNC) +#define SOC_GPP_3_DEV _SOC_DEV(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_3_FUNC) -/* PCIe GPP Bridge 2 */ -#define PCIE2_DEV 0x2 -#define PCIE2_FUNC 3 -#define PCIE2_DEVID 0x157c -#define PCIE2_DEVFN PCI_DEVFN(PCIE2_DEV, PCIE2_FUNC) -#define SOC_PCIE2_DEV _SOC_DEV(PCIE2_DEV, PCIE2_FUNC) +#define PCIE_GPP_4_FUNC 5 +#define PCIE_GPP_4_DEVFN PCI_DEVFN(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_4_FUNC) +#define SOC_GPP_4_DEV _SOC_DEV(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_4_FUNC) -/* PCIe GPP Bridge 3 */ -#define PCIE3_DEV 0x2 -#define PCIE3_FUNC 4 -#define PCIE3_DEVID 0x157c -#define PCIE3_DEVFN PCI_DEVFN(PCIE3_DEV, PCIE3_FUNC) -#define SOC_PCIE3_DEV _SOC_DEV(PCIE3_DEV, PCIE3_FUNC) +#define PCIE_GPP_5_FUNC 6 +#define PCIE_GPP_5_DEVFN PCI_DEVFN(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_5_FUNC) +#define SOC_GPP_5_DEV _SOC_DEV(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_5_FUNC) -/* PCIe GPP Bridge 4 */ -#define PCIE4_DEV 0x2 -#define PCIE4_FUNC 5 -#define PCIE4_DEVID 0x157c -#define PCIE4_DEVFN PCI_DEVFN(PCIE4_DEV, PCIE4_FUNC) -#define SOC_PCIE4_DEV _SOC_DEV(PCIE4_DEV, PCIE4_FUNC) +#define PCIE_GPP_6_FUNC 7 +#define PCIE_GPP_6_DEVFN PCI_DEVFN(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_6_FUNC) +#define SOC_GPP_6_DEV _SOC_DEV(PCIE_HOST_BRIDGE_06_DEV, PCIE_GPP_6_FUNC) -/* HD Audio 1 */ -#define HDA1_DEV 0x9 -#define HDA1_FUNC 2 -#define HDA1_DEVID 0x157a -#define HDA1_DEVFN PCI_DEVFN(HDA1_DEV, HDA1_FUNC) -#define SOC_HDA1_DEV _SOC_DEV(HDA1_DEV, HDA1_FUNC) +/* PCIe GPP Bridges to Bus A and Bus B devices */ +#define PCIE_HOST_BRIDGE_AB_DEV 0x8 + +#define PCIE_GPP_A_FUNC 1 +#define PCIE_GPP_A_DEVFN PCI_DEVFN(PCIE_HOST_BRIDGE_AB_DEV, PCIE_GPP_A_FUNC) +#define SOC_PCIE_GPP_A_DEV _SOC_DEV(PCIE_HOST_BRIDGE_AB_DEV, PCIE_GPP_A_FUNC) +#define GFX_DEV 0x0 +#define GFX_FUNC 0 +#define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) + +#define XHCI0_DEV 0x0 +#define XHCI0_FUNC 3 +#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC) + +#define XHCI1_DEV 0x0 +#define XHCI1_FUNC 4 +#define XHCI1_DEVFN PCI_DEVFN(XHCI1_DEV, XHCI1_FUNC) + +#define AUDIO_DEV 0x0 +#define AUDIO_FUNC 5 +#define AUDIO_DEVFN PCI_DEVFN(AUDIO_DEV, AUDIO_FUNC) + +#define HD_AUDIO_DEV 0x0 +#define HD_AUDIO_FUNC 6 +#define HD_AUDIO_DEVFN PCI_DEVFN(HD_AUDIO_DEV, HD_AUDIO_FUNC) + +#define PCIE_GPP_B_FUNC 2 +#define PCIE_GPP_B_DEVFN PCI_DEVFN(PCIE_HOST_BRIDGE_AB_DEV, PCIE_GPP_B_FUNC) +#define SOC_PCIE_GPP_B_DEV _SOC_DEV(PCIE_HOST_BRIDGE_AB_DEV, PCIE_GPP_B_FUNC) +#define SATA_DEV 0x0 +#define SATA_FUNC 0 +#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) /* Data Fabric functions */ #define DF_DEV 0x18 @@ -113,40 +112,15 @@ #define DF_F6_DEVFN PCI_DEVFN(DF_DEV, 6) #define SOC_DF_F6_DEV _SOC_DEV(DF_DEV, 6) -/* USB 3.1 */ -#define XHCI0_DEV 0x0 -#define XHCI0_FUNC 3 -#define XHCI0_DEVID 0x15e0 -#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC) -#define SOC_XHCI0_DEV _SOC_DEV(XHCI0_DEV, XHCI0_FUNC) - -/* USB 3.1 */ -#define XHCI1_DEV 0x0 -#define XHCI1_FUNC 4 -#define XHCI1_DEVID 0x15e1 -#define XHCI1_DEVFN PCI_DEVFN(XHCI1_DEV, XHCI1_FUNC) -#define SOC_XHCI1_DEV _SOC_DEV(XHCI1_DEV, XHCI1_FUNC) - -/* SATA */ -#define SATA_DEV 0x11 -#define SATA_FUNC 0 -#define SATA_IDE_DEVID 0x7900 -#define AHCI_DEVID_MS 0x7901 -#define AHCI_DEVID_AMD 0x7904 -#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) -#define SOC_SATA_DEV _SOC_DEV(SATA_DEV, SATA_FUNC) - /* SMBUS */ #define SMBUS_DEV 0x14 #define SMBUS_FUNC 0 -#define SMBUS_DEVID 0x790b #define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) #define SOC_SMBUS_DEV _SOC_DEV(SMBUS_DEV, SMBUS_FUNC) /* LPC BUS */ #define PCU_DEV 0x14 #define LPC_FUNC 3 -#define LPC_DEVID 0x790e #define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC) #define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC) From 6de79b9a1dedfb36e30a932f300de4ad8a5d27b4 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Tue, 19 May 2020 16:13:06 -0600 Subject: [PATCH 213/405] soc/amd/picasso/chip.c: Generate ACPI nodes for PCI Bridge A and B This node is required so we can add child ACPI nodes. BUG=b:147042464 TEST=Boot trembyle and confirm Bus A has a firmware node $ cat /sys/bus/pci/devices/0000\:00\:08.1/firmware_node/path \_SB_.PCI0.PBRA Signed-off-by: Raul E Rangel Change-Id: I18144a69ed28a913bc9a2523d69edf84a1402e7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41546 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/amd/picasso/chip.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 26dcbfb9df..f5936646d2 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -112,18 +112,35 @@ struct device_operations pci_domain_ops = { .acpi_name = soc_acpi_name, }; +static struct device_operations pci_ops_ops_bus_ab = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .acpi_fill_ssdt = acpi_device_write_pci_dev, +}; + static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) + if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; - else if (dev->path.type == DEVICE_PATH_PCI) + } else if (dev->path.type == DEVICE_PATH_PCI) { + if (dev->bus->dev->path.type == DEVICE_PATH_DOMAIN) { + switch (dev->path.pci.devfn) { + case PCIE_GPP_A_DEVFN: + case PCIE_GPP_B_DEVFN: + dev->ops = &pci_ops_ops_bus_ab; + } + } sb_enable(dev); - else if (dev->path.type == DEVICE_PATH_MMIO) + } else if (dev->path.type == DEVICE_PATH_MMIO) { if (i2c_acpi_name(dev) != NULL) dev->ops = &picasso_i2c_mmio_ops; + } } static void soc_init(void *chip_info) From 30ce0f383f2f3cf47e3f8cef2ea4ce2f7b478be9 Mon Sep 17 00:00:00 2001 From: Rob Barnes Date: Thu, 5 Mar 2020 13:09:32 -0700 Subject: [PATCH 214/405] util/amdfwtool: Fix MAX_PSP_ENTRIES value Had to increase MAX_PSP_ENTRIES to accommodate the 16 APCBs we have the ability to add. BUG=b:150862063 TEST=Boot Trembyle BRANCH=None Signed-off-by: Rob Barnes Change-Id: I64eccfa28839768788f53327caf187a564842162 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2090323 Reviewed-by: Raul E Rangel Reviewed-on: https://review.coreboot.org/c/coreboot/+/41580 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- util/amdfwtool/amdfwtool.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 42c63f1cf1..71da6fb7f2 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -479,7 +479,7 @@ typedef struct _bios_directory_table { bios_directory_entry entries[]; } bios_directory_table; -#define MAX_BIOS_ENTRIES 0x22 +#define MAX_BIOS_ENTRIES 0x2e typedef struct _context { char *rom; /* target buffer, size of flash device */ From 712311f56e2f9fec0124ca7903078dc180abf81c Mon Sep 17 00:00:00 2001 From: Peichao Wang Date: Sat, 18 Apr 2020 08:25:53 +0800 Subject: [PATCH 215/405] soc/amd/common/block/gpio: add API for gpio override table This function adds support for gpio_configure_pads_with_override which: 1. Takes as input two GPIO tables -- base config table and override config table 2. Configures each pad in base config by first checking if there is a config available for the pad in override config table. If yes, then uses the one from override config table. Else, uses the base config to configure the pad. BUG=b:153456574 TEST=Build and boot dalboz BRANCH=none Signed-off-by: peichao.wang Change-Id: I07bfe82827d1f7aea9fcc96574d6deab9e91d503 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2153423 Reviewed-by: Furquan Shaikh Commit-Queue: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41576 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/gpio_banks/gpio.c | 33 +++++++++++++++++++ .../block/include/amdblocks/gpio_banks.h | 15 +++++++++ 2 files changed, 48 insertions(+) diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 2d4558f17f..81ea72528c 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -294,3 +294,36 @@ int gpio_interrupt_status(gpio_t gpio) return 0; } + +/* + * This function checks to see if there is an override config present for the + * provided pad_config. If no override config is present, then the input config + * is returned. Else, it returns the override config. + */ +static const struct soc_amd_gpio *gpio_get_config(const struct soc_amd_gpio *c, + const struct soc_amd_gpio *override_cfg_table, + size_t num) +{ + size_t i; + if (override_cfg_table == NULL) + return c; + for (i = 0; i < num; i++) { + if (c->gpio == override_cfg_table[i].gpio) + return override_cfg_table + i; + } + return c; +} +void gpio_configure_pads_with_override(const struct soc_amd_gpio *base_cfg, + size_t base_num_pads, + const struct soc_amd_gpio *override_cfg, + size_t override_num_pads) +{ + size_t i; + const struct soc_amd_gpio *c; + + for (i = 0; i < base_num_pads; i++) { + c = gpio_get_config(base_cfg + i, override_cfg, + override_num_pads); + program_gpios(c, 1); + } +} diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h index b603e2ddd1..572e639f70 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h @@ -276,6 +276,21 @@ enum { typedef uint32_t gpio_t; +/* + * gpio_configure_pads_with_override accepts as input two GPIO tables: + * 1. Base config + * 2. Override config + * + * This function configures raw pads in base config and applies override in + * override config if any. Thus, for every GPIO_x in base config, this function + * looks up the GPIO in override config and if it is present there, then applies + * the configuration from override config. + */ +void gpio_configure_pads_with_override(const struct soc_amd_gpio *base_cfg, + size_t base_num_pads, + const struct soc_amd_gpio *override_cfg, + size_t override_num_pads); + /* Get the address of the control register of a particular pin */ uintptr_t gpio_get_address(gpio_t gpio_num); From 105e02d4fd99dba55d603d010802eebdebeee535 Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Tue, 12 May 2020 12:13:07 -0700 Subject: [PATCH 216/405] mb/google/volteer: fix error in generic SPD The SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex SPD contained an incorrect SDRAM Max Cycle Time (0 instead of 0x0f). After fixing that error, I noticed that two generic SPDs could be collapsed into one, so I removed one of the duplicate generic SPDs (SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_16Row_DDP_4267.spd.hex), and changed Makefile to collapse volteer's DRAM ID 2 into ID 0. BUG=b:156126658, b:156058720 TEST=Flash and boot a ripto to kernel. Also verified that ripto can boot successfully to the kernel at 4267 MT/sec with FSP built in debug mode with RMT enabled. Change-Id: Ib52bf674ebf91854d3d078015aa640aa7ee98a6f Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/41345 Reviewed-by: Caveh Jalali Reviewed-by: Tim Wawrzynczak Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- ...R4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex | 2 +- ...R4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex | 2 +- .../volteer/variants/volteer/Makefile.inc | 6 ++-- ...SPD_LPDDR4X_200b_1R_16Gb_DDP_4267.spd.hex} | 2 +- ...R4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex | 32 ------------------- 5 files changed, 6 insertions(+), 38 deletions(-) rename src/mainboard/google/volteer/variants/volteer/spd/{SPD_LPDDR4X_200b_1R_16Gb_16Row_DDP_4267.spd.hex => SPD_LPDDR4X_200b_1R_16Gb_DDP_4267.spd.hex} (96%) delete mode 100644 src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex diff --git a/src/mainboard/google/volteer/variants/malefor/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex b/src/mainboard/google/volteer/variants/malefor/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex index 94f258e1e9..1ead4c5405 100644 --- a/src/mainboard/google/volteer/variants/malefor/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex +++ b/src/mainboard/google/volteer/variants/malefor/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex @@ -1,5 +1,5 @@ 23 11 11 0E 15 21 95 08 00 00 00 00 02 01 00 00 -48 00 04 00 92 55 00 00 8C 00 90 A8 90 C0 08 60 +48 00 04 0F 92 55 00 00 8C 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/variants/ripto/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex b/src/mainboard/google/volteer/variants/ripto/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex index 94f258e1e9..1ead4c5405 100644 --- a/src/mainboard/google/volteer/variants/ripto/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex +++ b/src/mainboard/google/volteer/variants/ripto/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex @@ -1,5 +1,5 @@ 23 11 11 0E 15 21 95 08 00 00 00 00 02 01 00 00 -48 00 04 00 92 55 00 00 8C 00 90 A8 90 C0 08 60 +48 00 04 0F 92 55 00 00 8C 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/variants/volteer/Makefile.inc b/src/mainboard/google/volteer/variants/volteer/Makefile.inc index 5b97e8d729..07dbef7b88 100644 --- a/src/mainboard/google/volteer/variants/volteer/Makefile.inc +++ b/src/mainboard/google/volteer/variants/volteer/Makefile.inc @@ -2,8 +2,8 @@ ## ## Memory Options # DRAM ID # Part Num -SPD_SOURCES = SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267 # 0b0000 # K4U6E3S4AA-MGCL +SPD_SOURCES = SPD_LPDDR4X_200b_1R_16Gb_DDP_4267 # 0b0000 # K4U6E3S4AA-MGCL + # H9HCNNNBKMMLXR-NEE SPD_SOURCES += SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267 # 0b0001 # K4UBE3D4AA-MGCL -SPD_SOURCES += SPD_LPDDR4X_200b_1R_16Gb_16Row_DDP_4267 # 0b0010 # H9HCNNNBKMMLXR-NEE +SPD_SOURCES += SPD_LPDDR4X_200b_2R_32Gb_QDP_4267 # 0b0010 # MT53E1G32D2NP-046 WT:A SPD_SOURCES += SPD_LPDDR4X_200b_2R_64Gb_ODP_4267 # 0b0011 # H9HCNNNFAMMLXR-NEE -SPD_SOURCES += SPD_LPDDR4X_200b_2R_32Gb_QDP_4267 # 0b0100 # MT53E1G32D2NP-046 WT:A diff --git a/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_1R_16Gb_16Row_DDP_4267.spd.hex b/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_1R_16Gb_DDP_4267.spd.hex similarity index 96% rename from src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_1R_16Gb_16Row_DDP_4267.spd.hex rename to src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_1R_16Gb_DDP_4267.spd.hex index 9ec70a9878..1ead4c5405 100644 --- a/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_1R_16Gb_16Row_DDP_4267.spd.hex +++ b/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_1R_16Gb_DDP_4267.spd.hex @@ -1,5 +1,5 @@ 23 11 11 0E 15 21 95 08 00 00 00 00 02 01 00 00 -48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 +48 00 04 0F 92 55 00 00 8C 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex b/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex deleted file mode 100644 index 94f258e1e9..0000000000 --- a/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 11 0E 15 21 95 08 00 00 00 00 02 01 00 00 -48 00 04 00 92 55 00 00 8C 00 90 A8 90 C0 08 60 -04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 From 47b5a9820f2f95fda349f298054ca40cc2149548 Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Thu, 21 May 2020 10:54:55 -0700 Subject: [PATCH 217/405] mb/google/volteer: set DRAM Max Cycle Time to 15 The DRAM Max Cycle Time (tCKmax) for Samsung's K4UBE3D4AA-MGCL DRAM part should be set to 0xF. BUG=b:157178553, b:156555863 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot a SKU4 volteer to the kernel and run "memtester 6G 100" and verify it completes successfully without error and does not crash. Change-Id: Id95b19fe261e3f57a52a43055acab99af66b14ab Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/41634 Reviewed-by: Tim Wawrzynczak Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- .../spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex b/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex index 90202f983c..778967d5e7 100644 --- a/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex +++ b/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex @@ -1,5 +1,5 @@ 23 11 11 0E 15 21 B5 08 00 00 00 00 0A 01 00 00 -48 00 04 00 92 54 05 00 87 00 90 A8 90 C0 08 60 +48 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 From 526880754faa1246e97e0bd1d836ecc1738e8c90 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 29 Apr 2020 12:19:50 -0700 Subject: [PATCH 218/405] soc/intel/tigerlake: Add definition for PMC EPOC The PMC EPOC register indicates which external crystal oscillator is connected to the PCH. This frequency is important for determining the IP clock of internal PCH devices. Add definitions that allow this register to be read and extract the crystal frequency, and a helper function to extract and return this as the defined enum. BUG=b:146482091 Signed-off-by: Duncan Laurie Change-Id: I959fe507f3dbf93b6176b333a9e725ed09f56328 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40887 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/include/soc/pmc.h | 24 +++++++++++++++++++++++ src/soc/intel/tigerlake/pmc.c | 7 +++++++ 2 files changed, 31 insertions(+) diff --git a/src/soc/intel/tigerlake/include/soc/pmc.h b/src/soc/intel/tigerlake/include/soc/pmc.h index 0f72833fbe..b7a97cc824 100644 --- a/src/soc/intel/tigerlake/include/soc/pmc.h +++ b/src/soc/intel/tigerlake/include/soc/pmc.h @@ -101,6 +101,30 @@ extern struct device_operations pmc_ops; #define PCH2CPU_TPR_CFG_LOCK (1 << 31) #define PCH2CPU_TT_EN (1 << 26) +#define PCH_PMC_EPOC 0x18EC +#define PCH_EPOC_2LM(__epoc) ((__epoc) & 0x1) +/* XTAL frequency in bits 21, 20, 17 */ +#define PCH_EPOC_XTAL_FREQ(__epoc) ((((__epoc) >> 19) & 0x6) | ((__epoc) >> 17 & 0x1)) + +/** + * enum pch_pmc_xtal - External crystal oscillator frequency. + * @XTAL_24_MHZ: 24 MHz external crystal. + * @XTAL_19_2_MHZ: 19.2 MHz external crystal. + * @XTAL_38_4_MHZ: 38.4 MHz external crystal. + */ +enum pch_pmc_xtal { + XTAL_24_MHZ, + XTAL_19_2_MHZ, + XTAL_38_4_MHZ, +}; + +/** + * pmc_get_xtal_freq() - Return frequency of external oscillator. + * + * Return &enum pch_pmc_xtal corredsponding to frequency returned by PMC. + */ +enum pch_pmc_xtal pmc_get_xtal_freq(void); + #define PCH_PWRM_ACPI_TMR_CTL 0x18FC #define GPIO_GPE_CFG 0x1920 #define GPE0_DWX_MASK 0xf diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 2d30424cd0..62e37114f3 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -17,6 +17,13 @@ #include #include +enum pch_pmc_xtal pmc_get_xtal_freq(void) +{ + uint8_t *const pmcbase = pmc_mmio_regs(); + + return PCH_EPOC_XTAL_FREQ(read32(pmcbase + PCH_PMC_EPOC)); +} + static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) { uint32_t reg; From c2891f15fdc1a18220477485e2fe2f8a84a51bc2 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 29 Apr 2020 12:34:38 -0700 Subject: [PATCH 219/405] drivers/intel/soundwire: Add Intel SoundWire controller driver This driver provides support for Intel SoundWire controllers. It is intended to be used by multiple Intel SoCs and relies on retrieving controller/master information from the SoC itself. As such it provides a function that must be implemented by the SoC to fill out this structure. The Intel SoundWire driver in the Linux kernel expects firmware to inform it which master links are unused by adding a custom property to the link descriptor. This is done by looking for any children attached to the device that use each link and disabling the ones that are unused. Mainboards will enable this driver and define the controller in devicetree.cb in order provide the required ACPI tables, but the mainboard should not need to provide any configuration itself as that should all come from the SoC directly. This was tested with the volteer board by adding this controller and a codec to devicetree.cb and ensuring that the properties are all present, including the custom properties for the device clock and quirk mask for disabled links. Device (SNDW) { Name (_ADR, 0x40000003) Name (_CID, Package () { "PRP0001", "PNP0A05" }) Name (_DDN, "Intel SoundWire Controller") Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-sw-interface-revision", 0x00010000 }, Package () { "mipi-sdw-master-count", 0x04 } }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package () { Package () { "mipi-sdw-link-0-subproperties", "LNK0" }, Package () { "mipi-sdw-link-1-subproperties", "LNK1" }, Package () { "mipi-sdw-link-2-subproperties", "LNK2" }, Package () { "mipi-sdw-link-3-subproperties", "LNK3" }, } } Name (LNK0, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-clock-stop-mode0-supported", One }, [...] Package () { "intel-sdw-ip-clock", 0x0249F000 }, Package () { "intel-quirk-mask", Zero }, } } [...] } BUG=b:146482091 Signed-off-by: Duncan Laurie Change-Id: I4b4f843a7e5ea170b070a1697c8eedc7c103e127 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40888 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/drivers/intel/soundwire/Kconfig | 2 + src/drivers/intel/soundwire/Makefile.inc | 1 + src/drivers/intel/soundwire/chip.h | 9 ++ src/drivers/intel/soundwire/soundwire.c | 100 +++++++++++++++++++++++ src/drivers/intel/soundwire/soundwire.h | 43 ++++++++++ 5 files changed, 155 insertions(+) create mode 100644 src/drivers/intel/soundwire/Kconfig create mode 100644 src/drivers/intel/soundwire/Makefile.inc create mode 100644 src/drivers/intel/soundwire/chip.h create mode 100644 src/drivers/intel/soundwire/soundwire.c create mode 100644 src/drivers/intel/soundwire/soundwire.h diff --git a/src/drivers/intel/soundwire/Kconfig b/src/drivers/intel/soundwire/Kconfig new file mode 100644 index 0000000000..fd6e3996a5 --- /dev/null +++ b/src/drivers/intel/soundwire/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_INTEL_SOUNDWIRE + bool diff --git a/src/drivers/intel/soundwire/Makefile.inc b/src/drivers/intel/soundwire/Makefile.inc new file mode 100644 index 0000000000..1f6773ec26 --- /dev/null +++ b/src/drivers/intel/soundwire/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_INTEL_SOUNDWIRE) += soundwire.c diff --git a/src/drivers/intel/soundwire/chip.h b/src/drivers/intel/soundwire/chip.h new file mode 100644 index 0000000000..1ec35400ad --- /dev/null +++ b/src/drivers/intel/soundwire/chip.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_INTEL_SOUNDWIRE_CHIP_H__ +#define __DRIVERS_INTEL_SOUNDWIRE_CHIP_H__ + +struct drivers_intel_soundwire_config { +}; + +#endif /* __DRIVERS_INTEL_SOUNDWIRE_CHIP_H__ */ diff --git a/src/drivers/intel/soundwire/soundwire.c b/src/drivers/intel/soundwire/soundwire.c new file mode 100644 index 0000000000..ab09ff4473 --- /dev/null +++ b/src/drivers/intel/soundwire/soundwire.c @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "soundwire.h" +#include "chip.h" + +__weak int soc_fill_soundwire_controller(struct intel_soundwire_controller **controller) +{ + return -1; +} + +static bool link_enabled(const struct device *dev, unsigned int link) +{ + struct device *child; + + for (child = dev->link_list->children; child; child = child->sibling) { + if (child->enabled && child->path.type == DEVICE_PATH_GENERIC && + child->path.generic.id == link) + return true; + } + return false; +} + +static void intel_soundwire_link_prop_cb(struct acpi_dp *dsd, unsigned int id, + const struct soundwire_controller *controller) +{ + struct intel_soundwire_controller *intel_controller = + container_of(controller, struct intel_soundwire_controller, sdw); + unsigned int quirk_mask = intel_controller->quirk_mask; + + /* Disable link if no are children enabled on this link device. */ + if (!link_enabled(intel_controller->dev, id)) + quirk_mask |= INTEL_SOUNDWIRE_QUIRK_BUS_DISABLE; + + acpi_dp_add_integer(dsd, "intel-sdw-ip-clock", intel_controller->ip_clock); + acpi_dp_add_integer(dsd, "intel-quirk-mask", quirk_mask); +} + +static void intel_soundwire_fill_ssdt(const struct device *dev) +{ + struct acpi_dp *dsd; + struct intel_soundwire_controller *controller; + const char *scope = acpi_device_scope(dev); + + if (!dev->enabled || !scope) + return; + + if (soc_fill_soundwire_controller(&controller) < 0 || !controller) + return; + + /* Provide device pointer for link property callback function. */ + controller->dev = dev; + + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_DDN", dev->chip_ops->name); + acpigen_write_name_integer("_ADR", controller->acpi_address); + acpigen_write_name_string("_CID", ACPI_HID_CONTAINER); + + acpigen_write_STA(acpi_device_status(dev)); + + dsd = acpi_dp_new_table("_DSD"); + soundwire_gen_controller(dsd, &controller->sdw, &intel_soundwire_link_prop_cb); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static const char *intel_soundwire_acpi_name(const struct device *dev) +{ + return "SNDW"; +} + +static struct device_operations intel_soundwire_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = intel_soundwire_acpi_name, + .acpi_fill_ssdt = intel_soundwire_fill_ssdt, + .scan_bus = scan_static_bus, +}; + +static void intel_soundwire_enable(struct device *dev) +{ + dev->ops = &intel_soundwire_ops; +} + +struct chip_operations drivers_intel_soundwire_ops = { + CHIP_NAME("Intel SoundWire Controller") + .enable_dev = intel_soundwire_enable +}; diff --git a/src/drivers/intel/soundwire/soundwire.h b/src/drivers/intel/soundwire/soundwire.h new file mode 100644 index 0000000000..3e2addfcbf --- /dev/null +++ b/src/drivers/intel/soundwire/soundwire.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_INTEL_SOUNDWIRE_H__ +#define __DRIVERS_INTEL_SOUNDWIRE_H__ + +#include +#include + +/** + * enum intel_soundwire_quirk - Quirks for controller master links. + * @INTEL_SOUNDWIRE_QUIRK_STATIC_CLOCK: Link clock is fixed. + * @INTEL_SOUNDWIRE_QUIRK_BUS_DISABLE: This link should be disabled. + */ +enum intel_soundwire_quirk { + INTEL_SOUNDWIRE_QUIRK_STATIC_CLOCK = BIT(0), + INTEL_SOUNDWIRE_QUIRK_BUS_DISABLE = BIT(1), +}; + +/** + * struct intel_soundwire_controller - SoundWire controller configuration for Intel SoC. + * @dev: Device handle for this controller. + * @acpi_address: ACPI address for this controller. This is a custom address that is not + * compatible with either PCI or SoundWire. + * @ip_clock: Frequency of the source clock connected to the controller. + * @quirk_mask: Quirks that can be passed to the kernel drivers. + * @sdw: SoundWire controller properties defined in MIPI SoundWire DisCo Specification. + */ +struct intel_soundwire_controller { + const struct device *dev; + uint64_t acpi_address; + unsigned int ip_clock; + unsigned int quirk_mask; + struct soundwire_controller sdw; +}; + +/** + * soc_fill_soundwire_controller() - Get SoundWire controller properties from the SoC. + * @controller: Properties to be filled by the SoC. + * Return zero for success, -1 if there was any error filling the properties. + */ +int soc_fill_soundwire_controller(struct intel_soundwire_controller **controller); + +#endif /* __DRIVERS_INTEL_SOUNDWIRE_H__ */ From 2d0655008fa85d19c0c9e95dec9b26522fe2951f Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 29 Apr 2020 12:40:08 -0700 Subject: [PATCH 220/405] soc/intel/tigerlake: Provide SoundWire controller properties The Intel Tigerlake SoundWire controller has 4 master links which are configured differently depending on the external crystal oscillator which is connected to the PCH. This function will read the PCH PMC EPOC register to determine the frequency and then fill out the master link entries with the correct table values. The frequency is also provided directly in a custom "ip-clock" property which will be added to the link descriptor and passed to the OS driver so it can know the clock rate of the master. BUG=b:146482091 Signed-off-by: Duncan Laurie Change-Id: I98b7df21210c29cd8defeff648f2c2207d629295 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40889 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/tigerlake/Makefile.inc | 1 + src/soc/intel/tigerlake/soundwire.c | 71 ++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) create mode 100644 src/soc/intel/tigerlake/soundwire.c diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 51422f9c64..9ff767cfec 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -42,6 +42,7 @@ ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += smmrelocate.c +ramstage-y += soundwire.c ramstage-y += systemagent.c ramstage-y += me.c diff --git a/src/soc/intel/tigerlake/soundwire.c b/src/soc/intel/tigerlake/soundwire.c new file mode 100644 index 0000000000..f69efce2f9 --- /dev/null +++ b/src/soc/intel/tigerlake/soundwire.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static const struct soundwire_link link_xtal_38_4 = { + .clock_stop_mode0_supported = 1, + .clock_stop_mode1_supported = 1, + .clock_frequencies_supported_count = 1, + .clock_frequencies_supported = { 4800 * KHz }, + .default_frame_rate = 48 * KHz, + .default_frame_row_size = 50, + .default_frame_col_size = 4, + .dynamic_frame_shape = 1, + .command_error_threshold = 16, +}; + +static const struct soundwire_link link_xtal_24 = { + .clock_stop_mode0_supported = 1, + .clock_stop_mode1_supported = 1, + .clock_frequencies_supported_count = 1, + .clock_frequencies_supported = { 6 * MHz }, + .default_frame_rate = 48 * KHz, + .default_frame_row_size = 125, + .default_frame_col_size = 2, + .dynamic_frame_shape = 1, + .command_error_threshold = 16, +}; + +static struct intel_soundwire_controller intel_controller = { + .acpi_address = 0x40000000, + .sdw = { + .master_list_count = 4 + } +}; + +int soc_fill_soundwire_controller(struct intel_soundwire_controller **controller) +{ + const struct soundwire_link *link; + enum pch_pmc_xtal xtal = pmc_get_xtal_freq(); + size_t i; + + /* Select link config based on XTAL frequency and set IP clock. */ + switch (xtal) { + case XTAL_24_MHZ: + link = &link_xtal_24; + intel_controller.ip_clock = 24 * MHz; + break; + case XTAL_38_4_MHZ: + link = &link_xtal_38_4; + intel_controller.ip_clock = 38400 * KHz; + break; + case XTAL_19_2_MHZ: + default: + printk(BIOS_ERR, "%s: XTAL not supported: 0x%x\n", __func__, xtal); + return -1; + } + + /* Fill link config in controller map based on selected XTAL. */ + for (i = 0; i < intel_controller.sdw.master_list_count; i++) + memcpy(&intel_controller.sdw.master_list[i], link, sizeof(*link)); + + *controller = &intel_controller; + return 0; +} From e0563cc16e21dbb643abe0358a7eca0c396fb809 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 29 Apr 2020 14:01:04 -0700 Subject: [PATCH 221/405] drivers/soundwire/max98373: Support MAX98373 SoundWire device The MAX98373 smart speaker amp can be connected over SoundWire and be configured for mainboards to use: - Data Port 0 and Bulk Register Access is not supported - Data Port 1 is the 32bit data input for the speaker path - Data Port 3 is the 16bit data output for I/V sense ADC path The data port and audio mode properties are filled out as best as possible with the datasheet as a reference. The ACPI address for the codec is calculated with the information in the codec driver combined with the devicetree.cb hierarchy where the link and unique IDs are extracted from the device path. For example this device is connected to master link ID 1 and has strap settings configuring it for unique ID 3. chip drivers/soundwire/max98373 register "desc" = ""Left Speaker Amp"" device generic 1.3 on end end This driver was tested with the volteer reference design by booting and disassembling the runtime SSDT to ensure that the devices have the expected address and properties. Device (SW13) { Name (_ADR, 0x000123019F837300) Name (_DDN, "Left Speaker Amp") Method (_STA) { Return (0x0F) } Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-sw-interface-revision", 0x00010000 }, [...] }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package () { Package () { "mipi-sdw-port-audio-mode-0", "MOD0" }, Package () { "mipi-sdw-dp-1-sink-subproperties", "SNK1" }, Package () { "mipi-sdw-dp-3-source-subproperties", "SRC3" }, } } Name (MOD0, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-audio-mode-bus-frequency-configs", Package () { 0x00753000, [...] } }, [...] } } Name (SNK1, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-data-port-type", Zero }, [...] }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package () { Package () { "mipi-sdw-port-audio-mode-0", "MOD0" } } } Name (SRC3, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-data-port-type", Zero }, [...] }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package () { Package () { "mipi-sdw-port-audio-mode-0", "MOD0" } } } } BUG=b:146482091 Signed-off-by: Duncan Laurie Change-Id: I3f8cb2779ddde98c5df739bd8a1e83a12a305c00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40890 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/drivers/soundwire/max98373/Kconfig | 2 + src/drivers/soundwire/max98373/Makefile.inc | 1 + src/drivers/soundwire/max98373/chip.h | 11 ++ src/drivers/soundwire/max98373/max98373.c | 165 ++++++++++++++++++++ src/include/device/mipi_ids.h | 4 + 5 files changed, 183 insertions(+) create mode 100644 src/drivers/soundwire/max98373/Kconfig create mode 100644 src/drivers/soundwire/max98373/Makefile.inc create mode 100644 src/drivers/soundwire/max98373/chip.h create mode 100644 src/drivers/soundwire/max98373/max98373.c diff --git a/src/drivers/soundwire/max98373/Kconfig b/src/drivers/soundwire/max98373/Kconfig new file mode 100644 index 0000000000..0dc2c6116d --- /dev/null +++ b/src/drivers/soundwire/max98373/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_SOUNDWIRE_MAX98373 + bool diff --git a/src/drivers/soundwire/max98373/Makefile.inc b/src/drivers/soundwire/max98373/Makefile.inc new file mode 100644 index 0000000000..41c784d2ee --- /dev/null +++ b/src/drivers/soundwire/max98373/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_SOUNDWIRE_MAX98373) += max98373.c diff --git a/src/drivers/soundwire/max98373/chip.h b/src/drivers/soundwire/max98373/chip.h new file mode 100644 index 0000000000..c263577af5 --- /dev/null +++ b/src/drivers/soundwire/max98373/chip.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_SOUNDWIRE_MAX98373_CHIP_H__ +#define __DRIVERS_SOUNDWIRE_MAX98373_CHIP_H__ + +struct drivers_soundwire_max98373_config { + const char *name; + const char *desc; +}; + +#endif /* __DRIVERS_SOUNDWIRE_MAX98373_CHIP_H__ */ diff --git a/src/drivers/soundwire/max98373/max98373.c b/src/drivers/soundwire/max98373/max98373.c new file mode 100644 index 0000000000..231385cd57 --- /dev/null +++ b/src/drivers/soundwire/max98373/max98373.c @@ -0,0 +1,165 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" + +static struct soundwire_address max98373_address = { + .version = SOUNDWIRE_VERSION_1_1, + .manufacturer_id = MIPI_MFG_ID_MAXIM, + .part_id = MIPI_DEV_ID_MAXIM_MAX98373, + .class = MIPI_CLASS_NONE +}; + +static struct soundwire_slave max98373_slave = { + .wake_up_unavailable = false, + .test_mode_supported = false, + .clock_stop_mode1_supported = true, + .simplified_clockstopprepare_sm_supported = true, + .clockstopprepare_hard_reset_behavior = false, + .highPHY_capable = false, + .paging_supported = false, + .bank_delay_supported = false, + .port15_read_behavior = false, + .source_port_list = SOUNDWIRE_PORT(3), + .sink_port_list = SOUNDWIRE_PORT(1), +}; + +static struct soundwire_audio_mode max98373_audio_mode = { + /* Bus frequency must be 1/2/4/8 divider of supported input frequencies. */ + .bus_frequency_configs_count = 27, + .bus_frequency_configs = { + 7680 * KHz, 3840 * KHz, 1920 * KHz, 960 * KHz, /* 7.68 MHz */ + 8400 * KHz, 4200 * KHz, 2100 * KHz, 1050 * KHz, /* 8.4 MHz */ + 9600 * KHz, 4800 * KHz, 2400 * KHz, 1200 * KHz, /* 9.6 MHz */ + 11289600, 5644800, 2822400, 1411200, /* 11.2896 MHz */ + 12000 * KHz, 6000 * KHz, 3000 * KHz, 1500 * KHz, /* 12 MHz */ + 12288 * KHz, 6144 * KHz, 3072 * KHz, 1536 * KHz, /* 12.288 MHz */ + 13000 * KHz, 6500 * KHz, 3250 * KHz /* 13 MHz (no /8) */ + }, + /* Support 16 KHz to 96 KHz sampling frequency */ + .sampling_frequency_configs_count = 8, + .sampling_frequency_configs = { + 16 * KHz, + 22.05 * KHz, + 24 * KHz, + 32 * KHz, + 44.1 * KHz, + 48 * KHz, + 88.2 * KHz, + 96 * KHz, + }, + .prepare_channel_behavior = CHANNEL_PREPARE_ANY_FREQUENCY +}; + +static struct soundwire_dpn max98373_dp1 = { + .port_wordlength_configs_count = 1, + .port_wordlength_configs = { 32 }, + .data_port_type = FULL_DATA_PORT, + .max_grouping_supported = BLOCK_GROUP_COUNT_1, + .simplified_channelprepare_sm = false, + .imp_def_dpn_interrupts_supported = 0, + .min_channel_number = 1, + .max_channel_number = 2, + .modes_supported = MODE_ISOCHRONOUS | MODE_TX_CONTROLLED | + MODE_RX_CONTROLLED | MODE_FULL_ASYNCHRONOUS, + .block_packing_mode = true, + .port_audio_mode_count = 1, + .port_audio_mode_list = { 0 } +}; + +static struct soundwire_dpn max98373_dp3 = { + .port_wordlength_configs_count = 1, + .port_wordlength_configs = { 16 }, + .data_port_type = FULL_DATA_PORT, + .max_grouping_supported = BLOCK_GROUP_COUNT_1, + .simplified_channelprepare_sm = false, + .imp_def_dpn_interrupts_supported = 0, + .min_channel_number = 1, + .max_channel_number = 2, + .modes_supported = MODE_ISOCHRONOUS | MODE_TX_CONTROLLED | + MODE_RX_CONTROLLED | MODE_FULL_ASYNCHRONOUS, + .block_packing_mode = true, + .port_audio_mode_count = 1, + .port_audio_mode_list = { 0 } +}; + +static const struct soundwire_codec max98373_codec = { + .slave = &max98373_slave, + .audio_mode = { &max98373_audio_mode }, + .dpn = { + { + /* Data Input for Speaker Path */ + .port = 1, + .sink = &max98373_dp1 + }, + { + /* Data Output for I/V Sense ADC Path */ + .port = 3, + .source = &max98373_dp3, + } + } +}; + +static void soundwire_max98373_fill_ssdt(const struct device *dev) +{ + struct drivers_soundwire_max98373_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_dp *dsd; + + if (!dev->enabled || !scope) + return; + + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + + /* Set codec address IDs. */ + max98373_address.link_id = dev->path.generic.id; + max98373_address.unique_id = dev->path.generic.subid; + + acpigen_write_ADR_soundwire_device(&max98373_address); + acpigen_write_name_string("_DDN", config->desc ? : dev->chip_ops->name); + acpigen_write_STA(acpi_device_status(dev)); + + dsd = acpi_dp_new_table("_DSD"); + soundwire_gen_codec(dsd, &max98373_codec, NULL); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static const char *soundwire_max98373_acpi_name(const struct device *dev) +{ + struct drivers_soundwire_max98373_config *config = dev->chip_info; + static char name[5]; + + if (config->name) + return config->name; + snprintf(name, sizeof(name), "SW%1X%1X", dev->path.generic.id, dev->path.generic.subid); + return name; +} + +static struct device_operations soundwire_max98373_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = soundwire_max98373_acpi_name, + .acpi_fill_ssdt = soundwire_max98373_fill_ssdt, +}; + +static void soundwire_max98373_enable(struct device *dev) +{ + dev->ops = &soundwire_max98373_ops; +} + +struct chip_operations drivers_soundwire_max98373_ops = { + CHIP_NAME("Maxim MAX98373 SoundWire Codec") + .enable_dev = soundwire_max98373_enable +}; diff --git a/src/include/device/mipi_ids.h b/src/include/device/mipi_ids.h index 2e0254c0b7..4d01300e72 100644 --- a/src/include/device/mipi_ids.h +++ b/src/include/device/mipi_ids.h @@ -18,4 +18,8 @@ #define MIPI_MFG_ID_TI 0x0102 #define MIPI_MFG_ID_TOSHIBA 0x0126 +/* Contributing Members */ +#define MIPI_MFG_ID_MAXIM 0x019f +#define MIPI_DEV_ID_MAXIM_MAX98373 0x8373 + #endif /* __DEVICE_MIPI_IDS_H__ */ From 73ce9fb18a24cab40975d7e674120b90283e8ab1 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 29 Apr 2020 14:25:54 -0700 Subject: [PATCH 222/405] drivers/soundwire/alc5682: Support Realtek ALC5682 SoundWire device The ALC5682 headset codec can be connected over SoundWire and be configured for mainboards to use: - Data Port 0 and Bulk Register Access is supported - Data Ports 1-4 are supported as both source and sink The data port and audio mode properties are filled out as best as possible with the datasheet as a reference. The ACPI address for the codec is calculated with the information in the codec driver combined with the devicetree.cb hierarchy where the link and unique IDs are extracted from the device path. For example this device is connected to master link ID 0 and has strap settings configuring it for unique ID 1: chip drivers/soundwire/alc5682 register "desc" = ""Headset Codec"" device generic 0.1 on end end This driver was tested with the volteer reference design by booting and disassembling the runtime SSDT to ensure that the devices have the expected address and properties. Device (SW01) { Name (_ADR, 0x000021025D568200) Name (_DDN, "Headset Codec") Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-sw-interface-revision", 0x00010000 }, [...] }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package () { Package () { "mipi-sdw-port-bra-mode-0", "BRA0" }, Package () { "mipi-sdw-dp-0-subproperties", "DP0" }, Package () { "mipi-sdw-port-audio-mode-0", "MOD0" }, Package () { "mipi-sdw-dp-1-source-subproperties", "SRC1" }, Package () { "mipi-sdw-dp-1-sink-subproperties", "SNK1" }, [...] } } Name (BRA0, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-bra-mode-bus-frequency-configs", Package () { 0x000F4240, [...] } }, [...] } } Name (DP0, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-bra-flow-controlled", Zero }, [...] }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package () { Package () { "mipi-sdw-port-bra-mode-0", "BRA0" } } } Name (MOD0, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-audio-mode-bus-frequency-configs", Package () { 0x000F4240, [...] } }, [...] } } Name (SNK1, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-data-port-type", Zero }, [...] }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package () { Package () { "mipi-sdw-port-audio-mode-0", "MOD0" } } } Name (SNK1, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-data-port-type", Zero }, [...] }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package () { Package () { "mipi-sdw-port-audio-mode-0", "MOD0" } } } } BUG=b:146482091 Signed-off-by: Duncan Laurie Change-Id: I488dcd81d2e66a6f2c269ab7fa9f7ceaf2cbf003 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40891 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/drivers/soundwire/alc5682/Kconfig | 2 + src/drivers/soundwire/alc5682/Makefile.inc | 1 + src/drivers/soundwire/alc5682/alc5682.c | 179 +++++++++++++++++++++ src/drivers/soundwire/alc5682/chip.h | 11 ++ src/include/device/mipi_ids.h | 3 + 5 files changed, 196 insertions(+) create mode 100644 src/drivers/soundwire/alc5682/Kconfig create mode 100644 src/drivers/soundwire/alc5682/Makefile.inc create mode 100644 src/drivers/soundwire/alc5682/alc5682.c create mode 100644 src/drivers/soundwire/alc5682/chip.h diff --git a/src/drivers/soundwire/alc5682/Kconfig b/src/drivers/soundwire/alc5682/Kconfig new file mode 100644 index 0000000000..5d68c38b59 --- /dev/null +++ b/src/drivers/soundwire/alc5682/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_SOUNDWIRE_ALC5682 + bool diff --git a/src/drivers/soundwire/alc5682/Makefile.inc b/src/drivers/soundwire/alc5682/Makefile.inc new file mode 100644 index 0000000000..eab940cbb1 --- /dev/null +++ b/src/drivers/soundwire/alc5682/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_SOUNDWIRE_ALC5682) += alc5682.c diff --git a/src/drivers/soundwire/alc5682/alc5682.c b/src/drivers/soundwire/alc5682/alc5682.c new file mode 100644 index 0000000000..79ed610ab8 --- /dev/null +++ b/src/drivers/soundwire/alc5682/alc5682.c @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" + +static struct soundwire_address alc5682_address = { + .version = SOUNDWIRE_VERSION_1_1, + .manufacturer_id = MIPI_MFG_ID_REALTEK, + .part_id = MIPI_DEV_ID_REALTEK_ALC5682, + .class = MIPI_CLASS_NONE +}; + +static struct soundwire_slave alc5682_slave = { + .wake_up_unavailable = false, + .test_mode_supported = false, + .clock_stop_mode1_supported = true, + .simplified_clockstopprepare_sm_supported = true, + .clockstopprepare_hard_reset_behavior = false, + .highPHY_capable = false, + .paging_supported = false, + .bank_delay_supported = false, + .port15_read_behavior = false, + .source_port_list = SOUNDWIRE_PORT(1) | SOUNDWIRE_PORT(2) | + SOUNDWIRE_PORT(3) | SOUNDWIRE_PORT(4), + .sink_port_list = SOUNDWIRE_PORT(1) | SOUNDWIRE_PORT(2) | + SOUNDWIRE_PORT(3) | SOUNDWIRE_PORT(4) +}; + +static struct soundwire_bra_mode alc5682_dp0_bra_mode = { + .bus_frequency_configs_count = 7, + .bus_frequency_configs = { + 1000 * KHz, /* 1 MHz */ + 2400 * KHz, /* 2.4 MHz */ + 3000 * KHz, /* 3 MHz */ + 4000 * KHz, /* 4 MHz */ + 4800 * KHz, /* 4.8 MHz */ + 9600 * KHz, /* 9.6 MHz */ + 12000 * KHz, /* 12 MHz */ + }, + .max_data_per_frame = 470, + .min_us_between_transactions = 0 +}; + +static struct soundwire_dp0 alc5682_dp0 = { + .port_max_wordlength = 64, + .port_min_wordlength = 1, + .bra_imp_def_response_supported = false, + .simplified_channel_prepare_sm = true, + .imp_def_dp0_interrupts_supported = 0, + .imp_def_bpt_supported = true, + .bra_mode_count = 1, + .bra_mode_list = { 0 } +}; + +static struct soundwire_audio_mode alc5682_audio_mode = { + .bus_frequency_configs_count = 7, + .bus_frequency_configs = { + 1000 * KHz, /* 1 MHz */ + 2400 * KHz, /* 2.4 MHz */ + 3000 * KHz, /* 3 MHz */ + 4000 * KHz, /* 4 MHz */ + 4800 * KHz, /* 4.8 MHz */ + 9600 * KHz, /* 9.6 MHz */ + 12000 * KHz, /* 12 MHz */ + }, + /* Support 8 KHz to 192 KHz sampling frequency */ + .max_sampling_frequency = 192 * KHz, + .min_sampling_frequency = 8 * KHz, + .prepare_channel_behavior = CHANNEL_PREPARE_ANY_FREQUENCY +}; + +static struct soundwire_dpn alc5682_dpn = { + .port_wordlength_configs_count = 3, + .port_wordlength_configs = { 16, 20, 24 }, + .data_port_type = FULL_DATA_PORT, + .max_grouping_supported = BLOCK_GROUP_COUNT_1, + .simplified_channelprepare_sm = false, + .imp_def_dpn_interrupts_supported = 0, + .min_channel_number = 1, + .max_channel_number = 2, + .modes_supported = MODE_ISOCHRONOUS | MODE_TX_CONTROLLED | + MODE_RX_CONTROLLED | MODE_FULL_ASYNCHRONOUS, + .block_packing_mode = true, + .port_audio_mode_count = 1, + .port_audio_mode_list = { 0 } +}; + +static const struct soundwire_codec alc5682_codec = { + .slave = &alc5682_slave, + .dp0_bra_mode = { &alc5682_dp0_bra_mode }, + .dp0 = &alc5682_dp0, + .audio_mode = { &alc5682_audio_mode }, + .dpn = { + { + .port = 1, + .source = &alc5682_dpn, + .sink = &alc5682_dpn, + }, + { + .port = 2, + .source = &alc5682_dpn, + .sink = &alc5682_dpn, + }, + { + .port = 3, + .source = &alc5682_dpn, + .sink = &alc5682_dpn, + }, + { + .port = 4, + .source = &alc5682_dpn, + .sink = &alc5682_dpn, + } + } +}; + +static void soundwire_alc5682_fill_ssdt(const struct device *dev) +{ + struct drivers_soundwire_alc5682_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_dp *dsd; + + if (!dev->enabled || !scope) + return; + + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + + /* Set codec address IDs. */ + alc5682_address.link_id = dev->path.generic.id; + alc5682_address.unique_id = dev->path.generic.subid; + + acpigen_write_ADR_soundwire_device(&alc5682_address); + acpigen_write_name_string("_DDN", config->desc ? : dev->chip_ops->name); + acpigen_write_STA(acpi_device_status(dev)); + + dsd = acpi_dp_new_table("_DSD"); + soundwire_gen_codec(dsd, &alc5682_codec, NULL); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static const char *soundwire_alc5682_acpi_name(const struct device *dev) +{ + struct drivers_soundwire_alc5682_config *config = dev->chip_info; + static char name[5]; + + if (config->name) + return config->name; + snprintf(name, sizeof(name), "SW%1X%1X", dev->path.generic.id, dev->path.generic.subid); + return name; +} + +static struct device_operations soundwire_alc5682_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = soundwire_alc5682_acpi_name, + .acpi_fill_ssdt = soundwire_alc5682_fill_ssdt, +}; + +static void soundwire_alc5682_enable(struct device *dev) +{ + dev->ops = &soundwire_alc5682_ops; +} + +struct chip_operations drivers_soundwire_alc5682_ops = { + CHIP_NAME("Realtek ALC5682 SoundWire Codec") + .enable_dev = soundwire_alc5682_enable +}; diff --git a/src/drivers/soundwire/alc5682/chip.h b/src/drivers/soundwire/alc5682/chip.h new file mode 100644 index 0000000000..5dfcbfea7e --- /dev/null +++ b/src/drivers/soundwire/alc5682/chip.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_SOUNDWIRE_ALC5682_CHIP_H__ +#define __DRIVERS_SOUNDWIRE_ALC5682_CHIP_H__ + +struct drivers_soundwire_alc5682_config { + const char *name; + const char *desc; +}; + +#endif /* __DRIVERS_SOUNDWIRE_ALC5682_CHIP_H__ */ diff --git a/src/include/device/mipi_ids.h b/src/include/device/mipi_ids.h index 4d01300e72..2d3cd4af44 100644 --- a/src/include/device/mipi_ids.h +++ b/src/include/device/mipi_ids.h @@ -19,6 +19,9 @@ #define MIPI_MFG_ID_TOSHIBA 0x0126 /* Contributing Members */ +#define MIPI_MFG_ID_REALTEK 0x025d +#define MIPI_DEV_ID_REALTEK_ALC5682 0x5682 + #define MIPI_MFG_ID_MAXIM 0x019f #define MIPI_DEV_ID_MAXIM_MAX98373 0x8373 From ba56da85e8cb7f4918ec10d1e5aaab9f553e4e3e Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 29 Apr 2020 15:53:43 -0700 Subject: [PATCH 223/405] Documentation: Add info about SoundWire coreboot implementation This change adds a document about the SoundWire implementation in coreboot with details adding new controllers and codecs and connecting them in the mainboard devicetree. BUG=b:146482091 Signed-off-by: Duncan Laurie Change-Id: Ibc04442e22acfc03ff86c49c8a7a215ceefc24c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40892 Reviewed-by: Tim Wawrzynczak Reviewed-by: Sathyanarayana Nujella Tested-by: build bot (Jenkins) --- Documentation/drivers/index.md | 1 + Documentation/drivers/soundwire.md | 496 +++++++++++++++++++++++++++++ 2 files changed, 497 insertions(+) create mode 100644 Documentation/drivers/soundwire.md diff --git a/Documentation/drivers/index.md b/Documentation/drivers/index.md index 807ed85ed6..e215c6ab11 100644 --- a/Documentation/drivers/index.md +++ b/Documentation/drivers/index.md @@ -6,3 +6,4 @@ they allow to easily reuse existing code accross platforms. * [IPMI KCS](ipmi_kcs.md) * [SMMSTORE](smmstore.md) +* [SoundWire](soundwire.md) diff --git a/Documentation/drivers/soundwire.md b/Documentation/drivers/soundwire.md new file mode 100644 index 0000000000..9c48b75b37 --- /dev/null +++ b/Documentation/drivers/soundwire.md @@ -0,0 +1,496 @@ +# SoundWire Implementation in coreboot + +## Introduction + +SoundWire is an audio interface specification from the MIPI Alliance. + +- Low complexity +- Low power +- Low latency +- Two pins (clock and data) +- Multi-drop capable +- Multiple audio streams +- Embedded control/command channel + +The main *SoundWire Specification* is at version 1.2 and can be downloaded from + but it is unfortunately only available to MIPI Alliance members. + +There is a separate *SoundWire Discovery and Configuration (DisCo) Specification* which +is at version 1.0 and is available for non-members after providing name and email at +. + +The coreboot implementation is based on the SoundWire DisCo Specification which defines +object hierarchy and properties for providing topology and configuration information to +OS kernel drivers via ACPI or DeviceTree. + +SoundWire itself is architecture independent and the coreboot basic definition is also not +specific to any to any SoC. The examples in this document use ACPI to generate properties, +but the same structures and properties would be needed in a DeviceTree implementation. + +## Bus + +The SoundWire bus commonly consists of two pins: + +* Clock: A common clock signal distributed from the master to all of the slaves. +* Data: A shared data signal that can be driven by any of the devices, and has a defined +value when no device is driving it. + +While most designs have one data lane it is possible for a multi-lane device to have up +to 8 data lanes and thus would have more than two pins. + +A SoundWire bus consists of one master device, up to 11 slave devices, and an optional +monitor interface for debug. + +SoundWire is an enumerable bus, but not a discoverable one. That means it is required +for firmware to provide details about the connected devices to the OS. + +### Controller + +A SoundWire controller contains one or more master devices. The handling of multiple +masters is left up to the implementation, they may share a clock or be operated +independently or entirely in tandem. The master devices connected to a controller are +also referred to as links. + +In coreboot the controller device is provided by the SoC or an add-in PCI card. + +### Master + +A SoundWire master (or link) device is responsible for clock and data handling, bus +management, and bit slot allocation. + +In coreboot the definition of the master device is left up to the controller and the +mainboard should only need to know the controller's SoundWire topology (number of masters) +to configure `devicetree.cb`. + +It may however be expected to provide some additional SoC-specific configuration data to +the controller, such as an input clock rate or a list of available masters that cannot +be determined at run time. + +### Slave + +SoundWire slave devices are connected to a master and respond to the two-wire control +information on the SoundWire bus. There can be up to 11 slave devices on a bus and they +are capable of interrupting and waking the host. + +Slave devices may also have master links which can be connected to other slave devices. +It is also possible for a multi-lane slave device to have multiple data lanes connected +to different combinations of master and slave devices. + +In coreboot the slave device is defined by a codec driver which should be found in the +source tree at `src/drivers/soundwire`. + +The mainboard provides: + +* Master link that this slave device is connected to. +* Unique ID that this codec responds to on the SoundWire bus. +* Multi-lane mapping. (optional) + +The codec driver provides: + +* Slave device properties. +* Audio Mode properties including bus frequencies and sampling rates. +* Data Port 1-14 properties such as word lengths, interrupt support, channels. +* Data Port 0 and Bulk Register Access properties. (optional) + +### Monitor + +A SoundWire monitor device is defined that allows for test equipment to snoop the bus and +take over and issue commands. The monitor interface is not defined for coreboot. + +### Example SoundWire Bus + +``` ++---------------+ +---------------+ +| | Clock Signal | | +| Master |-------+-------------------------------| Slave | +| Interface | | Data Signal | Interface 1 | +| |-------|-------+-----------------------| | ++---------------+ | | +---------------+ + | | + | | + | | + +--+-------+--+ + | | + | Slave | + | Interface 2 | + | | + +-------------+ +``` + +## coreboot + +The coreboot implementation of SoundWire integrates with the device model and takes +advantage of the hierarchical nature of `devicetree.cb` to populate the topology. + +The architecture-independent SoundWire tables are defined at + + src/include/device/soundwire.h + +Support for new devices comes in three forms: + +1. New controller and master drivers. The first implementation in coreboot is for an Intel +SoC but the SoundWire specification is in wide use on various ARM SoCs. + + Controller drivers can be implemented in `src/soc` or `src/drivers` and should + strive to re-use code as much as possible between different SoC generations from the + same vendor. + +2. New codec drivers. These should be implemented for each codec that is added which +supports SoundWire. The properties vary between codecs and careful study of the data sheet +is necessary to ensure proper operation. + + Codec drivers should be implemented in `src/drivers/soundwire` as separate chip drivers. + As every codec is different there may not be opportunities of code re-use except between + similar codecs from the same vendor. + +3. New mainboards with SoundWire support. The mainboard will combine controllers and codecs +to form a topology that is described in `devicetree.cb`. Some devices may need to provide +board-specific configuration information, and multi-lane devices will need to provide the +master/slave lane map. + +## ACPI Implementation + +The implementation for x86 devices relies on ACPI for providing device properties to the OS +kernel drivers. + +The ACPI implementation can be found at + + src/acpi/soundwire.c + +And used by including + + #include + +### Controller + +The controller driver should populate a `struct soundwire_controller`: + +```c +/** + * struct soundwire_controller - SoundWire controller properties. + * @master_count: Number of masters present on this device. + * @master_list: One entry for each master device. + */ +struct soundwire_controller { + unsigned int master_list_count; + struct soundwire_link master_list[SOUNDWIRE_MAX_DEV]; +}; +``` + +Once the detail of the master links are specified in the `master_list` variable, the controller +properties for the ACPI object can be generated: + +```c +struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); +soundwire_gen_controller(dsd, &soc_controller, NULL); +acpi_dp_write(dsd); +``` + +If the controller needs to generate custom properties for links it can provide a callback +function to `soundwire_gen_controller()` instead of passing NULL: + +```c +static void controller_link_prop_cb(struct acpi_dp *dsd, unsigned int id, + struct soundwire_controller *controller) +{ + acpi_dp_add_integer(dsd, "custom-link-property", 1); +} +``` + +### Codec + +The codec driver should populate a *struct soundwire_codec* with necessary properties: + +```c +/** + * struct soundwire_codec - Contains all configuration for a SoundWire codec slave device. + * @slave: Properties for slave device. + * @audio_mode: Properties for Audio Mode for Data Ports 1-14. + * @dpn: Properties for Data Ports 1-14. + * @multilane: Properties for slave multilane device. (optional) + * @dp0_bra_mode: Properties for Bulk Register Access mode for Data Port 0. (optional) + * @dp0: Properties for Data Port 0 for Bulk Register Access. (optional) + */ +struct soundwire_codec { + struct soundwire_slave *slave; + struct soundwire_audio_mode *audio_mode[SOUNDWIRE_MAX_DEV]; + struct soundwire_dpn_entry dpn[SOUNDWIRE_MAX_DPN - SOUNDWIRE_MIN_DPN]; + struct soundwire_multilane *multilane; + struct soundwire_bra_mode *dp0_bra_mode[SOUNDWIRE_MAX_DEV]; + struct soundwire_dp0 *dp0; +}; +``` + +Many of these properties are optional, and depending on the codec will not be supported. + +#### Slave Device Properties + +These properties provide information about the codec device and what features it supports: + +* Wake capability +* Clock stop behavior +* Clock and channel state machine behavior +* Features like register pages, broadcast read, bank delay, and high performance PHY + +#### Multi-lane Slave Device Properties + +Most slave devices have a single data pin and a single lane, but it is possible for up to +7 other lanes to be supported on a device. These lanes can be connected to other master +links or to other slave devices. + +If a codec supports this feature it must indicate that by providing an entry for +`struct soundwire_multilane` in the chip configuration. + +```c +/** + * struct drivers_soundwire_example_config - Example codec configuration. + * @multilane: Multi-lane slave configuration. + */ +struct drivers_soundwire_example_config { + struct soundwire_multilane multilane; +}; +``` + +The mainboard is required to provide the lane map in `devicetree.cb` for any codec that has +multiple lanes connected. This includes the definition up to 7 entries that indicate which +lane number on the slave devices (array index starting at 1) maps to which other device: + +``` +chip drivers/soundwire/multilane_codec + register "multilane.lane_mapping" = "{ + { + # Slave Lane 1 maps to Master Lane 2 + .lane = 1, + .direction = MASTER_LANE, + .connection.master_lane = 2 + }, + { + # Slave Lane 3 maps to Slave Link B + .lane = 3, + .direction = SLAVE_LINK, + .connection.slave_link = 1 + } + }" + device generic 0.0 on end +end +``` + +#### Data Port 0 Properties + +SoundWire Data Port 0 (DP0) is a special port used for control and status operation relating +to the whole device interface, and as a special data port for bulk read/write operations. + +The properties for data port 0 are different from that of data ports 1-14 and are about the +control channel behavior and the overall bulk register mode. + +Data port 0 is not required to be supported by the slave device. + +#### Bulk Register Access Mode Properties + +Bulk Register Access (BRA) is an optional mechanism for transporting higher bandwidth of +register operations than the typical command mechanism. The BRA protocol is a particular +format of the data on the (optional) data port 0 connection between the master and slave. + +The BRA protocol may have alignment or timing requirements that are directly related to the +bus frequencies. As a result there may be several configurations listed, for symmetry with +the audio modes paired with data ports 1-14. + +#### Data Port 1-14 Properties + +Data ports 1-14 are typically dedicated to streaming audio payloads, and each data port can +have from 1 to 8 channels. There are different levels of data ports, with some registers +being required and supported on all data ports and some optional registers only being used +on some data ports. + +Data ports can have both a sink and a source component, and the codec may support one or +both of these on each port. + +Similar to data port 0 the properties defined here describe the capabilities and supported +features of each data port, and they may be configured separately. For example the Maxim +MAX98373 codec supports a 32bit source data port for speaker output, and a 16bit sink data +port for speaker sense data. + +#### Audio Mode Properties + +Each data port may be tied to one or more audio modes. The audio mode describes the actual +audio capabilities of the codec, including supported frequencies and sample rates. These +modes can be shared by multiple data ports and do not need to be duplicated. + +For example: + +``` +static struct soundwire_audio_mode audio_mode = { + .bus_frequency_max = 24 * MHz, + .bus_frequency_min = 24 * KHz, + .max_sampling_frequency = 192 * KHz, + .min_sampling_frequency = 8 * KHz, +}; +static struct soundwire_dpn codec_dp1 = { + [...] + .port_audio_mode_count = 1, + .port_audio_mode_list = {0} +}; +static struct soundwire_dpn codec_dp3 = { + [...] + .port_audio_mode_count = 1, + .port_audio_mode_list = {0} +}; +``` + +### Generating Codec Properties + +Once the properties are known it can generate the ACPI code with: + +```c +struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); +soundwire_gen_codec(dsd, &soundwire_codec, NULL); +acpi_dp_write(dsd); +``` + +If the codec needs to generate custom properties for links it can provide a callback +function to `soundwire_gen_codec()` instead of passing NULL: + +```c +static void codec_dp_prop_cb(struct acpi_dp *dsd, unsigned int id, + struct soundwire_codec *codec) +{ + acpi_dp_add_integer(dsd, "custom-dp-property", 1); +} +``` + +#### Codec Address + +SoundWire slave devices use a SoundWire defined ACPI _ADR that requires a 64-bit integer +and uses the master link ID and slave device unique ID to form a unique address for the +device on this controller. + +SoundWire addresses must be distinguishable from all other slave devices on the same master +link, so multiple instances of the same manufacturer and part on the same master link will +need different unique IDs. The value is typically determined by strapping pins on the codec +chip and can be decoded for this table with the codec datasheet and board schematics. + +```c +/** + * struct soundwire_address - SoundWire ACPI Device Address Encoding. + * @version: SoundWire specification version from &enum soundwire_version. + * @link_id: Zero-based SoundWire Link Number. + * @unique_id: Unique ID for multiple devices. + * @manufacturer_id: Manufacturer ID from include/device/mipi_ids.h. + * @part_id: Vendor defined part ID. + * @class: MIPI class encoding in &enum mipi_class. + */ +struct soundwire_address { + enum soundwire_version version; + uint8_t link_id; + uint8_t unique_id; + uint16_t manufacturer_id; + uint16_t part_id; + enum mipi_class class; +}; +``` + +This ACPI address can be generated by calling the provided acpigen function: + + acpigen_write_ADR_soundwire_device(const struct soundwire_address *sdw); + +### Mainboard + +The mainboard needs to select appropriate drivers in `Kconfig` and define the topology in +`devicetree.cb` with the controllers and codecs that exist on the board. + +The topology uses the **generic** device to describe SoundWire: + +```c +struct generic_path { + unsigned int id; /* SoundWire Master Link ID */ + unsigned int subid; /* SoundWire Slave Unique ID */ +}; +``` + +This allows devices to be specified in `devicetree.cb` with the necessary information to +generate ACPI address and device properties. + +``` +chip drivers/intel/soundwire + # SoundWire Controller 0 + device generic 0 on + chip drivers/soundwire/codec1 + # SoundWire Link 0 ID 0 + device generic 0.0 on end + end + chip drivers/soundwire/codec2 + # SoundWire Link 1 ID 2 + device generic 1.2 on end + end + end +end +``` + +## Volteer Example + +This is an example of an Intel Tiger Lake reference board using SoundWire Link 0 for the +headphone codec connection, and Link 1 for connecting two speaker amps for stereo speakers. + +The mainboard can be found at + + src/mainboard/google/volteer + +``` + +------------------+ +-------------------+ + | | | Headphone Codec | + | Intel Tiger Lake | +--->| Realtek ALC5682 | + | SoundWire | | | ID 1 | + | Controller | | +-------------------+ + | | | + | Link 0 +----+ +-------------------+ + | | | Left Speaker Amp | + | Link 1 +----+--->| Maxim MAX98373 | + | | | | ID 3 | + | Link 2 | | +-------------------+ + | | | + | Link 3 | | +-------------------+ + | | | | Right Speaker Amp | + +------------------+ +--->| Maxim MAX98373 | + | ID 7 | + +-------------------+ +``` + +This implementation requires a controller driver for the Intel Tigerlake SoC and a codec +driver for the Realtek and Maxim chips. If those drivers did not already exist they would +need to be added and reviewed separately before adding the support to the mainboard. + +The volteer example requires some `Kconfig` options to be selected: + +``` +config BOARD_GOOGLE_BASEBOARD_VOLTEER + select DRIVERS_INTEL_SOUNDWIRE + select DRIVERS_SOUNDWIRE_ALC5682 + select DRIVERS_SOUNDWIRE_MAX98373 +``` + +And the following `devicetree.cb` entries to define this topology: + +``` +device pci 1f.3 on + chip drivers/intel/soundwire + # SoundWire Controller 0 + device generic 0 on + chip drivers/soundwire/alc5682 + # SoundWire Link 0 ID 1 + register "desc" = ""Headphone Jack"" + device generic 0.1 on end + end + chip drivers/soundwire/max98373 + # SoundWire Link 0 ID 1 + register "desc" = ""Left Speaker Amp"" + device generic 1.3 on end + end + chip drivers/soundwire/max98373 + # SoundWire Link 1 ID 7 + register "desc" = ""Right Speaker Amp"" + device generic 1.7 on end + end + end + end +end +``` From 60894a071169c3df3f1f62f0224f117861e47a86 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 29 Apr 2020 16:02:40 -0700 Subject: [PATCH 224/405] mb/google/volteer: Add overridetree.cb for volteer variant Instead of only using the baseboard devicetree add a placeholder overridetree for volteer and refer to it in Kconfig. This will allow us to add the volteer specific devices here instead of at the baseboard level. BUG=b:146482091 Signed-off-by: Duncan Laurie Change-Id: I7788a5473fc2275a9791fb27e0e4018a0efcd0f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40893 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/Kconfig | 2 +- src/mainboard/google/volteer/variants/volteer/overridetree.cb | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) create mode 100644 src/mainboard/google/volteer/variants/volteer/overridetree.cb diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index f6ff42c652..b02ff89ddd 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -42,7 +42,7 @@ config DEVICETREE config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_VOLTEER + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config DRIVER_TPM_SPI_BUS default 0x1 diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb new file mode 100644 index 0000000000..75422d80bb --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -0,0 +1,4 @@ +chip soc/intel/tigerlake + device domain 0 on + end +end From da8f5077ffa495d632536f561ce7bbeb372f6141 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 29 Apr 2020 16:11:45 -0700 Subject: [PATCH 225/405] mb/google/volteer: Add SoundWire codecs to volteer variant Enable drivers for SoundWire codecs and define the topology in the devicetree for the volteer variant with the SoundWire daughter board connected. +------------------+ +-------------------+ | | | Headphone Codec | | Intel Tigerlake | +--->| Realtek ALC5682 | | SoundWire | | | ID 1 | | Controller | | +-------------------+ | | | | Link 0 +----+ +-------------------+ | | | Left Speaker Amp | | Link 1 +----+--->| Maxim MAX98373 | | | | | ID 3 | | Link 2 | | +-------------------+ | | | | Link 3 | | +-------------------+ | | | | Right Speaker Amp | +------------------+ +--->| Maxim MAX98373 | | ID 7 | +-------------------+ This was tested by booting the firmware and dumping the SSDT table to ensure that all SoundWire ACPI devices are created as expected with the properties that are defined in coreboot under \_SB.PCI0: HDAS - Intel Tigerlake HDA PCI device HDAS.SNDW - Intel Tigerlake SoundWire Controller HDAS.SNDW.SW01 - Realtek ALC5682 - Headphone Codec HDAS.SNDW.SW13 - Maxim MAX98373 - Left Speaker Amp HDAS.SNDW.SW17 - Maxim MAX98373 - Right Speaker Amp BUG=b:146482091 Signed-off-by: Duncan Laurie Change-Id: I7782059807416369e0e1ba0d4d7c79dcab0fcbc5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40894 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/Kconfig | 3 +++ .../volteer/variants/volteer/overridetree.cb | 21 +++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index b02ff89ddd..143a1eeccc 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -4,7 +4,10 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID + select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_SPI_ACPI + select DRIVERS_SOUNDWIRE_ALC5682 + select DRIVERS_SOUNDWIRE_MAX98373 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_SKUID diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index 75422d80bb..aa2c8fb12f 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -1,4 +1,25 @@ chip soc/intel/tigerlake device domain 0 on + device pci 1f.3 on + chip drivers/intel/soundwire + device generic 0 on + chip drivers/soundwire/alc5682 + # SoundWire Link 0 ID 1 + register "desc" = ""Headset Codec"" + device generic 0.1 on end + end + chip drivers/soundwire/max98373 + # SoundWire Link 1 ID 3 + register "desc" = ""Left Speaker Amp"" + device generic 1.3 on end + end + chip drivers/soundwire/max98373 + # SoundWire Link 1 ID 7 + register "desc" = ""Right Speaker Amp"" + device generic 1.7 on end + end + end + end + end end end From 6107064d66359213dd20736b2321990de29c39ff Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 15 May 2020 15:37:07 -0700 Subject: [PATCH 226/405] make: Add a target and dependency to parse the devicetree with sconfig This change adds a target to the top level Makefile that allows building sconfig and generating static.c/static.h without building the rest of coreboot. It also adds $(DEVICETREE_STATIC_C) to the c-deps for each stage so the files are generated before the build runs. Signed-off-by: Duncan Laurie Change-Id: I4320288422230d8913dfa7cc7b7512775a1a797b Reviewed-on: https://review.coreboot.org/c/coreboot/+/41439 Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- Makefile.inc | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index 7debe53ebd..210e9cf6c6 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -596,6 +596,17 @@ bootblock-y+=$(DEVICETREE_STATIC_C) postcar-y+=$(DEVICETREE_STATIC_C) smm-y+=$(DEVICETREE_STATIC_C) +# Ensure static.c and static.h are created before any objects are compiled +ramstage-c-deps+=$(DEVICETREE_STATIC_C) +romstage-c-deps+=$(DEVICETREE_STATIC_C) +verstage-c-deps+=$(DEVICETREE_STATIC_C) +bootblock-c-deps+=$(DEVICETREE_STATIC_C) +postcar-c-deps+=$(DEVICETREE_STATIC_C) +smm-c-deps+=$(DEVICETREE_STATIC_C) + +.PHONY: devicetree +devicetree: $(DEVICETREE_STATIC_C) + ####################################################################### # Clean up rules clean-abuild: From b29b22888ddd88da361a5c47b39afcfdb3791be3 Mon Sep 17 00:00:00 2001 From: Stefan Ott Date: Wed, 22 Apr 2020 23:20:03 +0200 Subject: [PATCH 227/405] mb/lenovo/t420: Add support for ThinkLight With this patch, the ThinkLight on the ThinkPad T420 can be controlled through the OS. The same change was done for the ThinkPad X200 in b45912f4: mb/lenovo/x200: Add support for ThinkLight After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight Unfortunately I do not own a T420 to test this. Change-Id: I4f9a9937a45995b72a9712919316e95bb8f82f45 Signed-off-by: Stefan Ott Reviewed-on: https://review.coreboot.org/c/coreboot/+/40714 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/lenovo/t420/dsdt.asl | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lenovo/t420/dsdt.asl b/src/mainboard/lenovo/t420/dsdt.asl index f0964d3561..b83fe38daa 100644 --- a/src/mainboard/lenovo/t420/dsdt.asl +++ b/src/mainboard/lenovo/t420/dsdt.asl @@ -35,4 +35,5 @@ DefinitionBlock( } #include + #include } From be698de76e102fd7801444a04343c4bfbad1ff2a Mon Sep 17 00:00:00 2001 From: Stefan Ott Date: Wed, 22 Apr 2020 23:20:03 +0200 Subject: [PATCH 228/405] mb/lenovo/x220: Add support for ThinkLight With this patch, the ThinkLight on the ThinkPad X220 can be controlled through the OS. This was initially done for the X201 in f63fbdb6: mb/lenovo/x201: Add support for ThinkLight. After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight Unfortunately I do not own an X220 to test this. Change-Id: Icead793694475e2f63353690203790ab7ce7c597 Signed-off-by: Stefan Ott Reviewed-on: https://review.coreboot.org/c/coreboot/+/40668 Reviewed-by: Alexander Couzens Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/x220/dsdt.asl | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl index f0964d3561..b83fe38daa 100644 --- a/src/mainboard/lenovo/x220/dsdt.asl +++ b/src/mainboard/lenovo/x220/dsdt.asl @@ -35,4 +35,5 @@ DefinitionBlock( } #include + #include } From af90a1e6afd93bb4c42393ebd9a47b21e2222737 Mon Sep 17 00:00:00 2001 From: Piotr Kleinschmidt Date: Thu, 21 May 2020 17:48:12 +0200 Subject: [PATCH 229/405] mb/pcengines/apu1/platform_cfg.h: Unset UsbRxMode to avoid platform reset issue MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On PC Engines apu1 there were issues with cold reset. Platform hangs in boot path after performing reset using CF9h. CB:10549 (amd/sb800: Make UsbRxMode per-board customizable) mentions a similar issue, and added a configuration macro for it. That error is also described in AMD SB800 Family Product Errata, section 15 USB Resets Asynchronously With Port CF9h Hard Reset. This workaround simply non-execute USB configuration during boot and hence no reset via CF9h is done. TEST=perform multiple cold resets and see if platform boots Signed-off-by: Piotr Kleinschmidt Change-Id: Ie6cebcfc4b77e121ef44a25fa81377eb5e1f0644 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41627 Reviewed-by: Michał Żygowski Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/pcengines/apu1/platform_cfg.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/mainboard/pcengines/apu1/platform_cfg.h b/src/mainboard/pcengines/apu1/platform_cfg.h index 2f5c56c0da..63a3d5a7cb 100644 --- a/src/mainboard/pcengines/apu1/platform_cfg.h +++ b/src/mainboard/pcengines/apu1/platform_cfg.h @@ -212,4 +212,18 @@ */ #define FADT_PM_PROFILE 1 +/** + * @def USB_RX_MODE + * 0x00 - leave Cg2Pll voltage at default value (1.222V) + * 0x01 - lower Cg2Pll voltage to 1.1V + * + * Workaround for reset issues via outb(0x6, 0xcf9). + * For details check: + * AMD SB800 Family Product Errata, + * Section 15. USB Resets Asynchronously With Port CF9h Hard Reset + * + */ + +#define USB_RX_MODE 0x00 + #endif /* _PLATFORM_CFG_H_ */ From 4e448fb79b426c6f7bdd0aa6fe2c4d0394e7de7c Mon Sep 17 00:00:00 2001 From: Stefan Ott Date: Wed, 22 Apr 2020 23:20:03 +0200 Subject: [PATCH 230/405] mb/lenovo/t430: Add support for ThinkLight With this patch, the ThinkLight on the ThinkPad T430 can be controlled through the OS. The same change was done for the ThinkPad X200 in b45912f4: mb/lenovo/x200: Add support for ThinkLight After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight Unfortunately I do not own a T430 to test this. Change-Id: I1fb1a9d3a84ce12ab9e3f22a699afbfd7cd1688f Signed-off-by: Stefan Ott Reviewed-on: https://review.coreboot.org/c/coreboot/+/40716 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens --- src/mainboard/lenovo/t430/dsdt.asl | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lenovo/t430/dsdt.asl b/src/mainboard/lenovo/t430/dsdt.asl index bc11b8cbf8..87eab8c120 100644 --- a/src/mainboard/lenovo/t430/dsdt.asl +++ b/src/mainboard/lenovo/t430/dsdt.asl @@ -30,4 +30,5 @@ DefinitionBlock( #include } } + #include } From 020f5a79bf32d46b01f6a333332b85f9bad03571 Mon Sep 17 00:00:00 2001 From: Stefan Ott Date: Wed, 22 Apr 2020 23:20:03 +0200 Subject: [PATCH 231/405] mb/lenovo/t530: Add support for ThinkLight With this patch, the ThinkLight on the ThinkPad T530 can be controlled through the OS. The same change was done for the ThinkPad X200 in b45912f4: mb/lenovo/x200: Add support for ThinkLight After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight Unfortunately I do not own a T530 to test this. Change-Id: I94d239b65e6e8546a27f751d569681a4e68a4109 Signed-off-by: Stefan Ott Reviewed-on: https://review.coreboot.org/c/coreboot/+/40719 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens --- src/mainboard/lenovo/t530/dsdt.asl | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl index f0964d3561..b83fe38daa 100644 --- a/src/mainboard/lenovo/t530/dsdt.asl +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -35,4 +35,5 @@ DefinitionBlock( } #include + #include } From 65bd97c6360a0e5190e393b84bc6b2d2029439a3 Mon Sep 17 00:00:00 2001 From: Stefan Ott Date: Wed, 22 Apr 2020 23:20:03 +0200 Subject: [PATCH 232/405] mb/lenovo/t520: Add support for ThinkLight With this patch, the ThinkLight on the ThinkPad T520 can be controlled through the OS. The same change was done for the ThinkPad X200 in b45912f4: mb/lenovo/x200: Add support for ThinkLight After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight Unfortunately I do not own a T520 to test this. Change-Id: Iffc5dd2f23ee4896da633c18cbbf22c9e448edf1 Signed-off-by: Stefan Ott Reviewed-on: https://review.coreboot.org/c/coreboot/+/40718 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens --- src/mainboard/lenovo/t520/dsdt.asl | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl index f0964d3561..b83fe38daa 100644 --- a/src/mainboard/lenovo/t520/dsdt.asl +++ b/src/mainboard/lenovo/t520/dsdt.asl @@ -35,4 +35,5 @@ DefinitionBlock( } #include + #include } From 39fc181e558ca11a2d36590bef25ba6f163046ec Mon Sep 17 00:00:00 2001 From: Stefan Ott Date: Wed, 22 Apr 2020 23:20:03 +0200 Subject: [PATCH 233/405] mb/lenovo/t420s: Add support for ThinkLight With this patch, the ThinkLight on the ThinkPad T420S can be controlled through the OS. The same change was done for the ThinkPad X200 in b45912f4: mb/lenovo/x200: Add support for ThinkLight After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight Unfortunately I do not own a T420S to test this. Change-Id: I245acf81b34abccf7bcb04126275ab8b154135d5 Signed-off-by: Stefan Ott Reviewed-on: https://review.coreboot.org/c/coreboot/+/40715 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens --- src/mainboard/lenovo/t420s/dsdt.asl | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl index f0964d3561..b83fe38daa 100644 --- a/src/mainboard/lenovo/t420s/dsdt.asl +++ b/src/mainboard/lenovo/t420s/dsdt.asl @@ -35,4 +35,5 @@ DefinitionBlock( } #include + #include } From 88d16c33d442f9f34e1d0c131df3335a9d98913b Mon Sep 17 00:00:00 2001 From: Stefan Ott Date: Wed, 22 Apr 2020 23:20:03 +0200 Subject: [PATCH 234/405] mb/lenovo/t430s: Add support for ThinkLight With this patch, the ThinkLight on the ThinkPad T430S can be controlled through the OS. The same change was done for the ThinkPad X200 in b45912f4: mb/lenovo/x200: Add support for ThinkLight After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight Unfortunately I do not own a T430S to test this. Change-Id: Ifa74f5373a6305d1237e7de6da35028e68f1e99c Signed-off-by: Stefan Ott Reviewed-on: https://review.coreboot.org/c/coreboot/+/40717 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens --- src/mainboard/lenovo/t430s/dsdt.asl | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lenovo/t430s/dsdt.asl b/src/mainboard/lenovo/t430s/dsdt.asl index f0964d3561..b83fe38daa 100644 --- a/src/mainboard/lenovo/t430s/dsdt.asl +++ b/src/mainboard/lenovo/t430s/dsdt.asl @@ -35,4 +35,5 @@ DefinitionBlock( } #include + #include } From da606d4114629f7b9816a6db981fb7b590a08e02 Mon Sep 17 00:00:00 2001 From: Stefan Ott Date: Wed, 22 Apr 2020 23:20:03 +0200 Subject: [PATCH 235/405] mb/lenovo/t400: Add support for ThinkLight With this patch, the ThinkLight on the ThinkPad T400 can be controlled through the OS. The same change was done for the ThinkPad X200 in b45912f4: mb/lenovo/x200: Add support for ThinkLight After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight Unfortunately I do not own a T400 to test this. Change-Id: I377854d6f54c5459e44626a7d7b61c513268183e Signed-off-by: Stefan Ott Reviewed-on: https://review.coreboot.org/c/coreboot/+/40713 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens --- src/mainboard/lenovo/t400/dsdt.asl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl index 6ca09dffb0..a1325fb27a 100644 --- a/src/mainboard/lenovo/t400/dsdt.asl +++ b/src/mainboard/lenovo/t400/dsdt.asl @@ -43,4 +43,6 @@ DefinitionBlock( /* Dock support code */ #include "acpi/dock.asl" + + #include } From d1e44b033ea48bc4ac3303ff8459544bc4abc040 Mon Sep 17 00:00:00 2001 From: Bill XIE Date: Mon, 18 May 2020 22:15:22 +0800 Subject: [PATCH 236/405] mb/lenovo/x230: add "docking_supported" to x230 overridetree The X230, like its larger cousins, has a docking connector. However, it lacks the "docking_supported" flag in devicetree, so add it. Change-Id: I188045e4cf9bbb0f2d434b353b84223470c951b9 Signed-off-by: Bill XIE Reviewed-on: https://review.coreboot.org/c/coreboot/+/41510 Reviewed-by: Alexander Couzens Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/x230/variants/x230/overridetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lenovo/x230/variants/x230/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb index 5f2f3a58d5..97e48b8c2a 100644 --- a/src/mainboard/lenovo/x230/variants/x230/overridetree.cb +++ b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb @@ -1,6 +1,7 @@ chip northbridge/intel/sandybridge device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "docking_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" device pci 1c.2 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" From 8a4536dfb7dfd00c0a6d91ecd220632eaf37136f Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 21 May 2020 17:17:09 +0200 Subject: [PATCH 237/405] 3rdparty/amd_blobs: update submodule pointer Change-Id: I468f0d3ab018ee0044e8de7df829c64940c7df2b Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/41623 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson Reviewed-by: Raul Rangel --- 3rdparty/amd_blobs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index dcfc2275a7..0e4b8285d9 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit dcfc2275a7b7c195a7afb657e9829b6bd1b86538 +Subproject commit 0e4b8285d95cdfd1facd3acccf848fd06edf6038 From ebf1daa001025377dd1f34ecbfe42b224109ba1f Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 19 May 2020 12:32:41 +0530 Subject: [PATCH 238/405] soc/intel/{jsl,tgl}: Override PRERAM_CBMEM_CONSOLE_SIZE default value This patch increases PRERAM_CBMEM_CONSOLE_SIZE to fix *** Pre-CBMEM romstage console overflowed, log truncated! *** issue. TEST=Verified on TGL platform. Change-Id: Iae66b6a1260a9290b35d804487b7a07242c5ebc2 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/41528 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Wonkyu Kim --- src/soc/intel/jasperlake/Kconfig | 4 ++++ src/soc/intel/tigerlake/Kconfig | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 47766ede75..bfefbf271b 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -207,4 +207,8 @@ config SOC_INTEL_JASPERLAKE_DEBUG_CONSENT 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0xe00 endif diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index a55b543100..e0d29fbeef 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -205,4 +205,8 @@ config SOC_INTEL_TIGERLAKE_DEBUG_CONSENT 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0xe00 endif From 41aab355c18f81f4788d64f8083f721d455f2a4d Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 13 Apr 2020 12:23:07 +0530 Subject: [PATCH 239/405] soc/intel/common/block: Update SA resource length to support 64 bit This patch provides an option for accommodating 64 bit width resource request with CONFIG_PCI_SEGMENT_GROUPS = 16 refer as PCIEX BAR length 4096MB (Bus 0-4095). Change-Id: I9a8448af7e9f26c8e0176e58e4fe253a6e77b69a Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/40336 Reviewed-by: Wonkyu Kim Reviewed-by: Aaron Durbin Reviewed-by: Lean Sheng Tan Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/include/intelblocks/systemagent.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index 11ea76a089..30c892ba13 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -31,13 +31,13 @@ void bootblock_systemagent_early_init(void); * INDEX = Either PCI configuration space registers or MMIO offsets * mapped from REG. * BASE = 64 bit Address. - * SIZE = base length + * SIZE = 64 bit base length * DESCRIPTION = Name of the register/offset. */ struct sa_mmio_descriptor { unsigned int index; uint64_t base; - size_t size; + uint64_t size; const char *description; }; From 005fe89daa6736089d5e968728aa32d449e78735 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Tue, 12 May 2020 22:37:39 -0600 Subject: [PATCH 240/405] Makefile: Use SPDX identifier Change-Id: Ia05f2ecd31d0606dfe2bca843dbe6df2b8212a27 Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/41598 Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- LICENSES/retained-copyrights.txt | 3 +++ Makefile | 31 +------------------------------ 2 files changed, 4 insertions(+), 30 deletions(-) diff --git a/LICENSES/retained-copyrights.txt b/LICENSES/retained-copyrights.txt index 6775d2eae5..671f37f0a3 100644 --- a/LICENSES/retained-copyrights.txt +++ b/LICENSES/retained-copyrights.txt @@ -25,6 +25,8 @@ Copyright (c) 2008, 2009 Pattrick Hueper Copyright (C) 2008 Advanced Micro Devices, Inc. Copyright (c) 2008, Google Inc. Copyright (C) 2008 Jordan Crouse +Copyright (C) 2008 Uwe Hermann +Copyright (C) 2009-2010 coresystems GmbH Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved. Copyright (c) 2010-2017, The Regents of the University of California Copyright (c) 2010, Code Aurora Forum. All rights reserved. @@ -36,6 +38,7 @@ Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. Copyright (c) 2011 - 2014 The Linux Foundation. All rights reserved. Copyright (c) 2011-2019 The Linux Foundation. All rights reserved. Copyright (c) 2011, Google Inc. +Copyright (C) 2011 secunet Security Networks AG Copyright (c) 2012 - 2013, 2015, 2019 The Linux Foundation. Copyright (c) 2012 - 2013, 2015 The Linux Foundation. All rights reserved. Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved. diff --git a/Makefile b/Makefile index 470be94537..2bc2a6fe63 100644 --- a/Makefile +++ b/Makefile @@ -1,33 +1,4 @@ -## -## -## Copyright (C) 2008 Advanced Micro Devices, Inc. -## Copyright (C) 2008 Uwe Hermann -## Copyright (C) 2009-2010 coresystems GmbH -## Copyright (C) 2011 secunet Security Networks AG -## -## Redistribution and use in source and binary forms, with or without -## modification, are permitted provided that the following conditions -## are met: -## 1. Redistributions of source code must retain the above copyright -## notice, this list of conditions and the following disclaimer. -## 2. Redistributions in binary form must reproduce the above copyright -## notice, this list of conditions and the following disclaimer in the -## documentation and/or other materials provided with the distribution. -## 3. The name of the author may not be used to endorse or promote products -## derived from this software without specific prior written permission. -## -## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -## SUCH DAMAGE. -## +## SPDX-License-Identifier: BSD-3-Clause ifneq ($(words $(CURDIR)),1) $(error Error: Path to the main directory cannot contain spaces) From e61f14965949863859d7158e7036b24e80f6b51c Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Wed, 20 May 2020 18:21:00 -0600 Subject: [PATCH 241/405] soc/intel/broadwell: Use SPDX identifier Change-Id: Ifbab50ef42f0fe49dd3949db662b245c63522f2d Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/41599 Reviewed-by: Patrick Georgi Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/include/soc/soc_chip.h | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/src/soc/intel/broadwell/include/soc/soc_chip.h b/src/soc/intel/broadwell/include/soc/soc_chip.h index ff77168e0a..bbd556e55d 100644 --- a/src/soc/intel/broadwell/include/soc/soc_chip.h +++ b/src/soc/intel/broadwell/include/soc/soc_chip.h @@ -1,16 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _SOC_BROADWELL_SOC_CHIP_H_ #define _SOC_BROADWELL_SOC_CHIP_H_ From acf80f287f75c7a39702358d5ad886e9b646b68b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 19 May 2020 01:27:23 +0200 Subject: [PATCH 242/405] mb/asrock/b85m_pro4/gma-mainboard.ads: Use GPL-2.0-or-later Other files in the tree use such license. I first added this file. Change-Id: I338654ec022bd6f2fa4a4381a8f27d024605e79d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41525 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/asrock/b85m_pro4/gma-mainboard.ads | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asrock/b85m_pro4/gma-mainboard.ads b/src/mainboard/asrock/b85m_pro4/gma-mainboard.ads index 0c7d30dac6..393275b958 100644 --- a/src/mainboard/asrock/b85m_pro4/gma-mainboard.ads +++ b/src/mainboard/asrock/b85m_pro4/gma-mainboard.ads @@ -1,4 +1,4 @@ --- SPDX-License-Identifier: GPL-2.0-only +-- SPDX-License-Identifier: GPL-2.0-or-later with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; From f309204c534d5af1e8e40d4145e82e9229c7d4ee Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 20 May 2020 01:42:40 +0200 Subject: [PATCH 243/405] soc/amd/picasso/include/cpu: add Raven1 CPUID Change-Id: Iaf848a68dc50c2af1e32b996f09296aaea935459 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/41628 Reviewed-by: Angel Pons Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/include/soc/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 11057bd5a9..a377c1ca42 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -11,6 +11,7 @@ void picasso_init_cpus(struct device *dev); int get_cpu_count(void); void check_mca(void); +#define RAVEN1_CPUID 0x00810f10 #define PICASSO_CPUID 0x00810f81 #define RAVEN2_CPUID 0x00820f01 From e6fcfc2a48fdb96637ee50b9afed98e38ce01a0a Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 20 May 2020 01:32:38 +0200 Subject: [PATCH 244/405] vc/amd/fsp/picasso: add Picasso misc data HOB GUID and struct BUG=b:153779573 Change-Id: I417ce34f2c302d61cfe94ff478f9022cae16f046 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/41629 Reviewed-by: Angel Pons Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/vendorcode/amd/fsp/picasso/FspGuids.h | 4 ++++ src/vendorcode/amd/fsp/picasso/misc_data.h | 14 ++++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 src/vendorcode/amd/fsp/picasso/misc_data.h diff --git a/src/vendorcode/amd/fsp/picasso/FspGuids.h b/src/vendorcode/amd/fsp/picasso/FspGuids.h index 69cb8b71c5..24b185d4a8 100644 --- a/src/vendorcode/amd/fsp/picasso/FspGuids.h +++ b/src/vendorcode/amd/fsp/picasso/FspGuids.h @@ -9,4 +9,8 @@ GUID_INIT(0x5fc7897a, 0x5aff, 0x4c61, \ 0xaa, 0x7a, 0xdd, 0xcf, 0xa9, 0x18, 0x43, 0x0c) +#define PICASSO_MISC_DATA_HOB_GUID \ + GUID_INIT(0xf2784616, 0xb9bf, 0x4e1e, \ + 0x99, 0xe0, 0x96, 0x26, 0xda, 0x7e, 0xa5, 0xf5) + #endif /* __FSP_GUIDS__ */ diff --git a/src/vendorcode/amd/fsp/picasso/misc_data.h b/src/vendorcode/amd/fsp/picasso/misc_data.h new file mode 100644 index 0000000000..c8032749f9 --- /dev/null +++ b/src/vendorcode/amd/fsp/picasso/misc_data.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __PI_PICASSO_MISC_DATA_H__ +#define __PI_PICASSO_MISC_DATA_H__ + +#define PICASSO_MISC_DATA_VERSION 1 + +struct picasso_misc_data { + uint8_t version; + uint8_t unused[3]; + uint32_t silicon_id; +} __packed; + +#endif /* __PI_PICASSO_MISC_DATA_H__ */ From fa8f567f3243e3d547a9e8388064a091ee294f98 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Mon, 18 May 2020 13:18:19 -0600 Subject: [PATCH 245/405] security/tpm: Use SPDX identifiers Also adjust a few comments to follow the style guide. Change-Id: I22001320f2ce1f0db348e0f7fabc5a65b50ba53e Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/41600 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- LICENSES/retained-copyrights.txt | 4 ++++ src/security/tpm/tss.h | 6 +----- src/security/tpm/tss/tcg-1.2/tss.c | 11 +++++------ src/security/tpm/tss/tcg-1.2/tss_internal.h | 5 +---- src/security/tpm/tss/tcg-1.2/tss_structures.h | 7 +++---- src/security/tpm/tss/tcg-2.0/tss.c | 7 +------ src/security/tpm/tss/tcg-2.0/tss_marshaling.c | 7 +------ src/security/tpm/tss/tcg-2.0/tss_marshaling.h | 7 ++----- src/security/tpm/tss/tcg-2.0/tss_structures.h | 6 +----- src/security/tpm/tss/vendor/cr50/cr50.c | 6 +----- src/security/tpm/tss_errors.h | 8 +++----- 11 files changed, 23 insertions(+), 51 deletions(-) diff --git a/LICENSES/retained-copyrights.txt b/LICENSES/retained-copyrights.txt index 671f37f0a3..066bf6f7d0 100644 --- a/LICENSES/retained-copyrights.txt +++ b/LICENSES/retained-copyrights.txt @@ -11,6 +11,7 @@ Copyright 2015 Google Inc. Copyright 2015, Google Inc. Copyright 2016 Jonathan Neuschäfer Copyright 2016 The Chromium OS Authors. All rights reserved. +Copyright 2017-2019 Eltan B.V. Copyright 2017 Google Inc. Copyright 2018 Generated Code Copyright 2018-present Facebook, Inc. @@ -32,6 +33,7 @@ Copyright (c) 2010-2017, The Regents of the University of California Copyright (c) 2010, Code Aurora Forum. All rights reserved. Copyright (C) 2010 coresystems GmbH Copyright (c) 2010 Per Odlund +Copyright (c) 2010 The Chromium OS Authors. All rights reserved. Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. Copyright (c) 2011-2012 The Linux Foundation. All rights reserved. Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. @@ -79,7 +81,9 @@ Copyright (C) 2015 Timothy Pearson , Raptor E Copyright (c) 2016, 2018, The Linux Foundation. All rights reserved. Copyright (C) 2016 Google Inc. Copyright (c) 2016, The Regents of the University of California (Regents). +Copyright (C) 2018-2019 Eltan B.V. Copyright (C) 2018 - 2019 The Linux Foundation. All rights reserved. +Copyright (c) 2018 Eltan B.V. Copyright (c) 2018, HardenedLinux. Copyright (C) 2018, The Linux Foundation. All rights reserved. Copyright Dave Airlie diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h index 57f3b24847..f644e3e7e7 100644 --- a/src/security/tpm/tss.h +++ b/src/security/tpm/tss.h @@ -1,8 +1,4 @@ -/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2018-2019 Eltan B.V. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ /* * TPM Lightweight Command Library. diff --git a/src/security/tpm/tss/tcg-1.2/tss.c b/src/security/tpm/tss/tcg-1.2/tss.c index ea3f94d5f8..4434ca6983 100644 --- a/src/security/tpm/tss/tcg-1.2/tss.c +++ b/src/security/tpm/tss/tcg-1.2/tss.c @@ -1,9 +1,7 @@ -/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ -/* A lightweight TPM command library. +/* + * A lightweight TPM command library. * * The general idea is that TPM commands are array of bytes whose * fields are mostly compile-time constant. The goal is to build much @@ -75,7 +73,8 @@ static inline int tpm_return_code(const uint8_t *buffer) return tpm_command_code(buffer); } -/* Like TlclSendReceive below, but do not retry if NEEDS_SELFTEST or +/* + * Like TlclSendReceive below, but do not retry if NEEDS_SELFTEST or * DOING_SELFTEST errors are returned. */ static uint32_t tlcl_send_receive_no_retry(const uint8_t *request, diff --git a/src/security/tpm/tss/tcg-1.2/tss_internal.h b/src/security/tpm/tss/tcg-1.2/tss_internal.h index e999cb947f..1f49f041f4 100644 --- a/src/security/tpm/tss/tcg-1.2/tss_internal.h +++ b/src/security/tpm/tss/tcg-1.2/tss_internal.h @@ -1,7 +1,4 @@ -/* Copyright (c) 2010 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ #ifndef TCG_TSS_INTERNAL_H_ #define TCG_TSS_INTERNAL_H_ diff --git a/src/security/tpm/tss/tcg-1.2/tss_structures.h b/src/security/tpm/tss/tcg-1.2/tss_structures.h index 50fa3fbf0c..4a976c810d 100644 --- a/src/security/tpm/tss/tcg-1.2/tss_structures.h +++ b/src/security/tpm/tss/tcg-1.2/tss_structures.h @@ -1,7 +1,6 @@ -/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * +/* SPDX-License-Identifier: BSD-3-Clause */ + +/* * Some TPM constants and type definitions for standalone compilation for use * in the firmware */ diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index 49a6cea083..79d8eb91b4 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -1,9 +1,4 @@ -/* - * Copyright 2016 The Chromium OS Authors. All rights reserved. - * Copyright 2017-2019 Eltan B.V. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ #include #include diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index eff1acd2cd..f31c7d0178 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -1,9 +1,4 @@ -/* - * Copyright 2016 The Chromium OS Authors. All rights reserved. - * Copyright (c) 2018 Eltan B.V. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ #include #include diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.h b/src/security/tpm/tss/tcg-2.0/tss_marshaling.h index d34756d566..432cf5a382 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.h +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.h @@ -1,8 +1,5 @@ -/* - * Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ + #ifndef TCG2_TSS_MARSHALING_H_ #define TCG2_TSS_MARSHALING_H_ diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index 3f0c6545ab..f8c6012990 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -1,8 +1,4 @@ -/* - * Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ #ifndef TCG2_TSS_STRUCTURES_H_ #define TCG2_TSS_STRUCTURES_H_ diff --git a/src/security/tpm/tss/vendor/cr50/cr50.c b/src/security/tpm/tss/vendor/cr50/cr50.c index d7bf48d711..3be1e5a722 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.c +++ b/src/security/tpm/tss/vendor/cr50/cr50.c @@ -1,8 +1,4 @@ -/* - * Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ #include #include diff --git a/src/security/tpm/tss_errors.h b/src/security/tpm/tss_errors.h index ed6fc3d77c..7c4e569397 100644 --- a/src/security/tpm/tss_errors.h +++ b/src/security/tpm/tss_errors.h @@ -1,9 +1,7 @@ -/* Copyright (c) 2010 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ -/* TPM error codes. +/* + * TPM error codes. * * Copy-pasted and lightly edited from TCG TPM Main Part 2 TPM Structures * Version 1.2 Level 2 Revision 103 26 October 2006 Draft. From 10999ea6288e58922eaf364d691dce95bfcf460b Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Mon, 18 May 2020 13:36:58 -0600 Subject: [PATCH 246/405] drivers: Use SPDX identifiers Convert the remaining files in src/drivers to use SPDX identifiers. int15.h and default_brightness_levels.asl did not have license headers, but they were both copied from other GPL2 files, so they should be under the GPL2 as well. ne2k.c and drm_dp_helper.h are licensed under custom BSD-like licenses that do not have an SPDX equivalent, so they are added as exceptions to the license header lint. Change-Id: I87fb1c637b8d11b0463f7c19f70b847413e14aed Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/41601 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- LICENSES/retained-copyrights.txt | 2 ++ .../intel/gma/acpi/default_brightness_levels.asl | 2 ++ src/drivers/intel/gma/int15.h | 2 ++ src/drivers/net/ns8390.h | 4 ++-- src/drivers/vpd/vpd.c | 6 +----- src/drivers/vpd/vpd.h | 6 +----- src/drivers/vpd/vpd_decode.c | 6 ++---- src/drivers/vpd/vpd_decode.h | 6 ++---- src/drivers/vpd/vpd_tables.h | 10 +++------- util/lint/lint-000-license-headers | 2 ++ 10 files changed, 19 insertions(+), 27 deletions(-) diff --git a/LICENSES/retained-copyrights.txt b/LICENSES/retained-copyrights.txt index 066bf6f7d0..bfa9ecccb8 100644 --- a/LICENSES/retained-copyrights.txt +++ b/LICENSES/retained-copyrights.txt @@ -7,6 +7,7 @@ Copyright © 2012 Intel Corporation Copyright 2012 Red Hat Inc. Copyright 2013 Google Inc. Copyright 2014 Google Inc. +Copyright 2014 The Chromium OS Authors. All rights reserved. Copyright 2015 Google Inc. Copyright 2015, Google Inc. Copyright 2016 Jonathan Neuschäfer @@ -16,6 +17,7 @@ Copyright 2017 Google Inc. Copyright 2018 Generated Code Copyright 2018-present Facebook, Inc. Copyright 2019 9Elements Agency GmbH +Copyright 2019 The Chromium OS Authors. All rights reserved. Copyright (C) 2002 David S. Peterson. All rights reserved. Copyright (c) 2003-2016 Cavium Inc. (support@cavium.com). All rights Copyright (c) 2003-2017 Cavium Inc. (support@cavium.com). All rights diff --git a/src/drivers/intel/gma/acpi/default_brightness_levels.asl b/src/drivers/intel/gma/acpi/default_brightness_levels.asl index b584c0925a..9e8174109f 100644 --- a/src/drivers/intel/gma/acpi/default_brightness_levels.asl +++ b/src/drivers/intel/gma/acpi/default_brightness_levels.asl @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #include "gma.asl" Scope (GFX0) diff --git a/src/drivers/intel/gma/int15.h b/src/drivers/intel/gma/int15.h index 176ae24bf1..559ec22ab1 100644 --- a/src/drivers/intel/gma/int15.h +++ b/src/drivers/intel/gma/int15.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + int intel_vga_int15_handler(void); enum { diff --git a/src/drivers/net/ns8390.h b/src/drivers/net/ns8390.h index 23a68a089d..635a0304bf 100644 --- a/src/drivers/net/ns8390.h +++ b/src/drivers/net/ns8390.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /************************************************************************** ETHERBOOT - BOOTP/TFTP Bootstrap Program @@ -6,8 +8,6 @@ Author: Martin Renters **************************************************************************/ -//FILE_LICENCE ( BSD2 ); - #define VENDOR_NONE 0 #define VENDOR_WD 1 #define VENDOR_NOVELL 2 diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c index 7ed1255357..7314c35025 100644 --- a/src/drivers/vpd/vpd.c +++ b/src/drivers/vpd/vpd.c @@ -1,8 +1,4 @@ -/* - * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ #include #include diff --git a/src/drivers/vpd/vpd.h b/src/drivers/vpd/vpd.h index 05b7db8f6d..a78662579a 100644 --- a/src/drivers/vpd/vpd.h +++ b/src/drivers/vpd/vpd.h @@ -1,8 +1,4 @@ -/* - * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ +/* SPDX-License-Identifier: BSD-3-Clause */ #ifndef __VPD_H__ #define __VPD_H__ diff --git a/src/drivers/vpd/vpd_decode.c b/src/drivers/vpd/vpd_decode.c index 527c50818e..944e21b2a7 100644 --- a/src/drivers/vpd/vpd_decode.c +++ b/src/drivers/vpd/vpd_decode.c @@ -1,8 +1,6 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /* - * Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * * This is a copy from upstream: * https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/lib/vpd_decode.c */ diff --git a/src/drivers/vpd/vpd_decode.h b/src/drivers/vpd/vpd_decode.h index 5d595f367f..d96a21000c 100644 --- a/src/drivers/vpd/vpd_decode.h +++ b/src/drivers/vpd/vpd_decode.h @@ -1,8 +1,6 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /* - * Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * * This is a copy from upstream: * https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/include/lib/vpd_decode.h */ diff --git a/src/drivers/vpd/vpd_tables.h b/src/drivers/vpd/vpd_tables.h index 4add5bd49d..54f1685e10 100644 --- a/src/drivers/vpd/vpd_tables.h +++ b/src/drivers/vpd/vpd_tables.h @@ -1,10 +1,6 @@ -/* - * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Ported from mosys project (http://code.google.com/p/mosys/). - */ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/* Ported from mosys project (http://code.google.com/p/mosys/). */ #ifndef __LIB_VPD_TABLES_H__ #define __LIB_VPD_TABLES_H__ diff --git a/util/lint/lint-000-license-headers b/util/lint/lint-000-license-headers index 12654e4f59..eb14a94632 100755 --- a/util/lint/lint-000-license-headers +++ b/util/lint/lint-000-license-headers @@ -12,6 +12,8 @@ HEADER_EXCLUDED="\ ^src/device/oprom/x86emu/|\ ^src/device/oprom/include/x86emu/|\ ^src/device/oprom/yabel/|\ +^src/drivers/intel/gma/drm_dp_helper.h\$|\ +^src/drivers/net/ne2k.c\$|\ ^src/drivers/xgi/common/initdef.h\$|\ ^src/drivers/xgi/common/vstruct.h\$|\ ^src/lib/gnat/|\ From 56f5cc7ee3dbdd258f14a9148918ec8aad10d50c Mon Sep 17 00:00:00 2001 From: Da Lao Date: Sun, 5 Apr 2020 00:23:09 +0800 Subject: [PATCH 247/405] ec/lenovo/h8: Config the ec hardware ids for newer thinkpads Currently coreboot is using the ec hardware id IBM0068 for all thinkpads, but for newer thinkpads the id maybe LEN0068 or LEN0268. On Windows, the Lenovo Vantage app can't get battery details when using IBM0068. This patch config this id by motherboard. The hardware IDs for the following models can be found by searching for disassembled dsdt.asl on vendor BIOS: (But this info is not easy to find online. So I only changed some of the thinkpads.) T420: https://github.com/tluck/Lenovo-T420-Clover/blob/master/EFI/CLOVER/ACPI/1600x900-EDID/DSDT.edid-2e2-hs.dsl LEN0068 T430: https://github.com/ThiagoSchetini/macosx-thinkpad-t430/blob/master/vanilla%20ACPI%20dsl's/DSDT.dsl LEN0068 T520: Confirmed by Patrick Rudolph LEN0068 W520: Confirmed by Patrick Rudolph LEN0068 T530: Confirmed by Prasun Gera LEN0068 W530: https://bugzilla.kernel.org/show_bug.cgi?id=66731 LEN0068 X230/X230T: https://github.com/tuandzung/ThinkPad-X230-macOS-10.12.x/blob/master/DSDT/DSDT.dsl LEN0068 T440p: https://github.com/doudou/t440p/blob/master/acpi/2.30/dsdt.dsl LEN0068 Signed-off-by: Da Lao Change-Id: I797080ec8ba7ce39d47fe587319f8f32d6938875 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40128 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/ec/lenovo/h8/Kconfig | 7 +++++++ src/ec/lenovo/h8/acpi/thinkpad.asl | 2 +- src/mainboard/lenovo/t420/Kconfig | 3 +++ src/mainboard/lenovo/t430/Kconfig | 3 +++ src/mainboard/lenovo/t440p/Kconfig | 3 +++ src/mainboard/lenovo/t520/Kconfig | 3 +++ src/mainboard/lenovo/t530/Kconfig | 3 +++ src/mainboard/lenovo/x230/Kconfig | 3 +++ 8 files changed, 26 insertions(+), 1 deletion(-) diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig index 6bd290f50e..2ea4faa9e2 100644 --- a/src/ec/lenovo/h8/Kconfig +++ b/src/ec/lenovo/h8/Kconfig @@ -44,4 +44,11 @@ config H8_HAS_PRIMARY_FN_KEYS bool default n +config THINKPADEC_HKEY_EISAID + string + default "IBM0068" + help + Motherboards of newer thinkpad models can override the default to match + vendor drivers and quirks. + endif # EC_LENOVO_H8 diff --git a/src/ec/lenovo/h8/acpi/thinkpad.asl b/src/ec/lenovo/h8/acpi/thinkpad.asl index 0b8ca15eb2..eca0d4471d 100644 --- a/src/ec/lenovo/h8/acpi/thinkpad.asl +++ b/src/ec/lenovo/h8/acpi/thinkpad.asl @@ -8,7 +8,7 @@ Device (HKEY) External (\HKBL, IntObj) External (\HUWB, IntObj) - Name (_HID, EisaId ("IBM0068")) + Name (_HID, EisaId (CONFIG_THINKPADEC_HKEY_EISAID)) Name (BTN, 0) diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index dfc8ed1d61..182ca46d58 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -81,4 +81,7 @@ config PS2K_EISAID config PS2M_EISAID default "LEN0015" +config THINKPADEC_HKEY_EISAID + default "LEN0068" + endif # BOARD_LENOVO_T420 diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index 45c7ae307a..6139452e86 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -75,4 +75,7 @@ config PS2K_EISAID config PS2M_EISAID default "LEN0015" +config THINKPADEC_HKEY_EISAID + default "LEN0068" + endif diff --git a/src/mainboard/lenovo/t440p/Kconfig b/src/mainboard/lenovo/t440p/Kconfig index e6785488df..7310dc106b 100644 --- a/src/mainboard/lenovo/t440p/Kconfig +++ b/src/mainboard/lenovo/t440p/Kconfig @@ -76,4 +76,7 @@ config PS2K_EISAID config PS2M_EISAID default "LEN0036" +config THINKPADEC_HKEY_EISAID + default "LEN0068" + endif diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index aebb2dee46..3529367d3f 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -90,4 +90,7 @@ config PS2K_EISAID config PS2M_EISAID default "LEN0015" +config THINKPADEC_HKEY_EISAID + default "LEN0068" + endif diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 2a0e3ea039..4dc77e9266 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -91,4 +91,7 @@ config PS2K_EISAID config PS2M_EISAID default "LEN0015" +config THINKPADEC_HKEY_EISAID + default "LEN0068" + endif diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 37b264dab2..f134bc863c 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -89,4 +89,7 @@ config PS2K_EISAID config PS2M_EISAID default "LEN0020" +config THINKPADEC_HKEY_EISAID + default "LEN0068" + endif # BOARD_LENOVO_X230 || BOARD_LENOVO_X230T From 641221c0a155cc0c601839791efbce578f671199 Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Thu, 14 May 2020 16:21:18 +0530 Subject: [PATCH 248/405] soc/intel/jasperlake: correct IRQ routing Jasper Lake Current Interrupt setting use 2nd parameters as device function number. Correct as interrupt pin number according to _PRT package format. {Address, pin, Source, Source index} Reference: - ACPI spec 6.2.13 _PRT BUG=None BRANCH=None TEST=Build and boot JSLRVP Verify Interrupt mappings are same as PCI INTR(0x3C) register and no interrupt storm is seen Change-Id: I21462c6befea310a49eecf9ad1b5c8770eccd5bd Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/41404 Reviewed-by: Karthik Ramasubramanian Reviewed-by: Aamir Bohra Reviewed-by: Maulik V Vaghela Tested-by: build bot (Jenkins) --- src/soc/intel/jasperlake/acpi/pci_irqs.asl | 178 ++++++++++----------- src/soc/intel/jasperlake/include/soc/irq.h | 58 ++----- 2 files changed, 91 insertions(+), 145 deletions(-) diff --git a/src/soc/intel/jasperlake/acpi/pci_irqs.asl b/src/soc/intel/jasperlake/acpi/pci_irqs.asl index 04bb615aa9..aa494a76f9 100644 --- a/src/soc/intel/jasperlake/acpi/pci_irqs.asl +++ b/src/soc/intel/jasperlake/acpi/pci_irqs.asl @@ -3,119 +3,103 @@ #include Name (PICP, Package () { - /* cAVS, SMBus, GbE, Northpeak */ - Package(){0x001FFFFF, 3, 0, cAVS_INTA_IRQ }, - Package(){0x001FFFFF, 4, 0, SMBUS_INTB_IRQ }, - Package(){0x001FFFFF, 6, 0, GbE_INTC_IRQ }, - Package(){0x001FFFFF, 7, 0, TRACE_HUB_INTD_IRQ }, - /* SerialIo */ + Package(){0x001FFFFF, 0, 0, PCH_IRQ_16 }, + Package(){0x001FFFFF, 1, 0, PCH_IRQ_17 }, + Package(){0x001FFFFF, 2, 0, PCH_IRQ_18 }, + Package(){0x001FFFFF, 3, 0, PCH_IRQ_19 }, + Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, - /* PCI Express Port 1-8 */ - Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, - Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, - Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, - Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, - Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ }, - Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ }, - Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ }, - Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ }, - /* eMMC */ - Package(){0x001AFFFF, 0, 0, eMMC_IRQ }, - /* SerialIo */ + + Package(){0x001CFFFF, 0, 0, PCH_IRQ_16 }, + Package(){0x001CFFFF, 1, 0, PCH_IRQ_17 }, + Package(){0x001CFFFF, 2, 0, PCH_IRQ_18 }, + Package(){0x001CFFFF, 3, 0, PCH_IRQ_19 }, + + Package(){0x001AFFFF, 0, 0, PCH_IRQ_16 }, + Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, - /* SATA controller */ - Package(){0x0017FFFF, 0, 0, SATA_IRQ }, - /* CSME (HECI, IDE-R, Keyboard and Text redirection */ - Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, - Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, - Package(){0x0016FFFF, 2, 0, IDER_IRQ }, - Package(){0x0016FFFF, 3, 0, KT_IRQ }, - Package(){0x0016FFFF, 4, 0, HECI_3_IRQ }, - Package(){0x0016FFFF, 5, 0, HECI_4_IRQ }, - /* SerialIo */ + + Package(){0x0017FFFF, 0, 0, PCH_IRQ_16 }, + + Package(){0x0016FFFF, 0, 0, PCH_IRQ_16 }, + Package(){0x0016FFFF, 1, 0, PCH_IRQ_17 }, + Package(){0x0016FFFF, 2, 0, PCH_IRQ_18 }, + Package(){0x0016FFFF, 3, 0, PCH_IRQ_19 }, + Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, - /* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */ - Package(){0x0014FFFF, 0, 0, XHCI_IRQ }, - Package(){0x0014FFFF, 1, 0, OTG_IRQ }, - Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ }, - Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ }, - Package(){0x0014FFFF, 5, 0, SD_IRQ }, - /* SerialIo */ - Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ }, - /* SA IGFX Device */ - Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, - /* SA Thermal Device */ - Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ }, - /* SA IPU Device */ - Package(){0x0005FFFF, 0, 0, IPU_IRQ }, + + Package(){0x0014FFFF, 0, 0, PCH_IRQ_16 }, + Package(){0x0014FFFF, 1, 0, PCH_IRQ_17 }, + Package(){0x0014FFFF, 2, 0, PCH_IRQ_18 }, + Package(){0x0014FFFF, 3, 0, PCH_IRQ_19 }, + + Package(){0x0012FFFF, 1, 0, LPSS_SPI2_IRQ }, /* SA GNA Device */ - Package(){0x0008FFFF, 0, 0, GNA_IRQ }, + Package(){0x0008FFFF, 0, 0, PCH_IRQ_16 }, + /* SA IPU Device */ + Package(){0x0005FFFF, 0, 0, PCH_IRQ_16 }, + /* SA Thermal Device */ + Package(){0x0004FFFF, 0, 0, PCH_IRQ_16 }, + /* SA IGFX Device */ + Package(){0x0002FFFF, 0, 0, PCH_IRQ_16 }, }) Name (PICN, Package () { - /* D31: cAVS, SMBus, GbE, Northpeak */ - Package () { 0x001FFFFF, 3, 0, 11 }, - Package () { 0x001FFFFF, 4, 0, 10 }, - Package () { 0x001FFFFF, 6, 0, 11 }, - Package () { 0x001FFFFF, 7, 0, 11 }, - /* D30: SerialIo */ - Package () {0x001EFFFF, 0, 0, 11 }, - Package () {0x001EFFFF, 1, 0, 10 }, - Package () {0x001EFFFF, 2, 0, 11 }, - Package () {0x001EFFFF, 3, 0, 11 }, - /* D28: PCI Express Port 1-8 */ - Package () { 0x001CFFFF, 0, 0, 11 }, - Package () { 0x001CFFFF, 1, 0, 10 }, - Package () { 0x001CFFFF, 2, 0, 11 }, - Package () { 0x001CFFFF, 3, 0, 11 }, - Package () { 0x001CFFFF, 4, 0, 11 }, - Package () { 0x001CFFFF, 5, 0, 10 }, - Package () { 0x001CFFFF, 6, 0, 11 }, - Package () { 0x001CFFFF, 7, 0, 11 }, - /* D26: eMMC */ - Package(){0x001AFFFF, 0, 0, 11 }, - /* D25: SerialIo */ - Package () {0x0019FFFF, 0, 0, 11 }, - Package () {0x0019FFFF, 1, 0, 10 }, - Package () {0x0019FFFF, 2, 0, 11 }, - /* D23: SATA controller */ - Package () { 0x0017FFFF, 0, 0, 11 }, - /* D22: CSME (HECI, IDE-R, KT redirection */ - Package () { 0x0016FFFF, 0, 0, 11 }, - Package () { 0x0016FFFF, 1, 0, 10 }, - Package () { 0x0016FFFF, 2, 0, 11 }, - Package () { 0x0016FFFF, 3, 0, 11 }, - Package () { 0x0016FFFF, 4, 0, 11 }, - Package () { 0x0016FFFF, 5, 0, 11 }, - /* D21: SerialIo */ - Package () {0x0015FFFF, 0, 0, 11 }, - Package () {0x0015FFFF, 1, 0, 10 }, - Package () {0x0015FFFF, 2, 0, 11 }, - Package () {0x0015FFFF, 3, 0, 11 }, - /* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */ - Package () { 0x0014FFFF, 0, 0, 11 }, - Package () { 0x0014FFFF, 1, 0, 10 }, - Package () { 0x0014FFFF, 2, 0, 11 }, - Package () { 0x0014FFFF, 3, 0, 11 }, - Package () { 0x0014FFFF, 5, 0, 11 }, - /* D18: SerialIo */ - Package () {0x0012FFFF, 6, 0, 11 }, - /* SA IGFX Device */ - Package () {0x0002FFFF, 0, 0, 11 }, - /* SA Thermal Device */ - Package () { 0x0004FFFF, 0, 0, 11 }, - /* SA IPU Device */ - Package () { 0x0005FFFF, 0, 0, 11 }, + Package () { 0x001FFFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x001FFFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x001FFFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x001FFFFF, 3, 0, PCH_IRQ11 }, + + Package () { 0x001EFFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x001EFFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x001EFFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x001EFFFF, 3, 0, PCH_IRQ11 }, + + Package () { 0x001CFFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x001CFFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x001CFFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x001CFFFF, 3, 0, PCH_IRQ11 }, + + Package () { 0x001AFFFF, 0, 0, PCH_IRQ11 }, + + Package () { 0x0019FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0019FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0019FFFF, 2, 0, PCH_IRQ11 }, + + Package () { 0x0017FFFF, 0, 0, PCH_IRQ11 }, + + Package () { 0x0016FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0016FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0016FFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x0016FFFF, 3, 0, PCH_IRQ11 }, + + Package () { 0x0015FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0015FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0015FFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x0015FFFF, 3, 0, PCH_IRQ11 }, + + Package () { 0x0014FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0014FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0014FFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x0014FFFF, 3, 0, PCH_IRQ11 }, + + Package () { 0x0012FFFF, 1, 0, PCH_IRQ10 }, /* SA GNA Device */ - Package () { 0x0008FFFF, 0, 0, 11 }, + Package () { 0x0008FFFF, 0, 0, PCH_IRQ11 }, + /* SA IPU Device */ + Package () { 0x0005FFFF, 0, 0, PCH_IRQ11 }, + /* SA Thermal Device */ + Package () { 0x0004FFFF, 0, 0, PCH_IRQ11 }, + /* SA IGFX Device */ + Package () { 0x0002FFFF, 0, 0, PCH_IRQ11 }, }) Method (_PRT) diff --git a/src/soc/intel/jasperlake/include/soc/irq.h b/src/soc/intel/jasperlake/include/soc/irq.h index beee7350b3..19033293ec 100644 --- a/src/soc/intel/jasperlake/include/soc/irq.h +++ b/src/soc/intel/jasperlake/include/soc/irq.h @@ -9,7 +9,7 @@ #define PCH_IRQ10 10 #define PCH_IRQ11 11 -/* LPSS Devices */ +/* LPSS Device IRQs */ #define LPSS_I2C0_IRQ 16 #define LPSS_I2C1_IRQ 17 #define LPSS_I2C2_IRQ 18 @@ -23,52 +23,14 @@ #define LPSS_UART1_IRQ 21 #define LPSS_UART2_IRQ 34 -/* PCI D:31 F:x */ -#define cAVS_INTA_IRQ 16 -#define SMBUS_INTA_IRQ 16 -#define SMBUS_INTB_IRQ 17 -#define GbE_INTA_IRQ 16 -#define GbE_INTC_IRQ 18 -#define TRACE_HUB_INTA_IRQ 16 -#define TRACE_HUB_INTD_IRQ 19 - -/* PCI D:28 F:x */ -#define PCIE_1_IRQ 16 -#define PCIE_2_IRQ 17 -#define PCIE_3_IRQ 18 -#define PCIE_4_IRQ 19 -#define PCIE_5_IRQ 16 -#define PCIE_6_IRQ 17 -#define PCIE_7_IRQ 18 -#define PCIE_8_IRQ 19 - -/* PCI D:26 F:x */ -#define eMMC_IRQ 16 - -/* PCI D:23 F:x */ -#define SATA_IRQ 16 - -/* PCI D:22 F:x */ -#define HECI_1_IRQ 16 -#define HECI_2_IRQ 17 -#define HECI_3_IRQ 16 -#define HECI_4_IRQ 19 -#define IDER_IRQ 18 -#define KT_IRQ 19 - -/* PCI D:20 F:x */ -#define XHCI_IRQ 16 -#define OTG_IRQ 17 -#define CNViWIFI_IRQ 16 -#define SD_IRQ 19 -#define PMC_SRAM_IRQ 18 - -/* PCI D:18 F:x */ -#define UFS_IRQ 16 - -#define IGFX_IRQ 16 -#define SA_THERMAL_IRQ 16 -#define IPU_IRQ 16 -#define GNA_IRQ 16 +/* PCI shared IRQs */ +#define PCH_IRQ_16 16 +#define PCH_IRQ_17 17 +#define PCH_IRQ_18 18 +#define PCH_IRQ_19 19 +#define PCH_IRQ_20 20 +#define PCH_IRQ_21 21 +#define PCH_IRQ_22 22 +#define PCH_IRQ_23 23 #endif /* _JSL_IRQ_H_ */ From 39ea0eab411b1ad7acff00e48d5520f351e868ac Mon Sep 17 00:00:00 2001 From: "Pandya, Varshit B" Date: Thu, 19 Mar 2020 16:10:54 +0530 Subject: [PATCH 249/405] mb/intel/jasperlake_rvp: Add world facing camera support 1. Configure GPIOs as per schematics 2. Add 1 Ports and 1 Endpoints 3. Add support for OTVI5675 WFC is on I2C5 with VCM support and using 2 data-lanes BUG=None BRANCH=None TEST=Build and Boot jslrvp board and able to capture image using world facing camera. Change-Id: I07ae9e3473c16bde8eb1597460e70cc478357b98 Signed-off-by: Pandya, Varshit B Reviewed-on: https://review.coreboot.org/c/coreboot/+/39669 Tested-by: build bot (Jenkins) Reviewed-by: Ronak Kanabar Reviewed-by: Maulik V Vaghela Reviewed-by: Aamir Bohra --- .../intel/jasperlake_rvp/Makefile.inc | 1 + src/mainboard/intel/jasperlake_rvp/dsdt.asl | 17 +- .../baseboard/include/baseboard/acpi/cam1.asl | 226 ++++++++++++++++++ .../include/baseboard/acpi/camera.asl | 5 + .../include/baseboard/acpi/ipu_endpoints.asl | 44 ++++ .../include/baseboard/acpi/ipu_mainboard.asl | 50 ++++ .../variants/jslrvp/devicetree.cb | 16 +- .../jasperlake_rvp/variants/jslrvp/gpio.c | 17 +- .../jslrvp/include/variant/acpi/camera.asl | 3 + 9 files changed, 365 insertions(+), 14 deletions(-) create mode 100644 src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam1.asl create mode 100644 src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl create mode 100644 src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl create mode 100644 src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl create mode 100644 src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include/variant/acpi/camera.asl diff --git a/src/mainboard/intel/jasperlake_rvp/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/Makefile.inc index 20b3be4bd9..c1fde4969c 100644 --- a/src/mainboard/intel/jasperlake_rvp/Makefile.inc +++ b/src/mainboard/intel/jasperlake_rvp/Makefile.inc @@ -19,6 +19,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c subdirs-y += ../common subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index 3e45cca168..f47424f996 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -36,15 +36,18 @@ DefinitionBlock( #if CONFIG(EC_GOOGLE_CHROMEEC) /* Chrome OS Embedded Controller */ - Scope (\_SB.PCI0.LPCB) - { - /* ACPI code for EC SuperIO functions */ - #include - /* ACPI code for EC functions */ - #include - } + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include + /* ACPI code for EC functions */ + #include + } #endif + /* Camera */ + #include + #include /* Mainboard specific */ diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam1.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam1.asl new file mode 100644 index 0000000000..14139981a9 --- /dev/null +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam1.asl @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.I2C5) +{ + PowerResource (FCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) /* _ON_: Power On */ + { + If ((STA == Zero)) + { + /* Enable CLK1 */ + MCON(1, 1) // Clock 1, 19.2MHz + /* Pull PWREN(GPIO R6) high */ + STXS(GPP_D4) + Sleep(5) /* 5 us */ + /* Pull RST(GPIO H12) low */ + CTXS(GPP_C19) + Sleep(5) /* 5 us */ + /* Pull RST high */ + STXS(GPP_C19) + Sleep(5) /* 5 us */ + STA = 1 + } + } + + Method (_OFF, 0, Serialized) /* _OFF: Power Off */ + { + If ((STA == One)) + { + /* Pull RST low */ + CTXS(GPP_C19) + /* Pull PWREN low */ + CTXS(GPP_D4) + /* Disable CLK0 */ + MCOF(1) /* Clock 1 */ + STA = 0 + } + } + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + + Device (CAM1) + { + Name (_HID, "OVTI5675") /* _HID: Hardware ID */ + + Name (_UID, Zero) /* _UID: Unique ID */ + + Name (_DDN, "Ov 5675 Camera") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C5", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + FCPR + }) + + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + FCPR + }) + + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x02) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + + Package (0x02) + { + "lens-focus", + Package (0x01) + { + VCM0 + } + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02 + } + }, + + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x1AD27480 + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + One, + Zero + } + } + } + }) + } + + Device (VCM0) + { + Name (_HID, "PRP0001") /* _HID: Hadware ID */ + + Name (_UID, 0x03) /* _UID: Unique ID */ + + Name (_DDN, "DW9714 VCM") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Setting */ + { + I2cSerialBusV2 (0x000C, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C5", + 0x00, ResourceConsumer, , Exclusive, + ) + }) + + Name (_DEP, Package (0x01) /* _DEP: Dependencies */ + { + CAM1 + }) + + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + FCPR + }) + + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3Hot */ + { + FCPR + }) + + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), /* Device Properties for _DSD */ + Package(0x01) + { + Package (0x02) + { + "compatible", + "dongwoon,dw9714" + } + } + }) + } +} diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl new file mode 100644 index 0000000000..48650c9360 --- /dev/null +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "ipu_mainboard.asl" +#include "ipu_endpoints.asl" +#include "cam1.asl" diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl new file mode 100644 index 0000000000..cebf15e753 --- /dev/null +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (_SB.PCI0.IPU0) +{ + Name (EP10, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02, + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C5.CAM1, + Zero, + Zero + } + } + } + }) +} diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl new file mode 100644 index 0000000000..013b26f3c6 --- /dev/null +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0) +{ + Device (IPU0) + { + Name (_ADR, 0x00050000) // _ADR: Address + + Name (_DDN, "Camera and Imaging Subsystem") // _DDN: DOS Device Name + } +} + +Scope (\_SB.PCI0.IPU0) +{ + Name (_DSD, Package (0x02) // _DSD: Device-Specific Data + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port1", + "PRT1" + } + } + }) + + Name (PRT1, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 2 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP10" + } + } + }) +} diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 1e88c7ae62..14ca4a5abd 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -137,7 +137,7 @@ chip soc/intel/jasperlake .speed_mhz = 1, .early_init = 1, }, - .i2c[0] = { + .i2c[0] = { .speed = I2C_SPEED_FAST, .speed_config[0] = { .speed = I2C_SPEED_FAST, @@ -146,13 +146,17 @@ chip soc/intel/jasperlake .sda_hold = 36, } }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, }" device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device - device pci 12.0 off end # Thermal Subsystem + device pci 04.0 off end # SA Thermal device + device pci 05.0 on end #IPU + device pci 12.0 off end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 device pci 14.0 on @@ -285,8 +289,8 @@ chip soc/intel/jasperlake device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 off end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 + device pci 19.0 off end # I2C #4 Cam 0 + device pci 19.1 on end # I2C #5 Cam 1 and VCM device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC device pci 1c.0 on end # PCI Express Port 1 @@ -308,7 +312,7 @@ chip soc/intel/jasperlake device spi 0 on end end end # GSPI #1 - device pci 1f.0 on end # eSPI Interface + device pci 1f.0 on end # eSPI Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel HDA diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c index 5a127a6ebf..d67f4a44e4 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c @@ -64,13 +64,19 @@ static const struct pad_config gpio_table[] = { /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, UP_2K, DEEP, NF1), + /* CAM2_RST_N */ + PAD_CFG_GPO(GPP_C19, 0, PLTRST), + /* WIFI_RF_KILL_N */ PAD_CFG_GPO(GPP_D0, 1, PLTRST), /* BT_RF_KILL_N */ PAD_CFG_GPO(GPP_D1, 1, PLTRST), - /* LAN_RST_N */ + /* CAM2_PWREN */ + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + + /*LAN_RST_N*/ PAD_CFG_GPO(GPP_D6, 1, PLTRST), /* AVS_I2S_MCLK */ @@ -85,6 +91,15 @@ static const struct pad_config gpio_table[] = { /* CNV_PA_BLANKING */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), + /* I2C5_SDA */ + PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1), + + /* I2C5_SCL */ + PAD_CFG_NF(GPP_D23, NONE, PLTRST, NF1), + + /* IMGCLKOUT_1 */ + PAD_CFG_NF(GPP_E2, NONE, PLTRST, NF1), + /* WWAN_FCP_OFF_N */ PAD_CFG_GPO(GPP_E3, 1, PLTRST), diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include/variant/acpi/camera.asl b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include/variant/acpi/camera.asl new file mode 100644 index 0000000000..318b0dea04 --- /dev/null +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include/variant/acpi/camera.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include From 477b4f8886bd5bca8a6c26035e0ab20a8709298a Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 28 Apr 2020 08:25:45 +0200 Subject: [PATCH 250/405] mb/lenovo/t410: Set default CBFS size Set the default CBFS size to cover the whole BIOS region. Change-Id: If719a9cd2897d933df53bd423e71503b832411fe Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/40776 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Christian Walter Reviewed-by: Arthur Heymans --- src/mainboard/lenovo/t410/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig index ee79f11e61..e939234db6 100644 --- a/src/mainboard/lenovo/t410/Kconfig +++ b/src/mainboard/lenovo/t410/Kconfig @@ -39,6 +39,9 @@ config VBOOT_VBNV_OFFSET hex default 0x2a +config CBFS_SIZE + default 0x300000 + config FMDFILE string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT From 927f6ae84a7b59b630250a7e559aac1eb05ae2f5 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 20 May 2020 23:19:17 +0200 Subject: [PATCH 251/405] mb/*/*/buildOpts.c: Drop BLDCFG_IR_PIN_CONTROL This does not exist anywhere in the entire coreboot tree. Drop it. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: I80320a20f4b44896e72d701a1d98786cb3a93dcc Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41588 Tested-by: build bot (Jenkins) Reviewed-by: Mike Banon Reviewed-by: Krystian Hebel --- src/mainboard/amd/olivehill/buildOpts.c | 1 - src/mainboard/amd/parmer/buildOpts.c | 1 - src/mainboard/amd/thatcher/buildOpts.c | 1 - src/mainboard/asrock/imb-a180/buildOpts.c | 1 - src/mainboard/asus/am1i-a/buildOpts.c | 1 - src/mainboard/asus/f2a85-m/buildOpts.c | 1 - src/mainboard/bap/ode_e20XX/buildOpts.c | 1 - src/mainboard/biostar/a68n_5200/buildOpts.c | 1 - src/mainboard/biostar/am1ml/buildOpts.c | 1 - src/mainboard/gizmosphere/gizmo2/buildOpts.c | 1 - src/mainboard/hp/abm/buildOpts.c | 1 - src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 1 - src/mainboard/lenovo/g505s/buildOpts.c | 1 - src/mainboard/msi/ms7721/buildOpts.c | 1 - 14 files changed, 14 deletions(-) diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index 78a5596b93..fd61756a23 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -306,7 +306,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 GPIO_CONTROL olivehill_gpio[] = { {183, Function1, GpioIn | GpioOutEnB | PullUpB}, diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index bf610672ba..c46657df02 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -307,7 +307,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 GPIO_CONTROL parmer_gpio[] = { {183, Function1, GpioIn | GpioOutEnB | PullUpB}, diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index de1f89fb0a..915f792159 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -307,7 +307,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 #define FCH_NO_XHCI_SUPPORT TRUE GPIO_CONTROL thatcher_gpio[] = { {183, Function1, PullUpB}, diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c index 4ed3a890fa..9fc4a43fc3 100644 --- a/src/mainboard/asrock/imb-a180/buildOpts.c +++ b/src/mainboard/asrock/imb-a180/buildOpts.c @@ -306,7 +306,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 GPIO_CONTROL imba180_gpio[] = { {183, Function1, GpioIn | GpioOutEnB | PullUpB}, diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index bbe16424f2..49fcb22b2a 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -318,7 +318,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 GPIO_CONTROL imba180_gpio[] = { {183, Function1, GpioIn | GpioOutEnB | PullUpB}, diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 29a717dcde..e2fe66cfdb 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -309,7 +309,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 //#define FCH_NO_XHCI_SUPPORT FALSE GPIO_CONTROL f2a85_m_gpio[] = { // {183, Function1, PullUpB}, diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c index f2956a12ad..ec4e17e655 100644 --- a/src/mainboard/bap/ode_e20XX/buildOpts.c +++ b/src/mainboard/bap/ode_e20XX/buildOpts.c @@ -305,7 +305,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 GPIO_CONTROL gizmo2_gpio[] = { {183, Function1, GpioIn | GpioOutEnB | PullUpB}, diff --git a/src/mainboard/biostar/a68n_5200/buildOpts.c b/src/mainboard/biostar/a68n_5200/buildOpts.c index 78a5596b93..fd61756a23 100644 --- a/src/mainboard/biostar/a68n_5200/buildOpts.c +++ b/src/mainboard/biostar/a68n_5200/buildOpts.c @@ -306,7 +306,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 GPIO_CONTROL olivehill_gpio[] = { {183, Function1, GpioIn | GpioOutEnB | PullUpB}, diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c index b25be51aa2..8cc90ddb3e 100644 --- a/src/mainboard/biostar/am1ml/buildOpts.c +++ b/src/mainboard/biostar/am1ml/buildOpts.c @@ -306,7 +306,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 GPIO_CONTROL imba180_gpio[] = { {183, Function1, GpioIn | GpioOutEnB | PullUpB}, diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c index f2956a12ad..ec4e17e655 100644 --- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c @@ -305,7 +305,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 GPIO_CONTROL gizmo2_gpio[] = { {183, Function1, GpioIn | GpioOutEnB | PullUpB}, diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index 337d35cf7a..05ed0147aa 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -310,7 +310,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 GPIO_CONTROL hp_abm_gpio[] = { { 45, Function2, GpioOutEnB | Sticky }, // Signal input APU_SD_LED diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 989df12da0..c46ba74f82 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -309,7 +309,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 /* * The GPIO control is not well documented in AGESA, but is in the BKDG diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index 70ac8259f0..6351aeedbb 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -309,7 +309,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 /* * The GPIO control is not well documented in AGESA, but is in the BKDG diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index ce55623e7c..d7e8c85a32 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -309,7 +309,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define BLDCFG_IR_PIN_CONTROL 0x33 //#define FCH_NO_XHCI_SUPPORT FALSE GPIO_CONTROL ms7721_m_gpio[] = { // {183, Function1, PullUpB}, From 66ee42daba635a0748262092b28a3ee87bbfd573 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 20 May 2020 23:34:54 +0200 Subject: [PATCH 252/405] mb/*/*/buildOpts.c: Clean up whitespace Drop multiple blank lines and use one space inside C-style comments. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Ibe1f279dd22ae7657ea7b7766f88004dbf4dceb5 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41589 Tested-by: build bot (Jenkins) Reviewed-by: Mike Banon Reviewed-by: Krystian Hebel --- src/mainboard/amd/inagua/buildOpts.c | 8 ++------ src/mainboard/amd/olivehill/buildOpts.c | 9 +++------ src/mainboard/amd/parmer/buildOpts.c | 14 ++++++-------- src/mainboard/amd/persimmon/buildOpts.c | 12 ++++-------- src/mainboard/amd/south_station/buildOpts.c | 12 ++++-------- src/mainboard/amd/thatcher/buildOpts.c | 14 ++++++-------- src/mainboard/amd/union_station/buildOpts.c | 12 ++++-------- src/mainboard/asrock/e350m1/buildOpts.c | 9 +++------ src/mainboard/asrock/imb-a180/buildOpts.c | 9 +++------ src/mainboard/asus/am1i-a/buildOpts.c | 12 +++++------- src/mainboard/asus/f2a85-m/buildOpts.c | 15 ++++++--------- src/mainboard/bap/ode_e20XX/buildOpts.c | 8 +++----- src/mainboard/biostar/a68n_5200/buildOpts.c | 9 +++------ src/mainboard/biostar/am1ml/buildOpts.c | 9 +++------ src/mainboard/elmex/pcm205400/buildOpts.c | 12 ++++-------- src/mainboard/gizmosphere/gizmo/buildOpts.c | 13 ++++--------- src/mainboard/gizmosphere/gizmo2/buildOpts.c | 8 +++----- src/mainboard/hp/abm/buildOpts.c | 8 +++----- src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 16 ++++++---------- src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 6 +----- src/mainboard/lenovo/g505s/buildOpts.c | 8 ++------ src/mainboard/lippert/frontrunner-af/buildOpts.c | 13 ++++--------- src/mainboard/lippert/toucan-af/buildOpts.c | 13 ++++--------- src/mainboard/msi/ms7721/buildOpts.c | 15 ++++++--------- src/mainboard/pcengines/apu1/buildOpts.c | 12 ++++-------- 25 files changed, 96 insertions(+), 180 deletions(-) diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index b9d6a2cc3d..e9f1e7120f 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -9,11 +9,8 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ - - /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE @@ -85,7 +82,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE - #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -206,7 +202,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { CPU_LIST_TERMINAL } }; -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" @@ -252,7 +248,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DDR1866_FREQUENCY 933 ///< DDR 1866 #define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency -/* QUANDRANK_TYPE*/ +/* QUANDRANK_TYPE */ #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index fd61756a23..1712708635 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -9,7 +9,6 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ #include @@ -29,7 +28,6 @@ #define INSTALL_AM3_SOCKET_SUPPORT FALSE #define INSTALL_FM2_SOCKET_SUPPORT FALSE - #ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE #undef INSTALL_FT3_SOCKET_SUPPORT @@ -152,7 +150,7 @@ #define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' #define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed -/* Process the options... +/* Process the options... * This file include MUST occur AFTER the user option selection settings */ /* @@ -214,8 +212,7 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList - -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" #include "cpuFamilyTranslation.h" @@ -250,7 +247,7 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = //#define DDR2400_FREQUENCY 1200 ///< DDR 2400 //#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency // -///* QUANDRANK_TYPE*/ +///* QUANDRANK_TYPE */ //#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM //#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM // diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index c46657df02..ada1a427a0 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -9,18 +9,17 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ #include -/* Select the CPU family. */ +/* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT FALSE #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE -/* Select the CPU socket type. */ +/* Select the CPU socket type. */ #define INSTALL_G34_SOCKET_SUPPORT FALSE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE @@ -141,7 +140,7 @@ #if CONFIG(GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ +//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M */ #define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif @@ -153,7 +152,7 @@ //#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID //#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID -/* Process the options... +/* Process the options... * This file include MUST occur AFTER the user option selection settings */ /* @@ -215,8 +214,7 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" #include "cpuFamilyTranslation.h" @@ -251,7 +249,7 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define DDR2400_FREQUENCY 1200 ///< DDR 2400 #define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -/* QUANDRANK_TYPE*/ +/* QUANDRANK_TYPE */ #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 8432e7e88c..38a9faf0e0 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -9,18 +9,15 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ - - -/* Select the CPU family. */ +/* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT TRUE #define INSTALL_FAMILY_15_SUPPORT FALSE -/* Select the CPU socket type. */ +/* Select the CPU socket type. */ #define INSTALL_G34_SOCKET_SUPPORT FALSE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE @@ -85,7 +82,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE - #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -206,7 +202,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { CPU_LIST_TERMINAL } }; -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" @@ -252,7 +248,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DDR1866_FREQUENCY 933 ///< DDR 1866 #define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency -/* QUANDRANK_TYPE*/ +/* QUANDRANK_TYPE */ #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index 4ad8a7ff68..8eec4f4c96 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -9,18 +9,15 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ - - -/* Select the CPU family. */ +/* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT TRUE #define INSTALL_FAMILY_15_SUPPORT FALSE -/* Select the CPU socket type. */ +/* Select the CPU socket type. */ #define INSTALL_G34_SOCKET_SUPPORT FALSE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE @@ -85,7 +82,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE - #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -206,7 +202,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { CPU_LIST_TERMINAL } }; -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" @@ -252,7 +248,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DDR1866_FREQUENCY 933 ///< DDR 1866 #define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency -/* QUANDRANK_TYPE*/ +/* QUANDRANK_TYPE */ #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index 915f792159..169e0096bb 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -9,18 +9,17 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ #include -/* Select the CPU family. */ +/* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT FALSE #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE -/* Select the CPU socket type. */ +/* Select the CPU socket type. */ #define INSTALL_G34_SOCKET_SUPPORT FALSE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE @@ -141,7 +140,7 @@ #if CONFIG(GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ +//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M */ #define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif @@ -153,7 +152,7 @@ //#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID //#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID -/* Process the options... +/* Process the options... * This file include MUST occur AFTER the user option selection settings */ /* @@ -215,8 +214,7 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" #include "cpuFamilyTranslation.h" @@ -251,7 +249,7 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define DDR2400_FREQUENCY 1200 ///< DDR 2400 #define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -/* QUANDRANK_TYPE*/ +/* QUANDRANK_TYPE */ #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index 4ad8a7ff68..8eec4f4c96 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -9,18 +9,15 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ - - -/* Select the CPU family. */ +/* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT TRUE #define INSTALL_FAMILY_15_SUPPORT FALSE -/* Select the CPU socket type. */ +/* Select the CPU socket type. */ #define INSTALL_G34_SOCKET_SUPPORT FALSE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE @@ -85,7 +82,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE - #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -206,7 +202,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { CPU_LIST_TERMINAL } }; -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" @@ -252,7 +248,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DDR1866_FREQUENCY 933 ///< DDR 1866 #define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency -/* QUANDRANK_TYPE*/ +/* QUANDRANK_TYPE */ #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index 1e644c5bc0..b49376ecbf 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -9,19 +9,17 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ #include - -/* Select the CPU family. */ +/* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT TRUE #define INSTALL_FAMILY_15_SUPPORT FALSE -/* Select the CPU socket type. */ +/* Select the CPU socket type. */ #define INSTALL_G34_SOCKET_SUPPORT FALSE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE @@ -86,7 +84,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE - /* * Agesa configuration values selection. * Uncomment and specify the value for the configuration options @@ -206,7 +203,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" #include "cpuFamilyTranslation.h" diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c index 9fc4a43fc3..78a4082038 100644 --- a/src/mainboard/asrock/imb-a180/buildOpts.c +++ b/src/mainboard/asrock/imb-a180/buildOpts.c @@ -9,7 +9,6 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ #include @@ -29,7 +28,6 @@ #define INSTALL_AM3_SOCKET_SUPPORT FALSE #define INSTALL_FM2_SOCKET_SUPPORT FALSE - #ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE #undef INSTALL_FT3_SOCKET_SUPPORT @@ -152,7 +150,7 @@ #define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' #define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed -/* Process the options... +/* Process the options... * This file include MUST occur AFTER the user option selection settings */ /* @@ -214,8 +212,7 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList - -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" #include "cpuFamilyTranslation.h" @@ -250,7 +247,7 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = //#define DDR2400_FREQUENCY 1200 ///< DDR 2400 //#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency // -///* QUANDRANK_TYPE*/ +///* QUANDRANK_TYPE */ //#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM //#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM // diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 49fcb22b2a..241d7b5897 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -9,13 +9,11 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ - #include -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include #include #include @@ -29,10 +27,10 @@ #include #include -/* Select the CPU family. */ +/* Select the CPU family. */ #define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE -/* Select the CPU socket type. */ +/* Select the CPU socket type. */ #define INSTALL_G34_SOCKET_SUPPORT FALSE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE @@ -178,7 +176,7 @@ //#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID //#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID -/* Process the options... +/* Process the options... * This file include MUST occur AFTER the user option selection settings */ /* @@ -262,7 +260,7 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = //#define DDR2400_FREQUENCY 1200 ///< DDR 2400 //#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency // -///* QUANDRANK_TYPE*/ +///* QUANDRANK_TYPE */ //#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM //#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM // diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index e2fe66cfdb..c30d5bd0c0 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -9,13 +9,11 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ - #include -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include #include #include @@ -27,14 +25,13 @@ #include #include - -/* Select the CPU family. */ +/* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT FALSE #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE -/* Select the CPU socket type. */ +/* Select the CPU socket type. */ #define INSTALL_G34_SOCKET_SUPPORT FALSE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE @@ -156,7 +153,7 @@ #if CONFIG(GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ +//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M */ #define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif @@ -168,7 +165,7 @@ //#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID //#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID -/* Process the options... +/* Process the options... * This file include MUST occur AFTER the user option selection settings */ /* @@ -252,7 +249,7 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define DDR2400_FREQUENCY 1200 ///< DDR 2400 #define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -/* QUANDRANK_TYPE*/ +/* QUANDRANK_TYPE */ #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c index ec4e17e655..4938d95bb7 100644 --- a/src/mainboard/bap/ode_e20XX/buildOpts.c +++ b/src/mainboard/bap/ode_e20XX/buildOpts.c @@ -9,7 +9,6 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ #include @@ -29,7 +28,6 @@ #define INSTALL_AM3_SOCKET_SUPPORT FALSE #define INSTALL_FM2_SOCKET_SUPPORT FALSE - #ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE #undef INSTALL_FT3_SOCKET_SUPPORT @@ -152,7 +150,7 @@ #define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' #define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed -/* Process the options... +/* Process the options... * This file include MUST occur AFTER the user option selection settings */ /* @@ -214,7 +212,7 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" #include "cpuFamilyTranslation.h" @@ -249,7 +247,7 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = //#define DDR2400_FREQUENCY 1200 ///< DDR 2400 //#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency // -///* QUANDRANK_TYPE*/ +///* QUANDRANK_TYPE */ //#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM //#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM // diff --git a/src/mainboard/biostar/a68n_5200/buildOpts.c b/src/mainboard/biostar/a68n_5200/buildOpts.c index fd61756a23..1712708635 100644 --- a/src/mainboard/biostar/a68n_5200/buildOpts.c +++ b/src/mainboard/biostar/a68n_5200/buildOpts.c @@ -9,7 +9,6 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ #include @@ -29,7 +28,6 @@ #define INSTALL_AM3_SOCKET_SUPPORT FALSE #define INSTALL_FM2_SOCKET_SUPPORT FALSE - #ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE #undef INSTALL_FT3_SOCKET_SUPPORT @@ -152,7 +150,7 @@ #define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' #define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed -/* Process the options... +/* Process the options... * This file include MUST occur AFTER the user option selection settings */ /* @@ -214,8 +212,7 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList - -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" #include "cpuFamilyTranslation.h" @@ -250,7 +247,7 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = //#define DDR2400_FREQUENCY 1200 ///< DDR 2400 //#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency // -///* QUANDRANK_TYPE*/ +///* QUANDRANK_TYPE */ //#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM //#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM // diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c index 8cc90ddb3e..09421507b8 100644 --- a/src/mainboard/biostar/am1ml/buildOpts.c +++ b/src/mainboard/biostar/am1ml/buildOpts.c @@ -9,7 +9,6 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ #include @@ -29,7 +28,6 @@ #define INSTALL_AM3_SOCKET_SUPPORT FALSE #define INSTALL_FM2_SOCKET_SUPPORT FALSE - #ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE #undef INSTALL_FT3_SOCKET_SUPPORT @@ -152,7 +150,7 @@ #define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' #define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed -/* Process the options... +/* Process the options... * This file include MUST occur AFTER the user option selection settings */ /* @@ -214,8 +212,7 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList - -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" #include "cpuFamilyTranslation.h" @@ -250,7 +247,7 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = //#define DDR2400_FREQUENCY 1200 ///< DDR 2400 //#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency // -///* QUANDRANK_TYPE*/ +///* QUANDRANK_TYPE */ //#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM //#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM // diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c index d39b25baf7..c6338f4eb3 100644 --- a/src/mainboard/elmex/pcm205400/buildOpts.c +++ b/src/mainboard/elmex/pcm205400/buildOpts.c @@ -9,18 +9,15 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ - - -/* Select the cpu family. */ +/* Select the cpu family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT TRUE #define INSTALL_FAMILY_15_SUPPORT FALSE -/* Select the cpu socket type. */ +/* Select the cpu socket type. */ #define INSTALL_G34_SOCKET_SUPPORT FALSE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE @@ -85,7 +82,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE - #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -206,7 +202,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { CPU_LIST_TERMINAL } }; -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" @@ -252,7 +248,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DDR1866_FREQUENCY 933 ///< DDR 1866 #define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency -/* QUANDRANK_TYPE*/ +/* QUANDRANK_TYPE */ #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c index b273428848..38a9faf0e0 100644 --- a/src/mainboard/gizmosphere/gizmo/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c @@ -9,19 +9,15 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ - - - -/* Select the CPU family. */ +/* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT TRUE #define INSTALL_FAMILY_15_SUPPORT FALSE -/* Select the CPU socket type. */ +/* Select the CPU socket type. */ #define INSTALL_G34_SOCKET_SUPPORT FALSE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE @@ -86,7 +82,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE - #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -207,7 +202,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { CPU_LIST_TERMINAL } }; -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" @@ -253,7 +248,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DDR1866_FREQUENCY 933 ///< DDR 1866 #define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency -/* QUANDRANK_TYPE*/ +/* QUANDRANK_TYPE */ #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c index ec4e17e655..4938d95bb7 100644 --- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c @@ -9,7 +9,6 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ #include @@ -29,7 +28,6 @@ #define INSTALL_AM3_SOCKET_SUPPORT FALSE #define INSTALL_FM2_SOCKET_SUPPORT FALSE - #ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE #undef INSTALL_FT3_SOCKET_SUPPORT @@ -152,7 +150,7 @@ #define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' #define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed -/* Process the options... +/* Process the options... * This file include MUST occur AFTER the user option selection settings */ /* @@ -214,7 +212,7 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" #include "cpuFamilyTranslation.h" @@ -249,7 +247,7 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = //#define DDR2400_FREQUENCY 1200 ///< DDR 2400 //#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency // -///* QUANDRANK_TYPE*/ +///* QUANDRANK_TYPE */ //#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM //#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM // diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index 05ed0147aa..e3c68a7312 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -33,7 +33,6 @@ #define INSTALL_AM3_SOCKET_SUPPORT FALSE #define INSTALL_FM2_SOCKET_SUPPORT FALSE - #ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE #undef INSTALL_FT3_SOCKET_SUPPORT @@ -156,7 +155,7 @@ #define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' #define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed -/* Process the options... +/* Process the options... * This file include MUST occur AFTER the user option selection settings */ /* @@ -218,8 +217,7 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList - -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" #include "cpuFamilyTranslation.h" @@ -254,7 +252,7 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = //#define DDR2400_FREQUENCY 1200 ///< DDR 2400 //#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency // -///* QUANDRANK_TYPE*/ +///* QUANDRANK_TYPE */ //#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM //#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM // diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index c46ba74f82..dc08a32ab9 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -9,15 +9,13 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ #include "mainboard.h" - #include -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include #include #include @@ -29,14 +27,13 @@ #include #include - -/* Select the CPU family. */ +/* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT FALSE #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE -/* Select the CPU socket type. */ +/* Select the CPU socket type. */ #define INSTALL_G34_SOCKET_SUPPORT FALSE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE @@ -157,7 +154,7 @@ #if CONFIG(GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ +//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M */ #define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif @@ -169,7 +166,7 @@ //#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID //#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID -/* Process the options... +/* Process the options... * This file include MUST occur AFTER the user option selection settings */ /* @@ -253,7 +250,7 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define DDR2400_FREQUENCY 1200 ///< DDR 2400 #define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -/* QUANDRANK_TYPE*/ +/* QUANDRANK_TYPE */ #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM @@ -339,7 +336,6 @@ GPIO_CONTROL pavilion_m6_1035dx_gpio[] = { }; #define BLDCFG_FCH_GPIO_CONTROL_LIST (&pavilion_m6_1035dx_gpio[0]) - /* These definitions could be moved to a common Hudson header, should we decide * to provide our own, saner SCI mapping function */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index cdaecf0efc..4e1c95af6f 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -9,10 +9,8 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ - #include /* Include the files that instantiate the configuration definitions. */ @@ -27,7 +25,6 @@ #include #include - /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE @@ -99,7 +96,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE - #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -255,7 +251,7 @@ const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DDR1866_FREQUENCY 933 /**< DDR 1866 */ #define UNSUPPORTED_DDR_FREQUENCY 934 /**< Max limit of DDR frequency */ -/* QUANDRANK_TYPE*/ +/* QUANDRANK_TYPE */ #define QUADRANK_REGISTERED 0 /**< Quadrank registered DIMM */ #define QUADRANK_UNBUFFERED 1 /**< Quadrank unbuffered DIMM */ diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index 6351aeedbb..bd7326dcd4 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -9,12 +9,10 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ #include "mainboard.h" - #include /* Include the files that instantiate the configuration definitions. */ @@ -29,7 +27,6 @@ #include #include - /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE @@ -157,7 +154,7 @@ #if CONFIG(GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ +//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M */ #define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif @@ -253,7 +250,7 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define DDR2400_FREQUENCY 1200 ///< DDR 2400 #define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -/* QUANDRANK_TYPE*/ +/* QUANDRANK_TYPE */ #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM @@ -339,7 +336,6 @@ GPIO_CONTROL lenovo_g505s_gpio[] = { }; #define BLDCFG_FCH_GPIO_CONTROL_LIST (&lenovo_g505s_gpio[0]) - /* These definitions could be moved to a common Hudson header, should we decide * to provide our own, saner SCI mapping function */ diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c index b273428848..38a9faf0e0 100644 --- a/src/mainboard/lippert/frontrunner-af/buildOpts.c +++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c @@ -9,19 +9,15 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ - - - -/* Select the CPU family. */ +/* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT TRUE #define INSTALL_FAMILY_15_SUPPORT FALSE -/* Select the CPU socket type. */ +/* Select the CPU socket type. */ #define INSTALL_G34_SOCKET_SUPPORT FALSE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE @@ -86,7 +82,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE - #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -207,7 +202,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { CPU_LIST_TERMINAL } }; -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" @@ -253,7 +248,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DDR1866_FREQUENCY 933 ///< DDR 1866 #define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency -/* QUANDRANK_TYPE*/ +/* QUANDRANK_TYPE */ #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c index b273428848..38a9faf0e0 100644 --- a/src/mainboard/lippert/toucan-af/buildOpts.c +++ b/src/mainboard/lippert/toucan-af/buildOpts.c @@ -9,19 +9,15 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ - - - -/* Select the CPU family. */ +/* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT TRUE #define INSTALL_FAMILY_15_SUPPORT FALSE -/* Select the CPU socket type. */ +/* Select the CPU socket type. */ #define INSTALL_G34_SOCKET_SUPPORT FALSE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE @@ -86,7 +82,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE - #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -207,7 +202,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { CPU_LIST_TERMINAL } }; -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" @@ -253,7 +248,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DDR1866_FREQUENCY 933 ///< DDR 1866 #define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency -/* QUANDRANK_TYPE*/ +/* QUANDRANK_TYPE */ #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index d7e8c85a32..7904f1c1a8 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -9,13 +9,11 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ - #include -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include #include #include @@ -27,14 +25,13 @@ #include #include - -/* Select the CPU family. */ +/* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT FALSE #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE -/* Select the CPU socket type. */ +/* Select the CPU socket type. */ #define INSTALL_G34_SOCKET_SUPPORT FALSE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE @@ -156,7 +153,7 @@ #if CONFIG(GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ +//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M */ #define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif @@ -168,7 +165,7 @@ //#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID //#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID -/* Process the options... +/* Process the options... * This file include MUST occur AFTER the user option selection settings */ /* @@ -252,7 +249,7 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define DDR2400_FREQUENCY 1200 ///< DDR 2400 #define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -/* QUANDRANK_TYPE*/ +/* QUANDRANK_TYPE */ #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c index 52a37f3668..7212a813bd 100644 --- a/src/mainboard/pcengines/apu1/buildOpts.c +++ b/src/mainboard/pcengines/apu1/buildOpts.c @@ -9,18 +9,15 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ - - -/* Select the CPU family. */ +/* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT TRUE #define INSTALL_FAMILY_15_SUPPORT FALSE -/* Select the CPU socket type. */ +/* Select the CPU socket type. */ #define INSTALL_G34_SOCKET_SUPPORT FALSE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE @@ -85,7 +82,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE - #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -206,7 +202,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { CPU_LIST_TERMINAL } }; -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" @@ -252,7 +248,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DDR1866_FREQUENCY 933 ///< DDR 1866 #define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency -/* QUANDRANK_TYPE*/ +/* QUANDRANK_TYPE */ #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM From f689d2ee19b25154b0f84fdff1cc2aaa337c4bab Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 21 May 2020 00:06:15 +0200 Subject: [PATCH 253/405] AGESA f14/f15tn/f16kb: Factor out AGESA_PACKAGE_STRING We use the same value everywhere, so factor it out. Note that the field where this value ends up in was doubled in size for AGESA fam16kb, but we did not update the definition to fill in the additional space. We are not changing it in this commit so as to preserve binary reproducibility. In any case, add a FIXME explaining why this value may not be correct. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Ied118d534ee1e9728db843944d1e042760b4f32c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41590 Tested-by: build bot (Jenkins) Reviewed-by: Mike Banon Reviewed-by: Krystian Hebel --- src/mainboard/amd/inagua/buildOpts.c | 17 ---------------- src/mainboard/amd/olivehill/buildOpts.c | 4 ---- src/mainboard/amd/parmer/buildOpts.c | 4 ---- src/mainboard/amd/persimmon/buildOpts.c | 17 ---------------- src/mainboard/amd/south_station/buildOpts.c | 17 ---------------- src/mainboard/amd/thatcher/buildOpts.c | 4 ---- src/mainboard/amd/union_station/buildOpts.c | 17 ---------------- src/mainboard/asrock/e350m1/buildOpts.c | 17 ---------------- src/mainboard/asrock/imb-a180/buildOpts.c | 4 ---- src/mainboard/asus/am1i-a/buildOpts.c | 4 ---- src/mainboard/asus/f2a85-m/buildOpts.c | 4 ---- src/mainboard/bap/ode_e20XX/buildOpts.c | 4 ---- src/mainboard/biostar/a68n_5200/buildOpts.c | 4 ---- src/mainboard/biostar/am1ml/buildOpts.c | 4 ---- src/mainboard/elmex/pcm205400/buildOpts.c | 17 ---------------- src/mainboard/gizmosphere/gizmo/buildOpts.c | 17 ---------------- src/mainboard/gizmosphere/gizmo2/buildOpts.c | 4 ---- src/mainboard/hp/abm/buildOpts.c | 4 ---- .../hp/pavilion_m6_1035dx/buildOpts.c | 4 ---- src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 20 ------------------- src/mainboard/lenovo/g505s/buildOpts.c | 4 ---- .../lippert/frontrunner-af/buildOpts.c | 17 ---------------- src/mainboard/lippert/toucan-af/buildOpts.c | 17 ---------------- src/mainboard/msi/ms7721/buildOpts.c | 4 ---- src/mainboard/pcengines/apu1/buildOpts.c | 17 ---------------- src/vendorcode/amd/agesa/f14/AGESA.h | 6 ++++++ src/vendorcode/amd/agesa/f15tn/AGESA.h | 6 ++++++ src/vendorcode/amd/agesa/f16kb/AGESA.h | 8 ++++++++ 28 files changed, 20 insertions(+), 246 deletions(-) diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index e9f1e7120f..18a5ac9c04 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -216,23 +216,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ -// This is the delivery package title, "BrazosPI" -// This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index 1712708635..4a9d759f8c 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -225,10 +225,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index ada1a427a0..81d777a471 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -227,10 +227,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 38a9faf0e0..f0c5761c0a 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -216,23 +216,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ -// This is the delivery package title, "BrazosPI" -// This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index 8eec4f4c96..c83af3900e 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -216,23 +216,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index 169e0096bb..dddf1f5309 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -227,10 +227,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index 8eec4f4c96..c83af3900e 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -216,23 +216,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index b49376ecbf..fd3ddc86ca 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -216,23 +216,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c index 78a4082038..88db840359 100644 --- a/src/mainboard/asrock/imb-a180/buildOpts.c +++ b/src/mainboard/asrock/imb-a180/buildOpts.c @@ -225,10 +225,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 241d7b5897..7082e2d46a 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -238,10 +238,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index c30d5bd0c0..5caffd4766 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -227,10 +227,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c index 4938d95bb7..a7ca6580e1 100644 --- a/src/mainboard/bap/ode_e20XX/buildOpts.c +++ b/src/mainboard/bap/ode_e20XX/buildOpts.c @@ -225,10 +225,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} diff --git a/src/mainboard/biostar/a68n_5200/buildOpts.c b/src/mainboard/biostar/a68n_5200/buildOpts.c index 1712708635..4a9d759f8c 100644 --- a/src/mainboard/biostar/a68n_5200/buildOpts.c +++ b/src/mainboard/biostar/a68n_5200/buildOpts.c @@ -225,10 +225,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c index 09421507b8..b76306fb94 100644 --- a/src/mainboard/biostar/am1ml/buildOpts.c +++ b/src/mainboard/biostar/am1ml/buildOpts.c @@ -225,10 +225,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c index c6338f4eb3..3d6c644e68 100644 --- a/src/mainboard/elmex/pcm205400/buildOpts.c +++ b/src/mainboard/elmex/pcm205400/buildOpts.c @@ -216,23 +216,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ -// This is the delivery package title, "BrazosPI" -// This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c index 38a9faf0e0..f0c5761c0a 100644 --- a/src/mainboard/gizmosphere/gizmo/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c @@ -216,23 +216,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ -// This is the delivery package title, "BrazosPI" -// This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c index 4938d95bb7..a7ca6580e1 100644 --- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c @@ -225,10 +225,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index e3c68a7312..7ae5f4321f 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -230,10 +230,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index dc08a32ab9..85ab1231fa 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -228,10 +228,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index 4e1c95af6f..1611c2139d 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -215,26 +215,6 @@ const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { CPU_LIST_TERMINAL } }; -/** - * @brief Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - */ - -/* - * This is the delivery package title, "BrazosPI" - * This string MUST be exactly 8 characters long - */ -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - /* This is the release version number of the AGESA component * This string MUST be exactly 12 characters long */ diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index bd7326dcd4..1565fbb036 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -228,10 +228,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c index 38a9faf0e0..f0c5761c0a 100644 --- a/src/mainboard/lippert/frontrunner-af/buildOpts.c +++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c @@ -216,23 +216,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ -// This is the delivery package title, "BrazosPI" -// This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c index 38a9faf0e0..f0c5761c0a 100644 --- a/src/mainboard/lippert/toucan-af/buildOpts.c +++ b/src/mainboard/lippert/toucan-af/buildOpts.c @@ -216,23 +216,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ -// This is the delivery package title, "BrazosPI" -// This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index 7904f1c1a8..f9c3f508f8 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -227,10 +227,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c index 7212a813bd..d42854e6d4 100644 --- a/src/mainboard/pcengines/apu1/buildOpts.c +++ b/src/mainboard/pcengines/apu1/buildOpts.c @@ -216,23 +216,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ -// This is the delivery package title, "BrazosPI" -// This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} - // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} diff --git a/src/vendorcode/amd/agesa/f14/AGESA.h b/src/vendorcode/amd/agesa/f14/AGESA.h index 9bf9207789..6d4cd7bee6 100644 --- a/src/vendorcode/amd/agesa/f14/AGESA.h +++ b/src/vendorcode/amd/agesa/f14/AGESA.h @@ -47,6 +47,12 @@ #ifndef _AGESA_H_ #define _AGESA_H_ +/* + * This is the delivery package title. + * This string MUST be exactly 8 characters long. + */ +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} + #include "Porting.h" #include "AMD.h" diff --git a/src/vendorcode/amd/agesa/f15tn/AGESA.h b/src/vendorcode/amd/agesa/f15tn/AGESA.h index ce3e857490..e03cdc72f6 100644 --- a/src/vendorcode/amd/agesa/f15tn/AGESA.h +++ b/src/vendorcode/amd/agesa/f15tn/AGESA.h @@ -44,6 +44,12 @@ #ifndef _AGESA_H_ #define _AGESA_H_ +/* + * This is the delivery package title. + * This string MUST be exactly 8 characters long. + */ +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} + #include "Porting.h" #include "AMD.h" diff --git a/src/vendorcode/amd/agesa/f16kb/AGESA.h b/src/vendorcode/amd/agesa/f16kb/AGESA.h index b9b4354d26..7a7d185f23 100644 --- a/src/vendorcode/amd/agesa/f16kb/AGESA.h +++ b/src/vendorcode/amd/agesa/f16kb/AGESA.h @@ -44,6 +44,14 @@ #ifndef _AGESA_H_ #define _AGESA_H_ +/* + * This is the delivery package title. + * This string MUST be exactly 16 characters long. + * + * FIXME: AMD_CODE_HEADER for this platform expects 16 characters, but there's only 8 here. + */ +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} + #include "Porting.h" #include "AMD.h" From c072e794e62433d75369b50c7e9c90c50e47ba89 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 21 May 2020 00:28:08 +0200 Subject: [PATCH 254/405] AGESA f14/f15tn/f16kb: Factor out AGESA_VERSION_STRING We use the same AGESA version numbers on all but one mainboard, so we might as well factor them out. The only exception is asrock/e350m1, which has the f15tn/f16kb version number even though it actually uses AGESA f14. To preserve reproducibility, do not change it in this commit. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: I0dad2352ccda454d5545f17228d52e4ff4f23f20 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41591 Reviewed-by: Mike Banon Tested-by: build bot (Jenkins) --- src/mainboard/amd/inagua/buildOpts.c | 4 ---- src/mainboard/amd/olivehill/buildOpts.c | 4 ---- src/mainboard/amd/parmer/buildOpts.c | 4 ---- src/mainboard/amd/persimmon/buildOpts.c | 4 ---- src/mainboard/amd/south_station/buildOpts.c | 4 ---- src/mainboard/amd/thatcher/buildOpts.c | 4 ---- src/mainboard/amd/union_station/buildOpts.c | 4 ---- src/mainboard/asrock/e350m1/buildOpts.c | 2 ++ src/mainboard/asrock/imb-a180/buildOpts.c | 4 ---- src/mainboard/asus/am1i-a/buildOpts.c | 4 ---- src/mainboard/asus/f2a85-m/buildOpts.c | 4 ---- src/mainboard/bap/ode_e20XX/buildOpts.c | 4 ---- src/mainboard/biostar/a68n_5200/buildOpts.c | 4 ---- src/mainboard/biostar/am1ml/buildOpts.c | 4 ---- src/mainboard/elmex/pcm205400/buildOpts.c | 4 ---- src/mainboard/gizmosphere/gizmo/buildOpts.c | 4 ---- src/mainboard/gizmosphere/gizmo2/buildOpts.c | 4 ---- src/mainboard/hp/abm/buildOpts.c | 4 ---- src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 4 ---- src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 5 ----- src/mainboard/lenovo/g505s/buildOpts.c | 4 ---- src/mainboard/lippert/frontrunner-af/buildOpts.c | 4 ---- src/mainboard/lippert/toucan-af/buildOpts.c | 4 ---- src/mainboard/msi/ms7721/buildOpts.c | 4 ---- src/mainboard/pcengines/apu1/buildOpts.c | 4 ---- src/vendorcode/amd/agesa/f14/AGESA.h | 6 ++++++ src/vendorcode/amd/agesa/f15tn/AGESA.h | 6 ++++++ src/vendorcode/amd/agesa/f16kb/AGESA.h | 6 ++++++ 28 files changed, 20 insertions(+), 97 deletions(-) diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index 18a5ac9c04..f56a03dac4 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -216,10 +216,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" -// This is the release version number of the AGESA component -// This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index 4a9d759f8c..dfcb46508a 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -225,10 +225,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} - /* MEMORY_BUS_SPEED */ //#define DDR400_FREQUENCY 200 ///< DDR 400 //#define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 81d777a471..e1c71c366e 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -227,10 +227,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index f0c5761c0a..3066cea0ae 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -216,10 +216,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" -// This is the release version number of the AGESA component -// This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index c83af3900e..9eac2cf3d7 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -216,10 +216,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index dddf1f5309..e1c3cd237c 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -227,10 +227,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index c83af3900e..9eac2cf3d7 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -216,10 +216,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index fd3ddc86ca..b674a5a6b4 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -216,6 +216,8 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" +/* FIXME: This is most likely wrong */ +#undef AGESA_VERSION_STRING // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c index 88db840359..97d49c765d 100644 --- a/src/mainboard/asrock/imb-a180/buildOpts.c +++ b/src/mainboard/asrock/imb-a180/buildOpts.c @@ -225,10 +225,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} - /* MEMORY_BUS_SPEED */ //#define DDR400_FREQUENCY 200 ///< DDR 400 //#define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 7082e2d46a..e2c01fcfee 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -238,10 +238,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} - /* MEMORY_BUS_SPEED */ //#define DDR400_FREQUENCY 200 ///< DDR 400 //#define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 5caffd4766..6c368cbe1d 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -227,10 +227,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c index a7ca6580e1..0d98c02d9e 100644 --- a/src/mainboard/bap/ode_e20XX/buildOpts.c +++ b/src/mainboard/bap/ode_e20XX/buildOpts.c @@ -225,10 +225,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} - /* MEMORY_BUS_SPEED */ //#define DDR400_FREQUENCY 200 ///< DDR 400 //#define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/biostar/a68n_5200/buildOpts.c b/src/mainboard/biostar/a68n_5200/buildOpts.c index 4a9d759f8c..dfcb46508a 100644 --- a/src/mainboard/biostar/a68n_5200/buildOpts.c +++ b/src/mainboard/biostar/a68n_5200/buildOpts.c @@ -225,10 +225,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} - /* MEMORY_BUS_SPEED */ //#define DDR400_FREQUENCY 200 ///< DDR 400 //#define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c index b76306fb94..5e9f256c17 100644 --- a/src/mainboard/biostar/am1ml/buildOpts.c +++ b/src/mainboard/biostar/am1ml/buildOpts.c @@ -225,10 +225,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} - /* MEMORY_BUS_SPEED */ //#define DDR400_FREQUENCY 200 ///< DDR 400 //#define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c index 3d6c644e68..e2f687b21f 100644 --- a/src/mainboard/elmex/pcm205400/buildOpts.c +++ b/src/mainboard/elmex/pcm205400/buildOpts.c @@ -216,10 +216,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" -// This is the release version number of the AGESA component -// This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c index f0c5761c0a..3066cea0ae 100644 --- a/src/mainboard/gizmosphere/gizmo/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c @@ -216,10 +216,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" -// This is the release version number of the AGESA component -// This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c index a7ca6580e1..0d98c02d9e 100644 --- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c @@ -225,10 +225,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} - /* MEMORY_BUS_SPEED */ //#define DDR400_FREQUENCY 200 ///< DDR 400 //#define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index 7ae5f4321f..7ebf119d9b 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -230,10 +230,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} - /* MEMORY_BUS_SPEED */ //#define DDR400_FREQUENCY 200 ///< DDR 400 //#define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 85ab1231fa..17b58047ba 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -228,10 +228,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index 1611c2139d..c3c64093f5 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -215,11 +215,6 @@ const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { CPU_LIST_TERMINAL } }; -/* This is the release version number of the AGESA component - * This string MUST be exactly 12 characters long - */ -#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 /**< DDR 400 */ #define DDR533_FREQUENCY 266 /**< DDR 533 */ diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index 1565fbb036..789bb40979 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -228,10 +228,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c index f0c5761c0a..3066cea0ae 100644 --- a/src/mainboard/lippert/frontrunner-af/buildOpts.c +++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c @@ -216,10 +216,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" -// This is the release version number of the AGESA component -// This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c index f0c5761c0a..3066cea0ae 100644 --- a/src/mainboard/lippert/toucan-af/buildOpts.c +++ b/src/mainboard/lippert/toucan-af/buildOpts.c @@ -216,10 +216,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" -// This is the release version number of the AGESA component -// This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index f9c3f508f8..aaa88b6a09 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -227,10 +227,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c index d42854e6d4..c63cfd11a8 100644 --- a/src/mainboard/pcengines/apu1/buildOpts.c +++ b/src/mainboard/pcengines/apu1/buildOpts.c @@ -216,10 +216,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h" -// This is the release version number of the AGESA component -// This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/vendorcode/amd/agesa/f14/AGESA.h b/src/vendorcode/amd/agesa/f14/AGESA.h index 6d4cd7bee6..047b0371f2 100644 --- a/src/vendorcode/amd/agesa/f14/AGESA.h +++ b/src/vendorcode/amd/agesa/f14/AGESA.h @@ -53,6 +53,12 @@ */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} +/* + * This is the release version number of the AGESA component. + * This string MUST be exactly 12 characters long. + */ +#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} + #include "Porting.h" #include "AMD.h" diff --git a/src/vendorcode/amd/agesa/f15tn/AGESA.h b/src/vendorcode/amd/agesa/f15tn/AGESA.h index e03cdc72f6..3ac9071f65 100644 --- a/src/vendorcode/amd/agesa/f15tn/AGESA.h +++ b/src/vendorcode/amd/agesa/f15tn/AGESA.h @@ -50,6 +50,12 @@ */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} +/* + * This is the release version number of the AGESA component. + * This string MUST be exactly 12 characters long. + */ +#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} + #include "Porting.h" #include "AMD.h" diff --git a/src/vendorcode/amd/agesa/f16kb/AGESA.h b/src/vendorcode/amd/agesa/f16kb/AGESA.h index 7a7d185f23..7e43de416c 100644 --- a/src/vendorcode/amd/agesa/f16kb/AGESA.h +++ b/src/vendorcode/amd/agesa/f16kb/AGESA.h @@ -52,6 +52,12 @@ */ #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} +/* + * This is the release version number of the AGESA component. + * This string MUST be exactly 12 characters long. + */ +#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} + #include "Porting.h" #include "AMD.h" From 033ea49bef6877ff38fe0b239ca9b399a7b1e23a Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 21 May 2020 00:39:12 +0200 Subject: [PATCH 255/405] AGESA f14 boards: Drop useless socket definitions AGESA f14 only uses INSTALL_FT1_SOCKET_SUPPORT. Drop the rest. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: I48efa7496c8101115b4735a99c8c472ac65c0523 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41592 Reviewed-by: Arthur Heymans Reviewed-by: Krystian Hebel Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/amd/inagua/buildOpts.c | 20 ------------------- src/mainboard/amd/persimmon/buildOpts.c | 20 ------------------- src/mainboard/amd/south_station/buildOpts.c | 20 ------------------- src/mainboard/amd/union_station/buildOpts.c | 20 ------------------- src/mainboard/asrock/e350m1/buildOpts.c | 20 ------------------- src/mainboard/elmex/pcm205400/buildOpts.c | 20 ------------------- src/mainboard/gizmosphere/gizmo/buildOpts.c | 20 ------------------- src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 20 ------------------- .../lippert/frontrunner-af/buildOpts.c | 20 ------------------- src/mainboard/lippert/toucan-af/buildOpts.c | 20 ------------------- src/mainboard/pcengines/apu1/buildOpts.c | 20 ------------------- 11 files changed, 220 deletions(-) diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index f56a03dac4..3cae218043 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -18,16 +18,7 @@ #define INSTALL_FAMILY_15_SUPPORT FALSE /* Select the CPU socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP1_SOCKET_SUPPORT FALSE #define INSTALL_FT1_SOCKET_SUPPORT TRUE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE /* * Agesa optional capabilities selection. @@ -40,17 +31,6 @@ #define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE -#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE -#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE - #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 3066cea0ae..16b65a0c16 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -18,16 +18,7 @@ #define INSTALL_FAMILY_15_SUPPORT FALSE /* Select the CPU socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP1_SOCKET_SUPPORT FALSE #define INSTALL_FT1_SOCKET_SUPPORT TRUE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE /* * Agesa optional capabilities selection. @@ -40,17 +31,6 @@ #define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE -#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE -#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE - #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index 9eac2cf3d7..85f692475f 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -18,16 +18,7 @@ #define INSTALL_FAMILY_15_SUPPORT FALSE /* Select the CPU socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP1_SOCKET_SUPPORT FALSE #define INSTALL_FT1_SOCKET_SUPPORT TRUE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE /* * Agesa optional capabilities selection. @@ -40,17 +31,6 @@ #define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE -#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE -#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE - #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index 9eac2cf3d7..85f692475f 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -18,16 +18,7 @@ #define INSTALL_FAMILY_15_SUPPORT FALSE /* Select the CPU socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP1_SOCKET_SUPPORT FALSE #define INSTALL_FT1_SOCKET_SUPPORT TRUE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE /* * Agesa optional capabilities selection. @@ -40,17 +31,6 @@ #define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE -#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE -#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE - #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index b674a5a6b4..ec013f45e9 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -20,16 +20,7 @@ #define INSTALL_FAMILY_15_SUPPORT FALSE /* Select the CPU socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP1_SOCKET_SUPPORT FALSE #define INSTALL_FT1_SOCKET_SUPPORT TRUE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE /* * Agesa optional capabilities selection. @@ -42,17 +33,6 @@ #define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE -#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE -#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE - #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c index e2f687b21f..ff8739bb18 100644 --- a/src/mainboard/elmex/pcm205400/buildOpts.c +++ b/src/mainboard/elmex/pcm205400/buildOpts.c @@ -18,16 +18,7 @@ #define INSTALL_FAMILY_15_SUPPORT FALSE /* Select the cpu socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP1_SOCKET_SUPPORT FALSE #define INSTALL_FT1_SOCKET_SUPPORT TRUE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE /* * Agesa optional capabilities selection. @@ -40,17 +31,6 @@ #define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE -#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE -#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE - #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c index 3066cea0ae..16b65a0c16 100644 --- a/src/mainboard/gizmosphere/gizmo/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c @@ -18,16 +18,7 @@ #define INSTALL_FAMILY_15_SUPPORT FALSE /* Select the CPU socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP1_SOCKET_SUPPORT FALSE #define INSTALL_FT1_SOCKET_SUPPORT TRUE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE /* * Agesa optional capabilities selection. @@ -40,17 +31,6 @@ #define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE -#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE -#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE - #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index c3c64093f5..e976a0cadf 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -32,16 +32,7 @@ #define INSTALL_FAMILY_15_SUPPORT FALSE /* Select the CPU socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP1_SOCKET_SUPPORT FALSE #define INSTALL_FT1_SOCKET_SUPPORT TRUE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE /** * AGESA optional capabilities selection. @@ -54,17 +45,6 @@ #define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE -#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE -#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE - #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c index 3066cea0ae..16b65a0c16 100644 --- a/src/mainboard/lippert/frontrunner-af/buildOpts.c +++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c @@ -18,16 +18,7 @@ #define INSTALL_FAMILY_15_SUPPORT FALSE /* Select the CPU socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP1_SOCKET_SUPPORT FALSE #define INSTALL_FT1_SOCKET_SUPPORT TRUE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE /* * Agesa optional capabilities selection. @@ -40,17 +31,6 @@ #define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE -#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE -#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE - #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c index 3066cea0ae..16b65a0c16 100644 --- a/src/mainboard/lippert/toucan-af/buildOpts.c +++ b/src/mainboard/lippert/toucan-af/buildOpts.c @@ -18,16 +18,7 @@ #define INSTALL_FAMILY_15_SUPPORT FALSE /* Select the CPU socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP1_SOCKET_SUPPORT FALSE #define INSTALL_FT1_SOCKET_SUPPORT TRUE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE /* * Agesa optional capabilities selection. @@ -40,17 +31,6 @@ #define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE -#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE -#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE - #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c index c63cfd11a8..31d7c9cfcc 100644 --- a/src/mainboard/pcengines/apu1/buildOpts.c +++ b/src/mainboard/pcengines/apu1/buildOpts.c @@ -18,16 +18,7 @@ #define INSTALL_FAMILY_15_SUPPORT FALSE /* Select the CPU socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP1_SOCKET_SUPPORT FALSE #define INSTALL_FT1_SOCKET_SUPPORT TRUE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE /* * Agesa optional capabilities selection. @@ -40,17 +31,6 @@ #define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE -#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE -#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE - #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE From 0c983df7caa041f86f28938ccae31ce2d45803e5 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 21 May 2020 00:46:53 +0200 Subject: [PATCH 256/405] AGESA f14 boards: Drop useless family definitions AGESA f14 only uses INSTALL_FAMILY_14_SUPPORT. Drop the rest. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: I2fc6ba94cde66a238da9705fc42330b9e7682800 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41593 Reviewed-by: Mike Banon Reviewed-by: Arthur Heymans Reviewed-by: Krystian Hebel Tested-by: build bot (Jenkins) --- src/mainboard/amd/inagua/buildOpts.c | 10 +--------- src/mainboard/amd/persimmon/buildOpts.c | 8 -------- src/mainboard/amd/south_station/buildOpts.c | 8 -------- src/mainboard/amd/union_station/buildOpts.c | 8 -------- src/mainboard/asrock/e350m1/buildOpts.c | 8 -------- src/mainboard/elmex/pcm205400/buildOpts.c | 10 +--------- src/mainboard/gizmosphere/gizmo/buildOpts.c | 8 -------- src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 8 -------- src/mainboard/lippert/frontrunner-af/buildOpts.c | 8 -------- src/mainboard/lippert/toucan-af/buildOpts.c | 8 -------- src/mainboard/pcengines/apu1/buildOpts.c | 8 -------- 11 files changed, 2 insertions(+), 90 deletions(-) diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index 3cae218043..c40ed43619 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -12,10 +12,7 @@ */ /* Select the CPU family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT FALSE -#define INSTALL_FAMILY_14_SUPPORT TRUE -#define INSTALL_FAMILY_15_SUPPORT FALSE +#define INSTALL_FAMILY_14_SUPPORT TRUE /* Select the CPU socket type. */ #define INSTALL_FT1_SOCKET_SUPPORT TRUE @@ -26,11 +23,6 @@ * Comment out or mark TRUE those features you want to REMOVE from the build. */ -#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE -#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE - #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 16b65a0c16..02b248fa7e 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -12,10 +12,7 @@ */ /* Select the CPU family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT TRUE -#define INSTALL_FAMILY_15_SUPPORT FALSE /* Select the CPU socket type. */ #define INSTALL_FT1_SOCKET_SUPPORT TRUE @@ -26,11 +23,6 @@ * Comment out or mark TRUE those features you want to REMOVE from the build. */ -#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE -#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE - #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index 85f692475f..1d6e6590c9 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -12,10 +12,7 @@ */ /* Select the CPU family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT TRUE -#define INSTALL_FAMILY_15_SUPPORT FALSE /* Select the CPU socket type. */ #define INSTALL_FT1_SOCKET_SUPPORT TRUE @@ -26,11 +23,6 @@ * Comment out or mark TRUE those features you want to REMOVE from the build. */ -#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE -#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE - #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index 85f692475f..1d6e6590c9 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -12,10 +12,7 @@ */ /* Select the CPU family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT TRUE -#define INSTALL_FAMILY_15_SUPPORT FALSE /* Select the CPU socket type. */ #define INSTALL_FT1_SOCKET_SUPPORT TRUE @@ -26,11 +23,6 @@ * Comment out or mark TRUE those features you want to REMOVE from the build. */ -#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE -#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE - #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index ec013f45e9..5583a8b118 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -14,10 +14,7 @@ #include /* Select the CPU family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT TRUE -#define INSTALL_FAMILY_15_SUPPORT FALSE /* Select the CPU socket type. */ #define INSTALL_FT1_SOCKET_SUPPORT TRUE @@ -28,11 +25,6 @@ * Comment out or mark TRUE those features you want to REMOVE from the build. */ -#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE -#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE - #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c index ff8739bb18..ebbf9c7275 100644 --- a/src/mainboard/elmex/pcm205400/buildOpts.c +++ b/src/mainboard/elmex/pcm205400/buildOpts.c @@ -11,11 +11,8 @@ * For Information about this file, see @ref platforminstall. */ -/* Select the cpu family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT FALSE +/* Select the CPU family. */ #define INSTALL_FAMILY_14_SUPPORT TRUE -#define INSTALL_FAMILY_15_SUPPORT FALSE /* Select the cpu socket type. */ #define INSTALL_FT1_SOCKET_SUPPORT TRUE @@ -26,11 +23,6 @@ * Comment out or mark TRUE those features you want to REMOVE from the build. */ -#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE -#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE - #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c index 16b65a0c16..02b248fa7e 100644 --- a/src/mainboard/gizmosphere/gizmo/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c @@ -12,10 +12,7 @@ */ /* Select the CPU family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT TRUE -#define INSTALL_FAMILY_15_SUPPORT FALSE /* Select the CPU socket type. */ #define INSTALL_FT1_SOCKET_SUPPORT TRUE @@ -26,11 +23,6 @@ * Comment out or mark TRUE those features you want to REMOVE from the build. */ -#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE -#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE - #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index e976a0cadf..39d9d7e28b 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -26,10 +26,7 @@ #include /* Select the CPU family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT TRUE -#define INSTALL_FAMILY_15_SUPPORT FALSE /* Select the CPU socket type. */ #define INSTALL_FT1_SOCKET_SUPPORT TRUE @@ -40,11 +37,6 @@ * Comment out or mark TRUE those features you want to REMOVE from the build. */ -#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE -#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE - #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c index 16b65a0c16..02b248fa7e 100644 --- a/src/mainboard/lippert/frontrunner-af/buildOpts.c +++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c @@ -12,10 +12,7 @@ */ /* Select the CPU family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT TRUE -#define INSTALL_FAMILY_15_SUPPORT FALSE /* Select the CPU socket type. */ #define INSTALL_FT1_SOCKET_SUPPORT TRUE @@ -26,11 +23,6 @@ * Comment out or mark TRUE those features you want to REMOVE from the build. */ -#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE -#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE - #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c index 16b65a0c16..02b248fa7e 100644 --- a/src/mainboard/lippert/toucan-af/buildOpts.c +++ b/src/mainboard/lippert/toucan-af/buildOpts.c @@ -12,10 +12,7 @@ */ /* Select the CPU family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT TRUE -#define INSTALL_FAMILY_15_SUPPORT FALSE /* Select the CPU socket type. */ #define INSTALL_FT1_SOCKET_SUPPORT TRUE @@ -26,11 +23,6 @@ * Comment out or mark TRUE those features you want to REMOVE from the build. */ -#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE -#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE - #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c index 31d7c9cfcc..4780c33304 100644 --- a/src/mainboard/pcengines/apu1/buildOpts.c +++ b/src/mainboard/pcengines/apu1/buildOpts.c @@ -12,10 +12,7 @@ */ /* Select the CPU family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT TRUE -#define INSTALL_FAMILY_15_SUPPORT FALSE /* Select the CPU socket type. */ #define INSTALL_FT1_SOCKET_SUPPORT TRUE @@ -26,11 +23,6 @@ * Comment out or mark TRUE those features you want to REMOVE from the build. */ -#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE -#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE - #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE From 41b820cbd66da001b02a426a7b5cf1b7f011702a Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 21 May 2020 00:58:33 +0200 Subject: [PATCH 257/405] AGESA f14: Factor out default MTRR settings All AGESA f14 boards use the same MTRR values. Factor them out, while still allowing a board to override them via BLDCFG. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Id980e4671e51fe800188f0a84768a307c8965886 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41594 Tested-by: build bot (Jenkins) Reviewed-by: Mike Banon --- src/mainboard/amd/inagua/buildOpts.c | 18 ------------------ src/mainboard/amd/persimmon/buildOpts.c | 18 ------------------ src/mainboard/amd/south_station/buildOpts.c | 18 ------------------ src/mainboard/amd/union_station/buildOpts.c | 18 ------------------ src/mainboard/asrock/e350m1/buildOpts.c | 18 ------------------ src/mainboard/elmex/pcm205400/buildOpts.c | 18 ------------------ src/mainboard/gizmosphere/gizmo/buildOpts.c | 18 ------------------ src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 18 ------------------ .../lippert/frontrunner-af/buildOpts.c | 18 ------------------ src/mainboard/lippert/toucan-af/buildOpts.c | 18 ------------------ src/mainboard/pcengines/apu1/buildOpts.c | 18 ------------------ .../amd/agesa/f14/Config/PlatformInstall.h | 19 ++++++++++++++++++- 12 files changed, 18 insertions(+), 199 deletions(-) diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index c40ed43619..781dde3cc7 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -83,7 +83,6 @@ #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE //#define BLDCFG_STARTING_BUSNUM 0 //#define BLDCFG_MAXIMUM_BUSNUM 0xf8 @@ -157,23 +156,6 @@ */ #include -/* The fixed MTRR values to be set after memory initialization. */ -CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, - { CPU_LIST_TERMINAL } -}; - /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 02b248fa7e..cda2d9d461 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -83,7 +83,6 @@ #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE //#define BLDCFG_STARTING_BUSNUM 0 //#define BLDCFG_MAXIMUM_BUSNUM 0xf8 @@ -157,23 +156,6 @@ */ #include -/* The fixed MTRR values to be set after memory initialization. */ -CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, - { CPU_LIST_TERMINAL } -}; - /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index 1d6e6590c9..8bddb38abd 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -83,7 +83,6 @@ #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE //#define BLDCFG_STARTING_BUSNUM 0 //#define BLDCFG_MAXIMUM_BUSNUM 0xf8 @@ -157,23 +156,6 @@ */ #include -/* The fixed MTRR values to be set after memory initialization. */ -CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, - { CPU_LIST_TERMINAL } -}; - /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index 1d6e6590c9..8bddb38abd 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -83,7 +83,6 @@ #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE //#define BLDCFG_STARTING_BUSNUM 0 //#define BLDCFG_MAXIMUM_BUSNUM 0xf8 @@ -157,23 +156,6 @@ */ #include -/* The fixed MTRR values to be set after memory initialization. */ -CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, - { CPU_LIST_TERMINAL } -}; - /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index 5583a8b118..1e2ebb07f1 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -62,23 +62,6 @@ * needed by the system. */ -/* The fixed MTRR values to be set after memory initialization. */ -CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1E }, - { CPU_LIST_TERMINAL } -}; - #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -108,7 +91,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE //#define BLDCFG_STARTING_BUSNUM 0 //#define BLDCFG_MAXIMUM_BUSNUM 0xf8 diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c index ebbf9c7275..bbc8f00b68 100644 --- a/src/mainboard/elmex/pcm205400/buildOpts.c +++ b/src/mainboard/elmex/pcm205400/buildOpts.c @@ -83,7 +83,6 @@ #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE //#define BLDCFG_STARTING_BUSNUM 0 //#define BLDCFG_MAXIMUM_BUSNUM 0xf8 @@ -157,23 +156,6 @@ */ #include -/* The fixed MTRR values to be set after memory initialization. */ -CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, - { CPU_LIST_TERMINAL } -}; - /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c index 02b248fa7e..cda2d9d461 100644 --- a/src/mainboard/gizmosphere/gizmo/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c @@ -83,7 +83,6 @@ #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE //#define BLDCFG_STARTING_BUSNUM 0 //#define BLDCFG_MAXIMUM_BUSNUM 0xf8 @@ -157,23 +156,6 @@ */ #include -/* The fixed MTRR values to be set after memory initialization. */ -CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, - { CPU_LIST_TERMINAL } -}; - /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index 39d9d7e28b..02a416a8c1 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -97,7 +97,6 @@ #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE //#define BLDCFG_STARTING_BUSNUM 0 //#define BLDCFG_MAXIMUM_BUSNUM 0xf8 @@ -170,23 +169,6 @@ * needed by the system. */ -/* The fixed MTRR values to be set after memory initialization. */ -const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, - { CPU_LIST_TERMINAL } -}; - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 /**< DDR 400 */ #define DDR533_FREQUENCY 266 /**< DDR 533 */ diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c index 02b248fa7e..cda2d9d461 100644 --- a/src/mainboard/lippert/frontrunner-af/buildOpts.c +++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c @@ -83,7 +83,6 @@ #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE //#define BLDCFG_STARTING_BUSNUM 0 //#define BLDCFG_MAXIMUM_BUSNUM 0xf8 @@ -157,23 +156,6 @@ */ #include -/* The fixed MTRR values to be set after memory initialization. */ -CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, - { CPU_LIST_TERMINAL } -}; - /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c index 02b248fa7e..cda2d9d461 100644 --- a/src/mainboard/lippert/toucan-af/buildOpts.c +++ b/src/mainboard/lippert/toucan-af/buildOpts.c @@ -83,7 +83,6 @@ #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE //#define BLDCFG_STARTING_BUSNUM 0 //#define BLDCFG_MAXIMUM_BUSNUM 0xf8 @@ -157,23 +156,6 @@ */ #include -/* The fixed MTRR values to be set after memory initialization. */ -CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, - { CPU_LIST_TERMINAL } -}; - /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c index 4780c33304..5f9272086a 100644 --- a/src/mainboard/pcengines/apu1/buildOpts.c +++ b/src/mainboard/pcengines/apu1/buildOpts.c @@ -83,7 +83,6 @@ #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE //#define BLDCFG_STARTING_BUSNUM 0 //#define BLDCFG_MAXIMUM_BUSNUM 0xf8 @@ -157,23 +156,6 @@ */ #include -/* The fixed MTRR values to be set after memory initialization. */ -CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, - { CPU_LIST_TERMINAL } -}; - /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" diff --git a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h index 86fe800a2a..9aa9cbd16a 100644 --- a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h @@ -65,6 +65,23 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { NULL }; +/* The default fixed MTRR values to be set after memory initialization */ +static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, + { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, + { CPU_LIST_TERMINAL }, +}; + /* Process solution defined socket / family installations * * As part of the release package for each image, define the options below to select the @@ -1079,7 +1096,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_AP_MTRR_SETTINGS_LIST #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST) #else - #define CFG_AP_MTRR_SETTINGS_LIST (NULL) + #define CFG_AP_MTRR_SETTINGS_LIST (&OntarioApMtrrSettingsList) #endif /*--------------------------------------------------------------------------- From 5f82370d7bc4ba385ae8911cbfdabd4450f0e944 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 21 May 2020 01:06:28 +0200 Subject: [PATCH 258/405] AGESA f14/f15tn/f16kb: Factor out PCI MMIO base/size We set BLDCFG_PCI_MMIO_BASE and BLDCFG_PCI_MMIO_SIZE to the same values everywhere, so we might as well factor them out. As we have equivalent Kconfig options in coreboot, also deprecate overriding them via BLDCFG. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: I7244c39d2c2aa02a3a9092ddae98e4ac9da89107 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41595 Tested-by: build bot (Jenkins) Reviewed-by: Mike Banon --- src/mainboard/amd/inagua/buildOpts.c | 3 --- src/mainboard/amd/olivehill/buildOpts.c | 2 -- src/mainboard/amd/parmer/buildOpts.c | 2 -- src/mainboard/amd/persimmon/buildOpts.c | 3 --- src/mainboard/amd/south_station/buildOpts.c | 3 --- src/mainboard/amd/thatcher/buildOpts.c | 2 -- src/mainboard/amd/union_station/buildOpts.c | 3 --- src/mainboard/asrock/e350m1/buildOpts.c | 3 --- src/mainboard/asrock/imb-a180/buildOpts.c | 2 -- src/mainboard/asus/am1i-a/buildOpts.c | 2 -- src/mainboard/asus/f2a85-m/buildOpts.c | 2 -- src/mainboard/bap/ode_e20XX/buildOpts.c | 2 -- src/mainboard/biostar/a68n_5200/buildOpts.c | 2 -- src/mainboard/biostar/am1ml/buildOpts.c | 2 -- src/mainboard/elmex/pcm205400/buildOpts.c | 3 --- src/mainboard/gizmosphere/gizmo/buildOpts.c | 3 --- src/mainboard/gizmosphere/gizmo2/buildOpts.c | 2 -- src/mainboard/hp/abm/buildOpts.c | 2 -- .../hp/pavilion_m6_1035dx/buildOpts.c | 2 -- src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 3 --- src/mainboard/lenovo/g505s/buildOpts.c | 2 -- .../lippert/frontrunner-af/buildOpts.c | 3 --- src/mainboard/lippert/toucan-af/buildOpts.c | 3 --- src/mainboard/msi/ms7721/buildOpts.c | 2 -- src/mainboard/pcengines/apu1/buildOpts.c | 3 --- .../amd/agesa/f14/Config/PlatformInstall.h | 19 +++++++++---------- .../amd/agesa/f15tn/Config/PlatformInstall.h | 19 +++++++++---------- .../amd/agesa/f16kb/Config/PlatformInstall.h | 19 +++++++++---------- 28 files changed, 27 insertions(+), 91 deletions(-) diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index 781dde3cc7..4729577be7 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -54,9 +54,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER - #define BLDCFG_VRM_CURRENT_LIMIT 24000 //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index dfcb46508a..d2bc4e78b8 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -66,8 +66,6 @@ //#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER /* Build configuration values here. */ #define BLDCFG_VRM_CURRENT_LIMIT 15000 diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index e1c71c366e..a3cbb7e4f7 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -63,8 +63,6 @@ //#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER /* Build configuration values here. */ #define BLDCFG_VRM_CURRENT_LIMIT 90000 diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index cda2d9d461..5f18c39e97 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -54,9 +54,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER - #define BLDCFG_VRM_CURRENT_LIMIT 24000 //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index 8bddb38abd..d3d65713cb 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -54,9 +54,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER - #define BLDCFG_VRM_CURRENT_LIMIT 24000 //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index e1c3cd237c..53929b8f35 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -63,8 +63,6 @@ //#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER /* Build configuration values here. */ #define BLDCFG_VRM_CURRENT_LIMIT 90000 diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index 8bddb38abd..d3d65713cb 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -54,9 +54,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER - #define BLDCFG_VRM_CURRENT_LIMIT 24000 //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index 1e2ebb07f1..5f8700b659 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -62,9 +62,6 @@ * needed by the system. */ -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER - #define BLDCFG_VRM_CURRENT_LIMIT 24000 //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c index 97d49c765d..99b6180c71 100644 --- a/src/mainboard/asrock/imb-a180/buildOpts.c +++ b/src/mainboard/asrock/imb-a180/buildOpts.c @@ -66,8 +66,6 @@ //#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER /* Build configuration values here. */ #define BLDCFG_VRM_CURRENT_LIMIT 15000 diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index e2c01fcfee..a364982f46 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -82,8 +82,6 @@ //#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER /* Build configuration values here. */ #define BLDCFG_VRM_CURRENT_LIMIT 15000 diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 6c368cbe1d..38d302e760 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -76,8 +76,6 @@ //#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER /* Build configuration values here. */ #define BLDCFG_VRM_CURRENT_LIMIT 90000 diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c index 0d98c02d9e..2bcabf404a 100644 --- a/src/mainboard/bap/ode_e20XX/buildOpts.c +++ b/src/mainboard/bap/ode_e20XX/buildOpts.c @@ -66,8 +66,6 @@ //#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER /* Build configuration values here. */ #define BLDCFG_VRM_CURRENT_LIMIT 15000 diff --git a/src/mainboard/biostar/a68n_5200/buildOpts.c b/src/mainboard/biostar/a68n_5200/buildOpts.c index dfcb46508a..d2bc4e78b8 100644 --- a/src/mainboard/biostar/a68n_5200/buildOpts.c +++ b/src/mainboard/biostar/a68n_5200/buildOpts.c @@ -66,8 +66,6 @@ //#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER /* Build configuration values here. */ #define BLDCFG_VRM_CURRENT_LIMIT 15000 diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c index 5e9f256c17..b9a3efea3e 100644 --- a/src/mainboard/biostar/am1ml/buildOpts.c +++ b/src/mainboard/biostar/am1ml/buildOpts.c @@ -66,8 +66,6 @@ //#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER /* Build configuration values here. */ #define BLDCFG_VRM_CURRENT_LIMIT 15000 diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c index bbc8f00b68..8c34cd6dba 100644 --- a/src/mainboard/elmex/pcm205400/buildOpts.c +++ b/src/mainboard/elmex/pcm205400/buildOpts.c @@ -54,9 +54,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER - #define BLDCFG_VRM_CURRENT_LIMIT 24000 //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c index cda2d9d461..5f18c39e97 100644 --- a/src/mainboard/gizmosphere/gizmo/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c @@ -54,9 +54,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER - #define BLDCFG_VRM_CURRENT_LIMIT 24000 //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c index 0d98c02d9e..2bcabf404a 100644 --- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c @@ -66,8 +66,6 @@ //#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER /* Build configuration values here. */ #define BLDCFG_VRM_CURRENT_LIMIT 15000 diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index 7ebf119d9b..a649c737c1 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -71,8 +71,6 @@ //#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER /* Build configuration values here. */ #define BLDCFG_VRM_CURRENT_LIMIT 15000 diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 17b58047ba..e7ff996145 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -77,8 +77,6 @@ //#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER /* Build configuration values here. */ #define BLDCFG_VRM_CURRENT_LIMIT 90000 diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index 02a416a8c1..a20d133f3a 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -68,9 +68,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER - #define BLDCFG_VRM_CURRENT_LIMIT 24000 //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index 789bb40979..f4993d6450 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -77,8 +77,6 @@ //#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER /* Build configuration values here. */ #define BLDCFG_VRM_CURRENT_LIMIT 90000 diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c index cda2d9d461..5f18c39e97 100644 --- a/src/mainboard/lippert/frontrunner-af/buildOpts.c +++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c @@ -54,9 +54,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER - #define BLDCFG_VRM_CURRENT_LIMIT 24000 //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c index cda2d9d461..5f18c39e97 100644 --- a/src/mainboard/lippert/toucan-af/buildOpts.c +++ b/src/mainboard/lippert/toucan-af/buildOpts.c @@ -54,9 +54,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER - #define BLDCFG_VRM_CURRENT_LIMIT 24000 //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index aaa88b6a09..4029bc3781 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -76,8 +76,6 @@ //#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER /* Build configuration values here. */ #define BLDCFG_VRM_CURRENT_LIMIT 90000 diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c index 5f9272086a..639d605a9f 100644 --- a/src/mainboard/pcengines/apu1/buildOpts.c +++ b/src/mainboard/pcengines/apu1/buildOpts.c @@ -54,9 +54,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER - #define BLDCFG_VRM_CURRENT_LIMIT 24000 //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 diff --git a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h index 9aa9cbd16a..2de9de5b6e 100644 --- a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h @@ -1081,17 +1081,9 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #define CFG_PLATFORM_POWER_POLICY_MODE (Performance) #endif -#ifdef BLDCFG_PCI_MMIO_BASE - #define CFG_PCI_MMIO_BASE (BLDCFG_PCI_MMIO_BASE) -#else - #define CFG_PCI_MMIO_BASE (0) -#endif +#define CFG_PCI_MMIO_BASE (CONFIG_MMCONF_BASE_ADDRESS) -#ifdef BLDCFG_PCI_MMIO_SIZE - #define CFG_PCI_MMIO_SIZE (BLDCFG_PCI_MMIO_SIZE) -#else - #define CFG_PCI_MMIO_SIZE (0) -#endif +#define CFG_PCI_MMIO_SIZE (CONFIG_MMCONF_BUS_NUMBER) #ifdef BLDCFG_AP_MTRR_SETTINGS_LIST #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST) @@ -1102,6 +1094,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; /*--------------------------------------------------------------------------- * Processing the options: Third, perform the option cross checks *--------------------------------------------------------------------------*/ +// Check that deprecated options are not used +#ifdef BLDCFG_PCI_MMIO_BASE + #error BLDOPT: BLDCFG_PCI_MMIO_BASE has been deprecated in coreboot. Do not use! +#endif +#ifdef BLDCFG_PCI_MMIO_SIZE + #error BLDOPT: BLDCFG_PCI_MMIO_SIZE has been deprecated in coreboot. Do not use! +#endif // Assure that at least one type of memory support is included #if OPTION_UDIMMS == FALSE #if OPTION_RDIMMS == FALSE diff --git a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h index 70c213509a..63dae95969 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h @@ -2418,17 +2418,9 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #define CFG_PLATFORM_POWER_POLICY_MODE (Performance) #endif -#ifdef BLDCFG_PCI_MMIO_BASE - #define CFG_PCI_MMIO_BASE (BLDCFG_PCI_MMIO_BASE) -#else - #define CFG_PCI_MMIO_BASE (0) -#endif +#define CFG_PCI_MMIO_BASE (CONFIG_MMCONF_BASE_ADDRESS) -#ifdef BLDCFG_PCI_MMIO_SIZE - #define CFG_PCI_MMIO_SIZE (BLDCFG_PCI_MMIO_SIZE) -#else - #define CFG_PCI_MMIO_SIZE (0) -#endif +#define CFG_PCI_MMIO_SIZE (CONFIG_MMCONF_BUS_NUMBER) #ifdef BLDCFG_AP_MTRR_SETTINGS_LIST #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST) @@ -2445,6 +2437,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; /*--------------------------------------------------------------------------- * Processing the options: Third, perform the option cross checks *--------------------------------------------------------------------------*/ +// Check that deprecated options are not used +#ifdef BLDCFG_PCI_MMIO_BASE + #error BLDOPT: BLDCFG_PCI_MMIO_BASE has been deprecated in coreboot. Do not use! +#endif +#ifdef BLDCFG_PCI_MMIO_SIZE + #error BLDOPT: BLDCFG_PCI_MMIO_SIZE has been deprecated in coreboot. Do not use! +#endif // Assure that at least one type of memory support is included #if OPTION_UDIMMS == FALSE #if OPTION_RDIMMS == FALSE diff --git a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h index 90c4e3fbff..6c84bcb6fd 100644 --- a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h @@ -1426,17 +1426,9 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #define CFG_LHTC_TEMPERATURE_LIMIT (0) #endif -#ifdef BLDCFG_PCI_MMIO_BASE - #define CFG_PCI_MMIO_BASE (BLDCFG_PCI_MMIO_BASE) -#else - #define CFG_PCI_MMIO_BASE (0) -#endif +#define CFG_PCI_MMIO_BASE (CONFIG_MMCONF_BASE_ADDRESS) -#ifdef BLDCFG_PCI_MMIO_SIZE - #define CFG_PCI_MMIO_SIZE (BLDCFG_PCI_MMIO_SIZE) -#else - #define CFG_PCI_MMIO_SIZE (0) -#endif +#define CFG_PCI_MMIO_SIZE (CONFIG_MMCONF_BUS_NUMBER) #ifdef BLDCFG_AP_MTRR_SETTINGS_LIST #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST) @@ -1501,6 +1493,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; /*--------------------------------------------------------------------------- * Processing the options: Third, perform the option cross checks *--------------------------------------------------------------------------*/ +// Check that deprecated options are not used +#ifdef BLDCFG_PCI_MMIO_BASE + #error BLDOPT: BLDCFG_PCI_MMIO_BASE has been deprecated in coreboot. Do not use! +#endif +#ifdef BLDCFG_PCI_MMIO_SIZE + #error BLDOPT: BLDCFG_PCI_MMIO_SIZE has been deprecated in coreboot. Do not use! +#endif // Assure that at least one type of memory support is included #if OPTION_UDIMMS == FALSE #if OPTION_RDIMMS == FALSE From 7e577ad22f2f7fb6e2fca062f87c93e1c1dc3344 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 21 May 2020 15:14:07 +0200 Subject: [PATCH 259/405] AGESA f14/f15tn/f16kb: Factor out memory settings We use the same values everywhere, so we might as well factor them out. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Ie6f166034d5d642dff37730a8d83264fb2e019b4 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41663 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Krystian Hebel --- src/mainboard/amd/inagua/buildOpts.c | 11 ----------- src/mainboard/amd/olivehill/buildOpts.c | 11 ----------- src/mainboard/amd/parmer/buildOpts.c | 11 ----------- src/mainboard/amd/persimmon/buildOpts.c | 11 ----------- src/mainboard/amd/south_station/buildOpts.c | 11 ----------- src/mainboard/amd/thatcher/buildOpts.c | 11 ----------- src/mainboard/amd/union_station/buildOpts.c | 11 ----------- src/mainboard/asrock/e350m1/buildOpts.c | 11 ----------- src/mainboard/asrock/imb-a180/buildOpts.c | 11 ----------- src/mainboard/asus/am1i-a/buildOpts.c | 11 ----------- src/mainboard/asus/f2a85-m/buildOpts.c | 11 ----------- src/mainboard/bap/ode_e20XX/buildOpts.c | 11 ----------- src/mainboard/biostar/a68n_5200/buildOpts.c | 11 ----------- src/mainboard/biostar/am1ml/buildOpts.c | 11 ----------- src/mainboard/elmex/pcm205400/buildOpts.c | 11 ----------- src/mainboard/gizmosphere/gizmo/buildOpts.c | 11 ----------- src/mainboard/gizmosphere/gizmo2/buildOpts.c | 11 ----------- src/mainboard/hp/abm/buildOpts.c | 11 ----------- src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 11 ----------- src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 13 ------------- src/mainboard/lenovo/g505s/buildOpts.c | 11 ----------- src/mainboard/lippert/frontrunner-af/buildOpts.c | 11 ----------- src/mainboard/lippert/toucan-af/buildOpts.c | 11 ----------- src/mainboard/msi/ms7721/buildOpts.c | 11 ----------- src/mainboard/pcengines/apu1/buildOpts.c | 11 ----------- .../amd/agesa/f14/Config/PlatformInstall.h | 16 ++++++++-------- .../amd/agesa/f15tn/Config/PlatformInstall.h | 16 ++++++++-------- .../amd/agesa/f16kb/Config/PlatformInstall.h | 16 ++++++++-------- 28 files changed, 24 insertions(+), 301 deletions(-) diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index 4729577be7..1ac2266ab7 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -191,16 +191,5 @@ #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - // Instantiate all solution relevant data. #include diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index d2bc4e78b8..5ea4c0c81a 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -300,15 +300,4 @@ GPIO_CONTROL olivehill_gpio[] = { }; //#define BLDCFG_FCH_GPIO_CONTROL_LIST (&olivehill_gpio[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - #include diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index a3cbb7e4f7..05ac8c6dd3 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -302,15 +302,4 @@ GPIO_CONTROL parmer_gpio[] = { }; #define BLDCFG_FCH_GPIO_CONTROL_LIST (&parmer_gpio[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - #include diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 5f18c39e97..66d1a74b3d 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -191,16 +191,5 @@ #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - // Instantiate all solution relevant data. #include diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index d3d65713cb..29668bcc87 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -191,16 +191,5 @@ #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - // Instantiate all solution relevant data. #include diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index 53929b8f35..a97e8f0952 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -302,15 +302,4 @@ GPIO_CONTROL thatcher_gpio[] = { }; #define BLDCFG_FCH_GPIO_CONTROL_LIST (&thatcher_gpio[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - #include diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index d3d65713cb..29668bcc87 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -191,16 +191,5 @@ #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - // Instantiate all solution relevant data. #include diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index 5f8700b659..6fba259328 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -197,16 +197,5 @@ #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - // Instantiate all solution relevant data. #include diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c index 99b6180c71..042fe59367 100644 --- a/src/mainboard/asrock/imb-a180/buildOpts.c +++ b/src/mainboard/asrock/imb-a180/buildOpts.c @@ -300,15 +300,4 @@ GPIO_CONTROL imba180_gpio[] = { }; //#define BLDCFG_FCH_GPIO_CONTROL_LIST (&imba180_gpio[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - #include diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index a364982f46..fde272a9ba 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -313,16 +313,5 @@ GPIO_CONTROL imba180_gpio[] = { }; //#define BLDCFG_FCH_GPIO_CONTROL_LIST (&imba180_gpio[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - /* AGESA nonsense: this header depends on the definitions above */ #include diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 38d302e760..8bb0b80cf4 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -303,16 +303,5 @@ GPIO_CONTROL f2a85_m_gpio[] = { }; #define BLDCFG_FCH_GPIO_CONTROL_LIST (&f2a85_m_gpio[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - /* Moving this include up will break AGESA. */ #include diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c index 2bcabf404a..b615353693 100644 --- a/src/mainboard/bap/ode_e20XX/buildOpts.c +++ b/src/mainboard/bap/ode_e20XX/buildOpts.c @@ -300,15 +300,4 @@ GPIO_CONTROL gizmo2_gpio[] = { }; //#define BLDCFG_FCH_GPIO_CONTROL_LIST (&gizmo2_gpio[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - #include diff --git a/src/mainboard/biostar/a68n_5200/buildOpts.c b/src/mainboard/biostar/a68n_5200/buildOpts.c index d2bc4e78b8..5ea4c0c81a 100644 --- a/src/mainboard/biostar/a68n_5200/buildOpts.c +++ b/src/mainboard/biostar/a68n_5200/buildOpts.c @@ -300,15 +300,4 @@ GPIO_CONTROL olivehill_gpio[] = { }; //#define BLDCFG_FCH_GPIO_CONTROL_LIST (&olivehill_gpio[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - #include diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c index b9a3efea3e..24f8da0e37 100644 --- a/src/mainboard/biostar/am1ml/buildOpts.c +++ b/src/mainboard/biostar/am1ml/buildOpts.c @@ -300,15 +300,4 @@ GPIO_CONTROL imba180_gpio[] = { }; //#define BLDCFG_FCH_GPIO_CONTROL_LIST (&imba180_gpio[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - #include diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c index 8c34cd6dba..7fa480b220 100644 --- a/src/mainboard/elmex/pcm205400/buildOpts.c +++ b/src/mainboard/elmex/pcm205400/buildOpts.c @@ -191,16 +191,5 @@ #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - // Instantiate all solution relevant data. #include diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c index 5f18c39e97..66d1a74b3d 100644 --- a/src/mainboard/gizmosphere/gizmo/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c @@ -191,16 +191,5 @@ #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - // Instantiate all solution relevant data. #include diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c index 2bcabf404a..b615353693 100644 --- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c @@ -300,15 +300,4 @@ GPIO_CONTROL gizmo2_gpio[] = { }; //#define BLDCFG_FCH_GPIO_CONTROL_LIST (&gizmo2_gpio[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - #include diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index a649c737c1..919096843b 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -314,15 +314,4 @@ GPIO_CONTROL hp_abm_gpio[] = { }; #define BLDCFG_FCH_GPIO_CONTROL_LIST (&hp_abm_gpio[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - #include diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index e7ff996145..8e90a08ebf 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -346,16 +346,5 @@ SCI_MAP_CONTROL m6_1035dx_sci_map[] = { }; #define BLDCFG_FCH_SCI_MAP_LIST (&m6_1035dx_sci_map[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - /* AGESA nonsense: this header depends on the definitions above */ #include diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index a20d133f3a..1e81f5b497 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -190,19 +190,6 @@ #define POWER_DOWN_BY_CHANNEL 0 /**< Channel power down mode */ #define POWER_DOWN_BY_CHIP_SELECT 1 /**< Chip select power down mode */ -/** - * The following definitions specify the default values for various parameters - * in which there are no clearly defined defaults to be used in the common - * file. The values below are based on product and BKDG content. - */ -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - /* AGESA nonsense: this header depends on the definitions above */ /* Instantiate all solution relevant data. */ #include diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index f4993d6450..fd1c977da4 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -346,16 +346,5 @@ SCI_MAP_CONTROL lenovo_g505s_sci_map[] = { }; #define BLDCFG_FCH_SCI_MAP_LIST (&lenovo_g505s_sci_map[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - /* AGESA nonsense: this header depends on the definitions above */ #include diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c index 5f18c39e97..66d1a74b3d 100644 --- a/src/mainboard/lippert/frontrunner-af/buildOpts.c +++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c @@ -191,16 +191,5 @@ #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - // Instantiate all solution relevant data. #include diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c index 5f18c39e97..66d1a74b3d 100644 --- a/src/mainboard/lippert/toucan-af/buildOpts.c +++ b/src/mainboard/lippert/toucan-af/buildOpts.c @@ -191,16 +191,5 @@ #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - // Instantiate all solution relevant data. #include diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index 4029bc3781..c969d54d5e 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -303,16 +303,5 @@ GPIO_CONTROL ms7721_m_gpio[] = { }; #define BLDCFG_FCH_GPIO_CONTROL_LIST (&ms7721_m_gpio[0]) -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - /* Moving this include up will break AGESA. */ #include diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c index 639d605a9f..a810559f37 100644 --- a/src/mainboard/pcengines/apu1/buildOpts.c +++ b/src/mainboard/pcengines/apu1/buildOpts.c @@ -191,16 +191,5 @@ #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - // Instantiate all solution relevant data. #include diff --git a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h index 2de9de5b6e..883d509bca 100644 --- a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h @@ -583,7 +583,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_VRM_SLEW_RATE #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE #else - #define CFG_VRM_SLEW_RATE DFLT_VRM_SLEW_RATE + #define CFG_VRM_SLEW_RATE (5000) #endif #ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT @@ -613,7 +613,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_VRM_NB_SLEW_RATE #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE #else - #define CFG_VRM_NB_SLEW_RATE DFLT_VRM_SLEW_RATE + #define CFG_VRM_NB_SLEW_RATE (5000) #endif #ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT @@ -722,7 +722,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_MEMORY_QUADRANK_TYPE #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE #else - #define CFG_MEMORY_QUADRANK_TYPE DFLT_MEMORY_QUADRANK_TYPE + #define CFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #endif #ifdef BLDCFG_MEMORY_RDIMM_CAPABLE @@ -848,31 +848,31 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_SCRUB_DRAM_RATE #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE #else - #define CFG_SCRUB_DRAM_RATE DFLT_SCRUB_DRAM_RATE + #define CFG_SCRUB_DRAM_RATE (0) #endif #ifdef BLDCFG_SCRUB_L2_RATE #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE #else - #define CFG_SCRUB_L2_RATE DFLT_SCRUB_L2_RATE + #define CFG_SCRUB_L2_RATE (0) #endif #ifdef BLDCFG_SCRUB_L3_RATE #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE #else - #define CFG_SCRUB_L3_RATE DFLT_SCRUB_L3_RATE + #define CFG_SCRUB_L3_RATE (0) #endif #ifdef BLDCFG_SCRUB_IC_RATE #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE #else - #define CFG_SCRUB_IC_RATE DFLT_SCRUB_IC_RATE + #define CFG_SCRUB_IC_RATE (0) #endif #ifdef BLDCFG_SCRUB_DC_RATE #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE #else - #define CFG_SCRUB_DC_RATE DFLT_SCRUB_DC_RATE + #define CFG_SCRUB_DC_RATE (0) #endif #ifdef BLDCFG_ECC_SYNC_FLOOD diff --git a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h index 63dae95969..d769220dd2 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h @@ -1758,7 +1758,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_VRM_SLEW_RATE #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE #else - #define CFG_VRM_SLEW_RATE DFLT_VRM_SLEW_RATE + #define CFG_VRM_SLEW_RATE (5000) #endif #ifdef BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT @@ -1820,7 +1820,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_VRM_NB_SLEW_RATE #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE #else - #define CFG_VRM_NB_SLEW_RATE DFLT_VRM_SLEW_RATE + #define CFG_VRM_NB_SLEW_RATE (5000) #endif #ifdef BLDCFG_PLAT_NUM_IO_APICS @@ -1928,7 +1928,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_MEMORY_QUADRANK_TYPE #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE #else - #define CFG_MEMORY_QUADRANK_TYPE DFLT_MEMORY_QUADRANK_TYPE + #define CFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #endif #ifdef BLDCFG_MEMORY_RDIMM_CAPABLE @@ -2060,31 +2060,31 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_SCRUB_DRAM_RATE #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE #else - #define CFG_SCRUB_DRAM_RATE DFLT_SCRUB_DRAM_RATE + #define CFG_SCRUB_DRAM_RATE (0) #endif #ifdef BLDCFG_SCRUB_L2_RATE #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE #else - #define CFG_SCRUB_L2_RATE DFLT_SCRUB_L2_RATE + #define CFG_SCRUB_L2_RATE (0) #endif #ifdef BLDCFG_SCRUB_L3_RATE #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE #else - #define CFG_SCRUB_L3_RATE DFLT_SCRUB_L3_RATE + #define CFG_SCRUB_L3_RATE (0) #endif #ifdef BLDCFG_SCRUB_IC_RATE #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE #else - #define CFG_SCRUB_IC_RATE DFLT_SCRUB_IC_RATE + #define CFG_SCRUB_IC_RATE (0) #endif #ifdef BLDCFG_SCRUB_DC_RATE #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE #else - #define CFG_SCRUB_DC_RATE DFLT_SCRUB_DC_RATE + #define CFG_SCRUB_DC_RATE (0) #endif #ifdef BLDCFG_ECC_SYNC_FLOOD diff --git a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h index 6c84bcb6fd..ff5b91c291 100644 --- a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h @@ -747,7 +747,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_VRM_SLEW_RATE #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE #else - #define CFG_VRM_SLEW_RATE DFLT_VRM_SLEW_RATE + #define CFG_VRM_SLEW_RATE (5000) #endif #ifdef BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT @@ -789,7 +789,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_VRM_NB_SLEW_RATE #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE #else - #define CFG_VRM_NB_SLEW_RATE DFLT_VRM_SLEW_RATE + #define CFG_VRM_NB_SLEW_RATE (5000) #endif #ifdef BLDCFG_PLAT_NUM_IO_APICS @@ -897,7 +897,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_MEMORY_QUADRANK_TYPE #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE #else - #define CFG_MEMORY_QUADRANK_TYPE DFLT_MEMORY_QUADRANK_TYPE + #define CFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #endif #ifdef BLDCFG_MEMORY_RDIMM_CAPABLE @@ -1029,31 +1029,31 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_SCRUB_DRAM_RATE #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE #else - #define CFG_SCRUB_DRAM_RATE DFLT_SCRUB_DRAM_RATE + #define CFG_SCRUB_DRAM_RATE (0) #endif #ifdef BLDCFG_SCRUB_L2_RATE #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE #else - #define CFG_SCRUB_L2_RATE DFLT_SCRUB_L2_RATE + #define CFG_SCRUB_L2_RATE (0) #endif #ifdef BLDCFG_SCRUB_L3_RATE #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE #else - #define CFG_SCRUB_L3_RATE DFLT_SCRUB_L3_RATE + #define CFG_SCRUB_L3_RATE (0) #endif #ifdef BLDCFG_SCRUB_IC_RATE #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE #else - #define CFG_SCRUB_IC_RATE DFLT_SCRUB_IC_RATE + #define CFG_SCRUB_IC_RATE (0) #endif #ifdef BLDCFG_SCRUB_DC_RATE #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE #else - #define CFG_SCRUB_DC_RATE DFLT_SCRUB_DC_RATE + #define CFG_SCRUB_DC_RATE (0) #endif #ifdef BLDCFG_ECC_SYNC_FLOOD From 7ee8e7f12969f3141fd0b1c814c3b648268156b8 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 21 May 2020 15:24:42 +0200 Subject: [PATCH 260/405] AGESA f15tn: Factor out default MTRR settings All AGESA f15tn boards use the same MTRR values. Factor them out, while still allowing a board to override them via BLDCFG. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: I90c95493de1bb5b8f32c06b9575fef3aa7aca031 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41664 Tested-by: build bot (Jenkins) Reviewed-by: Mike Banon --- src/mainboard/amd/parmer/buildOpts.c | 18 ------------------ src/mainboard/amd/thatcher/buildOpts.c | 18 ------------------ src/mainboard/asus/f2a85-m/buildOpts.c | 18 ------------------ .../hp/pavilion_m6_1035dx/buildOpts.c | 18 ------------------ src/mainboard/lenovo/g505s/buildOpts.c | 18 ------------------ src/mainboard/msi/ms7721/buildOpts.c | 18 ------------------ .../amd/agesa/f15tn/Config/PlatformInstall.h | 18 +++++++++++++++++- 7 files changed, 17 insertions(+), 109 deletions(-) diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 05ac8c6dd3..c8af85807e 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -194,24 +194,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE -CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index a97e8f0952..c4e0fce9a9 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -194,24 +194,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE -CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 8bb0b80cf4..13f2bd80af 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -207,24 +207,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE -CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 8e90a08ebf..19aac23fdd 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -208,24 +208,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE -CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index fd1c977da4..92a1c6921b 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -208,24 +208,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE -CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index c969d54d5e..c7c44267f6 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -207,24 +207,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE -CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h index d769220dd2..1bca388000 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h @@ -62,6 +62,22 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { NULL }; +/* The default fixed MTRR values to be set after memory initialization */ +static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, + { CPU_LIST_TERMINAL }, +}; /* Process solution defined socket / family installations * @@ -2425,7 +2441,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_AP_MTRR_SETTINGS_LIST #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST) #else - #define CFG_AP_MTRR_SETTINGS_LIST (NULL) + #define CFG_AP_MTRR_SETTINGS_LIST (TrinityApMtrrSettingsList) #endif #ifdef BLDCFG_IOMMU_EXCLUSION_RANGE_LIST From 64829161111ea833453df8479d1bada1f91ee511 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 21 May 2020 15:29:17 +0200 Subject: [PATCH 261/405] AGESA f16kb: Factor out default MTRR settings All AGESA f16kb boards use the same MTRR values. Factor them out, while still allowing a board to override them via BLDCFG. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: I236e9d45505e92027acc3ba5ff496f5e2f09b9f3 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41665 Tested-by: build bot (Jenkins) Reviewed-by: Mike Banon --- src/mainboard/amd/olivehill/buildOpts.c | 18 ------------------ src/mainboard/asrock/imb-a180/buildOpts.c | 18 ------------------ src/mainboard/asus/am1i-a/buildOpts.c | 18 ------------------ src/mainboard/bap/ode_e20XX/buildOpts.c | 18 ------------------ src/mainboard/biostar/a68n_5200/buildOpts.c | 18 ------------------ src/mainboard/biostar/am1ml/buildOpts.c | 18 ------------------ src/mainboard/gizmosphere/gizmo2/buildOpts.c | 18 ------------------ src/mainboard/hp/abm/buildOpts.c | 18 ------------------ .../amd/agesa/f16kb/Config/PlatformInstall.h | 19 ++++++++++++++++++- 9 files changed, 18 insertions(+), 145 deletions(-) diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index 5ea4c0c81a..cd2aa2ebd1 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -192,24 +192,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE -CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList - /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c index 042fe59367..9145a174b2 100644 --- a/src/mainboard/asrock/imb-a180/buildOpts.c +++ b/src/mainboard/asrock/imb-a180/buildOpts.c @@ -192,24 +192,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE -CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList - /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index fde272a9ba..b57581f092 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -218,24 +218,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE -CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList - /* MEMORY_BUS_SPEED */ //#define DDR400_FREQUENCY 200 ///< DDR 400 //#define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c index b615353693..a42bbcac38 100644 --- a/src/mainboard/bap/ode_e20XX/buildOpts.c +++ b/src/mainboard/bap/ode_e20XX/buildOpts.c @@ -192,24 +192,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE -CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList - /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" diff --git a/src/mainboard/biostar/a68n_5200/buildOpts.c b/src/mainboard/biostar/a68n_5200/buildOpts.c index 5ea4c0c81a..cd2aa2ebd1 100644 --- a/src/mainboard/biostar/a68n_5200/buildOpts.c +++ b/src/mainboard/biostar/a68n_5200/buildOpts.c @@ -192,24 +192,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE -CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList - /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c index 24f8da0e37..61cbf0f961 100644 --- a/src/mainboard/biostar/am1ml/buildOpts.c +++ b/src/mainboard/biostar/am1ml/buildOpts.c @@ -192,24 +192,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE -CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList - /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c index b615353693..a42bbcac38 100644 --- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c @@ -192,24 +192,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE -CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList - /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index 919096843b..8efd0a2b8c 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -197,24 +197,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE -CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList - /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" diff --git a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h index ff5b91c291..686dfb153a 100644 --- a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h @@ -62,6 +62,23 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { NULL }; +/* The default fixed MTRR values to be set after memory initialization */ +static const AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, + { CPU_LIST_TERMINAL }, +}; + /* Process solution defined socket / family installations * * As part of the release package for each image, define the options below to select the @@ -1433,7 +1450,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_AP_MTRR_SETTINGS_LIST #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST) #else - #define CFG_AP_MTRR_SETTINGS_LIST (NULL) + #define CFG_AP_MTRR_SETTINGS_LIST (KabiniApMtrrSettingsList) #endif #ifdef BLDCFG_IOMMU_EXCLUSION_RANGE_LIST From ec6e03e4d8b75af84bbc5698912202edf43ba20a Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 21 May 2020 16:30:00 +0200 Subject: [PATCH 262/405] AGESA f14/f15tn/f16kb: Deduplicate RAM settings On AGESA f14/f15tn, various RAM-related options were defined in an enum. However, the preprocessor mess can't compare enum values. To make AGESA build, each board redefined them as macros, shadowing the enum elements. Clean this up by replacing the enums with macros in AGESA headers, and delete the now-redundant redefinitions from all the mainboards. Note that AGESA f16kb already uses macros, but each mainboard still had commented-out definitions. Remove them as well, as they are unnecessary. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Ie1085539013d3ae0363b1596fa48555300e45172 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41666 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/mainboard/amd/inagua/buildOpts.c | 24 -------- src/mainboard/amd/olivehill/buildOpts.c | 27 --------- src/mainboard/amd/parmer/buildOpts.c | 27 --------- src/mainboard/amd/persimmon/buildOpts.c | 24 -------- src/mainboard/amd/south_station/buildOpts.c | 24 -------- src/mainboard/amd/thatcher/buildOpts.c | 27 --------- src/mainboard/amd/union_station/buildOpts.c | 24 -------- src/mainboard/asrock/e350m1/buildOpts.c | 24 -------- src/mainboard/asrock/imb-a180/buildOpts.c | 27 --------- src/mainboard/asus/am1i-a/buildOpts.c | 27 --------- src/mainboard/asus/f2a85-m/buildOpts.c | 27 --------- src/mainboard/bap/ode_e20XX/buildOpts.c | 27 --------- src/mainboard/biostar/a68n_5200/buildOpts.c | 27 --------- src/mainboard/biostar/am1ml/buildOpts.c | 27 --------- src/mainboard/elmex/pcm205400/buildOpts.c | 24 -------- src/mainboard/gizmosphere/gizmo/buildOpts.c | 24 -------- src/mainboard/gizmosphere/gizmo2/buildOpts.c | 27 --------- src/mainboard/hp/abm/buildOpts.c | 27 --------- .../hp/pavilion_m6_1035dx/buildOpts.c | 27 --------- src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 30 ---------- src/mainboard/lenovo/g505s/buildOpts.c | 27 --------- .../lippert/frontrunner-af/buildOpts.c | 24 -------- src/mainboard/lippert/toucan-af/buildOpts.c | 24 -------- src/mainboard/msi/ms7721/buildOpts.c | 27 --------- src/mainboard/pcengines/apu1/buildOpts.c | 24 -------- src/vendorcode/amd/agesa/f14/AGESA.h | 50 ++++++++--------- src/vendorcode/amd/agesa/f15tn/AGESA.h | 56 +++++++++---------- 27 files changed, 53 insertions(+), 701 deletions(-) diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index 1ac2266ab7..aecc9a5b08 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -167,29 +167,5 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency - -/* QUANDRANK_TYPE */ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM - -/* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed - -/* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - // Instantiate all solution relevant data. #include diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index cd2aa2ebd1..f5ac742727 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -205,33 +205,6 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* MEMORY_BUS_SPEED */ -//#define DDR400_FREQUENCY 200 ///< DDR 400 -//#define DDR533_FREQUENCY 266 ///< DDR 533 -//#define DDR667_FREQUENCY 333 ///< DDR 667 -//#define DDR800_FREQUENCY 400 ///< DDR 800 -//#define DDR1066_FREQUENCY 533 ///< DDR 1066 -//#define DDR1333_FREQUENCY 667 ///< DDR 1333 -//#define DDR1600_FREQUENCY 800 ///< DDR 1600 -//#define DDR1866_FREQUENCY 933 ///< DDR 1866 -//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -// -///* QUANDRANK_TYPE */ -//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM -// -///* USER_MEMORY_TIMING_MODE */ -//#define TIMING_MODE_AUTO 0 ///< Use best rate possible -//#define TIMING_MODE_LIMITED 1 ///< Set user top limit -//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed -// -///* POWER_DOWN_MODE */ -//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - /* * Agesa optional capabilities selection. * Uncomment and mark FALSE those features you wish to include in the build. diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index c8af85807e..694eda7a1b 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -207,33 +207,6 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency - -/* QUANDRANK_TYPE */ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM - -/* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed - -/* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - /* * Agesa optional capabilities selection. * Uncomment and mark FALSE those features you wish to include in the build. diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 66d1a74b3d..91c2182361 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -167,29 +167,5 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency - -/* QUANDRANK_TYPE */ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM - -/* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed - -/* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - // Instantiate all solution relevant data. #include diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index 29668bcc87..44248a25e5 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -167,29 +167,5 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency - -/* QUANDRANK_TYPE */ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM - -/* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed - -/* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - // Instantiate all solution relevant data. #include diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index c4e0fce9a9..f9908ef309 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -207,33 +207,6 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency - -/* QUANDRANK_TYPE */ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM - -/* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed - -/* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - /* * Agesa optional capabilities selection. * Uncomment and mark FALSE those features you wish to include in the build. diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index 29668bcc87..44248a25e5 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -167,29 +167,5 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency - -/* QUANDRANK_TYPE */ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM - -/* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed - -/* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - // Instantiate all solution relevant data. #include diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index 6fba259328..701d7ee196 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -173,29 +173,5 @@ // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} -/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency - -/* QUANDRANK_TYPE */ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM - -/* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed - -/* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - // Instantiate all solution relevant data. #include diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c index 9145a174b2..34561210f7 100644 --- a/src/mainboard/asrock/imb-a180/buildOpts.c +++ b/src/mainboard/asrock/imb-a180/buildOpts.c @@ -205,33 +205,6 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* MEMORY_BUS_SPEED */ -//#define DDR400_FREQUENCY 200 ///< DDR 400 -//#define DDR533_FREQUENCY 266 ///< DDR 533 -//#define DDR667_FREQUENCY 333 ///< DDR 667 -//#define DDR800_FREQUENCY 400 ///< DDR 800 -//#define DDR1066_FREQUENCY 533 ///< DDR 1066 -//#define DDR1333_FREQUENCY 667 ///< DDR 1333 -//#define DDR1600_FREQUENCY 800 ///< DDR 1600 -//#define DDR1866_FREQUENCY 933 ///< DDR 1866 -//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -// -///* QUANDRANK_TYPE */ -//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM -// -///* USER_MEMORY_TIMING_MODE */ -//#define TIMING_MODE_AUTO 0 ///< Use best rate possible -//#define TIMING_MODE_LIMITED 1 ///< Set user top limit -//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed -// -///* POWER_DOWN_MODE */ -//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - /* * Agesa optional capabilities selection. * Uncomment and mark FALSE those features you wish to include in the build. diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index b57581f092..d0a8a433ef 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -218,33 +218,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE -/* MEMORY_BUS_SPEED */ -//#define DDR400_FREQUENCY 200 ///< DDR 400 -//#define DDR533_FREQUENCY 266 ///< DDR 533 -//#define DDR667_FREQUENCY 333 ///< DDR 667 -//#define DDR800_FREQUENCY 400 ///< DDR 800 -//#define DDR1066_FREQUENCY 533 ///< DDR 1066 -//#define DDR1333_FREQUENCY 667 ///< DDR 1333 -//#define DDR1600_FREQUENCY 800 ///< DDR 1600 -//#define DDR1866_FREQUENCY 933 ///< DDR 1866 -//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -// -///* QUANDRANK_TYPE */ -//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM -// -///* USER_MEMORY_TIMING_MODE */ -//#define TIMING_MODE_AUTO 0 ///< Use best rate possible -//#define TIMING_MODE_LIMITED 1 ///< Set user top limit -//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed -// -///* POWER_DOWN_MODE */ -//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - /* * Agesa optional capabilities selection. * Uncomment and mark FALSE those features you wish to include in the build. diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 13f2bd80af..65731aae86 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -207,33 +207,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE -/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency - -/* QUANDRANK_TYPE */ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM - -/* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed - -/* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - /* * Agesa optional capabilities selection. * Uncomment and mark FALSE those features you wish to include in the build. diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c index a42bbcac38..d4c398adba 100644 --- a/src/mainboard/bap/ode_e20XX/buildOpts.c +++ b/src/mainboard/bap/ode_e20XX/buildOpts.c @@ -205,33 +205,6 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* MEMORY_BUS_SPEED */ -//#define DDR400_FREQUENCY 200 ///< DDR 400 -//#define DDR533_FREQUENCY 266 ///< DDR 533 -//#define DDR667_FREQUENCY 333 ///< DDR 667 -//#define DDR800_FREQUENCY 400 ///< DDR 800 -//#define DDR1066_FREQUENCY 533 ///< DDR 1066 -//#define DDR1333_FREQUENCY 667 ///< DDR 1333 -//#define DDR1600_FREQUENCY 800 ///< DDR 1600 -//#define DDR1866_FREQUENCY 933 ///< DDR 1866 -//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -// -///* QUANDRANK_TYPE */ -//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM -// -///* USER_MEMORY_TIMING_MODE */ -//#define TIMING_MODE_AUTO 0 ///< Use best rate possible -//#define TIMING_MODE_LIMITED 1 ///< Set user top limit -//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed -// -///* POWER_DOWN_MODE */ -//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - /* * Agesa optional capabilities selection. * Uncomment and mark FALSE those features you wish to include in the build. diff --git a/src/mainboard/biostar/a68n_5200/buildOpts.c b/src/mainboard/biostar/a68n_5200/buildOpts.c index cd2aa2ebd1..f5ac742727 100644 --- a/src/mainboard/biostar/a68n_5200/buildOpts.c +++ b/src/mainboard/biostar/a68n_5200/buildOpts.c @@ -205,33 +205,6 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* MEMORY_BUS_SPEED */ -//#define DDR400_FREQUENCY 200 ///< DDR 400 -//#define DDR533_FREQUENCY 266 ///< DDR 533 -//#define DDR667_FREQUENCY 333 ///< DDR 667 -//#define DDR800_FREQUENCY 400 ///< DDR 800 -//#define DDR1066_FREQUENCY 533 ///< DDR 1066 -//#define DDR1333_FREQUENCY 667 ///< DDR 1333 -//#define DDR1600_FREQUENCY 800 ///< DDR 1600 -//#define DDR1866_FREQUENCY 933 ///< DDR 1866 -//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -// -///* QUANDRANK_TYPE */ -//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM -// -///* USER_MEMORY_TIMING_MODE */ -//#define TIMING_MODE_AUTO 0 ///< Use best rate possible -//#define TIMING_MODE_LIMITED 1 ///< Set user top limit -//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed -// -///* POWER_DOWN_MODE */ -//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - /* * Agesa optional capabilities selection. * Uncomment and mark FALSE those features you wish to include in the build. diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c index 61cbf0f961..54f92466b3 100644 --- a/src/mainboard/biostar/am1ml/buildOpts.c +++ b/src/mainboard/biostar/am1ml/buildOpts.c @@ -205,33 +205,6 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* MEMORY_BUS_SPEED */ -//#define DDR400_FREQUENCY 200 ///< DDR 400 -//#define DDR533_FREQUENCY 266 ///< DDR 533 -//#define DDR667_FREQUENCY 333 ///< DDR 667 -//#define DDR800_FREQUENCY 400 ///< DDR 800 -//#define DDR1066_FREQUENCY 533 ///< DDR 1066 -//#define DDR1333_FREQUENCY 667 ///< DDR 1333 -//#define DDR1600_FREQUENCY 800 ///< DDR 1600 -//#define DDR1866_FREQUENCY 933 ///< DDR 1866 -//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -// -///* QUANDRANK_TYPE */ -//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM -// -///* USER_MEMORY_TIMING_MODE */ -//#define TIMING_MODE_AUTO 0 ///< Use best rate possible -//#define TIMING_MODE_LIMITED 1 ///< Set user top limit -//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed -// -///* POWER_DOWN_MODE */ -//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - /* * Agesa optional capabilities selection. * Uncomment and mark FALSE those features you wish to include in the build. diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c index 7fa480b220..be07053185 100644 --- a/src/mainboard/elmex/pcm205400/buildOpts.c +++ b/src/mainboard/elmex/pcm205400/buildOpts.c @@ -167,29 +167,5 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency - -/* QUANDRANK_TYPE */ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM - -/* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed - -/* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - // Instantiate all solution relevant data. #include diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c index 66d1a74b3d..91c2182361 100644 --- a/src/mainboard/gizmosphere/gizmo/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c @@ -167,29 +167,5 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency - -/* QUANDRANK_TYPE */ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM - -/* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed - -/* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - // Instantiate all solution relevant data. #include diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c index a42bbcac38..d4c398adba 100644 --- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c @@ -205,33 +205,6 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* MEMORY_BUS_SPEED */ -//#define DDR400_FREQUENCY 200 ///< DDR 400 -//#define DDR533_FREQUENCY 266 ///< DDR 533 -//#define DDR667_FREQUENCY 333 ///< DDR 667 -//#define DDR800_FREQUENCY 400 ///< DDR 800 -//#define DDR1066_FREQUENCY 533 ///< DDR 1066 -//#define DDR1333_FREQUENCY 667 ///< DDR 1333 -//#define DDR1600_FREQUENCY 800 ///< DDR 1600 -//#define DDR1866_FREQUENCY 933 ///< DDR 1866 -//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -// -///* QUANDRANK_TYPE */ -//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM -// -///* USER_MEMORY_TIMING_MODE */ -//#define TIMING_MODE_AUTO 0 ///< Use best rate possible -//#define TIMING_MODE_LIMITED 1 ///< Set user top limit -//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed -// -///* POWER_DOWN_MODE */ -//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - /* * Agesa optional capabilities selection. * Uncomment and mark FALSE those features you wish to include in the build. diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index 8efd0a2b8c..12974844ec 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -210,33 +210,6 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* MEMORY_BUS_SPEED */ -//#define DDR400_FREQUENCY 200 ///< DDR 400 -//#define DDR533_FREQUENCY 266 ///< DDR 533 -//#define DDR667_FREQUENCY 333 ///< DDR 667 -//#define DDR800_FREQUENCY 400 ///< DDR 800 -//#define DDR1066_FREQUENCY 533 ///< DDR 1066 -//#define DDR1333_FREQUENCY 667 ///< DDR 1333 -//#define DDR1600_FREQUENCY 800 ///< DDR 1600 -//#define DDR1866_FREQUENCY 933 ///< DDR 1866 -//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -// -///* QUANDRANK_TYPE */ -//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM -// -///* USER_MEMORY_TIMING_MODE */ -//#define TIMING_MODE_AUTO 0 ///< Use best rate possible -//#define TIMING_MODE_LIMITED 1 ///< Set user top limit -//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed -// -///* POWER_DOWN_MODE */ -//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - /* * Agesa optional capabilities selection. * Uncomment and mark FALSE those features you wish to include in the build. diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 19aac23fdd..107c9937dc 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -208,33 +208,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE -/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency - -/* QUANDRANK_TYPE */ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM - -/* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed - -/* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - /* * Agesa optional capabilities selection. * Uncomment and mark FALSE those features you wish to include in the build. diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index 1e81f5b497..3bc97ea97a 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -160,36 +160,6 @@ #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 -/** - * AGESA configuration values selection. - * Uncomment and specify the value for the configuration options - * needed by the system. - */ - -/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 /**< DDR 400 */ -#define DDR533_FREQUENCY 266 /**< DDR 533 */ -#define DDR667_FREQUENCY 333 /**< DDR 667 */ -#define DDR800_FREQUENCY 400 /**< DDR 800 */ -#define DDR1066_FREQUENCY 533 /**< DDR 1066 */ -#define DDR1333_FREQUENCY 667 /**< DDR 1333 */ -#define DDR1600_FREQUENCY 800 /**< DDR 1600 */ -#define DDR1866_FREQUENCY 933 /**< DDR 1866 */ -#define UNSUPPORTED_DDR_FREQUENCY 934 /**< Max limit of DDR frequency */ - -/* QUANDRANK_TYPE */ -#define QUADRANK_REGISTERED 0 /**< Quadrank registered DIMM */ -#define QUADRANK_UNBUFFERED 1 /**< Quadrank unbuffered DIMM */ - -/* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 /**< Use best rate possible */ -#define TIMING_MODE_LIMITED 1 /**< Set user top limit */ -#define TIMING_MODE_SPECIFIC 2 /**< Set user specified speed */ - -/* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 /**< Channel power down mode */ -#define POWER_DOWN_BY_CHIP_SELECT 1 /**< Chip select power down mode */ - /* AGESA nonsense: this header depends on the definitions above */ /* Instantiate all solution relevant data. */ #include diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index 92a1c6921b..c78c5c5374 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -208,33 +208,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE -/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency - -/* QUANDRANK_TYPE */ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM - -/* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed - -/* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - /* * Agesa optional capabilities selection. * Uncomment and mark FALSE those features you wish to include in the build. diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c index 66d1a74b3d..91c2182361 100644 --- a/src/mainboard/lippert/frontrunner-af/buildOpts.c +++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c @@ -167,29 +167,5 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency - -/* QUANDRANK_TYPE */ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM - -/* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed - -/* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - // Instantiate all solution relevant data. #include diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c index 66d1a74b3d..91c2182361 100644 --- a/src/mainboard/lippert/toucan-af/buildOpts.c +++ b/src/mainboard/lippert/toucan-af/buildOpts.c @@ -167,29 +167,5 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency - -/* QUANDRANK_TYPE */ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM - -/* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed - -/* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - // Instantiate all solution relevant data. #include diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index c7c44267f6..61858940c0 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -207,33 +207,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE -/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency - -/* QUANDRANK_TYPE */ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM - -/* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed - -/* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - /* * Agesa optional capabilities selection. * Uncomment and mark FALSE those features you wish to include in the build. diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c index a810559f37..3a14ce5a25 100644 --- a/src/mainboard/pcengines/apu1/buildOpts.c +++ b/src/mainboard/pcengines/apu1/buildOpts.c @@ -167,29 +167,5 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency - -/* QUANDRANK_TYPE */ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM - -/* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed - -/* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - // Instantiate all solution relevant data. #include diff --git a/src/vendorcode/amd/agesa/f14/AGESA.h b/src/vendorcode/amd/agesa/f14/AGESA.h index 047b0371f2..03f1670049 100644 --- a/src/vendorcode/amd/agesa/f14/AGESA.h +++ b/src/vendorcode/amd/agesa/f14/AGESA.h @@ -1015,37 +1015,37 @@ typedef enum { } TECHNOLOGY_TYPE; /// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT -typedef enum { - DDR400_FREQUENCY = 200, ///< DDR 400 - DDR533_FREQUENCY = 266, ///< DDR 533 - DDR667_FREQUENCY = 333, ///< DDR 667 - DDR800_FREQUENCY = 400, ///< DDR 800 - DDR1066_FREQUENCY = 533, ///< DDR 1066 - DDR1333_FREQUENCY = 667, ///< DDR 1333 - DDR1600_FREQUENCY = 800, ///< DDR 1600 - DDR1866_FREQUENCY = 933, ///< DDR 1866 - UNSUPPORTED_DDR_FREQUENCY ///< Highest limit of DDR frequency -} MEMORY_BUS_SPEED; +typedef unsigned int MEMORY_BUS_SPEED; + +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency /// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE -typedef enum { - QUADRANK_REGISTERED, ///< Quadrank registered DIMM - QUADRANK_UNBUFFERED ///< Quadrank unbuffered DIMM -} QUANDRANK_TYPE; +typedef unsigned int QUANDRANK_TYPE; + +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM /// Build Configuration values for BLDCFG_TIMING_MODE_SELECT -typedef enum { - TIMING_MODE_AUTO, ///< Use best rate possible - TIMING_MODE_LIMITED, ///< Set user top limit - TIMING_MODE_SPECIFIC ///< Set user specified speed -} USER_MEMORY_TIMING_MODE; +typedef unsigned int USER_MEMORY_TIMING_MODE; + +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed /// Build Configuration values for BLDCFG_POWER_DOWN_MODE -typedef enum { - POWER_DOWN_BY_CHANNEL, ///< Channel power down mode - POWER_DOWN_BY_CHIP_SELECT, ///< Chip select power down mode - POWER_DOWN_MODE_AUTO ///< AGESA to select power down mode -} POWER_DOWN_MODE; +typedef unsigned int POWER_DOWN_MODE; + +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_MODE_AUTO 2 ///< AGESA to select power down mode /// Low voltage support typedef enum { diff --git a/src/vendorcode/amd/agesa/f15tn/AGESA.h b/src/vendorcode/amd/agesa/f15tn/AGESA.h index 3ac9071f65..922a8ee633 100644 --- a/src/vendorcode/amd/agesa/f15tn/AGESA.h +++ b/src/vendorcode/amd/agesa/f15tn/AGESA.h @@ -1382,40 +1382,40 @@ typedef enum { } TECHNOLOGY_TYPE; /// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT -typedef enum { - DDR400_FREQUENCY = 200, ///< DDR 400 - DDR533_FREQUENCY = 266, ///< DDR 533 - DDR667_FREQUENCY = 333, ///< DDR 667 - DDR800_FREQUENCY = 400, ///< DDR 800 - DDR1066_FREQUENCY = 533, ///< DDR 1066 - DDR1333_FREQUENCY = 667, ///< DDR 1333 - DDR1600_FREQUENCY = 800, ///< DDR 1600 - DDR1866_FREQUENCY = 933, ///< DDR 1866 - DDR2100_FREQUENCY = 1050, ///< DDR 2100 - DDR2133_FREQUENCY = 1066, ///< DDR 2133 - DDR2400_FREQUENCY = 1200, ///< DDR 2400 - UNSUPPORTED_DDR_FREQUENCY ///< Highest limit of DDR frequency -} MEMORY_BUS_SPEED; +typedef unsigned int MEMORY_BUS_SPEED; + +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define DDR2100_FREQUENCY 1050 ///< DDR 2100 +#define DDR2133_FREQUENCY 1066 ///< DDR 2133 +#define DDR2400_FREQUENCY 1200 ///< DDR 2400 +#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency /// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE -typedef enum { - QUADRANK_REGISTERED, ///< Quadrank registered DIMM - QUADRANK_UNBUFFERED ///< Quadrank unbuffered DIMM -} QUANDRANK_TYPE; +typedef unsigned int QUANDRANK_TYPE; + +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM /// Build Configuration values for BLDCFG_TIMING_MODE_SELECT -typedef enum { - TIMING_MODE_AUTO, ///< Use best rate possible - TIMING_MODE_LIMITED, ///< Set user top limit - TIMING_MODE_SPECIFIC ///< Set user specified speed -} USER_MEMORY_TIMING_MODE; +typedef unsigned int USER_MEMORY_TIMING_MODE; + +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed /// Build Configuration values for BLDCFG_POWER_DOWN_MODE -typedef enum { - POWER_DOWN_BY_CHANNEL, ///< Channel power down mode - POWER_DOWN_BY_CHIP_SELECT, ///< Chip select power down mode - POWER_DOWN_MODE_AUTO ///< AGESA to select power down mode -} POWER_DOWN_MODE; +typedef unsigned int POWER_DOWN_MODE; + +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_MODE_AUTO 2 ///< AGESA to select power down mode /// Low voltage support typedef enum { From a0bf2d6cf5135214a3d96cc980b7255b0eb2c9c4 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 24 May 2020 21:24:38 +0200 Subject: [PATCH 263/405] superio/ite/Makefile.inc: Add it8613e This Super I/O was not being built at all. Correct that. Change-Id: Id053fa919cac7b2df6a6fc45aae5e34a0dc8c0ae Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41688 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Felix Held Reviewed-by: Paul Menzel --- src/superio/ite/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index 1fc29fd20b..f2ebda05fb 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -8,6 +8,7 @@ romstage-$(CONFIG_SUPERIO_ITE_COMMON_PRE_RAM) += common/early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_ENV_CTRL) += common/env_ctrl.c subdirs-y += it8528e +subdirs-y += it8613e subdirs-y += it8623e subdirs-y += it8671f subdirs-y += it8712f From 93b62e61709be4cd69232dd05a8097af5a7dd297 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 31 Jan 2020 12:53:45 -0700 Subject: [PATCH 264/405] soc/amd/picasso: Give the mainboard the ability to modify the MADT table By default legacy ISA IRQs use edge triggering. Depending on what devices are used the IRQ types might need to be changed. We add a setting to the device tree to allow the mainboard to configure the IRS IRQs. BUG=b:145102877 TEST=Booted trembyle and was able to use the keyboard. Change-Id: Ie95e8cc7ca835fb60bee8f10d5f28def6c2801dc Signed-off-by: Raul E Rangel Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2033493 Reviewed-by: Martin Roth Reviewed-on: https://review.coreboot.org/c/coreboot/+/41577 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/amd/picasso/acpi.c | 23 +++++++++++++++++++++-- src/soc/amd/picasso/chip.h | 12 ++++++++++++ 2 files changed, 33 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index ac23d0f1e9..2eea6f9aeb 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -23,6 +24,7 @@ #include #include #include +#include "chip.h" unsigned long acpi_fill_mcfg(unsigned long current) { @@ -38,6 +40,11 @@ unsigned long acpi_fill_mcfg(unsigned long current) unsigned long acpi_fill_madt(unsigned long current) { + const struct soc_amd_picasso_config *cfg = config_of_soc(); + unsigned int i; + uint8_t irq; + uint8_t flags; + /* create all subtables for processors */ current = acpi_create_madt_lapics(current); @@ -51,8 +58,20 @@ unsigned long acpi_fill_madt(unsigned long current) /* 5 mean: 0101 --> Edge-triggered, Active high */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xf); + current += acpi_create_madt_irqoverride( + (acpi_madt_irqoverride_t *)current, 0, 9, 9, + MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + for (i = 0; i < ARRAY_SIZE(cfg->irq_override); ++i) { + irq = cfg->irq_override[i].irq; + flags = cfg->irq_override[i].flags; + + if (!flags) + continue; + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, + irq, irq, flags); + } /* create all subtables for processors */ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 80cb1ceab2..e52751a2eb 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -12,6 +12,7 @@ #include #include #include +#include struct soc_amd_picasso_config { struct soc_amd_common_config common_config; @@ -34,6 +35,17 @@ struct soc_amd_picasso_config { I2S_PINS_UNCONF = 7, /* All pads will be input mode */ } acp_pin_cfg; + /** + * IRQ 0 - 15 have a default trigger of edge and default polarity of high. + * If you have a device that requires a different configuration you can override the + * settings here. + */ + struct { + uint8_t irq; + /* See MP_IRQ_* from mpspec.h */ + uint8_t flags; + } irq_override[16]; + /* Options for these are in src/arch/x86/include/acpi/acpi.h */ uint8_t fadt_pm_profile; uint16_t fadt_boot_arch; From a1b19de44768d2e2ea483fe7f59de66eee3a3a49 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 1 Apr 2020 13:35:48 +0200 Subject: [PATCH 265/405] Documentation/acpi: Fix the path to variants/hatch/overridetree.cb Change-Id: I7c3fd942318f28b4714bc7c2a47bedf85f7923ed Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40012 Tested-by: build bot (Jenkins) Reviewed-by: Christian Walter Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- Documentation/acpi/devicetree.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/acpi/devicetree.md b/Documentation/acpi/devicetree.md index c3c4c2e402..e8680e359f 100644 --- a/Documentation/acpi/devicetree.md +++ b/Documentation/acpi/devicetree.md @@ -23,7 +23,7 @@ write the ASL (ACPI Source Language) code yourself. ## Device drivers Let's take a look at an example entry from -``src/mainboard/google/hatch/variant/hatch/overridetree.cb``: +``src/mainboard/google/hatch/variants/hatch/overridetree.cb``: ``` device pci 15.0 on From bfc255a12146a364f0d08ee9818af715a485a579 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 7 Mar 2020 13:05:14 +0100 Subject: [PATCH 266/405] src/sb: Use 'print("%s...", __func__)' Change-Id: Ie0d845d3e501ed5ebeef1997944445d31768e410 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39373 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/southbridge/amd/agesa/hudson/hudson.c | 2 +- src/southbridge/amd/agesa/hudson/smi.c | 2 +- src/southbridge/amd/cimx/sb800/late.c | 4 +-- src/southbridge/amd/cimx/sb800/lpc.c | 12 ++++---- src/southbridge/amd/cimx/sb800/smbus.c | 36 +++++++++++------------ src/southbridge/amd/pi/hudson/hudson.c | 2 +- src/southbridge/amd/pi/hudson/smi.c | 2 +- src/southbridge/intel/bd82x6x/lpc.c | 4 +-- src/southbridge/intel/i82801gx/lpc.c | 2 +- src/southbridge/intel/i82801ix/lpc.c | 2 +- src/southbridge/intel/i82801jx/lpc.c | 2 +- src/southbridge/intel/i82870/ioapic.c | 4 +-- src/southbridge/intel/ibexpeak/lpc.c | 2 +- src/southbridge/intel/lynxpoint/lpc.c | 2 +- 14 files changed, 39 insertions(+), 39 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index 3f04987328..3609314f4e 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -39,7 +39,7 @@ static void hudson_disable_usb(u8 disable) void hudson_enable(struct device *dev) { - printk(BIOS_DEBUG, "hudson_enable()\n"); + printk(BIOS_DEBUG, "%s()\n", __func__); switch (dev->path.pci.devfn) { case PCI_DEVFN(0x14, 5): if (dev->enabled == 0) { diff --git a/src/southbridge/amd/agesa/hudson/smi.c b/src/southbridge/amd/agesa/hudson/smi.c index 567a3f89fc..9e6db341fd 100644 --- a/src/southbridge/amd/agesa/hudson/smi.c +++ b/src/southbridge/amd/agesa/hudson/smi.c @@ -12,7 +12,7 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { - printk(BIOS_DEBUG, "smm_setup_structures STUB!!!\n"); + printk(BIOS_DEBUG, "%s STUB!!!\n", __func__); } /** Set the EOS bit and enable SMI generation from southbridge */ diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index cf84b2140c..1cf3ae8d00 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -108,7 +108,7 @@ static struct pci_operations lops_pci = { static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__); cmos_check_update_date(); @@ -122,7 +122,7 @@ static void lpc_init(struct device *dev) setup_i8259(); /* Initialize i8259 pic */ setup_i8254(); /* Initialize i8254 timers */ - printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n"); + printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__); } unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index 9517d95031..a082e0ca5a 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -11,7 +11,7 @@ void lpc_read_resources(struct device *dev) { struct resource *res; - printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_read_resources - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - Start.\n", __func__); /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ @@ -37,14 +37,14 @@ void lpc_read_resources(struct device *dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; compact_resources(dev); - printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_read_resources - End.\n"); + printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - End.\n", __func__); } void lpc_set_resources(struct device *dev) { struct resource *res; - printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - Start.\n", __func__); /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ res = find_resource(dev, 2); @@ -52,7 +52,7 @@ void lpc_set_resources(struct device *dev) pci_dev_set_resources(dev); - printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - End.\n"); + printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - End.\n", __func__); } /** @@ -68,7 +68,7 @@ void lpc_enable_childrens_resources(struct device *dev) int var_num = 0; u16 reg_var[3]; - printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_enable_childrens_resources - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - Start.\n", __func__); reg = pci_read_config32(dev, 0x44); reg_x = pci_read_config32(dev, 0x48); @@ -166,5 +166,5 @@ void lpc_enable_childrens_resources(struct device *dev) //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata break; } - printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_enable_childrens_resources - End.\n"); + printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - End.\n", __func__); } diff --git a/src/southbridge/amd/cimx/sb800/smbus.c b/src/southbridge/amd/cimx/sb800/smbus.c index bc9d92119a..86bde267ff 100644 --- a/src/southbridge/amd/cimx/sb800/smbus.c +++ b/src/southbridge/amd/cimx/sb800/smbus.c @@ -50,11 +50,11 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - smbus not ready.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - smbus not ready.\n", __func__); return -2; /* not ready */ } - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); /* set the device I'm talking to */ outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); @@ -71,7 +71,7 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device) /* read results of transaction */ byte = inb(smbus_io_base + SMBHSTCMD); - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - End.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); return byte; } @@ -80,11 +80,11 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - smbus not ready.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - smbus not ready.\n", __func__); return -2; /* not ready */ } - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); /* set the command... */ outb(val, smbus_io_base + SMBHSTCMD); @@ -101,7 +101,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) return -3; /* timeout or error */ } - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - End.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); return 0; } @@ -110,11 +110,11 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - smbus not ready.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - smbus not ready.\n", __func__); return -2; /* not ready */ } - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); /* set the command/address... */ outb(address & 0xff, smbus_io_base + SMBHSTCMD); @@ -134,7 +134,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) /* read results of transaction */ byte = inb(smbus_io_base + SMBHSTDAT0); - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - End.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); return byte; } @@ -143,11 +143,11 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - smbus not ready.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - smbus not ready.\n", __func__); return -2; /* not ready */ } - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); /* set the command/address... */ outb(address & 0xff, smbus_io_base + SMBHSTCMD); @@ -167,7 +167,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) return -3; /* timeout or error */ } - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - End.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); return 0; } @@ -175,7 +175,7 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) { u32 tmp; - printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ab_indx - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); tmp = inl(AB_DATA); /* rpr 4.2 @@ -191,14 +191,14 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ outl(tmp, AB_DATA); outl(0, AB_INDX); - printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ab_indx - End.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); } void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) { u32 tmp; - printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_rc_indx - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); tmp = inl(AB_DATA); /* rpr 4.2 @@ -214,7 +214,7 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ outl(tmp, AB_DATA); outl(0, AB_INDX); - printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_rc_indx - End.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); } /* space = 0: AX_INDXC, AX_DATAC @@ -224,7 +224,7 @@ void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val) { u32 tmp; - printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ax_indx - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); /* read axindc to tmp */ outl(space << 29 | space << 3 | 0x30, AB_INDX); outl(axindc, AB_DATA); @@ -243,5 +243,5 @@ void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val) outl(space << 29 | space << 3 | 0x34, AB_INDX); outl(tmp, AB_DATA); outl(0, AB_INDX); - printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ax_indx - End.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); } diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index 63fe473afb..852144b2db 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -26,7 +26,7 @@ int acpi_get_sleep_type(void) void hudson_enable(struct device *dev) { - printk(BIOS_DEBUG, "hudson_enable()\n"); + printk(BIOS_DEBUG, "%s()\n", __func__); switch (dev->path.pci.devfn) { case PCI_DEVFN(0x14, 7): /* SD */ if (dev->enabled == 0) { diff --git a/src/southbridge/amd/pi/hudson/smi.c b/src/southbridge/amd/pi/hudson/smi.c index 567a3f89fc..9e6db341fd 100644 --- a/src/southbridge/amd/pi/hudson/smi.c +++ b/src/southbridge/amd/pi/hudson/smi.c @@ -12,7 +12,7 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { - printk(BIOS_DEBUG, "smm_setup_structures STUB!!!\n"); + printk(BIOS_DEBUG, "%s STUB!!!\n", __func__); } /** Set the EOS bit and enable SMI generation from southbridge */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 0341de2fdc..987db360e2 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -446,7 +446,7 @@ static void pch_spi_init(const struct device *const dev) { const config_t *const config = dev->chip_info; - printk(BIOS_DEBUG, "pch_spi_init\n"); + printk(BIOS_DEBUG, "%s\n", __func__); if (config->spi_uvscc) RCBA32(0x3800 + 0xc8) = config->spi_uvscc; @@ -526,7 +526,7 @@ static void report_pch_info(struct device *dev) static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "pch: lpc_init\n"); + printk(BIOS_DEBUG, "pch: %s\n", __func__); /* Print detected platform */ report_pch_info(dev); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index b69dba49e5..7e2b5a7ca6 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -354,7 +354,7 @@ static void i82801gx_fixups(struct device *dev) static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "i82801gx: lpc_init\n"); + printk(BIOS_DEBUG, "i82801gx: %s\n", __func__); /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 455e3b816c..37f9852c64 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -366,7 +366,7 @@ static void i82801ix_set_acpi_mode(struct device *dev) static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "i82801ix: lpc_init\n"); + printk(BIOS_DEBUG, "i82801ix: %s\n", __func__); /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 73eaede288..ae98fddc2a 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -371,7 +371,7 @@ static void i82801jx_set_acpi_mode(struct device *dev) static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "i82801jx: lpc_init\n"); + printk(BIOS_DEBUG, "i82801jx: %s\n", __func__); /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c index 6be212f75c..4763703644 100644 --- a/src/southbridge/intel/i82870/ioapic.c +++ b/src/southbridge/intel/i82870/ioapic.c @@ -72,13 +72,13 @@ static void p64h2_ioapic_init(struct device *dev) *pWindowRegister = (*pWindowRegister & ~(0x0f << 24)) | apic_id; // Set the ID if ((*pWindowRegister & (0x0f << 24)) != apic_id) - die("p64h2_ioapic_init failed"); + die("%s failed", __func__); *pIndexRegister = 3; // Select Boot Configuration register *pWindowRegister |= 1; // Use Processor System Bus to deliver interrupts if (!(*pWindowRegister & 1)) - die("p64h2_ioapic_init failed"); + die("%s failed", __func__); } static struct device_operations ioapic_ops = { diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index f1fa0d22d3..0d15b5d8fa 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -441,7 +441,7 @@ static void pch_fixups(struct device *dev) static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "pch: lpc_init\n"); + printk(BIOS_DEBUG, "pch: %s\n", __func__); /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 3535312779..7e1355a7d5 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -509,7 +509,7 @@ static void pch_fixups(struct device *dev) static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "pch: lpc_init\n"); + printk(BIOS_DEBUG, "pch: %s\n", __func__); /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); From 38b58d4f51c80ad1fc416e48a79b47e75a109b34 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 17 May 2020 16:53:18 +0200 Subject: [PATCH 267/405] mb/google/foster: Remove unused 'include Change-Id: Ic26d03d0e695ce0823332d4c6430186c7bfbeac1 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41487 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/foster/mainboard.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/google/foster/mainboard.c b/src/mainboard/google/foster/mainboard.c index f18e95a2ed..4a56e8aae0 100644 --- a/src/mainboard/google/foster/mainboard.c +++ b/src/mainboard/google/foster/mainboard.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include From 95dcf29b2fcc9f7c02812d760ec0be492d5b7580 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 17 May 2020 16:54:08 +0200 Subject: [PATCH 268/405] drivers/intel/fsp2_0: Remove unused 'include ' Change-Id: Ic3eb8fca22e73a0d485a6c1bf35c33b1fc606e4a Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41488 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp2_0/temp_ram_exit.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c index 557cbb91a7..c3bfbba6af 100644 --- a/src/drivers/intel/fsp2_0/temp_ram_exit.c +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include From 9ea70c02cd0e5e28f38136ebbb6dbad72ad177c7 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 12 Oct 2019 15:16:33 +0200 Subject: [PATCH 269/405] intel/cannonlake: Implement PCIe RP devicetree update Some existing devicetrees were manually adapted to anticipate root-port switching. Now, their PCI-device on/off settings should just reflect the `PcieRpEnable` state and configuration happens on the PCI function that was assigned at reset. Change-Id: I4d76f38c222b74053c6a2f80b492d4660ab4db6d Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36651 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan Reviewed-by: Patrick Rudolph Reviewed-by: Furquan Shaikh Reviewed-by: Angel Pons --- .../hatch/variants/duffy/overridetree.cb | 5 ++--- .../hatch/variants/kaisa/overridetree.cb | 5 ++--- .../hatch/variants/puff/overridetree.cb | 5 ++--- .../sarien/variants/arcada/devicetree.cb | 6 +++--- src/mainboard/system76/lemp9/devicetree.cb | 2 +- src/soc/intel/cannonlake/chip.c | 20 +++++++++++++++++++ 6 files changed, 30 insertions(+), 13 deletions(-) diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb index d7acbd71e7..4e7692c1e9 100644 --- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb @@ -294,7 +294,7 @@ chip soc/intel/cannonlake end end #I2C #4 device pci 1a.0 on end # eMMC - device pci 1c.0 on + device pci 1c.6 on chip drivers/net register "customized_leds" = "0x05af" register "wake" = "GPE0_DW1_07" # GPP_C7 @@ -305,8 +305,7 @@ chip soc/intel/cannonlake register "device_index" = "0" device pci 00.0 on end end - end # FSP requires func0 be enabled. - device pci 1c.6 on end # RTL8111H Ethernet NIC (becomes RP1). + end # RTL8111H Ethernet NIC device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) device pci 1e.3 off end # GSPI #1 end diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb index f5e85bde23..c7655ac5c1 100644 --- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb @@ -294,7 +294,7 @@ chip soc/intel/cannonlake end end #I2C #4 device pci 1a.0 on end # eMMC - device pci 1c.0 on + device pci 1c.6 on chip drivers/net register "customized_leds" = "0x05af" register "wake" = "GPE0_DW1_07" # GPP_C7 @@ -305,8 +305,7 @@ chip soc/intel/cannonlake register "device_index" = "0" device pci 00.0 on end end - end # FSP requires func0 be enabled. - device pci 1c.6 on end # RTL8111H Ethernet NIC (becomes RP1). + end # RTL8111H Ethernet NIC device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) device pci 1e.3 off end # GSPI #1 end diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index 31efc4a1d9..83fcf9a76c 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -297,7 +297,7 @@ chip soc/intel/cannonlake end end #I2C #4 device pci 1a.0 on end # eMMC - device pci 1c.0 on + device pci 1c.6 on chip drivers/net register "customized_leds" = "0x05af" register "wake" = "GPE0_DW1_07" # GPP_C7 @@ -308,8 +308,7 @@ chip soc/intel/cannonlake register "device_index" = "0" device pci 00.0 on end end - end # FSP requires func0 be enabled. - device pci 1c.6 on end # RTL8111H Ethernet NIC (becomes RP1). + end # RTL8111H Ethernet NIC device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) device pci 1e.3 off end # GSPI #1 end diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 6bc3df11af..d1d9b038b2 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -373,10 +373,10 @@ chip soc/intel/cannonlake device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 on smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" - end # PCI Express Port 9 - device pci 1d.1 on end # PCI Express Port 10 + end # PCI Express Port 10 device pci 1d.2 on end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 3fa2c170e3..6cf0fff9de 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -207,7 +207,7 @@ chip soc/intel/cannonlake device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 off end # eMMC - device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.0 off end # PCI Express Port 1 device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 51678add67..ef85215623 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -16,6 +17,19 @@ #include "chip.h" +static const struct pcie_rp_group pch_lp_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, + { 0 } +}; + +static const struct pcie_rp_group pch_h_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 }, + { 0 } +}; + #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { @@ -166,6 +180,12 @@ void soc_init_pre_device(void *chip_info) cnl_configure_pads(NULL, 0); soc_gpio_pm_configuration(); + + /* swap enabled PCI ports in device tree if needed */ + if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) + pcie_rp_update_devicetree(pch_h_rp_groups); + else + pcie_rp_update_devicetree(pch_lp_rp_groups); } static struct device_operations pci_domain_ops = { From e6e9fa6ef90bc62d645da942f3bdc7bdeb1c1930 Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Wed, 6 May 2020 09:18:37 +0200 Subject: [PATCH 270/405] soc/intel/cannonlake: Add VrPowerDeliveryDesign to chip options Intel introduced the UPD VrPowerDeliveryDesign with Cannon Lake. The BIOS needs to program VrPowerDeliverDesign configuration per platform according to the platform capabilities to avoid incorrect electrial/power parameters. This is only added for Cannon Lake. Refer to document 599797 for more details. Change-Id: I89b8dceb40fa6a9dc67b218e91bf728ff928b5a0 Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/41081 Reviewed-by: Philipp Deppenwiese Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/chip.h | 4 ++++ src/soc/intel/cannonlake/fsp_params.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 4f015a71f7..f6ec7ce7cb 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -413,6 +413,10 @@ struct soc_intel_cannonlake_config { uint8_t LanWakeFromDeepSx; uint8_t WolEnableOverride; +#if !CONFIG(SOC_INTEL_COMETLAKE) + uint32_t VrPowerDeliveryDesign; +#endif + /* * Override GPIO PM configuration: * 0: Use FSP default GPIO PM program, diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index b432087a32..b7e9ad8d8b 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -459,6 +459,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) #endif } +#if !CONFIG(SOC_INTEL_COMETLAKE) + params->VrPowerDeliveryDesign = config->VrPowerDeliveryDesign; +#endif + dev = pcidev_path_on_root(SA_DEVFN_IGD); if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) params->PeiGraphicsPeimInit = 1; From 7d054bd38f5cfe36f6abd4f4422c463243bc3749 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Tue, 19 May 2020 11:10:21 -0700 Subject: [PATCH 271/405] soc/intel/tigerlake: Fix wrong operation region for CPU to PCH method CPU to PCH method refers to PCH ACPI operation region which was wrongly defined as SystemMemory and PCH_PWRM_BASE_ADDRESS. Change the operation region to be SystemIO and ACPI_BASE_ADDRESS. BUG=b:156530805 TEST=Built and booted to kernel. Signed-off-by: John zhao Change-Id: Ifa291a993ec23e1e4dfad8f6cdfabc80b824d20c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41537 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/soc/intel/tigerlake/acpi/tcss.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 7d586dd11e..abdcb515fa 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -45,10 +45,10 @@ Scope (\_SB) } /* - * Define PCH ACPIBASE as an ACPI operating region. The base address can be + * Define PCH ACPIBASE IO as an ACPI operating region. The base address can be * found in Device 31, Function 2, Offset 40h. */ - OperationRegion (PMIO, SystemMemory, PCH_PWRM_BASE_ADDRESS, 0x80) + OperationRegion (PMIO, SystemIO, ACPI_BASE_ADDRESS, 0x80) Field (PMIO, ByteAcc, NoLock, Preserve) { Offset(0x6C), /* 0x6C, General Purpose Event 0 Status [127:96] */ , 19, From 309ccf74dd7c25874572c6a62ffc7042dcdadc66 Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Sat, 9 May 2020 16:37:30 +0530 Subject: [PATCH 272/405] cannonlake: update processor power limits configuration Update processor power limit configuration parameters based on common code base support for Intel Cannonlake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on drallion system Change-Id: Iac6e6f81343fcd769619e9d7ac339430966834f6 Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/41235 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../drallion/variants/drallion/devicetree.cb | 8 +- .../hatch/variants/akemi/overridetree.cb | 6 +- .../hatch/variants/baseboard/devicetree.cb | 6 +- .../hatch/variants/dratini/overridetree.cb | 6 +- .../google/hatch/variants/duffy/mainboard.c | 9 +- .../hatch/variants/helios/overridetree.cb | 6 +- .../variants/helios_diskswap/overridetree.cb | 6 +- .../hatch/variants/jinlon/overridetree.cb | 6 +- .../google/hatch/variants/kaisa/mainboard.c | 9 +- .../hatch/variants/kindred/overridetree.cb | 6 +- .../hatch/variants/kohaku/overridetree.cb | 6 +- .../hatch/variants/mushu/overridetree.cb | 6 +- .../hatch/variants/nightfury/overridetree.cb | 6 +- .../hatch/variants/palkia/overridetree.cb | 6 +- .../google/hatch/variants/puff/mainboard.c | 7 +- .../sarien/variants/arcada/devicetree.cb | 8 +- .../sarien/variants/sarien/devicetree.cb | 8 +- src/mainboard/system76/lemp9/devicetree.cb | 6 +- src/soc/intel/cannonlake/Kconfig | 1 + src/soc/intel/cannonlake/chip.h | 21 +- src/soc/intel/cannonlake/cpu.c | 190 ------------------ src/soc/intel/cannonlake/fsp_params.c | 9 +- src/soc/intel/cannonlake/include/soc/cpu.h | 3 - src/soc/intel/cannonlake/systemagent.c | 8 +- 24 files changed, 98 insertions(+), 255 deletions(-) diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 9bb09abd98..e9daf0d00d 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -42,11 +42,13 @@ chip soc/intel/cannonlake register "PchUsb2PhySusPgDisable" = "1" register "speed_shift_enable" = "1" - register "psys_pmax" = "140" register "s0ix_enable" = "1" register "dptf_enable" = "1" - register "tdp_pl1_override" = "25" - register "tdp_pl2_override" = "51" + register "power_limits_config" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 51, + .psys_pmax = 140, + }" register "Device4Enable" = "1" register "AcousticNoiseMitigation" = "1" register "SlowSlewRateForIa" = "2" diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb index 27d11ccfb1..0e3972813a 100644 --- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -1,6 +1,8 @@ chip soc/intel/cannonlake - register "tdp_pl1_override" = "15" - register "tdp_pl2_override" = "51" + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 9894e56324..2d3156ae6b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -37,8 +37,10 @@ chip soc/intel/cannonlake register "s0ix_enable" = "1" # Enable DPTF register "dptf_enable" = "1" - register "tdp_pl1_override" = "15" - register "tdp_pl2_override" = "64" + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 64, + }" register "Device4Enable" = "1" # Enable eDP device register "DdiPortEdp" = "1" diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index 0bd3d8ee93..0bada7d916 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -1,6 +1,8 @@ chip soc/intel/cannonlake - register "tdp_pl1_override" = "15" - register "tdp_pl2_override" = "51" + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/google/hatch/variants/duffy/mainboard.c b/src/mainboard/google/hatch/variants/duffy/mainboard.c index ef5df4ae4b..ecc0937fa8 100644 --- a/src/mainboard/google/hatch/variants/duffy/mainboard.c +++ b/src/mainboard/google/hatch/variants/duffy/mainboard.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #define GPIO_HDMI_HPD GPP_E13 @@ -86,7 +87,7 @@ static void wait_for_hpd(gpio_t gpio, long timeout) #define PSYS_IMAX 9600 #define BJ_VOLTS_MV 19000 -static void mainboard_set_power_limits(config_t *conf) +static void mainboard_set_power_limits(struct soc_power_limits_config *conf) { enum usb_chg_type type; u32 watts; @@ -123,7 +124,8 @@ static void mainboard_set_power_limits(config_t *conf) void variant_ramstage_init(void) { static const long display_timeout_ms = 3000; - config_t *conf = config_of_soc(); + struct soc_power_limits_config *soc_config; + config_t *confg = config_of_soc(); /* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */ gpio_input(GPIO_HDMI_HPD); @@ -136,5 +138,6 @@ void variant_ramstage_init(void) wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); } /* Psys_pmax needs to be setup before FSP-S */ - mainboard_set_power_limits(conf); + soc_config = &confg->power_limits_config; + mainboard_set_power_limits(soc_config); } diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index 94639dcabe..0d73814249 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -1,6 +1,8 @@ chip soc/intel/cannonlake - register "tdp_pl1_override" = "15" - register "tdp_pl2_override" = "64" + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 64, + }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb index 8a3745d174..0422a57bd3 100644 --- a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb @@ -1,6 +1,8 @@ chip soc/intel/cannonlake - register "tdp_pl1_override" = "13" - register "tdp_pl2_override" = "64" + register "power_limits_config" = "{ + .tdp_pl1_override = 13, + .tdp_pl2_override = 64, + }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index 546267011d..a3bb782a36 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -1,6 +1,8 @@ chip soc/intel/cannonlake - register "tdp_pl1_override" = "15" - register "tdp_pl2_override" = "51" + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/google/hatch/variants/kaisa/mainboard.c b/src/mainboard/google/hatch/variants/kaisa/mainboard.c index ef5df4ae4b..ecc0937fa8 100644 --- a/src/mainboard/google/hatch/variants/kaisa/mainboard.c +++ b/src/mainboard/google/hatch/variants/kaisa/mainboard.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #define GPIO_HDMI_HPD GPP_E13 @@ -86,7 +87,7 @@ static void wait_for_hpd(gpio_t gpio, long timeout) #define PSYS_IMAX 9600 #define BJ_VOLTS_MV 19000 -static void mainboard_set_power_limits(config_t *conf) +static void mainboard_set_power_limits(struct soc_power_limits_config *conf) { enum usb_chg_type type; u32 watts; @@ -123,7 +124,8 @@ static void mainboard_set_power_limits(config_t *conf) void variant_ramstage_init(void) { static const long display_timeout_ms = 3000; - config_t *conf = config_of_soc(); + struct soc_power_limits_config *soc_config; + config_t *confg = config_of_soc(); /* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */ gpio_input(GPIO_HDMI_HPD); @@ -136,5 +138,6 @@ void variant_ramstage_init(void) wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); } /* Psys_pmax needs to be setup before FSP-S */ - mainboard_set_power_limits(conf); + soc_config = &confg->power_limits_config; + mainboard_set_power_limits(soc_config); } diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index 8afae3968b..43fdfbf5fa 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -1,6 +1,8 @@ chip soc/intel/cannonlake - register "tdp_pl1_override" = "15" - register "tdp_pl2_override" = "51" + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 08bbb2a9b0..df18277408 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -1,6 +1,8 @@ chip soc/intel/cannonlake - register "tdp_pl1_override" = "8" - register "tdp_pl2_override" = "51" + register "power_limits_config" = "{ + .tdp_pl1_override = 8, + .tdp_pl2_override = 51, + }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index 7bd1fac4e8..db86d68204 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -24,8 +24,10 @@ chip soc/intel/cannonlake register "FastPkgCRampDisableGt" = "1" register "FastPkgCRampDisableSa" = "1" - register "tdp_pl1_override" = "25" - register "tdp_pl2_override" = "44" + register "power_limits_config" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 44, + }" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index 2c759bc4bb..82f80a96f5 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -1,6 +1,8 @@ chip soc/intel/cannonlake - register "tdp_pl1_override" = "15" - register "tdp_pl2_override" = "51" + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/google/hatch/variants/palkia/overridetree.cb b/src/mainboard/google/hatch/variants/palkia/overridetree.cb index bce58011d3..31017bc01d 100644 --- a/src/mainboard/google/hatch/variants/palkia/overridetree.cb +++ b/src/mainboard/google/hatch/variants/palkia/overridetree.cb @@ -1,6 +1,8 @@ chip soc/intel/cannonlake - register "tdp_pl1_override" = "15" - register "tdp_pl2_override" = "64" + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 64, + }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/google/hatch/variants/puff/mainboard.c b/src/mainboard/google/hatch/variants/puff/mainboard.c index ef5df4ae4b..b5bc699ca0 100644 --- a/src/mainboard/google/hatch/variants/puff/mainboard.c +++ b/src/mainboard/google/hatch/variants/puff/mainboard.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #define GPIO_HDMI_HPD GPP_E13 @@ -86,7 +87,7 @@ static void wait_for_hpd(gpio_t gpio, long timeout) #define PSYS_IMAX 9600 #define BJ_VOLTS_MV 19000 -static void mainboard_set_power_limits(config_t *conf) +static void mainboard_set_power_limits(struct soc_power_limits_config *conf) { enum usb_chg_type type; u32 watts; @@ -123,6 +124,7 @@ static void mainboard_set_power_limits(config_t *conf) void variant_ramstage_init(void) { static const long display_timeout_ms = 3000; + struct soc_power_limits_config *soc_config; config_t *conf = config_of_soc(); /* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */ @@ -136,5 +138,6 @@ void variant_ramstage_init(void) wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); } /* Psys_pmax needs to be setup before FSP-S */ - mainboard_set_power_limits(conf); + soc_config = &conf->power_limits_config; + mainboard_set_power_limits(soc_config); } diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index d1d9b038b2..a84e73a826 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -31,12 +31,14 @@ chip soc/intel/cannonlake register "PchUsb2PhySusPgDisable" = "1" register "speed_shift_enable" = "1" - register "psys_pmax" = "140" register "s0ix_enable" = "1" register "dptf_enable" = "1" register "satapwroptimize" = "1" - register "tdp_pl1_override" = "25" - register "tdp_pl2_override" = "51" + register "power_limits_config" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 51, + .psys_pmax = 140, + }" register "Device4Enable" = "1" register "AcousticNoiseMitigation" = "1" register "SlowSlewRateForIa" = "2" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index b2aa8d5e8d..09b4240993 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -42,9 +42,11 @@ chip soc/intel/cannonlake register "SlowSlewRateForGt" = "2" register "SlowSlewRateForSa" = "2" register "SlowSlewRateForFivr" = "2" - register "tdp_pl1_override" = "15" - register "tdp_pl2_override" = "51" - register "psys_pmax" = "136" + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + .psys_pmax = 136, + }" register "Device4Enable" = "1" # Enable eDP device register "DdiPortEdp" = "1" diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 6cf0fff9de..4c6c866440 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -19,8 +19,10 @@ chip soc/intel/cannonlake # CPU (soc/intel/cannonlake/cpu.c) # Power limit - register "tdp_pl1_override" = "15" - register "tdp_pl2_override" = "25" + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 25, + }" # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 6a86576c2b..7a56d0d42d 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -103,6 +103,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET + select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index f6ec7ce7cb..a30f732ce3 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -32,6 +33,9 @@ struct soc_intel_cannonlake_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; + /* Common struct containing power limits configuration information */ + struct soc_power_limits_config power_limits_config; + /* Gpio group routed to each dword of the GPE0 block. Values are * of the form GPP_[A:G] or GPD. */ uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ @@ -231,23 +235,6 @@ struct soc_intel_cannonlake_config { /* Enables support for Teton Glacier hybrid storage device */ uint8_t TetonGlacierMode; - /* PL1 Override value in Watts */ - uint32_t tdp_pl1_override; - /* PL2 Override value in Watts */ - uint32_t tdp_pl2_override; - /* SysPL2 Value in Watts */ - uint32_t tdp_psyspl2; - /* SysPL3 Value in Watts */ - uint32_t tdp_psyspl3; - /* SysPL3 window size */ - uint32_t tdp_psyspl3_time; - /* SysPL3 duty cycle */ - uint32_t tdp_psyspl3_dutycycle; - /* PL4 Value in Watts */ - uint32_t tdp_pl4; - /* Estimated maximum platform power in Watts */ - uint16_t psys_pmax; - /* Intel Speed Shift Technology */ uint8_t speed_shift_enable; /* Enable VR specific mailbox command diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 2f1a08020c..5b329eef3c 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -22,196 +22,6 @@ #include "chip.h" -/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ -static const u8 power_limit_time_sec_to_msr[] = { - [0] = 0x00, - [1] = 0x0a, - [2] = 0x0b, - [3] = 0x4b, - [4] = 0x0c, - [5] = 0x2c, - [6] = 0x4c, - [7] = 0x6c, - [8] = 0x0d, - [10] = 0x2d, - [12] = 0x4d, - [14] = 0x6d, - [16] = 0x0e, - [20] = 0x2e, - [24] = 0x4e, - [28] = 0x6e, - [32] = 0x0f, - [40] = 0x2f, - [48] = 0x4f, - [56] = 0x6f, - [64] = 0x10, - [80] = 0x30, - [96] = 0x50, - [112] = 0x70, - [128] = 0x11, -}; - -/* Convert POWER_LIMIT_1_TIME MSR value to seconds */ -static const u8 power_limit_time_msr_to_sec[] = { - [0x00] = 0, - [0x0a] = 1, - [0x0b] = 2, - [0x4b] = 3, - [0x0c] = 4, - [0x2c] = 5, - [0x4c] = 6, - [0x6c] = 7, - [0x0d] = 8, - [0x2d] = 10, - [0x4d] = 12, - [0x6d] = 14, - [0x0e] = 16, - [0x2e] = 20, - [0x4e] = 24, - [0x6e] = 28, - [0x0f] = 32, - [0x2f] = 40, - [0x4f] = 48, - [0x6f] = 56, - [0x10] = 64, - [0x30] = 80, - [0x50] = 96, - [0x70] = 112, - [0x11] = 128, -}; - -/* - * Configure processor power limits if possible - * This must be done AFTER set of BIOS_RESET_CPL - */ -void set_power_limits(u8 power_limit_1_time) -{ - msr_t msr = rdmsr(MSR_PLATFORM_INFO); - msr_t limit; - unsigned int power_unit; - unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1; - u8 power_limit_1_val; - - config_t *conf = config_of_soc(); - - if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) - power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; - - if (!(msr.lo & PLATFORM_INFO_SET_TDP)) - return; - - /* Get units */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 1 << (msr.lo & 0xf); - - /* Get power defaults for this SKU */ - msr = rdmsr(MSR_PKG_POWER_SKU); - tdp = msr.lo & 0x7fff; - min_power = (msr.lo >> 16) & 0x7fff; - max_power = msr.hi & 0x7fff; - max_time = (msr.hi >> 16) & 0x7f; - - printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); - - if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) - power_limit_1_time = power_limit_time_msr_to_sec[max_time]; - - if (min_power > 0 && tdp < min_power) - tdp = min_power; - - if (max_power > 0 && tdp > max_power) - tdp = max_power; - - power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; - - /* Set long term power limit to TDP */ - limit.lo = 0; - tdp_pl1 = ((conf->tdp_pl1_override == 0) ? - tdp : (conf->tdp_pl1_override * power_unit)); - limit.lo |= (tdp_pl1 & PKG_POWER_LIMIT_MASK); - - /* Set PL1 Pkg Power clamp bit */ - limit.lo |= PKG_POWER_LIMIT_CLAMP; - - limit.lo |= PKG_POWER_LIMIT_EN; - limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << - PKG_POWER_LIMIT_TIME_SHIFT; - - /* Set short term power limit to 1.25 * TDP if no config given */ - limit.hi = 0; - tdp_pl2 = (conf->tdp_pl2_override == 0) ? - (tdp * 125) / 100 : (conf->tdp_pl2_override * power_unit); - printk(BIOS_DEBUG, "CPU PL2 = %u Watts\n", tdp_pl2 / power_unit); - limit.hi |= (tdp_pl2) & PKG_POWER_LIMIT_MASK; - limit.hi |= PKG_POWER_LIMIT_CLAMP; - limit.hi |= PKG_POWER_LIMIT_EN; - - /* Power limit 2 time is only programmable on server SKU */ - wrmsr(MSR_PKG_POWER_LIMIT, limit); - - /* Set PL2 power limit values in MCHBAR and disable PL1 */ - MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo & (~(PKG_POWER_LIMIT_EN)); - MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi; - - /* Set PsysPl2 */ - if (conf->tdp_psyspl2) { - limit = rdmsr(MSR_PLATFORM_POWER_LIMIT); - limit.hi = 0; - printk(BIOS_DEBUG, "CPU PsysPL2 = %u Watts\n", - conf->tdp_psyspl2); - limit.hi |= (conf->tdp_psyspl2 * power_unit) & - PKG_POWER_LIMIT_MASK; - limit.hi |= PKG_POWER_LIMIT_CLAMP; - limit.hi |= PKG_POWER_LIMIT_EN; - - wrmsr(MSR_PLATFORM_POWER_LIMIT, limit); - } - - /* Set PsysPl3 */ - if (conf->tdp_psyspl3) { - limit = rdmsr(MSR_PL3_CONTROL); - limit.lo = 0; - printk(BIOS_DEBUG, "CPU PsysPL3 = %u Watts\n", - conf->tdp_psyspl3); - limit.lo |= (conf->tdp_psyspl3 * power_unit) & - PKG_POWER_LIMIT_MASK; - /* Enable PsysPl3 */ - limit.lo |= PKG_POWER_LIMIT_EN; - /* set PsysPl3 time window */ - limit.lo |= (conf->tdp_psyspl3_time & - PKG_POWER_LIMIT_TIME_MASK) << - PKG_POWER_LIMIT_TIME_SHIFT; - /* set PsysPl3 duty cycle */ - limit.lo |= (conf->tdp_psyspl3_dutycycle & - PKG_POWER_LIMIT_DUTYCYCLE_MASK) << - PKG_POWER_LIMIT_DUTYCYCLE_SHIFT; - wrmsr(MSR_PL3_CONTROL, limit); - } - - /* Set Pl4 */ - if (conf->tdp_pl4) { - limit = rdmsr(MSR_VR_CURRENT_CONFIG); - limit.lo = 0; - printk(BIOS_DEBUG, "CPU PL4 = %u Watts\n", - conf->tdp_pl4); - limit.lo |= (conf->tdp_pl4 * power_unit) & - PKG_POWER_LIMIT_MASK; - wrmsr(MSR_VR_CURRENT_CONFIG, limit); - } - - /* Set DDR RAPL power limit by copying from MMIO to MSR */ - msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO); - msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI); - wrmsr(MSR_DDR_RAPL_LIMIT, msr); - - /* Use nominal TDP values for CPUs with configurable TDP */ - if (cpu_config_tdp_levels()) { - limit.hi = 0; - limit.lo = cpu_get_tdp_nominal_ratio(); - wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); - } -} - static void soc_fsp_load(void) { fsps_load(romstage_handoff_is_resume()); diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index b7e9ad8d8b..8788838c3f 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -152,11 +153,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) mainboard_silicon_init_params(params); + const struct soc_power_limits_config *soc_config; + soc_config = &config->power_limits_config; /* Set PsysPmax if it is available from DT */ - if (config->psys_pmax) { - printk(BIOS_DEBUG, "psys_pmax = %dW\n", config->psys_pmax); + if (soc_config->psys_pmax) { + printk(BIOS_DEBUG, "psys_pmax = %dW\n", soc_config->psys_pmax); /* PsysPmax is in unit of 1/8 Watt */ - tconfig->PsysPmax = config->psys_pmax * 8; + tconfig->PsysPmax = soc_config->psys_pmax * 8; } /* Unlock upper 8 bytes of RTC RAM */ diff --git a/src/soc/intel/cannonlake/include/soc/cpu.h b/src/soc/intel/cannonlake/include/soc/cpu.h index ea30755069..b356d3a9b8 100644 --- a/src/soc/intel/cannonlake/include/soc/cpu.h +++ b/src/soc/intel/cannonlake/include/soc/cpu.h @@ -31,7 +31,4 @@ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ (IRTL_1024_NS >> 10)) -/* Configure power limits for turbo mode */ -void set_power_limits(u8 power_limit_1_time); - #endif diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c index a041c0e154..c225651649 100644 --- a/src/soc/intel/cannonlake/systemagent.c +++ b/src/soc/intel/cannonlake/systemagent.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -57,6 +58,9 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) */ void soc_systemagent_init(struct device *dev) { + struct soc_power_limits_config *soc_config; + config_t *config; + /* Enable Power Aware Interrupt Routing */ enable_power_aware_intr(); @@ -65,5 +69,7 @@ void soc_systemagent_init(struct device *dev) /* Configure turbo power limits 1ms after reset complete bit */ mdelay(1); - set_power_limits(28); + config = config_of_soc(); + soc_config = &config->power_limits_config; + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); } From 1c3faabf2472c5eee9ceabc233896e7c28e0d863 Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Thu, 14 May 2020 10:23:55 +0800 Subject: [PATCH 273/405] libpayload/cbgfx: Remove gap between adjacent boxes When drawing two adjacent boxes with draw_box(), there will be a gap between them. This is due to the truncation in integer division when calculating the bottom right coordinate of the box. In this patch, the relative bottom right coordinate is calculated before transforming to an absolute one. The same issue is also fixed for draw_rounded_box(). Also check validity of 'pos_rel' and 'dim_rel' arguments for draw_rounded_box(). BRANCH=none BUG=chromium:1082593 TEST=emerge-nami libpayload Change-Id: I073cf8ec6eb3952a0dcb417b4c3c3c7047567837 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/41392 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- payloads/libpayload/drivers/video/graphics.c | 50 ++++++++++++++++---- 1 file changed, 40 insertions(+), 10 deletions(-) diff --git a/payloads/libpayload/drivers/video/graphics.c b/payloads/libpayload/drivers/video/graphics.c index ea10f131da..81d2bb9e55 100644 --- a/payloads/libpayload/drivers/video/graphics.c +++ b/payloads/libpayload/drivers/video/graphics.c @@ -72,6 +72,35 @@ static int is_valid_fraction(const struct fraction *f) return f->d != 0; } +static int is_valid_scale(const struct scale *s) +{ + return is_valid_fraction(&s->x) && is_valid_fraction(&s->y); +} + +static void add_fractions(struct fraction *out, + const struct fraction *f1, const struct fraction *f2) +{ + int64_t n, d; + int shift; + n = (int64_t)f1->n * f2->d + (int64_t)f2->n * f1->d; + d = (int64_t)f1->d * f2->d; + /* Simplest way to reduce the fraction until fitting in int32_t */ + shift = log2(MAX(ABS(n), ABS(d)) >> 31); + if (shift > 0) { + n >>= shift; + d >>= shift; + } + out->n = n; + out->d = d; +} + +static void add_scales(struct scale *out, + const struct scale *s1, const struct scale *s2) +{ + add_fractions(&out->x, &s1->x, &s2->x); + add_fractions(&out->y, &s1->y, &s2->y); +} + /* * Transform a vector: * x' = x * a_x + offset_x @@ -82,7 +111,7 @@ static int transform_vector(struct vector *out, const struct scale *a, const struct vector *offset) { - if (!is_valid_fraction(&a->x) || !is_valid_fraction(&a->y)) + if (!is_valid_scale(a)) return CBGFX_ERROR_INVALID_PARAMETER; out->x = a->x.n * in->x / a->x.d + offset->x; out->y = a->y.n * in->y / a->y.d + offset->y; @@ -211,7 +240,6 @@ static int cbgfx_init(void) int draw_box(const struct rect *box, const struct rgb_color *rgb) { struct vector top_left; - struct vector size; struct vector p, t; if (cbgfx_init()) @@ -222,14 +250,13 @@ int draw_box(const struct rect *box, const struct rgb_color *rgb) .x = { .n = box->offset.x, .d = CANVAS_SCALE, }, .y = { .n = box->offset.y, .d = CANVAS_SCALE, } }; - const struct scale size_s = { - .x = { .n = box->size.x, .d = CANVAS_SCALE, }, - .y = { .n = box->size.y, .d = CANVAS_SCALE, } + const struct scale bottom_right_s = { + .x = { .n = box->offset.x + box->size.x, .d = CANVAS_SCALE, }, + .y = { .n = box->offset.y + box->size.y, .d = CANVAS_SCALE, } }; transform_vector(&top_left, &canvas.size, &top_left_s, &canvas.offset); - transform_vector(&size, &canvas.size, &size_s, &vzero); - add_vectors(&t, &top_left, &size); + transform_vector(&t, &canvas.size, &bottom_right_s, &canvas.offset); if (within_box(&t, &canvas) < 0) { LOG("Box exceeds canvas boundary\n"); return CBGFX_ERROR_BOUNDARY; @@ -247,8 +274,8 @@ int draw_rounded_box(const struct scale *pos_rel, const struct scale *dim_rel, const struct fraction *thickness, const struct fraction *radius) { + struct scale pos_end_rel; struct vector top_left; - struct vector size; struct vector p, t; if (cbgfx_init()) @@ -256,9 +283,12 @@ int draw_rounded_box(const struct scale *pos_rel, const struct scale *dim_rel, const uint32_t color = calculate_color(rgb, 0); + if (!is_valid_scale(pos_rel) || !is_valid_scale(dim_rel)) + return CBGFX_ERROR_INVALID_PARAMETER; + + add_scales(&pos_end_rel, pos_rel, dim_rel); transform_vector(&top_left, &canvas.size, pos_rel, &canvas.offset); - transform_vector(&size, &canvas.size, dim_rel, &vzero); - add_vectors(&t, &top_left, &size); + transform_vector(&t, &canvas.size, &pos_end_rel, &canvas.offset); if (within_box(&t, &canvas) < 0) { LOG("Box exceeds canvas boundary\n"); return CBGFX_ERROR_BOUNDARY; From fcbbb911162aa4dea1fc7fcc8794b22f86579fe8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 20 Apr 2020 10:21:39 +0300 Subject: [PATCH 274/405] Remove MAYBE_STATIC_BSS and ENV_STAGE_HAS_BSS_SECTION MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After removal of CAR_MIGRATION there are no more reasons to carry around ENV_STAGE_HAS_BSS_SECTION=n case. Replace 'MAYBE_STATIC_BSS' with 'static' and remove explicit zero-initializers. Change-Id: I14dd9f52da5b06f0116bd97496cf794e5e71bc37 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/40535 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Duncan Laurie Reviewed-by: Julius Werner Reviewed-by: Furquan Shaikh --- src/arch/x86/car.ld | 2 -- src/device/device_const.c | 2 +- src/drivers/pc80/rtc/option.c | 2 +- src/ec/google/chromeec/ec.c | 2 +- src/ec/google/chromeec/ec_lpc.c | 2 +- src/include/rules.h | 3 --- src/include/stddef.h | 6 ------ src/lib/imd_cbmem.c | 2 +- src/lib/lzma.c | 2 +- src/lib/program.ld | 2 +- src/mainboard/google/stout/chromeos.c | 4 ++-- src/security/tpm/tspi/log.c | 4 ++-- src/soc/intel/baytrail/northcluster.c | 2 +- src/soc/intel/braswell/northcluster.c | 2 +- toolchain.inc | 2 +- 15 files changed, 14 insertions(+), 25 deletions(-) diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 0ea40d0083..ddd4e7a2bf 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -62,13 +62,11 @@ . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _bss = .; -#if ENV_STAGE_HAS_BSS_SECTION /* Allow global uninitialized variables for stages without CAR teardown. */ *(.bss) *(.bss.*) *(.sbss) *(.sbss.*) -#endif . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _ebss = .; _car_unallocated_start = .; diff --git a/src/device/device_const.c b/src/device/device_const.c index 3ad00f8838..12d5386d22 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -227,7 +227,7 @@ DEVTREE_CONST struct device *pcidev_path_on_bus(unsigned int bus, pci_devfn_t de DEVTREE_CONST struct bus *pci_root_bus(void) { DEVTREE_CONST struct device *pci_domain; - MAYBE_STATIC_BSS DEVTREE_CONST struct bus *pci_root = NULL; + static DEVTREE_CONST struct bus *pci_root; if (pci_root) return pci_root; diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c index 5815e7c239..0a73cb3232 100644 --- a/src/drivers/pc80/rtc/option.c +++ b/src/drivers/pc80/rtc/option.c @@ -52,7 +52,7 @@ static enum cb_err get_cmos_value(unsigned long bit, unsigned long length, static enum cb_err locate_cmos_layout(struct region_device *rdev) { uint32_t cbfs_type = CBFS_COMPONENT_CMOS_LAYOUT; - MAYBE_STATIC_BSS struct cbfsf fh = {}; + static struct cbfsf fh; /* * In case VBOOT is enabled and this function is called from SMM, diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index b96458152d..034e9313c9 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1343,7 +1343,7 @@ static void google_chromeec_log_uptimeinfo(void) /* Cache and retrieve the EC image type (ro or rw) */ enum ec_image google_chromeec_get_current_image(void) { - MAYBE_STATIC_BSS enum ec_image ec_image_type = EC_IMAGE_UNKNOWN; + static enum ec_image ec_image_type = EC_IMAGE_UNKNOWN; if (ec_image_type != EC_IMAGE_UNKNOWN) return ec_image_type; diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 52b5e6469b..5306dcca5b 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -387,7 +387,7 @@ void google_chromeec_ioport_range(uint16_t *out_base, size_t *out_size) int google_chromeec_command(struct chromeec_command *cec_command) { - MAYBE_STATIC_BSS int command_version = 0; + static int command_version; if (command_version <= 0) command_version = google_chromeec_command_version(); diff --git a/src/include/rules.h b/src/include/rules.h index 6af25a9577..614f37ad52 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -252,12 +252,9 @@ #define ENV_CACHE_AS_RAM (ENV_ROMSTAGE_OR_BEFORE && !CONFIG(RESET_VECTOR_IN_RAM)) /* No .data sections with execute-in-place from ROM. */ #define ENV_STAGE_HAS_DATA_SECTION !ENV_CACHE_AS_RAM -/* No .bss sections for stage with CAR teardown. */ -#define ENV_STAGE_HAS_BSS_SECTION 1 #else /* Both .data and .bss, sometimes SRAM not DRAM. */ #define ENV_STAGE_HAS_DATA_SECTION 1 -#define ENV_STAGE_HAS_BSS_SECTION 1 #define ENV_CACHE_AS_RAM 0 #endif diff --git a/src/include/stddef.h b/src/include/stddef.h index e3183096a0..b668b1aeb6 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -41,12 +41,6 @@ typedef unsigned int wint_t; #define MAYBE_STATIC_NONZERO #endif -#if ENV_STAGE_HAS_BSS_SECTION -#define MAYBE_STATIC_BSS static -#else -#define MAYBE_STATIC_BSS -#endif - /* Provide a pointer to address 0 that thwarts any "accessing this is * undefined behaviour and do whatever" trickery in compilers. * Use when you _really_ need to read32(zeroptr) (ie. read address 0). diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 2f065ff7d2..d06a9e9416 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -19,7 +19,7 @@ static struct imd imd; void *cbmem_top(void) { if (ENV_ROMSTAGE) { - MAYBE_STATIC_BSS void *top = NULL; + static void *top; if (top) return top; top = cbmem_top_chipset(); diff --git a/src/lib/lzma.c b/src/lib/lzma.c index 16b6e228fb..d2e3e4b45d 100644 --- a/src/lib/lzma.c +++ b/src/lib/lzma.c @@ -26,7 +26,7 @@ size_t ulzman(const void *src, size_t srcn, void *dst, size_t dstn) int res; CLzmaDecoderState state; SizeT mallocneeds; - MAYBE_STATIC_BSS unsigned char scratchpad[15980]; + static unsigned char scratchpad[15980]; const unsigned char *cp; if (srcn < data_offset) { diff --git a/src/lib/program.ld b/src/lib/program.ld index b56a400ceb..734f040fcd 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -112,7 +112,7 @@ } #endif -#if ENV_STAGE_HAS_BSS_SECTION && !ENV_CACHE_AS_RAM +#if !ENV_CACHE_AS_RAM .bss . : { . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _bss = .; diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index b67762e13b..dfab358abc 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -53,8 +53,8 @@ int get_lid_switch(void) */ int get_recovery_mode_switch(void) { - MAYBE_STATIC_BSS int ec_in_rec_mode = 0; - MAYBE_STATIC_BSS int ec_rec_flag_good = 0; + static int ec_in_rec_mode; + static int ec_rec_flag_good; if (ec_rec_flag_good) return ec_in_rec_mode; diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index 07623f75b1..1d6f9acf32 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -11,7 +11,7 @@ static struct tcpa_table *tcpa_cbmem_init(void) { - MAYBE_STATIC_BSS struct tcpa_table *tclt = NULL; + static struct tcpa_table *tclt; if (tclt) return tclt; @@ -32,7 +32,7 @@ static struct tcpa_table *tcpa_cbmem_init(void) struct tcpa_table *tcpa_log_init(void) { - MAYBE_STATIC_BSS struct tcpa_table *tclt = NULL; + static struct tcpa_table *tclt; /* We are dealing here with pre CBMEM environment. * If cbmem isn't available use CAR or SRAM */ diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index b4bad8a913..bb01844e2d 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -51,7 +51,7 @@ uint32_t nc_read_top_of_low_memory(void) { - MAYBE_STATIC_BSS uint32_t tolm = 0; + static uint32_t tolm; if (tolm) return tolm; diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 2070cd7419..94b91cc047 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -56,7 +56,7 @@ uint32_t nc_read_top_of_low_memory(void) { - MAYBE_STATIC_BSS uint32_t tolm = 0; + static uint32_t tolm; if (tolm) return tolm; diff --git a/toolchain.inc b/toolchain.inc index 31d3e21876..b680b1c77d 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -55,7 +55,7 @@ CFLAGS_ppc64 += # stack use, we use 1.5K as heuristic, assuming that we typically have lots # of tiny stack frames and the odd large one. # -# Store larger buffers in BSS, use MAYBE_STATIC_BSS to share data in cache-as-ram +# Store larger buffers in BSS, use static to share data in cache-as-ram # on x86. # Since GCCs detection of dynamic array bounds unfortunately seems to be # very basic, you'll sometimes have to use a static upper bound for the From 4751390b61fcf61ad319dfb59857fa3d5c12ccda Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 24 Apr 2020 17:52:01 +0200 Subject: [PATCH 275/405] soc/intel/skylake/acpi/smbus.asl: Fix typo in comment Change-Id: I2d0c90afe8acf8405da2cb6444e47dc98ad8cc9b Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40691 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- src/soc/intel/skylake/acpi/smbus.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/acpi/smbus.asl b/src/soc/intel/skylake/acpi/smbus.asl index 7f4d253daa..63976225a8 100644 --- a/src/soc/intel/skylake/acpi/smbus.asl +++ b/src/soc/intel/skylake/acpi/smbus.asl @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -// Intel SMBus Controller 0:1f.3 +// Intel SMBus Controller 0:1f.4 Device (SBUS) { From d9cd064ac66148293385671160e56bd1c2664015 Mon Sep 17 00:00:00 2001 From: William Wei Date: Wed, 20 May 2020 14:30:13 +0800 Subject: [PATCH 276/405] mb/google/volteer: Enable ELAN trackpad wake suspend function BUG=b:156990317 TEST=emerge-volteer coreboot chromeos-bootimage Boot to kernel and check the ELAN trackpad can wake up unit from suspend. Signed-off-by: William Wei Change-Id: If4bea8a9742f7533be2e51b855cc39ca77d73608 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41556 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 3 ++- src/mainboard/google/volteer/variants/baseboard/gpio.c | 2 +- src/mainboard/google/volteer/variants/malefor/gpio.c | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 25b42c74f7..693369542b 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -350,7 +350,8 @@ chip soc/intel/tigerlake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E15_IRQ)" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" register "probed" = "1" device i2c 15 on end end diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index 8cbda1c0cb..3290f44ad5 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -225,7 +225,7 @@ static const struct pad_config gpio_table[] = { /* E14 : DDPC_HPDA ==> SOC_EDP_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_E15, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), /* E16 : ISH_GP7 ==> WWAN_SIM1_DET_OD */ PAD_CFG_GPI(GPP_E16, NONE, DEEP), /* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */ diff --git a/src/mainboard/google/volteer/variants/malefor/gpio.c b/src/mainboard/google/volteer/variants/malefor/gpio.c index bd66acd57c..d3c36f851e 100644 --- a/src/mainboard/google/volteer/variants/malefor/gpio.c +++ b/src/mainboard/google/volteer/variants/malefor/gpio.c @@ -220,7 +220,7 @@ static const struct pad_config gpio_table[] = { /* E14 : DDPC_HPDA ==> SOC_EDP_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_E15, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), /* E16 : ISH_GP7 ==> NOT USED */ PAD_NC(GPP_E16, NONE), /* E17 : THC0_SPI1_INT# ==> NOT USED */ From 1408798637125f1707ded7215e22461c623a79a8 Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Wed, 20 May 2020 09:54:26 -0700 Subject: [PATCH 277/405] Mushu: Enable PCIe 1d.4 to enable dgpu BUG=b:147249494,b:147249494 BRANCH=None TEST=boot up mushu check cbmem -1 to make sure PCIe 1d.4 is enabled Change-Id: I36404217f0ecffb0cce1105e76f507c9062df053 Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/41564 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/variants/mushu/overridetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index db86d68204..100f7d5603 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -185,6 +185,7 @@ chip soc/intel/cannonlake device i2c 1a on end end end #I2C #4 + device pci 1d.4 on end # PCI Express port 13 device pci 1e.3 on chip drivers/spi/acpi register "name" = ""CRFP"" From 8aac881fe8caacd264fe6e0951750c6357bb3b5c Mon Sep 17 00:00:00 2001 From: John Zhao Date: Sat, 16 May 2020 13:06:25 -0700 Subject: [PATCH 278/405] soc/intel/tigerlake: Add FSP UPD D3HotEnable and D3ColdEnable This adds FSP UPD D3HotEnable and D3ColdEnable for configuration. D3Hot low power mode support is for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers. D3Cold is lower mode for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold transition. BUG=:b:146624360 TEST=Built and booted on Volteer. Signed-off-by: John Zhao Change-Id: I6782cde6a1bfe13f46e75db8c85537c6d62f5d41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41474 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Wonkyu Kim --- src/soc/intel/tigerlake/chip.h | 9 +++++++-- src/soc/intel/tigerlake/fsp_params.c | 4 ++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 2e3591f4a6..46c2d417a5 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -44,6 +44,11 @@ struct soc_intel_tigerlake_config { /* Enable S0iX support */ int s0ix_enable; + /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */ + uint8_t TcssD3HotEnable; + /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */ + uint8_t TcssD3ColdEnable; + /* Enable DPTF support */ int dptf_enable; @@ -216,11 +221,11 @@ struct soc_intel_tigerlake_config { FORCE_ENABLE, } CnviBtAudioOffload; - /* Tcss USB */ + /* TCSS USB */ uint8_t TcssXhciEn; uint8_t TcssXdciEn; - /* Tcss DMA */ + /* TCSS DMA */ uint8_t TcssDma0En; uint8_t TcssDma1En; diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 0c67105300..850cdbd169 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -101,6 +101,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; } + /* D3Hot and D3Cold for TCSS */ + params->D3HotEnable = config->TcssD3HotEnable; + params->D3ColdEnable = config->TcssD3ColdEnable; + params->TcssAuxOri = config->TcssAuxOri; for (i = 0; i < 8; i++) params->IomTypeCPortPadCfg[i] = config->IomTypeCPortPadCfg[i]; From 3c8cb24fc32d0322da5cfd7fabae3b66ac16470b Mon Sep 17 00:00:00 2001 From: John Zhao Date: Tue, 19 May 2020 20:21:00 -0700 Subject: [PATCH 279/405] mb/intel/tglrvp: Enable D3HotEnable and D3ColdEnable for tglrvp This explicitly enables both of TCSS D3HotEnable and D3ColdEnable from tglrvp devicetree.cb setting. BUG=:b:146624360 TEST=Built and booted on tglrvp. Signed-off-by: John Zhao Change-Id: I3b77fe15bd67e513f193f704030a98241e058437 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41554 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Wonkyu Kim --- src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 4 ++++ src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 045dc89e4d..24cc907da7 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -109,6 +109,10 @@ chip soc/intel/tigerlake [PchSerialIoIndexUART2] = PchSerialIoPci, }" + # D3Hot and D3Cold for TCSS + register "TcssD3HotEnable" = "1" + register "TcssD3ColdEnable" = "1" + # TCSS USB3 register "TcssAuxOri" = "0" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 83b6c0ae0c..eb6814e5bf 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -105,6 +105,10 @@ chip soc/intel/tigerlake [PchSerialIoIndexUART2] = PchSerialIoPci, }" + # D3Hot and D3Cold for TCSS + register "TcssD3HotEnable" = "1" + register "TcssD3ColdEnable" = "1" + # TCSS USB3 register "TcssAuxOri" = "0" From f5b33c00166f0e4511de07f0f6ecd639237c5cc2 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Tue, 19 May 2020 15:29:07 -0700 Subject: [PATCH 280/405] mb/google/volteer: Enable D3HotEnable and D3ColdEnable for Volteer This explicitly enables both of TCSS D3HotEnable and D3ColdEnable from Volteer devicetree.cb setting. BUG=:b:146624360 TEST=Built and booted on Volteer. Signed-off-by: John Zhao Change-Id: I1a168ad87169c0f6633704c55c9293aa25710188 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41547 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Wonkyu Kim --- src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 693369542b..02060bdf45 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -136,6 +136,10 @@ chip soc/intel/tigerlake register "IomTypeCPortPadCfg[7]" = "0x0" + # D3Hot and D3Cold for TCSS + register "TcssD3HotEnable" = "1" + register "TcssD3ColdEnable" = "1" + # DP port register "DdiPortAConfig" = "1" # eDP register "DdiPortBConfig" = "0" From a54bfd5e950ef108e9941a8319d0c24d786528ec Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 19 May 2020 11:38:53 -0700 Subject: [PATCH 281/405] Update vboot submodule to upstream master (commit hash c531000) This change updates vboot submodule from commit hash 3aab301: vboot: Convert reboot-related errors to vboot2-style to commit hash c531000: vboot: Add recovery reason code for CSE Lite SKU errors Signed-off-by: Furquan Shaikh Change-Id: Ifbf5a09e6602c3f6833e6e8fbbd3cee3f60f1b47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41536 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Sridhar Siricilla Reviewed-by: Angel Pons --- 3rdparty/vboot | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/vboot b/3rdparty/vboot index 3aab301473..c531000f85 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 3aab301473ec0b95f109a245efeadc20c3b7d57d +Subproject commit c531000f851418520b6873f65c202d21f141eb84 From 2adb50d32e8cd9c61773b1d60de545255c6a4049 Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Sat, 9 May 2020 15:37:09 +0530 Subject: [PATCH 282/405] apollolake: update processor power limits configuration Update processor power limit configuration parameters based on common code base support for Intel Apollo Lake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on octopus system Change-Id: I609744d165a53c8f91e42a67da1b972de00076a5 Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/41233 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- .../octopus/variants/baseboard/devicetree.cb | 8 +- .../reef/variants/baseboard/devicetree.cb | 8 +- .../google/reef/variants/coral/devicetree.cb | 8 +- .../google/reef/variants/pyro/devicetree.cb | 8 +- .../google/reef/variants/sand/devicetree.cb | 8 +- .../google/reef/variants/snappy/devicetree.cb | 8 +- .../glkrvp/variants/baseboard/devicetree.cb | 6 +- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/apollolake/chip.c | 78 +++---------------- src/soc/intel/apollolake/chip.h | 9 +-- src/soc/intel/apollolake/include/soc/msr.h | 9 +++ 11 files changed, 57 insertions(+), 94 deletions(-) create mode 100644 src/soc/intel/apollolake/include/soc/msr.h diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 9253f11372..80e4873694 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -42,12 +42,14 @@ chip soc/intel/apollolake register "gpe0_dw2" = "PMC_GPE_N_95_64" register "gpe0_dw3" = "PMC_GPE_N_63_32" - # PL1 override 10000 mW: Due to error in the energy calculation for + # PL1 override 10 W: Due to error in the energy calculation for # current VR solution. Experiments show that SoC TDP max (6W) can # be reached when RAPL PL1 is set to 10W. - register "tdp_pl1_override_mw" = "10000" # Set RAPL PL2 to 15W. - register "tdp_pl2_override_mw" = "15000" + register "power_limits_config" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 15, + }" # Minimum SLP S3 assertion width 28ms. register "slp_s3_assertion_width_usecs" = "28000" diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index cbc2e22d37..4c35bd25da 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -52,12 +52,14 @@ chip soc/intel/apollolake # Enable DPTF register "dptf_enable" = "1" - # PL1 override 12000 mW: the energy calculation is wrong with the + # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can # be reached when RAPL PL1 is set to 12W. - register "tdp_pl1_override_mw" = "12000" # Set RAPL PL2 to 15W. - register "tdp_pl2_override_mw" = "15000" + register "power_limits_config" = "{ + .tdp_pl1_override = 12, + .tdp_pl2_override = 15, + }" # Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1" diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index 00e63bc94c..f987e1da02 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -52,12 +52,14 @@ chip soc/intel/apollolake # Enable DPTF register "dptf_enable" = "1" - # PL1 override 12000 mW: the energy calculation is wrong with the + # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can # be reached when RAPL PL1 is set to 12W. - register "tdp_pl1_override_mw" = "12000" # Set RAPL PL2 to 15W. - register "tdp_pl2_override_mw" = "15000" + register "power_limits_config" = "{ + .tdp_pl1_override = 12, + .tdp_pl2_override = 15, + }" # Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1" diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index f62af8a39a..1282edb9ba 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -52,12 +52,14 @@ chip soc/intel/apollolake # Enable DPTF register "dptf_enable" = "1" - # PL1 override 12000 mW: the energy calculation is wrong with the + # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can # be reached when RAPL PL1 is set to 12W. - register "tdp_pl1_override_mw" = "12000" # Set RAPL PL2 to 15W. - register "tdp_pl2_override_mw" = "15000" + register "power_limits_config" = "{ + .tdp_pl1_override = 12, + .tdp_pl2_override = 15, + }" # Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1" diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index b62704a8f5..ad76a9194d 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -49,12 +49,14 @@ chip soc/intel/apollolake # Enable DPTF register "dptf_enable" = "1" - # PL1 override 12000 mW: the energy calculation is wrong with the + # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can # be reached when RAPL PL1 is set to 12W. - register "tdp_pl1_override_mw" = "12000" # Set RAPL PL2 to 15W. - register "tdp_pl2_override_mw" = "15000" + register "power_limits_config" = "{ + .tdp_pl1_override = 12, + .tdp_pl2_override = 15, + }" # Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1" diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index 7189508d18..a82400ff60 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -52,12 +52,14 @@ chip soc/intel/apollolake # Enable DPTF register "dptf_enable" = "1" - # PL1 override 12000 mW: the energy calculation is wrong with the + # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can # be reached when RAPL PL1 is set to 12W. - register "tdp_pl1_override_mw" = "12000" # Set RAPL PL2 to 15W. - register "tdp_pl2_override_mw" = "15000" + register "power_limits_config" = "{ + .tdp_pl1_override = 12, + .tdp_pl2_override = 15, + }" # Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1" diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index 361a4a30b8..75d69d309a 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -56,9 +56,11 @@ chip soc/intel/apollolake register "dptf_enable" = "1" # PL1 override: 7.5W setting gives a run-time 6W actual - register "tdp_pl1_override_mw" = "7500" # Set RAPL PL2 to 15W. - register "tdp_pl2_override_mw" = "15000" + register "power_limits_config" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 15, + }" # Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1" diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 9118b18af8..9323aed8ff 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -61,6 +61,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 058222ce39..cc190bae24 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -34,6 +35,7 @@ #include #include #include +#include #include "chip.h" @@ -269,73 +271,6 @@ static void pcie_override_devicetree_after_silicon_init(void) pcie_update_device_tree(PCH_DEVFN_PCIE5, 2); } -/* Configure package power limits */ -static void set_power_limits(void) -{ - struct soc_intel_apollolake_config *cfg; - msr_t rapl_msr_reg, limit; - uint32_t power_unit; - uint32_t tdp, min_power, max_power; - uint32_t pl2_val; - - cfg = config_of_soc(); - - if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { - printk(BIOS_INFO, "Skip the RAPL settings.\n"); - return; - } - - /* Get units */ - rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 1 << (rapl_msr_reg.lo & 0xf); - - /* Get power defaults for this SKU */ - rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU); - tdp = rapl_msr_reg.lo & PKG_POWER_LIMIT_MASK; - pl2_val = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; - min_power = (rapl_msr_reg.lo >> 16) & PKG_POWER_LIMIT_MASK; - max_power = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; - - if (min_power > 0 && tdp < min_power) - tdp = min_power; - - if (max_power > 0 && tdp > max_power) - tdp = max_power; - - /* Set PL1 override value */ - tdp = (cfg->tdp_pl1_override_mw == 0) ? - tdp : (cfg->tdp_pl1_override_mw * power_unit) / 1000; - /* Set PL2 override value */ - pl2_val = (cfg->tdp_pl2_override_mw == 0) ? - pl2_val : (cfg->tdp_pl2_override_mw * power_unit) / 1000; - - /* Set long term power limit to TDP */ - limit.lo = tdp & PKG_POWER_LIMIT_MASK; - /* Set PL1 Pkg Power clamp bit */ - limit.lo |= PKG_POWER_LIMIT_CLAMP; - - limit.lo |= PKG_POWER_LIMIT_EN; - limit.lo |= (MB_POWER_LIMIT1_TIME_DEFAULT & - PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT; - - /* Set short term power limit PL2 */ - limit.hi = pl2_val & PKG_POWER_LIMIT_MASK; - limit.hi |= PKG_POWER_LIMIT_EN; - - /* Program package power limits in RAPL MSR */ - wrmsr(MSR_PKG_POWER_LIMIT, limit); - printk(BIOS_INFO, "RAPL PL1 %d.%dW\n", tdp / power_unit, - 100 * (tdp % power_unit) / power_unit); - printk(BIOS_INFO, "RAPL PL2 %d.%dW\n", pl2_val / power_unit, - 100 * (pl2_val % power_unit) / power_unit); - - /* Setting RAPL MMIO register for Power limits. - * RAPL driver is using MSR instead of MMIO. - * So, disabled LIMIT_EN bit for MMIO. */ - MCHBAR32(MCHBAR_RAPL_PPL) = limit.lo & ~PKG_POWER_LIMIT_EN; - MCHBAR32(MCHBAR_RAPL_PPL + 4) = limit.hi & ~PKG_POWER_LIMIT_EN; -} - /* Overwrites the SCI IRQ if another IRQ number is given by device tree. */ static void set_sci_irq(void) { @@ -355,6 +290,9 @@ static void set_sci_irq(void) static void soc_init(void *data) { + struct soc_power_limits_config *soc_config; + config_t *config; + /* Snapshot the current GPIO IRQ polarities. FSP is setting a * default policy that doesn't honor boards' requirements. */ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); @@ -384,8 +322,10 @@ static void soc_init(void *data) /* Allocate ACPI NVS in CBMEM */ cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs_t)); - /* Set RAPL MSR for Package power limits*/ - set_power_limits(); + config = config_of_soc(); + /* Set RAPL MSR for Package power limits */ + soc_config = &config->power_limits_config; + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); /* * FSP-S routes SCI to IRQ 9. With the help of this function you can diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 8c0a6d2d1a..ce446a063a 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -28,6 +29,9 @@ struct soc_intel_apollolake_config { /* Common structure containing soc config data required by common code*/ struct soc_intel_common_config common_soc_config; + /* Common struct containing power limits configuration info */ + struct soc_power_limits_config power_limits_config; + /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has * four CLKREQ inputs, but six root ports. Root ports without an @@ -99,11 +103,6 @@ struct soc_intel_apollolake_config { /* TCC activation offset value in degrees Celsius */ int tcc_offset; - /* PL1 override value in mW for APL */ - uint16_t tdp_pl1_override_mw; - /* PL2 override value in mW for APL */ - uint16_t tdp_pl2_override_mw; - /* Configure Audio clk gate and power gate * IOSF-SB port ID 92 offset 0x530 [5] and [3] */ diff --git a/src/soc/intel/apollolake/include/soc/msr.h b/src/soc/intel/apollolake/include/soc/msr.h new file mode 100644 index 0000000000..cee11c29a8 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/msr.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef _SOC_MSR_H_ +#define _SOC_MSR_H_ + +#include + +#endif From f381d97856854a4b43c0acdae9aaff991837ce64 Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Wed, 20 May 2020 10:13:12 -0700 Subject: [PATCH 283/405] drivers/intel/fsp2_0: print soc specific GUID extension hobs Some SoC specific hobs are of HOB_TYPE_GUID_EXTENSION. Call SoC specific soc_display_hob() to display the content as necessary. Signed-off-by: Jonathan Zhang Change-Id: Ib4e4abe2d89b04504d1988d8d3c2fde268b5345a Reviewed-on: https://review.coreboot.org/c/coreboot/+/41565 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/drivers/intel/fsp2_0/hob_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/drivers/intel/fsp2_0/hob_display.c b/src/drivers/intel/fsp2_0/hob_display.c index 5c5e48d958..f21ebfeb5f 100644 --- a/src/drivers/intel/fsp2_0/hob_display.c +++ b/src/drivers/intel/fsp2_0/hob_display.c @@ -161,6 +161,9 @@ void fsp_print_guid_extension_hob(const struct hob_header *hob) printk(BIOS_SPEW, "\t"); fsp_print_guid(res->owner_guid); printk(BIOS_SPEW, ": %s\n", fsp_get_guid_name(res->owner_guid)); + + /* Some of the SoC FSP specific hobs are of type HOB_TYPE_GUID_EXTENSION */ + soc_display_hob(hob); } __weak const char *soc_get_guid_name(const uint8_t *guid) From 165efa1b863ad8c35646beda6ddd76075c5674a2 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Tue, 5 May 2020 09:10:13 -0700 Subject: [PATCH 284/405] soc/intel/tigerlake: Disable VMD It's already disabled by FSP default but disable VMD by devicetree to remove dependency with FSP default setting. BUG=None Branch=None Test=Build TGLRVP and boot up and check FSP log for checking VMD is disabled. Signed-off-by: Wonkyu Kim Change-Id: Ief81fe481b94abed9754881cf1f454999fafa52e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41061 Reviewed-by: Caveh Jalali Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- .../intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 2 +- .../intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 2 +- src/soc/intel/tigerlake/fsp_params.c | 7 +++++++ src/soc/intel/tigerlake/include/soc/pci_devs.h | 4 ++++ 4 files changed, 13 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 24cc907da7..7669b183fc 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -164,7 +164,7 @@ chip soc/intel/tigerlake device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 device pci 0d.2 off end # TBT DMA0 0x9A1B device pci 0d.3 off end # TBT DMA1 0x9A1D - device pci 0e.0 on end # VMD 0x9A0B + device pci 0e.0 off end # VMD 0x9A0B # From PCH EDS(576591) device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index eb6814e5bf..1d1d6dc633 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -160,7 +160,7 @@ chip soc/intel/tigerlake device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 device pci 0d.2 off end # TBT DMA0 0x9A1B device pci 0d.3 off end # TBT DMA1 0x9A1D - device pci 0e.0 on end # VMD 0x9A0B + device pci 0e.0 off end # VMD 0x9A0B # From PCH EDS(576591) device pci 10.2 off end # CNVi: BT 0xA0F5 - A0F7 diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 850cdbd169..611a61035d 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -214,6 +214,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) else params->CnviMode = 0; + /* VMD */ + dev = pcidev_path_on_root(SA_DEVFN_VMD); + if (dev) + params->VmdEnable = dev->enabled; + else + params->VmdEnable = 0; + /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index d76c4a105b..ee3e894a92 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -54,6 +54,10 @@ #define SA_DEV_TCSS_DMA0 PCI_DEV(0, SA_DEV_SLOT_TCSS, 2) #define SA_DEV_TCSS_DMA1 PCI_DEV(0, SA_DEV_SLOT_TCSS, 3) +#define SA_DEV_SLOT_VMD 0x0e +#define SA_DEVFN_VMD PCI_DEVFN(SA_DEV_SLOT_VMD, 0) +#define SA_DEV_VMD PCI_DEV(0, SA_DEV_SLOT_VMD, 0) + /* PCH Devices */ #define PCH_DEV_SLOT_SIO0 0x10 #define PCH_DEVFN_CNVI_BT _PCH_DEVFN(SIO0, 2) From b4d7116a740b2847ef112cc1954462dac0b4cf85 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Wed, 20 May 2020 13:25:04 -0700 Subject: [PATCH 285/405] soc/intel/tigerlake: Delete unused configuration Delete below configuration - Heci3Enabled: deprecated, see https://review.coreboot.org/cgit/coreboot.git/tree/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h#n442 - PchIshEnable: don't need as it's handled by devicetree dev on/off, see https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/tigerlake/romstage/fsp_params.c#n87 BUG:b:151166877 BRANCH=none TEST=Build and boot to OS Signed-off-by: Wonkyu Kim Change-Id: If96cc7db7118dd6c2ac02aab3bb0c96763ffc722 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41572 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/tigerlake/chip.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 46c2d417a5..86e703b055 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -136,12 +136,6 @@ struct soc_intel_tigerlake_config { /* SMBus */ uint8_t SmbusEnable; - /* Integrated Sensor */ - uint8_t PchIshEnable; - - /* Heci related */ - uint8_t Heci3Enabled; - /* Gfx related */ uint8_t IgdDvmt50PreAlloc; uint8_t InternalGfx; From b30fe36734df3c48ec35438052ee8b28bf7a6a44 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Wed, 20 May 2020 11:55:36 -0700 Subject: [PATCH 286/405] soc/intel/tigerlake: Remove MIPI clock setting from devicetree In Tiger Lake we have support for enabling MIPI clocks at runtime in ACPI. Hence remove setting pch_islclk from devcietree and chip.h. Also update functions which reference pch_isclk. BUG=b:148884060 Branch=None Test=build and boot volteer and verify camera functionality Signed-off-by: Srinidhi N Kaushik Change-Id: I6b3399172c43b4afa4267873ddd8ccf8d417ca16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41570 Reviewed-by: Furquan Shaikh Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- .../volteer/variants/baseboard/devicetree.cb | 3 --- src/soc/intel/tigerlake/chip.h | 3 --- src/soc/intel/tigerlake/finalize.c | 20 ------------------- 3 files changed, 26 deletions(-) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 02060bdf45..c6a2e8b1a6 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -32,9 +32,6 @@ chip soc/intel/tigerlake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 Camera - # Enable Pch iSCLK - register "pch_isclk" = "1" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201" diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 86e703b055..5892829ef4 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -206,9 +206,6 @@ struct soc_intel_tigerlake_config { DEBUG_INTERFACE_TRACEHUB = (1 << 5), } debug_interface_flag; - /* Enable Pch iSCLK */ - uint8_t pch_isclk; - /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ enum { FORCE_DISABLE, diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index 7de64a3a50..a402625799 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -27,24 +27,6 @@ #include #include -#define CAMERA1_CLK 0x8000 /* Camera 1 Clock */ -#define CAMERA2_CLK 0x8080 /* Camera 2 Clock */ -#define CAM_CLK_EN (1 << 1) -#define MIPI_CLK (1 << 0) -#define HDPLL_CLK (0 << 0) - -static void pch_enable_isclk(void) -{ - pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK); - pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK); -} - -static void pch_handle_sideband(config_t *config) -{ - if (config->pch_isclk) - pch_enable_isclk(); -} - static void pch_finalize(void) { uint32_t reg32; @@ -83,8 +65,6 @@ static void pch_finalize(void) write32(pmcbase + CPPMVRIC, reg32); } - pch_handle_sideband(config); - pmc_clear_pmcon_sts(); } From 5ac723e5a4a22bc9a08098cd59de5026b18d362d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 29 Apr 2020 09:09:12 +0200 Subject: [PATCH 287/405] nb/intel: Fix 16-bit read/write PCI_COMMAND register Change-Id: I7c7fb10308a6fcd1ead292c53ed03ddc693f6f15 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40835 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/gm45/iommu.c | 7 +++---- src/northbridge/intel/gm45/northbridge.c | 6 +----- src/northbridge/intel/pineview/northbridge.c | 6 +----- src/northbridge/intel/x4x/northbridge.c | 6 +----- 4 files changed, 6 insertions(+), 19 deletions(-) diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 0d106b8e27..10e0d02066 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -36,17 +36,16 @@ void init_iommu() const pci_devfn_t igd = PCI_DEV(0, 2, 0); /* setup somewhere */ - u8 cmd = pci_read_config8(igd, PCI_COMMAND); - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config8(igd, PCI_COMMAND, cmd); + pci_or_config16(igd, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); void *bar = (void *)pci_read_config32(igd, PCI_BASE_ADDRESS_0); /* clear GTT, 2MB is enough (and should be safe) */ memset(bar, 0, 2<<20); /* and now disable again */ + u16 cmd = pci_read_config8(igd, PCI_COMMAND); cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config8(igd, PCI_COMMAND, cmd); + pci_write_config16(igd, PCI_COMMAND, cmd); pci_write_config32(igd, PCI_BASE_ADDRESS_0, 0); } diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index cd64dfe3dd..b3dbe16b75 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -178,14 +178,10 @@ static void mch_domain_set_resources(struct device *dev) static void mch_domain_init(struct device *dev) { - u32 reg32; - struct device *mch = pcidev_on_root(0, 0); /* Enable SERR */ - reg32 = pci_read_config32(mch, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(mch, PCI_COMMAND, reg32); + pci_or_config16(mch, PCI_COMMAND, PCI_COMMAND_SERR); } static const char *northbridge_acpi_name(const struct device *dev) diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 83bc60eece..856eab3301 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -147,12 +147,8 @@ static void mch_domain_set_resources(struct device *dev) static void mch_domain_init(struct device *dev) { - u32 reg32; - /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } static const char *northbridge_acpi_name(const struct device *dev) diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 45b6ce3248..9c32dae275 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -131,12 +131,8 @@ static void mch_domain_set_resources(struct device *dev) static void mch_domain_init(struct device *dev) { - u32 reg32; - /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } static const char *northbridge_acpi_name(const struct device *dev) From 2f2191a3d0876fb90ab0c5f09e1c802b0a89b83e Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 28 Apr 2020 19:59:30 +0200 Subject: [PATCH 288/405] sb/intel/i82801dx: Fix 16-bit read/write PCI_COMMAND register Change-Id: Ie27054ded47b91a27036b5b4a21ab69b387239dc Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40810 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/i82801dx/smihandler.c | 8 ++++---- src/southbridge/intel/i82801dx/usb.c | 5 +---- src/southbridge/intel/i82801dx/usb2.c | 5 +---- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 4c5adeb79d..9f9f2f36dc 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -226,7 +226,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u32 reg32; + u16 reg16; pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); @@ -236,9 +236,9 @@ static void busmaster_disable_on_bus(int bus) continue; /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16); /* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); diff --git a/src/southbridge/intel/i82801dx/usb.c b/src/southbridge/intel/i82801dx/usb.c index 696b55977a..2abfa8a34f 100644 --- a/src/southbridge/intel/i82801dx/usb.c +++ b/src/southbridge/intel/i82801dx/usb.c @@ -9,11 +9,8 @@ static void usb_init(struct device *dev) { - u32 cmd; printk(BIOS_DEBUG, "USB: Setting up controller.. "); - cmd = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, - cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); printk(BIOS_DEBUG, "done.\n"); } diff --git a/src/southbridge/intel/i82801dx/usb2.c b/src/southbridge/intel/i82801dx/usb2.c index de30216ed1..e333bb613f 100644 --- a/src/southbridge/intel/i82801dx/usb2.c +++ b/src/southbridge/intel/i82801dx/usb2.c @@ -10,11 +10,8 @@ static void usb2_init(struct device *dev) { - u32 cmd; printk(BIOS_DEBUG, "USB: Setting up controller.. "); - cmd = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, - cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); printk(BIOS_DEBUG, "done.\n"); } From ae22fe293fc97a9f6b0fbf52230277b2a4332cda Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 21 May 2020 09:04:16 +0200 Subject: [PATCH 289/405] sb/intel/i82801gx: Use macro instead of numbers Change-Id: Ide6516937ea79c35cd54127ed2823352a1cac6d4 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41611 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82801gx/ac97.c | 3 ++- src/southbridge/intel/i82801gx/early_smbus.c | 2 +- src/southbridge/intel/i82801gx/ide.c | 16 ++++++++-------- src/southbridge/intel/i82801gx/pcie.c | 2 +- 4 files changed, 12 insertions(+), 11 deletions(-) diff --git a/src/southbridge/intel/i82801gx/ac97.c b/src/southbridge/intel/i82801gx/ac97.c index 175b5cd657..67426c7323 100644 --- a/src/southbridge/intel/i82801gx/ac97.c +++ b/src/southbridge/intel/i82801gx/ac97.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -96,7 +97,7 @@ static void init_cnr(void) static void program_sigid(struct device *dev, u32 id) { - pci_write_config32(dev, 0x2c, id); + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, id); } static void ac97_audio_init(struct device *dev) diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 7cd4a671d5..4d4ecb18c5 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -16,7 +16,7 @@ int smbus_enable_iobar(uintptr_t base) const pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x2) != 0x27da) + if (pci_read_config16(dev, PCI_DEVICE_ID) != 0x27da) return -1; /* Set SMBus I/O base. */ diff --git a/src/southbridge/intel/i82801gx/ide.c b/src/southbridge/intel/i82801gx/ide.c index f1ccd0f295..5c4c96d8c8 100644 --- a/src/southbridge/intel/i82801gx/ide.c +++ b/src/southbridge/intel/i82801gx/ide.c @@ -40,10 +40,10 @@ static void ide_init(struct device *dev) if (enable_primary) { /* Enable primary IDE interface. */ ideTimingConfig |= IDE_DECODE_ENABLE; - ideTimingConfig |= (2 << 12); // ISP = 3 clocks - ideTimingConfig |= (3 << 8); // RCT = 1 clock - ideTimingConfig |= (1 << 1); // IE0 - ideTimingConfig |= (1 << 0); // TIME0 + ideTimingConfig |= IDE_ISP_3_CLOCKS; + ideTimingConfig |= IDE_RCT_1_CLOCKS; + ideTimingConfig |= IDE_IE0; + ideTimingConfig |= IDE_TIME0; // TIME0 printk(BIOS_DEBUG, " IDE0"); } pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig); @@ -54,10 +54,10 @@ static void ide_init(struct device *dev) if (enable_secondary) { /* Enable secondary IDE interface. */ ideTimingConfig |= IDE_DECODE_ENABLE; - ideTimingConfig |= (2 << 12); // ISP = 3 clocks - ideTimingConfig |= (3 << 8); // RCT = 1 clock - ideTimingConfig |= (1 << 1); // IE0 - ideTimingConfig |= (1 << 0); // TIME0 + ideTimingConfig |= IDE_ISP_3_CLOCKS; + ideTimingConfig |= IDE_RCT_1_CLOCKS; + ideTimingConfig |= IDE_IE0; + ideTimingConfig |= IDE_TIME0; printk(BIOS_DEBUG, " IDE1"); } pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig); diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 56cf1f287d..7a49e52859 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -50,7 +50,7 @@ static void pci_init(struct device *dev) /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it - pci_write_config8(dev, 0x0c, 0x10); + pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 0x10); reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); reg16 &= ~PCI_BRIDGE_CTL_PARITY; From 1075b2944437320648d1d3cb9517a0c99bc55d16 Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Wed, 20 May 2020 13:44:28 -0700 Subject: [PATCH 290/405] soc/intel/xeon_sp: select UDK_2017_binding Select UDK_2017_BINDING instead of UDK_2015_BIDING. Otherwise there is build error when turning on FSP debugging. Remove duplicate configs from SKX-SP and CPX-SP directories, to keep the configs at SoC family level. Signed-off-by: Jonathan Zhang Change-Id: I6b25bf25dcb57937e2d9fec54eeb7951b0ee4b2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/41573 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/soc/intel/xeon_sp/Kconfig | 2 +- src/soc/intel/xeon_sp/cpx/Kconfig | 8 -------- src/soc/intel/xeon_sp/skx/Kconfig | 8 -------- 3 files changed, 1 insertion(+), 17 deletions(-) diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index e07de9b9db..8e39b77d3a 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -68,7 +68,7 @@ config USE_FSP2_0_DRIVER def_bool y depends on MAINBOARD_USES_FSP2_0 select PLATFORM_USES_FSP2_0 - select UDK_2015_BINDING + select UDK_2017_BINDING select POSTCAR_CONSOLE select POSTCAR_STAGE diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 86fdf1bfa3..59ccc6f98e 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -6,14 +6,6 @@ config MAINBOARD_USES_FSP2_0 bool default y -config USE_FSP2_0_DRIVER - def_bool y - depends on MAINBOARD_USES_FSP2_0 - select PLATFORM_USES_FSP2_0 - select UDK_2015_BINDING - select POSTCAR_CONSOLE - select POSTCAR_STAGE - config FSP_HEADER_PATH string "Location of FSP headers" depends on MAINBOARD_USES_FSP2_0 diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index 7af0b582cb..0e3e699de6 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -6,14 +6,6 @@ config MAINBOARD_USES_FSP2_0 bool default y -config USE_FSP2_0_DRIVER - def_bool y - depends on MAINBOARD_USES_FSP2_0 - select PLATFORM_USES_FSP2_0 - select UDK_2015_BINDING - select POSTCAR_CONSOLE - select POSTCAR_STAGE - config FSP_HEADER_PATH string "Location of FSP headers" depends on MAINBOARD_USES_FSP2_0 From 730b2616aa3c24d6ee9da5cf00ba7f0248776cbd Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Wed, 20 May 2020 00:32:50 +0200 Subject: [PATCH 291/405] device/pci: Refactor pci_set_resource() This function is too long and quirky. Factor the actual resource write out, so we can focus on the logic. Change-Id: I6c7f930614dcd63d4ee2a4ca7cf541a9de4fd557 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/41551 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons Reviewed-by: Furquan Shaikh --- src/device/pci_device.c | 119 ++++++++++++++++++++++------------------ 1 file changed, 65 insertions(+), 54 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 5f50a31460..9011f0da4b 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -444,10 +444,70 @@ void pci_domain_set_resources(struct device *dev) assign_resources(dev->link_list); } -static void pci_set_resource(struct device *dev, struct resource *resource) +static void pci_store_resource(const struct device *const dev, + const struct resource *const resource) +{ + unsigned long base_lo, base_hi; + + base_lo = resource->base & 0xffffffff; + base_hi = (resource->base >> 32) & 0xffffffff; + + /* + * Some chipsets allow us to set/clear the I/O bit + * (e.g. VIA 82C686A). So set it to be safe. + */ + if (resource->flags & IORESOURCE_IO) + base_lo |= PCI_BASE_ADDRESS_SPACE_IO; + + pci_write_config32(dev, resource->index, base_lo); + if (resource->flags & IORESOURCE_PCI64) + pci_write_config32(dev, resource->index + 4, base_hi); +} + +static void pci_store_bridge_resource(const struct device *const dev, + struct resource *const resource) { resource_t base, end; + /* + * PCI bridges have no enable bit. They are disabled if the base of + * the range is greater than the limit. If the size is zero, disable + * by setting the base = limit and end = limit - 2^gran. + */ + if (resource->size == 0) { + base = resource->limit; + end = resource->limit - (1 << resource->gran); + resource->base = base; + } else { + base = resource->base; + end = resource_end(resource); + } + + if (resource->index == PCI_IO_BASE) { + /* Set the I/O ranges. */ + pci_write_config8(dev, PCI_IO_BASE, base >> 8); + pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16); + pci_write_config8(dev, PCI_IO_LIMIT, end >> 8); + pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16); + } else if (resource->index == PCI_MEMORY_BASE) { + /* Set the memory range. */ + pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16); + pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16); + } else if (resource->index == PCI_PREF_MEMORY_BASE) { + /* Set the prefetchable memory range. */ + pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16); + pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32); + pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16); + pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32); + } else { + /* Don't let me think I stored the resource. */ + resource->flags &= ~IORESOURCE_STORED; + printk(BIOS_ERR, "ERROR: invalid resource->index %lx\n", resource->index); + } +} + +static void pci_set_resource(struct device *dev, struct resource *resource) +{ /* Make certain the resource has actually been assigned a value. */ if (!(resource->flags & IORESOURCE_ASSIGNED)) { printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx not " @@ -482,62 +542,13 @@ static void pci_set_resource(struct device *dev, struct resource *resource) dev->command |= PCI_COMMAND_MASTER; } - /* Get the base address. */ - base = resource->base; - - /* Get the end. */ - end = resource_end(resource); - /* Now store the resource. */ resource->flags |= IORESOURCE_STORED; - /* - * PCI bridges have no enable bit. They are disabled if the base of - * the range is greater than the limit. If the size is zero, disable - * by setting the base = limit and end = limit - 2^gran. - */ - if (resource->size == 0 && (resource->flags & IORESOURCE_PCI_BRIDGE)) { - base = resource->limit; - end = resource->limit - (1 << resource->gran); - resource->base = base; - } - - if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) { - unsigned long base_lo, base_hi; - - /* - * Some chipsets allow us to set/clear the I/O bit - * (e.g. VIA 82C686A). So set it to be safe. - */ - base_lo = base & 0xffffffff; - base_hi = (base >> 32) & 0xffffffff; - if (resource->flags & IORESOURCE_IO) - base_lo |= PCI_BASE_ADDRESS_SPACE_IO; - pci_write_config32(dev, resource->index, base_lo); - if (resource->flags & IORESOURCE_PCI64) - pci_write_config32(dev, resource->index + 4, base_hi); - } else if (resource->index == PCI_IO_BASE) { - /* Set the I/O ranges. */ - pci_write_config8(dev, PCI_IO_BASE, base >> 8); - pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16); - pci_write_config8(dev, PCI_IO_LIMIT, end >> 8); - pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16); - } else if (resource->index == PCI_MEMORY_BASE) { - /* Set the memory range. */ - pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16); - pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16); - } else if (resource->index == PCI_PREF_MEMORY_BASE) { - /* Set the prefetchable memory range. */ - pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16); - pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32); - pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16); - pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32); - } else { - /* Don't let me think I stored the resource. */ - resource->flags &= ~IORESOURCE_STORED; - printk(BIOS_ERR, "ERROR: invalid resource->index %lx\n", - resource->index); - } + if (resource->flags & IORESOURCE_PCI_BRIDGE) + pci_store_bridge_resource(dev, resource); + else + pci_store_resource(dev, resource); report_resource_stored(dev, resource, ""); } From f531244d20998091bd8c311a4183de0bcc9f6ff2 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Wed, 20 May 2020 01:02:18 +0200 Subject: [PATCH 292/405] device/pci: Handle unassigned bus resources gracefully The I/O windows of PCI bridges can be disabled individually by setting their limit lower than their base. Always do this if a resource wasn't assigned a value. Change-Id: I73f6817c4b12cb1689627044735d1fed6d825afe Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/41552 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons Reviewed-by: Furquan Shaikh --- src/device/pci_device.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 9011f0da4b..e6c6ff31a4 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -510,10 +510,16 @@ static void pci_set_resource(struct device *dev, struct resource *resource) { /* Make certain the resource has actually been assigned a value. */ if (!(resource->flags & IORESOURCE_ASSIGNED)) { - printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx not " - "assigned\n", dev_path(dev), resource->index, - resource_type(resource), resource->size); - return; + if (resource->flags & IORESOURCE_BRIDGE) { + /* If a bridge resource has no value assigned, + we can treat it like an empty resource. */ + resource->size = 0; + } else { + printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx not " + "assigned\n", dev_path(dev), resource->index, + resource_type(resource), resource->size); + return; + } } /* If this resource is fixed don't worry about it. */ From afaae8aa00d59a1a74e7f7891d8def8cc21d9eb2 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 18 May 2020 16:00:53 -0700 Subject: [PATCH 293/405] device_util,agesa/family14: Do not consider unassigned resources in find_pci_tolm() This change updates find_pci_tolm() to not consider any unassigned resources. This is achieved by adding the following checks: 1. Call search_bus_resources() with mask set to IORESOURCE_MEM | IORESOURCE_ASSIGNED. 2. In the callback tolm_test, check that the new resource selected has a non-zero size. This change is being made so that the resource allocator does not have to set the IORESOURCE_ASSIGNED flag for marking a resource as invalid. Change-Id: I796784dd93aa165e20a672c985b4875991901c87 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41524 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/device/device_util.c | 11 +++++++++-- src/northbridge/amd/agesa/family14/northbridge.c | 3 ++- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/src/device/device_util.c b/src/device/device_util.c index 88608597f2..22c3db1c44 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -883,6 +883,13 @@ void tolm_test(void *gp, struct device *dev, struct resource *new) best = *best_p; + /* + * If resource is not allocated any space i.e. size is zero, + * then do not consider this resource in tolm calculations. + */ + if (new->size == 0) + return; + if (!best || (best->base > new->base)) best = new; @@ -893,9 +900,9 @@ u32 find_pci_tolm(struct bus *bus) { struct resource *min = NULL; u32 tolm; + unsigned long mask_match = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, - tolm_test, &min); + search_bus_resources(bus, mask_match, mask_match, tolm_test, &min); tolm = 0xffffffffUL; diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 5cb99d6ec2..34fc0c08b3 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -284,8 +284,9 @@ static void amdfam14_link_read_bases(struct device *dev, u32 nodeid, u32 link) static u32 my_find_pci_tolm(struct bus *bus, u32 tolm) { struct resource *min; + unsigned long mask_match = IORESOURCE_MEM | IORESOURCE_ASSIGNED; min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, + search_bus_resources(bus, mask_match, mask_match, tolm_test, &min); if (min && tolm > min->base) { tolm = min->base; From 69395742b8e45433e42c54e6cf8e67a692f923e9 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 15 May 2020 15:43:15 -0700 Subject: [PATCH 294/405] device: Move resource allocation into a separate compilation unit This change moves the resource allocator functions out of device.c and into two separate files: 1. resource_allocator_v3.c: This is the old implementation of resource allocator that uses a single window for resource allocation. It is required to support some AMD chipsets that do not provide an accurate map of allocated resources by the time the allocator runs. They work fine with the old allocator since it restricts itself to allocations in a single window at the top of the 4G space. 2. resource_allocator_common.c: This file contains the functions that can be shared by the old and new resource allocator. Entry point into the resource allocation is allocate_resources() which can be implemented by both old and new allocators. This change also adds a Kconfig option RESOURCE_ALLOCATOR_V3 which enables the old resource allocator. This config option is enabled by default currently, but in the following CLs this will be enabled only for the broken boards. Reason for this split: Both the old and new resource allocators need to be retained in the tree until the broken chipsets are fixed. Change-Id: I2f5440cf83c6e9e15a5f22e79cc3c66aa2cec4c0 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41442 Reviewed-by: Aaron Durbin Reviewed-by: Mike Banon Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/device/Kconfig | 7 + src/device/Makefile.inc | 3 + src/device/device.c | 593 +------------------------ src/device/resource_allocator_common.c | 61 +++ src/device/resource_allocator_v3.c | 546 +++++++++++++++++++++++ src/include/device/resource.h | 20 + 6 files changed, 638 insertions(+), 592 deletions(-) create mode 100644 src/device/resource_allocator_common.c create mode 100644 src/device/resource_allocator_v3.c diff --git a/src/device/Kconfig b/src/device/Kconfig index 751083cf81..a60965a01a 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -777,4 +777,11 @@ config SOFTWARE_I2C I2C controller is not (yet) available. The platform code needs to provide bindings to manually toggle I2C lines. +config RESOURCE_ALLOCATOR_V3 + bool + default y + help + This config option enables resource allocator v3 which performs + top down allocation of resources in a single MMIO window. + endmenu diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index 966ca0d198..9bbab37fce 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -58,3 +58,6 @@ bootblock-y += mmio.c verstage-y += mmio.c romstage-y += mmio.c ramstage-y += mmio.c + +ramstage-y += resource_allocator_common.c +ramstage-$(CONFIG_RESOURCE_ALLOCATOR_V3) += resource_allocator_v3.c diff --git a/src/device/device.c b/src/device/device.c index e4b5f12023..c54a345eeb 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -145,33 +145,6 @@ struct device *alloc_find_dev(struct bus *parent, struct device_path *path) return child; } -/** - * Round a number up to an alignment. - * - * @param val The starting value. - * @param pow Alignment as a power of two. - * @return Rounded up number. - */ -static resource_t round(resource_t val, unsigned long pow) -{ - resource_t mask; - mask = (1ULL << pow) - 1ULL; - val += mask; - val &= ~mask; - return val; -} - -static const char *resource2str(struct resource *res) -{ - if (res->flags & IORESOURCE_IO) - return "io"; - if (res->flags & IORESOURCE_PREFETCH) - return "prefmem"; - if (res->flags & IORESOURCE_MEM) - return "mem"; - return "undefined"; -} - /** * Read the resources on all devices of a given bus. * @@ -209,523 +182,6 @@ static void read_resources(struct bus *bus) dev_path(bus->dev), bus->secondary, bus->link_num); } -struct pick_largest_state { - struct resource *last; - const struct device *result_dev; - struct resource *result; - int seen_last; -}; - -static void pick_largest_resource(void *gp, struct device *dev, - struct resource *resource) -{ - struct pick_largest_state *state = gp; - struct resource *last; - - last = state->last; - - /* Be certain to pick the successor to last. */ - if (resource == last) { - state->seen_last = 1; - return; - } - if (resource->flags & IORESOURCE_FIXED) - return; /* Skip it. */ - if (last && ((last->align < resource->align) || - ((last->align == resource->align) && - (last->size < resource->size)) || - ((last->align == resource->align) && - (last->size == resource->size) && (!state->seen_last)))) { - return; - } - if (!state->result || - (state->result->align < resource->align) || - ((state->result->align == resource->align) && - (state->result->size < resource->size))) { - state->result_dev = dev; - state->result = resource; - } -} - -static const struct device *largest_resource(struct bus *bus, - struct resource **result_res, - unsigned long type_mask, - unsigned long type) -{ - struct pick_largest_state state; - - state.last = *result_res; - state.result_dev = NULL; - state.result = NULL; - state.seen_last = 0; - - search_bus_resources(bus, type_mask, type, pick_largest_resource, - &state); - - *result_res = state.result; - return state.result_dev; -} - -/** - * This function is the guts of the resource allocator. - * - * The problem. - * - Allocate resource locations for every device. - * - Don't overlap, and follow the rules of bridges. - * - Don't overlap with resources in fixed locations. - * - Be efficient so we don't have ugly strategies. - * - * The strategy. - * - Devices that have fixed addresses are the minority so don't - * worry about them too much. Instead only use part of the address - * space for devices with programmable addresses. This easily handles - * everything except bridges. - * - * - PCI devices are required to have their sizes and their alignments - * equal. In this case an optimal solution to the packing problem - * exists. Allocate all devices from highest alignment to least - * alignment or vice versa. Use this. - * - * - So we can handle more than PCI run two allocation passes on bridges. The - * first to see how large the resources are behind the bridge, and what - * their alignment requirements are. The second to assign a safe address to - * the devices behind the bridge. This allows us to treat a bridge as just - * a device with a couple of resources, and not need to special case it in - * the allocator. Also this allows handling of other types of bridges. - * - * @param bus The bus we are traversing. - * @param bridge The bridge resource which must contain the bus' resources. - * @param type_mask This value gets ANDed with the resource type. - * @param type This value must match the result of the AND. - * @return TODO - */ -static void compute_resources(struct bus *bus, struct resource *bridge, - unsigned long type_mask, unsigned long type) -{ - const struct device *dev; - struct resource *resource; - resource_t base; - base = round(bridge->base, bridge->align); - - if (!bus) - return; - - printk(BIOS_SPEW, "%s %s: base: %llx size: %llx align: %d gran: %d" - " limit: %llx\n", dev_path(bus->dev), resource2str(bridge), - base, bridge->size, bridge->align, - bridge->gran, bridge->limit); - - /* For each child which is a bridge, compute the resource needs. */ - for (dev = bus->children; dev; dev = dev->sibling) { - struct resource *child_bridge; - - if (!dev->link_list) - continue; - - /* Find the resources with matching type flags. */ - for (child_bridge = dev->resource_list; child_bridge; - child_bridge = child_bridge->next) { - struct bus* link; - - if (!(child_bridge->flags & IORESOURCE_BRIDGE) - || (child_bridge->flags & type_mask) != type) - continue; - - /* - * Split prefetchable memory if combined. Many domains - * use the same address space for prefetchable memory - * and non-prefetchable memory. Bridges below them need - * it separated. Add the PREFETCH flag to the type_mask - * and type. - */ - link = dev->link_list; - while (link && link->link_num != - IOINDEX_LINK(child_bridge->index)) - link = link->next; - - if (link == NULL) { - printk(BIOS_ERR, "link %ld not found on %s\n", - IOINDEX_LINK(child_bridge->index), - dev_path(dev)); - } - - compute_resources(link, child_bridge, - type_mask | IORESOURCE_PREFETCH, - type | (child_bridge->flags & - IORESOURCE_PREFETCH)); - } - } - - /* Remember we haven't found anything yet. */ - resource = NULL; - - /* - * Walk through all the resources on the current bus and compute the - * amount of address space taken by them. Take granularity and - * alignment into account. - */ - while ((dev = largest_resource(bus, &resource, type_mask, type))) { - - /* Size 0 resources can be skipped. */ - if (!resource->size) - continue; - - /* Propagate the resource alignment to the bridge resource. */ - if (resource->align > bridge->align) - bridge->align = resource->align; - - /* Propagate the resource limit to the bridge register. */ - if (bridge->limit > resource->limit) - bridge->limit = resource->limit; - - /* Warn if it looks like APICs aren't declared. */ - if ((resource->limit == 0xffffffff) && - (resource->flags & IORESOURCE_ASSIGNED)) { - printk(BIOS_ERR, - "Resource limit looks wrong! (no APIC?)\n"); - printk(BIOS_ERR, "%s %02lx limit %08llx\n", - dev_path(dev), resource->index, resource->limit); - } - - if (resource->flags & IORESOURCE_IO) { - /* - * Don't allow potential aliases over the legacy PCI - * expansion card addresses. The legacy PCI decodes - * only 10 bits, uses 0x100 - 0x3ff. Therefore, only - * 0x00 - 0xff can be used out of each 0x400 block of - * I/O space. - */ - if ((base & 0x300) != 0) { - base = (base & ~0x3ff) + 0x400; - } - /* - * Don't allow allocations in the VGA I/O range. - * PCI has special cases for that. - */ - else if ((base >= 0x3b0) && (base <= 0x3df)) { - base = 0x3e0; - } - } - /* Base must be aligned. */ - base = round(base, resource->align); - resource->base = base; - base += resource->size; - - printk(BIOS_SPEW, "%s %02lx * [0x%llx - 0x%llx] %s\n", - dev_path(dev), resource->index, resource->base, - resource->base + resource->size - 1, - resource2str(resource)); - } - - /* - * A PCI bridge resource does not need to be a power of two size, but - * it does have a minimum granularity. Round the size up to that - * minimum granularity so we know not to place something else at an - * address positively decoded by the bridge. - */ - bridge->size = round(base, bridge->gran) - - round(bridge->base, bridge->align); - - printk(BIOS_SPEW, "%s %s: base: %llx size: %llx align: %d gran: %d" - " limit: %llx done\n", dev_path(bus->dev), - resource2str(bridge), - base, bridge->size, bridge->align, bridge->gran, bridge->limit); -} - -/** - * This function is the second part of the resource allocator. - * - * See the compute_resources function for a more detailed explanation. - * - * This function assigns the resources a value. - * - * @param bus The bus we are traversing. - * @param bridge The bridge resource which must contain the bus' resources. - * @param type_mask This value gets ANDed with the resource type. - * @param type This value must match the result of the AND. - * - * @see compute_resources - */ -static void allocate_resources(struct bus *bus, struct resource *bridge, - unsigned long type_mask, unsigned long type) -{ - const struct device *dev; - struct resource *resource; - resource_t base; - base = bridge->base; - - if (!bus) - return; - - printk(BIOS_SPEW, "%s %s: base:%llx size:%llx align:%d gran:%d " - "limit:%llx\n", dev_path(bus->dev), - resource2str(bridge), - base, bridge->size, bridge->align, bridge->gran, bridge->limit); - - /* Remember we haven't found anything yet. */ - resource = NULL; - - /* - * Walk through all the resources on the current bus and allocate them - * address space. - */ - while ((dev = largest_resource(bus, &resource, type_mask, type))) { - - /* Propagate the bridge limit to the resource register. */ - if (resource->limit > bridge->limit) - resource->limit = bridge->limit; - - /* Size 0 resources can be skipped. */ - if (!resource->size) { - /* Set the base to limit so it doesn't confuse tolm. */ - resource->base = resource->limit; - resource->flags |= IORESOURCE_ASSIGNED; - continue; - } - - if (resource->flags & IORESOURCE_IO) { - /* - * Don't allow potential aliases over the legacy PCI - * expansion card addresses. The legacy PCI decodes - * only 10 bits, uses 0x100 - 0x3ff. Therefore, only - * 0x00 - 0xff can be used out of each 0x400 block of - * I/O space. - */ - if ((base & 0x300) != 0) { - base = (base & ~0x3ff) + 0x400; - } - /* - * Don't allow allocations in the VGA I/O range. - * PCI has special cases for that. - */ - else if ((base >= 0x3b0) && (base <= 0x3df)) { - base = 0x3e0; - } - } - - if ((round(base, resource->align) + resource->size - 1) <= - resource->limit) { - /* Base must be aligned. */ - base = round(base, resource->align); - resource->base = base; - resource->limit = resource->base + resource->size - 1; - resource->flags |= IORESOURCE_ASSIGNED; - resource->flags &= ~IORESOURCE_STORED; - base += resource->size; - } else { - printk(BIOS_ERR, "!! Resource didn't fit !!\n"); - printk(BIOS_ERR, " aligned base %llx size %llx " - "limit %llx\n", round(base, resource->align), - resource->size, resource->limit); - printk(BIOS_ERR, " %llx needs to be <= %llx " - "(limit)\n", (round(base, resource->align) + - resource->size) - 1, resource->limit); - printk(BIOS_ERR, " %s%s %02lx * [0x%llx - 0x%llx]" - " %s\n", (resource->flags & IORESOURCE_ASSIGNED) - ? "Assigned: " : "", dev_path(dev), - resource->index, resource->base, - resource->base + resource->size - 1, - resource2str(resource)); - } - - printk(BIOS_SPEW, "%s %02lx * [0x%llx - 0x%llx] %s\n", - dev_path(dev), resource->index, resource->base, - resource->size ? resource->base + resource->size - 1 : - resource->base, resource2str(resource)); - } - - /* - * A PCI bridge resource does not need to be a power of two size, but - * it does have a minimum granularity. Round the size up to that - * minimum granularity so we know not to place something else at an - * address positively decoded by the bridge. - */ - - bridge->flags |= IORESOURCE_ASSIGNED; - - printk(BIOS_SPEW, "%s %s: next_base: %llx size: %llx align: %d " - "gran: %d done\n", dev_path(bus->dev), - resource2str(bridge), base, bridge->size, bridge->align, - bridge->gran); - - /* For each child which is a bridge, allocate_resources. */ - for (dev = bus->children; dev; dev = dev->sibling) { - struct resource *child_bridge; - - if (!dev->link_list) - continue; - - /* Find the resources with matching type flags. */ - for (child_bridge = dev->resource_list; child_bridge; - child_bridge = child_bridge->next) { - struct bus* link; - - if (!(child_bridge->flags & IORESOURCE_BRIDGE) || - (child_bridge->flags & type_mask) != type) - continue; - - /* - * Split prefetchable memory if combined. Many domains - * use the same address space for prefetchable memory - * and non-prefetchable memory. Bridges below them need - * it separated. Add the PREFETCH flag to the type_mask - * and type. - */ - link = dev->link_list; - while (link && link->link_num != - IOINDEX_LINK(child_bridge->index)) - link = link->next; - if (link == NULL) - printk(BIOS_ERR, "link %ld not found on %s\n", - IOINDEX_LINK(child_bridge->index), - dev_path(dev)); - - allocate_resources(link, child_bridge, - type_mask | IORESOURCE_PREFETCH, - type | (child_bridge->flags & - IORESOURCE_PREFETCH)); - } - } -} - -static int resource_is(struct resource *res, u32 type) -{ - return (res->flags & IORESOURCE_TYPE_MASK) == type; -} - -struct constraints { - struct resource io, mem; -}; - -static struct resource *resource_limit(struct constraints *limits, - struct resource *res) -{ - struct resource *lim = NULL; - - /* MEM, or I/O - skip any others. */ - if (resource_is(res, IORESOURCE_MEM)) - lim = &limits->mem; - else if (resource_is(res, IORESOURCE_IO)) - lim = &limits->io; - - return lim; -} - -static void constrain_resources(const struct device *dev, - struct constraints* limits) -{ - const struct device *child; - struct resource *res; - struct resource *lim; - struct bus *link; - - /* Constrain limits based on the fixed resources of this device. */ - for (res = dev->resource_list; res; res = res->next) { - if (!(res->flags & IORESOURCE_FIXED)) - continue; - if (!res->size) { - /* It makes no sense to have 0-sized, fixed resources.*/ - printk(BIOS_ERR, "skipping %s@%lx fixed resource, " - "size=0!\n", dev_path(dev), res->index); - continue; - } - - lim = resource_limit(limits, res); - if (!lim) - continue; - - /* - * Is it a fixed resource outside the current known region? - * If so, we don't have to consider it - it will be handled - * correctly and doesn't affect current region's limits. - */ - if (((res->base + res->size -1) < lim->base) - || (res->base > lim->limit)) - continue; - - printk(BIOS_SPEW, "%s: %s %02lx base %08llx limit %08llx %s (fixed)\n", - __func__, dev_path(dev), res->index, res->base, - res->base + res->size - 1, resource2str(res)); - - /* - * Choose to be above or below fixed resources. This check is - * signed so that "negative" amounts of space are handled - * correctly. - */ - if ((signed long long)(lim->limit - (res->base + res->size -1)) - > (signed long long)(res->base - lim->base)) - lim->base = res->base + res->size; - else - lim->limit = res->base -1; - } - - /* Descend into every enabled child and look for fixed resources. */ - for (link = dev->link_list; link; link = link->next) { - for (child = link->children; child; child = child->sibling) { - if (child->enabled) - constrain_resources(child, limits); - } - } -} - -static void avoid_fixed_resources(const struct device *dev) -{ - struct constraints limits; - struct resource *res; - struct resource *lim; - - printk(BIOS_SPEW, "%s: %s\n", __func__, dev_path(dev)); - - /* Initialize constraints to maximum size. */ - limits.io.base = 0; - limits.io.limit = 0xffffffffffffffffULL; - limits.mem.base = 0; - limits.mem.limit = 0xffffffffffffffffULL; - - /* Constrain the limits to dev's initial resources. */ - for (res = dev->resource_list; res; res = res->next) { - if ((res->flags & IORESOURCE_FIXED)) - continue; - printk(BIOS_SPEW, "%s:@%s %02lx limit %08llx\n", __func__, - dev_path(dev), res->index, res->limit); - - lim = resource_limit(&limits, res); - if (!lim) - continue; - - if (res->base > lim->base) - lim->base = res->base; - if (res->limit < lim->limit) - lim->limit = res->limit; - } - - /* Look through the tree for fixed resources and update the limits. */ - constrain_resources(dev, &limits); - - /* Update dev's resources with new limits. */ - for (res = dev->resource_list; res; res = res->next) { - if ((res->flags & IORESOURCE_FIXED)) - continue; - - lim = resource_limit(&limits, res); - if (!lim) - continue; - - /* Is the resource outside the limits? */ - if (lim->base > res->base) - res->base = lim->base; - if (res->limit > lim->limit) - res->limit = lim->limit; - - /* MEM resources need to start at the highest address manageable. */ - if (res->flags & IORESOURCE_MEM) - res->base = resource_max(res); - - printk(BIOS_SPEW, "%s:@%s %02lx base %08llx limit %08llx\n", - __func__, dev_path(dev), res->index, res->base, res->limit); - } -} - struct device *vga_pri = NULL; static void set_vga_bridge_bits(void) { @@ -996,9 +452,7 @@ void dev_enumerate(void) */ void dev_configure(void) { - struct resource *res; const struct device *root; - const struct device *child; set_vga_bridge_bits(); @@ -1020,53 +474,8 @@ void dev_configure(void) print_resource_tree(root, BIOS_SPEW, "After reading."); - /* Compute resources for all domains. */ - for (child = root->link_list->children; child; child = child->sibling) { - if (!(child->path.type == DEVICE_PATH_DOMAIN)) - continue; - post_log_path(child); - for (res = child->resource_list; res; res = res->next) { - if (res->flags & IORESOURCE_FIXED) - continue; - if (res->flags & IORESOURCE_MEM) { - compute_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_MEM); - continue; - } - if (res->flags & IORESOURCE_IO) { - compute_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_IO); - continue; - } - } - } + allocate_resources(root); - /* For all domains. */ - for (child = root->link_list->children; child; child=child->sibling) - if (child->path.type == DEVICE_PATH_DOMAIN) - avoid_fixed_resources(child); - - /* Store the computed resource allocations into device registers ... */ - printk(BIOS_INFO, "Setting resources...\n"); - for (child = root->link_list->children; child; child = child->sibling) { - if (!(child->path.type == DEVICE_PATH_DOMAIN)) - continue; - post_log_path(child); - for (res = child->resource_list; res; res = res->next) { - if (res->flags & IORESOURCE_FIXED) - continue; - if (res->flags & IORESOURCE_MEM) { - allocate_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_MEM); - continue; - } - if (res->flags & IORESOURCE_IO) { - allocate_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_IO); - continue; - } - } - } assign_resources(root->link_list); printk(BIOS_INFO, "Done setting resources.\n"); print_resource_tree(root, BIOS_SPEW, "After assigning values."); diff --git a/src/device/resource_allocator_common.c b/src/device/resource_allocator_common.c new file mode 100644 index 0000000000..202318bfe6 --- /dev/null +++ b/src/device/resource_allocator_common.c @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +struct pick_largest_state { + struct resource *last; + const struct device *result_dev; + struct resource *result; + int seen_last; +}; + +static void pick_largest_resource(void *gp, struct device *dev, + struct resource *resource) +{ + struct pick_largest_state *state = gp; + struct resource *last; + + last = state->last; + + /* Be certain to pick the successor to last. */ + if (resource == last) { + state->seen_last = 1; + return; + } + if (resource->flags & IORESOURCE_FIXED) + return; /* Skip it. */ + if (last && ((last->align < resource->align) || + ((last->align == resource->align) && + (last->size < resource->size)) || + ((last->align == resource->align) && + (last->size == resource->size) && (!state->seen_last)))) { + return; + } + if (!state->result || + (state->result->align < resource->align) || + ((state->result->align == resource->align) && + (state->result->size < resource->size))) { + state->result_dev = dev; + state->result = resource; + } +} + +const struct device *largest_resource(struct bus *bus, + struct resource **result_res, + unsigned long type_mask, + unsigned long type) +{ + struct pick_largest_state state; + + state.last = *result_res; + state.result_dev = NULL; + state.result = NULL; + state.seen_last = 0; + + search_bus_resources(bus, type_mask, type, pick_largest_resource, + &state); + + *result_res = state.result; + return state.result_dev; +} diff --git a/src/device/resource_allocator_v3.c b/src/device/resource_allocator_v3.c new file mode 100644 index 0000000000..4eeb2409f8 --- /dev/null +++ b/src/device/resource_allocator_v3.c @@ -0,0 +1,546 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/** + * Round a number up to an alignment. + * + * @param val The starting value. + * @param pow Alignment as a power of two. + * @return Rounded up number. + */ +static resource_t round(resource_t val, unsigned long pow) +{ + resource_t mask; + mask = (1ULL << pow) - 1ULL; + val += mask; + val &= ~mask; + return val; +} + +static const char *resource2str(struct resource *res) +{ + if (res->flags & IORESOURCE_IO) + return "io"; + if (res->flags & IORESOURCE_PREFETCH) + return "prefmem"; + if (res->flags & IORESOURCE_MEM) + return "mem"; + return "undefined"; +} + +/** + * This function is the guts of the resource allocator. + * + * The problem. + * - Allocate resource locations for every device. + * - Don't overlap, and follow the rules of bridges. + * - Don't overlap with resources in fixed locations. + * - Be efficient so we don't have ugly strategies. + * + * The strategy. + * - Devices that have fixed addresses are the minority so don't + * worry about them too much. Instead only use part of the address + * space for devices with programmable addresses. This easily handles + * everything except bridges. + * + * - PCI devices are required to have their sizes and their alignments + * equal. In this case an optimal solution to the packing problem + * exists. Allocate all devices from highest alignment to least + * alignment or vice versa. Use this. + * + * - So we can handle more than PCI run two allocation passes on bridges. The + * first to see how large the resources are behind the bridge, and what + * their alignment requirements are. The second to assign a safe address to + * the devices behind the bridge. This allows us to treat a bridge as just + * a device with a couple of resources, and not need to special case it in + * the allocator. Also this allows handling of other types of bridges. + * + * @param bus The bus we are traversing. + * @param bridge The bridge resource which must contain the bus' resources. + * @param type_mask This value gets ANDed with the resource type. + * @param type This value must match the result of the AND. + * @return TODO + */ +static void compute_resources(struct bus *bus, struct resource *bridge, + unsigned long type_mask, unsigned long type) +{ + const struct device *dev; + struct resource *resource; + resource_t base; + base = round(bridge->base, bridge->align); + + if (!bus) + return; + + printk(BIOS_SPEW, "%s %s: base: %llx size: %llx align: %d gran: %d" + " limit: %llx\n", dev_path(bus->dev), resource2str(bridge), + base, bridge->size, bridge->align, + bridge->gran, bridge->limit); + + /* For each child which is a bridge, compute the resource needs. */ + for (dev = bus->children; dev; dev = dev->sibling) { + struct resource *child_bridge; + + if (!dev->link_list) + continue; + + /* Find the resources with matching type flags. */ + for (child_bridge = dev->resource_list; child_bridge; + child_bridge = child_bridge->next) { + struct bus* link; + + if (!(child_bridge->flags & IORESOURCE_BRIDGE) + || (child_bridge->flags & type_mask) != type) + continue; + + /* + * Split prefetchable memory if combined. Many domains + * use the same address space for prefetchable memory + * and non-prefetchable memory. Bridges below them need + * it separated. Add the PREFETCH flag to the type_mask + * and type. + */ + link = dev->link_list; + while (link && link->link_num != + IOINDEX_LINK(child_bridge->index)) + link = link->next; + + if (link == NULL) { + printk(BIOS_ERR, "link %ld not found on %s\n", + IOINDEX_LINK(child_bridge->index), + dev_path(dev)); + } + + compute_resources(link, child_bridge, + type_mask | IORESOURCE_PREFETCH, + type | (child_bridge->flags & + IORESOURCE_PREFETCH)); + } + } + + /* Remember we haven't found anything yet. */ + resource = NULL; + + /* + * Walk through all the resources on the current bus and compute the + * amount of address space taken by them. Take granularity and + * alignment into account. + */ + while ((dev = largest_resource(bus, &resource, type_mask, type))) { + + /* Size 0 resources can be skipped. */ + if (!resource->size) + continue; + + /* Propagate the resource alignment to the bridge resource. */ + if (resource->align > bridge->align) + bridge->align = resource->align; + + /* Propagate the resource limit to the bridge register. */ + if (bridge->limit > resource->limit) + bridge->limit = resource->limit; + + /* Warn if it looks like APICs aren't declared. */ + if ((resource->limit == 0xffffffff) && + (resource->flags & IORESOURCE_ASSIGNED)) { + printk(BIOS_ERR, + "Resource limit looks wrong! (no APIC?)\n"); + printk(BIOS_ERR, "%s %02lx limit %08llx\n", + dev_path(dev), resource->index, resource->limit); + } + + if (resource->flags & IORESOURCE_IO) { + /* + * Don't allow potential aliases over the legacy PCI + * expansion card addresses. The legacy PCI decodes + * only 10 bits, uses 0x100 - 0x3ff. Therefore, only + * 0x00 - 0xff can be used out of each 0x400 block of + * I/O space. + */ + if ((base & 0x300) != 0) { + base = (base & ~0x3ff) + 0x400; + } + /* + * Don't allow allocations in the VGA I/O range. + * PCI has special cases for that. + */ + else if ((base >= 0x3b0) && (base <= 0x3df)) { + base = 0x3e0; + } + } + /* Base must be aligned. */ + base = round(base, resource->align); + resource->base = base; + base += resource->size; + + printk(BIOS_SPEW, "%s %02lx * [0x%llx - 0x%llx] %s\n", + dev_path(dev), resource->index, resource->base, + resource->base + resource->size - 1, + resource2str(resource)); + } + + /* + * A PCI bridge resource does not need to be a power of two size, but + * it does have a minimum granularity. Round the size up to that + * minimum granularity so we know not to place something else at an + * address positively decoded by the bridge. + */ + bridge->size = round(base, bridge->gran) - + round(bridge->base, bridge->align); + + printk(BIOS_SPEW, "%s %s: base: %llx size: %llx align: %d gran: %d" + " limit: %llx done\n", dev_path(bus->dev), + resource2str(bridge), + base, bridge->size, bridge->align, bridge->gran, bridge->limit); +} + +/** + * This function is the second part of the resource allocator. + * + * See the compute_resources function for a more detailed explanation. + * + * This function assigns the resources a value. + * + * @param bus The bus we are traversing. + * @param bridge The bridge resource which must contain the bus' resources. + * @param type_mask This value gets ANDed with the resource type. + * @param type This value must match the result of the AND. + * + * @see compute_resources + */ +static void __allocate_resources(struct bus *bus, struct resource *bridge, + unsigned long type_mask, unsigned long type) +{ + const struct device *dev; + struct resource *resource; + resource_t base; + base = bridge->base; + + if (!bus) + return; + + printk(BIOS_SPEW, "%s %s: base:%llx size:%llx align:%d gran:%d " + "limit:%llx\n", dev_path(bus->dev), + resource2str(bridge), + base, bridge->size, bridge->align, bridge->gran, bridge->limit); + + /* Remember we haven't found anything yet. */ + resource = NULL; + + /* + * Walk through all the resources on the current bus and allocate them + * address space. + */ + while ((dev = largest_resource(bus, &resource, type_mask, type))) { + + /* Propagate the bridge limit to the resource register. */ + if (resource->limit > bridge->limit) + resource->limit = bridge->limit; + + /* Size 0 resources can be skipped. */ + if (!resource->size) { + /* Set the base to limit so it doesn't confuse tolm. */ + resource->base = resource->limit; + resource->flags |= IORESOURCE_ASSIGNED; + continue; + } + + if (resource->flags & IORESOURCE_IO) { + /* + * Don't allow potential aliases over the legacy PCI + * expansion card addresses. The legacy PCI decodes + * only 10 bits, uses 0x100 - 0x3ff. Therefore, only + * 0x00 - 0xff can be used out of each 0x400 block of + * I/O space. + */ + if ((base & 0x300) != 0) { + base = (base & ~0x3ff) + 0x400; + } + /* + * Don't allow allocations in the VGA I/O range. + * PCI has special cases for that. + */ + else if ((base >= 0x3b0) && (base <= 0x3df)) { + base = 0x3e0; + } + } + + if ((round(base, resource->align) + resource->size - 1) <= + resource->limit) { + /* Base must be aligned. */ + base = round(base, resource->align); + resource->base = base; + resource->limit = resource->base + resource->size - 1; + resource->flags |= IORESOURCE_ASSIGNED; + resource->flags &= ~IORESOURCE_STORED; + base += resource->size; + } else { + printk(BIOS_ERR, "!! Resource didn't fit !!\n"); + printk(BIOS_ERR, " aligned base %llx size %llx " + "limit %llx\n", round(base, resource->align), + resource->size, resource->limit); + printk(BIOS_ERR, " %llx needs to be <= %llx " + "(limit)\n", (round(base, resource->align) + + resource->size) - 1, resource->limit); + printk(BIOS_ERR, " %s%s %02lx * [0x%llx - 0x%llx]" + " %s\n", (resource->flags & IORESOURCE_ASSIGNED) + ? "Assigned: " : "", dev_path(dev), + resource->index, resource->base, + resource->base + resource->size - 1, + resource2str(resource)); + } + + printk(BIOS_SPEW, "%s %02lx * [0x%llx - 0x%llx] %s\n", + dev_path(dev), resource->index, resource->base, + resource->size ? resource->base + resource->size - 1 : + resource->base, resource2str(resource)); + } + + /* + * A PCI bridge resource does not need to be a power of two size, but + * it does have a minimum granularity. Round the size up to that + * minimum granularity so we know not to place something else at an + * address positively decoded by the bridge. + */ + + bridge->flags |= IORESOURCE_ASSIGNED; + + printk(BIOS_SPEW, "%s %s: next_base: %llx size: %llx align: %d " + "gran: %d done\n", dev_path(bus->dev), + resource2str(bridge), base, bridge->size, bridge->align, + bridge->gran); + + /* For each child which is a bridge, __allocate_resources. */ + for (dev = bus->children; dev; dev = dev->sibling) { + struct resource *child_bridge; + + if (!dev->link_list) + continue; + + /* Find the resources with matching type flags. */ + for (child_bridge = dev->resource_list; child_bridge; + child_bridge = child_bridge->next) { + struct bus* link; + + if (!(child_bridge->flags & IORESOURCE_BRIDGE) || + (child_bridge->flags & type_mask) != type) + continue; + + /* + * Split prefetchable memory if combined. Many domains + * use the same address space for prefetchable memory + * and non-prefetchable memory. Bridges below them need + * it separated. Add the PREFETCH flag to the type_mask + * and type. + */ + link = dev->link_list; + while (link && link->link_num != + IOINDEX_LINK(child_bridge->index)) + link = link->next; + if (link == NULL) + printk(BIOS_ERR, "link %ld not found on %s\n", + IOINDEX_LINK(child_bridge->index), + dev_path(dev)); + + __allocate_resources(link, child_bridge, + type_mask | IORESOURCE_PREFETCH, + type | (child_bridge->flags & + IORESOURCE_PREFETCH)); + } + } +} + +static int resource_is(struct resource *res, u32 type) +{ + return (res->flags & IORESOURCE_TYPE_MASK) == type; +} + +struct constraints { + struct resource io, mem; +}; + +static struct resource *resource_limit(struct constraints *limits, + struct resource *res) +{ + struct resource *lim = NULL; + + /* MEM, or I/O - skip any others. */ + if (resource_is(res, IORESOURCE_MEM)) + lim = &limits->mem; + else if (resource_is(res, IORESOURCE_IO)) + lim = &limits->io; + + return lim; +} + +static void constrain_resources(const struct device *dev, + struct constraints* limits) +{ + const struct device *child; + struct resource *res; + struct resource *lim; + struct bus *link; + + /* Constrain limits based on the fixed resources of this device. */ + for (res = dev->resource_list; res; res = res->next) { + if (!(res->flags & IORESOURCE_FIXED)) + continue; + if (!res->size) { + /* It makes no sense to have 0-sized, fixed resources.*/ + printk(BIOS_ERR, "skipping %s@%lx fixed resource, " + "size=0!\n", dev_path(dev), res->index); + continue; + } + + lim = resource_limit(limits, res); + if (!lim) + continue; + + /* + * Is it a fixed resource outside the current known region? + * If so, we don't have to consider it - it will be handled + * correctly and doesn't affect current region's limits. + */ + if (((res->base + res->size -1) < lim->base) + || (res->base > lim->limit)) + continue; + + printk(BIOS_SPEW, "%s: %s %02lx base %08llx limit %08llx %s (fixed)\n", + __func__, dev_path(dev), res->index, res->base, + res->base + res->size - 1, resource2str(res)); + + /* + * Choose to be above or below fixed resources. This check is + * signed so that "negative" amounts of space are handled + * correctly. + */ + if ((signed long long)(lim->limit - (res->base + res->size -1)) + > (signed long long)(res->base - lim->base)) + lim->base = res->base + res->size; + else + lim->limit = res->base -1; + } + + /* Descend into every enabled child and look for fixed resources. */ + for (link = dev->link_list; link; link = link->next) { + for (child = link->children; child; child = child->sibling) { + if (child->enabled) + constrain_resources(child, limits); + } + } +} + +static void avoid_fixed_resources(const struct device *dev) +{ + struct constraints limits; + struct resource *res; + struct resource *lim; + + printk(BIOS_SPEW, "%s: %s\n", __func__, dev_path(dev)); + + /* Initialize constraints to maximum size. */ + limits.io.base = 0; + limits.io.limit = 0xffffffffffffffffULL; + limits.mem.base = 0; + limits.mem.limit = 0xffffffffffffffffULL; + + /* Constrain the limits to dev's initial resources. */ + for (res = dev->resource_list; res; res = res->next) { + if ((res->flags & IORESOURCE_FIXED)) + continue; + printk(BIOS_SPEW, "%s:@%s %02lx limit %08llx\n", __func__, + dev_path(dev), res->index, res->limit); + + lim = resource_limit(&limits, res); + if (!lim) + continue; + + if (res->base > lim->base) + lim->base = res->base; + if (res->limit < lim->limit) + lim->limit = res->limit; + } + + /* Look through the tree for fixed resources and update the limits. */ + constrain_resources(dev, &limits); + + /* Update dev's resources with new limits. */ + for (res = dev->resource_list; res; res = res->next) { + if ((res->flags & IORESOURCE_FIXED)) + continue; + + lim = resource_limit(&limits, res); + if (!lim) + continue; + + /* Is the resource outside the limits? */ + if (lim->base > res->base) + res->base = lim->base; + if (res->limit > lim->limit) + res->limit = lim->limit; + + /* MEM resources need to start at the highest address manageable. */ + if (res->flags & IORESOURCE_MEM) + res->base = resource_max(res); + + printk(BIOS_SPEW, "%s:@%s %02lx base %08llx limit %08llx\n", + __func__, dev_path(dev), res->index, res->base, res->limit); + } +} + +void allocate_resources(const struct device *root) +{ + struct resource *res; + const struct device *child; + + /* Compute resources for all domains. */ + for (child = root->link_list->children; child; child = child->sibling) { + if (!(child->path.type == DEVICE_PATH_DOMAIN)) + continue; + post_log_path(child); + for (res = child->resource_list; res; res = res->next) { + if (res->flags & IORESOURCE_FIXED) + continue; + if (res->flags & IORESOURCE_MEM) { + compute_resources(child->link_list, + res, IORESOURCE_TYPE_MASK, IORESOURCE_MEM); + continue; + } + if (res->flags & IORESOURCE_IO) { + compute_resources(child->link_list, + res, IORESOURCE_TYPE_MASK, IORESOURCE_IO); + continue; + } + } + } + + /* For all domains. */ + for (child = root->link_list->children; child; child=child->sibling) + if (child->path.type == DEVICE_PATH_DOMAIN) + avoid_fixed_resources(child); + + /* Store the computed resource allocations into device registers ... */ + printk(BIOS_INFO, "Setting resources...\n"); + for (child = root->link_list->children; child; child = child->sibling) { + if (!(child->path.type == DEVICE_PATH_DOMAIN)) + continue; + post_log_path(child); + for (res = child->resource_list; res; res = res->next) { + if (res->flags & IORESOURCE_FIXED) + continue; + if (res->flags & IORESOURCE_MEM) { + __allocate_resources(child->link_list, + res, IORESOURCE_TYPE_MASK, IORESOURCE_MEM); + continue; + } + if (res->flags & IORESOURCE_IO) { + __allocate_resources(child->link_list, + res, IORESOURCE_TYPE_MASK, IORESOURCE_IO); + continue; + } + } + } +} diff --git a/src/include/device/resource.h b/src/include/device/resource.h index 1d04e9a1c8..c97b01d22f 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -91,4 +91,24 @@ static inline void *res2mmio(struct resource *res, unsigned long offset, return (void *)(uintptr_t)((res->base + offset) & ~mask); } +/* + * Pick largest resource on the bus using the given mask and type. + * Params: + * bus = Bus from which the resource needs to picked from. + * result_res = If NULL, there was no previous resource picked on this bus, else it points to + * the last picked resource. + * type_mask = Mask to be applied when searching for resource + * type = Expected type for the resource + * + * Returns: + * If resource is found, returns the device and sets result_rest to point to the resource. Else + * returns NULL. + */ +const struct device *largest_resource(struct bus *bus, struct resource **result_res, + unsigned long type_mask, unsigned long type); + + +/* Compute and allocate resources. This is the main resource allocator entry point. */ +void allocate_resources(const struct device *root); + #endif /* DEVICE_RESOURCE_H */ From 468bc6cd8f765016aa4e01e20e8f020ac820cbb7 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 20 May 2020 10:18:35 -0700 Subject: [PATCH 295/405] device/resource_allocator_v3: Do not set IORESOURCE_ASSIGNED for size 0 resource find_pci_tolm() is updated to ensure that it ignores resources that have a zero size. This change removes the setting of resource flags to IORESOURCE_ASSIGNED when the resource is not really allocated any space by the allocator. It also drops the setting of base to limit since that is not required anymore. Change-Id: If8c0d4bf1aa9cd6a5bdf056140f65cf2d70ed216 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41566 Reviewed-by: Nico Huber Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/device/resource_allocator_v3.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/device/resource_allocator_v3.c b/src/device/resource_allocator_v3.c index 4eeb2409f8..236e149cef 100644 --- a/src/device/resource_allocator_v3.c +++ b/src/device/resource_allocator_v3.c @@ -241,12 +241,8 @@ static void __allocate_resources(struct bus *bus, struct resource *bridge, resource->limit = bridge->limit; /* Size 0 resources can be skipped. */ - if (!resource->size) { - /* Set the base to limit so it doesn't confuse tolm. */ - resource->base = resource->limit; - resource->flags |= IORESOURCE_ASSIGNED; + if (!resource->size) continue; - } if (resource->flags & IORESOURCE_IO) { /* From f4bc9eb2e652ca72554a4a0a5a221ee924a56f69 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 15 May 2020 16:04:28 -0700 Subject: [PATCH 296/405] device: Add support for resource allocator v4 This change adds back support for the resource allocator using multiple ranges as originally landed in CB:39486(commit hash 3b02006) and reverted in CB:41413(commit hash 6186cbc). The new resource allocator can be selected by Kconfig option RESOURCE_ALLOCATOR_V4. It was identified that there are some AMD chipsets in the tree that do not really work well with the dynamic resource allocation. Until these chipsets are fixed, old (v3) and new (v4) of the resource allocator need to live side-by-side in the tree. There were some other chipsets in the tree which originally demonstrated problems with the new resource allocator, but have been since fixed in the tree. This change picks up the same additions as performed in CB:39486 along with the following changes: 1. Changes to avoid fixed resources in the entire tree. Use of search_bus_resources() is replaced with a walk of the entire tree in avoid_fixed_resources(). This is required to ensure that all fixed resources added to any device (including domain) are taken into consideration to avoid overlap during dynamic resource allocation. 2. Changes to set up alignment for memranges when initializing them. This is done to ensure that the right granularity is used for IORESOURCE_IO(no special alignment) and IORESOURCE_MEM(4KiB) resource requests. 3. mark_resource_invalid() is dropped as the resource no longer needs to be marked in any special way if allocation is not being done. Instead setting of IORESOURCE_ASSIGNED flag is skipped in this case. 4. initialize_memranges() is updated to check IORESOURCE_ASSIGNED instead of base == limit. Original commit message: This change updates the resource allocator in coreboot to allow using multiple ranges for resource allocation rather than restricting available window to a single base/limit pair. This is done in preparation to allow 64-bit resource allocation. Following changes are made as part of this: a) Resource allocator still makes 2 passes at the entire tree. The first pass is to gather the resource requirements of each device under each domain. It walks recursively in DFS fashion to gather the requirements of the leaf devices and propagates this back up to the downstream bridges of the domain. Domain is special in the sense that it has fixed resource ranges. Hence, the resource requirements from the downstream devices have no effect on the domain resource windows. This results in domain resource limits being unmodified after the first pass. b) Once the requirements for all the devices under the domain are gathered, resource allocator walks a second time to allocate resources to downstream devices as per the requirements. Here, instead of maintaining a single window for allocating resources, it creates a list of memranges starting with the resource window at domain and then applying constraints to create holes for any fixed resources. This ensures that there is no overlap with fixed resources under the domain. c) Domain does not differentiate between mem and prefmem. Since they are allocated space from the same resource window at the domain level, it considers all resource requests from downstream devices of the domain independent of the prefetch type. d) Once resource allocation is done at the domain level, resource allocator walks down the downstream bridges and continues the same process until it reaches the leaves. Bridges have separate windows for mem and prefmem. Hence, unlike domain, the resource allocator at bridge level ensures that downstream requirements are satisfied by taking prefetch type into consideration. e) This whole 2-pass process is performed for every domain in the system under the assumption that domains do not have overlapping address spaces. Noticeable differences from previous resource allocator: a) Changes in print logs observed due to flows being slightly different. b) Base, limit and size of domain resources are no longer updated based on downstream requirements. c) Memranges are used instead of a single base/limit pair for determining resource allocation. d) Previously, if a resource request did not fit in the available base/limit window, then the resource would be allocated over DRAM or any other address space defeating the principle of "no overlap". With this change, any time a resource cannot fit in the available ranges, it complains and ensures that the resource is effectively disabled by setting base same as the limit. e) Resource allocator no longer looks at multiple links to determine the right bus for a resource. None of the current boards have multiple buses under any downstream device of the domain. The only device with multiple links seems to be the cpu cluster device for some AMD platforms. Change-Id: Ide4d98528197bb03850a8fb4d73c41cd2c0195aa Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41443 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/device/Kconfig | 9 + src/device/Makefile.inc | 1 + src/device/resource_allocator_v4.c | 552 +++++++++++++++++++++++++++++ 3 files changed, 562 insertions(+) create mode 100644 src/device/resource_allocator_v4.c diff --git a/src/device/Kconfig b/src/device/Kconfig index a60965a01a..801b040e08 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -784,4 +784,13 @@ config RESOURCE_ALLOCATOR_V3 This config option enables resource allocator v3 which performs top down allocation of resources in a single MMIO window. +config RESOURCE_ALLOCATOR_V4 + bool + default n if RESOURCE_ALLOCATOR_V3 + default y if !RESOURCE_ALLOCATOR_V3 + help + This config option enables resource allocator v4 which uses multiple + ranges for allocating resources. This allows allocation of resources + above 4G boundary as well. + endmenu diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index 9bbab37fce..2e62d4284d 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -61,3 +61,4 @@ ramstage-y += mmio.c ramstage-y += resource_allocator_common.c ramstage-$(CONFIG_RESOURCE_ALLOCATOR_V3) += resource_allocator_v3.c +ramstage-$(CONFIG_RESOURCE_ALLOCATOR_V4) += resource_allocator_v4.c diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c new file mode 100644 index 0000000000..ece7150b32 --- /dev/null +++ b/src/device/resource_allocator_v4.c @@ -0,0 +1,552 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +/** + * Round a number up to an alignment. + * + * @param val The starting value. + * @param pow Alignment as a power of two. + * @return Rounded up number. + */ +static resource_t round(resource_t val, unsigned long pow) +{ + return ALIGN_UP(val, POWER_OF_2(pow)); +} + +static const char *resource2str(const struct resource *res) +{ + if (res->flags & IORESOURCE_IO) + return "io"; + if (res->flags & IORESOURCE_PREFETCH) + return "prefmem"; + if (res->flags & IORESOURCE_MEM) + return "mem"; + return "undefined"; +} + +static bool dev_has_children(const struct device *dev) +{ + const struct bus *bus = dev->link_list; + return bus && bus->children; +} + +/* + * During pass 1, once all the requirements for downstream devices of a bridge are gathered, + * this function calculates the overall resource requirement for the bridge. It starts by + * picking the largest resource requirement downstream for the given resource type and works by + * adding requirements in descending order. + * + * Additionally, it takes alignment and limits of the downstream devices into consideration and + * ensures that they get propagated to the bridge resource. This is required to guarantee that + * the upstream bridge/domain honors the limit and alignment requirements for this bridge based + * on the tightest constraints downstream. + */ +static void update_bridge_resource(const struct device *bridge, struct resource *bridge_res, + unsigned long type_match) +{ + const struct device *child; + struct resource *child_res; + resource_t base; + bool first_child_res = true; + const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH; + struct bus *bus = bridge->link_list; + + child_res = NULL; + + /* + * `base` keeps track of where the next allocation for child resource can take place + * from within the bridge resource window. Since the bridge resource window allocation + * is not performed yet, it can start at 0. Base gets updated every time a resource + * requirement is accounted for in the loop below. After scanning all these resources, + * base will indicate the total size requirement for the current bridge resource + * window. + */ + base = 0; + + printk(BIOS_SPEW, "%s %s: size: %llx align: %d gran: %d limit: %llx\n", + dev_path(bridge), resource2str(bridge_res), bridge_res->size, + bridge_res->align, bridge_res->gran, bridge_res->limit); + + while ((child = largest_resource(bus, &child_res, type_mask, type_match))) { + + /* Size 0 resources can be skipped. */ + if (!child_res->size) + continue; + + /* + * Propagate the resource alignment to the bridge resource if this is the first + * child resource with non-zero size being considered. For all other children + * resources, alignment is taken care of by updating the base to round up as per + * the child resource alignment. It is guaranteed that pass 2 follows the exact + * same method of picking the resource for allocation using + * largest_resource(). Thus, as long as the alignment for first child resource + * is propagated up to the bridge resource, it can be guaranteed that the + * alignment for all resources is appropriately met. + */ + if (first_child_res && (child_res->align > bridge_res->align)) + bridge_res->align = child_res->align; + + first_child_res = false; + + /* + * Propagate the resource limit to the bridge resource only if child resource + * limit is non-zero. If a downstream device has stricter requirements + * w.r.t. limits for any resource, that constraint needs to be propagated back + * up to the downstream bridges of the domain. This guarantees that the resource + * allocation which starts at the domain level takes into account all these + * constraints thus working on a global view. + */ + if (child_res->limit && (child_res->limit < bridge_res->limit)) + bridge_res->limit = child_res->limit; + + /* + * Alignment value of 0 means that the child resource has no alignment + * requirements and so the base value remains unchanged here. + */ + base = round(base, child_res->align); + + printk(BIOS_SPEW, "%s %02lx * [0x%llx - 0x%llx] %s\n", + dev_path(child), child_res->index, base, base + child_res->size - 1, + resource2str(child_res)); + + base += child_res->size; + } + + /* + * After all downstream device resources are scanned, `base` represents the total size + * requirement for the current bridge resource window. This size needs to be rounded up + * to the granularity requirement of the bridge to ensure that the upstream + * bridge/domain allocates big enough window. + */ + bridge_res->size = round(base, bridge_res->gran); + + printk(BIOS_SPEW, "%s %s: size: %llx align: %d gran: %d limit: %llx done\n", + dev_path(bridge), resource2str(bridge_res), bridge_res->size, + bridge_res->align, bridge_res->gran, bridge_res->limit); +} + +/* + * During pass 1, resource allocator at bridge level gathers requirements from downstream + * devices and updates its own resource windows for the provided resource type. + */ +static void compute_bridge_resources(const struct device *bridge, unsigned long type_match) +{ + const struct device *child; + struct resource *res; + struct bus *bus = bridge->link_list; + const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH; + + for (res = bridge->resource_list; res; res = res->next) { + if (!(res->flags & IORESOURCE_BRIDGE)) + continue; + + if ((res->flags & type_mask) != type_match) + continue; + + /* + * Ensure that the resource requirements for all downstream bridges are + * gathered before updating the window for current bridge resource. + */ + for (child = bus->children; child; child = child->sibling) { + if (!dev_has_children(child)) + continue; + compute_bridge_resources(child, type_match); + } + + /* + * Update the window for current bridge resource now that all downstream + * requirements are gathered. + */ + update_bridge_resource(bridge, res, type_match); + } +} + +/* + * During pass 1, resource allocator walks down the entire sub-tree of a domain. It gathers + * resource requirements for every downstream bridge by looking at the resource requests of its + * children. Thus, the requirement gathering begins at the leaf devices and is propagated back + * up to the downstream bridges of the domain. + * + * At domain level, it identifies every downstream bridge and walks down that bridge to gather + * requirements for each resource type i.e. i/o, mem and prefmem. Since bridges have separate + * windows for mem and prefmem, requirements for each need to be collected separately. + * + * Domain resource windows are fixed ranges and hence requirement gathering does not result in + * any changes to these fixed ranges. + */ +static void compute_domain_resources(const struct device *domain) +{ + const struct device *child; + + if (domain->link_list == NULL) + return; + + for (child = domain->link_list->children; child; child = child->sibling) { + + /* Skip if this is not a bridge or has no children under it. */ + if (!dev_has_children(child)) + continue; + + compute_bridge_resources(child, IORESOURCE_IO); + compute_bridge_resources(child, IORESOURCE_MEM); + compute_bridge_resources(child, IORESOURCE_MEM | IORESOURCE_PREFETCH); + } +} + +static unsigned char get_alignment_by_resource_type(const struct resource *res) +{ + if (res->flags & IORESOURCE_MEM) + return 12; /* Page-aligned --> log2(4KiB) */ + else if (res->flags & IORESOURCE_IO) + return 0; /* No special alignment required --> log2(1) */ + + die("Unexpected resource type: flags(%d)!\n", res->flags); +} + +static void initialize_memranges(struct memranges *ranges, const struct resource *res, + unsigned long memrange_type) +{ + resource_t res_base; + resource_t res_limit; + unsigned char align = get_alignment_by_resource_type(res); + + memranges_init_empty_with_alignment(ranges, NULL, 0, align); + + if ((res == NULL) || !(res->flags & IORESOURCE_ASSIGNED)) + return; + + res_base = res->base; + res_limit = res->limit; + + memranges_insert(ranges, res_base, res_limit - res_base + 1, memrange_type); +} + +static void print_resource_ranges(const struct memranges *ranges) +{ + const struct range_entry *r; + + printk(BIOS_INFO, "Resource ranges:\n"); + + if (memranges_is_empty(ranges)) + printk(BIOS_INFO, "EMPTY!!\n"); + + memranges_each_entry(r, ranges) { + printk(BIOS_INFO, "Base: %llx, Size: %llx, Tag: %lx\n", + range_entry_base(r), range_entry_size(r), range_entry_tag(r)); + } +} + +/* + * This is where the actual allocation of resources happens during pass 2. Given the list of + * memory ranges corresponding to the resource of given type, it finds the biggest unallocated + * resource using the type mask on the downstream bus. This continues in a descending + * order until all resources of given type are allocated address space within the current + * resource window. + */ +static void allocate_child_resources(struct bus *bus, struct memranges *ranges, + unsigned long type_mask, unsigned long type_match) +{ + struct resource *resource = NULL; + const struct device *dev; + + while ((dev = largest_resource(bus, &resource, type_mask, type_match))) { + + if (!resource->size) + continue; + + if (memranges_steal(ranges, resource->limit, resource->size, resource->align, + type_match, &resource->base) == false) { + printk(BIOS_ERR, "ERROR: Resource didn't fit!!! "); + printk(BIOS_SPEW, "%s %02lx * size: 0x%llx limit: %llx %s\n", + dev_path(dev), resource->index, + resource->size, resource->limit, resource2str(resource)); + continue; + } + + resource->limit = resource->base + resource->size - 1; + resource->flags |= IORESOURCE_ASSIGNED; + + printk(BIOS_SPEW, "%s %02lx * [0x%llx - 0x%llx] limit: %llx %s\n", + dev_path(dev), resource->index, resource->base, + resource->size ? resource->base + resource->size - 1 : + resource->base, resource->limit, resource2str(resource)); + } +} + +static void update_constraints(struct memranges *ranges, const struct device *dev, + const struct resource *res) +{ + if (!res->size) + return; + + printk(BIOS_SPEW, "%s: %s %02lx base %08llx limit %08llx %s (fixed)\n", + __func__, dev_path(dev), res->index, res->base, + res->base + res->size - 1, resource2str(res)); + + memranges_create_hole(ranges, res->base, res->size); +} + +/* + * Scan the entire tree to identify any fixed resources allocated by any device to + * ensure that the address map for domain resources are appropriately updated. + * + * Domains can typically provide memrange for entire address space. So, this function + * punches holes in the address space for all fixed resources that are already + * defined. Both IO and normal memory resources are added as fixed. Both need to be + * removed from address space where dynamic resource allocations are sourced. + */ +static void avoid_fixed_resources(struct memranges *ranges, const struct device *dev, + unsigned long mask_match) +{ + const struct resource *res; + const struct device *child; + const struct bus *bus; + + for (res = dev->resource_list; res != NULL; res = res->next) { + if ((res->flags & mask_match) != mask_match) + continue; + update_constraints(ranges, dev, res); + } + + bus = dev->link_list; + if (bus == NULL) + return; + + for (child = bus->children; child != NULL; child = child->sibling) + avoid_fixed_resources(ranges, child, mask_match); +} + +static void constrain_domain_resources(const struct device *domain, struct memranges *ranges, + unsigned long type) +{ + unsigned long mask_match = type | IORESOURCE_FIXED; + + if (type == IORESOURCE_IO) { + /* + * Don't allow allocations in the VGA I/O range. PCI has special cases for + * that. + */ + memranges_create_hole(ranges, 0x3b0, 0x3df); + + /* + * Resource allocator no longer supports the legacy behavior where I/O resource + * allocation is guaranteed to avoid aliases over legacy PCI expansion card + * addresses. + */ + } + + avoid_fixed_resources(ranges, domain, mask_match); +} + +/* + * This function creates a list of memranges of given type using the resource that is + * provided. If the given resource is NULL or if the resource window size is 0, then it creates + * an empty list. This results in resource allocation for that resource type failing for all + * downstream devices since there is nothing to allocate from. + * + * In case of domain, it applies additional constraints to ensure that the memranges do not + * overlap any of the fixed resources under that domain. Domain typically seems to provide + * memrange for entire address space. Thus, it is up to the chipset to add DRAM and all other + * windows which cannot be used for resource allocation as fixed resources. + */ +static void setup_resource_ranges(const struct device *dev, const struct resource *res, + unsigned long type, struct memranges *ranges) +{ + printk(BIOS_SPEW, "%s %s: base: %llx size: %llx align: %d gran: %d limit: %llx\n", + dev_path(dev), resource2str(res), res->base, res->size, res->align, + res->gran, res->limit); + + initialize_memranges(ranges, res, type); + + if (dev->path.type == DEVICE_PATH_DOMAIN) + constrain_domain_resources(dev, ranges, type); + + print_resource_ranges(ranges); +} + +static void cleanup_resource_ranges(const struct device *dev, struct memranges *ranges, + const struct resource *res) +{ + memranges_teardown(ranges); + printk(BIOS_SPEW, "%s %s: base: %llx size: %llx align: %d gran: %d limit: %llx done\n", + dev_path(dev), resource2str(res), res->base, res->size, res->align, + res->gran, res->limit); +} + +/* + * Pass 2 of resource allocator at the bridge level loops through all the resources for the + * bridge and generates a list of memory ranges similar to that at the domain level. However, + * there is no need to apply any additional constraints since the window allocated to the bridge + * is guaranteed to be non-overlapping by the allocator at domain level. + * + * Allocation at the bridge level works the same as at domain level (starts with the biggest + * resource requirement from downstream devices and continues in descending order). One major + * difference at the bridge level is that it considers prefmem resources separately from mem + * resources. + * + * Once allocation at the current bridge is complete, resource allocator continues walking down + * the downstream bridges until it hits the leaf devices. + */ +static void allocate_bridge_resources(const struct device *bridge) +{ + struct memranges ranges; + const struct resource *res; + struct bus *bus = bridge->link_list; + unsigned long type_match; + struct device *child; + const unsigned long type_mask = IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH; + + for (res = bridge->resource_list; res; res = res->next) { + if (!res->size) + continue; + + if (!(res->flags & IORESOURCE_BRIDGE)) + continue; + + type_match = res->flags & type_mask; + + setup_resource_ranges(bridge, res, type_match, &ranges); + allocate_child_resources(bus, &ranges, type_mask, type_match); + cleanup_resource_ranges(bridge, &ranges, res); + } + + for (child = bus->children; child; child = child->sibling) { + if (!dev_has_children(child)) + continue; + + allocate_bridge_resources(child); + } +} + +static const struct resource *find_domain_resource(const struct device *domain, + unsigned long type) +{ + const struct resource *res; + + for (res = domain->resource_list; res; res = res->next) { + if (res->flags & IORESOURCE_FIXED) + continue; + + if ((res->flags & IORESOURCE_TYPE_MASK) == type) + return res; + } + + return NULL; +} + +/* + * Pass 2 of resource allocator begins at the domain level. Every domain has two types of + * resources - io and mem. For each of these resources, this function creates a list of memory + * ranges that can be used for downstream resource allocation. This list is constrained to + * remove any fixed resources in the domain sub-tree of the given resource type. It then uses + * the memory ranges to apply best fit on the resource requirements of the downstream devices. + * + * Once resources are allocated to all downstream devices of the domain, it walks down each + * downstream bridge to continue the same process until resources are allocated to all devices + * under the domain. + */ +static void allocate_domain_resources(const struct device *domain) +{ + struct memranges ranges; + struct device *child; + const struct resource *res; + + /* Resource type I/O */ + res = find_domain_resource(domain, IORESOURCE_IO); + if (res) { + setup_resource_ranges(domain, res, IORESOURCE_IO, &ranges); + allocate_child_resources(domain->link_list, &ranges, IORESOURCE_TYPE_MASK, + IORESOURCE_IO); + cleanup_resource_ranges(domain, &ranges, res); + } + + /* + * Resource type Mem: + * Domain does not distinguish between mem and prefmem resources. Thus, the resource + * allocation at domain level considers mem and prefmem together when finding the best + * fit based on the biggest resource requirement. + */ + res = find_domain_resource(domain, IORESOURCE_MEM); + if (res) { + setup_resource_ranges(domain, res, IORESOURCE_MEM, &ranges); + allocate_child_resources(domain->link_list, &ranges, IORESOURCE_TYPE_MASK, + IORESOURCE_MEM); + cleanup_resource_ranges(domain, &ranges, res); + } + + for (child = domain->link_list->children; child; child = child->sibling) { + if (!dev_has_children(child)) + continue; + + /* Continue allocation for all downstream bridges. */ + allocate_bridge_resources(child); + } +} + +/* + * This function forms the guts of the resource allocator. It walks through the entire device + * tree for each domain two times. + * + * Every domain has a fixed set of ranges. These ranges cannot be relaxed based on the + * requirements of the downstream devices. They represent the available windows from which + * resources can be allocated to the different devices under the domain. + * + * In order to identify the requirements of downstream devices, resource allocator walks in a + * DFS fashion. It gathers the requirements from leaf devices and propagates those back up + * to their upstream bridges until the requirements for all the downstream devices of the domain + * are gathered. This is referred to as pass 1 of resource allocator. + * + * Once the requirements for all the devices under the domain are gathered, resource allocator + * walks a second time to allocate resources to downstream devices as per the + * requirements. It always picks the biggest resource request as per the type (i/o and mem) to + * allocate space from its fixed window to the immediate downstream device of the domain. In + * order to accomplish best fit for the resources, a list of ranges is maintained by each + * resource type (i/o and mem). Domain does not differentiate between mem and prefmem. Since + * they are allocated space from the same window, the resource allocator at the domain level + * ensures that the biggest requirement is selected indepedent of the prefetch type. Once the + * resource allocation for all immediate downstream devices is complete at the domain level, + * resource allocator walks down the subtree for each downstream bridge to continue the + * allocation process at the bridge level. Since bridges have separate windows for i/o, mem and + * prefmem, best fit algorithm at bridge level looks for the biggest requirement considering + * prefmem resources separately from non-prefmem resources. This continues until resource + * allocation is performed for all downstream bridges in the domain sub-tree. This is referred + * to as pass 2 of resource allocator. + * + * Some rules that are followed by the resource allocator: + * - Allocate resource locations for every device as long as the requirements can be satisfied. + * - If a resource cannot be allocated any address space, then that resource needs to be + * properly updated to ensure that it does not incorrectly overlap some address space reserved + * for a different purpose. + * - Don't overlap with resources in fixed locations. + * - Don't overlap and follow the rules of bridges -- downstream devices of bridges should use + * parts of the address space allocated to the bridge. + */ +void allocate_resources(const struct device *root) +{ + const struct device *child; + + if ((root == NULL) || (root->link_list == NULL)) + return; + + for (child = root->link_list->children; child; child = child->sibling) { + + if (child->path.type != DEVICE_PATH_DOMAIN) + continue; + + post_log_path(child); + + /* Pass 1 - Gather requirements. */ + printk(BIOS_INFO, "Resource allocator: %s - Pass 1 (gathering requirements)\n", + dev_path(child)); + compute_domain_resources(child); + + /* Pass 2 - Allocate resources as per gathered requirements. */ + printk(BIOS_INFO, "Resource allocator: %s - Pass 2 (allocating resources)\n", + dev_path(child)); + allocate_domain_resources(child); + } +} From 8bdf3f4a047d5777534e18ac641f53a304587fe7 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 15 May 2020 16:21:22 -0700 Subject: [PATCH 297/405] northbridge/amd: Keep using old resource allocator This change selects the old resource allocator RESOURCE_ALLOCATOR_V3 for northbridge/amd chipsets. This is required until the chipsets can be fixed to report the resource requirements correctly before resource allocator runs. Issues identified in the chipset code are captured in the mailing list thread here: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/QWLUXO3V5IR5AS6ARRI722BFVAPOD5TS Change-Id: Iaf873ee76a67482483e410aede653dd8f662e468 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41444 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Mike Banon --- src/northbridge/amd/agesa/family14/Kconfig | 1 + src/northbridge/amd/agesa/family15tn/Kconfig | 1 + src/northbridge/amd/agesa/family16kb/Kconfig | 1 + src/northbridge/amd/pi/00630F01/Kconfig | 1 + src/northbridge/amd/pi/00660F01/Kconfig | 1 + src/northbridge/amd/pi/00730F01/Kconfig | 1 + 6 files changed, 6 insertions(+) diff --git a/src/northbridge/amd/agesa/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig index 050f471490..edd7dcb3ad 100644 --- a/src/northbridge/amd/agesa/family14/Kconfig +++ b/src/northbridge/amd/agesa/family14/Kconfig @@ -2,6 +2,7 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY14 bool + select RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_AGESA_FAMILY14 diff --git a/src/northbridge/amd/agesa/family15tn/Kconfig b/src/northbridge/amd/agesa/family15tn/Kconfig index a3fafc1de5..8f012d5083 100644 --- a/src/northbridge/amd/agesa/family15tn/Kconfig +++ b/src/northbridge/amd/agesa/family15tn/Kconfig @@ -2,6 +2,7 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY15_TN bool + select RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_AGESA_FAMILY15_TN diff --git a/src/northbridge/amd/agesa/family16kb/Kconfig b/src/northbridge/amd/agesa/family16kb/Kconfig index 3ae31c7d84..4488f8dc42 100644 --- a/src/northbridge/amd/agesa/family16kb/Kconfig +++ b/src/northbridge/amd/agesa/family16kb/Kconfig @@ -2,6 +2,7 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY16_KB bool + select RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_AGESA_FAMILY16_KB diff --git a/src/northbridge/amd/pi/00630F01/Kconfig b/src/northbridge/amd/pi/00630F01/Kconfig index 73df343de4..292492e6ea 100644 --- a/src/northbridge/amd/pi/00630F01/Kconfig +++ b/src/northbridge/amd/pi/00630F01/Kconfig @@ -2,6 +2,7 @@ config NORTHBRIDGE_AMD_PI_00630F01 bool + select RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_PI_00630F01 diff --git a/src/northbridge/amd/pi/00660F01/Kconfig b/src/northbridge/amd/pi/00660F01/Kconfig index 3bd9d78bac..e42ba80f0d 100644 --- a/src/northbridge/amd/pi/00660F01/Kconfig +++ b/src/northbridge/amd/pi/00660F01/Kconfig @@ -2,6 +2,7 @@ config NORTHBRIDGE_AMD_PI_00660F01 bool + select RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_PI_00660F01 diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig index d0d34a8739..cb655062d0 100644 --- a/src/northbridge/amd/pi/00730F01/Kconfig +++ b/src/northbridge/amd/pi/00730F01/Kconfig @@ -2,6 +2,7 @@ config NORTHBRIDGE_AMD_PI_00730F01 bool + select RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_PI_00730F01 From 7cf96aeeb7b983d50387297931bbeeed642552fc Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 16 May 2020 23:55:02 -0700 Subject: [PATCH 298/405] northbridge/intel/i945: Mark legacy VGA memory as reserved This change adds legacy VGA memory (0xa0000 - 0xbffff) as mmio_resource in northbridge.c read_resources() to match what is exposed to the OS in hostbridge.asl. It ensures that the resource allocator does not use this range for dynamic resource allocation. Change-Id: I24e3aaf97202575fa9df8408366c8db5bea07145 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41482 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: HAOUAS Elyes --- src/northbridge/intel/i945/northbridge.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index f814c976b4..56cad7a971 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -110,6 +110,8 @@ static void mch_domain_read_resources(struct device *dev) uma_resource(dev, 5, uma_memory_base >> 10, uma_memory_size >> 10); mmio_resource(dev, 6, tseg_memory_base >> 10, tseg_memory_size >> 10); uma_resource(dev, 7, cbmem_topk, delta_cbmem); + /* legacy VGA memory */ + mmio_resource(dev, 8, 640, 768 - 640); } static void mch_domain_set_resources(struct device *dev) From 23b874a374bd149ed4068d4e109364e8a5e8fd58 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 15 May 2020 16:25:47 -0700 Subject: [PATCH 299/405] device: Switch to resource allocator v4 by default treewide This change disables the old resource allocator by default and instead uses the new v4 resource allocator. Only the chipsets that explicitly select RESOURCE_ALLOCATOR_V3 will continue to use the old v3 resource allocator. Change-Id: I2ab9f1d612b5f193f058011a18b1d6373e09f788 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41445 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Mike Banon --- src/device/Kconfig | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index 801b040e08..55abfe89b2 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -779,10 +779,12 @@ config SOFTWARE_I2C config RESOURCE_ALLOCATOR_V3 bool - default y + default n help This config option enables resource allocator v3 which performs - top down allocation of resources in a single MMIO window. + top down allocation of resources in a single MMIO window. This is the + old resource allocator meant to be used only until the broken AMD + chipsets are fixed. DO NOT USE THIS FOR ANY NEW CHIPSETS! config RESOURCE_ALLOCATOR_V4 bool From fd7373809ed2e450f3fd7ea3ee8f79e8a3892d7d Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Wed, 20 May 2020 15:54:54 -0700 Subject: [PATCH 300/405] mb/google/volteer: fix some white space nits Convert spaces to tabs in volteer variant makefiles, and remove empty comment lines from file headers. BUG=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and verify volteer boots to kernel. Change-Id: I6c818c3adcc55ce89707efff6dd9a6bce512daa5 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/41587 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- .../google/volteer/variants/malefor/Makefile.inc | 6 +++--- .../google/volteer/variants/ripto/Makefile.inc | 5 +++-- .../google/volteer/variants/volteer/Makefile.inc | 13 ++++++------- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/volteer/variants/malefor/Makefile.inc b/src/mainboard/google/volteer/variants/malefor/Makefile.inc index e63868c80a..44beb90963 100644 --- a/src/mainboard/google/volteer/variants/malefor/Makefile.inc +++ b/src/mainboard/google/volteer/variants/malefor/Makefile.inc @@ -1,7 +1,7 @@ -## SPDX-License-Identifier: GPL-2.0-only +# SPDX-License-Identifier: GPL-2.0-only -## Memory Options -SPD_SOURCES = SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267 # 0b0000 +## Memory Options # DRAM ID # Part Num +SPD_SOURCES = SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267 # 0b0000 # MT53E512M32D2NP-046 romstage-y += memory.c diff --git a/src/mainboard/google/volteer/variants/ripto/Makefile.inc b/src/mainboard/google/volteer/variants/ripto/Makefile.inc index 826bab1db3..02b6f512c3 100644 --- a/src/mainboard/google/volteer/variants/ripto/Makefile.inc +++ b/src/mainboard/google/volteer/variants/ripto/Makefile.inc @@ -1,6 +1,7 @@ -## SPDX-License-Identifier: GPL-2.0-only +# SPDX-License-Identifier: GPL-2.0-only -SPD_SOURCES = SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267 # 0b0000 +## Memory Options # DRAM ID # Part Num +SPD_SOURCES = SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267 # 0b0000 # K4U6E3S4AA-MGCL bootblock-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/volteer/Makefile.inc b/src/mainboard/google/volteer/variants/volteer/Makefile.inc index 07dbef7b88..2cf0adc5ae 100644 --- a/src/mainboard/google/volteer/variants/volteer/Makefile.inc +++ b/src/mainboard/google/volteer/variants/volteer/Makefile.inc @@ -1,9 +1,8 @@ -## SPDX-License-Identifier: GPL-2.0-or-later -## +# SPDX-License-Identifier: GPL-2.0-or-later -## Memory Options # DRAM ID # Part Num -SPD_SOURCES = SPD_LPDDR4X_200b_1R_16Gb_DDP_4267 # 0b0000 # K4U6E3S4AA-MGCL - # H9HCNNNBKMMLXR-NEE +## Memory Options # DRAM ID # Part Num +SPD_SOURCES = SPD_LPDDR4X_200b_1R_16Gb_DDP_4267 # 0b0000 # K4U6E3S4AA-MGCL +# # 0b0000 # H9HCNNNBKMMLXR-NEE SPD_SOURCES += SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267 # 0b0001 # K4UBE3D4AA-MGCL -SPD_SOURCES += SPD_LPDDR4X_200b_2R_32Gb_QDP_4267 # 0b0010 # MT53E1G32D2NP-046 WT:A -SPD_SOURCES += SPD_LPDDR4X_200b_2R_64Gb_ODP_4267 # 0b0011 # H9HCNNNFAMMLXR-NEE +SPD_SOURCES += SPD_LPDDR4X_200b_2R_32Gb_QDP_4267 # 0b0010 # MT53E1G32D2NP-046 WT:A +SPD_SOURCES += SPD_LPDDR4X_200b_2R_64Gb_ODP_4267 # 0b0011 # H9HCNNNFAMMLXR-NEE From dd956cbb57a255f6050628242be524f0e56df9be Mon Sep 17 00:00:00 2001 From: Jairaj Arava Date: Thu, 21 May 2020 16:48:43 -0700 Subject: [PATCH 301/405] mb/google/deltaur: Update audio verb table for jack detection Additional verb changes are needed for Headset and Mic detection to work properly. BUG=b:155360937 TEST=Headset and Mic detection is working in the UI audio tray Change-Id: I184a05949f5522e929969156b72629be3d957e3f Signed-off-by: Jairaj Arava Reviewed-on: https://review.coreboot.org/c/coreboot/+/41642 Reviewed-by: EricR Lai Reviewed-by: Sathyanarayana Nujella Tested-by: build bot (Jenkins) --- .../variants/baseboard/include/baseboard/hda_verb.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/hda_verb.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/hda_verb.h index 671b0ed2c5..670bffd649 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/hda_verb.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/hda_verb.h @@ -45,10 +45,10 @@ const u32 cim_verb_data[] = { 0x01871E11, 0x01871F41, /* Pin widget 0x19 - MIC2 (Port-F) */ - 0x01971CF0, - 0x01971D11, - 0x01971E11, - 0x01971F41, + 0x01971C30, + 0x01971D10, + 0x01971Ea1, + 0x01971F02, /* Pin widget 0x1A - LINE1 (Port-C) */ 0x01A71CF0, 0x01A71D11, @@ -100,7 +100,7 @@ const u32 cim_verb_data[] = { 0x02050038, 0x02043901, 0x02050045, - 0x0204C489, + 0x02045089, /* H/W AGC setting-1 */ 0x02050016, 0x02040C50, From a1d0fb031c74853922d76d7341023efa2435562c Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Thu, 7 May 2020 13:26:57 +0900 Subject: [PATCH 302/405] mb/google/nightfury: Enable max98390 amp This change enables max98390 audio codec on nightfury. BUG=b:149443429 BRANCH=firmware-hatch-12672.B TEST=Built and checked audio function on nightfury Signed-off-by: Seunghwan Kim Change-Id: Ic9678583370cf5e41c87e35ba12f86572708fada Reviewed-on: https://review.coreboot.org/c/coreboot/+/41127 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/hatch/Kconfig.name | 2 ++ .../hatch/variants/nightfury/overridetree.cb | 24 ++++++++++++------- 2 files changed, 18 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 798438fd0e..195a4ea544 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -87,6 +87,8 @@ config BOARD_GOOGLE_NIGHTFURY bool "-> Nightfury" select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 + select CHROMEOS_DSM_CALIB + select DRIVERS_I2C_MAX98390 config BOARD_GOOGLE_PUFF bool "-> Puff" diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index 82f80a96f5..3c184eb139 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -249,19 +249,27 @@ chip soc/intel/cannonlake register "mic_amp_in_sel" = ""diff"" device i2c 0x1a on end end + chip drivers/i2c/max98390 + register "desc" = ""MAX98390 Speaker Amp 0"" + register "uid" = "0" + register "name" = ""MXW0"" + register "r0_calib_key" = ""dsm_calib_r0_0"" + register "temperature_calib_key" = ""dsm_calib_temp_0"" + device i2c 0x38 on end + end + chip drivers/i2c/max98390 + register "desc" = ""MAX98390 Speaker Amp 1"" + register "uid" = "1" + register "name" = ""MXW1"" + register "r0_calib_key" = ""dsm_calib_r0_1"" + register "temperature_calib_key" = ""dsm_calib_temp_1"" + device i2c 0x39 on end + end end # No PCIe WiFi device pci 1d.5 off end device pci 1a.0 on end #eMMC device pci 1e.3 off end # GSPI #1 - device pci 1f.3 on - chip drivers/generic/max98357a - register "hid" = ""MX98357A"" - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" - register "sdmode_delay" = "5" - device generic 0 on end - end - end # Intel HDA end # domain end From 879eba583b9be3df34532ea6a4ac67a7eadadbf7 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Fri, 22 Nov 2019 17:52:39 -0700 Subject: [PATCH 303/405] soc/amd/picasso: Use C00n for CPU ACPI string Match the path generated by AGESA. Add more PPKG packages. TEST=Verify that "\_PR.C00n" AE_NOT_FOUND errors go away BUG=b:145013057 Change-Id: I82587648d37c0be885991f2e5741d9f874d6a2eb Signed-off-by: Marshall Dawson Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/1937788 Reviewed-by: Martin Roth Commit-Queue: Martin Roth Tested-by: Martin Roth Reviewed-on: https://review.coreboot.org/c/coreboot/+/41635 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/amd/picasso/Kconfig | 2 +- src/soc/amd/picasso/acpi/cpu.asl | 44 +++++++++++++++++++++++--------- 2 files changed, 33 insertions(+), 13 deletions(-) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index ce1f0743f5..ddbc6c3137 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -176,7 +176,7 @@ config SMM_MODULE_STACK_SIZE config ACPI_CPU_STRING string - default "\\_PR.P%03d" + default "\\_PR.C%03d" config ACPI_BERT bool "Build ACPI BERT Table" diff --git a/src/soc/amd/picasso/acpi/cpu.asl b/src/soc/amd/picasso/acpi/cpu.asl index c40ebf0968..41d5bf5324 100644 --- a/src/soc/amd/picasso/acpi/cpu.asl +++ b/src/soc/amd/picasso/acpi/cpu.asl @@ -9,28 +9,48 @@ Method (PNOT) * Processor Object */ /* These devices are created at runtime */ -External (\_SB.P000, DeviceObj) -External (\_SB.P001, DeviceObj) -External (\_SB.P002, DeviceObj) -External (\_SB.P003, DeviceObj) -External (\_SB.P004, DeviceObj) -External (\_SB.P005, DeviceObj) -External (\_SB.P006, DeviceObj) -External (\_SB.P007, DeviceObj) +External (\_PR.C000, DeviceObj) +External (\_PR.C001, DeviceObj) +External (\_PR.C002, DeviceObj) +External (\_PR.C003, DeviceObj) +External (\_PR.C004, DeviceObj) +External (\_PR.C005, DeviceObj) +External (\_PR.C006, DeviceObj) +External (\_PR.C007, DeviceObj) /* Return a package containing enabled processor entries */ Method (PPKG) { - If (LGreaterEqual (\PCNT, 2)) { + If (LGreaterEqual (\PCNT, 8)) { Return (Package () { - \_SB.P000, - \_SB.P001 + \_PR.C000, + \_PR.C001, + \_PR.C002, + \_PR.C003, + \_PR.C004, + \_PR.C005, + \_PR.C006, + \_PR.C007 + }) + } ElseIf (LGreaterEqual (\PCNT, 4)) { + Return (Package () + { + \_PR.C000, + \_PR.C001, + \_PR.C002, + \_PR.C003 + }) + } ElseIf (LGreaterEqual (\PCNT, 2)) { + Return (Package () + { + \_PR.C000, + \_PR.C001 }) } Else { Return (Package () { - \_SB.P000 + \_PR.C000 }) } } From 0cbe320ac8711135657da36976f0055dc981ef24 Mon Sep 17 00:00:00 2001 From: Jan Dabros Date: Thu, 21 May 2020 14:21:49 +0200 Subject: [PATCH 304/405] submodules: Add new submodule 3rdparty/cmocka Cmocka unit testing framework is used for writing and building coreboot unit tests. This repo will be checked-in only when building some test targets. Signed-off-by: Jan Dabros Change-Id: I3cdfd32f5bba795d5834ebeae1afff0f7006a0d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41652 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg Reviewed-by: Patrick Georgi --- .gitmodules | 4 ++++ 3rdparty/cmocka | 1 + 2 files changed, 5 insertions(+) create mode 160000 3rdparty/cmocka diff --git a/.gitmodules b/.gitmodules index 010ab6b49d..9545bb624d 100644 --- a/.gitmodules +++ b/.gitmodules @@ -42,3 +42,7 @@ url = ../amd_blobs update = none ignore = dirty +[submodule "3rdparty/cmocka"] + path = 3rdparty/cmocka + url = ../cmocka.git + update = none diff --git a/3rdparty/cmocka b/3rdparty/cmocka new file mode 160000 index 0000000000..672c5cee79 --- /dev/null +++ b/3rdparty/cmocka @@ -0,0 +1 @@ +Subproject commit 672c5cee79eb412025c3dd8b034e611c1f119055 From 7f00dba33beb65e0380ed4b3194102083630b2f4 Mon Sep 17 00:00:00 2001 From: Jan Dabros Date: Fri, 22 May 2020 09:57:17 +0200 Subject: [PATCH 305/405] tests: Build Cmocka from source Relying on Cmocka packages, which are provided with different OS distributions, may introduce some problems with setup environments across developers (e.g. library version mismatch). Instead, let's build Cmocka from source code, which is now added to git submodules as 3rdparty/cmocka. Please note, that cmake tool is required for building Cmocka (thus also coreboot unit tests). Signed-off-by: Jan Dabros Change-Id: Ia947c5c60d5c58b76acebe4b614dd427ef995950 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41653 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg Reviewed-by: Patrick Georgi --- tests/Makefile.inc | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/tests/Makefile.inc b/tests/Makefile.inc index be32434e83..a6689a2d06 100644 --- a/tests/Makefile.inc +++ b/tests/Makefile.inc @@ -2,6 +2,12 @@ testsrc = $(top)/tests testobj = $(obj)/tests +cmockasrc = 3rdparty/cmocka +cmockaobj = $(cmockasrc)/build + +CMOCKA_LIB := $(cmockaobj)/src/libcmocka.so + +CMAKE:= cmake TEST_DEFAULT_CONFIG = $(top)/configs/config.emulation_qemu_x86_i440fx TEST_DOTCONFIG = $(testobj)/.config @@ -26,8 +32,14 @@ TEST_CFLAGS += -I$(dir $(TEST_KCONFIG_AUTOHEADER)) TEST_CFLAGS += -std=gnu11 -Os -ffunction-sections -fdata-sections -fno-builtin +# Checkout Cmocka repository +forgetthis:=$(shell git submodule update --init --checkout 3rdparty/cmocka) + +TEST_CFLAGS += -I$(cmockasrc)/include + # Link against Cmocka -TEST_LDFLAGS = -lcmocka -Wl,--gc-sections +TEST_LDFLAGS = -L$(cmockaobj)/src -lcmocka -Wl,-rpath=$(cmockaobj)/src +TEST_LDFLAGS += -Wl,--gc-sections # Extra attributes for unit tests, declared per test attributes:= srcs cflags mocks stage @@ -69,7 +81,7 @@ $($(1)-objs): $(obj)/$(1)/%.o: $$$$*.c $(TEST_KCONFIG_AUTOHEADER) -MT $$@ -c $$< -o $$@ $($(1)-bin): TEST_LDFLAGS+= $$(foreach mock,$$($(1)-mocks),-Wl,--wrap=$$(mock)) -$($(1)-bin): $($(1)-objs) +$($(1)-bin): $($(1)-objs) $(CMOCKA_LIB) $(HOSTCC) $$^ $($(1)-cflags) $$(TEST_LDFLAGS) -o $$@ endef @@ -90,6 +102,13 @@ $(foreach test, $(alltests), \ DEPENDENCIES += $(addsuffix .d,$(basename $(all-test-objs))) -include $(DEPENDENCIES) +# Build cmocka +$(CMOCKA_LIB): + echo "*** Building CMOCKA ***" + mkdir -p $(cmockaobj) + cd $(cmockaobj) && $(CMAKE) $(abspath $(cmockasrc)) + $(MAKE) -C $(cmockaobj) + # Kconfig targets $(TEST_DOTCONFIG): mkdir -p $(dir $@) From e184e39e2ed9ac3f76d2c4f2cc830e335a216e45 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Thu, 14 May 2020 10:23:19 -0600 Subject: [PATCH 306/405] drivers/intel/pmc_mux/con: Add new PMC MUX & CON chip drivers The Tiger Lake PMC device has a MUX device which is expected to be exposed in ACPI tables. The MUX device simply has a _HID and _DDN. The CON devices link the USB-2 and USB-3 port numbers (from SoC point of view) to the physical connector. They also have orientation options for the sideband (SBU) and USB High Speed signals (HSL), meaning that they can be fixed (i.e, another device besides the SoC controls the orientation, and effectively the SoC is following only CC1 or CC2 orientation), or they can follow the CC lines. BUG=b:151646486 TEST=Tested with next patch in series (see TEST line there) Change-Id: I8b5f275907601960410459aa669e257b80ff3dc2 Signed-off-by: Tim Wawrzynczak Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/40862 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/drivers/intel/pmc_mux/Kconfig | 7 ++ src/drivers/intel/pmc_mux/Makefile.inc | 2 + src/drivers/intel/pmc_mux/chip.h | 9 +++ src/drivers/intel/pmc_mux/con/Makefile.inc | 1 + src/drivers/intel/pmc_mux/con/chip.h | 26 +++++++ src/drivers/intel/pmc_mux/con/con.c | 83 ++++++++++++++++++++++ src/drivers/intel/pmc_mux/mux.c | 42 +++++++++++ 7 files changed, 170 insertions(+) create mode 100644 src/drivers/intel/pmc_mux/Kconfig create mode 100644 src/drivers/intel/pmc_mux/Makefile.inc create mode 100644 src/drivers/intel/pmc_mux/chip.h create mode 100644 src/drivers/intel/pmc_mux/con/Makefile.inc create mode 100644 src/drivers/intel/pmc_mux/con/chip.h create mode 100644 src/drivers/intel/pmc_mux/con/con.c create mode 100644 src/drivers/intel/pmc_mux/mux.c diff --git a/src/drivers/intel/pmc_mux/Kconfig b/src/drivers/intel/pmc_mux/Kconfig new file mode 100644 index 0000000000..24eb1a19d3 --- /dev/null +++ b/src/drivers/intel/pmc_mux/Kconfig @@ -0,0 +1,7 @@ +config DRIVERS_INTEL_PMC + bool + default n + depends on HAVE_ACPI_TABLES + help + When enabled, driver/intel/pmc_mux will add support for mux + configuration of USB Type-C ports via the SoC's muxes. diff --git a/src/drivers/intel/pmc_mux/Makefile.inc b/src/drivers/intel/pmc_mux/Makefile.inc new file mode 100644 index 0000000000..f27f01444b --- /dev/null +++ b/src/drivers/intel/pmc_mux/Makefile.inc @@ -0,0 +1,2 @@ +subdirs-y += con +ramstage-$(CONFIG_DRIVERS_INTEL_PMC) += mux.c diff --git a/src/drivers/intel/pmc_mux/chip.h b/src/drivers/intel/pmc_mux/chip.h new file mode 100644 index 0000000000..dcca2a3ecc --- /dev/null +++ b/src/drivers/intel/pmc_mux/chip.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __DRIVERS_INTEL_PMC_MUX_H__ +#define __DRIVERS_INTEL_PMC_MUX_H__ + +struct drivers_intel_pmc_mux_config { +}; + +#endif /* __DRIVERS_INTEL_PMC_MUX_H__ */ diff --git a/src/drivers/intel/pmc_mux/con/Makefile.inc b/src/drivers/intel/pmc_mux/con/Makefile.inc new file mode 100644 index 0000000000..213e8fc7ec --- /dev/null +++ b/src/drivers/intel/pmc_mux/con/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_INTEL_PMC) += con.c diff --git a/src/drivers/intel/pmc_mux/con/chip.h b/src/drivers/intel/pmc_mux/con/chip.h new file mode 100644 index 0000000000..02d018a2e9 --- /dev/null +++ b/src/drivers/intel/pmc_mux/con/chip.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __DRIVERS_INTEL_PMC_MUX_CON_H__ +#define __DRIVERS_INTEL_PMC_MUX_CON_H__ + +enum typec_orientation { + /* The orientation of the signal follows the orientation of the CC lines. */ + TYPEC_ORIENTATION_FOLLOW_CC = 0, + /* The orientation of the signal is fixed to follow CC1 */ + TYPEC_ORIENTATION_NORMAL, + /* The orientation of the signal is fixed to follow CC2 */ + TYPEC_ORIENTATION_REVERSE, +}; + +struct drivers_intel_pmc_mux_con_config { + /* 1-based port numbers (from SoC point of view) */ + int usb2_port_number; + /* 1-based port numbers (from SoC point of view) */ + int usb3_port_number; + /* Orientation of the sideband signals (SBU) */ + enum typec_orientation sbu_orientation; + /* Orientation of the High Speed lines */ + enum typec_orientation hsl_orientation; +}; + +#endif /* __DRIVERS_INTEL_PMC_MUX_CON_H__ */ diff --git a/src/drivers/intel/pmc_mux/con/con.c b/src/drivers/intel/pmc_mux/con/con.c new file mode 100644 index 0000000000..08c38e8875 --- /dev/null +++ b/src/drivers/intel/pmc_mux/con/con.c @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include "chip.h" + +static const char *con_acpi_name(const struct device *dev) +{ + static char name[5]; + snprintf(name, sizeof(name), "CON%1X", dev->path.generic.id); + return name; +} + +static const char *orientation_to_str(enum typec_orientation ori) +{ + switch (ori) { + case TYPEC_ORIENTATION_NORMAL: + return "normal"; + case TYPEC_ORIENTATION_REVERSE: + return "reverse"; + case TYPEC_ORIENTATION_FOLLOW_CC: /* Intentional fallthrough */ + default: + return ""; + } +} + +static void con_fill_ssdt(const struct device *dev) +{ + struct drivers_intel_pmc_mux_con_config *config = dev->chip_info; + struct acpi_dp *dsd; + + if (!dev->enabled) + return; + + /* Reference the existing scope and write CONx device */ + acpigen_write_scope(acpi_device_scope(dev)); + acpigen_write_device(acpi_device_name(dev)); + + acpigen_write_name_integer("_ADR", dev->path.generic.id); + + /* _DSD, Device-Specific Data */ + dsd = acpi_dp_new_table("_DSD"); + acpi_dp_add_integer(dsd, "usb2-port-number", config->usb2_port_number); + acpi_dp_add_integer(dsd, "usb3-port-number", config->usb3_port_number); + + /* + * The kernel assumes that these Type-C signals (SBUs and HSLs) follow the CC lines, + * unless they are explicitly called out otherwise. + */ + if (config->sbu_orientation != TYPEC_ORIENTATION_FOLLOW_CC) + acpi_dp_add_string(dsd, "sbu-orientation", + orientation_to_str(config->sbu_orientation)); + + if (config->hsl_orientation != TYPEC_ORIENTATION_FOLLOW_CC) + acpi_dp_add_string(dsd, "hsl-orientation", + orientation_to_str(config->hsl_orientation)); + + acpi_dp_write(dsd); + + acpigen_pop_len(); /* CONx Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name, + dev_path(dev)); +} + +static struct device_operations con_dev_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = con_acpi_name, + .acpi_fill_ssdt = con_fill_ssdt, +}; + +static void con_enable(struct device *dev) +{ + dev->ops = &con_dev_ops; +} + +struct chip_operations drivers_intel_pmc_mux_con_ops = { + CHIP_NAME("Intel PMC MUX CON Driver") + .enable_dev = con_enable, +}; diff --git a/src/drivers/intel/pmc_mux/mux.c b/src/drivers/intel/pmc_mux/mux.c new file mode 100644 index 0000000000..29ed1a9603 --- /dev/null +++ b/src/drivers/intel/pmc_mux/mux.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include "chip.h" + +#define TGL_PMC_MUX_HID "INTC105C" + +static const char *mux_acpi_name(const struct device *dev) +{ + return "MUX"; +} + +static void mux_fill_ssdt(const struct device *dev) +{ + acpigen_write_scope(acpi_device_scope(dev)); + acpigen_write_device(acpi_device_name(dev)); + + acpigen_write_name_string("_HID", TGL_PMC_MUX_HID); + acpigen_write_name_string("_DDN", dev->chip_ops->name); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static struct device_operations mux_dev_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = mux_acpi_name, + .acpi_fill_ssdt = mux_fill_ssdt, + .scan_bus = scan_static_bus, +}; + +static void mux_enable(struct device *dev) +{ + dev->ops = &mux_dev_ops; +} + +struct chip_operations drivers_intel_pmc_mux_ops = { + CHIP_NAME("Intel PMC MUX Driver") + .enable_dev = mux_enable, +}; From b77b446ca8cbca1a5e56570b94e24a57b9889554 Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Mon, 27 Apr 2020 20:26:53 +0530 Subject: [PATCH 307/405] vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2114 The FSP-M/S headers added are generated as per FSP v2114. Following UPDs are deprecated - IedSize - EnableC6Dram Following UPDs are added - TurboMode - PavpEnable - CnviMode - CnviBtCore - PchFivrExtV1p05RailEnabledStates - PchFivrExtVnnRailSxEnabledStates - PchFivrVccinAuxRetToLowCurModeVolTranTime - PchFivrVccinAuxRetToHighCurModeVolTranTime - PchFivrVccinAuxLowToHighCurModeVolTranTime - PchLockDownGlobalSmi - PchLockDownBiosInterface - PchLockDownBiosLock BUG=b:155054804 BRANCH=None TEST=Build and boot JSLRVP Cq-Depend: TBD Change-Id: Id9355a1eccfbdc1e9a07b37cb3d8e3de125054d9 Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/41240 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Aamir Bohra Reviewed-by: Maulik V Vaghela --- .../intel/fsp/fsp2_0/jasperlake/FspmUpd.h | 138 ++++++++--------- .../intel/fsp/fsp2_0/jasperlake/FspsUpd.h | 142 ++++++++++++++---- 2 files changed, 169 insertions(+), 111 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h index 4018ed0c68..7bcd6c09f0 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h @@ -136,35 +136,29 @@ typedef struct { **/ UINT8 Reserved2[6]; -/** Offset 0x009C - Intel Enhanced Debug - Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied - 0 : Disable, 0x400000 : Enable -**/ - UINT32 IedSize; - -/** Offset 0x00A0 - Tseg Size +/** Offset 0x009C - Tseg Size Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build 0x0400000:4MB, 0x01000000:16MB **/ UINT32 TsegSize; -/** Offset 0x00A4 - Reserved +/** Offset 0x00A0 - Reserved **/ UINT8 Reserved3[6]; -/** Offset 0x00AA - Enable SMBus +/** Offset 0x00A6 - Enable SMBus Enable/disable SMBus controller. $EN_DIS **/ UINT8 SmbusEnable; -/** Offset 0x00AB - Spd Address Tabl +/** Offset 0x00A7 - Spd Address Tabl Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used if SPD Address is 00 **/ UINT8 SpdAddressTable[4]; -/** Offset 0x00AF - Platform Debug Consent +/** Offset 0x00AB - Platform Debug Consent To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. Enabling this BIOS option may alter the default value of other debug-related BIOS options.\Manual: Do not use Platform Debug Consent to override other debug-relevant @@ -175,42 +169,42 @@ typedef struct { **/ UINT8 PlatformDebugConsent; -/** Offset 0x00B0 - Reserved +/** Offset 0x00AC - Reserved **/ UINT8 Reserved4[2]; -/** Offset 0x00B2 - Enable DCI ModPHY Pwoer Gate +/** Offset 0x00AE - Enable DCI ModPHY Pwoer Gate Enable ModPHY Pwoer Gate when DCI is enabled $EN_DIS **/ UINT8 DciModphyPg; -/** Offset 0x00B3 - Reserved +/** Offset 0x00AF - Reserved **/ UINT8 Reserved5; -/** Offset 0x00B4 - PCH Trace Hub Mode +/** Offset 0x00B0 - PCH Trace Hub Mode Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode **/ UINT8 PchTraceHubMode; -/** Offset 0x00B5 - Reserved +/** Offset 0x00B1 - Reserved **/ UINT8 Reserved6[47]; -/** Offset 0x00E4 - Disable VT-d +/** Offset 0x00E0 - Disable VT-d 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) $EN_DIS **/ UINT8 VtdDisable; -/** Offset 0x00E5 - Reserved +/** Offset 0x00E1 - Reserved **/ UINT8 Reserved7[3]; -/** Offset 0x00E8 - Internal Graphics Pre-allocated Memory +/** Offset 0x00E4 - Internal Graphics Pre-allocated Memory Size of memory preallocated for internal graphics. 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, @@ -218,147 +212,135 @@ typedef struct { **/ UINT8 IgdDvmt50PreAlloc; -/** Offset 0x00E9 - Internal Graphics +/** Offset 0x00E5 - Internal Graphics Enable/disable internal graphics. $EN_DIS **/ UINT8 InternalGfx; -/** Offset 0x00EA - Reserved +/** Offset 0x00E6 - Reserved **/ UINT8 Reserved8; -/** Offset 0x00EB - Board Type +/** Offset 0x00E7 - Board Type MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile Halo, 7=UP Server 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server **/ UINT8 UserBd; -/** Offset 0x00EC - Reserved +/** Offset 0x00E8 - Reserved **/ UINT8 Reserved9[2]; -/** Offset 0x00EE - SA GV +/** Offset 0x00EA - SA GV System Agent dynamic frequency support and when enabled memory will be training at three different frequencies. 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled **/ UINT8 SaGv; -/** Offset 0x00EF - Reserved +/** Offset 0x00EB - Reserved **/ UINT8 Reserved10[5]; -/** Offset 0x00F4 - Rank Margin Tool +/** Offset 0x00F0 - Rank Margin Tool Enable/disable Rank Margin Tool. $EN_DIS **/ UINT8 RMT; -/** Offset 0x00F5 - Reserved +/** Offset 0x00F1 - Reserved **/ UINT8 Reserved11[24]; -/** Offset 0x010D - Memory Reference Clock +/** Offset 0x0109 - Memory Reference Clock 100MHz, 133MHz. 0:133MHz, 1:100MHz **/ UINT8 RefClk; -/** Offset 0x010E - Reserved +/** Offset 0x010A - Reserved **/ UINT8 Reserved12[26]; -/** Offset 0x0128 - Enable Intel HD Audio (Azalia) +/** Offset 0x0124 - Enable Intel HD Audio (Azalia) 0: Disable, 1: Enable (Default) Azalia controller $EN_DIS **/ UINT8 PchHdaEnable; -/** Offset 0x0129 - CPU Trace Hub Mode +/** Offset 0x0125 - CPU Trace Hub Mode Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. 0: Disable, 1:Target Debugger Mode, 2:Host Debugger Mode **/ UINT8 CpuTraceHubMode; -/** Offset 0x012A - Reserved +/** Offset 0x0126 - Reserved **/ UINT8 Reserved13[98]; -/** Offset 0x018C - Program GPIOs for LFP on DDI port-A device +/** Offset 0x0188 - Program GPIOs for LFP on DDI port-A device 0=Disabled,1(Default)=eDP, 2=MIPI DSI 0:Disabled, 1:eDP, 2:MIPI DSI **/ UINT8 DdiPortAConfig; -/** Offset 0x018D - Reserved +/** Offset 0x0189 - Reserved **/ UINT8 Reserved14[2]; -/** Offset 0x018F - Enable or disable HPD of DDI port B +/** Offset 0x018B - Enable or disable HPD of DDI port B 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortBHpd; -/** Offset 0x0190 - Enable or disable HPD of DDI port C +/** Offset 0x018C - Enable or disable HPD of DDI port C 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPortCHpd; -/** Offset 0x0191 - Reserved +/** Offset 0x018D - Reserved **/ UINT8 Reserved15[5]; -/** Offset 0x0196 - Enable or disable DDC of DDI port B +/** Offset 0x0192 - Enable or disable DDC of DDI port B 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortBDdc; -/** Offset 0x0197 - Enable or disable DDC of DDI port C +/** Offset 0x0193 - Enable or disable DDC of DDI port C 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPortCDdc; -/** Offset 0x0198 - Reserved +/** Offset 0x0194 - Reserved **/ - UINT8 Reserved16[165]; + UINT8 Reserved16[176]; -/** Offset 0x023D - C6DRAM power gating feature - This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM - power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating - feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature. - $EN_DIS -**/ - UINT8 EnableC6Dram; - -/** Offset 0x023E - Reserved -**/ - UINT8 Reserved17[7]; - -/** Offset 0x0245 - CPU ratio value +/** Offset 0x0244 - CPU ratio value CPU ratio value. Valid Range 0 to 63 **/ UINT8 CpuRatio; -/** Offset 0x0246 - Reserved +/** Offset 0x0245 - Reserved **/ - UINT8 Reserved18[4]; + UINT8 Reserved17[4]; -/** Offset 0x024A - Enable or Disable VMX +/** Offset 0x0249 - Enable or Disable VMX Enable or Disable VMX; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 VmxEnable; -/** Offset 0x024B - Reserved +/** Offset 0x024A - Reserved **/ - UINT8 Reserved19[31]; + UINT8 Reserved18[32]; /** Offset 0x026A - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable @@ -368,7 +350,7 @@ typedef struct { /** Offset 0x026B - Reserved **/ - UINT8 Reserved20[5]; + UINT8 Reserved19[5]; /** Offset 0x0270 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -382,7 +364,7 @@ typedef struct { /** Offset 0x0278 - Reserved **/ - UINT8 Reserved21[543]; + UINT8 Reserved20[543]; /** Offset 0x0497 - Usage type for ClkSrc 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use @@ -397,7 +379,7 @@ typedef struct { /** Offset 0x04B7 - Reserved **/ - UINT8 Reserved22[5]; + UINT8 Reserved21[5]; /** Offset 0x04BC - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 @@ -420,7 +402,7 @@ typedef struct { /** Offset 0x04C2 - Reserved **/ - UINT8 Reserved23[22]; + UINT8 Reserved22[22]; /** Offset 0x04D8 - Early Command Training Enables/Disable Early Command Training @@ -430,7 +412,7 @@ typedef struct { /** Offset 0x04D9 - Reserved **/ - UINT8 Reserved24[2]; + UINT8 Reserved23[2]; /** Offset 0x04DB - Read MPR Training Enables/Disable Read MPR Training @@ -440,7 +422,7 @@ typedef struct { /** Offset 0x04DC - Reserved **/ - UINT8 Reserved25[7]; + UINT8 Reserved24[7]; /** Offset 0x04E3 - Dimm ODT Training Enables/Disable Dimm ODT Training @@ -456,7 +438,7 @@ typedef struct { /** Offset 0x04E5 - Reserved **/ - UINT8 Reserved26; + UINT8 Reserved25; /** Offset 0x04E6 - Write Slew Rate Training Enables/Disable Write Slew Rate Training @@ -484,7 +466,7 @@ typedef struct { /** Offset 0x04EA - Reserved **/ - UINT8 Reserved27[3]; + UINT8 Reserved26[3]; /** Offset 0x04ED - Read Voltage Centering 2D Enables/Disable Read Voltage Centering 2D @@ -494,7 +476,7 @@ typedef struct { /** Offset 0x04EE - Reserved **/ - UINT8 Reserved28[3]; + UINT8 Reserved27[3]; /** Offset 0x04F1 - Turn Around Timing Training Enables/Disable Turn Around Timing Training @@ -504,7 +486,7 @@ typedef struct { /** Offset 0x04F2 - Reserved **/ - UINT8 Reserved29[6]; + UINT8 Reserved28[6]; /** Offset 0x04F8 - Receive Enable Centering 1D Enables/Disable Receive Enable Centering 1D @@ -520,7 +502,7 @@ typedef struct { /** Offset 0x04FA - Reserved **/ - UINT8 Reserved30[60]; + UINT8 Reserved29[60]; /** Offset 0x0536 - RAPL PL 1 WindowX Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) @@ -534,7 +516,7 @@ typedef struct { /** Offset 0x0538 - Reserved **/ - UINT8 Reserved31[2]; + UINT8 Reserved30[2]; /** Offset 0x053A - RAPL PL 1 Power range[0;2^14-1]= [2047.875;0]in W, (224= Def) @@ -543,7 +525,7 @@ typedef struct { /** Offset 0x053C - Reserved **/ - UINT8 Reserved32[68]; + UINT8 Reserved31[68]; /** Offset 0x0580 - LpDdrDqDqsReTraining Enables/Disable LpDdrDqDqsReTraining @@ -553,7 +535,7 @@ typedef struct { /** Offset 0x0581 - Reserved **/ - UINT8 Reserved33[172]; + UINT8 Reserved32[172]; /** Offset 0x062D - Enable HD Audio Link Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. @@ -563,7 +545,7 @@ typedef struct { /** Offset 0x062E - Reserved **/ - UINT8 Reserved34[3]; + UINT8 Reserved33[3]; /** Offset 0x0631 - Enable HD Audio DMIC_N Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. @@ -572,7 +554,7 @@ typedef struct { /** Offset 0x0633 - Reserved **/ - UINT8 Reserved35[17]; + UINT8 Reserved34[17]; /** Offset 0x0644 - Enable HD Audio DSP Enable/disable HD Audio DSP feature. @@ -582,7 +564,7 @@ typedef struct { /** Offset 0x0645 - Reserved **/ - UINT8 Reserved36[11]; + UINT8 Reserved35[11]; /** Offset 0x0650 - Enable HD Audio SSP0 Link Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 @@ -596,7 +578,7 @@ typedef struct { /** Offset 0x065A - Reserved **/ - UINT8 Reserved37[7]; + UINT8 Reserved36[7]; /** Offset 0x0661 - Skip MBP HOB Test, 0: disable, 1: enable, Enable/Disable MOB HOB. @@ -606,7 +588,7 @@ typedef struct { /** Offset 0x0662 - Reserved **/ - UINT8 Reserved38[22]; + UINT8 Reserved37[22]; } FSP_M_CONFIG; /** Fsp M UPD Configuration diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h index 15e78c2c75..6ec68c414c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h @@ -172,7 +172,13 @@ typedef struct { /** Offset 0x0075 - Reserved **/ - UINT8 Reserved2[136]; + UINT8 Reserved2[135]; + +/** Offset 0x00FC - Turbo Mode + Enable/Disable Turbo mode. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 TurboMode; /** Offset 0x00FD - Enable SATA SALP Support Enable/disable SATA Aggressive Link Power Management. @@ -355,7 +361,16 @@ typedef struct { /** Offset 0x0301 - Reserved **/ - UINT8 Reserved8[83]; + UINT8 Reserved8[81]; + +/** Offset 0x0352 - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states + Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 +**/ + UINT8 PchFivrExtV1p05RailEnabledStates; + +/** Offset 0x0353 - Reserved +**/ + UINT8 Reserved9; /** Offset 0x0354 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) @@ -369,7 +384,7 @@ typedef struct { /** Offset 0x0357 - Reserved **/ - UINT8 Reserved9; + UINT8 Reserved10; /** Offset 0x0358 - External Vnn Voltage Value that will be used in S0ix/Sx states Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) @@ -381,9 +396,11 @@ typedef struct { **/ UINT8 PchFivrExtVnnRailIccMax; -/** Offset 0x035B - Reserved +/** Offset 0x035B - Mask to enable the usage of external Vnn VR rail in Sx states + Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in + Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5 **/ - UINT8 Reserved10; + UINT8 PchFivrExtVnnRailSxEnabledStates; /** Offset 0x035C - External Vnn Voltage Value that will be used in Sx states Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments @@ -397,9 +414,23 @@ typedef struct { **/ UINT8 PchFivrExtVnnRailSxIccMax; -/** Offset 0x035F - Reserved +/** Offset 0x035F - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to low current mode voltage. **/ - UINT8 Reserved11[3]; + UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime; + +/** Offset 0x0360 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to retention mode voltage. +**/ + UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime; + +/** Offset 0x0361 - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to retention mode voltage. +**/ + UINT8 PchFivrVccinAuxRetToLowCurModeVolTranTime; /** Offset 0x0362 - Transition time in microseconds from Off (0V) to High Current Mode Voltage This field has 1us resolution. When value is 0 Transition to 0V is disabled. @@ -408,7 +439,20 @@ typedef struct { /** Offset 0x0364 - Reserved **/ - UINT8 Reserved12[22]; + UINT8 Reserved11[20]; + +/** Offset 0x0378 - CNVi Configuration + This option allows for automatic detection of Connectivity Solution. [Auto Detection] + assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. + 0:Disable, 1:Auto +**/ + UINT8 CnviMode; + +/** Offset 0x0379 - CNVi BT Core + Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtCore; /** Offset 0x037A - CNVi BT Audio Offload Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE @@ -418,7 +462,7 @@ typedef struct { /** Offset 0x037B - Reserved **/ - UINT8 Reserved13; + UINT8 Reserved12; /** Offset 0x037C - CNVi RF_RESET pin muxing Select CNVi RF_RESET# pin depending on board routing. ICP-N: GPP_H12 = 0x2746E40C(default) @@ -434,7 +478,13 @@ typedef struct { /** Offset 0x0384 - Reserved **/ - UINT8 Reserved14[146]; + UINT8 Reserved13[145]; + +/** Offset 0x0415 - Enable/Disable PavpEnable + Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable + $EN_DIS +**/ + UINT8 PavpEnable; /** Offset 0x0416 - CdClock Frequency selection 0: (Default) Auto (Max based on reference clock frequency), 1: 172.8 Mhz, 2: 180 @@ -446,14 +496,15 @@ typedef struct { UINT8 CdClock; /** Offset 0x0417 - Enable/Disable PeiGraphicsPeimInit - Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit + Enable: FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB. + Disable(Default): FSP will NOT initialize the framebuffer. $EN_DIS **/ UINT8 PeiGraphicsPeimInit; /** Offset 0x0418 - Reserved **/ - UINT8 Reserved15[152]; + UINT8 Reserved14[152]; /** Offset 0x04B0 - Skip Multi-Processor Initialization When this is skipped, boot loader must initialize processors before SilicionInit @@ -464,16 +515,29 @@ typedef struct { /** Offset 0x04B1 - Reserved **/ - UINT8 Reserved16[11]; + UINT8 Reserved15[11]; /** Offset 0x04BC - CpuMpPpi - Pointer for CpuMpPpi + Optional pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. + If not NULL, FSP will use the boot loader's implementation of multiprocessing. + See section 5.1.4 of the FSP Integration Guide for more details. **/ UINT32 CpuMpPpi; /** Offset 0x04C0 - Reserved **/ - UINT8 Reserved17[86]; + UINT8 Reserved16[83]; + +/** Offset 0x0513 - Enable LOCKDOWN BIOS LOCK + Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region + protection. + $EN_DIS +**/ + UINT8 PchLockDownBiosLock; + +/** Offset 0x0514 - Reserved +**/ + UINT8 Reserved17[2]; /** Offset 0x0516 - RTC Cmos Memory Lock Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper @@ -565,19 +629,19 @@ typedef struct { /** Offset 0x07FC - Reserved **/ - UINT8 Reserved24[511]; + UINT8 Reserved24[487]; -/** Offset 0x09FB - Enable/Disable IGFX PmSupport +/** Offset 0x09E3 - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport $EN_DIS **/ UINT8 PmSupport; -/** Offset 0x09FC - Reserved +/** Offset 0x09E4 - Reserved **/ UINT8 Reserved25[32]; -/** Offset 0x0A1C - TCC Activation Offset +/** Offset 0x0A04 - TCC Activation Offset TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For SKL Y SKU, the recommended default for this policy is @@ -585,50 +649,62 @@ typedef struct { **/ UINT8 TccActivationOffset; -/** Offset 0x0A1D - Reserved +/** Offset 0x0A05 - Reserved **/ UINT8 Reserved26[34]; -/** Offset 0x0A3F - Enable or Disable CPU power states (C-states) +/** Offset 0x0A27 - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable $EN_DIS **/ UINT8 Cx; -/** Offset 0x0A40 - Reserved +/** Offset 0x0A28 - Reserved **/ UINT8 Reserved27[74]; -/** Offset 0x0A8A - Platform Power Pmax +/** Offset 0x0A72 - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. Range 0-1024 Watts. Value of 800 = 100W **/ UINT16 PsysPmax; -/** Offset 0x0A8C - Reserved +/** Offset 0x0A74 - Reserved **/ - UINT8 Reserved28[116]; + UINT8 Reserved28[115]; -/** Offset 0x0B00 - End of Post message +/** Offset 0x0AE7 - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved **/ UINT8 EndOfPostMessage; -/** Offset 0x0B01 - Reserved +/** Offset 0x0AE8 - Reserved **/ - UINT8 Reserved29[3]; + UINT8 Reserved29; -/** Offset 0x0B04 - Unlock all GPIO pads +/** Offset 0x0AE9 - Enable LOCKDOWN SMI + Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. + $EN_DIS +**/ + UINT8 PchLockDownGlobalSmi; + +/** Offset 0x0AEA - Enable LOCKDOWN BIOS Interface + Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. + $EN_DIS +**/ + UINT8 PchLockDownBiosInterface; + +/** Offset 0x0AEB - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose. $EN_DIS **/ UINT8 PchUnlockGpioPads; -/** Offset 0x0B05 - Reserved +/** Offset 0x0AEC - Reserved **/ - UINT8 Reserved30[451]; + UINT8 Reserved30[452]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -643,11 +719,11 @@ typedef struct { **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0CC8 +/** Offset 0x0CB0 **/ UINT8 UnusedUpdSpace36[6]; -/** Offset 0x0CCE +/** Offset 0x0CB6 **/ UINT16 UpdTerminator; } FSPS_UPD; From 828ca06cdbedacb41f73dc70bf18262031f7ad90 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 20 May 2020 02:34:59 +0200 Subject: [PATCH 308/405] soc/amd/picasso: rewrite soc_util This adds proper RV2 silicon and Dali SKU detection using both CPUID information and some bits from silicon_id in the Picasso misc data HOB that FSP-M stores in memory. BUG=b:153779573 Change-Id: I589be3bdac4b94785e6ecacf55235be4ad5673d9 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/41630 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/picasso/include/soc/soc_util.h | 26 ++- src/soc/amd/picasso/soc_util.c | 179 +++++++++++++++++++-- 2 files changed, 188 insertions(+), 17 deletions(-) diff --git a/src/soc/amd/picasso/include/soc/soc_util.h b/src/soc/amd/picasso/include/soc/soc_util.h index 6515761a8a..6399e42bb9 100644 --- a/src/soc/amd/picasso/include/soc/soc_util.h +++ b/src/soc/amd/picasso/include/soc/soc_util.h @@ -11,12 +11,34 @@ enum socket_type { SOCKET_FT5 = 3, }; -void print_socket_type(void); +enum silicon_type { + SILICON_RV1, + SILICON_PCO, + SILICON_RV2, + SILICON_UNKNOWN, +}; +enum soc_type { + SOC_PICASSO, + SOC_DALI, + SOC_POLLOCK, + SOC_UNKNOWN, +}; + +enum socket_type get_socket_type(void); +enum silicon_type get_silicon_type(void); +enum soc_type get_soc_type(void); + +void print_socket_type(void); +void print_silicon_type(void); +void print_soc_type(void); + +/* functions to determine the connectivity feature set */ bool soc_is_pollock(void); bool soc_is_dali(void); bool soc_is_picasso(void); + +/* function to determine the iGPU type */ bool soc_is_raven2(void); -bool soc_is_zen_plus(void); #endif /* __PICASSO_SOC_UTIL_H__ */ diff --git a/src/soc/amd/picasso/soc_util.c b/src/soc/amd/picasso/soc_util.c index 89aa0a40ff..70cc578ec9 100644 --- a/src/soc/amd/picasso/soc_util.c +++ b/src/soc/amd/picasso/soc_util.c @@ -2,6 +2,9 @@ #include #include +#include +#include +#include #include #include #include @@ -9,7 +12,7 @@ #define SOCKET_TYPE_SHIFT 28 #define SOCKET_TYPSE_MASK (0xf << SOCKET_TYPE_SHIFT) -static enum socket_type get_socket_type(void) +enum socket_type get_socket_type(void) { uint32_t ebx = cpuid_ebx(0x80000001); ebx = (ebx & SOCKET_TYPSE_MASK) >> SOCKET_TYPE_SHIFT; @@ -37,33 +40,179 @@ void print_socket_type(void) } } -bool soc_is_pollock(void) +/* returns 0 in case or errors */ +static uint32_t get_internal_silicon_type(void) { - return soc_is_zen_plus() && get_socket_type() == SOCKET_FT5; + static uint32_t silicon_type; + size_t hob_size = 0; + const struct picasso_misc_data *hob; + + if (silicon_type) + return silicon_type; + + hob = fsp_find_extension_hob_by_guid(PICASSO_MISC_DATA_HOB_GUID.b, &hob_size); + + if (hob == NULL || hob_size == 0) { + printk(BIOS_ERR, "Couldn't find Picasso misc data HOB.\n"); + return 0; + } + + if (hob->version != PICASSO_MISC_DATA_VERSION) { + printk(BIOS_ERR, "Unexpected Picasso misc data HOB version.\n"); + return 0; + } + + silicon_type = hob->silicon_id; + + printk(BIOS_DEBUG, "Silicon ID = 0x%x\n", silicon_type); + + return silicon_type; } -/* - * TODO: This detection works for the Dali SKUs used in Chrome-devices, but fails for other - * Dali SKUs, since other Dali SKUs have a Zen+ CPUID and not a Raven2 one. - */ -bool soc_is_dali(void) +#define SILICON_IS_MYSTERY_MEAT (1 << 31) +#define SILICON_IS_RV2 (1 << 30) + +static bool is_rv2_silicon(void) { - return soc_is_raven2() && get_socket_type() == SOCKET_FP5; + return get_internal_silicon_type() & SILICON_IS_RV2; } -bool soc_is_picasso(void) +static bool is_mystery_silicon(void) { - return soc_is_zen_plus() && get_socket_type() == SOCKET_FP5; + return get_internal_silicon_type() & SILICON_IS_MYSTERY_MEAT; } -bool soc_is_raven2(void) +static bool is_fam17_1x(void) +{ + /* mask lower model number nibble and stepping */ + return cpuid_eax(1) >> 8 == PICASSO_CPUID >> 8; +} + +static bool is_fam17_11(void) +{ + /* only mask stepping */ + return cpuid_eax(1) >> 4 == RAVEN1_CPUID >> 4; +} + +static bool is_fam17_18(void) +{ + /* only mask stepping */ + return cpuid_eax(1) >> 4 == PICASSO_CPUID >> 4; +} + +static bool is_fam17_2x(void) { /* mask lower model number nibble and stepping */ return cpuid_eax(1) >> 8 == RAVEN2_CPUID >> 8; } -bool soc_is_zen_plus(void) +static bool is_fam17_20(void) { - /* mask lower model number nibble and stepping */ - return cpuid_eax(1) >> 8 == PICASSO_CPUID >> 8; + /* only mask stepping */ + return cpuid_eax(1) >> 4 == RAVEN2_A1_CPUID >> 4; +} + +enum silicon_type get_silicon_type(void) +{ + /* + * RV2 is fam17_20, but might return a fam17_1x CPUID in the is_mystery_silicon() case. + * is_rv2_silicon() has the correct information, but requires the HOB to be present. + */ + if (is_fam17_20() || is_rv2_silicon()) + return SILICON_RV2; + + if (is_fam17_18() && !is_rv2_silicon()) + return SILICON_PCO; + + if (is_fam17_11() && !is_rv2_silicon()) + return SILICON_RV1; + + /* some cases might still be missing */ + + return SILICON_UNKNOWN; +} + +enum soc_type get_soc_type(void) +{ + switch (get_socket_type()) { + case SOCKET_FP5: + if (is_fam17_1x() && !is_mystery_silicon()) + return SOC_PICASSO; + + if (is_fam17_2x() || (is_fam17_1x() && is_mystery_silicon())) + return SOC_DALI; + + break; + case SOCKET_FT5: + /* add is_fam17_20() CPUID sanity check here? */ + return SOC_POLLOCK; + break; + case SOCKET_AM4: + /* AM4 SoC type detection logic not implemented */ + break; + } + + return SOC_UNKNOWN; +} + +void print_silicon_type(void) +{ + const enum silicon_type silicon = get_silicon_type(); + + printk(BIOS_INFO, "Silicon type: "); + + switch (silicon) { + case SILICON_RV1: + printk(BIOS_INFO, "RV1\n"); + break; + case SILICON_PCO: + printk(BIOS_INFO, "PCO\n"); + break; + case SILICON_RV2: + printk(BIOS_INFO, "RV2\n"); + break; + default: + printk(BIOS_INFO, "unknown\n"); + } +} + +void print_soc_type(void) +{ + const enum soc_type soc = get_soc_type(); + + printk(BIOS_INFO, "SoC type: "); + + switch (soc) { + case SOC_PICASSO: + printk(BIOS_INFO, "Picasso\n"); + break; + case SOC_DALI: + printk(BIOS_INFO, "Dali\n"); + break; + case SOC_POLLOCK: + printk(BIOS_INFO, "Pollock\n"); + break; + default: + printk(BIOS_INFO, "unknown\n"); + } +} + +bool soc_is_pollock(void) +{ + return get_soc_type() == SOC_POLLOCK; +} + +bool soc_is_dali(void) +{ + return get_soc_type() == SOC_DALI; +} + +bool soc_is_picasso(void) +{ + return get_soc_type() == SOC_PICASSO; +} + +bool soc_is_raven2(void) +{ + return get_silicon_type() == SILICON_RV2; } From ab114c96064422f92f8932f5d9fd837b259e93d6 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 22 May 2020 02:40:40 +0200 Subject: [PATCH 309/405] soc/amd/picasso: add and use CPUIDs for older steppings Change-Id: Ibe768ef7cd714c17fd5a296d9a3e5f963ae0ef01 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/41641 Reviewed-by: Raul Rangel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/cpu.c | 7 ++++--- src/soc/amd/picasso/include/soc/cpu.h | 8 +++++--- src/soc/amd/picasso/soc_util.c | 8 ++++---- 3 files changed, 13 insertions(+), 10 deletions(-) diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 88626971c5..55f9014c8f 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -115,9 +115,10 @@ static struct device_operations cpu_dev_ops = { }; static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x810f80 }, - { X86_VENDOR_AMD, PICASSO_CPUID }, - { X86_VENDOR_AMD, RAVEN2_CPUID }, + { X86_VENDOR_AMD, PICASSO_B0_CPUID }, + { X86_VENDOR_AMD, PICASSO_B1_CPUID }, + { X86_VENDOR_AMD, RAVEN2_A0_CPUID }, + { X86_VENDOR_AMD, RAVEN2_A1_CPUID }, { 0, 0 }, }; diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index a377c1ca42..d413c7293f 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -11,8 +11,10 @@ void picasso_init_cpus(struct device *dev); int get_cpu_count(void); void check_mca(void); -#define RAVEN1_CPUID 0x00810f10 -#define PICASSO_CPUID 0x00810f81 -#define RAVEN2_CPUID 0x00820f01 +#define RAVEN1_B0_CPUID 0x00810f10 +#define PICASSO_B0_CPUID 0x00810f80 +#define PICASSO_B1_CPUID 0x00810f81 +#define RAVEN2_A0_CPUID 0x00820f00 +#define RAVEN2_A1_CPUID 0x00820f01 #endif /* __PICASSO_CPU_H__ */ diff --git a/src/soc/amd/picasso/soc_util.c b/src/soc/amd/picasso/soc_util.c index 70cc578ec9..9c256ae703 100644 --- a/src/soc/amd/picasso/soc_util.c +++ b/src/soc/amd/picasso/soc_util.c @@ -85,25 +85,25 @@ static bool is_mystery_silicon(void) static bool is_fam17_1x(void) { /* mask lower model number nibble and stepping */ - return cpuid_eax(1) >> 8 == PICASSO_CPUID >> 8; + return cpuid_eax(1) >> 8 == PICASSO_B1_CPUID >> 8; } static bool is_fam17_11(void) { /* only mask stepping */ - return cpuid_eax(1) >> 4 == RAVEN1_CPUID >> 4; + return cpuid_eax(1) >> 4 == RAVEN1_B0_CPUID >> 4; } static bool is_fam17_18(void) { /* only mask stepping */ - return cpuid_eax(1) >> 4 == PICASSO_CPUID >> 4; + return cpuid_eax(1) >> 4 == PICASSO_B1_CPUID >> 4; } static bool is_fam17_2x(void) { /* mask lower model number nibble and stepping */ - return cpuid_eax(1) >> 8 == RAVEN2_CPUID >> 8; + return cpuid_eax(1) >> 8 == RAVEN2_A1_CPUID >> 8; } static bool is_fam17_20(void) From 8288555eadfe2a8d66f7ef79b2d9be9fef4e433e Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Tue, 26 May 2020 13:06:11 -0600 Subject: [PATCH 310/405] 3rdparty/amd_blobs: Update to include APCB_magic.bin BUG=b:157140753 TEST=Built zork/trembyle and boot to OS. Signed-off-by: Raul E Rangel Change-Id: I30a27a149ee7f368f45fdf5d4a081127f15e7629 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41736 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Felix Held Reviewed-by: Furquan Shaikh --- 3rdparty/amd_blobs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 0e4b8285d9..0ac1af437d 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 0e4b8285d95cdfd1facd3acccf848fd06edf6038 +Subproject commit 0ac1af437d2cc461b94bd2cdaa195e86dd481d37 From 2b76ee0179179836b665f36e3f20f3dddf07e31c Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Tue, 26 May 2020 14:47:05 -0600 Subject: [PATCH 311/405] Makefile: Add missing APCB_EDIT_TOOL variable Apparently I missed adding this variable definition. BUG=b:157140753 TEST=Build APCBs with clean tree :) Fixes: cbaa835f211 ("soc/amd/picasso/Makefile: Use apcb_tool to generate APCBs from SPDs") Signed-off-by: Raul E Rangel Change-Id: Ia9055ed3507996cbf78687a97599aab3b0b39d6f Reviewed-on: https://review.coreboot.org/c/coreboot/+/41738 Reviewed-by: Felix Held Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index 210e9cf6c6..86467a66a8 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -562,6 +562,8 @@ $(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c @printf " HOSTCC $(subst $(obj)/,,$(@))\n" $(HOSTCC) $(HOSTCFLAGS) -DCONFIG_ROM_SIZE=$(CONFIG_ROM_SIZE) -o $@ $< +APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py + CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage FUTILITY?=$(objutil)/futility/futility From 55c735a417e75387e988553f9f66d27e19f2364b Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Thu, 27 Feb 2020 16:06:15 -0700 Subject: [PATCH 312/405] ec/google/chromeec/acpi/superio: Add PS/2 Mouse ACPI entry The PNP ID Means: PNP0F13 PS/2 Port for PS/2-style Mice BUG=b:145575366 BRANCH=none TEST=Verified mouse was initialized Signed-off-by: Raul E Rangel Change-Id: I2a4f071ad54730ea75f75ebf1633a4a08f7f2dd0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2080664 Tested-by: Martin Roth Reviewed-by: Martin Roth Commit-Queue: Martin Roth Reviewed-on: https://review.coreboot.org/c/coreboot/+/41639 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/ec/google/chromeec/acpi/superio.asl | 27 +++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/src/ec/google/chromeec/acpi/superio.asl b/src/ec/google/chromeec/acpi/superio.asl index cc91aba8e0..05310be800 100644 --- a/src/ec/google/chromeec/acpi/superio.asl +++ b/src/ec/google/chromeec/acpi/superio.asl @@ -157,3 +157,30 @@ Scope (\_SB.PCI0) } } #endif + +#ifdef SIO_EC_ENABLE_PS2M +Scope (\_SB.PCI0) +{ + Device (PS2M) // Mouse + { + Name (_UID, 0) + Name (_HID, "GOOG0015") + Name (_CID, Package() { EISAID("PNP0F13") } ) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) +#ifdef SIO_EC_PS2M_IRQ + SIO_EC_PS2M_IRQ +#else + IRQ (Edge, ActiveHigh, Exclusive) {12} +#endif + }) + } +} +#endif From 563e614bcde9627b764445dfe2fe7cfca7e99c96 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 26 May 2020 12:04:35 -0700 Subject: [PATCH 313/405] resource_allocator_v4: Fix size of I/O hole at 0x3b0 Addressing comment from CB:41443 that was received after the change landed. memranges_create_hole() takes size as the last parameter. So, the I/O hole created at 0x3b0 needs to set size as 0x3df - 0x3b0 + 1 as 0x3df is the upper limit of that hole. Change-Id: I08fca283436924427e12c6c69edced7e51db42a9 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41737 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Angel Pons Reviewed-by: Aaron Durbin --- src/device/resource_allocator_v4.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c index ece7150b32..b65fc8bf37 100644 --- a/src/device/resource_allocator_v4.c +++ b/src/device/resource_allocator_v4.c @@ -330,7 +330,7 @@ static void constrain_domain_resources(const struct device *domain, struct memra * Don't allow allocations in the VGA I/O range. PCI has special cases for * that. */ - memranges_create_hole(ranges, 0x3b0, 0x3df); + memranges_create_hole(ranges, 0x3b0, 0x3df - 0x3b0 + 1); /* * Resource allocator no longer supports the legacy behavior where I/O resource From 02e76c2e4dfb1a60187e8b3cacafe347f0030388 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Tue, 26 May 2020 11:34:05 -0600 Subject: [PATCH 314/405] soc/amd/picasso/Makefile: Change APCB_magic.bin location The APCB_magic.bin lives in amd_blobs, not blobs. BUG=b:157140753 TEST=Boot trembyle to OS Signed-off-by: Raul E Rangel Change-Id: Ib082a8e7fc631ca7145b0b77e49ea0cbf99dff41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41734 Reviewed-by: Furquan Shaikh Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index e1416bcddd..05d46eacfe 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -289,7 +289,7 @@ $(obj)/APCB_%.bin: $(MAINBOARD_BLOBS_DIR)/APCB_%.bin cp $< $@ # APCB binary with magic numbers to be replaced by apcb_edit tool -APCB_MAGIC_BLOB:=$(MAINBOARD_BLOBS_DIR)/APCB_magic.bin +APCB_MAGIC_BLOB:=$(FIRMWARE_LOCATE)/APCB_magic.bin $(obj)/APCB_empty.bin: $(APCB_MAGIC_BLOB) $(APCB_EDIT_TOOL) $(APCB_EDIT_TOOL) \ From 030d21473894b0e1d4a19dd74cfb42f5c5a3db7b Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Tue, 26 May 2020 15:11:47 -0600 Subject: [PATCH 315/405] util/apcb: Use python3 for apcb_edit.py The code was written on a workstation that has python pointing to python3. BUG=b:157140753 TEST=Built trembyle and was able to boot to the OS Signed-off-by: Raul E Rangel Change-Id: I181d87aad1ffb10e12f8ffd7513318f6d6bcbc3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/41739 Reviewed-by: Rob Barnes Reviewed-by: Felix Held Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- util/apcb/apcb_edit.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/apcb/apcb_edit.py b/util/apcb/apcb_edit.py index 4a7e683ebe..e5dd0cd586 100755 --- a/util/apcb/apcb_edit.py +++ b/util/apcb/apcb_edit.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python +#!/usr/bin/env python3 # Script for editing APCB binaries, such as injecting SPDs and GPIO # configurations. From 5c5049e2832d2a6869a075e44966e0525dae5fab Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Thu, 23 Apr 2020 06:43:44 -0600 Subject: [PATCH 316/405] soc/amd/picasso: Add generic SMU service request Add a new feature that allows messages to be sent to the SMU. The offsets of the PCI config index/data indirect registers have been documented for prior generation devices. The index/data pair is used to access a command register, a response, and six argument values. BUG=b:153264473 TEST=Verify service can be used to take the system into S3 Change-Id: Ide431aa976cb2f8bdc248cb08aa0724a9596ac5a Signed-off-by: Marshall Dawson Signed-off-by: Felix Held Reviewed-on: https://chromium-review.googlesource.com/2161796 Reviewed-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41625 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Raul Rangel --- src/soc/amd/picasso/Makefile.inc | 1 + src/soc/amd/picasso/include/soc/smu.h | 40 ++++++++++++ src/soc/amd/picasso/smu.c | 90 +++++++++++++++++++++++++++ 3 files changed, 131 insertions(+) create mode 100644 src/soc/amd/picasso/include/soc/smu.h create mode 100644 src/soc/amd/picasso/smu.c diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 05d46eacfe..d0046eaf10 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -72,6 +72,7 @@ smm-y += tsc_freq.c smm-$(CONFIG_DEBUG_SMI) += uart.c smm-y += gpio.c smm-y += psp.c +smm-y += smu.c smm-y += config.c CPPFLAGS_common += -I$(src)/soc/amd/picasso diff --git a/src/soc/amd/picasso/include/soc/smu.h b/src/soc/amd/picasso/include/soc/smu.h new file mode 100644 index 0000000000..128f4c4ed7 --- /dev/null +++ b/src/soc/amd/picasso/include/soc/smu.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __PICASSO_SMU_H__ +#define __PICASSO_SMU_H__ + +#include + +/* SMU registers accessed indirectly using an index/data pair in D0F00 config space */ +#define SMU_INDEX_ADDR 0xb8 /* 32 bit */ +#define SMU_DATA_ADDR 0xbc /* 32 bit */ + +#define REG_ADDR_MESG_ID 0x3b10528 +#define REG_ADDR_MESG_RESP 0x3b10564 +#define REG_ADDR_MESG_ARGS_BASE 0x0b10998 + +/* Argument 0-5 indexed locations are contiguous */ +#define SMU_NUM_ARGS 6 +#define REG_ADDR_MESG_ARG(x) (REG_ADDR_MESG_ARGS_BASE + ((x) * sizeof(uint32_t))) + +enum smu_message_id { + SMC_MSG_S3ENTRY = 0x0c, +}; + +struct smu_payload { + uint32_t msg[SMU_NUM_ARGS]; +}; + +/* + * Send a message and bi-directional payload to the SMU. SMU response, if + * any, is returned via arg. Returns 0 if success or -1 on failure. + */ +enum cb_err send_smu_message(enum smu_message_id id, struct smu_payload *arg); + +/* + * Request the SMU put system into S3, S4, or S5. On entry, SlpTyp determines + * S-State and SlpTypeEn is clear. Function does not return if successful. + */ +void smu_sx_entry(void); + +#endif /* __PICASSO_SMU_H__ */ diff --git a/src/soc/amd/picasso/smu.c b/src/soc/amd/picasso/smu.c new file mode 100644 index 0000000000..cfe2240021 --- /dev/null +++ b/src/soc/amd/picasso/smu.c @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +static uint32_t smu_read32(uint32_t reg) +{ + pci_write_config32(SOC_GNB_DEV, SMU_INDEX_ADDR, reg); + return pci_read_config32(SOC_GNB_DEV, SMU_DATA_ADDR); +} + +static void smu_write32(uint32_t reg, uint32_t val) +{ + pci_write_config32(SOC_GNB_DEV, SMU_INDEX_ADDR, reg); + pci_write_config32(SOC_GNB_DEV, SMU_DATA_ADDR, val); +} + +#define SMU_MESG_RESP_TIMEOUT 0x00 +#define SMU_MESG_RESP_OK 0x01 + +/* returns SMU_MESG_RESP_OK, SMU_MESG_RESP_TIMEOUT or a negative number */ +static int32_t smu_poll_response(void) +{ + struct stopwatch sw; + const long timeout_ms = 10 * MSECS_PER_SEC; + int32_t result; + + stopwatch_init_msecs_expire(&sw, timeout_ms); + + do { + result = smu_read32(REG_ADDR_MESG_RESP); + if (result) { + printk(BIOS_SPEW, "SMU command consumed %ld msecs\n", + stopwatch_duration_usecs(&sw)); + return result; + } + } while (!stopwatch_expired(&sw)); + + printk(BIOS_ERR, "Error: timeout sending SMU message\n"); + return SMU_MESG_RESP_TIMEOUT; +} + +/* + * Send a message and bi-directional payload to the SMU. SMU response, if any, is returned via + * arg. + */ +enum cb_err send_smu_message(enum smu_message_id id, struct smu_payload *arg) +{ + size_t i; + + /* wait until SMU can process a new request; don't care if an old request failed */ + if (smu_poll_response() == SMU_MESG_RESP_TIMEOUT) + return CB_ERR; + + /* clear response register */ + smu_write32(REG_ADDR_MESG_RESP, 0); + + /* populate arguments */ + for (i = 0 ; i < SMU_NUM_ARGS ; i++) + smu_write32(REG_ADDR_MESG_ARG(i), arg->msg[i]); + + /* send message to SMU */ + smu_write32(REG_ADDR_MESG_ID, id); + + /* wait until SMU has processed the message and check if it was successful */ + if (smu_poll_response() != SMU_MESG_RESP_OK) + return CB_ERR; + + /* copy returned values */ + for (i = 0 ; i < SMU_NUM_ARGS ; i++) + arg->msg[i] = smu_read32(REG_ADDR_MESG_ARG(i)); + + return CB_SUCCESS; +} + +/* + * Request the SMU to put system into S3, S4, or S5. On entry, SlpTyp determines S-State and + * SlpTypeEn is clear. Function does not return if successful. + */ +void smu_sx_entry(void) +{ + struct smu_payload msg = { 0 }; /* Unused for SMC_MSG_S3ENTRY */ + + printk(BIOS_DEBUG, "SMU: Put system into S3/S4/S5\n"); + send_smu_message(SMC_MSG_S3ENTRY, &msg); +} From 4dc4cb6b5c835ca947356a4d4e8c10228966bebc Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Fri, 3 Apr 2020 12:07:00 -0600 Subject: [PATCH 317/405] soc/amd/picasso: Use SMU to put system into S3 Send a message to the SMU to turn off the system power. SMU will take the proper final steps based on PmControl[SlpTyp]. BUG=b:153264473 TEST=verify system can enter S3 Change-Id: I3c0d98110c12963aa6fef5d176fd9acaa7ed9f26 Signed-off-by: Marshall Dawson Reviewed-on: https://chromium-review.googlesource.com/2140471 Reviewed-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41626 Reviewed-by: Raul Rangel Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/smihandler.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index d7a46d3461..992dc2b55a 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -15,6 +15,7 @@ #include #include #include +#include /* bits in smm_io_trap */ #define SMM_IO_TRAP_PORT_OFFSET 16 @@ -209,11 +210,9 @@ static void sb_slp_typ_handler(void) psp_notify_sx_info(slp_typ); - /* - * An IO cycle is required to trigger the STPCLK/STPGNT - * handshake when the Pm1 write is reissued. - */ - outw(pm1cnt | SLP_EN, pm_read16(PM1_CNT_BLK)); + smu_sx_entry(); /* Leave SlpTypeEn clear, SMU will set */ + printk(BIOS_ERR, "Error: System did not go to sleep\n"); + hlt(); } } From f2a0be235cdf72caff549a1cfe0b986bdd99e93b Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 26 Apr 2020 17:01:25 +0200 Subject: [PATCH 318/405] drivers/intel/gma: Move IGD OpRegion to CBMEM It never was in GNVS, it never belonged among the ACPI tables. Having it in CBMEM, makes it easy to look the location up on resume, and saves us additional boilerplate. TEST=Booted Linux on Lenovo/X201s, confirmed ASLS is set and intel_backlight + acpi_video synchronize, both before and after suspend. Change-Id: I5fdd6634e4a671a85b1df8bc9815296ff42edf29 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/40724 Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/drivers/intel/gma/opregion.c | 32 ++++++----- src/drivers/intel/gma/opregion.h | 6 +-- src/northbridge/intel/gm45/gma.c | 46 +--------------- src/northbridge/intel/haswell/gma.c | 44 +-------------- src/northbridge/intel/i945/gma.c | 46 +--------------- src/northbridge/intel/ironlake/gma.c | 45 +--------------- src/northbridge/intel/pineview/gma.c | 45 +--------------- src/northbridge/intel/sandybridge/gma.c | 44 +-------------- src/northbridge/intel/x4x/gma.c | 51 +----------------- src/soc/intel/apollolake/graphics.c | 19 +------ src/soc/intel/baytrail/acpi/globalnvs.asl | 42 --------------- src/soc/intel/baytrail/gfx.c | 47 +--------------- src/soc/intel/baytrail/include/soc/nvs.h | 35 +----------- src/soc/intel/braswell/acpi.c | 22 -------- src/soc/intel/braswell/acpi/globalnvs.asl | 42 --------------- src/soc/intel/braswell/gfx.c | 17 +----- src/soc/intel/braswell/include/soc/nvs.h | 35 +----------- src/soc/intel/broadwell/acpi/globalnvs.asl | 42 --------------- src/soc/intel/broadwell/igd.c | 45 +--------------- src/soc/intel/broadwell/include/soc/nvs.h | 35 +----------- src/soc/intel/cannonlake/graphics.c | 18 +------ .../intel/common/block/graphics/graphics.c | 1 - .../block/include/intelblocks/graphics.h | 14 ----- src/soc/intel/icelake/graphics.c | 19 +------ src/soc/intel/jasperlake/graphics.c | 19 +------ src/soc/intel/skylake/acpi/globalnvs.asl | 42 --------------- src/soc/intel/skylake/graphics.c | 54 +------------------ src/soc/intel/skylake/include/soc/nvs.h | 37 +------------ src/soc/intel/tigerlake/graphics.c | 19 +------ .../intel/bd82x6x/acpi/globalnvs.asl | 41 +------------- src/southbridge/intel/bd82x6x/nvs.h | 33 +----------- src/southbridge/intel/i82801dx/nvs.h | 22 +------- .../intel/i82801gx/acpi/globalnvs.asl | 27 ---------- src/southbridge/intel/i82801gx/nvs.h | 22 +------- .../intel/i82801ix/acpi/globalnvs.asl | 27 ---------- src/southbridge/intel/i82801ix/nvs.h | 22 +------- .../intel/i82801jx/acpi/globalnvs.asl | 27 ---------- src/southbridge/intel/i82801jx/nvs.h | 22 +------- src/southbridge/intel/ibexpeak/nvs.h | 34 +----------- .../intel/lynxpoint/acpi/globalnvs.asl | 42 --------------- src/southbridge/intel/lynxpoint/nvs.h | 35 +----------- 41 files changed, 65 insertions(+), 1252 deletions(-) diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 566f35101d..7682af199b 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -57,7 +57,7 @@ void *locate_vbt(size_t *vbt_size) } /* Write ASLS PCI register and prepare SWSCI register. */ -void intel_gma_opregion_register(uintptr_t opregion) +static void intel_gma_opregion_register(uintptr_t opregion) { struct device *igd; u16 reg16; @@ -94,17 +94,16 @@ void intel_gma_opregion_register(uintptr_t opregion) } /* Restore ASLS register on S3 resume and prepare SWSCI. */ -void intel_gma_restore_opregion(void) +static enum cb_err intel_gma_restore_opregion(void) { - if (acpi_is_wakeup_s3()) { - const void *const gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - uintptr_t aslb; - - if (gnvs && (aslb = gma_get_gnvs_aslb(gnvs))) - intel_gma_opregion_register(aslb); - else - printk(BIOS_ERR, "Error: GNVS or ASLB not set.\n"); + const igd_opregion_t *const opregion = cbmem_find(CBMEM_ID_IGD_OPREGION); + if (!opregion) { + printk(BIOS_ERR, "GMA: Failed to find IGD OpRegion.\n"); + return CB_ERR; } + /* Write ASLS PCI register and prepare SWSCI register. */ + intel_gma_opregion_register((uintptr_t)opregion); + return CB_SUCCESS; } static enum cb_err vbt_validate(struct region_device *rdev) @@ -224,14 +223,17 @@ static enum cb_err locate_vbt_vbios_cbfs(struct region_device *rdev) } /* Initialize IGD OpRegion, called from ACPI code and OS drivers */ -enum cb_err -intel_gma_init_igd_opregion(igd_opregion_t *opregion) +enum cb_err intel_gma_init_igd_opregion(void) { + igd_opregion_t *opregion; struct region_device rdev; optionrom_vbt_t *vbt = NULL; optionrom_vbt_t *ext_vbt; bool found = false; + if (acpi_is_wakeup_s3()) + return intel_gma_restore_opregion(); + /* Search for vbt.bin in CBFS. */ if (locate_vbt_cbfs(&rdev) == CB_SUCCESS && vbt_validate(&rdev) == CB_SUCCESS) { @@ -273,6 +275,12 @@ intel_gma_init_igd_opregion(igd_opregion_t *opregion) return CB_ERR; } + opregion = cbmem_add(CBMEM_ID_IGD_OPREGION, sizeof(*opregion)); + if (!opregion) { + printk(BIOS_ERR, "GMA: Failed to add IGD OpRegion to CBMEM.\n"); + return CB_ERR; + } + memset(opregion, 0, sizeof(igd_opregion_t)); memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, diff --git a/src/drivers/intel/gma/opregion.h b/src/drivers/intel/gma/opregion.h index 079d08fa4e..879017b6a2 100644 --- a/src/drivers/intel/gma/opregion.h +++ b/src/drivers/intel/gma/opregion.h @@ -231,11 +231,7 @@ typedef struct { u8 coreblock_biossignon[155]; } __packed optionrom_vbt_t; -void intel_gma_opregion_register(uintptr_t opregion); -void intel_gma_restore_opregion(void); -uintptr_t gma_get_gnvs_aslb(const void *gnvs); -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb); -enum cb_err intel_gma_init_igd_opregion(igd_opregion_t *opregion); +enum cb_err intel_gma_init_igd_opregion(void); /* * Returns the CBFS filename of the VBT blob. diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 0c97b64b39..e9bd722da9 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -11,8 +11,6 @@ #include #include #include -#include -#include #include #include "drivers/intel/gma/i915_reg.h" @@ -31,19 +29,6 @@ void gtt_write(u32 reg, u32 data) write32(res2mmio(gtt_res, reg, 0), data); } -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static u32 get_cdclk(struct device *const dev) { const u16 cdclk_sel = @@ -165,6 +150,8 @@ static void gma_func0_init(struct device *dev) struct edid edid_lvds; const struct northbridge_intel_gm45_config *const conf = dev->chip_info; + intel_gma_init_igd_opregion(); + /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; @@ -203,8 +190,6 @@ static void gma_func0_init(struct device *dev) generate_fake_intel_oprom(&conf->gfx, dev, "$VBT CANTIGA"); } } - - intel_gma_restore_opregion(); } static void gma_generate_ssdt(const struct device *device) @@ -214,32 +199,6 @@ static void gma_generate_ssdt(const struct device *device) drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } -static unsigned long -gma_write_acpi_tables(const struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; -} - static const char *gma_acpi_name(const struct device *dev) { return "GFX0"; @@ -257,7 +216,6 @@ static struct device_operations gma_func0_ops = { .init = gma_func0_init, .ops_pci = &gma_pci_ops, .acpi_name = gma_acpi_name, - .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 0caa64fe11..ae9e25704d 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include @@ -16,7 +15,6 @@ #include #include #include -#include #include #include @@ -209,19 +207,6 @@ int gtt_poll(u32 reg, u32 mask, u32 value) return 0; } -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void power_well_enable(void) { gtt_write(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_ENABLE); @@ -475,6 +460,8 @@ static void gma_func0_init(struct device *dev) int lightup_ok = 0; u32 reg32; + intel_gma_init_igd_opregion(); + /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; @@ -509,7 +496,6 @@ static void gma_func0_init(struct device *dev) gma_pm_init_post_vbios(dev); gma_enable_swsci(); - intel_gma_restore_opregion(); } static void gma_generate_ssdt(const struct device *dev) @@ -519,31 +505,6 @@ static void gma_generate_ssdt(const struct device *dev) drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } -static unsigned long gma_write_acpi_tables(const struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; -} - static struct pci_operations gma_pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; @@ -555,7 +516,6 @@ static struct device_operations gma_func0_ops = { .init = gma_func0_init, .acpi_fill_ssdt = gma_generate_ssdt, .ops_pci = &gma_pci_ops, - .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = { diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index dfdd2fa34e..181aee56e7 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -18,8 +18,6 @@ #include #include #include -#include -#include #include #include "i945.h" @@ -43,19 +41,6 @@ #define DEFAULT_BLC_PWM 180 -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static int gtt_setup(u8 *mmiobase) { unsigned long PGETBL_save; @@ -677,6 +662,8 @@ static void gma_func0_init(struct device *dev) { u32 reg32; + intel_gma_init_igd_opregion(); + /* Unconditionally reset graphics */ pci_write_config8(dev, GDRST, 1); udelay(50); @@ -707,8 +694,6 @@ static void gma_func0_init(struct device *dev) /* PCI Init, will run VBIOS */ pci_dev_init(dev); } - - intel_gma_restore_opregion(); } /* This doesn't reclaim stolen UMA memory, but IGD could still @@ -763,32 +748,6 @@ static void gma_func0_read_resources(struct device *dev) pci_dev_read_resources(dev); } -static unsigned long -gma_write_acpi_tables(const struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; -} - static const char *gma_acpi_name(const struct device *dev) { return "GFX0"; @@ -807,7 +766,6 @@ static struct device_operations gma_func0_ops = { .disable = gma_func0_disable, .ops_pci = &gma_pci_ops, .acpi_name = gma_acpi_name, - .write_acpi_tables = gma_write_acpi_tables, }; diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c index 1836d84253..6de64fb065 100644 --- a/src/northbridge/intel/ironlake/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -13,9 +13,7 @@ #include #include #include -#include #include -#include #include #include "chip.h" @@ -64,19 +62,6 @@ int gtt_poll(u32 reg, u32 mask, u32 value) return 0; } -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void gma_pm_init_post_vbios(struct device *dev) { struct northbridge_intel_ironlake_config *conf = dev->chip_info; @@ -152,6 +137,8 @@ static void gma_func0_init(struct device *dev) { u32 reg32; + intel_gma_init_igd_opregion(); + /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; @@ -180,7 +167,6 @@ static void gma_func0_init(struct device *dev) gma_pm_init_post_vbios(dev); gma_enable_swsci(); - intel_gma_restore_opregion(); } static void gma_read_resources(struct device *dev) @@ -209,32 +195,6 @@ static void gma_generate_ssdt(const struct device *device) drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } -static unsigned long -gma_write_acpi_tables(const struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; -} - static struct pci_operations gma_pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; @@ -246,7 +206,6 @@ static struct device_operations gma_func0_ops = { .acpi_fill_ssdt = gma_generate_ssdt, .init = gma_func0_init, .ops_pci = &gma_pci_ops, - .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = { diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index b0ecfe1d64..e2d0d18bad 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -12,8 +12,6 @@ #include #include #include -#include -#include #include #include #include @@ -42,19 +40,6 @@ static struct resource *gtt_res = NULL; static struct resource *mmio_res = NULL; -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static int gtt_setup(u8 *mmiobase) { u32 gttbase; @@ -235,6 +220,8 @@ static void gma_func0_init(struct device *dev) { u32 reg32; + intel_gma_init_igd_opregion(); + /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; @@ -273,33 +260,6 @@ static void gma_func0_init(struct device *dev) /* Linux relies on VBT for panel info. */ generate_fake_intel_oprom(&conf->gfx, dev, "$VBT PINEVIEW"); } - - intel_gma_restore_opregion(); -} - -static unsigned long gma_write_acpi_tables(const struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; } static const char *gma_acpi_name(const struct device *dev) @@ -318,7 +278,6 @@ static struct device_operations gma_func0_ops = { .init = gma_func0_init, .ops_pci = &gma_pci_ops, .acpi_name = gma_acpi_name, - .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 9ff68d1e7d..82e43fc575 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -10,10 +10,8 @@ #include #include #include -#include #include #include -#include #include #include "chip.h" @@ -302,19 +300,6 @@ int gtt_poll(u32 reg, u32 mask, u32 value) return 0; } -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void gma_pm_init_pre_vbios(struct device *dev) { u32 reg32; @@ -602,6 +587,8 @@ static void gma_func0_init(struct device *dev) { u32 reg32; + intel_gma_init_igd_opregion(); + /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; @@ -636,7 +623,6 @@ static void gma_func0_init(struct device *dev) } gma_enable_swsci(); - intel_gma_restore_opregion(); } static void gma_generate_ssdt(const struct device *device) @@ -646,31 +632,6 @@ static void gma_generate_ssdt(const struct device *device) drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } -static unsigned long gma_write_acpi_tables(const struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; -} - static const char *gma_acpi_name(const struct device *dev) { return "GFX0"; @@ -702,7 +663,6 @@ static struct device_operations gma_func0_ops = { .disable = gma_func0_disable, .ops_pci = &gma_pci_ops, .acpi_name = gma_acpi_name, - .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = { diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 0067d71bbc..004960fd8c 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -19,31 +18,14 @@ #include "drivers/intel/gma/i915_reg.h" #include "x4x.h" -#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) -#include -#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX) -#include -#endif - #define BASE_FREQUENCY 96000 -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void gma_func0_init(struct device *dev) { u32 reg32; + intel_gma_init_igd_opregion(); + /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; @@ -65,8 +47,6 @@ static void gma_func0_init(struct device *dev) } else { pci_dev_init(dev); } - - intel_gma_restore_opregion(); } static void gma_func0_disable(struct device *dev) @@ -86,32 +66,6 @@ static void gma_generate_ssdt(const struct device *device) drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } -static unsigned long -gma_write_acpi_tables(const struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; -} - static const char *gma_acpi_name(const struct device *dev) { return "GFX0"; @@ -130,7 +84,6 @@ static struct device_operations gma_func0_ops = { .ops_pci = &gma_pci_ops, .disable = gma_func0_disable, .acpi_name = gma_acpi_name, - .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index a5e361e7f1..2070baf14c 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -20,6 +20,8 @@ uintptr_t fsp_soc_get_igd_bar(void) void graphics_soc_init(struct device *const dev) { + intel_gma_init_igd_opregion(); + if (CONFIG(RUN_FSP_GOP)) return; @@ -38,20 +40,3 @@ void graphics_soc_init(struct device *const dev) pci_dev_init(dev); } } - -uintptr_t graphics_soc_write_acpi_opregion(const struct device *device, - uintptr_t current, struct acpi_rsdp *rsdp) -{ - igd_opregion_t *opregion; - - printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = (igd_opregion_t *)current; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - /* FIXME: Add platform specific mailbox initialization */ - - current += sizeof(igd_opregion_t); - return acpi_align_current(current); -} diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index 699c8b087e..6cb68ba7f7 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -53,48 +53,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) TOLM, 32, // 0x34 - Top of Low Memory CBMC, 32, // 0x38 - coreboot mem console pointer - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD Power conservation feature - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 - - ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) - PAVP, 8, // 0xe9 - IGD PAVP data - Offset (0xeb), - OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native PCIe support - PLFL, 8, // 0xed - platform flavor - BREV, 8, // 0xee - board revision - DPBM, 8, // 0xef - digital port b mode - DPCM, 8, // 0xf0 - digital port c mode - DPDM, 8, // 0xf1 - digital port d mode - ALFP, 8, // 0xf2 - active lfp - IMON, 8, // 0xf3 - current graphics turbo imon value - MMIO, 8, // 0xf4 - 64bit mmio support - /* ChromeOS specific */ Offset (0x100), #include diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 44ec9f3e77..0da1fe49d3 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -10,10 +10,8 @@ #include #include #include -#include #include #include -#include #include #include "chip.h" @@ -352,21 +350,10 @@ static void gfx_panel_setup(struct device *dev) } } -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void gfx_init(struct device *dev) { + intel_gma_init_igd_opregion(); + /* Pre VBIOS Init */ gfx_pre_vbios_init(dev); @@ -380,9 +367,6 @@ static void gfx_init(struct device *dev) /* Post VBIOS Init */ gfx_post_vbios_init(dev); - - /* Restore opregion on S3 resume */ - intel_gma_restore_opregion(); } static void gma_generate_ssdt(const struct device *dev) @@ -392,39 +376,12 @@ static void gma_generate_ssdt(const struct device *dev) drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } -static unsigned long -gma_write_acpi_tables(const struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; -} - static struct device_operations gfx_device_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gfx_init, .ops_pci = &soc_pci_ops, - .write_acpi_tables = gma_write_acpi_tables, .acpi_fill_ssdt = gma_generate_ssdt, }; diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index 96f7afdbe0..cc70f78b2a 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -46,40 +46,7 @@ typedef struct global_nvs_t { u32 cbmc; /* 0x38 - coreboot memconsole */ u8 rsvd3[120]; /* 0x3c - 0xb3 - unused */ - /* IGD OpRegion */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; /* 0xb8 - IGD boot type */ - u8 ipat; /* 0xb9 - IGD panel type */ - u8 itvf; /* 0xba - IGD TV format */ - u8 itvm; /* 0xbb - IGD TV minor format */ - u8 ipsc; /* 0xbc - IGD Panel Scaling */ - u8 iblc; /* 0xbd - IGD BLC configuration */ - u8 ibia; /* 0xbe - IGD BIA configuration */ - u8 issc; /* 0xbf - IGD SSC configuration */ - u8 i409; /* 0xc0 - IGD 0409 modified settings */ - u8 i509; /* 0xc1 - IGD 0509 modified settings */ - u8 i609; /* 0xc2 - IGD 0609 modified settings */ - u8 i709; /* 0xc3 - IGD 0709 modified settings */ - u8 idmm; /* 0xc4 - IGD Power Conservation */ - u8 idms; /* 0xc5 - IGD DVMT memory size */ - u8 if1e; /* 0xc6 - IGD Function 1 Enable */ - u8 hvco; /* 0xc7 - IGD HPLL VCO */ - u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ - u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ - u8 pavp; /* 0xe9 - IGD PAVP data */ - u8 rsvd12; /* 0xea - rsvd */ - u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native PCIe support */ - u8 plfl; /* 0xed - platform flavor */ - u8 brev; /* 0xee - board revision */ - u8 dpbm; /* 0xef - digital port b mode */ - u8 dpcm; /* 0xf0 - digital port c mode */ - u8 dpdm; /* 0xf1 - digital port c mode */ - u8 alfp; /* 0xf2 - active lfp */ - u8 imon; /* 0xf3 - current graphics turbo imon value */ - u8 mmio; /* 0xf4 - 64bit mmio support */ - - u8 unused[11]; + u8 unused[76]; /* ChromeOS specific (0x100-0xfff)*/ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index d0051d1fb7..a3025c23c6 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -460,38 +460,16 @@ unsigned long acpi_madt_irq_overrides(unsigned long current) return current; } -/* Initialize IGD OpRegion, called from ACPI code */ -static int update_igd_opregion(igd_opregion_t *opregion) -{ - /* FIXME: Add platform specific mailbox initialization */ - - return 0; -} - unsigned long southcluster_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { acpi_header_t *ssdt2; - global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (!CONFIG(DISABLE_HPET)) { current = acpi_write_hpet(device, current, rsdp); current = acpi_align_current(current); } - if (CONFIG(INTEL_GMA_ADD_VBT)) { - igd_opregion_t *opregion; - - printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = (igd_opregion_t *)current; - intel_gma_init_igd_opregion(opregion); - if (gnvs) - gnvs->aslb = (u32)opregion; - update_igd_opregion(opregion); - current += sizeof(igd_opregion_t); - current = acpi_align_current(current); - } - ssdt2 = (acpi_header_t *)current; memset(ssdt2, 0, sizeof(acpi_header_t)); acpi_create_serialio_ssdt(ssdt2); diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index c790438f65..c983d93db7 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -55,48 +55,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) TOLM, 32, /* 0x34 - Top of Low Memory */ CBMC, 32, /* 0x38 - coreboot mem console pointer */ - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD Power conservation feature - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 - - ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) - PAVP, 8, // 0xe9 - IGD PAVP data - Offset (0xeb), - OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native PCIe support - PLFL, 8, // 0xed - platform flavor - BREV, 8, // 0xee - board revision - DPBM, 8, // 0xef - digital port b mode - DPCM, 8, // 0xf0 - digital port c mode - DPDM, 8, // 0xf1 - digital port d mode - ALFP, 8, // 0xf2 - active lfp - IMON, 8, // 0xf3 - current graphics turbo imon value - MMIO, 8, // 0xf4 - 64bit mmio support - /* ChromeOS specific */ Offset (0x100), #include diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c index 9de5126034..0365ea2779 100644 --- a/src/soc/intel/braswell/gfx.c +++ b/src/soc/intel/braswell/gfx.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include @@ -50,6 +49,8 @@ static void gfx_init(struct device *dev) { printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); + intel_gma_init_igd_opregion(); + if (!CONFIG(RUN_FSP_GOP)) { /* Pre VBIOS Init */ gfx_pre_vbios_init(dev); @@ -60,20 +61,6 @@ static void gfx_init(struct device *dev) /* Post VBIOS Init */ gfx_post_vbios_init(dev); } - intel_gma_restore_opregion(); -} - -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; } static void gma_generate_ssdt(const struct device *dev) diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 412d7b9746..22ea10fe93 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -48,40 +48,7 @@ typedef struct global_nvs_t { u32 cbmc; /* 0x38 - coreboot memconsole */ u8 rsvd3[120]; /* 0x3c - 0xb3 - unused */ - /* IGD OpRegion */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; /* 0xb8 - IGD boot type */ - u8 ipat; /* 0xb9 - IGD panel type */ - u8 itvf; /* 0xba - IGD TV format */ - u8 itvm; /* 0xbb - IGD TV minor format */ - u8 ipsc; /* 0xbc - IGD Panel Scaling */ - u8 iblc; /* 0xbd - IGD BLC configuration */ - u8 ibia; /* 0xbe - IGD BIA configuration */ - u8 issc; /* 0xbf - IGD SSC configuration */ - u8 i409; /* 0xc0 - IGD 0409 modified settings */ - u8 i509; /* 0xc1 - IGD 0509 modified settings */ - u8 i609; /* 0xc2 - IGD 0609 modified settings */ - u8 i709; /* 0xc3 - IGD 0709 modified settings */ - u8 idmm; /* 0xc4 - IGD Power Conservation */ - u8 idms; /* 0xc5 - IGD DVMT memory size */ - u8 if1e; /* 0xc6 - IGD Function 1 Enable */ - u8 hvco; /* 0xc7 - IGD HPLL VCO */ - u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ - u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ - u8 pavp; /* 0xe9 - IGD PAVP data */ - u8 rsvd12; /* 0xea - rsvd */ - u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native PCIe support */ - u8 plfl; /* 0xed - platform flavor */ - u8 brev; /* 0xee - board revision */ - u8 dpbm; /* 0xef - digital port b mode */ - u8 dpcm; /* 0xf0 - digital port c mode */ - u8 dpdm; /* 0xf1 - digital port c mode */ - u8 alfp; /* 0xf2 - active lfp */ - u8 imon; /* 0xf3 - current graphics turbo imon value */ - u8 mmio; /* 0xf4 - 64bit mmio support */ - - u8 unused[11]; + u8 unused[76]; /* ChromeOS specific (0x100-0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl index 1fb90021bb..3c6c5f5998 100644 --- a/src/soc/intel/broadwell/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/acpi/globalnvs.asl @@ -45,48 +45,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit GPEI, 64, // 0x28 - 0x2f - GPE wake status bit - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD Power conservation feature - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 - - ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) - PAVP, 8, // 0xe9 - IGD PAVP data - Offset (0xeb), - OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native PCIe support - PLFL, 8, // 0xed - platform flavor - BREV, 8, // 0xee - board revision - DPBM, 8, // 0xef - digital port b mode - DPCM, 8, // 0xf0 - digital port c mode - DPDM, 8, // 0xf1 - digital port d mode - ALFP, 8, // 0xf2 - active lfp - IMON, 8, // 0xf3 - current graphics turbo imon value - MMIO, 8, // 0xf4 - 64bit mmio support - /* ChromeOS specific */ Offset (0x100), #include diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 1e39861915..fbd45cb7fe 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -11,13 +11,11 @@ #include #include #include -#include #include #include #include #include #include -#include #include #include #include @@ -491,24 +489,13 @@ static void igd_cdclk_init(struct device *dev, const int is_broadwell) gtt_rmw(0x64810, 0xfffff800, dpdiv); } -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void igd_init(struct device *dev) { int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT); u32 rp1_gfx_freq; + intel_gma_init_igd_opregion(); + /* IGD needs to be Bus Master */ u32 reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; @@ -586,33 +573,6 @@ static void igd_init(struct device *dev) gma_gfxinit(&lightup_ok); gfx_set_init_done(lightup_ok); } - - intel_gma_restore_opregion(); -} - -static unsigned long -gma_write_acpi_tables(const struct device *const dev, unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; } static void gma_generate_ssdt(const struct device *dev) @@ -628,7 +588,6 @@ static struct device_operations igd_ops = { .enable_resources = &pci_dev_enable_resources, .init = &igd_init, .ops_pci = &broadwell_pci_ops, - .write_acpi_tables = gma_write_acpi_tables, .acpi_fill_ssdt = gma_generate_ssdt, }; diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index 67f1b623e4..8772a02983 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -38,40 +38,7 @@ typedef struct global_nvs_t { u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ u8 unused1[132]; /* 0x30 - 0xb3 - unused */ - /* IGD OpRegion */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; /* 0xb8 - IGD boot type */ - u8 ipat; /* 0xb9 - IGD panel type */ - u8 itvf; /* 0xba - IGD TV format */ - u8 itvm; /* 0xbb - IGD TV minor format */ - u8 ipsc; /* 0xbc - IGD Panel Scaling */ - u8 iblc; /* 0xbd - IGD BLC configuration */ - u8 ibia; /* 0xbe - IGD BIA configuration */ - u8 issc; /* 0xbf - IGD SSC configuration */ - u8 i409; /* 0xc0 - IGD 0409 modified settings */ - u8 i509; /* 0xc1 - IGD 0509 modified settings */ - u8 i609; /* 0xc2 - IGD 0609 modified settings */ - u8 i709; /* 0xc3 - IGD 0709 modified settings */ - u8 idmm; /* 0xc4 - IGD Power Conservation */ - u8 idms; /* 0xc5 - IGD DVMT memory size */ - u8 if1e; /* 0xc6 - IGD Function 1 Enable */ - u8 hvco; /* 0xc7 - IGD HPLL VCO */ - u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ - u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ - u8 pavp; /* 0xe9 - IGD PAVP data */ - u8 rsvd2; /* 0xea - rsvd */ - u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native PCIe support */ - u8 plfl; /* 0xed - platform flavor */ - u8 brev; /* 0xee - board revision */ - u8 dpbm; /* 0xef - digital port b mode */ - u8 dpcm; /* 0xf0 - digital port c mode */ - u8 dpdm; /* 0xf1 - digital port c mode */ - u8 alfp; /* 0xf2 - active lfp */ - u8 imon; /* 0xf3 - current graphics turbo imon value */ - u8 mmio; /* 0xf4 - 64bit mmio support */ - - u8 unused2[11]; + u8 unused2[76]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index 5f61db4ee2..1db46254c5 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -22,6 +22,8 @@ void graphics_soc_init(struct device *dev) { uint32_t ddi_buf_ctl; + intel_gma_init_igd_opregion(); + /* * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. * This will allow the kernel to use 4-lane eDP links properly @@ -59,19 +61,3 @@ void graphics_soc_init(struct device *dev) pci_dev_init(dev); } } - -uintptr_t graphics_soc_write_acpi_opregion(const struct device *device, - uintptr_t current, struct acpi_rsdp *rsdp) -{ - igd_opregion_t *opregion; - - printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = (igd_opregion_t *)current; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - return acpi_align_current(current); -} diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 71a619a440..ae45d67214 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -119,7 +119,6 @@ static const struct device_operations graphics_ops = { .init = graphics_soc_init, .ops_pci = &pci_dev_ops_pci, #if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = graphics_soc_write_acpi_opregion, .acpi_fill_ssdt = gma_generate_ssdt, #endif .scan_bus = scan_generic_bus, diff --git a/src/soc/intel/common/block/include/intelblocks/graphics.h b/src/soc/intel/common/block/include/intelblocks/graphics.h index de1a0a595c..e65be4a1af 100644 --- a/src/soc/intel/common/block/include/intelblocks/graphics.h +++ b/src/soc/intel/common/block/include/intelblocks/graphics.h @@ -18,20 +18,6 @@ */ void graphics_soc_init(struct device *dev); -/* - * Write ASL entry for Graphics opregion - * Input: - * struct device *device: device structure - * current: start address of graphics opregion - * rsdp: pointer to RSDT (and XSDT) structure - * - * Output: - * End address of graphics opregion so that the called - * can use the same for future calls to write_acpi_tables - */ -uintptr_t graphics_soc_write_acpi_opregion(const struct device *device, - uintptr_t current, struct acpi_rsdp *rsdp); - /* i915 controller info for ACPI backlight controls */ const struct i915_gpu_controller_info * intel_igd_get_controller_info(const struct device *device); diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c index cd2cc5db0e..3118495498 100644 --- a/src/soc/intel/icelake/graphics.c +++ b/src/soc/intel/icelake/graphics.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include #include #include @@ -17,6 +16,8 @@ uintptr_t fsp_soc_get_igd_bar(void) void graphics_soc_init(struct device *dev) { + intel_gma_init_igd_opregion(); + /* * GFX PEIM module inside FSP binary is taking care of graphics * initialization based on RUN_FSP_GOP Kconfig @@ -37,19 +38,3 @@ void graphics_soc_init(struct device *dev) /* Initialize PCI device, load/execute BIOS Option ROM */ pci_dev_init(dev); } - -uintptr_t graphics_soc_write_acpi_opregion(const struct device *device, - uintptr_t current, struct acpi_rsdp *rsdp) -{ - igd_opregion_t *opregion; - - printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = (igd_opregion_t *)current; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - return acpi_align_current(current); -} diff --git a/src/soc/intel/jasperlake/graphics.c b/src/soc/intel/jasperlake/graphics.c index cd2cc5db0e..3118495498 100644 --- a/src/soc/intel/jasperlake/graphics.c +++ b/src/soc/intel/jasperlake/graphics.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include #include #include @@ -17,6 +16,8 @@ uintptr_t fsp_soc_get_igd_bar(void) void graphics_soc_init(struct device *dev) { + intel_gma_init_igd_opregion(); + /* * GFX PEIM module inside FSP binary is taking care of graphics * initialization based on RUN_FSP_GOP Kconfig @@ -37,19 +38,3 @@ void graphics_soc_init(struct device *dev) /* Initialize PCI device, load/execute BIOS Option ROM */ pci_dev_init(dev); } - -uintptr_t graphics_soc_write_acpi_opregion(const struct device *device, - uintptr_t current, struct acpi_rsdp *rsdp) -{ - igd_opregion_t *opregion; - - printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = (igd_opregion_t *)current; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - return acpi_align_current(current); -} diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index c2584db90b..abcde9421b 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -58,48 +58,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) A4GB, 64, // 0x54 - 0x5B Base of above 4GB MMIO Resource A4GS, 64, // 0x5C - 0x63 Length of above 4GB MMIO Resource - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD Power conservation feature - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 - - ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) - PAVP, 8, // 0xe9 - IGD PAVP data - Offset (0xeb), - OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native PCIe support - PLFL, 8, // 0xed - platform flavor - BREV, 8, // 0xee - board revision - DPBM, 8, // 0xef - digital port b mode - DPCM, 8, // 0xf0 - digital port c mode - DPDM, 8, // 0xf1 - digital port d mode - ALFP, 8, // 0xf2 - active lfp - IMON, 8, // 0xf3 - current graphics turbo imon value - MMIO, 8, // 0xf4 - 64bit mmio support - /* ChromeOS specific */ Offset (0x100), #include diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index 0f6e35a173..dab7e145d1 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include @@ -12,7 +11,6 @@ #include #include #include -#include #include #include @@ -85,6 +83,8 @@ void graphics_soc_init(struct device *dev) { u32 ddi_buf_ctl; + intel_gma_init_igd_opregion(); + graphics_setup_panel(dev); /* @@ -123,56 +123,6 @@ void graphics_soc_init(struct device *dev) /* Initialize PCI device, load/execute BIOS Option ROM */ pci_dev_init(dev); } - - intel_gma_restore_opregion(); -} - -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - -/* Initialize IGD OpRegion, called from ACPI code */ -static void update_igd_opregion(igd_opregion_t *opregion) -{ - /* FIXME: Add platform specific mailbox initialization */ -} - -uintptr_t graphics_soc_write_acpi_opregion(const struct device *device, - uintptr_t current, struct acpi_rsdp *rsdp) -{ - igd_opregion_t *opregion; - global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - - /* If GOP is not used, exit here */ - if (!CONFIG(INTEL_GMA_ADD_VBT)) - return current; - - /* If IGD is disabled, exit here */ - if (pci_read_config16(device, PCI_VENDOR_ID) == 0xFFFF) - return current; - - printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = (igd_opregion_t *)current; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - if (gnvs) - gnvs->aslb = (u32)(uintptr_t)opregion; - update_igd_opregion(opregion); - current += sizeof(igd_opregion_t); - current = acpi_align_current(current); - - printk(BIOS_DEBUG, "current = %lx\n", current); - return current; } const struct i915_gpu_controller_info * diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 630ceb7a78..4973597947 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -47,42 +47,7 @@ typedef struct global_nvs_t { u64 elng; /* 0x4C - 0x53 EPC Length */ u64 a4gb; /* 0x54 - 0x5B Base of above 4GB MMIO Resource */ u64 a4gs; /* 0x5C - 0x63 Length of above 4GB MMIO Resource */ - u8 rsvd[80]; - - /* IGD OpRegion */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; /* 0xb8 - IGD boot type */ - u8 ipat; /* 0xb9 - IGD panel type */ - u8 itvf; /* 0xba - IGD TV format */ - u8 itvm; /* 0xbb - IGD TV minor format */ - u8 ipsc; /* 0xbc - IGD Panel Scaling */ - u8 iblc; /* 0xbd - IGD BLC configuration */ - u8 ibia; /* 0xbe - IGD BIA configuration */ - u8 issc; /* 0xbf - IGD SSC configuration */ - u8 i409; /* 0xc0 - IGD 0409 modified settings */ - u8 i509; /* 0xc1 - IGD 0509 modified settings */ - u8 i609; /* 0xc2 - IGD 0609 modified settings */ - u8 i709; /* 0xc3 - IGD 0709 modified settings */ - u8 idmm; /* 0xc4 - IGD Power Conservation */ - u8 idms; /* 0xc5 - IGD DVMT memory size */ - u8 if1e; /* 0xc6 - IGD Function 1 Enable */ - u8 hvco; /* 0xc7 - IGD HPLL VCO */ - u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ - u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ - u8 pavp; /* 0xe9 - IGD PAVP data */ - u8 rsvd12; /* 0xea - rsvd */ - u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native PCIe support */ - u8 plfl; /* 0xed - platform flavor */ - u8 brev; /* 0xee - board revision */ - u8 dpbm; /* 0xef - digital port b mode */ - u8 dpcm; /* 0xf0 - digital port c mode */ - u8 dpdm; /* 0xf1 - digital port c mode */ - u8 alfp; /* 0xf2 - active lfp */ - u8 imon; /* 0xf3 - current graphics turbo imon value */ - u8 mmio; /* 0xf4 - 64bit mmio support */ - - u8 unused[11]; + u8 rsvd[156]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/tigerlake/graphics.c b/src/soc/intel/tigerlake/graphics.c index 22812fbb29..ea90d44033 100644 --- a/src/soc/intel/tigerlake/graphics.c +++ b/src/soc/intel/tigerlake/graphics.c @@ -6,7 +6,6 @@ * Chapter number: 4 */ -#include #include #include #include @@ -23,6 +22,8 @@ uintptr_t fsp_soc_get_igd_bar(void) void graphics_soc_init(struct device *dev) { + intel_gma_init_igd_opregion(); + /* * GFX PEIM module inside FSP binary is taking care of graphics * initialization based on RUN_FSP_GOP Kconfig @@ -43,19 +44,3 @@ void graphics_soc_init(struct device *dev) /* Initialize PCI device, load/execute BIOS Option ROM */ pci_dev_init(dev); } - -uintptr_t graphics_soc_write_acpi_opregion(const struct device *device, - uintptr_t current, struct acpi_rsdp *rsdp) -{ - igd_opregion_t *opregion; - - printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = (igd_opregion_t *)current; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - return acpi_align_current(current); -} diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index 468e07b189..f9944720a8 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -108,47 +108,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) /* XHCI */ Offset (0xb2), XHCI, 8, - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD Power conservation feature - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 - ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) - PAVP, 8, // 0xe9 - IGD PAVP data - Offset (0xeb), - OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native PCIe support - PLFL, 8, // 0xed - platform flavor - BREV, 8, // 0xee - board revision - DPBM, 8, // 0xef - digital port b mode - DPCM, 8, // 0xf0 - digital port c mode - DPDM, 8, // 0xf1 - digital port d mode - ALFP, 8, // 0xf2 - active lfp - IMON, 8, // 0xf3 - current graphics turbo imon value - MMIO, 8, // 0xf4 - 64bit mmio support + Offset (0xf5), TPIQ, 8, // 0xf5 - trackpad IRQ value /* ChromeOS specific */ diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 9dc65c4084..075eae0921 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -96,38 +96,7 @@ typedef struct global_nvs_t { u8 rsvd11[6]; /* XHCI */ u8 xhci; - /* IGD OpRegion (not implemented yet) */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; /* 0xb8 - IGD boot type */ - u8 ipat; /* 0xb9 - IGD panel type */ - u8 itvf; /* 0xba - IGD TV format */ - u8 itvm; /* 0xbb - IGD TV minor format */ - u8 ipsc; /* 0xbc - IGD Panel Scaling */ - u8 iblc; /* 0xbd - IGD BLC configuration */ - u8 ibia; /* 0xbe - IGD BIA configuration */ - u8 issc; /* 0xbf - IGD SSC configuration */ - u8 i409; /* 0xc0 - IGD 0409 modified settings */ - u8 i509; /* 0xc1 - IGD 0509 modified settings */ - u8 i609; /* 0xc2 - IGD 0609 modified settings */ - u8 i709; /* 0xc3 - IGD 0709 modified settings */ - u8 idmm; /* 0xc4 - IGD Power Conservation */ - u8 idms; /* 0xc5 - IGD DVMT memory size */ - u8 if1e; /* 0xc6 - IGD Function 1 Enable */ - u8 hvco; /* 0xc7 - IGD HPLL VCO */ - u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ - u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ - u8 pavp; /* 0xe9 - IGD PAVP data */ - u8 rsvd12; /* 0xea - rsvd */ - u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native PCIe support */ - u8 plfl; /* 0xed - platform flavor */ - u8 brev; /* 0xee - board revision */ - u8 dpbm; /* 0xef - digital port b mode */ - u8 dpcm; /* 0xf0 - digital port c mode */ - u8 dpdm; /* 0xf1 - digital port c mode */ - u8 alfp; /* 0xf2 - active lfp */ - u8 imon; /* 0xf3 - current graphics turbo imon value */ - u8 mmio; /* 0xf4 - 64bit mmio support */ + u8 rsvd12[65]; u8 tpiq; /* 0xf5 - trackpad IRQ value */ u8 rsvd13[10]; /* 0xf6 - rsvd */ diff --git a/src/southbridge/intel/i82801dx/nvs.h b/src/southbridge/intel/i82801dx/nvs.h index a369ac66ab..9bd16786a3 100644 --- a/src/southbridge/intel/i82801dx/nvs.h +++ b/src/southbridge/intel/i82801dx/nvs.h @@ -90,27 +90,7 @@ typedef struct { u8 gtf2[7]; u8 idem; u8 idet; - u8 rsvd11[7]; - /* IGD OpRegion (not implemented yet) */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; - u8 ipat; - u8 itvf; - u8 itvm; - u8 ipsc; - u8 iblc; - u8 ibia; - u8 issc; - u8 i409; - u8 i509; - u8 i609; - u8 i709; - u8 idmm; - u8 idms; - u8 if1e; - u8 hvco; - u32 nxd[8]; - u8 rsvd12[8]; + u8 rsvd11[67]; /* Mainboard specific */ u8 dock; /* 0xf0 - Docking Status */ u8 bten; diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index 36d938fcc2..848005dcb9 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -104,33 +104,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) GTF2, 56, // 0xa4 - GTF task file buffer for port 2 IDEM, 8, // 0xab - IDE mode (compatible / enhanced) IDET, 8, // 0xac - IDE - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD DVMT Mode - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 /* Mainboard Specific (TODO move elsewhere) */ Offset (0xf0), DOCK, 8, // 0xf0 - Docking Status diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/nvs.h index f23b050909..6b697f224e 100644 --- a/src/southbridge/intel/i82801gx/nvs.h +++ b/src/southbridge/intel/i82801gx/nvs.h @@ -89,27 +89,7 @@ typedef struct { u8 gtf2[7]; u8 idem; u8 idet; - u8 rsvd11[7]; - /* IGD OpRegion (not implemented yet) */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; - u8 ipat; - u8 itvf; - u8 itvm; - u8 ipsc; - u8 iblc; - u8 ibia; - u8 issc; - u8 i409; - u8 i509; - u8 i609; - u8 i709; - u8 idmm; - u8 idms; - u8 if1e; - u8 hvco; - u32 nxd[8]; - u8 rsvd12[8]; + u8 rsvd11[67]; /* Mainboard specific */ u8 dock; /* 0xf0 - Docking Status */ u8 bten; diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl index e90049984a..3b6115feb5 100644 --- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -108,33 +108,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) GTF2, 56, // 0xa4 - GTF task file buffer for port 2 IDEM, 8, // 0xab - IDE mode (compatible / enhanced) IDET, 8, // 0xac - IDE - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD DVMT Mode - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 /* Mainboard Specific (TODO move elsewhere) */ Offset (0xf0), DOCK, 8, // 0xf0 - Docking Status diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h index 6f83f54a50..3cd4c58d7c 100644 --- a/src/southbridge/intel/i82801ix/nvs.h +++ b/src/southbridge/intel/i82801ix/nvs.h @@ -91,27 +91,7 @@ typedef struct { u8 gtf2[7]; u8 idem; u8 idet; - u8 rsvd11[7]; - /* IGD OpRegion (not implemented yet) */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; - u8 ipat; - u8 itvf; - u8 itvm; - u8 ipsc; - u8 iblc; - u8 ibia; - u8 issc; - u8 i409; - u8 i509; - u8 i609; - u8 i709; - u8 idmm; - u8 idms; - u8 if1e; - u8 hvco; - u32 nxd[8]; - u8 rsvd12[8]; + u8 rsvd11[67]; /* Mainboard specific */ u8 dock; /* 0xf0 - Docking Status */ u8 bten; diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl index d2611072d8..34c550c206 100644 --- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl @@ -108,33 +108,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) GTF2, 56, // 0xa4 - GTF task file buffer for port 2 IDEM, 8, // 0xab - IDE mode (compatible / enhanced) IDET, 8, // 0xac - IDE - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD DVMT Mode - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 /* Mainboard Specific (TODO move elsewhere) */ Offset (0xf0), DOCK, 8, // 0xf0 - Docking Status diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/nvs.h index a0c3af83c2..8dd012f03d 100644 --- a/src/southbridge/intel/i82801jx/nvs.h +++ b/src/southbridge/intel/i82801jx/nvs.h @@ -89,27 +89,7 @@ typedef struct { u8 gtf2[7]; u8 idem; u8 idet; - u8 rsvd11[7]; - /* IGD OpRegion (not implemented yet) */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; - u8 ipat; - u8 itvf; - u8 itvm; - u8 ipsc; - u8 iblc; - u8 ibia; - u8 issc; - u8 i409; - u8 i509; - u8 i609; - u8 i709; - u8 idmm; - u8 idms; - u8 if1e; - u8 hvco; - u32 nxd[8]; - u8 rsvd12[8]; + u8 rsvd11[67]; /* Mainboard specific */ u8 dock; /* 0xf0 - Docking Status */ u8 bten; diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index 1dd69bda30..6b82de33b2 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -95,39 +95,7 @@ typedef struct global_nvs_t { u8 rsvd11[6]; /* XHCI */ u8 xhci; - /* IGD OpRegion (not implemented yet) */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; /* 0xb8 - IGD boot type */ - u8 ipat; /* 0xb9 - IGD panel type */ - u8 itvf; /* 0xba - IGD TV format */ - u8 itvm; /* 0xbb - IGD TV minor format */ - u8 ipsc; /* 0xbc - IGD Panel Scaling */ - u8 iblc; /* 0xbd - IGD BLC configuration */ - u8 ibia; /* 0xbe - IGD BIA configuration */ - u8 issc; /* 0xbf - IGD SSC configuration */ - u8 i409; /* 0xc0 - IGD 0409 modified settings */ - u8 i509; /* 0xc1 - IGD 0509 modified settings */ - u8 i609; /* 0xc2 - IGD 0609 modified settings */ - u8 i709; /* 0xc3 - IGD 0709 modified settings */ - u8 idmm; /* 0xc4 - IGD Power Conservation */ - u8 idms; /* 0xc5 - IGD DVMT memory size */ - u8 if1e; /* 0xc6 - IGD Function 1 Enable */ - u8 hvco; /* 0xc7 - IGD HPLL VCO */ - u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ - u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ - u8 pavp; /* 0xe9 - IGD PAVP data */ - u8 rsvd12; /* 0xea - rsvd */ - u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native PCIe support */ - u8 plfl; /* 0xed - platform flavor */ - u8 brev; /* 0xee - board revision */ - u8 dpbm; /* 0xef - digital port b mode */ - u8 dpcm; /* 0xf0 - digital port c mode */ - u8 dpdm; /* 0xf1 - digital port c mode */ - u8 alfp; /* 0xf2 - active lfp */ - u8 imon; /* 0xf3 - current graphics turbo imon value */ - u8 mmio; /* 0xf4 - 64bit mmio support */ - u8 rsvd13[11]; /* 0xf5 - rsvd */ + u8 rsvd13[76]; /* 0xf5 - rsvd */ /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index fdb0973b31..16c4b75f96 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -103,48 +103,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0xa0), CBMC, 32, // 0xa0 - coreboot mem console pointer - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD Power conservation feature - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 - - ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) - PAVP, 8, // 0xe9 - IGD PAVP data - Offset (0xeb), - OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native PCIe support - PLFL, 8, // 0xed - platform flavor - BREV, 8, // 0xee - board revision - DPBM, 8, // 0xef - digital port b mode - DPCM, 8, // 0xf0 - digital port c mode - DPDM, 8, // 0xf1 - digital port d mode - ALFP, 8, // 0xf2 - active lfp - IMON, 8, // 0xf3 - current graphics turbo imon value - MMIO, 8, // 0xf4 - 64bit mmio support - /* ChromeOS specific */ Offset (0x100), #include diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index a52f5e38c5..b5b6e9fc02 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -72,40 +72,7 @@ typedef struct global_nvs_t { u32 s0b[8]; /* 0x60 - 0x7f - BAR0 */ u32 s1b[8]; /* 0x80 - 0x9f - BAR1 */ u32 cbmc; /* 0xa0 - 0xa3 - coreboot memconsole */ - u8 rsvd6[16]; - /* IGD OpRegion (not implemented yet) */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; /* 0xb8 - IGD boot type */ - u8 ipat; /* 0xb9 - IGD panel type */ - u8 itvf; /* 0xba - IGD TV format */ - u8 itvm; /* 0xbb - IGD TV minor format */ - u8 ipsc; /* 0xbc - IGD Panel Scaling */ - u8 iblc; /* 0xbd - IGD BLC configuration */ - u8 ibia; /* 0xbe - IGD BIA configuration */ - u8 issc; /* 0xbf - IGD SSC configuration */ - u8 i409; /* 0xc0 - IGD 0409 modified settings */ - u8 i509; /* 0xc1 - IGD 0509 modified settings */ - u8 i609; /* 0xc2 - IGD 0609 modified settings */ - u8 i709; /* 0xc3 - IGD 0709 modified settings */ - u8 idmm; /* 0xc4 - IGD Power Conservation */ - u8 idms; /* 0xc5 - IGD DVMT memory size */ - u8 if1e; /* 0xc6 - IGD Function 1 Enable */ - u8 hvco; /* 0xc7 - IGD HPLL VCO */ - u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ - u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ - u8 pavp; /* 0xe9 - IGD PAVP data */ - u8 rsvd12; /* 0xea - rsvd */ - u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native PCIe support */ - u8 plfl; /* 0xed - platform flavor */ - u8 brev; /* 0xee - board revision */ - u8 dpbm; /* 0xef - digital port b mode */ - u8 dpcm; /* 0xf0 - digital port c mode */ - u8 dpdm; /* 0xf1 - digital port c mode */ - u8 alfp; /* 0xf2 - active lfp */ - u8 imon; /* 0xf3 - current graphics turbo imon value */ - u8 mmio; /* 0xf4 - 64bit mmio support */ - u8 rsvd13[11]; /* 0xf5 - rsvd */ + u8 rsvd6[92]; /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; From 826094f65cf8778bd120e08917ef5557d0bad49d Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 26 Apr 2020 19:24:00 +0200 Subject: [PATCH 319/405] soc/intel/gma: Move display and opregion init to common code Change-Id: I359b529df44db7d63c5a7922cb1ebd8e130d0c43 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/40725 Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/graphics.c | 32 -------------- src/soc/intel/cannonlake/graphics.c | 33 --------------- .../intel/common/block/graphics/graphics.c | 42 +++++++++++++++++-- src/soc/intel/icelake/graphics.c | 30 ------------- src/soc/intel/jasperlake/graphics.c | 30 ------------- src/soc/intel/skylake/graphics.c | 35 +--------------- src/soc/intel/tigerlake/graphics.c | 30 ------------- 7 files changed, 41 insertions(+), 191 deletions(-) diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index 2070baf14c..c8d282d837 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -1,42 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include -#include -#include -#include #include -#include -#include -#include #include -#include -#include #include uintptr_t fsp_soc_get_igd_bar(void) { return graphics_get_memory_base(); } - -void graphics_soc_init(struct device *const dev) -{ - intel_gma_init_igd_opregion(); - - if (CONFIG(RUN_FSP_GOP)) - return; - - uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { - if (!acpi_is_wakeup_s3() && display_init_required()) { - int lightup_ok; - gma_gfxinit(&lightup_ok); - gfx_set_init_done(lightup_ok); - } - } else { - /* Initialize PCI device, load/execute BIOS Option ROM */ - pci_dev_init(dev); - } -} diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index 1db46254c5..cd5e773dbb 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -1,15 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include -#include -#include #include #include -#include -#include #include -#include -#include #include #include @@ -22,8 +16,6 @@ void graphics_soc_init(struct device *dev) { uint32_t ddi_buf_ctl; - intel_gma_init_igd_opregion(); - /* * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. * This will allow the kernel to use 4-lane eDP links properly @@ -35,29 +27,4 @@ void graphics_soc_init(struct device *dev) DDI_BUF_IS_IDLE); graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); } - - /* IGD needs to Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | - PCI_COMMAND_IO); - - /* - * GFX PEIM module inside FSP binary is taking care of graphics - * initialization based on RUN_FSP_GOP Kconfig option and input - * VBT file. - * - * In case of non-FSP solution, SoC need to select another - * Kconfig to perform GFX initialization. - */ - if (CONFIG(RUN_FSP_GOP)) { - /* nothing to do */ - } else if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { - if (!acpi_is_wakeup_s3() && display_init_required()) { - int lightup_ok; - gma_gfxinit(&lightup_ok); - gfx_set_init_done(lightup_ok); - } - } else { - /* Initialize PCI device, load/execute BIOS Option ROM */ - pci_dev_init(dev); - } } diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index ae45d67214..5110aad3d6 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -1,11 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include #include #include #include #include #include +#include +#include #include #include @@ -15,9 +18,7 @@ __weak void graphics_soc_init(struct device *dev) /* * User needs to implement SoC override in case wishes * to perform certain specific graphics initialization - * along with pci_dev_init(dev) */ - pci_dev_init(dev); } __weak const struct i915_gpu_controller_info * @@ -26,6 +27,41 @@ intel_igd_get_controller_info(const struct device *device) return NULL; } +static void gma_init(struct device *const dev) +{ + intel_gma_init_igd_opregion(); + + /* SoC specific configuration. */ + graphics_soc_init(dev); + + /* + * GFX PEIM module inside FSP binary is taking care of graphics + * initialization based on RUN_FSP_GOP Kconfig option and input + * VBT file. + * + * In case of non-FSP solution, SoC need to select another + * Kconfig to perform GFX initialization. + */ + if (CONFIG(RUN_FSP_GOP)) + return; + + /* IGD needs to Bus Master */ + u32 reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config32(dev, PCI_COMMAND, reg32); + + if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { + if (!acpi_is_wakeup_s3() && display_init_required()) { + int lightup_ok; + gma_gfxinit(&lightup_ok); + gfx_set_init_done(lightup_ok); + } + } else { + /* Initialize PCI device, load/execute BIOS Option ROM */ + pci_dev_init(dev); + } +} + static void gma_generate_ssdt(const struct device *device) { const struct i915_gpu_controller_info *gfx = intel_igd_get_controller_info(device); @@ -116,7 +152,7 @@ static const struct device_operations graphics_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = graphics_soc_init, + .init = gma_init, .ops_pci = &pci_dev_ops_pci, #if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt = gma_generate_ssdt, diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c index 3118495498..c8d282d837 100644 --- a/src/soc/intel/icelake/graphics.c +++ b/src/soc/intel/icelake/graphics.c @@ -1,11 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include -#include -#include -#include -#include #include #include @@ -13,28 +8,3 @@ uintptr_t fsp_soc_get_igd_bar(void) { return graphics_get_memory_base(); } - -void graphics_soc_init(struct device *dev) -{ - intel_gma_init_igd_opregion(); - - /* - * GFX PEIM module inside FSP binary is taking care of graphics - * initialization based on RUN_FSP_GOP Kconfig - * option and input VBT file. Hence no need to load/execute legacy VGA - * OpROM in order to initialize GFX. - * - * In case of non-FSP solution, SoC need to select VGA_ROM_RUN - * Kconfig to perform GFX initialization through VGA OpRom. - */ - if (CONFIG(RUN_FSP_GOP)) - return; - - /* IGD needs to Bus Master */ - uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* Initialize PCI device, load/execute BIOS Option ROM */ - pci_dev_init(dev); -} diff --git a/src/soc/intel/jasperlake/graphics.c b/src/soc/intel/jasperlake/graphics.c index 3118495498..c8d282d837 100644 --- a/src/soc/intel/jasperlake/graphics.c +++ b/src/soc/intel/jasperlake/graphics.c @@ -1,11 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include -#include -#include -#include -#include #include #include @@ -13,28 +8,3 @@ uintptr_t fsp_soc_get_igd_bar(void) { return graphics_get_memory_base(); } - -void graphics_soc_init(struct device *dev) -{ - intel_gma_init_igd_opregion(); - - /* - * GFX PEIM module inside FSP binary is taking care of graphics - * initialization based on RUN_FSP_GOP Kconfig - * option and input VBT file. Hence no need to load/execute legacy VGA - * OpROM in order to initialize GFX. - * - * In case of non-FSP solution, SoC need to select VGA_ROM_RUN - * Kconfig to perform GFX initialization through VGA OpRom. - */ - if (CONFIG(RUN_FSP_GOP)) - return; - - /* IGD needs to Bus Master */ - uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* Initialize PCI device, load/execute BIOS Option ROM */ - pci_dev_init(dev); -} diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index dab7e145d1..d88709777a 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -1,16 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include #include #include -#include -#include +#include #include #include #include -#include #include -#include #include #include @@ -83,8 +80,6 @@ void graphics_soc_init(struct device *dev) { u32 ddi_buf_ctl; - intel_gma_init_igd_opregion(); - graphics_setup_panel(dev); /* @@ -97,32 +92,6 @@ void graphics_soc_init(struct device *dev) ddi_buf_ctl |= DDI_A_4_LANES; graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); } - - /* IGD needs to Bus Master */ - u32 reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* - * GFX PEIM module inside FSP binary is taking care of graphics - * initialization based on RUN_FSP_GOP Kconfig option and input - * VBT file. - * - * In case of non-FSP solution, SoC need to select another - * Kconfig to perform GFX initialization. - */ - if (CONFIG(RUN_FSP_GOP)) { - /* nothing to do */ - } else if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { - if (!acpi_is_wakeup_s3() && display_init_required()) { - int lightup_ok; - gma_gfxinit(&lightup_ok); - gfx_set_init_done(lightup_ok); - } - } else { - /* Initialize PCI device, load/execute BIOS Option ROM */ - pci_dev_init(dev); - } } const struct i915_gpu_controller_info * diff --git a/src/soc/intel/tigerlake/graphics.c b/src/soc/intel/tigerlake/graphics.c index ea90d44033..11aea72211 100644 --- a/src/soc/intel/tigerlake/graphics.c +++ b/src/soc/intel/tigerlake/graphics.c @@ -6,12 +6,7 @@ * Chapter number: 4 */ -#include #include -#include -#include -#include -#include #include #include @@ -19,28 +14,3 @@ uintptr_t fsp_soc_get_igd_bar(void) { return graphics_get_memory_base(); } - -void graphics_soc_init(struct device *dev) -{ - intel_gma_init_igd_opregion(); - - /* - * GFX PEIM module inside FSP binary is taking care of graphics - * initialization based on RUN_FSP_GOP Kconfig - * option and input VBT file. Hence no need to load/execute legacy VGA - * OpROM in order to initialize GFX. - * - * In case of non-FSP solution, SoC need to select VGA_ROM_RUN - * Kconfig to perform GFX initialization through VGA OpRom. - */ - if (CONFIG(RUN_FSP_GOP)) - return; - - /* IGD needs to Bus Master */ - uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* Initialize PCI device, load/execute BIOS Option ROM */ - pci_dev_init(dev); -} From dfdf102000584e38952122c74858e46fa69acc60 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 26 Apr 2020 19:26:36 +0200 Subject: [PATCH 320/405] intel/gma: Don't bluntly enable I/O The allocator should take care of this. Change-Id: I4ec88ebe23b4dcab069f764decc8b9b0c6e6a142 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/40726 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/northbridge/intel/gm45/gma.c | 2 +- src/northbridge/intel/haswell/gma.c | 2 +- src/northbridge/intel/i945/gma.c | 8 +++----- src/northbridge/intel/ironlake/gma.c | 2 +- src/northbridge/intel/pineview/gma.c | 2 +- src/northbridge/intel/sandybridge/gma.c | 2 +- src/northbridge/intel/x4x/gma.c | 2 +- src/soc/intel/broadwell/igd.c | 2 +- src/soc/intel/common/block/graphics/graphics.c | 2 +- 9 files changed, 11 insertions(+), 13 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index e9bd722da9..b48b3c3100 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -154,7 +154,7 @@ static void gma_func0_init(struct device *dev) /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + reg32 |= PCI_COMMAND_MASTER; pci_write_config32(dev, PCI_COMMAND, reg32); gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index ae9e25704d..fa67fe1982 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -464,7 +464,7 @@ static void gma_func0_init(struct device *dev) /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + reg32 |= PCI_COMMAND_MASTER; pci_write_config32(dev, PCI_COMMAND, reg32); /* Init graphics power management */ diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 181aee56e7..71ed4c42ea 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -674,8 +674,7 @@ static void gma_func0_init(struct device *dev) /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER - | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); + pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; @@ -717,10 +716,9 @@ static void gma_func1_init(struct device *dev) u32 reg32; u8 val; - /* IGD needs to be Bus Master, also enable IO access */ + /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); if (get_option(&val, "tft_brightness") == CB_SUCCESS) pci_write_config8(dev, 0xf4, val); diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c index 6de64fb065..6ba95d30fc 100644 --- a/src/northbridge/intel/ironlake/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -141,7 +141,7 @@ static void gma_func0_init(struct device *dev) /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + reg32 |= PCI_COMMAND_MASTER; pci_write_config32(dev, PCI_COMMAND, reg32); gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index e2d0d18bad..7e5b236bff 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -224,7 +224,7 @@ static void gma_func0_init(struct device *dev) /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + reg32 |= PCI_COMMAND_MASTER; pci_write_config32(dev, PCI_COMMAND, reg32); if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 82e43fc575..6e89b4ef35 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -591,7 +591,7 @@ static void gma_func0_init(struct device *dev) /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + reg32 |= PCI_COMMAND_MASTER; pci_write_config32(dev, PCI_COMMAND, reg32); /* Init graphics power management */ diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 004960fd8c..69b6f7103d 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -28,7 +28,7 @@ static void gma_func0_init(struct device *dev) /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + reg32 |= PCI_COMMAND_MASTER; pci_write_config32(dev, PCI_COMMAND, reg32); /* configure GMBUSFREQ */ diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index fbd45cb7fe..0f83937a77 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -498,7 +498,7 @@ static void igd_init(struct device *dev) /* IGD needs to be Bus Master */ u32 reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + reg32 |= PCI_COMMAND_MASTER; pci_write_config32(dev, PCI_COMMAND, reg32); gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 5110aad3d6..6b035bc736 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -47,7 +47,7 @@ static void gma_init(struct device *const dev) /* IGD needs to Bus Master */ u32 reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + reg32 |= PCI_COMMAND_MASTER; pci_write_config32(dev, PCI_COMMAND, reg32); if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { From dd597627295e0063e29ba43a0b2d6fdefb12c2c6 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 26 Apr 2020 19:46:35 +0200 Subject: [PATCH 321/405] intel/gma: Only enable bus mastering if we are going to use it Also fix wrong 32-bit writes. Change-Id: Ib038f0cd558223536da08ba2264774db11cd8357 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/40727 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/northbridge/intel/gm45/gma.c | 8 ++------ src/northbridge/intel/haswell/gma.c | 9 +++------ src/northbridge/intel/i945/gma.c | 13 ++++--------- src/northbridge/intel/ironlake/gma.c | 8 ++------ src/northbridge/intel/pineview/gma.c | 8 ++------ src/northbridge/intel/sandybridge/gma.c | 10 +++------- src/northbridge/intel/x4x/gma.c | 8 ++------ src/soc/intel/broadwell/igd.c | 8 +++----- src/soc/intel/common/block/graphics/graphics.c | 6 ++---- 9 files changed, 23 insertions(+), 55 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index b48b3c3100..6a51daee7c 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -144,7 +144,6 @@ static void gma_pm_init_post_vbios(struct device *const dev, static void gma_func0_init(struct device *dev) { - u32 reg32; u8 *mmio; u8 edid_data_lvds[128]; struct edid edid_lvds; @@ -152,16 +151,13 @@ static void gma_func0_init(struct device *dev) intel_gma_init_igd_opregion(); - /* IGD needs to be Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); if (gtt_res == NULL) return; mmio = res2mmio(gtt_res, 0, 0); + if (!CONFIG(NO_GFX_INIT)) + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); if (!CONFIG(MAINBOARD_USE_LIBGFXINIT)) { /* PCI Init, will run VBIOS */ diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index fa67fe1982..19341d4d37 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -458,21 +458,18 @@ static void gma_enable_swsci(void) static void gma_func0_init(struct device *dev) { int lightup_ok = 0; - u32 reg32; intel_gma_init_igd_opregion(); - /* IGD needs to be Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - /* Init graphics power management */ gma_pm_init_pre_vbios(dev); /* Pre panel init */ gma_setup_panel(dev); + if (!CONFIG(NO_GFX_INIT)) + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 71ed4c42ea..183c8f5b59 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -660,8 +660,6 @@ static void gma_ngi(struct device *const dev) static void gma_func0_init(struct device *dev) { - u32 reg32; - intel_gma_init_igd_opregion(); /* Unconditionally reset graphics */ @@ -672,9 +670,8 @@ static void gma_func0_init(struct device *dev) while (pci_read_config8(dev, GDRST) & 1) ; - /* IGD needs to be Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + if (!CONFIG(NO_GFX_INIT)) + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; @@ -713,12 +710,10 @@ static void gma_func0_disable(struct device *dev) static void gma_func1_init(struct device *dev) { - u32 reg32; u8 val; - /* IGD needs to be Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + if (!CONFIG(NO_GFX_INIT)) + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); if (get_option(&val, "tft_brightness") == CB_SUCCESS) pci_write_config8(dev, 0xf4, val); diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c index 6ba95d30fc..5ccf8a6a6b 100644 --- a/src/northbridge/intel/ironlake/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -135,14 +135,10 @@ static void gma_enable_swsci(void) static void gma_func0_init(struct device *dev) { - u32 reg32; - intel_gma_init_igd_opregion(); - /* IGD needs to be Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + if (!CONFIG(NO_GFX_INIT)) + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!gtt_res || !gtt_res->base) diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index 7e5b236bff..2f4b629ee6 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -218,14 +218,10 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info, static void gma_func0_init(struct device *dev) { - u32 reg32; - intel_gma_init_igd_opregion(); - /* IGD needs to be Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + if (!CONFIG(NO_GFX_INIT)) + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { /* PCI init, will run VBIOS */ diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 6e89b4ef35..150b61c9b9 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -585,18 +585,14 @@ static void gma_enable_swsci(void) static void gma_func0_init(struct device *dev) { - u32 reg32; - intel_gma_init_igd_opregion(); - /* IGD needs to be Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - /* Init graphics power management */ gma_pm_init_pre_vbios(dev); + if (!CONFIG(NO_GFX_INIT)) + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + if (!CONFIG(MAINBOARD_USE_LIBGFXINIT)) /* PCI Init, will run VBIOS */ pci_dev_init(dev); diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 69b6f7103d..ecbd63e616 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -22,14 +22,10 @@ static void gma_func0_init(struct device *dev) { - u32 reg32; - intel_gma_init_igd_opregion(); - /* IGD needs to be Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + if (!CONFIG(NO_GFX_INIT)) + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* configure GMBUSFREQ */ pci_update_config16(dev, 0xcc, ~0x1ff, 0xbc); diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 0f83937a77..41167b1cf9 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -496,15 +496,13 @@ static void igd_init(struct device *dev) intel_gma_init_igd_opregion(); - /* IGD needs to be Bus Master */ - u32 reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!gtt_res || !gtt_res->base) return; + if (!CONFIG(NO_GFX_INIT)) + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + /* Wait for any configured pre-graphics delay */ if (!acpi_is_wakeup_s3()) { #if CONFIG(CHROMEOS) diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 6b035bc736..ba4bc85a22 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -45,10 +45,8 @@ static void gma_init(struct device *const dev) if (CONFIG(RUN_FSP_GOP)) return; - /* IGD needs to Bus Master */ - u32 reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + if (!CONFIG(NO_GFX_INIT)) + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { if (!acpi_is_wakeup_s3() && display_init_required()) { From dd274e2971ff128742e362daef65181dc2818aaa Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 26 Apr 2020 20:37:32 +0200 Subject: [PATCH 322/405] soc/intel/gma: Move DDI-A 4-lane config to common code Change-Id: I0572dbbfb61e5e0129fe6a3a1b5894145d74fd0d Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/40728 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/Kconfig | 3 +++ src/soc/intel/cannonlake/graphics.c | 17 --------------- src/soc/intel/common/block/graphics/Kconfig | 5 +++++ .../intel/common/block/graphics/graphics.c | 8 +++++++ src/soc/intel/skylake/Kconfig | 1 + src/soc/intel/skylake/graphics.c | 21 +------------------ 6 files changed, 18 insertions(+), 37 deletions(-) diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 7a56d0d42d..f06d84b87c 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -25,6 +25,7 @@ config SOC_INTEL_COFFEELAKE select SOC_INTEL_CANNONLAKE_BASE select FSP_USES_CB_STACK select HAVE_INTEL_FSP_REPO + select SOC_INTEL_CONFIGURE_DDI_A_4_LANES help Intel Coffeelake support @@ -33,6 +34,7 @@ config SOC_INTEL_WHISKEYLAKE select SOC_INTEL_CANNONLAKE_BASE select FSP_USES_CB_STACK select HAVE_INTEL_FSP_REPO + select SOC_INTEL_CONFIGURE_DDI_A_4_LANES help Intel Whiskeylake support @@ -41,6 +43,7 @@ config SOC_INTEL_COMETLAKE select SOC_INTEL_CANNONLAKE_BASE select FSP_USES_CB_STACK select HAVE_INTEL_FSP_REPO + select SOC_INTEL_CONFIGURE_DDI_A_4_LANES help Intel Cometlake support diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index cd5e773dbb..5fbe0d53a3 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -11,20 +11,3 @@ uintptr_t fsp_soc_get_igd_bar(void) { return graphics_get_memory_base(); } - -void graphics_soc_init(struct device *dev) -{ - uint32_t ddi_buf_ctl; - - /* - * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. - * This will allow the kernel to use 4-lane eDP links properly - * if the VBIOS or GOP driver do not execute. - */ - ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); - if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) { - ddi_buf_ctl |= (DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED | - DDI_BUF_IS_IDLE); - graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); - } -} diff --git a/src/soc/intel/common/block/graphics/Kconfig b/src/soc/intel/common/block/graphics/Kconfig index 4ab92001c3..e632cb9bb0 100644 --- a/src/soc/intel/common/block/graphics/Kconfig +++ b/src/soc/intel/common/block/graphics/Kconfig @@ -2,3 +2,8 @@ config SOC_INTEL_COMMON_BLOCK_GRAPHICS bool help Intel Processor common Graphics support + +config SOC_INTEL_CONFIGURE_DDI_A_4_LANES + bool + help + Selected by platforms that require DDI-A bifurcation setup. diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index ba4bc85a22..e2c90600ac 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include #include #include #include @@ -34,6 +35,13 @@ static void gma_init(struct device *const dev) /* SoC specific configuration. */ graphics_soc_init(dev); + if (CONFIG(SOC_INTEL_CONFIGURE_DDI_A_4_LANES) && !acpi_is_wakeup_s3()) { + const u32 ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); + /* Only program if the buffer is not enabled yet. */ + if (!(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) + graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl | DDI_A_4_LANES); + } + /* * GFX PEIM module inside FSP binary is taking care of graphics * initialization based on RUN_FSP_GOP Kconfig option and input diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 55437f356e..27c108497c 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -74,6 +74,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT + select SOC_INTEL_CONFIGURE_DDI_A_4_LANES select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index d88709777a..27cb87481c 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -16,7 +15,7 @@ uintptr_t fsp_soc_get_igd_bar(void) return graphics_get_memory_base(); } -static void graphics_setup_panel(struct device *dev) +void graphics_soc_init(struct device *dev) { struct soc_intel_skylake_config *conf = config_of(dev); struct resource *mmio_res; @@ -76,24 +75,6 @@ static void graphics_setup_panel(struct device *dev) } } -void graphics_soc_init(struct device *dev) -{ - u32 ddi_buf_ctl; - - graphics_setup_panel(dev); - - /* - * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. - * This will allow the kernel to use 4-lane eDP links properly - * if the VBIOS or GOP driver does not execute. - */ - ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); - if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) { - ddi_buf_ctl |= DDI_A_4_LANES; - graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); - } -} - const struct i915_gpu_controller_info * intel_igd_get_controller_info(const struct device *device) { From bd4af105c4b5a0bffc890024d5112a73443c102f Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 26 Apr 2020 20:43:42 +0200 Subject: [PATCH 323/405] soc/intel/gma: Implement fsp_soc_get_igd_bar() in common code `fsp/util.h` draws incompatible UDK headers in. Hence, we have to declare it locally again. Change-Id: Iaa5981088eeb5c36f765d6332ae47a38a6a4c875 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/40729 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/Makefile.inc | 1 - src/soc/intel/apollolake/graphics.c | 10 ---------- src/soc/intel/cannonlake/Makefile.inc | 1 - src/soc/intel/cannonlake/graphics.c | 13 ------------- src/soc/intel/common/block/graphics/graphics.c | 11 +++++++++++ src/soc/intel/icelake/Makefile.inc | 1 - src/soc/intel/icelake/graphics.c | 10 ---------- src/soc/intel/jasperlake/Makefile.inc | 1 - src/soc/intel/jasperlake/graphics.c | 10 ---------- src/soc/intel/skylake/graphics.c | 5 ----- src/soc/intel/tigerlake/Makefile.inc | 1 - src/soc/intel/tigerlake/graphics.c | 16 ---------------- 12 files changed, 11 insertions(+), 69 deletions(-) delete mode 100644 src/soc/intel/apollolake/graphics.c delete mode 100644 src/soc/intel/cannonlake/graphics.c delete mode 100644 src/soc/intel/icelake/graphics.c delete mode 100644 src/soc/intel/jasperlake/graphics.c delete mode 100644 src/soc/intel/tigerlake/graphics.c diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index a20a554be1..517c8ca97d 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -54,7 +54,6 @@ ramstage-y += cpu.c ramstage-y += chip.c ramstage-y += cse.c ramstage-y += elog.c -ramstage-y += graphics.c ramstage-y += gspi.c ramstage-y += heci.c ramstage-y += i2c.c diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c deleted file mode 100644 index c8d282d837..0000000000 --- a/src/soc/intel/apollolake/graphics.c +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include - -uintptr_t fsp_soc_get_igd_bar(void) -{ - return graphics_get_memory_base(); -} diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index e0605817ae..96f1f97d0e 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -36,7 +36,6 @@ ramstage-y += cpu.c ramstage-y += elog.c ramstage-y += finalize.c ramstage-y += fsp_params.c -ramstage-y += graphics.c ramstage-y += gspi.c ramstage-y += i2c.c ramstage-y += lockdown.c diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c deleted file mode 100644 index 5fbe0d53a3..0000000000 --- a/src/soc/intel/cannonlake/graphics.c +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include -#include -#include -#include - -uintptr_t fsp_soc_get_igd_bar(void) -{ - return graphics_get_memory_base(); -} diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index e2c90600ac..f232ee545f 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -12,6 +12,7 @@ #include #include #include +#include /* SoC Overrides */ __weak void graphics_soc_init(struct device *dev) @@ -154,6 +155,16 @@ void graphics_gtt_rmw(unsigned long reg, uint32_t andmask, uint32_t ormask) graphics_gtt_write(reg, val); } +/* + * fsp_soc_get_igd_bar() is declared in , + * but that draws incompatible UDK headers in. + */ +uintptr_t fsp_soc_get_igd_bar(void); +uintptr_t fsp_soc_get_igd_bar(void) +{ + return graphics_get_memory_base(); +} + static const struct device_operations graphics_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index f30816e003..05f4846963 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -35,7 +35,6 @@ ramstage-y += espi.c ramstage-y += finalize.c ramstage-y += fsp_params.c ramstage-y += gpio.c -ramstage-y += graphics.c ramstage-y += lockdown.c ramstage-y += p2sb.c ramstage-y += pmc.c diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c deleted file mode 100644 index c8d282d837..0000000000 --- a/src/soc/intel/icelake/graphics.c +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include - -uintptr_t fsp_soc_get_igd_bar(void) -{ - return graphics_get_memory_base(); -} diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index c5ad4d2095..1cba218700 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -36,7 +36,6 @@ ramstage-y += espi.c ramstage-y += finalize.c ramstage-y += fsp_params.c ramstage-y += gpio.c -ramstage-y += graphics.c ramstage-y += lockdown.c ramstage-y += p2sb.c ramstage-y += pmc.c diff --git a/src/soc/intel/jasperlake/graphics.c b/src/soc/intel/jasperlake/graphics.c deleted file mode 100644 index c8d282d837..0000000000 --- a/src/soc/intel/jasperlake/graphics.c +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include - -uintptr_t fsp_soc_get_igd_bar(void) -{ - return graphics_get_memory_base(); -} diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index 27cb87481c..4ecf67a98d 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -10,11 +10,6 @@ #include #include -uintptr_t fsp_soc_get_igd_bar(void) -{ - return graphics_get_memory_base(); -} - void graphics_soc_init(struct device *dev) { struct soc_intel_skylake_config *conf = config_of(dev); diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 9ff767cfec..c4f71c78b3 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -36,7 +36,6 @@ ramstage-y += espi.c ramstage-y += finalize.c ramstage-y += fsp_params.c ramstage-y += gpio.c -ramstage-y += graphics.c ramstage-y += lockdown.c ramstage-y += p2sb.c ramstage-y += pmc.c diff --git a/src/soc/intel/tigerlake/graphics.c b/src/soc/intel/tigerlake/graphics.c deleted file mode 100644 index 11aea72211..0000000000 --- a/src/soc/intel/tigerlake/graphics.c +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * This file is created based on Intel Tiger Lake Processor SA Datasheet - * Document number: 571131 - * Chapter number: 4 - */ - -#include -#include -#include - -uintptr_t fsp_soc_get_igd_bar(void) -{ - return graphics_get_memory_base(); -} From d64779acaaf7af27b5ead59dac0bc773d482a90f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 26 May 2020 23:57:48 +0200 Subject: [PATCH 324/405] mb/asrock/h110m: Remove duplicated PmTimerDisabled This option appears twice in the devicetree. Drop one instance. Change-Id: I2121770688f64542a02c777d4175fe4739ebb28a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41752 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/mainboard/asrock/h110m/devicetree.cb | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 254eff853c..1327a3615f 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -135,7 +135,6 @@ chip soc/intel/skylake }" register "EnableLan" = "0" - register "PmTimerDisabled" = "0" # USB register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" From 01a9493cfc2d79306053f6b5c96b0c916170ed28 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 27 May 2020 00:01:55 +0200 Subject: [PATCH 325/405] mb/intel/saddlebrook: Remove duplicated PmTimerDisabled This option appears twice in the devicetree. Drop one instance. Change-Id: Ib8c93665048e8fa9fcff39ca5a015cea09ceaa03 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41753 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/mainboard/intel/saddlebrook/devicetree.cb | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 4811a41491..7c2a7d7f35 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -184,8 +184,6 @@ chip soc/intel/skylake register "pirqg_routing" = "0x0b" register "pirqh_routing" = "0x0b" - register "PmTimerDisabled" = "0" - register "EnableSata" = "1" register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ \ From fc9b8b916f7bc0c6ac1579b915937ed23ea3327a Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 26 May 2020 23:31:56 +0200 Subject: [PATCH 326/405] soc/amd/picasso/smu: only print time for actual command execution When waiting for the SMU to be ready to accept a new command, the time spent waiting shouldn't be printed as command execution time. Also fix the time unit in the print statement. Change-Id: I6b97b11cd9efae7029779ee2096d4f2224cecd72 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/41751 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/picasso/smu.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/soc/amd/picasso/smu.c b/src/soc/amd/picasso/smu.c index cfe2240021..4a373ce273 100644 --- a/src/soc/amd/picasso/smu.c +++ b/src/soc/amd/picasso/smu.c @@ -23,7 +23,7 @@ static void smu_write32(uint32_t reg, uint32_t val) #define SMU_MESG_RESP_OK 0x01 /* returns SMU_MESG_RESP_OK, SMU_MESG_RESP_TIMEOUT or a negative number */ -static int32_t smu_poll_response(void) +static int32_t smu_poll_response(bool print_command_duration) { struct stopwatch sw; const long timeout_ms = 10 * MSECS_PER_SEC; @@ -34,7 +34,8 @@ static int32_t smu_poll_response(void) do { result = smu_read32(REG_ADDR_MESG_RESP); if (result) { - printk(BIOS_SPEW, "SMU command consumed %ld msecs\n", + if (print_command_duration) + printk(BIOS_SPEW, "SMU command consumed %ld usecs\n", stopwatch_duration_usecs(&sw)); return result; } @@ -53,7 +54,7 @@ enum cb_err send_smu_message(enum smu_message_id id, struct smu_payload *arg) size_t i; /* wait until SMU can process a new request; don't care if an old request failed */ - if (smu_poll_response() == SMU_MESG_RESP_TIMEOUT) + if (smu_poll_response(false) == SMU_MESG_RESP_TIMEOUT) return CB_ERR; /* clear response register */ @@ -67,7 +68,7 @@ enum cb_err send_smu_message(enum smu_message_id id, struct smu_payload *arg) smu_write32(REG_ADDR_MESG_ID, id); /* wait until SMU has processed the message and check if it was successful */ - if (smu_poll_response() != SMU_MESG_RESP_OK) + if (smu_poll_response(true) != SMU_MESG_RESP_OK) return CB_ERR; /* copy returned values */ From b3c41329fdca84a251c183bbc2b0767978e9d96f Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Wed, 20 May 2020 14:07:41 -0600 Subject: [PATCH 327/405] mb/google/zork: Add Picasso based Zork mainboard and variants This is a copy of the mb/google/zork directory from the chromiumos coreboot-zork branch. This was from commit 29308ac8606. See https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/29308ac8606/src/mainboard/google/zork Changes: * Minor changes to make the board build. * Add bootblock.c. * Modify romstage.c * Removed the FSP_X configs from zork/Kconfig since they should be set in picasso/Kconfig. picasso/Kconfig doesn't currently define the binaries since they haven't been published. To get a working build a custom config that sets FSP_X_FILE is required. BUG=b:157140753 TEST=Build trembyle and boot to OS Signed-off-by: Raul E Rangel Change-Id: I3933fa54e3f603985a0818852a1c77d8e248484f Reviewed-on: https://review.coreboot.org/c/coreboot/+/41581 Reviewed-by: Furquan Shaikh Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/mainboard/google/zork/Kconfig | 135 +++++++ src/mainboard/google/zork/Kconfig.name | 21 ++ src/mainboard/google/zork/Makefile.inc | 30 ++ src/mainboard/google/zork/board_info.txt | 6 + src/mainboard/google/zork/bootblock.c | 13 + src/mainboard/google/zork/chromeos.c | 34 ++ src/mainboard/google/zork/chromeos.fmd | 38 ++ src/mainboard/google/zork/dsdt.asl | 67 ++++ src/mainboard/google/zork/ec.c | 27 ++ src/mainboard/google/zork/mainboard.c | 255 +++++++++++++ src/mainboard/google/zork/romstage.c | 29 ++ src/mainboard/google/zork/sku_id.c | 17 + src/mainboard/google/zork/smihandler.c | 28 ++ ...R4-2666-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex | 32 ++ ...DR4-2666-8Gbx1-4Bk-4BkG-16x10-8bit.spd.hex | 32 ++ ...DR4-2666-8Gbx2-4Bk-2BkG-16x10-8bit.spd.hex | 32 ++ ...DR4-2666-8Gbx2-4Bk-4BkG-16x10-8bit.spd.hex | 32 ++ ...4-3200-16Gbx1-4Bk-2BkG-16x10-16bit.spd.hex | 32 ++ ...4-3200-16Gbx1-4Bk-2BkG-17x10-16bit.spd.hex | 32 ++ ...R4-3200-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex | 32 ++ .../google/zork/spd/DDR4-template.spd.hex | 336 ++++++++++++++++++ src/mainboard/google/zork/spd/Makefile.inc | 29 ++ src/mainboard/google/zork/spd/empty.spd.hex | 33 ++ .../zork/spd/hynix-H5AN8G6NCJR-VKC.spd.hex | 331 +++++++++++++++++ .../zork/spd/hynix-H5AN8G6NDJR-XNC.spd.hex | 33 ++ .../zork/spd/hynix-H5ANAG6NCMR-VKC.spd.hex | 33 ++ .../zork/spd/hynix-H5ANAG6NCMR-XNC.spd.hex | 33 ++ .../zork/spd/hynix-HMA851S6CJR6N-VK.spd.hex | 331 +++++++++++++++++ .../zork/spd/hynix-HMAA1GS6CMR6N-VK.spd.hex | 331 +++++++++++++++++ .../spd/micron-MT40A1G16KD-062E-E.spd.hex | 33 ++ .../spd/micron-MT40A1G16KNR-075-E.spd.hex | 33 ++ .../spd/micron-MT40A512M16TB-062E-J.spd.hex | 33 ++ .../zork/spd/samsung-K4A8G165WC-BCTD.spd.hex | 33 ++ .../zork/spd/samsung-K4A8G165WC-BCWE.spd.hex | 33 ++ .../zork/spd/samsung-K4AAG165WA-BCWE.spd.hex | 33 ++ .../zork/spd/samsung-K4AAG165WB-MCTD.spd.hex | 33 ++ .../zork/variants/baseboard/Makefile.inc | 48 +++ .../zork/variants/baseboard/devicetree.cb | 189 ++++++++++ .../baseboard/fsps_baseboard_dalboz.c | 75 ++++ .../baseboard/fsps_baseboard_trembyle.c | 187 ++++++++++ .../baseboard/gpio_baseboard_dalboz.c | 238 +++++++++++++ .../baseboard/gpio_baseboard_trembyle.c | 247 +++++++++++++ .../google/zork/variants/baseboard/helpers.c | 115 ++++++ .../include/baseboard/acpi/audio.asl | 45 +++ .../include/baseboard/acpi/mainboard.asl | 15 + .../include/baseboard/acpi/sb_fch.asl | 246 +++++++++++++ .../include/baseboard/acpi/sleep.asl | 73 ++++ .../include/baseboard/acpi/thermal.asl | 76 ++++ .../variants/baseboard/include/baseboard/ec.h | 77 ++++ .../baseboard/include/baseboard/gpio.h | 77 ++++ .../baseboard/include/baseboard/thermal.h | 24 ++ .../baseboard/include/baseboard/variants.h | 57 +++ .../google/zork/variants/baseboard/tpm_tis.c | 10 + .../google/zork/variants/berknip/Makefile.inc | 7 + .../google/zork/variants/berknip/gpio.c | 34 ++ .../berknip/include/variant/acpi/audio.asl | 3 + .../include/variant/acpi/mainboard.asl | 3 + .../berknip/include/variant/acpi/sleep.asl | 3 + .../berknip/include/variant/acpi/thermal.asl | 3 + .../variants/berknip/include/variant/ec.h | 3 + .../variants/berknip/include/variant/gpio.h | 3 + .../berknip/include/variant/thermal.h | 3 + .../zork/variants/berknip/overridetree.cb | 91 +++++ .../google/zork/variants/berknip/romstage.c | 38 ++ .../zork/variants/berknip/spd/Makefile.inc | 26 ++ .../google/zork/variants/dalboz/Makefile.inc | 8 + .../google/zork/variants/dalboz/gpio.c | 37 ++ .../dalboz/include/variant/acpi/audio.asl | 3 + .../dalboz/include/variant/acpi/mainboard.asl | 3 + .../dalboz/include/variant/acpi/sleep.asl | 3 + .../dalboz/include/variant/acpi/thermal.asl | 3 + .../zork/variants/dalboz/include/variant/ec.h | 3 + .../variants/dalboz/include/variant/gpio.h | 3 + .../variants/dalboz/include/variant/thermal.h | 3 + .../zork/variants/dalboz/overridetree.cb | 105 ++++++ .../google/zork/variants/dalboz/romstage.c | 25 ++ .../zork/variants/dalboz/spd/Makefile.inc | 25 ++ .../google/zork/variants/dalboz/variant.c | 201 +++++++++++ .../google/zork/variants/ezkinil/Makefile.inc | 6 + .../google/zork/variants/ezkinil/gpio.c | 34 ++ .../ezkinil/include/variant/acpi/audio.asl | 3 + .../include/variant/acpi/mainboard.asl | 3 + .../ezkinil/include/variant/acpi/sleep.asl | 3 + .../ezkinil/include/variant/acpi/thermal.asl | 3 + .../variants/ezkinil/include/variant/ec.h | 3 + .../variants/ezkinil/include/variant/gpio.h | 3 + .../ezkinil/include/variant/thermal.h | 3 + .../zork/variants/ezkinil/overridetree.cb | 92 +++++ .../zork/variants/ezkinil/spd/Makefile.inc | 25 ++ .../google/zork/variants/ezkinil/variant.c | 34 ++ .../zork/variants/morphius/Makefile.inc | 7 + .../google/zork/variants/morphius/gpio.c | 48 +++ .../morphius/include/variant/acpi/audio.asl | 3 + .../include/variant/acpi/mainboard.asl | 3 + .../morphius/include/variant/acpi/sleep.asl | 3 + .../morphius/include/variant/acpi/thermal.asl | 3 + .../variants/morphius/include/variant/ec.h | 6 + .../variants/morphius/include/variant/gpio.h | 3 + .../morphius/include/variant/thermal.h | 3 + .../zork/variants/morphius/overridetree.cb | 83 +++++ .../google/zork/variants/morphius/romstage.c | 42 +++ .../zork/variants/morphius/spd/Makefile.inc | 26 ++ .../zork/variants/trembyle/Makefile.inc | 5 + .../google/zork/variants/trembyle/gpio.c | 48 +++ .../trembyle/include/variant/acpi/audio.asl | 3 + .../include/variant/acpi/mainboard.asl | 3 + .../trembyle/include/variant/acpi/sleep.asl | 3 + .../trembyle/include/variant/acpi/thermal.asl | 3 + .../variants/trembyle/include/variant/ec.h | 3 + .../variants/trembyle/include/variant/gpio.h | 3 + .../trembyle/include/variant/thermal.h | 3 + .../zork/variants/trembyle/overridetree.cb | 162 +++++++++ src/mainboard/google/zork/verstage.c | 35 ++ 113 files changed, 5796 insertions(+) create mode 100644 src/mainboard/google/zork/Kconfig create mode 100644 src/mainboard/google/zork/Kconfig.name create mode 100644 src/mainboard/google/zork/Makefile.inc create mode 100644 src/mainboard/google/zork/board_info.txt create mode 100644 src/mainboard/google/zork/bootblock.c create mode 100644 src/mainboard/google/zork/chromeos.c create mode 100644 src/mainboard/google/zork/chromeos.fmd create mode 100644 src/mainboard/google/zork/dsdt.asl create mode 100644 src/mainboard/google/zork/ec.c create mode 100644 src/mainboard/google/zork/mainboard.c create mode 100644 src/mainboard/google/zork/romstage.c create mode 100644 src/mainboard/google/zork/sku_id.c create mode 100644 src/mainboard/google/zork/smihandler.c create mode 100644 src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex create mode 100644 src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-4BkG-16x10-8bit.spd.hex create mode 100644 src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-2BkG-16x10-8bit.spd.hex create mode 100644 src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-4BkG-16x10-8bit.spd.hex create mode 100644 src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-16x10-16bit.spd.hex create mode 100644 src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-17x10-16bit.spd.hex create mode 100644 src/mainboard/google/zork/spd/DDR4-3200-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex create mode 100644 src/mainboard/google/zork/spd/DDR4-template.spd.hex create mode 100644 src/mainboard/google/zork/spd/Makefile.inc create mode 100644 src/mainboard/google/zork/spd/empty.spd.hex create mode 100644 src/mainboard/google/zork/spd/hynix-H5AN8G6NCJR-VKC.spd.hex create mode 100644 src/mainboard/google/zork/spd/hynix-H5AN8G6NDJR-XNC.spd.hex create mode 100644 src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-VKC.spd.hex create mode 100644 src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-XNC.spd.hex create mode 100644 src/mainboard/google/zork/spd/hynix-HMA851S6CJR6N-VK.spd.hex create mode 100644 src/mainboard/google/zork/spd/hynix-HMAA1GS6CMR6N-VK.spd.hex create mode 100644 src/mainboard/google/zork/spd/micron-MT40A1G16KD-062E-E.spd.hex create mode 100644 src/mainboard/google/zork/spd/micron-MT40A1G16KNR-075-E.spd.hex create mode 100644 src/mainboard/google/zork/spd/micron-MT40A512M16TB-062E-J.spd.hex create mode 100644 src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCTD.spd.hex create mode 100644 src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCWE.spd.hex create mode 100644 src/mainboard/google/zork/spd/samsung-K4AAG165WA-BCWE.spd.hex create mode 100644 src/mainboard/google/zork/spd/samsung-K4AAG165WB-MCTD.spd.hex create mode 100644 src/mainboard/google/zork/variants/baseboard/Makefile.inc create mode 100644 src/mainboard/google/zork/variants/baseboard/devicetree.cb create mode 100644 src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c create mode 100644 src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c create mode 100644 src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c create mode 100644 src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c create mode 100644 src/mainboard/google/zork/variants/baseboard/helpers.c create mode 100644 src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/audio.asl create mode 100644 src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/mainboard.asl create mode 100644 src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sb_fch.asl create mode 100644 src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sleep.asl create mode 100644 src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl create mode 100644 src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h create mode 100644 src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h create mode 100644 src/mainboard/google/zork/variants/baseboard/include/baseboard/thermal.h create mode 100644 src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h create mode 100644 src/mainboard/google/zork/variants/baseboard/tpm_tis.c create mode 100644 src/mainboard/google/zork/variants/berknip/Makefile.inc create mode 100644 src/mainboard/google/zork/variants/berknip/gpio.c create mode 100644 src/mainboard/google/zork/variants/berknip/include/variant/acpi/audio.asl create mode 100644 src/mainboard/google/zork/variants/berknip/include/variant/acpi/mainboard.asl create mode 100644 src/mainboard/google/zork/variants/berknip/include/variant/acpi/sleep.asl create mode 100644 src/mainboard/google/zork/variants/berknip/include/variant/acpi/thermal.asl create mode 100644 src/mainboard/google/zork/variants/berknip/include/variant/ec.h create mode 100644 src/mainboard/google/zork/variants/berknip/include/variant/gpio.h create mode 100644 src/mainboard/google/zork/variants/berknip/include/variant/thermal.h create mode 100644 src/mainboard/google/zork/variants/berknip/overridetree.cb create mode 100644 src/mainboard/google/zork/variants/berknip/romstage.c create mode 100644 src/mainboard/google/zork/variants/berknip/spd/Makefile.inc create mode 100644 src/mainboard/google/zork/variants/dalboz/Makefile.inc create mode 100644 src/mainboard/google/zork/variants/dalboz/gpio.c create mode 100644 src/mainboard/google/zork/variants/dalboz/include/variant/acpi/audio.asl create mode 100644 src/mainboard/google/zork/variants/dalboz/include/variant/acpi/mainboard.asl create mode 100644 src/mainboard/google/zork/variants/dalboz/include/variant/acpi/sleep.asl create mode 100644 src/mainboard/google/zork/variants/dalboz/include/variant/acpi/thermal.asl create mode 100644 src/mainboard/google/zork/variants/dalboz/include/variant/ec.h create mode 100644 src/mainboard/google/zork/variants/dalboz/include/variant/gpio.h create mode 100644 src/mainboard/google/zork/variants/dalboz/include/variant/thermal.h create mode 100644 src/mainboard/google/zork/variants/dalboz/overridetree.cb create mode 100644 src/mainboard/google/zork/variants/dalboz/romstage.c create mode 100644 src/mainboard/google/zork/variants/dalboz/spd/Makefile.inc create mode 100644 src/mainboard/google/zork/variants/dalboz/variant.c create mode 100644 src/mainboard/google/zork/variants/ezkinil/Makefile.inc create mode 100644 src/mainboard/google/zork/variants/ezkinil/gpio.c create mode 100644 src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/audio.asl create mode 100644 src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/mainboard.asl create mode 100644 src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/sleep.asl create mode 100644 src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/thermal.asl create mode 100644 src/mainboard/google/zork/variants/ezkinil/include/variant/ec.h create mode 100644 src/mainboard/google/zork/variants/ezkinil/include/variant/gpio.h create mode 100644 src/mainboard/google/zork/variants/ezkinil/include/variant/thermal.h create mode 100644 src/mainboard/google/zork/variants/ezkinil/overridetree.cb create mode 100644 src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc create mode 100644 src/mainboard/google/zork/variants/ezkinil/variant.c create mode 100644 src/mainboard/google/zork/variants/morphius/Makefile.inc create mode 100644 src/mainboard/google/zork/variants/morphius/gpio.c create mode 100644 src/mainboard/google/zork/variants/morphius/include/variant/acpi/audio.asl create mode 100644 src/mainboard/google/zork/variants/morphius/include/variant/acpi/mainboard.asl create mode 100644 src/mainboard/google/zork/variants/morphius/include/variant/acpi/sleep.asl create mode 100644 src/mainboard/google/zork/variants/morphius/include/variant/acpi/thermal.asl create mode 100644 src/mainboard/google/zork/variants/morphius/include/variant/ec.h create mode 100644 src/mainboard/google/zork/variants/morphius/include/variant/gpio.h create mode 100644 src/mainboard/google/zork/variants/morphius/include/variant/thermal.h create mode 100644 src/mainboard/google/zork/variants/morphius/overridetree.cb create mode 100644 src/mainboard/google/zork/variants/morphius/romstage.c create mode 100644 src/mainboard/google/zork/variants/morphius/spd/Makefile.inc create mode 100644 src/mainboard/google/zork/variants/trembyle/Makefile.inc create mode 100644 src/mainboard/google/zork/variants/trembyle/gpio.c create mode 100644 src/mainboard/google/zork/variants/trembyle/include/variant/acpi/audio.asl create mode 100644 src/mainboard/google/zork/variants/trembyle/include/variant/acpi/mainboard.asl create mode 100644 src/mainboard/google/zork/variants/trembyle/include/variant/acpi/sleep.asl create mode 100644 src/mainboard/google/zork/variants/trembyle/include/variant/acpi/thermal.asl create mode 100644 src/mainboard/google/zork/variants/trembyle/include/variant/ec.h create mode 100644 src/mainboard/google/zork/variants/trembyle/include/variant/gpio.h create mode 100644 src/mainboard/google/zork/variants/trembyle/include/variant/thermal.h create mode 100644 src/mainboard/google/zork/variants/trembyle/overridetree.cb create mode 100644 src/mainboard/google/zork/verstage.c diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig new file mode 100644 index 0000000000..343b30ba09 --- /dev/null +++ b/src/mainboard/google/zork/Kconfig @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_GOOGLE_BASEBOARD_TREMBYLE + def_bool n + +config BOARD_GOOGLE_BASEBOARD_DALBOZ + def_bool n + +if BOARD_GOOGLE_BASEBOARD_TREMBYLE || BOARD_GOOGLE_BASEBOARD_DALBOZ + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_AMD_COMMON_BLOCK_USE_ESPI + select SOC_AMD_PICASSO + select VGA_BIOS + select BOARD_ROMSIZE_KB_16384 + select DISABLE_SPI_FLASH_ROM_SHARING + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_I2C_TUNNEL + select EC_GOOGLE_CHROMEEC_SKUID + select HAVE_ACPI_TABLES + select GFXUMA + select GOOGLE_SMBIOS_MAINBOARD_VERSION + select MAINBOARD_HAS_CHROMEOS + select PICASSO_UART + select MAINBOARD_HAS_I2C_TPM_CR50 + select MAINBOARD_HAS_TPM2 + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_COMMON_CLOCK + select PCIEXP_L1_SUB_STATE + select HAVE_EM100_SUPPORT + select SYSTEM_TYPE_LAPTOP + select DRIVERS_GENERIC_MAX98357A + select HAVE_ACPI_RESUME + select DRIVERS_USB_ACPI + +config MAINBOARD_DIR + string + default google/zork + +config VARIANT_DIR + string + default "ezkinil" if BOARD_GOOGLE_EZKINIL + default "morphius" if BOARD_GOOGLE_MORPHIUS + default "trembyle" if BOARD_GOOGLE_TREMBYLE + default "dalboz" if BOARD_GOOGLE_DALBOZ + default "berknip" if BOARD_GOOGLE_BERKNIP + +config MAINBOARD_PART_NUMBER + string + default "Ezkinil" if BOARD_GOOGLE_EZKINIL + default "Morphius" if BOARD_GOOGLE_MORPHIUS + default "Trembyle" if BOARD_GOOGLE_TREMBYLE + default "Dalboz" if BOARD_GOOGLE_DALBOZ + default "Berknip" if BOARD_GOOGLE_BERKNIP + +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config MAINBOARD_FAMILY + string + default "Google_Zork" + +config MAX_CPUS + int + default 8 + +config IRQ_SLOT_COUNT + int + default 11 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VBOOT + select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_LID_SWITCH + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + +config VBOOT_VBNV_OFFSET + hex + default 0x2A + +config CHROMEOS + # Use default libpayload config + select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE + +config AMD_FWM_POSITION_INDEX + int + default 2 + +config DRIVER_TPM_I2C_BUS + hex + default 0x03 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x50 + +config USE_OEM_BIN + bool "Add an oem.bin file" + help + Add an oem.bin file to identify the manufacturer in SMBIOS, overriding the + CONFIG_MAINBOARD_SMBIOS_MANUFACTURER value. + +config OEM_BIN_FILE + string "OEM ID table" + depends on USE_OEM_BIN + default "" + +config VARIANT_HAS_FW_CONFIG + bool + help + Honor FW_CONFIG in CBI. + +config VARIANT_BOARD_VER_FW_CONFIG_VALID + int + default 256 + depends on VARIANT_HAS_FW_CONFIG + help + Which board version did FW_CONFIG become valid in CBI. + +endif # BOARD_GOOGLE_BASEBOARD_TREMBYLE || BOARD_GOOGLE_BASEBOARD_DALBOZ diff --git a/src/mainboard/google/zork/Kconfig.name b/src/mainboard/google/zork/Kconfig.name new file mode 100644 index 0000000000..065f60cb0a --- /dev/null +++ b/src/mainboard/google/zork/Kconfig.name @@ -0,0 +1,21 @@ +comment "Zork" + +config BOARD_GOOGLE_DALBOZ + bool "-> Dalboz" + select BOARD_GOOGLE_BASEBOARD_DALBOZ + +config BOARD_GOOGLE_EZKINIL + bool "-> Ezkinil" + select BOARD_GOOGLE_BASEBOARD_TREMBYLE + +config BOARD_GOOGLE_MORPHIUS + bool "-> Morphius" + select BOARD_GOOGLE_BASEBOARD_TREMBYLE + +config BOARD_GOOGLE_TREMBYLE + bool "-> Trembyle" + select BOARD_GOOGLE_BASEBOARD_TREMBYLE + +config BOARD_GOOGLE_BERKNIP + bool "-> Berknip" + select BOARD_GOOGLE_BASEBOARD_TREMBYLE diff --git a/src/mainboard/google/zork/Makefile.inc b/src/mainboard/google/zork/Makefile.inc new file mode 100644 index 0000000000..07628c186b --- /dev/null +++ b/src/mainboard/google/zork/Makefile.inc @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c + +romstage-y += chromeos.c +romstage-y += ec.c +romstage-y += sku_id.c + +ramstage-y += chromeos.c +ramstage-y += ec.c +ramstage-y += sku_id.c + +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +verstage-y += memlayout.ld +verstage-y += verstage.c +else +verstage-y += chromeos.c +verstage-y += ec.c +endif + +smm-y += smihandler.c + +subdirs-y += variants/baseboard +subdirs-y += spd + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include/baseboard/acpi + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/zork/board_info.txt b/src/mainboard/google/zork/board_info.txt new file mode 100644 index 0000000000..947c0420b1 --- /dev/null +++ b/src/mainboard/google/zork/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Trembyle +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/google/zork/bootblock.c b/src/mainboard/google/zork/bootblock.c new file mode 100644 index 0000000000..0e7af52ecd --- /dev/null +++ b/src/mainboard/google/zork/bootblock.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void bootblock_mainboard_early_init(void) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + + gpios = variant_early_gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); +} diff --git a/src/mainboard/google/zork/chromeos.c b/src/mainboard/google/zork/chromeos.c new file mode 100644 index 0000000000..2256ef24b0 --- /dev/null +++ b/src/mainboard/google/zork/chromeos.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_write_protect_state(void) +{ + /* Write protect on zork is active low, so invert it here */ + return !gpio_get(CROS_WP_GPIO); +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/zork/chromeos.fmd b/src/mainboard/google/zork/chromeos.fmd new file mode 100644 index 0000000000..963d1ee841 --- /dev/null +++ b/src/mainboard/google/zork/chromeos.fmd @@ -0,0 +1,38 @@ +FLASH@0xFF000000 0x1000000 { + SI_BIOS@0x0 0x1000000 { + UNIFIED_MRC_CACHE@0x0 0x21000 { + RW_MRC_CACHE@0x0 0x10000 + MRC_CACHE_HOLE@0x10000 0x11000 + } + RW_SECTION_A@0x21000 0x39E000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x38DFC0 + RW_FWID_A@0x39DFC0 0x40 + } + RW_SECTION_B@0x3BF000 0x39E000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x38DFC0 + RW_FWID_B@0x39DFC0 0x40 + } + RW_ELOG(PRESERVE)@0x75D000 0x4000 + RW_SHARED@0x761000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x765000 0x2000 + RW_NVRAM(PRESERVE)@0x767000 0x5000 + RW_UNUSED@0x76C000 0x14000 + SMMSTORE(PRESERVE)@0x780000 0x20000 + RW_LEGACY(CBFS)@0x7A0000 0x360000 + WP_RO@0xB00000 0x500000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x4FC000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7C0 + GBB@0x1000 0x70000 + COREBOOT(CBFS)@0x71000 0x48B000 + } + } + } +} diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl new file mode 100644 index 0000000000..0831ddd5b7 --- /dev/null +++ b/src/mainboard/google/zork/dsdt.asl @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +/* DefinitionBlock Statement */ +#include + +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include */ /* as needed */ + + /* global NVS and variables */ + #include + + /* Globals for the platform */ + #include + + /* PCI IRQ mapping for the Southbridge */ + #include + + /* Describe the processor tree (\_PR) */ + #include + + /* Contains the supported sleep states for this chipset */ + #include + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include + + /* Contains _SWS methods */ + #include + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include + + /* Describe the SOC */ + #include + + } /* End \_SB scope */ + + /* Thermal handler */ + #include + + /* Chrome OS specific */ + #include + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include + /* ACPI code for EC functions */ + #include + /* ACPI code for EC I2C Audio Tunnel */ + #include + } +} +/* End of ASL file */ diff --git a/src/mainboard/google/zork/ec.c b/src/mainboard/google/zork/ec.c new file mode 100644 index 0000000000..4c4329dd07 --- /dev/null +++ b/src/mainboard/google/zork/ec.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +static void ramstage_ec_init(void) +{ + const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + }; + + printk(BIOS_DEBUG, "mainboard: EC init\n"); + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} + +void mainboard_ec_init(void) +{ + if (ENV_RAMSTAGE) + ramstage_ec_init(); +} diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c new file mode 100644 index 0000000000..73ece65930 --- /dev/null +++ b/src/mainboard/google/zork/mainboard.c @@ -0,0 +1,255 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + */ +static uint8_t fch_pic_routing[0x80]; +static uint8_t fch_apic_routing[0x80]; + +_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing), + "PIC and APIC FCH interrupt tables must be the same size"); + +/* + * This table doesn't actually perform any routing. It only populates the + * PCI_INTERRUPT_LINE register on the PCI device with the PIC value specified + * in fch_apic_routing. The linux kernel only looks at this field as a backup + * if ACPI routing fails to describe the PCI routing correctly. The linux kernel + * also uses the APIC by default, so the value coded into the registers will be + * wrong. + * + * This table is also confusing because PCI Interrupt routing happens at the + * device/slot level, not the function level. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + { PCIE_GPP_0_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE_GPP_1_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 1 - Wifi + { PCIE_GPP_2_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 2 - SD + { PCIE_GPP_3_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE_GPP_4_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE_GPP_5_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE_GPP_6_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 6 - NVME + { PCIE_GPP_A_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE_GPP_B_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { SMBUS_DEVFN, { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, +}; + +/* + * This controls the device -> IRQ routing. + * The PIC values are limited to 0,1, 3 - 12, 14, 15. + */ +static const struct fch_apic_routing { + uint8_t intr_index; + uint8_t pic_irq_num; + uint8_t apic_irq_num; +} fch_pirq[] = { + { PIRQ_A, 6, 16 }, + { PIRQ_B, 6, 17 }, + { PIRQ_C, 14, 18 }, + { PIRQ_D, 15, 19 }, + { PIRQ_E, PIRQ_NC, PIRQ_NC }, + { PIRQ_F, PIRQ_NC, PIRQ_NC }, + { PIRQ_G, PIRQ_NC, PIRQ_NC }, + { PIRQ_H, PIRQ_NC, PIRQ_NC }, + { PIRQ_SIRQA, PIRQ_NC, PIRQ_NC }, + { PIRQ_SIRQB, PIRQ_NC, PIRQ_NC }, + { PIRQ_SIRQC, PIRQ_NC, PIRQ_NC }, + { PIRQ_SIRQD, PIRQ_NC, PIRQ_NC }, + { PIRQ_SCI, 9, 9 }, + { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC }, + { PIRQ_ASF, PIRQ_NC, PIRQ_NC }, + { PIRQ_PMON, PIRQ_NC, PIRQ_NC }, + { PIRQ_SD, PIRQ_NC, PIRQ_NC }, + { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, + { PIRQ_CIR, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPIOA, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPIOB, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPIOC, PIRQ_NC, PIRQ_NC }, + { PIRQ_SATA, PIRQ_NC, PIRQ_NC }, + { PIRQ_EMMC, 5, 5 }, + { PIRQ_GPP0, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPP1, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPP2, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPP3, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPIO, 7, 7 }, + { PIRQ_I2C0, PIRQ_NC, PIRQ_NC }, + { PIRQ_I2C1, PIRQ_NC, PIRQ_NC }, + { PIRQ_I2C2, 10, 10 }, + { PIRQ_I2C3, 11, 11 }, + { PIRQ_UART0, 4, 4 }, + { PIRQ_UART1, 3, 3 }, + { PIRQ_I2C4, PIRQ_NC, PIRQ_NC }, + { PIRQ_I2C5, PIRQ_NC, PIRQ_NC }, + { PIRQ_UART2, PIRQ_NC, PIRQ_NC }, + { PIRQ_UART3, PIRQ_NC, PIRQ_NC }, + + /* The MISC registers are not interrupt numbers */ + { PIRQ_MISC, 0xfa, 0x00 }, + { PIRQ_MISC0, 0xf1, 0x00 }, + { PIRQ_MISC1, 0x00, 0x00 }, + { PIRQ_MISC2, 0x00, 0x00 }, +}; + +static void init_tables(void) +{ + const struct fch_apic_routing *entry; + int i; + + memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); + memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); + + for (i = 0; i < ARRAY_SIZE(fch_pirq); i++) { + entry = fch_pirq + i; + fch_pic_routing[entry->intr_index] = entry->pic_irq_num; + fch_apic_routing[entry->intr_index] = entry->apic_irq_num; + } +} + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + init_tables(); + + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); + intr_data_ptr = fch_apic_routing; + picr_data_ptr = fch_pic_routing; +} + +static void mainboard_configure_gpios(void) +{ + size_t base_num_gpios, override_num_gpios; + const struct soc_amd_gpio *base_gpios, *override_gpios; + + base_gpios = variant_base_gpio_table(&base_num_gpios); + override_gpios = variant_override_gpio_table(&override_num_gpios); + + gpio_configure_pads_with_override(base_gpios, base_num_gpios, override_gpios, + override_num_gpios); +} + +static void mainboard_init(void *chip_info) +{ + const struct sci_source *gpes; + size_t num; + int boardid; + + mainboard_ec_init(); + boardid = board_id(); + printk(BIOS_INFO, "Board ID: %d\n", boardid); + + mainboard_configure_gpios(); + + /* Update DUT configuration */ + variant_devtree_update(); + + /* + * Some platforms use SCI not generated by a GPIO pin (event above 23). + * For these boards, gpe_configure_sci() is still needed, but all GPIO + * generated events (23-0) must be removed from gpe_table[]. + * For boards that only have GPIO generated events, table gpe_table[] + * must be removed, and get_gpe_table() should return NULL. + */ + gpes = get_gpe_table(&num); + if (gpes != NULL) + gpe_configure_sci(gpes, num); +} + +void mainboard_get_pcie_ddi_descriptors(const picasso_fsp_pcie_descriptor **pcie_descs, + size_t *pcie_num, + const picasso_fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num) +{ + variant_get_pcie_ddi_descriptors(pcie_descs, pcie_num, ddi_descs, ddi_num); +} + +/************************************************* + * Dedicated mainboard function + *************************************************/ +static void zork_enable(struct device *dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); + + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; +} + +static const struct soc_amd_gpio gpio_set_bl[] = { + PAD_GPO(GPIO_85, LOW), +}; + +static void reset_backlight_gpio(void *unused) +{ + printk(BIOS_DEBUG, "Reset backlight GPIO\n"); + /* Re-Enable backlight - GPIO 85 active low */ + /* TODO: Remove this after AGESA stops enabling the fan - b/155667589 */ + program_gpios(gpio_set_bl, ARRAY_SIZE(gpio_set_bl)); /* APU_EDP_BL_DISABLE */ +} + +static void mainboard_final(void *chip_info) +{ + struct global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + reset_backlight_gpio(NULL); + + if (gnvs) { + gnvs->tmps = CTL_TDP_SENSOR_ID; + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + } +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = zork_enable, + .final = mainboard_final, +}; + +void __weak variant_devtree_update(void) +{ +} + +__weak const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + /* Default weak implementation - No overrides. */ + *size = 0; + return NULL; +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, reset_backlight_gpio, NULL); diff --git a/src/mainboard/google/zork/romstage.c b/src/mainboard/google/zork/romstage.c new file mode 100644 index 0000000000..0e3b2da3c3 --- /dev/null +++ b/src/mainboard/google/zork/romstage.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include + +void __weak variant_romstage_entry(void) +{ + /* By default, don't do anything */ +} + +void mainboard_romstage_entry_s3(int s3_resume) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + + gpios = variant_romstage_gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); + gpios = variant_wifi_romstage_gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); + + mainboard_ec_init(); + + variant_romstage_entry(); +} diff --git a/src/mainboard/google/zork/sku_id.c b/src/mainboard/google/zork/sku_id.c new file mode 100644 index 0000000000..82ee355084 --- /dev/null +++ b/src/mainboard/google/zork/sku_id.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +uint32_t sku_id(void) +{ + return google_chromeec_get_board_sku(); +} + +/* An unprovisioned SKU ID indicates we're in the factory booting prior to + proper SKU ID provisioning. */ +int boot_is_factory_unprovisioned(void) +{ + return sku_id() == CROS_SKU_UNPROVISIONED; +} diff --git a/src/mainboard/google/zork/smihandler.c b/src/mainboard/google/zork/smihandler.c new file mode 100644 index 0000000000..7c88215ecb --- /dev/null +++ b/src/mainboard/google/zork/smihandler.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include +#include +#include +#include +#include +#include +#include +#include + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + chromeec_smi_process_events(); +} +void mainboard_smi_sleep(u8 slp_typ) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} +int mainboard_smi_apmc(u8 apmc) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +} diff --git a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex new file mode 100644 index 0000000000..7ae89df525 --- /dev/null +++ b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 B4 EF +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-4BkG-16x10-8bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-4BkG-16x10-8bit.spd.hex new file mode 100644 index 0000000000..8d9fd4d9bf --- /dev/null +++ b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-4BkG-16x10-8bit.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 00 08 00 60 00 03 01 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 EF F6 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-2BkG-16x10-8bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-2BkG-16x10-8bit.spd.hex new file mode 100644 index 0000000000..af9ba32181 --- /dev/null +++ b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-2BkG-16x10-8bit.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 10 08 00 60 00 03 01 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 E7 7D +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-4BkG-16x10-8bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-4BkG-16x10-8bit.spd.hex new file mode 100644 index 0000000000..56677fa37a --- /dev/null +++ b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-4BkG-16x10-8bit.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 10 08 00 60 00 03 01 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 55 24 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-16x10-16bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-16x10-16bit.spd.hex new file mode 100644 index 0000000000..cc1ca7384b --- /dev/null +++ b/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-16x10-16bit.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 21 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 B3 E1 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-17x10-16bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-17x10-16bit.spd.hex new file mode 100644 index 0000000000..3b1a73e7b8 --- /dev/null +++ b/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-17x10-16bit.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 3C 41 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-3200-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-3200-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex new file mode 100644 index 0000000000..07342ab8fc --- /dev/null +++ b/src/mainboard/google/zork/spd/DDR4-3200-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 4C 24 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-template.spd.hex b/src/mainboard/google/zork/spd/DDR4-template.spd.hex new file mode 100644 index 0000000000..6198f3daf1 --- /dev/null +++ b/src/mainboard/google/zork/spd/DDR4-template.spd.hex @@ -0,0 +1,336 @@ +# Generic DDR4 SPD template +# Fields that are not required should be set to zero +# CRC will be calculated when generating SPDs from this template, so no need +# to update here + +# Number of Serial PD Bytes Written / SPD Device Size (SPD Bytes Used : 384 / SPD Bytes Total : 512) +23 + +# SPD Revision (Rev. 1.1) +11 + +# Key Byte / DRAM Device Type (DDR4 SDRAM) +0C + +# Key Byte / Module Type (nECC SO-DIMM) +03 + +# SDRAM Density and Banks (2BG/4BK/8Gb) +45 + +# SDRAM Addressing (16/10) +21 + +# Primary SDRAM Package Type (Flipchip SDP) +00 + +# SDRAM Optional Features (Unlimited MAC) +08 + +# SDRAM Thermal and Refresh Options (Reserved) +00 + +# Other SDRAM Optional Features (PPR) (hPPR, sPPR supported) +60 + +# Secondary SDRAM Package Type +00 + +# Module Nominal Volatage, VDD (1.2V) +03 + +# Module Organization +01 + +# Module Memory Bus Width (LP/x64) +03 + +# Module Thermal Sensor (Termal sensor not incorporated) +00 + +# Extended Module Type (Reserved) +00 + +# Reserved +00 + +# Timebases (MTB : 125ps, FTB : 1ps) +00 + +# SDRAM Minimum Cycle Time (tCKAVGmin) (0.75ns) +06 + +# SDRAM Maximum Cycle Time (tCKAVGmax) (1.6ns) +0D + +# CAS Latencies Supported, First Byte (10, 11, 12, 13, 14) +F8 + +# CAS Latencies Supported, Second Byte (15, 16, 17, 18, 19, 20) +3F + +# CAS Latencies Supported, Third Byte +00 + +# CAS Latencies Supported, Fourth Byte +00 + +# Minimum CAS Latency Time (tAAmin) (13.75ns) +6E + +# Minimum RAS to CAS Delay Time (tRCDmin) (13.75ns) +6E + +# Minimum RAS to CAS Delay Time (tRPmin) (13.75ns) +6E + +# Upper Nibbles for tRASmin and tRCmin (32ns / 45.75ns) +11 + +# tRASmin, Least Significant Byte (32ns) +00 + +# tRCmin, Least Significant Byte (45.75ns) +6E + +# tRFC1min, LSB (350ns) +F0 + +# tRFC1min, MSB (350ns) +0A + +# tRFC2min, LSB (260ns) +20 + +# tRFC2min, MSB (260ns) +08 + +# tRFC4min, LSB (160ns) +00 + +# tRFC4min, MSB (160ns) +05 + +# Upper Nibble for tFAW (30ns) +00 + +# tFAWmin LSB (30ns) +F0 + +# tRRD_Smin (5.3ns) +2B + +# tRRD_L min (6.40ns) +34 + +# tCCD_Lmin, same bank group (5ns) +28 + +# tWRmin Upper Nibbles (15ns) +00 + +# tWRmin (15ns) +78 + +# tWTRmin Upper Nibbles (2.5ns/7.5ns) +00 + +# tWTR_Smin (2.5ns) +14 + +# tWTR_Lmin (7.5ns) +3C + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Connector to SDRAM Bit Mapping (DQ0-3) +00 + +# Connector to SDRAM Bit Mapping (DQ4-7) +00 + +# Connector to SDRAM Bit Mapping (DQ8-11) +00 + +# Connector to SDRAM Bit Mapping (DQ12-15) +00 + +# Connector to SDRAM Bit Mapping (DQ16-19) +00 + +# Connector to SDRAM Bit Mapping (DQ20-23) +00 + +# Connector to SDRAM Bit Mapping (DQ24-27) +00 + +# Connector to SDRAM Bit Mapping (DQ28-31) +00 + +# Connector to SDRAM Bit Mapping (CB0-3) +00 + +# Connector to SDRAM Bit Mapping (CB4-7) +00 + +# Connector to SDRAM Bit Mapping (DQ32-35) +00 + +# Connector to SDRAM Bit Mapping (DQ36-39) +00 + +# Connector to SDRAM Bit Mapping (DQ40-43) +00 + +# Connector to SDRAM Bit Mapping (DQ44-47) +00 + +# Connector to SDRAM Bit Mapping (DQ48-51) +00 + +# Connector to SDRAM Bit Mapping (DQ52-55) +00 + +# Connector to SDRAM Bit Mapping (DQ56-59) +00 + +# Connector to SDRAM Bit Mapping (DQ60-63) +00 + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 + +# Fine offset for tCCD_Lmin, same bank group (5ns) +00 + +# tRRD_L min offset (6.40ns) +9C + +# tRRD_Smin offset (blank) +00 + +# Fine offset for tRCmin (45.75ns) +00 + +# Fine offset for tRPmin (13.75ns) +00 + +# Fine offset for tRCDmin (13.75ns) +00 + +# Fine offset for tAAmin (13.75ns) +00 + +# Fine offset for tCKAVGmax (1.6ns) +E7 + +# Fine offset for tCKAVGmin (0.75ns) +00 + +# CRC for Base Configuration Section, LSB (CRC cover 0~125 byte) +00 + +# CRC for Base Configuration Section, MSB (CRC cover 0~125 byte) +00 + +# RC Extension, Module Nominal Height +00 + +# Module Maximum Thickness +00 + +# Reference Raw Card Used +00 + +# Address Mapping from Edge Connector to DRAM (Standard) +00 + +# Reserved +00 00 00 00 00 00 00 00 + +# Reserved (Must be coded as 0x00) +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 + +# CRC for Module Specific Section, LSB (CRC cover 128~253 byte) +00 + +# CRC for Module Specific Section, MSB (CRC cover 128~253 byte) +00 + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Module Manufacturer's ID Code, LSB (blank) +00 + +# Module Manufacturer's ID Code, MSB (blank) +00 + +# Module Manufacturing Location (blank) +00 + +# Module Manufacturing Date (Variable) +00 + +# Module Manufacturing Date (Variable) +00 + +# Module Serial Number (Undefined) +00 + +# Module Serial Number (Undefined) +00 + +# Module Serial Number (Undefined) +00 + +# Module Serial Number (Undefined) +00 + +# Module Part Number (blank) +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 + +# Module Revision Code (Revision 0) +00 + +# DRAM Manufacturer's ID code, LSB (blank) +00 + +# DRAM Manufacturer's ID code, MSB (blank) +00 + +# DRAM Stepping (Undefined) +00 + +# Module Manufacturer's Specific Data (blank) +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Reserved +00 00 + +# End User Programmable +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/Makefile.inc b/src/mainboard/google/zork/spd/Makefile.inc new file mode 100644 index 0000000000..e401fa6fdc --- /dev/null +++ b/src/mainboard/google/zork/spd/Makefile.inc @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This directory +SPD_SOURCES_DIR := src/mainboard/$(MAINBOARDDIR)/spd + +# Ordered List of APCB entries, up to 16. +# Entries should match this pattern {NAME}_x{1,2} +# There should be a matching SPD hex file in SPD_SOURCES_DIR +# matching the pattern {NAME}.spd.hex +# The _x{1,2} suffix denotes single or dual channel +# TODO: Remove channel suffix when b:141434940 is fixed +# Alternatively, generated APCBs stored at +# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included. +APCB_SOURCES = hynix-H5AN8G6NCJR-VKC_x1 # 0b0000 +APCB_SOURCES += hynix-H5ANAG6NCMR-VKC_x2 # 0b0001 +APCB_SOURCES += empty # 0b0010 +APCB_SOURCES += empty # 0b0011 +APCB_SOURCES += empty # 0b0100 +APCB_SOURCES += empty # 0b0101 +APCB_SOURCES += empty # 0b0110 +APCB_SOURCES += empty # 0b0111 +APCB_SOURCES += empty # 0b1000 +APCB_SOURCES += empty # 0b1001 +APCB_SOURCES += empty # 0b1010 +APCB_SOURCES += empty # 0b1011 +APCB_SOURCES += empty # 0b1100 +APCB_SOURCES += empty # 0b1101 +APCB_SOURCES += empty # 0b1110 +APCB_SOURCES += empty # 0b1111 diff --git a/src/mainboard/google/zork/spd/empty.spd.hex b/src/mainboard/google/zork/spd/empty.spd.hex new file mode 100644 index 0000000000..0d22dd0cf0 --- /dev/null +++ b/src/mainboard/google/zork/spd/empty.spd.hex @@ -0,0 +1,33 @@ +#Empty SPD - placeholder file +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/hynix-H5AN8G6NCJR-VKC.spd.hex b/src/mainboard/google/zork/spd/hynix-H5AN8G6NCJR-VKC.spd.hex new file mode 100644 index 0000000000..1c5e87f9d4 --- /dev/null +++ b/src/mainboard/google/zork/spd/hynix-H5AN8G6NCJR-VKC.spd.hex @@ -0,0 +1,331 @@ +# Number of Serial PD Bytes Written / SPD Device Size (SPD Bytes Used : 384 / SPD Bytes Total : 512) +23 + +# SPD Revision (Rev. 1.1) +11 + +# Key Byte / DRAM Device Type (DDR4 SDRAM) +0C + +# Key Byte / Module Type (nECC SO-DIMM) +03 + +# SDRAM Density and Banks (2BG/4BK/8Gb) +45 + +# SDRAM Addressing (16/10) +21 + +# Primary SDRAM Package Type (Flipchip SDP) +00 + +# SDRAM Optional Features (Unlimited MAC) +08 + +# SDRAM Thermal and Refresh Options (Reserved) +00 + +# Other SDRAM Optional Features (PPR) (hPPR, sPPR supported) +60 + +# Secondary SDRAM Package Type +00 + +# Module Nominal Volatage, VDD (1.2V) +03 + +# Module Organization (1Rx16) +02 + +# Module Memory Bus Width (LP/x64) +03 + +# Module Thermal Sensor (Termal sensor not incorporated) +00 + +# Extended Module Type (Reserved) +00 + +# Reserved +00 + +# Timebases (MTB : 125ps, FTB : 1ps) +00 + +# SDRAM Minimum Cycle Time (tCKAVGmin) (0.75ns) +06 + +# SDRAM Maximum Cycle Time (tCKAVGmax) (1.6ns) +0D + +# CAS Latencies Supported, First Byte (10, 11, 12, 13, 14) +F8 + +# CAS Latencies Supported, Second Byte (15, 16, 17, 18, 19, 20) +3F + +# CAS Latencies Supported, Third Byte +00 + +# CAS Latencies Supported, Fourth Byte +00 + +# Minimum CAS Latency Time (tAAmin) (13.75ns) +6E + +# Minimum RAS to CAS Delay Time (tRCDmin) (13.75ns) +6E + +# Minimum RAS to CAS Delay Time (tRPmin) (13.75ns) +6E + +# Upper Nibbles for tRASmin and tRCmin (32ns / 45.75ns) +11 + +# tRASmin, Least Significant Byte (32ns) +00 + +# tRCmin, Least Significant Byte (45.75ns) +6E + +# tRFC1min, LSB (350ns) +F0 + +# tRFC1min, MSB (350ns) +0A + +# tRFC2min, LSB (260ns) +20 + +# tRFC2min, MSB (260ns) +08 + +# tRFC4min, LSB (160ns) +00 + +# tRFC4min, MSB (160ns) +05 + +# Upper Nibble for tFAW (30ns) +00 + +# tFAWmin LSB (30ns) +F0 + +# tRRD_Smin (5.3ns) +2B + +# tRRD_L min (6.40ns) +34 + +# tCCD_Lmin, same bank group (5ns) +28 + +# tWRmin Upper Nibbles (15ns) +00 + +# tWRmin (15ns) +78 + +# tWTRmin Upper Nibbles (2.5ns/7.5ns) +00 + +# tWTR_Smin (2.5ns) +14 + +# tWTR_Lmin (7.5ns) +3C + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Connector to SDRAM Bit Mapping (DQ0-3) +16 + +# Connector to SDRAM Bit Mapping (DQ4-7) +36 + +# Connector to SDRAM Bit Mapping (DQ8-11) +0B + +# Connector to SDRAM Bit Mapping (DQ12-15) +35 + +# Connector to SDRAM Bit Mapping (DQ16-19) +16 + +# Connector to SDRAM Bit Mapping (DQ20-23) +36 + +# Connector to SDRAM Bit Mapping (DQ24-27) +0B + +# Connector to SDRAM Bit Mapping (DQ28-31) +35 + +# Connector to SDRAM Bit Mapping (CB0-3) +00 + +# Connector to SDRAM Bit Mapping (CB4-7) +00 + +# Connector to SDRAM Bit Mapping (DQ32-35) +16 + +# Connector to SDRAM Bit Mapping (DQ36-39) +36 + +# Connector to SDRAM Bit Mapping (DQ40-43) +0B + +# Connector to SDRAM Bit Mapping (DQ44-47) +35 + +# Connector to SDRAM Bit Mapping (DQ48-51) +16 + +# Connector to SDRAM Bit Mapping (DQ52-55) +36 + +# Connector to SDRAM Bit Mapping (DQ56-59) +0B + +# Connector to SDRAM Bit Mapping (DQ60-63) +35 + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 + +# Fine offset for tCCD_Lmin, same bank group (5ns) +00 + +# tRRD_L min offset (6.40ns) +9C + +# tRRD_Smin offset (5.3ns) +B5 + +# Fine offset for tRCmin (45.75ns) +00 + +# Fine offset for tRPmin (13.75ns) +00 + +# Fine offset for tRCDmin (13.75ns) +00 + +# Fine offset for tAAmin (13.75ns) +00 + +# Fine offset for tCKAVGmax (1.6ns) +E7 + +# Fine offset for tCKAVGmin (0.75ns) +00 + +# CRC for Base Configuration Section, LSB (CRC cover 0~125 byte) +87 + +# CRC for Base Configuration Section, MSB (CRC cover 0~125 byte) +2E + +# RC Extention, Module Nominal Height (30.00) +0F + +# Module Maximum Thickness (1.0/1.2) +01 + +# Reference Raw Card Used (C0) +02 + +# Address Mapping from Edge Connector to DRAM (Standard) +00 + +# Reserved +00 00 00 00 00 00 00 00 + +# Reserved (Must be coded as 0x00) +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 + +# CRC for Module Specific Section, LSB (CRC cover 128~253 byte) +C0 + +# CRC for Module Specific Section, MSB (CRC cover 128~253 byte) +E2 + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Module Manufacturer's ID Code, LSB (SK hynix) +80 + +# Module Manufacturer's ID Code, MSB (SK hynix) +AD + +# Module Manufacturing Location (SK hynix (Icheon)) +01 + +# Module Manufacturing Date (Variable) +00 + +# Module Manufacturing Date (Variable) +00 + +# Module Serial Number (Undefined) +00 + +# Module Serial Number (Undefined) +00 + +# Module Serial Number (Undefined) +00 + +# Module Serial Number (Undefined) +00 + +# Module Part Number (H5AN8G6NCJR-VKC ) +48 35 41 4E 38 47 36 4E 43 4A 52 2D 56 4B 43 20 +20 20 20 20 + +# Module Revision Code (Revision 0) +00 + +# DRAM Manufacturer's ID code, LSB (SK hynix) +80 + +# DRAM Manufacturer's ID code, MSB (SK hynix) +AD + +# DRAM Stepping (Undefined) +FF + +# Module Manufacturer's Specific Data +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 DD + +# Reserved +00 00 + +# End User Programmable +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/hynix-H5AN8G6NDJR-XNC.spd.hex b/src/mainboard/google/zork/spd/hynix-H5AN8G6NDJR-XNC.spd.hex new file mode 100644 index 0000000000..144c8e3f08 --- /dev/null +++ b/src/mainboard/google/zork/spd/hynix-H5AN8G6NDJR-XNC.spd.hex @@ -0,0 +1,33 @@ +# Hynix H5AN8G6NDJR-XNC +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B4 00 00 00 00 E7 00 75 20 +0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 AD 01 00 00 00 00 00 00 48 35 41 4E 38 47 36 +4E 44 4A 52 2D 58 4E 43 20 20 20 20 20 00 80 AD +FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-VKC.spd.hex b/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-VKC.spd.hex new file mode 100644 index 0000000000..e75e4c12d9 --- /dev/null +++ b/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-VKC.spd.hex @@ -0,0 +1,33 @@ +# Hynix H5ANAG6NCMR-VKC +23 11 0C 03 85 21 91 08 00 60 00 03 01 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04 +16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 43 CE +0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 EF 55 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 AD 01 00 00 00 00 00 00 48 4D 41 41 31 47 53 +36 43 4D 52 38 4E 2D 56 4B 20 20 20 20 00 80 AD +FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 DD 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-XNC.spd.hex b/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-XNC.spd.hex new file mode 100644 index 0000000000..3cfb32cfc8 --- /dev/null +++ b/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-XNC.spd.hex @@ -0,0 +1,33 @@ +# Hynix H5ANAG6NCMR-XNC +23 11 0C 03 85 21 91 08 00 60 00 03 01 03 00 00 +00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 A8 14 28 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 C0 6E +0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 7D 21 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 AD 01 00 00 00 00 00 00 48 35 41 4E 41 47 36 +4E 43 4D 52 2D 58 4E 43 20 20 20 20 20 00 80 AD +FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 DD 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/hynix-HMA851S6CJR6N-VK.spd.hex b/src/mainboard/google/zork/spd/hynix-HMA851S6CJR6N-VK.spd.hex new file mode 100644 index 0000000000..7ad9466cf4 --- /dev/null +++ b/src/mainboard/google/zork/spd/hynix-HMA851S6CJR6N-VK.spd.hex @@ -0,0 +1,331 @@ +# Number of Serial PD Bytes Written / SPD Device Size (SPD Bytes Used : 384 / SPD Bytes Total : 512) +23 + +# SPD Revision (Rev. 1.1) +11 + +# Key Byte / DRAM Device Type (DDR4 SDRAM) +0C + +# Key Byte / Module Type (nECC SO-DIMM) +03 + +# SDRAM Density and Banks (2BG/4BK/8Gb) +45 + +# SDRAM Addressing (16/10) +21 + +# Primary SDRAM Package Type (Flipchip SDP) +00 + +# SDRAM Optional Features (Unlimited MAC) +08 + +# SDRAM Thermal and Refresh Options (Reserved) +00 + +# Other SDRAM Optional Features (PPR) (hPPR, sPPR supported) +60 + +# Secondary SDRAM Package Type +00 + +# Module Nominal Volatage, VDD (1.2V) +03 + +# Module Organization (1Rx16) +02 + +# Module Memory Bus Width (LP/x64) +03 + +# Module Thermal Sensor (Termal sensor not incorporated) +00 + +# Extended Module Type (Reserved) +00 + +# Reserved +00 + +# Timebases (MTB : 125ps, FTB : 1ps) +00 + +# SDRAM Minimum Cycle Time (tCKAVGmin) (0.75ns) +06 + +# SDRAM Maximum Cycle Time (tCKAVGmax) (1.6ns) +0D + +# CAS Latencies Supported, First Byte (10, 11, 12, 13, 14) +F8 + +# CAS Latencies Supported, Second Byte (15, 16, 17, 18, 19, 20) +3F + +# CAS Latencies Supported, Third Byte +00 + +# CAS Latencies Supported, Fourth Byte +00 + +# Minimum CAS Latency Time (tAAmin) (13.75ns) +6E + +# Minimum RAS to CAS Delay Time (tRCDmin) (13.75ns) +6E + +# Minimum RAS to CAS Delay Time (tRPmin) (13.75ns) +6E + +# Upper Nibbles for tRASmin and tRCmin (32ns / 45.75ns) +11 + +# tRASmin, Least Significant Byte (32ns) +00 + +# tRCmin, Least Significant Byte (45.75ns) +6E + +# tRFC1min, LSB (350ns) +F0 + +# tRFC1min, MSB (350ns) +0A + +# tRFC2min, LSB (260ns) +20 + +# tRFC2min, MSB (260ns) +08 + +# tRFC4min, LSB (160ns) +00 + +# tRFC4min, MSB (160ns) +05 + +# Upper Nibble for tFAW (30ns) +00 + +# tFAWmin LSB (30ns) +F0 + +# tRRD_Smin (5.3ns) +2B + +# tRRD_L min (6.40ns) +34 + +# tCCD_Lmin, same bank group (5ns) +28 + +# tWRmin Upper Nibbles (15ns) +00 + +# tWRmin (15ns) +78 + +# tWTRmin Upper Nibbles (2.5ns/7.5ns) +00 + +# tWTR_Smin (2.5ns) +14 + +# tWTR_Lmin (7.5ns) +3C + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Connector to SDRAM Bit Mapping (DQ0-3) +16 + +# Connector to SDRAM Bit Mapping (DQ4-7) +36 + +# Connector to SDRAM Bit Mapping (DQ8-11) +0B + +# Connector to SDRAM Bit Mapping (DQ12-15) +35 + +# Connector to SDRAM Bit Mapping (DQ16-19) +16 + +# Connector to SDRAM Bit Mapping (DQ20-23) +36 + +# Connector to SDRAM Bit Mapping (DQ24-27) +0B + +# Connector to SDRAM Bit Mapping (DQ28-31) +35 + +# Connector to SDRAM Bit Mapping (CB0-3) +00 + +# Connector to SDRAM Bit Mapping (CB4-7) +00 + +# Connector to SDRAM Bit Mapping (DQ32-35) +16 + +# Connector to SDRAM Bit Mapping (DQ36-39) +36 + +# Connector to SDRAM Bit Mapping (DQ40-43) +0B + +# Connector to SDRAM Bit Mapping (DQ44-47) +35 + +# Connector to SDRAM Bit Mapping (DQ48-51) +16 + +# Connector to SDRAM Bit Mapping (DQ52-55) +36 + +# Connector to SDRAM Bit Mapping (DQ56-59) +0B + +# Connector to SDRAM Bit Mapping (DQ60-63) +35 + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 + +# Fine offset for tCCD_Lmin, same bank group (5ns) +00 + +# tRRD_L min offset (6.40ns) +9C + +# tRRD_Smin offset (5.3ns) +B5 + +# Fine offset for tRCmin (45.75ns) +00 + +# Fine offset for tRPmin (13.75ns) +00 + +# Fine offset for tRCDmin (13.75ns) +00 + +# Fine offset for tAAmin (13.75ns) +00 + +# Fine offset for tCKAVGmax (1.6ns) +E7 + +# Fine offset for tCKAVGmin (0.75ns) +00 + +# CRC for Base Configuration Section, LSB (CRC cover 0~125 byte) +87 + +# CRC for Base Configuration Section, MSB (CRC cover 0~125 byte) +2E + +# RC Extention, Module Nominal Height (30.00) +0F + +# Module Maximum Thickness (1.0/1.2) +01 + +# Reference Raw Card Used (C0) +02 + +# Address Mapping from Edge Connector to DRAM (Standard) +00 + +# Reserved +00 00 00 00 00 00 00 00 + +# Reserved (Must be coded as 0x00) +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 + +# CRC for Module Specific Section, LSB (CRC cover 128~253 byte) +C0 + +# CRC for Module Specific Section, MSB (CRC cover 128~253 byte) +E2 + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Module Manufacturer's ID Code, LSB (SK hynix) +80 + +# Module Manufacturer's ID Code, MSB (SK hynix) +AD + +# Module Manufacturing Location (SK hynix (Icheon)) +01 + +# Module Manufacturing Date (Variable) +00 + +# Module Manufacturing Date (Variable) +00 + +# Module Serial Number (Undefined) +00 + +# Module Serial Number (Undefined) +00 + +# Module Serial Number (Undefined) +00 + +# Module Serial Number (Undefined) +00 + +# Module Part Number (HMA851S6CJR6N-VK ) +48 4D 41 38 35 31 53 36 43 4A 52 36 4E 2D 56 4B +20 20 20 20 + +# Module Revision Code (Revision 0) +00 + +# DRAM Manufacturer's ID code, LSB (SK hynix) +80 + +# DRAM Manufacturer's ID code, MSB (SK hynix) +AD + +# DRAM Stepping (Undefined) +FF + +# Module Manufacturer's Specific Data +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 DD + +# Reserved +00 00 + +# End User Programmable +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/hynix-HMAA1GS6CMR6N-VK.spd.hex b/src/mainboard/google/zork/spd/hynix-HMAA1GS6CMR6N-VK.spd.hex new file mode 100644 index 0000000000..ff166d6e75 --- /dev/null +++ b/src/mainboard/google/zork/spd/hynix-HMAA1GS6CMR6N-VK.spd.hex @@ -0,0 +1,331 @@ +# Number of Serial PD Bytes Written / SPD Device Size (SPD Bytes Used : 384 / SPD Bytes Total : 512) +23 + +# SPD Revision (Rev. 1.1) +11 + +# Key Byte / DRAM Device Type (DDR4 SDRAM) +0C + +# Key Byte / Module Type (nECC SO-DIMM) +03 + +# SDRAM Density and Banks (2BG/4BK/8Gb) +45 + +# SDRAM Addressing (16/10) +21 + +# Primary SDRAM Package Type (DDP) +91 + +# SDRAM Optional Features (Unlimited MAC) +08 + +# SDRAM Thermal and Refresh Options (Reserved) +00 + +# Other SDRAM Optional Features (PPR) (hPPR, sPPR supported) +60 + +# Secondary SDRAM Package Type +00 + +# Module Nominal Volatage, VDD (1.2V) +03 + +# Module Organization (1Rx8) +01 + +# Module Memory Bus Width (LP/x64) +03 + +# Module Thermal Sensor (Termal sensor not incorporated) +00 + +# Extended Module Type (Reserved) +00 + +# Reserved +00 + +# Timebases (MTB : 125ps, FTB : 1ps) +00 + +# SDRAM Minimum Cycle Time (tCKAVGmin) (0.75ns) +06 + +# SDRAM Maximum Cycle Time (tCKAVGmax) (1.6ns) +0D + +# CAS Latencies Supported, First Byte (10, 11, 12, 13, 14) +F8 + +# CAS Latencies Supported, Second Byte (15, 16, 17, 18, 19, 20) +3F + +# CAS Latencies Supported, Third Byte +00 + +# CAS Latencies Supported, Fourth Byte +00 + +# Minimum CAS Latency Time (tAAmin) (13.75ns) +6E + +# Minimum RAS to CAS Delay Time (tRCDmin) (13.75ns) +6E + +# Minimum RAS to CAS Delay Time (tRPmin) (13.75ns) +6E + +# Upper Nibbles for tRASmin and tRCmin (32ns / 45.75ns) +11 + +# tRASmin, Least Significant Byte (32ns) +00 + +# tRCmin, Least Significant Byte (45.75ns) +6E + +# tRFC1min, LSB (350ns) +F0 + +# tRFC1min, MSB (350ns) +0A + +# tRFC2min, LSB (260ns) +20 + +# tRFC2min, MSB (260ns) +08 + +# tRFC4min, LSB (160ns) +00 + +# tRFC4min, MSB (160ns) +05 + +# Upper Nibble for tFAW (30ns) +00 + +# tFAWmin LSB (30ns) +F0 + +# tRRD_Smin (5.3ns) +2B + +# tRRD_L min (6.40ns) +34 + +# tCCD_Lmin, same bank group (5ns) +28 + +# tWRmin Upper Nibbles (15ns) +00 + +# tWRmin (15ns) +78 + +# tWTRmin Upper Nibbles (2.5ns/7.5ns) +00 + +# tWTR_Smin (2.5ns) +14 + +# tWTR_Lmin (7.5ns) +3C + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Connector to SDRAM Bit Mapping (DQ0-3) +16 + +# Connector to SDRAM Bit Mapping (DQ4-7) +36 + +# Connector to SDRAM Bit Mapping (DQ8-11) +0B + +# Connector to SDRAM Bit Mapping (DQ12-15) +35 + +# Connector to SDRAM Bit Mapping (DQ16-19) +16 + +# Connector to SDRAM Bit Mapping (DQ20-23) +36 + +# Connector to SDRAM Bit Mapping (DQ24-27) +0B + +# Connector to SDRAM Bit Mapping (DQ28-31) +35 + +# Connector to SDRAM Bit Mapping (CB0-3) +00 + +# Connector to SDRAM Bit Mapping (CB4-7) +00 + +# Connector to SDRAM Bit Mapping (DQ32-35) +16 + +# Connector to SDRAM Bit Mapping (DQ36-39) +36 + +# Connector to SDRAM Bit Mapping (DQ40-43) +0B + +# Connector to SDRAM Bit Mapping (DQ44-47) +35 + +# Connector to SDRAM Bit Mapping (DQ48-51) +16 + +# Connector to SDRAM Bit Mapping (DQ52-55) +36 + +# Connector to SDRAM Bit Mapping (DQ56-59) +0B + +# Connector to SDRAM Bit Mapping (DQ60-63) +35 + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 + +# Fine offset for tCCD_Lmin, same bank group (5ns) +00 + +# tRRD_L min offset (6.40ns) +9C + +# tRRD_Smin offset (5.3ns) +B5 + +# Fine offset for tRCmin (45.75ns) +00 + +# Fine offset for tRPmin (13.75ns) +00 + +# Fine offset for tRCDmin (13.75ns) +00 + +# Fine offset for tAAmin (13.75ns) +00 + +# Fine offset for tCKAVGmax (1.6ns) +E7 + +# Fine offset for tCKAVGmin (0.75ns) +00 + +# CRC for Base Configuration Section, LSB (CRC cover 0~125 byte) +FD + +# CRC for Base Configuration Section, MSB (CRC cover 0~125 byte) +EE + +# RC Extention, Module Nominal Height (30.00) +0F + +# Module Maximum Thickness (1.0/1.2) +01 + +# Reference Raw Card Used (ZZ0) +1F + +# Address Mapping from Edge Connector to DRAM (Standard) +00 + +# Reserved +00 00 00 00 00 00 00 00 + +# Reserved (Must be coded as 0x00) +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 + +# CRC for Module Specific Section, LSB (CRC cover 128~253 byte) +7D + +# CRC for Module Specific Section, MSB (CRC cover 128~253 byte) +21 + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Module Manufacturer's ID Code, LSB (SK hynix) +80 + +# Module Manufacturer's ID Code, MSB (SK hynix) +AD + +# Module Manufacturing Location (SK hynix (Icheon)) +01 + +# Module Manufacturing Date (Variable) +00 + +# Module Manufacturing Date (Variable) +00 + +# Module Serial Number (Undefined) +00 + +# Module Serial Number (Undefined) +00 + +# Module Serial Number (Undefined) +00 + +# Module Serial Number (Undefined) +00 + +# Module Part Number (HMAA1GS6CMR6N-VK ) +48 4D 41 41 31 47 53 36 43 4D 52 36 4E 2D 56 4B +20 20 20 20 + +# Module Revision Code (Revision 0) +00 + +# DRAM Manufacturer's ID code, LSB (SK hynix) +80 + +# DRAM Manufacturer's ID code, MSB (SK hynix) +AD + +# DRAM Stepping (Undefined) +FF + +# Module Manufacturer's Specific Data +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 DD + +# Reserved +00 00 + +# End User Programmable +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/micron-MT40A1G16KD-062E-E.spd.hex b/src/mainboard/google/zork/spd/micron-MT40A1G16KD-062E-E.spd.hex new file mode 100644 index 0000000000..17778473af --- /dev/null +++ b/src/mainboard/google/zork/spd/micron-MT40A1G16KD-062E-E.spd.hex @@ -0,0 +1,33 @@ +# Micron MT40A1G16KD-062E:E +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 7C A0 +0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 21 7D +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 31 47 +31 36 4B 44 2D 30 36 32 45 3A 45 20 20 31 80 2C +45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/micron-MT40A1G16KNR-075-E.spd.hex b/src/mainboard/google/zork/spd/micron-MT40A1G16KNR-075-E.spd.hex new file mode 100644 index 0000000000..988ea54b23 --- /dev/null +++ b/src/mainboard/google/zork/spd/micron-MT40A1G16KNR-075-E.spd.hex @@ -0,0 +1,33 @@ +# Micron MT40A1G16KNR-075:E +23 11 0C 03 85 21 00 08 00 60 00 03 01 03 00 00 +00 00 06 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 8D 60 +0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 21 7D +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 31 47 +31 36 4B 4E 52 2D 30 37 35 3A 45 20 20 31 80 2C +45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/micron-MT40A512M16TB-062E-J.spd.hex b/src/mainboard/google/zork/spd/micron-MT40A512M16TB-062E-J.spd.hex new file mode 100644 index 0000000000..67640fe849 --- /dev/null +++ b/src/mainboard/google/zork/spd/micron-MT40A512M16TB-062E-J.spd.hex @@ -0,0 +1,33 @@ +# MT40A512M16TB-062E:J +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 30 53 +0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 35 31 +32 4D 31 36 54 42 2D 30 36 32 45 3A 4A 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCTD.spd.hex b/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCTD.spd.hex new file mode 100644 index 0000000000..e16d2f729b --- /dev/null +++ b/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCTD.spd.hex @@ -0,0 +1,33 @@ +# Samsung K4A8G165WC-BCTD +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 87 2e +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4B 34 41 38 47 31 36 +35 57 43 2D 42 43 54 44 20 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCWE.spd.hex b/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCWE.spd.hex new file mode 100644 index 0000000000..4fb1561c6a --- /dev/null +++ b/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCWE.spd.hex @@ -0,0 +1,33 @@ +# Samsung K4A8G165WC-BCWE +23 11 0C 03 46 21 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 14 98 +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4B 34 41 38 47 31 36 +35 57 43 2D 42 43 57 45 20 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/samsung-K4AAG165WA-BCWE.spd.hex b/src/mainboard/google/zork/spd/samsung-K4AAG165WA-BCWE.spd.hex new file mode 100644 index 0000000000..390e5a5417 --- /dev/null +++ b/src/mainboard/google/zork/spd/samsung-K4AAG165WA-BCWE.spd.hex @@ -0,0 +1,33 @@ +# Samsung K4AAG165WA-BCWE +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 E8 F5 +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4B 34 41 41 47 31 36 +35 57 41 2D 42 43 57 45 20 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/samsung-K4AAG165WB-MCTD.spd.hex b/src/mainboard/google/zork/spd/samsung-K4AAG165WB-MCTD.spd.hex new file mode 100644 index 0000000000..ede001a4d5 --- /dev/null +++ b/src/mainboard/google/zork/spd/samsung-K4AAG165WB-MCTD.spd.hex @@ -0,0 +1,33 @@ +# Samsung K4AAG165WB-MCTD +23 11 0C 03 85 21 00 08 00 60 00 03 01 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04 +16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 D0 4E +0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 EF 55 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 31 4B +34 33 42 42 31 2D 43 54 44 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/variants/baseboard/Makefile.inc b/src/mainboard/google/zork/variants/baseboard/Makefile.inc new file mode 100644 index 0000000000..4bcaf68aed --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/Makefile.inc @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c +bootblock-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c + +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +verstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c +verstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c +endif +verstage-y += tpm_tis.c + +romstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c +romstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c +romstage-y += tpm_tis.c + +ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c +ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += fsps_baseboard_trembyle.c +ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c +ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += fsps_baseboard_dalboz.c +ramstage-y += helpers.c +ramstage-y += tpm_tis.c + +# Add OEM ID table +ifeq ($(CONFIG_USE_OEM_BIN),y) +cbfs-files-y += oem.bin +oem.bin-file := $(call strip_quotes,$(CONFIG_OEM_BIN_FILE)) +oem.bin-type := raw +endif #($(CONFIG_USE_OEM_BIN),y) + +# APCB Board ID GPIO configuration. +# These GPIOs determine which memory SPD will be used during boot. +# APCB_BOARD_ID_GPIO[0-3] = GPIO_NUMBER GPIO_IO_MUX GPIO_BANK_CTL +# GPIO_NUMBER: FCH GPIO number +# GPIO_IO_MUX: Value write to IOMUX to configure this GPIO +# GPIO_BANK_CTL: Value write to GPIOBankCtl[23:16] to configure this GPIO +ifeq ($(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE),y) +APCB_BOARD_ID_GPIO0 = 121 1 0 +APCB_BOARD_ID_GPIO1 = 120 1 0 +APCB_BOARD_ID_GPIO2 = 131 3 0 +APCB_BOARD_ID_GPIO3 = 116 1 0 +else ifeq ($(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ),y) +APCB_BOARD_ID_GPIO0 = 132 1 0 +APCB_BOARD_ID_GPIO1 = 90 1 0 +APCB_BOARD_ID_GPIO2 = 86 3 0 +APCB_BOARD_ID_GPIO3 = 69 1 0 +else +$(error Undefined APCB selection GPIOS for Zork baseboard) +endif #($(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE),y) diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/devicetree.cb new file mode 100644 index 0000000000..c90c3225a3 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/devicetree.cb @@ -0,0 +1,189 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/picasso + + # Set FADT Configuration + register "fadt_pm_profile" = "PM_MOBILE" + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" + register "fadt_flags" = "ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_32BIT_TIMER | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_SEALED_CASE | + ACPI_FADT_PCI_EXPRESS_WAKE | + ACPI_FADT_REMOTE_POWER_ON" + + register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" + + # Start : OPN Performance Configuration + # (Configuratin that is common for all variants) + # For the below fields, 0 indicates use SOC default + + # PROCHOT_L de-assertion Ramp Time + register "prochot_l_deassertion_ramp_time" = "20" #mS + + # Lower die temperature limit + register "thermctl_limit" = "100" #degrees C + + # FP5 Processor Voltage Supply PSI Currents + register "psi0_current_limit" = "18000" #mA + register "psi0_soc_current_limit" = "12000" #mA + register "vddcr_soc_voltage_margin" = "0" #mV + register "vddcr_vdd_voltage_margin" = "0" #mV + + # VRM Limits + register "vrm_maximum_current_limit" = "0" #mA + register "vrm_soc_maximum_current_limit" = "0" #mA + register "vrm_current_limit" = "0" #mA + register "vrm_soc_current_limit" = "0" #mA + + # Misc SMU settings + register "sb_tsi_alert_comparator_mode_en" = "0" + register "core_dldo_bypass" = "1" + register "min_soc_vid_offset" = "0" + register "aclk_dpm0_freq_400MHz" = "0" + + # End : OPN Performance Configuration + + register "sd_emmc_config" = "SD_EMMC_EMMC_HS400" + + # SPI Configuration + register "common_config.spi_config" = "{ + .normal_speed = SPI_SPEED_66M, /* MHz */ + .fast_speed = SPI_SPEED_66M, /* MHz */ + .altio_speed = SPI_SPEED_66M, /* MHz */ + .tpm_speed = SPI_SPEED_66M, /* MHz */ + .read_mode = SPI_READ_MODE_DUAL112, + }" + + # eSPI Configuration + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x62, + /* + * Only 0x62 and 0x66 are required. But, this is not supported by + * standard IO decodes and there are only 4 generic I/O windows + * available. Hence, open a window from 0x62-0x67. + */ + .size = 5, + }, + .generic_io_range[1] = { + .base = 0x800, /* EC_HOST_CMD_REGION0 */ + .size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */ + }, + .generic_io_range[2] = { + .base = 0x900, /* EC_LPC_ADDR_MEMMAP */ + .size = 255, /* EC_MEMMAP_SIZE */ + }, + .generic_io_range[3] = { + .base = 0x200, /* EC_LPC_ADDR_HOST_DATA */ + .size = 8, /* 0x200 - 0x207 */ + }, + + .io_mode = ESPI_IO_MODE_QUAD, + .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, + .crc_check_enable = 1, + .dedicated_alert_pin = 1, + .periph_ch_en = 1, + .vw_ch_en = 1, + .oob_ch_en = 0, + .flash_ch_en = 0, + + .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_LOW(1) | ESPI_VW_IRQ_LEVEL_LOW(12), + }" + + register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" + + register "irq_override" = "{ + /* PS/2 keyboard IRQ1 override */ + {1, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH}, + + /* PS/2 mouse IRQ12 override */ + {12, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH}, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Dummy Host Bridge, must be enabled + device pci 1.1 off end # GPP Bridge 0 + device pci 1.2 on end # GPP Bridge 1 - Wifi + device pci 1.3 on end # GPP Bridge 2 - SD + device pci 1.4 off end # GPP Bridge 3 + device pci 1.5 off end # GPP Bridge 4 + device pci 8.0 on end # Dummy Host Bridge, must be enabled + device pci 8.1 on # Internal GPP Bridge 0 to Bus A + device pci 0.0 on end # Internal GPU + device pci 0.1 on end # Display HDA + device pci 0.2 on end # Crypto Coprocesor + device pci 0.5 on end # Audio + device pci 0.6 on end # HDA + device pci 0.7 on end # non-Sensor Fusion Hub device + end + device pci 8.2 on # Internal GPP Bridge 0 to Bus B + device pci 0.0 on end # AHCI + end + device pci 14.0 on end # SM + device pci 14.3 on # - D14F3 bridge + chip ec/google/chromeec + device pnp 0c09.0 on + chip ec/google/chromeec/i2c_tunnel + register "uid" = "1" + register "remote_bus" = "8" + device generic 0.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "uid" = "1" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(62)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end + end + chip ec/google/chromeec/i2c_tunnel + register "name" = ""MSTH"" + register "uid" = "1" + register "remote_bus" = "9" + device generic 1.0 on end + end + end + end + end + device pci 18.0 on end # Data fabric [0-7] + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + end # domain + + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_91)" + register "sdmode_delay" = "5" + device generic 0.1 on end + end + + device mmio 0xfedc5000 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "desc" = ""Cr50 TPM"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)" + device i2c 50 on end + end + end + +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c new file mode 100644 index 0000000000..e67755ccc5 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +void __weak variant_get_pcie_ddi_descriptors(const picasso_fsp_pcie_descriptor **pcie_descs, + size_t *pcie_num, + const picasso_fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num) +{ + *pcie_descs = baseboard_get_pcie_descriptors(pcie_num); + *ddi_descs = baseboard_get_ddi_descriptors(ddi_num); +} + +static const picasso_fsp_pcie_descriptor pcie_descriptors[] = { + { + // NVME SSD + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = NVME_START_LANE, + .end_lane = NVME_END_LANE, + .device_number = 1, + .function_number = 7, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = NVME_CLKREQ, + .clk_pm_support = true, + }, + { + // WLAN + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = WLAN_START_LANE, + .end_lane = WLAN_END_LANE, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = WLAN_CLKREQ, + .clk_pm_support = true, + }, + { + // SD Reader + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = SD_START_LANE, + .end_lane = SD_END_LANE, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = SD_CLKREQ, + } +}; + +const picasso_fsp_pcie_descriptor *baseboard_get_pcie_descriptors(size_t *num) +{ + *num = ARRAY_SIZE(pcie_descriptors); + return pcie_descriptors; +} + +const picasso_fsp_ddi_descriptor *baseboard_get_ddi_descriptors(size_t *num) +{ + /* Different configurations of dalboz have different ddi configurations. + * Therefore, don't provide any baseboard defaults. */ + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c new file mode 100644 index 0000000000..fb96ff2537 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +void __weak variant_get_pcie_ddi_descriptors(const picasso_fsp_pcie_descriptor **pcie_descs, + size_t *pcie_num, + const picasso_fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num) +{ + *pcie_descs = baseboard_get_pcie_descriptors(pcie_num); + *ddi_descs = baseboard_get_ddi_descriptors(ddi_num); +} + +/* FP5 package can support Type 1 (Picasso) and Type 2 (Dali), however some + * Type 1 parts, while reporting as Picasso through cpuid, are fused like a Dali. + * Those parts need to be configured as Type 2. */ + +static const picasso_fsp_pcie_descriptor pco_pcie_descriptors[] = { + { + // NVME SSD + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 0, + .end_lane = 3, + .device_number = 1, + .function_number = 7, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = NVME_CLKREQ, + }, + { + // WLAN + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 4, + .end_lane = 4, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = WLAN_CLKREQ, + .clk_pm_support = true, + }, + { + // SD Reader + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 5, + .end_lane = 5, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = SD_CLKREQ, + } +}; + +static const picasso_fsp_pcie_descriptor dali_pcie_descriptors[] = { + { + // NVME SSD + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = NVME_START_LANE, + .end_lane = NVME_END_LANE, + .device_number = 1, + .function_number = 7, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = NVME_CLKREQ, + .clk_pm_support = true, + }, + { + // WLAN + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = WLAN_START_LANE, + .end_lane = WLAN_END_LANE, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = WLAN_CLKREQ, + .clk_pm_support = true, + }, + { + // SD Reader + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = SD_START_LANE, + .end_lane = SD_END_LANE, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = SD_CLKREQ, + } +}; + +const picasso_fsp_pcie_descriptor *baseboard_get_pcie_descriptors(size_t *num) +{ + /* Type 2 or Type 1 fused like Type 2. */ + if (soc_is_dali()) { + *num = ARRAY_SIZE(dali_pcie_descriptors); + return dali_pcie_descriptors; + } else { + /* Type 1 */ + *num = ARRAY_SIZE(pco_pcie_descriptors); + return pco_pcie_descriptors; + } + +} + +static const picasso_fsp_ddi_descriptor pco_ddi_descriptors[] = { + { + // DDI0, DP0, eDP + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { + // DDI1, DP1, DB OPT1 HDMI + .connector_type = HDMI, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { + // DDI2, DP2, DB OPT1 USB-C1 + .connector_type = DP, + .aux_index = AUX3, + .hdp_index = HDP3, + }, + { + // DDI3, DP3, USB-C0 + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +static const picasso_fsp_ddi_descriptor dali_ddi_descriptors[] = { + { + // DDI0, DP0, eDP + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { + // DDI1, DP1, DB OPT2 USB-C1 / DB OPT3 MST hub + .connector_type = DP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { + // DDI2, DP3, USB-C0 + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +const picasso_fsp_ddi_descriptor *baseboard_get_ddi_descriptors(size_t *num) +{ + /* Type 2 or Type 1 fused like Type 2. */ + if (soc_is_dali()) { + *num = ARRAY_SIZE(dali_ddi_descriptors); + return dali_ddi_descriptors; + } else { + /* Type 1 */ + *num = ARRAY_SIZE(pco_ddi_descriptors); + return pco_ddi_descriptors; + } +} diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c new file mode 100644 index 0000000000..b5b2847841 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -0,0 +1,238 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +static const struct soc_amd_gpio gpio_set_stage_reset[] = { + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_UP, EDGE_LOW, STATUS), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_UP), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_UP), + + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + + /* ESPI_ALERT_L (may be unused) */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP), + + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), + /* BIOS_FLASH_WP_ODL */ + PAD_GPI(GPIO_137, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), +}; + +static const struct soc_amd_gpio gpio_set_stage_rom[] = { + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_UP, EDGE_LOW, STATUS), + /* PEN_POWER_EN - reset */ + PAD_GPO(GPIO_5, LOW), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_UP), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_UP), + /* EC_FCH_WAKE_L */ + PAD_GPI(GPIO_24, PULL_UP), + PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5), + /* PCIE_RST0_L - Fixed timings */ + /* TODO: Make sure this gets locked at end of post */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* PCIE_RST1_L - Variable timings (May remove) */ + PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, HIGH), + /* WIFI_AUX_RESET_L */ + PAD_GPO(GPIO_42, HIGH), + /* EN_PWR_TOUCHPAD_PS2 - reset */ + PAD_GPO(GPIO_67, LOW), + /* EMMC_RESET - reset (default stuffing unused)*/ + PAD_GPO(GPIO_68, HIGH), + /* EN_PWR_CAMERA - reset */ + PAD_GPO(GPIO_76, LOW), + /* CLK_REQ0_L - WIFI */ + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP), + /* ESPI_ALERT_L (may be unused) */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP), + /* CLK_REQ1_L - SD Card */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP), + /* CLK_REQ2_L - NVMe */ + PAD_NF(GPIO_116, CLK_REQ2_L, PULL_UP), + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), + /* BIOS_FLASH_WP_ODL */ + PAD_GPI(GPIO_137, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), + /* USI_RESET - reset */ + PAD_GPO(GPIO_140, HIGH), + /* USB_HUB_RST_L - reset*/ + PAD_GPO(GPIO_141, LOW), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_142, HIGH), +}; + +static const struct soc_amd_gpio gpio_set_wifi[] = { + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_29, HIGH), +}; + +static const struct soc_amd_gpio gpio_set_stage_ram[] = { + + /* PWR_BTN_L */ + PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP), + /* SYS_RESET_L */ + PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), + /* PCIE_WAKE_L */ + PAD_NF(GPIO_2, WAKE_L, PULL_UP), + /* PEN_DETECT_ODL */ + PAD_GPI(GPIO_4, PULL_UP), + /* PEN_POWER_EN - Enabled*/ + PAD_GPO(GPIO_5, HIGH), + /* DMIC_SEL */ + PAD_GPO(GPIO_6, LOW), // Select Camera 1 Dmic + /* I2S_SDIN */ + PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), + /* I2S_LRCLK - Bit banged in depthcharge */ + PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), + /* TOUCHPAD_INT_ODL */ + /* TODO: Make sure driver sets as wake source */ + PAD_GPI(GPIO_9, PULL_UP), + /* S0iX SLP - (unused - goes to EC & FPMCU */ + PAD_GPI(GPIO_10, PULL_UP), + /* EC_IN_RW_OD */ + PAD_GPI(GPIO_11, PULL_UP), + /* USI_INT_ODL */ + PAD_GPI(GPIO_12, PULL_UP), + /* DMIC_SEL */ + PAD_NF(GPIO_16, USB_OC0_L, PULL_UP), + /* USB_OC1_L - USB C1 */ + PAD_NF(GPIO_17, USB_OC1_L, PULL_UP), + /* WIFI_DISABLE */ + PAD_GPO(GPIO_18, LOW), + /* EMMC_CMD */ + PAD_NF(GPIO_21, EMMC_CMD, PULL_UP), + /* EC_FCH_SCI_ODL */ + PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW), + /* AC_PRES */ + PAD_NF(GPIO_23, AC_PRES, PULL_UP), + /* EC_AP_INT_ODL (Sensor Framesync) */ + PAD_GPI(GPIO_31, PULL_UP), + /* */ + PAD_GPI(GPIO_32, PULL_DOWN), + /* EN_PWR_TOUCHPAD_PS2 */ + /* + * EN_PWR_TOUCHPAD_PS2 - Make sure Ext ROM Sharing is disabled before + * using this GPIO. Otherwise SPI flash access will be very slow. + */ + PAD_GPO(GPIO_67, HIGH), + /* EMMC_RESET */ + PAD_GPO(GPIO_68, LOW), + /* RAM ID 3*/ + PAD_GPI(GPIO_69, PULL_NONE), + /* EMMC_CLK */ + PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE), + /* EMMC_DATA4 */ + PAD_NF(GPIO_74, EMMC_DATA4, PULL_NONE), + /* EMMC_DATA6 */ + PAD_NF(GPIO_75, EMMC_DATA6, PULL_NONE), + /* EN_PWR_CAMERA */ + PAD_GPO(GPIO_76, HIGH), + /* UNUSED */ + PAD_GPO(GPIO_84, HIGH), + /* APU_EDP_BL_DISABLE TODP: Set low in depthcharge */ + PAD_GPO(GPIO_85, HIGH), + /* RAM ID 2 */ + PAD_GPI(GPIO_86, PULL_NONE), + /* EMMC_DATA7 */ + PAD_NF(GPIO_87, EMMC_DATA7, PULL_NONE), + /* EMMC_DATA5 */ + PAD_NF(GPIO_88, EMMC_DATA5, PULL_NONE), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* RAM ID 1 */ + PAD_GPI(GPIO_90, PULL_NONE), + /* EN_SPKR TODO: Verify driver enables this (add to ACPI) */ + PAD_GPO(GPIO_91, LOW), + /* EMMC_DATA0 */ + PAD_NF(GPIO_104, EMMC_DATA0, PULL_NONE), + /* EMMC_DATA1 */ + PAD_NF(GPIO_105, EMMC_DATA1, PULL_NONE), + /* EMMC_DATA2 */ + PAD_NF(GPIO_106, EMMC_DATA2, PULL_NONE), + /* EMMC_DATA3 */ + PAD_NF(GPIO_107, EMMC_DATA3, PULL_NONE), + /* EMMC_DS */ + PAD_NF(GPIO_109, EMMC_DS, PULL_NONE), + /* I2C2_SCL - USI/Touchpad */ + PAD_NF(GPIO_113, I2C2_SCL, PULL_UP), + /* I2C2_SDA - USI/Touchpad */ + PAD_NF(GPIO_114, I2C2_SDA, PULL_UP), + /* KBRST_L */ + PAD_NF(GPIO_129, KBRST_L, PULL_UP), + /* RAM ID 0 */ + PAD_GPI(GPIO_132, PULL_NONE), + /* DEV_BEEP_CODEC_IN (Dev beep Data out) */ + PAD_GPI(GPIO_135, PULL_NONE), + /* DEV_BEEP_BCLK */ + PAD_GPI(GPIO_139, PULL_NONE), + /* USI_RESET */ + PAD_GPO(GPIO_140, LOW), + /* USB_HUB_RST_L */ + PAD_GPO(GPIO_141, HIGH), + /* BT_DISABLE */ + PAD_GPO(GPIO_143, LOW), + /* + * USI_REPORT_EN - TODO: Driver resets this later. + * Do we want it high or low initially? + */ + PAD_GPO(GPIO_144, HIGH), +}; + +const __weak +struct soc_amd_gpio *variant_early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_reset); + return gpio_set_stage_reset; +} + +const __weak +struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_rom); + return gpio_set_stage_rom; +} + +const __weak +struct soc_amd_gpio *variant_wifi_romstage_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_wifi); + return gpio_set_wifi; +} + +const __weak +struct soc_amd_gpio *variant_base_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_ram); + return gpio_set_stage_ram; +} + +/* + * This function is still needed for boards that sets gevents above 23 + * that will generate SCI or SMI. Normally this function + * points to a table of gevents and what needs to be set. The code that + * calls it was modified so that when this function returns NULL then the + * caller does nothing. + */ +const __weak struct sci_source *get_gpe_table(size_t *num) +{ + return NULL; +} diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c new file mode 100644 index 0000000000..6101330a79 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -0,0 +1,247 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +static const struct soc_amd_gpio gpio_set_stage_reset[] = { + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_UP, EDGE_LOW, STATUS), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_UP), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_UP), + + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + + /* ESPI_ALERT_L (may be unused) */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP), + + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), + /* BIOS_FLASH_WP_ODL */ + PAD_GPI(GPIO_137, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), +}; + +static const struct soc_amd_gpio gpio_set_stage_rom[] = { + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_UP, EDGE_LOW, STATUS), + /* PEN_POWER_EN - reset */ + PAD_GPO(GPIO_5, LOW), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_UP), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_UP), + /* EC_FCH_WAKE_L */ + PAD_GPI(GPIO_24, PULL_UP), + PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5), + /* PCIE_RST0_L - Fixed timings */ + /* TODO: Make sure this gets locked at end of post */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* PCIE_RST1_L - Variable timings (May remove) */ + PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, HIGH), + /* WIFI_AUX_RESET_L */ + PAD_GPO(GPIO_42, HIGH), + /* EN_PWR_TOUCHPAD_PS2 - reset */ + PAD_GPO(GPIO_67, LOW), + /* EMMC_RESET - reset (default stuffing unused)*/ + PAD_GPO(GPIO_68, HIGH), + /* EN_PWR_CAMERA - reset */ + PAD_GPO(GPIO_76, LOW), + /* RAM_ID_4 */ + PAD_GPI(GPIO_84, PULL_NONE), + /* CLK_REQ0_L - WIFI */ + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP), + /* ESPI_ALERT_L (may be unused) */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP), + /* CLK_REQ1_L - SD Card */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP), + /* RAM_ID_3 */ + PAD_GPI(GPIO_116, PULL_NONE), + /* RAM_ID_1 */ + PAD_GPI(GPIO_120, PULL_NONE), + /* RAM_ID_0 */ + PAD_GPI(GPIO_121, PULL_NONE), + /* RAM_ID_2 */ + PAD_GPI(GPIO_131, PULL_NONE), + /* CLK_REQ4_L - SSD */ + PAD_NF(GPIO_132, CLK_REQ4_L, PULL_UP), + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), + /* BIOS_FLASH_WP_ODL */ + PAD_GPI(GPIO_137, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), + /* USI_RESET - reset */ + PAD_GPO(GPIO_140, HIGH), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_142, HIGH), +}; + +static const struct soc_amd_gpio gpio_set_wifi[] = { + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_29, HIGH), +}; + +static const struct soc_amd_gpio gpio_set_stage_ram[] = { + + /* PWR_BTN_L */ + PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP), + /* SYS_RESET_L */ + PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), + /* PCIE_WAKE_L */ + PAD_NF(GPIO_2, WAKE_L, PULL_UP), + /* PEN_DETECT_ODL */ + PAD_GPI(GPIO_4, PULL_UP), + /* PEN_POWER_EN - Enabled*/ + PAD_GPO(GPIO_5, HIGH), + /* FPMCU_INT_L */ + PAD_GPI(GPIO_6, PULL_UP), + PAD_WAKE(GPIO_6, PULL_UP, EDGE_LOW, S3_S4_S5), + /* I2S_SDIN */ + PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), + /* I2S_LRCLK - Bit banged in depthcharge */ + PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), + /* TOUCHPAD_INT_ODL */ + /* TODO: Make sure driver sets as wake source */ + PAD_GPI(GPIO_9, PULL_UP), + /* S0iX SLP - (unused - goes to EC & FPMCU */ + PAD_GPI(GPIO_10, PULL_UP), + /* FPMCU_RST_L */ + PAD_GPO(GPIO_11, HIGH), + /* USI_INT_ODL */ + PAD_GPI(GPIO_12, PULL_UP), + /* DMIC_SEL */ + PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic + /* BT_DISABLE */ + PAD_GPO(GPIO_14, LOW), + /* USB_OC0_L - USB C0 + USB A0 */ + PAD_NF(GPIO_16, USB_OC0_L, PULL_UP), + /* USB_OC1_L - USB C1 + USB A1 */ + PAD_NF(GPIO_17, USB_OC1_L, PULL_UP), + /* WIFI_DISABLE */ + PAD_GPO(GPIO_18, LOW), + /* EMMC_CMD */ + PAD_NF(GPIO_21, EMMC_CMD, PULL_UP), + /* EC_FCH_SCI_ODL */ + PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW), + /* AC_PRES */ + PAD_NF(GPIO_23, AC_PRES, PULL_UP), + /* EC_AP_INT_ODL (Sensor Framesync) */ + PAD_GPI(GPIO_31, PULL_UP), + /* EN_PWR_FP */ + PAD_GPO(GPIO_32, HIGH), + /* EN_PWR_TOUCHPAD_PS2 */ + /* + * EN_PWR_TOUCHPAD_PS2 - Make sure Ext ROM Sharing is disabled before + * using this GPIO. Otherwise SPI flash access will be very slow. + */ + PAD_GPO(GPIO_67, HIGH), + /* EMMC_RESET */ + PAD_GPO(GPIO_68, LOW), + /* FPMCU_BOOT0 - TODO: Check this */ + PAD_GPO(GPIO_69, LOW), + /* EMMC_CLK */ + PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE), + /* EMMC_DATA4 */ + PAD_NF(GPIO_74, EMMC_DATA4, PULL_NONE), + /* EMMC_DATA6 */ + PAD_NF(GPIO_75, EMMC_DATA6, PULL_NONE), + /* EN_PWR_CAMERA */ + PAD_GPO(GPIO_76, HIGH), + /* APU_EDP_BL_DISABLE TODP: Set low in depthcharge */ + PAD_GPO(GPIO_85, HIGH), + /* MST_GPIO_2 (Fw Update HDMI hub) */ + PAD_GPI(GPIO_86, PULL_NONE), + /* EMMC_DATA7 */ + PAD_NF(GPIO_87, EMMC_DATA7, PULL_NONE), + /* EMMC_DATA5 */ + PAD_NF(GPIO_88, EMMC_DATA5, PULL_NONE), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* MST_GPIO_3 (Fw Update HDMI hub) */ + PAD_GPI(GPIO_90, PULL_NONE), + /* EN_SPKR TODO: Verify driver enables this (add to ACPI) */ + PAD_GPO(GPIO_91, LOW), + /* EMMC_DATA0 */ + PAD_NF(GPIO_104, EMMC_DATA0, PULL_NONE), + /* EMMC_DATA1 */ + PAD_NF(GPIO_105, EMMC_DATA1, PULL_NONE), + /* EMMC_DATA2 */ + PAD_NF(GPIO_106, EMMC_DATA2, PULL_NONE), + /* EMMC_DATA3 */ + PAD_NF(GPIO_107, EMMC_DATA3, PULL_NONE), + /* EMMC_DS */ + PAD_NF(GPIO_109, EMMC_DS, PULL_NONE), + /* I2C2_SCL - USI/Touchpad */ + PAD_NF(GPIO_113, I2C2_SCL, PULL_UP), + /* I2C2_SDA - USI/Touchpad */ + PAD_NF(GPIO_114, I2C2_SDA, PULL_UP), + /* KBRST_L */ + PAD_NF(GPIO_129, KBRST_L, PULL_UP), + /* EC_IN_RW_OD */ + PAD_GPI(GPIO_130, PULL_UP), + /* DEV_BEEP_CODEC_IN (Dev beep Data out) */ + PAD_GPI(GPIO_135, PULL_NONE), + /* DEV_BEEP_BCLK */ + PAD_GPI(GPIO_139, PULL_NONE), + /* USI_RESET */ + PAD_GPO(GPIO_140, LOW), + /* UART1_RXD - FPMCU */ + PAD_NF(GPIO_141, UART1_RXD, PULL_NONE), + /* UART1_TXD - FPMCU */ + PAD_NF(GPIO_143, UART1_TXD, PULL_NONE), + /* USI_REPORT_EN */ + /* TODO: Driver resets this later. Do we want it high or low initially? */ + PAD_GPO(GPIO_144, HIGH), +}; + +const __weak +struct soc_amd_gpio *variant_early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_reset); + return gpio_set_stage_reset; +} + +const __weak +struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_rom); + return gpio_set_stage_rom; +} + +const __weak +struct soc_amd_gpio *variant_wifi_romstage_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_wifi); + return gpio_set_wifi; +} + +const __weak +struct soc_amd_gpio *variant_base_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_ram); + return gpio_set_stage_ram; +} + +/* + * This function is still needed for boards that sets gevents above 23 + * that will generate SCI or SMI. Normally this function + * points to a table of gevents and what needs to be set. The code that + * calls it was modified so that when this function returns NULL then the + * caller does nothing. + */ +const __weak struct sci_source *get_gpe_table(size_t *num) +{ + return NULL; +} diff --git a/src/mainboard/google/zork/variants/baseboard/helpers.c b/src/mainboard/google/zork/variants/baseboard/helpers.c new file mode 100644 index 0000000000..06cc9ad4ff --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/helpers.c @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Global definitions for FW_CONFIG values */ +enum { + /* Daughterboard index for attributes. */ + FW_CONFIG_MASK_DB_INDEX = 0xf, + FW_CONFIG_DB_INDEX_SHIFT = 0, + /* Mainboard USB index for attributes. */ + FW_CONFIG_MASK_MB_USB_INDEX = 0xf, + FW_CONFIG_MB_USB_INDEX_SHIFT = 4, + /* Lid accelerometer properties. */ + FW_CONFIG_MASK_LID_ACCEL = 0x7, + FW_CONFIG_LID_ACCEL_SHIFT = 8, + /* Base gyro sensor properties. */ + FW_CONFIG_MASK_BASE_GYRO = 0x7, + FW_CONFIG_BASE_GYRO_SHIFT = 11, + /* Keyboard backlight presence */ + FW_CONFIG_MASK_KEYB_BL = 0x1, + FW_CONFIG_KEYB_BL_SHIFT = 14, + /* Tablet mode supported through lid angle */ + FW_CONFIG_MASK_LID_ANGLE_TABLET_MODE = 0x1, + FW_CONFIG_LID_ANGLE_TABLET_MODE_SHIFT = 15, + /* Stylus presence */ + FW_CONFIG_MASK_STYLUS = 0x1, + FW_CONFIG_STYLUS_SHIFT = 16, + /* Fingerprint sensor presence */ + FW_CONFIG_MASK_FP = 0x1, + FW_CONFIG_SHIFT_FP = 17, + /* NVME presence */ + FW_CONFIG_MASK_NVME = 0x1, + FW_CONFIG_SHIFT_NVME = 18, + /* EMMC presence */ + FW_CONFIG_MASK_EMMC = 0x1, + FW_CONFIG_SHIFT_EMMC = 19, + /* SD controller type */ + FW_CONFIG_MASK_SD_CTRLR = 0x7, + FW_CONFIG_SHIFT_SD_CTRLR = 20, + /* SPI speed value */ + FW_CONFIG_MASK_SPI_SPEED = 0xf, + FW_CONFIG_SHIFT_SPI_SPEED = 23, + /* Fan information */ + FW_CONFIG_MASK_FAN = 0x3, + FW_CONFIG_SHIFT_FAN = 27, +}; + +int variant_fw_config_valid(void) +{ + static uint32_t board_version; + const uint32_t bv_valid = CONFIG_VARIANT_BOARD_VER_FW_CONFIG_VALID; + + if (!CONFIG(VARIANT_HAS_FW_CONFIG)) + return 0; + + /* Fast path for non-zero board version. */ + if (board_version >= bv_valid) + return 1; + + if (google_chromeec_cbi_get_board_version(&board_version)) { + printk(BIOS_ERR, "Unable to obtain board version for FW_CONFIG\n"); + return 0; + } + + if (board_version >= bv_valid) + return 1; + + return 0; +} + +static int get_fw_config(uint32_t *val) +{ + static uint32_t known_value; + + if (!variant_fw_config_valid()) + return -1; + + if (known_value) { + *val = known_value; + return 0; + } + + if (google_chromeec_cbi_get_fw_config(&known_value)) { + printk(BIOS_ERR, "FW_CONFIG not set in CBI\n"); + return -1; + } + + *val = known_value; + + return 0; +} + +static unsigned int extract_field(uint32_t mask, int shift) +{ + uint32_t fw_config; + + /* On errors nothing is assumed to be set. */ + if (get_fw_config(&fw_config)) + return 0; + + return (fw_config >> shift) & mask; +} + +int variant_has_emmc(void) +{ + return !!extract_field(FW_CONFIG_MASK_EMMC, FW_CONFIG_SHIFT_EMMC); +} + +int variant_has_nvme(void) +{ + return !!extract_field(FW_CONFIG_MASK_NVME, FW_CONFIG_SHIFT_NVME); +} diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/audio.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/audio.asl new file mode 100644 index 0000000000..ae5663e7c7 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/audio.asl @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +Scope (EC0.CREC) { + #include +} + +/* machine driver */ +Device (I2SM) +{ + Name (_HID, "AMDI5682") + Name (_UID, 1) + Name (_DDN, "I2S machine Driver") + + Name (_CRS, ResourceTemplate () + { +#if CONFIG(BOARD_GOOGLE_BASEBOARD_DALBOZ) + /* DMIC select GPIO */ + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, + IoRestrictionNone, "\\_SB.GPIO", 0x00, + ResourceConsumer,,) { 6 } +#else + /* DMIC select GPIO */ + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, + IoRestrictionNone, "\\_SB.GPIO", 0x00, + ResourceConsumer,,) { 13 } +#endif + }) + /* Device-Specific Data */ + Name (_DSD, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () + { + "dmic-gpio", Package () { ^I2SM, 0, 0, 0 } + } + } + + }) + Method (_STA) + { + Return (0xF) + } +} diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/mainboard.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/mainboard.asl new file mode 100644 index 0000000000..b3d39969f1 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/mainboard.asl @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sb_fch.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sb_fch.asl new file mode 100644 index 0000000000..21c31a3b01 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sb_fch.asl @@ -0,0 +1,246 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +Device (AAHB) +{ + Name (_HID, "AAHB0000") + Name (_UID, 0x0) + Name (_CRS, ResourceTemplate() + { + Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000) + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (GPIO) +{ + Name (_HID, GPIO_DEVICE_NAME) + Name (_CID, GPIO_DEVICE_NAME) + Name (_UID, 0) + Name (_DDN, GPIO_DEVICE_DESC) + + Method(_CRS ,0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Level, + ActiveLow, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, 0xFED81500, 0x300) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If(PMOD) { + IRQN=IGPI + } Else { + IRQN=PGPI + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, 0xFED81500, 0x300) + }) + } Else { + Return(local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (MMC0) +{ + Name (_HID, "AMDI0040") + Name (_UID, 0x0) + Method(_CRS ,0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Level, + ActiveLow, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_EMMC_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If(PMOD) { + IRQN=IMMC + } Else { + IRQN=PMMC + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_EMMC_BASE, 0x1000) + }) + } Else { + Return(local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (FUR0) +{ + Name (_HID, "AMD0020") + Name (_UID, 0x0) + Method(_CRS ,0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC0_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If(PMOD) { + IRQN=IUA0 + } Else { + IRQN=PUA0 + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC0_BASE, 0x1000) + }) + } Else { + Return(local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (FUR1) { + Name (_HID, "AMD0020") + Name (_UID, 0x1) + Method(_CRS ,0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If(PMOD) { + IRQN=IUA1 + } Else { + IRQN=PUA1 + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000) + }) + } Else { + Return(local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (I2C2) { + Name (_HID, "AMD0010") + Name (_UID, 0x2) + Method(_CRS ,0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If(PMOD) { + IRQN=II22 + } Else { + IRQN=PI22 + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) + }) + } Else { + Return(local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (I2C3) +{ + Name (_HID, "AMD0010") + Name (_UID, 0x3) + Method(_CRS ,0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If(PMOD) { + IRQN=II23 + } Else { + IRQN=PI23 + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000) + }) + } Else { + Return(local0) + } + } + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (MISC) +{ + Name (_HID, "AMD0040") + Name (_UID, 0x3) + Name (_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sleep.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sleep.asl new file mode 100644 index 0000000000..c8fb05fe1f --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sleep.asl @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear wake status structure. */ + Store(0, PEWD) + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + Store(7, UPWS) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl new file mode 100644 index 0000000000..8f5aa6ab5e --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +/* Thermal Zone */ + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + /* Thermal constants for passive cooling */ + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + /* Thermal zone polling frequency: 10 seconds */ + Name (_TZP, 100) + + /* Thermal sampling period for passive cooling: 2 seconds */ + Name (_TSP, 20) + + /* Convert from Degrees C to 1/10 Kelvin for ACPI */ + Method (CTOK, 1) { + /* 10th of Degrees C */ + Multiply (Arg0, 10, Local0) + + /* Convert to Kelvin */ + Add (Local0, 2732, Local0) + + Return (Local0) + } + + /* Threshold for OS to shutdown */ + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + /* Threshold for passive cooling */ + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + /* Processors used for passive cooling */ + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + Method (_TMP, 0, Serialized) + { + /* Get temperature from EC in deci-kelvin */ + Store (\_SB.PCI0.LPCB.EC0.TSRD (TMPS), Local0) + + /* Critical temperature in deci-kelvin */ + Store (CTOK (\TCRT), Local1) + + If (LGreaterEqual (Local0, Local1)) { + Store ("CRITICAL TEMPERATURE", Debug) + Store (Local0, Debug) + + /* Wait 1 second for EC to re-poll */ + Sleep (1000) + + /* Re-read temperature from EC */ + Store (\_SB.PCI0.LPCB.EC0.TSRD (TMPS), Local0) + + Store ("RE-READ TEMPERATURE", Debug) + Store (Local0, Debug) + } + + Return (Local0) + } + + } +} diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000000..8ef0645afd --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include +#include +#include + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or + * mode change event + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* Enable LID switch */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN EC_WAKE_GPI + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ +#define SIO_EC_PS2K_IRQ IRQ (Level, ActiveHigh, Exclusive) {1} +#define SIO_EC_PS2M_IRQ IRQ (Level, ActiveHigh, Exclusive) {12} + +/* + * Enable EC sync interrupt via GPIO controller, EC_SYNC_IRQ is defined in + * variant/gpio.h + */ +#define EC_ENABLE_SYNC_IRQ_GPIO + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +/* Enable Tablet switch */ +#define EC_ENABLE_TBMC_DEVICE + +#endif diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000000..4801a5ec7b --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#ifndef __ACPI__ +#include +#include + +#define H1_PCH_INT GPIO_3 +#define PEN_DETECT_ODL GPIO_4 +#define PEN_POWER_EN GPIO_5 +#define TOUCHPAD_INT_ODL GPIO_9 +#define EC_FCH_WAKE_L GPIO_24 +#define WIFI_PCIE_RESET_L GPIO_26 +#define PCIE_RST1_L GPIO_27 +#define EN_PWR_WIFI GPIO_29 +#define NVME_AUX_RESET_L GPIO_40 +#define WIFI_AUX_RESET_L GPIO_42 +#define EN_PWR_CAMERA GPIO_76 +#define EN_PWR_TOUCHPAD_PS2 GPIO_67 +#define PCIE_0_WIFI_CLKREQ_ODL GPIO_92 +#define PCIE_1_SD_CLKREQ_ODL GPIO_115 +#define BIOS_FLASH_WP_ODL GPIO_137 +#define SD_AUX_RESET_L GPIO_142 +#define WLAN_CLKREQ CLK_REQ0 +#define SD_CLKREQ CLK_REQ1 + +#if CONFIG(BOARD_GOOGLE_BASEBOARD_DALBOZ) +#define NVME_START_LANE 4 +#define NVME_END_LANE 5 +#define WLAN_START_LANE 0 +#define WLAN_END_LANE 0 +#define SD_START_LANE 1 +#define SD_END_LANE 1 +#else +#define NVME_START_LANE 0 +#define NVME_END_LANE 1 +#define WLAN_START_LANE 4 +#define WLAN_END_LANE 4 +#define SD_START_LANE 5 +#define SD_END_LANE 5 +#endif + +#if CONFIG(BOARD_GOOGLE_BASEBOARD_TREMBYLE) +#define FPMCU_INT_L GPIO_6 +#define FPMCU_RST_ODL GPIO_11 +#define EC_IN_RW_OD GPIO_130 +#define PCIE_4_NVME_CLKREQ_ODL GPIO_132 +#define NVME_CLKREQ CLK_REQ4 +#else +#define EC_IN_RW_OD GPIO_11 +#define PCIE_2_NVME_CLKREQ_ODL GPIO_116 +#define NVME_CLKREQ CLK_REQ2 +#endif + +/* SPI Write protect */ +#define CROS_WP_GPIO BIOS_FLASH_WP_ODL +#define GPIO_EC_IN_RW EC_IN_RW_OD + +/* PCIe reset pins */ +#define PCIE_0_RST WIFI_AUX_RESET_L +#define PCIE_1_RST SD_AUX_RESET_L +#define PCIE_2_RST 0 +#define PCIE_3_RST 0 +#define PCIE_4_RST NVME_AUX_RESET_L + +#endif /* _ACPI__ */ + +/* These define the GPE, not the GPIO. */ +#define EC_SCI_GPI 3 /* eSPI system event -> GPE 3 */ +#define EC_WAKE_GPI 15 /* AGPIO 24 -> GPE 15 */ + +/* EC sync irq */ +#define EC_SYNC_IRQ 31 + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/thermal.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/thermal.h new file mode 100644 index 0000000000..b3c951bbaf --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/thermal.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef THERMAL_H +#define THERMAL_H + +/* + * Picasso Thermal Requirements + * TDP (W) 15 + * T die,max (°C) 105 + * T ctl,max 105 + * T die,lmt (default) 100 + * T ctl,lmt (default) 100 + */ + +/* Control TDP Settings */ +#define CTL_TDP_SENSOR_ID 2 /* EC TIN2 */ + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 104 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 95 + +#endif diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000000..c682eca1a4 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include +#include +#include +#include +#include "chip.h" + +const struct sci_source *get_gpe_table(size_t *num); +const struct soc_amd_gpio *variant_early_gpio_table(size_t *size); +const struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size); +const struct soc_amd_gpio *variant_wifi_romstage_gpio_table(size_t *size); +/* + * This function provides base GPIO configuration table. It is typically provided by + * baseboard using a weak implementation. If GPIO configuration for a variant differs + * significantly from the baseboard, then the variant can also provide a strong implementation + * of this function. + */ +const struct soc_amd_gpio *variant_base_gpio_table(size_t *size); +/* + * This function allows variant to override any GPIOs that are different than the base GPIO + * configuration provided by variant_base_gpio_table(). + */ +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size); +void variant_romstage_entry(void); +/* Modify devictree settings during ramstage. */ +void variant_devtree_update(void); + +/* Per variant FSP-S initialization, default implementation in baseboard and + * overrideable by the variant. */ +void variant_get_pcie_ddi_descriptors(const picasso_fsp_pcie_descriptor **pcie_descs, + size_t *pcie_num, + const picasso_fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num); + +/* Provide the descriptors for the associated baseboard for the variant. These functions + * can be used for obtaining the baseboard's descriptors if the variant followed the + * baseboard. */ +const picasso_fsp_pcie_descriptor *baseboard_get_pcie_descriptors(size_t *num); +const picasso_fsp_ddi_descriptor *baseboard_get_ddi_descriptors(size_t *num); + +/* Retrieve attributes from FW_CONFIG in CBI. */ +/* Return 1 if FW_CONFIG expected to be valid, else 0. */ +int variant_fw_config_valid(void); +/* Return 0 if non-existent, 1 if present. */ +int variant_has_emmc(void); +/* Return 0 if non-existent, 1 if present. */ +int variant_has_nvme(void); + +/* Determine if booting in factory by using CROS_SKU_UNPROVISIONED. */ +int boot_is_factory_unprovisioned(void); + +#endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/zork/variants/baseboard/tpm_tis.c b/src/mainboard/google/zork/variants/baseboard/tpm_tis.c new file mode 100644 index 0000000000..52e83cf44c --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/tpm_tis.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +int tis_plat_irq_status(void) +{ + return gpio_interrupt_status(H1_PCH_INT); +} diff --git a/src/mainboard/google/zork/variants/berknip/Makefile.inc b/src/mainboard/google/zork/variants/berknip/Makefile.inc new file mode 100644 index 0000000000..b1212bcbdd --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ./spd + +romstage-y += ./romstage.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/zork/variants/berknip/gpio.c b/src/mainboard/google/zork/variants/berknip/gpio.c new file mode 100644 index 0000000000..f7a1e37e06 --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/gpio.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +static const struct soc_amd_gpio berknip_v1_gpio_set_stage_ram[] = { + /* USB_OC4_L - USB_A1 */ + PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), + /* USB_OC2_L - USB A0 */ + PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), +}; +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + uint32_t board_version; + + /* + * If board version cannot be read, assume that this is an older revision of the board + * and so apply overrides. If board version is provided by the EC, then apply overrides + * if version < 2. + */ + if (google_chromeec_cbi_get_board_version(&board_version)) + board_version = 1; + + if (board_version <= 1) { + *size = ARRAY_SIZE(berknip_v1_gpio_set_stage_ram); + return berknip_v1_gpio_set_stage_ram; + } + + *size = 0; + return NULL; +} diff --git a/src/mainboard/google/zork/variants/berknip/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/berknip/include/variant/acpi/audio.asl new file mode 100644 index 0000000000..900e36f277 --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/include/variant/acpi/audio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/berknip/include/variant/acpi/mainboard.asl b/src/mainboard/google/zork/variants/berknip/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..a1161edb5f --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/include/variant/acpi/mainboard.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/berknip/include/variant/acpi/sleep.asl b/src/mainboard/google/zork/variants/berknip/include/variant/acpi/sleep.asl new file mode 100644 index 0000000000..8177a9df2a --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/include/variant/acpi/sleep.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/berknip/include/variant/acpi/thermal.asl b/src/mainboard/google/zork/variants/berknip/include/variant/acpi/thermal.asl new file mode 100644 index 0000000000..7a793d8102 --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/include/variant/acpi/thermal.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/berknip/include/variant/ec.h b/src/mainboard/google/zork/variants/berknip/include/variant/ec.h new file mode 100644 index 0000000000..9e61a440cf --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/include/variant/ec.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/berknip/include/variant/gpio.h b/src/mainboard/google/zork/variants/berknip/include/variant/gpio.h new file mode 100644 index 0000000000..dfaeec3ae1 --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/berknip/include/variant/thermal.h b/src/mainboard/google/zork/variants/berknip/include/variant/thermal.h new file mode 100644 index 0000000000..2af647973d --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/include/variant/thermal.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb new file mode 100644 index 0000000000..fe83307954 --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/picasso + + # Start : OPN Performance Configuration + # See devhub #55593 Chapter 3.2 for documentation + # For the below fields, 0 indicates use SOC default + + # System config index + register "system_config" = "3" + + # Set STAPM confiuration. All of these fields must be set >0 to take affect + register "slow_ppt_limit" = "25000" #mw + register "fast_ppt_limit" = "30000" #mw + register "slow_ppt_time_constant" = "5" #second + register "stapm_time_constant" = "200" #second + register "sustained_power_limit" = "25000" #mw + + register "telemetry_vddcr_vdd_slope" = "78289" #mA + register "telemetry_vddcr_vdd_offset" = "0" + register "telemetry_vddcr_soc_slope" = "24519" #mA + register "telemetry_vddcr_soc_offset" = "0" + + # End : OPN Performance Configuration + + # Enable I2C2 for trackpad, touchscreen, pen at 400kHz + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 3, + .fall_time_ns = 2, + }" + + # Enable I2C3 for H1 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 16, + .fall_time_ns = 8, + .early_init = true, + }" + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 1.6 off end # GPP Bridge 5 + device pci 1.7 on end # GPP Bridge 6 - NVME + device pci 8.1 on # Internal GPP Bridge 0 to Bus A + device pci 0.3 on end # USB 3.1 + device pci 0.4 on end # USB 3.1 + end + device pci 14.6 off end # Non-Functional SDHCI + end # domain + + device mmio 0xfedc4000 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "wake" = "7" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "generic.wake" = "7" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "reset_delay_ms" = "20" + register "has_power_resource" = "1" + device i2c 39 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "reset_delay_ms" = "20" + register "has_power_resource" = "1" + device i2c 10 on end + end + end +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/berknip/romstage.c b/src/mainboard/google/zork/variants/berknip/romstage.c new file mode 100644 index 0000000000..6d93b5e91e --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/romstage.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include +#include +#include + +void variant_romstage_entry(void) +{ + /* Power the wifi card */ + gpio_set(EN_PWR_WIFI, 1); +} + +static const struct soc_amd_gpio berknip_gpio_set_wifi[] = { + /* EN_PWR_WIFI - Power off. Pull high in romstage.c */ + PAD_GPO(GPIO_29, LOW), +}; + +const struct soc_amd_gpio *variant_wifi_romstage_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(berknip_gpio_set_wifi); + return berknip_gpio_set_wifi; +} diff --git a/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc b/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc new file mode 100644 index 0000000000..7731c0733b --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Ordered List of APCB entries, up to 16. +# Entries should match this pattern {NAME}_x{1,2} +# There should be a matching SPD hex file in SPD_SOURCES_DIR +# matching the pattern {NAME}.spd.hex +# The _x{1,2} suffix denotes single or dual channel +# Alternatively, generated APCBs stored at +# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included. +APCB_SOURCES = samsung-K4A8G165WC-BCTD_x2 # 0b0000 +APCB_SOURCES += samsung-K4A8G165WC-BCWE_x2 # 0b0001 +# b/149596178: We can't use dual channel channel until the PSP supports missing +# channels. +APCB_SOURCES += micron-MT40A512M16TB-062E-J_x2 # 0b0010 +APCB_SOURCES += hynix-H5AN8G6NDJR-XNC_x1 # 0b0011 +APCB_SOURCES += hynix-H5ANAG6NCMR-VKC_x2 # 0b0100 +APCB_SOURCES += empty # 0b0101 +APCB_SOURCES += empty # 0b0110 +APCB_SOURCES += empty # 0b0111 +APCB_SOURCES += empty # 0b1000 +APCB_SOURCES += empty # 0b1001 +APCB_SOURCES += empty # 0b1010 +APCB_SOURCES += empty # 0b1011 +APCB_SOURCES += empty # 0b1100 +APCB_SOURCES += empty # 0b1101 +APCB_SOURCES += empty # 0b1110 diff --git a/src/mainboard/google/zork/variants/dalboz/Makefile.inc b/src/mainboard/google/zork/variants/dalboz/Makefile.inc new file mode 100644 index 0000000000..a616e2fdc0 --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/Makefile.inc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ./spd + +romstage-y += romstage.c + +ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/zork/variants/dalboz/gpio.c b/src/mainboard/google/zork/variants/dalboz/gpio.c new file mode 100644 index 0000000000..3e705a6b34 --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/gpio.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +/* This table is used by dalboz variant with board version < 2. */ +static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = { + /* USB_OC2_L - USB A0 & A1 */ + PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), + /* Unused */ + PAD_GPI(GPIO_143, PULL_DOWN), +}; + +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + uint32_t board_version; + + /* + * If board version cannot be read, assume that this is an older revision of the board + * and so apply overrides. If board version is provided by the EC, then apply overrides + * if version < 2. + */ + if (google_chromeec_cbi_get_board_version(&board_version)) + board_version = 1; + + if (board_version < 2) { + *size = ARRAY_SIZE(bid_1_gpio_set_stage_ram); + return bid_1_gpio_set_stage_ram; + } + + *size = 0; + return NULL; +} diff --git a/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/audio.asl new file mode 100644 index 0000000000..900e36f277 --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/audio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/mainboard.asl b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..a1161edb5f --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/mainboard.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/sleep.asl b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/sleep.asl new file mode 100644 index 0000000000..8177a9df2a --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/sleep.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/thermal.asl b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/thermal.asl new file mode 100644 index 0000000000..7a793d8102 --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/thermal.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/dalboz/include/variant/ec.h b/src/mainboard/google/zork/variants/dalboz/include/variant/ec.h new file mode 100644 index 0000000000..9e61a440cf --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/include/variant/ec.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/dalboz/include/variant/gpio.h b/src/mainboard/google/zork/variants/dalboz/include/variant/gpio.h new file mode 100644 index 0000000000..dfaeec3ae1 --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/dalboz/include/variant/thermal.h b/src/mainboard/google/zork/variants/dalboz/include/variant/thermal.h new file mode 100644 index 0000000000..2af647973d --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/include/variant/thermal.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/dalboz/overridetree.cb b/src/mainboard/google/zork/variants/dalboz/overridetree.cb new file mode 100644 index 0000000000..8ac3348e2a --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/overridetree.cb @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/picasso + + # Start : OPN Performance Configuration + # See devhub #56670 Chapter 5 for documentation + # For the below fields, 0 indicates use SOC default + + # System config index + register "system_config" = "1" + + # Set STAPM confiuration. All of these fields must be set >0 to take affect + register "slow_ppt_limit" = "6000" #mw + register "fast_ppt_limit" = "9000" #mw + register "slow_ppt_time_constant" = "5" #second + register "stapm_time_constant" = "2500" #second + register "sustained_power_limit" = "4800" #mw + + # End : OPN Performance Configuration + + # I2C2 for touchscreen and trackpad + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 18, /* 0 to 2.31 (3.3 * .7) */ + .fall_time_ns = 57, /* 2.31 to 0 */ + }" + + # I2C3 for H1 + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 184, /* 0 to 1.26v (1.8 * .7) */ + .fall_time_ns = 42, /* 1.26v to 0 */ + .early_init = true, + }" + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 8.1 on # Internal GPP Bridge 0 to Bus A + device pci 0.3 on end # USB 3.1 + end + end # domain + + device mmio 0xfedc4000 on # APU_I2C2_BASE + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "reset_delay_ms" = "20" + register "has_power_resource" = "1" + device i2c 39 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "reset_delay_ms" = "20" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""SYTS7817"" + register "generic.desc" = ""Synaptics Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "45" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 20 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "120" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "wake" = "7" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "generic.wake" = "7" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/dalboz/romstage.c b/src/mainboard/google/zork/variants/dalboz/romstage.c new file mode 100644 index 0000000000..42e36c4525 --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/romstage.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include + +void variant_romstage_entry(void) +{ + uint32_t board_version; + + if (google_chromeec_cbi_get_board_version(&board_version)) + board_version = 1; + + if (board_version < 2) { + /* SET PCIE_RST0_L HIGH */ + gpio_set(WIFI_PCIE_RESET_L, 1); + } else { + /* SET PCIE_RST1_L HIGH */ + gpio_set(PCIE_RST1_L, 1); + } +} diff --git a/src/mainboard/google/zork/variants/dalboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/dalboz/spd/Makefile.inc new file mode 100644 index 0000000000..7baf8be205 --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/spd/Makefile.inc @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Ordered List of APCB entries, up to 16. +# Entries should match this pattern {NAME}_x{1,2} +# There should be a matching SPD hex file in SPD_SOURCES_DIR +# matching the pattern {NAME}.spd.hex +# The _x{1,2} suffix denotes single or dual channel +# Alternatively, generated APCBs stored at +# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included. +APCB_SOURCES = hynix-HMA851S6CJR6N-VK_x1 # 0b0000 +APCB_SOURCES += hynix-H5ANAG6NCMR-VKC_x1 # 0b0001 +APCB_SOURCES += samsung-K4A8G165WC-BCTD_x1 # 0b0010 +APCB_SOURCES += samsung-K4AAG165WB-MCTD_x1 # 0b0011 +APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0100 +APCB_SOURCES += empty # 0b0101 +APCB_SOURCES += empty # 0b0110 +APCB_SOURCES += empty # 0b0111 +APCB_SOURCES += empty # 0b1000 +APCB_SOURCES += empty # 0b1001 +APCB_SOURCES += empty # 0b1010 +APCB_SOURCES += empty # 0b1011 +APCB_SOURCES += empty # 0b1100 +APCB_SOURCES += empty # 0b1101 +APCB_SOURCES += empty # 0b1110 +APCB_SOURCES += empty # 0b1111 diff --git a/src/mainboard/google/zork/variants/dalboz/variant.c b/src/mainboard/google/zork/variants/dalboz/variant.c new file mode 100644 index 0000000000..aae8f03058 --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/variant.c @@ -0,0 +1,201 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define EC_PNP_ID 0x0c09 + +/* Look for an EC device of type PNP with id 0x0c09 */ +static bool match_ec_dev(DEVTREE_CONST struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_PNP) + return false; + + if (dev->path.pnp.port != EC_PNP_ID) + return false; + + return true; +} + +extern struct chip_operations drivers_i2c_generic_ops; + +/* Look for an I2C device with HID "10EC5682" */ +static bool match_audio_dev(DEVTREE_CONST struct device *dev) +{ + struct drivers_i2c_generic_config *cfg; + + if (dev->chip_ops != &drivers_i2c_generic_ops) + return false; + + cfg = dev->chip_info; + + return !strcmp(cfg->hid, "10EC5682"); +} + +extern struct chip_operations ec_google_chromeec_i2c_tunnel_ops; + +/* Look for Cros EC tunnel device which has audio device under it. */ +static bool match_audio_tunnel(DEVTREE_CONST struct device *dev) +{ + const struct device *audio_dev; + + if (dev->chip_ops != &ec_google_chromeec_i2c_tunnel_ops) + return false; + + audio_dev = dev_find_matching_device_on_bus(dev->link_list, match_audio_dev); + + if (!audio_dev) + return false; + + return true; +} + +/* + * This is to allow support for audio on older board versions (< 2). [b/153458561]. This + * should be removed once these boards are phased out. + */ +static void update_audio_configuration(void) +{ + uint32_t board_version; + const struct device *lpc_controller; + const struct device *ec_dev; + const struct device *i2c_tunnel_dev; + struct ec_google_chromeec_i2c_tunnel_config *cfg; + + /* If CBI board version cannot be read, assume this is an older revision of hardware. */ + if (google_chromeec_cbi_get_board_version(&board_version) != 0) + board_version = 1; + + if (board_version >= 2) + return; + + lpc_controller = SOC_LPC_DEV; + if (lpc_controller == NULL) { + printk(BIOS_ERR, "%s: LPC controller device not found!\n", __func__); + return; + } + + ec_dev = dev_find_matching_device_on_bus(lpc_controller->link_list, match_ec_dev); + + if (ec_dev == NULL) { + printk(BIOS_ERR, "%s: EC device not found!\n", __func__); + return; + } + + i2c_tunnel_dev = dev_find_matching_device_on_bus(ec_dev->link_list, match_audio_tunnel); + + if (i2c_tunnel_dev == NULL) { + printk(BIOS_ERR, "%s: I2C tunnel device not found!\n", __func__); + return; + } + + cfg = i2c_tunnel_dev->chip_info; + if (cfg == NULL) { + printk(BIOS_ERR, "%s: I2C tunnel device config not found!\n", __func__); + return; + } + + cfg->remote_bus = 5; +} + +static int sku_has_emmc(void) +{ + uint32_t board_sku = sku_id(); + + /* Factory flow requires all OS boot media to be enabled. */ + if (boot_is_factory_unprovisioned()) + return 1; + + /* FIXME: This needs to be fw_config controlled. */ + /* Enable emmc0 for unknown skus. Only sku3/0xC really has it. */ + if (board_sku == 0x5A80000C || board_sku == 0x5A800003 || board_sku == CROS_SKU_UNKNOWN) + return 1; + + return 0; +} + +void variant_devtree_update(void) +{ + struct soc_amd_picasso_config *cfg; + + cfg = config_of_soc(); + + if (sku_has_emmc()) { + if (sku_id() == 0x5A800003) + /* rev0 boards have issues with HS400 */ + cfg->sd_emmc_config = SD_EMMC_EMMC_HS200; + } else { + cfg->sd_emmc_config = SD_EMMC_DISABLE; + } + + update_audio_configuration(); +} + +/* FIXME: Comments seem to suggest these are not entirely correct. */ +static const picasso_fsp_ddi_descriptor non_hdmi_ddi_descriptors[] = { + { + // DDI0, DP0, eDP + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { + // DDI1, DP1, DB OPT2 USB-C1 / DB OPT3 MST hub + .connector_type = DP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { + // DP2 pins not connected on Dali + // DDI2, DP3, USB-C0 + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +static const picasso_fsp_ddi_descriptor hdmi_ddi_descriptors[] = { + { // DDI0, DP0, eDP + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { // DDI1, DP1, DB OPT2 USB-C1 / DB OPT3 MST hub + .connector_type = HDMI, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + // DP2 pins not connected on Dali + { // DDI2, DP3, USB-C0 + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +void variant_get_pcie_ddi_descriptors(const picasso_fsp_pcie_descriptor **pcie_descs, + size_t *pcie_num, + const picasso_fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num) +{ + uint32_t board_sku = sku_id(); + + *pcie_descs = baseboard_get_pcie_descriptors(pcie_num); + + /* SKU 1, A, and D DB have HDMI, as well as unknown */ + /* FIXME: this needs to be fw_config controlled. */ + if ((board_sku == 0x5A80000A) || (board_sku == 0x5A80000D) || (board_sku == 0x5A800001) + || (board_sku == CROS_SKU_UNKNOWN)) { + *ddi_descs = &hdmi_ddi_descriptors[0]; + *ddi_num = ARRAY_SIZE(hdmi_ddi_descriptors); + } else { + *ddi_descs = &non_hdmi_ddi_descriptors[0]; + *ddi_num = ARRAY_SIZE(non_hdmi_ddi_descriptors); + } +} diff --git a/src/mainboard/google/zork/variants/ezkinil/Makefile.inc b/src/mainboard/google/zork/variants/ezkinil/Makefile.inc new file mode 100644 index 0000000000..51d19fe9ba --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/Makefile.inc @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ./spd + +ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/zork/variants/ezkinil/gpio.c b/src/mainboard/google/zork/variants/ezkinil/gpio.c new file mode 100644 index 0000000000..1b1ed54447 --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/gpio.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +static const struct soc_amd_gpio ezkinil_v1_gpio_set_stage_ram[] = { + /* USB_OC4_L - USB_A1 */ + PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), + /* USB_OC2_L - USB A0 */ + PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), +}; +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + uint32_t board_version; + + /* + * If board version cannot be read, assume that this is an older revision of the board + * and so apply overrides. If board version is provided by the EC, then apply overrides + * if version < 2. + */ + if (google_chromeec_cbi_get_board_version(&board_version)) + board_version = 1; + + if (board_version <= 1) { + *size = ARRAY_SIZE(ezkinil_v1_gpio_set_stage_ram); + return ezkinil_v1_gpio_set_stage_ram; + } + + *size = 0; + return NULL; +} diff --git a/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/audio.asl new file mode 100644 index 0000000000..900e36f277 --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/audio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/mainboard.asl b/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..a1161edb5f --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/mainboard.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/sleep.asl b/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/sleep.asl new file mode 100644 index 0000000000..8177a9df2a --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/sleep.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/thermal.asl b/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/thermal.asl new file mode 100644 index 0000000000..7a793d8102 --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/thermal.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/ezkinil/include/variant/ec.h b/src/mainboard/google/zork/variants/ezkinil/include/variant/ec.h new file mode 100644 index 0000000000..9e61a440cf --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/include/variant/ec.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/ezkinil/include/variant/gpio.h b/src/mainboard/google/zork/variants/ezkinil/include/variant/gpio.h new file mode 100644 index 0000000000..dfaeec3ae1 --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/ezkinil/include/variant/thermal.h b/src/mainboard/google/zork/variants/ezkinil/include/variant/thermal.h new file mode 100644 index 0000000000..2af647973d --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/include/variant/thermal.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb new file mode 100644 index 0000000000..c208dae9ca --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/picasso + + # Start : OPN Performance Configuration + # See devhub #55593 Chapter 3.2 for documentation + # For the below fields, 0 indicates use SOC default + + # System config index + register "system_config" = "2" + + # Set STAPM confiuration. All of these fields must be set >0 to take affect + register "slow_ppt_limit" = "20000" #mw + register "fast_ppt_limit" = "24000" #mw + register "slow_ppt_time_constant" = "5" #second + register "stapm_time_constant" = "200" #second + register "sustained_power_limit" = "12000" #mw + + register "telemetry_vddcr_vdd_slope" = "62413" #mA + register "telemetry_vddcr_vdd_offset" = "0" + register "telemetry_vddcr_soc_slope" = "28977" #mA + register "telemetry_vddcr_soc_offset" = "0" + + # End : OPN Performance Configuration + + # Enable I2C2 for trackpad, touchscreen, pen at 400kHz + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 3, + .fall_time_ns = 2, + }" + + # Enable I2C3 for H1 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 16, + .fall_time_ns = 8, + .early_init = true, + }" + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 1.6 off end # GPP Bridge 5 + device pci 1.7 on end # GPP Bridge 6 - NVME + device pci 8.1 on # Internal GPP Bridge 0 to Bus A + device pci 0.3 on end # USB 3.1 + device pci 0.4 on end # USB 3.1 + end + device pci 14.6 off end # Non-Functional SDHCI + end # domain + + device mmio 0xfedc4000 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "wake" = "7" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "generic.wake" = "7" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "reset_delay_ms" = "20" + register "has_power_resource" = "1" + device i2c 39 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9004"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.probed" = "1" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc b/src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc new file mode 100644 index 0000000000..cd912726c4 --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Ordered List of APCB entries, up to 16. +# Entries should match this pattern {NAME}_x{1,2} +# There should be a matching SPD hex file in SPD_SOURCES_DIR +# matching the pattern {NAME}.spd.hex +# The _x{1,2} suffix denotes single or dual channel +# Alternatively, generated APCBs stored at +# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included. +APCB_SOURCES = hynix-H5AN8G6NCJR-VKC_x2 # 0b0000 +APCB_SOURCES += hynix-HMAA1GS6CMR6N-VK_x2 # 0b0001 +APCB_SOURCES += micron-MT40A512M16TB-062E-J_x2 # 0b0010 +APCB_SOURCES += micron-MT40A1G16KNR-075-E_x2 # 0b0011 +APCB_SOURCES += samsung-K4A8G165WC-BCTD_x2 # 0b0100 +APCB_SOURCES += empty # 0b0101 +APCB_SOURCES += empty # 0b0110 +APCB_SOURCES += empty # 0b0111 +APCB_SOURCES += empty # 0b1000 +APCB_SOURCES += empty # 0b1001 +APCB_SOURCES += empty # 0b1010 +APCB_SOURCES += empty # 0b1011 +APCB_SOURCES += empty # 0b1100 +APCB_SOURCES += empty # 0b1101 +APCB_SOURCES += empty # 0b1110 +APCB_SOURCES += empty # 0b1111 diff --git a/src/mainboard/google/zork/variants/ezkinil/variant.c b/src/mainboard/google/zork/variants/ezkinil/variant.c new file mode 100644 index 0000000000..d7cf5a8803 --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/variant.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +static int sku_has_emmc(void) +{ + uint32_t board_sku = sku_id(); + + /* Factory flow requires all OS boot media to be enabled. */ + if (boot_is_factory_unprovisioned()) + return 1; + + if ((board_sku == 0x5A020000) || + (board_sku == 0x5A020001) || (board_sku == 0x5A020002) || + (board_sku == 0x5A020005) || (board_sku == 0x5A020006) || + (board_sku == 0x5A020009) || (board_sku == 0x5A02000A) || + (board_sku == 0x5A02000D) || (board_sku == 0x5A02000E)) + return 1; + + return 0; +} + +void variant_devtree_update(void) +{ + struct soc_amd_picasso_config *cfg; + + cfg = config_of_soc(); + + if (!sku_has_emmc()) + cfg->sd_emmc_config = SD_EMMC_DISABLE; +} diff --git a/src/mainboard/google/zork/variants/morphius/Makefile.inc b/src/mainboard/google/zork/variants/morphius/Makefile.inc new file mode 100644 index 0000000000..b1212bcbdd --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ./spd + +romstage-y += ./romstage.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/zork/variants/morphius/gpio.c b/src/mainboard/google/zork/variants/morphius/gpio.c new file mode 100644 index 0000000000..ff8fa202fc --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/gpio.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +static const struct soc_amd_gpio morphius_v1_gpio_set_stage_ram[] = { + /* USB_OC4_L - USB_A1 */ + PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), + /* USB_OC2_L - USB A0 */ + PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), + /* DMIC_AD_EN */ + PAD_GPO(GPIO_84, HIGH), +}; + +static const struct soc_amd_gpio morphius_v2_gpio_set_stage_ram[] = { + /* USB_OC4_L - USB_A1 */ + PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), + /* USB_OC2_L - USB A0 */ + PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), +}; + +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + uint32_t board_version; + + /* + * If board version cannot be read, assume that this is an older revision of the board + * and so apply overrides. If board version is provided by the EC, then apply overrides + * if version < 2. + */ + if (google_chromeec_cbi_get_board_version(&board_version)) + board_version = 1; + + if (board_version <= 1) { + *size = ARRAY_SIZE(morphius_v1_gpio_set_stage_ram); + return morphius_v1_gpio_set_stage_ram; + } else if (board_version <= 2) { + *size = ARRAY_SIZE(morphius_v2_gpio_set_stage_ram); + return morphius_v2_gpio_set_stage_ram; + } + + *size = 0; + return NULL; +} diff --git a/src/mainboard/google/zork/variants/morphius/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/morphius/include/variant/acpi/audio.asl new file mode 100644 index 0000000000..900e36f277 --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/include/variant/acpi/audio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/morphius/include/variant/acpi/mainboard.asl b/src/mainboard/google/zork/variants/morphius/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..a1161edb5f --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/include/variant/acpi/mainboard.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/morphius/include/variant/acpi/sleep.asl b/src/mainboard/google/zork/variants/morphius/include/variant/acpi/sleep.asl new file mode 100644 index 0000000000..8177a9df2a --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/include/variant/acpi/sleep.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/morphius/include/variant/acpi/thermal.asl b/src/mainboard/google/zork/variants/morphius/include/variant/acpi/thermal.asl new file mode 100644 index 0000000000..7a793d8102 --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/include/variant/acpi/thermal.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/morphius/include/variant/ec.h b/src/mainboard/google/zork/variants/morphius/include/variant/ec.h new file mode 100644 index 0000000000..e177507e22 --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/include/variant/ec.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +/* Enable PS/2 Mouse */ +#define SIO_EC_ENABLE_PS2M diff --git a/src/mainboard/google/zork/variants/morphius/include/variant/gpio.h b/src/mainboard/google/zork/variants/morphius/include/variant/gpio.h new file mode 100644 index 0000000000..dfaeec3ae1 --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/morphius/include/variant/thermal.h b/src/mainboard/google/zork/variants/morphius/include/variant/thermal.h new file mode 100644 index 0000000000..2af647973d --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/include/variant/thermal.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb new file mode 100644 index 0000000000..b4a801566e --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/picasso + + # Start : OPN Performance Configuration + # See devhub #55593 Chapter 3.2 for documentation + # For the below fields, 0 indicates use SOC default + + # System config index + register "system_config" = "2" + + # Set STAPM confiuration. All of these fields must be set >0 to take affect + register "slow_ppt_limit" = "20000" #mw + register "fast_ppt_limit" = "24000" #mw + register "slow_ppt_time_constant" = "5" #second + register "stapm_time_constant" = "200" #second + register "sustained_power_limit" = "12000" #mw + + register "telemetry_vddcr_vdd_slope" = "78289" #mA + register "telemetry_vddcr_vdd_offset" = "0" + register "telemetry_vddcr_soc_slope" = "24519" #mA + register "telemetry_vddcr_soc_offset" = "0" + + # End : OPN Performance Configuration + + # Enable I2C2 for trackpad, touchscreen, pen at 400kHz + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 18, /* 0 to 2.31 (3.3 * .7) */ + .fall_time_ns = 57, /* 2.31 to 0 */ + }" + + # Enable I2C3 for H1 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 184, /* 0 to 1.26v (1.8 * .7) */ + .fall_time_ns = 42, /* 1.26v to 0 */ + .early_init = true, + }" + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 1.6 off end # GPP Bridge 5 + device pci 1.7 on end # GPP Bridge 6 - NVME + device pci 8.1 on # Internal GPP Bridge 0 to Bus A + device pci 0.3 on end # USB 3.1 + device pci 0.4 on end # USB 3.1 + end + device pci 14.6 off end # Non-Functional SDHCI + end # domain + + device mmio 0xfedc4000 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "wake" = "7" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "generic.wake" = "7" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7375L"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "120" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + end +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/morphius/romstage.c b/src/mainboard/google/zork/variants/morphius/romstage.c new file mode 100644 index 0000000000..876b836adc --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/romstage.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +#include +#include +#include +#include + +void variant_romstage_entry(void) +{ + //SET WIFI_PCIE_RESET_L HIGH + gpio_set(WIFI_PCIE_RESET_L, 1); + + /* Power the wifi card */ + /* wait 10ms to discharge EN_PWR_WIFI to 0V */ + mdelay(10); + gpio_set(EN_PWR_WIFI, 1); + + /* SET WIFI_PCIE_RESET_L LOW */ + gpio_set(WIFI_PCIE_RESET_L, 0); + + /* Qualcomm Atheros NFA344A needs at least 10ms delay */ + mdelay(10); + + /* SET WIFI_PCIE_RESET_L HIGH */ + gpio_set(WIFI_PCIE_RESET_L, 1); +} + +static const struct soc_amd_gpio morphius_gpio_set_wifi[] = { + /* EN_PWR_WIFI - Power off. Pull high in romstage.c */ + PAD_GPO(GPIO_29, LOW), +}; + +const struct soc_amd_gpio *variant_wifi_romstage_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(morphius_gpio_set_wifi); + return morphius_gpio_set_wifi; +} diff --git a/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc b/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc new file mode 100644 index 0000000000..4f0929f422 --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Ordered List of APCB entries, up to 16. +# Entries should match this pattern {NAME}_x{1,2} +# There should be a matching SPD hex file in SPD_SOURCES_DIR +# matching the pattern {NAME}.spd.hex +# The _x{1,2} suffix denotes single or dual channel +# Alternatively, generated APCBs stored at +# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included. +APCB_SOURCES = samsung-K4AAG165WA-BCWE_x2 # 0b0000 +APCB_SOURCES += empty # 0b0001 +# b/149596178: We can't use dual channel channel until the PSP supports missing +# channels. +APCB_SOURCES += micron-MT40A512M16TB-062E-J_x1 # 0b0010 +APCB_SOURCES += micron-MT40A1G16KD-062E-E_x2 # 0b0011 +APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0100 +APCB_SOURCES += hynix-H5AN8G6NDJR-XNC_x1 # 0b0101 +APCB_SOURCES += micron-MT40A512M16TB-062E-J_x1 # 0b0110 +APCB_SOURCES += samsung-K4AAG165WA-BCWE_x2 # 0b0111 +APCB_SOURCES += hynix-H5ANAG6NCMR-XNC_x2 # 0b1000 +APCB_SOURCES += empty # 0b1001 +APCB_SOURCES += empty # 0b1010 +APCB_SOURCES += empty # 0b1011 +APCB_SOURCES += empty # 0b1100 +APCB_SOURCES += empty # 0b1101 +APCB_SOURCES += empty # 0b1110 diff --git a/src/mainboard/google/zork/variants/trembyle/Makefile.inc b/src/mainboard/google/zork/variants/trembyle/Makefile.inc new file mode 100644 index 0000000000..0b6bc4b349 --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ../baseboard/spd + +ramstage-y += gpio.c diff --git a/src/mainboard/google/zork/variants/trembyle/gpio.c b/src/mainboard/google/zork/variants/trembyle/gpio.c new file mode 100644 index 0000000000..7973858d5e --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/gpio.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +static const struct soc_amd_gpio trembyle_v1_v2_gpio_set_stage_ram[] = { + /* USB_OC4_L - USB_A1 */ + PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), + /* USB_OC2_L - USB A0 */ + PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), + /* DMIC_AD_EN */ + PAD_GPO(GPIO_84, HIGH), +}; + +static const struct soc_amd_gpio trembyle_v3_gpio_set_stage_ram[] = { + /* USB_OC4_L - USB_A1 */ + PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), + /* USB_OC2_L - USB A0 */ + PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), +}; + +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + uint32_t board_version; + + /* + * If board version cannot be read, assume that this is an older revision of the board + * and so apply overrides. If board version is provided by the EC, then apply overrides + * if version < 2. + */ + if (google_chromeec_cbi_get_board_version(&board_version)) + board_version = 1; + + if (board_version <= 2) { + *size = ARRAY_SIZE(trembyle_v1_v2_gpio_set_stage_ram); + return trembyle_v1_v2_gpio_set_stage_ram; + } else if (board_version <= 3) { + *size = ARRAY_SIZE(trembyle_v3_gpio_set_stage_ram); + return trembyle_v3_gpio_set_stage_ram; + } + + *size = 0; + return NULL; +} diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/audio.asl new file mode 100644 index 0000000000..900e36f277 --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/audio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/mainboard.asl b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..a1161edb5f --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/mainboard.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/sleep.asl b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/sleep.asl new file mode 100644 index 0000000000..8177a9df2a --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/sleep.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/thermal.asl b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/thermal.asl new file mode 100644 index 0000000000..7a793d8102 --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/thermal.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/ec.h b/src/mainboard/google/zork/variants/trembyle/include/variant/ec.h new file mode 100644 index 0000000000..9e61a440cf --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/include/variant/ec.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/gpio.h b/src/mainboard/google/zork/variants/trembyle/include/variant/gpio.h new file mode 100644 index 0000000000..dfaeec3ae1 --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/thermal.h b/src/mainboard/google/zork/variants/trembyle/include/variant/thermal.h new file mode 100644 index 0000000000..2af647973d --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/include/variant/thermal.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/trembyle/overridetree.cb b/src/mainboard/google/zork/variants/trembyle/overridetree.cb new file mode 100644 index 0000000000..46fada9f5f --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/overridetree.cb @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/picasso + + # Start : OPN Performance Configuration + # See devhub #55593 Chapter 3.2 for documentation + # For the below fields, 0 indicates use SOC default + + # System config index + register "system_config" = "2" + + # Set STAPM confiuration. All of these fields must be set >0 to take affect + register "slow_ppt_limit" = "25000" #mw + register "fast_ppt_limit" = "30000" #mw + register "slow_ppt_time_constant" = "5" #second + register "stapm_time_constant" = "200" #second + register "sustained_power_limit" = "15000" #mw + + register "telemetry_vddcr_vdd_slope" = "71222" #mA + register "telemetry_vddcr_vdd_offset" = "0" + register "telemetry_vddcr_soc_slope" = "28977" #mA + register "telemetry_vddcr_soc_offset" = "0" + + # End : OPN Performance Configuration + + # Enable I2C2 for trackpad, touchscreen, pen at 400kHz + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 21, /* 0 to 2.31 (3.3 * .7) */ + .fall_time_ns = 76, /* 2.31 to 0 */ + }" + + # Enable I2C3 for H1 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 125, /* 0 to 1.26v (1.8 * .7) */ + .fall_time_ns = 37, /* 1.26v to 0 */ + .early_init = true, + }" + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 1.6 off end # GPP Bridge 5 + device pci 1.7 on end # GPP Bridge 6 - NVME + device pci 8.1 on # Internal GPP Bridge 0 to Bus A + device pci 0.3 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""User-Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""AR Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.4 on end + end + end + end + end # USB 3.1 + device pci 0.4 on end # USB 3.1 + end + device pci 14.6 off end # Non-Functional SDHCI + end # domain + + device mmio 0xfedc4000 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "wake" = "22" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "generic.wake" = "22" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "reset_delay_ms" = "20" + register "has_power_resource" = "1" + device i2c 39 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "reset_delay_ms" = "20" + register "has_power_resource" = "1" + device i2c 10 on end + end + end + +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/verstage.c b/src/mainboard/google/zork/verstage.c new file mode 100644 index 0000000000..7bfc10782a --- /dev/null +++ b/src/mainboard/google/zork/verstage.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +static void setup_gpio(void) +{ + const struct soc_amd_gpio *gpios; + size_t num_gpios; + + printk(BIOS_DEBUG, "Setting GPIOs\n"); + gpios = variant_romstage_gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); + printk(BIOS_DEBUG, "GPIOs setup\n"); +} + +static void setup_i2c(void) +{ + printk(BIOS_DEBUG, "Setting up i2c\n"); + i2c_soc_early_init(); + printk(BIOS_DEBUG, "i2c setup\n"); +} + +void verstage_mainboard_early_init(void) +{ + setup_gpio(); +} + +void verstage_mainboard_init(void) +{ + setup_i2c(); +} From e3f564988b7d893bfe681f3f93bb2a89d36f9b01 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Fri, 15 May 2020 11:04:39 -0600 Subject: [PATCH 328/405] mb/google/dedede: Enable Intel Speed Shift Technology Enable Intel Speed Shift Technology (ISST) by default. Disable ISST in waddledee and waddledoo variants on early phases. BUG=b:151281860 TEST=Build and boot the mainboard. Ensure that cpufreq driver to configure P-states is enabled in kernel on boards where board version is provisioned. Change-Id: Id65d7981501c2f282e564bfc140f8d499d5713e8 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/39477 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Aamir Bohra Reviewed-by: Sumeet R Pawnikar --- src/mainboard/google/dedede/mainboard.c | 17 +++++++++++++++++ .../dedede/variants/baseboard/devicetree.cb | 3 +++ .../baseboard/include/baseboard/variants.h | 3 +++ .../dedede/variants/waddledee/Makefile.inc | 2 ++ .../google/dedede/variants/waddledee/variant.c | 16 ++++++++++++++++ .../dedede/variants/waddledoo/Makefile.inc | 2 ++ .../google/dedede/variants/waddledoo/variant.c | 16 ++++++++++++++++ 7 files changed, 59 insertions(+) create mode 100644 src/mainboard/google/dedede/variants/waddledee/variant.c create mode 100644 src/mainboard/google/dedede/variants/waddledoo/variant.c diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index c503a86a6e..fe89527e5a 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -1,11 +1,25 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include #include #include #include #include +__weak void variant_isst_override(void) +{ + /* + * Implement the override only if the board uses very early/initial revisions of + * Silicon. Otherwise nothing to override. + */ +} + +static void mainboard_config_isst(void *unused) +{ + variant_isst_override(); +} + static void mainboard_init(void *chip_info) { const struct pad_config *pads; @@ -37,3 +51,6 @@ struct chip_operations mainboard_ops = { .init = mainboard_init, .enable_dev = mainboard_enable, }; + +/* Configure ISST before CPU initialization */ +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, mainboard_config_isst, NULL); diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index c891e6e376..1b42dfb81a 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -133,6 +133,9 @@ chip soc/intel/jasperlake register "DdiPortBDdc" = "1" register "DdiPortCDdc" = "1" + # Enable Speed Shift Technology support + register "speed_shift_enable" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index 3fdc7824eb..5d8355b2fe 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -39,4 +39,7 @@ int variant_memory_sku(void); */ bool variant_mem_is_half_populated(void); +/* Variant Intel Speed Shift Technology override */ +void variant_isst_override(void); + #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc index dfb97bae95..aaa65e2a2a 100644 --- a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc @@ -4,3 +4,5 @@ SPD_SOURCES = SPD_LPDDR4X_200b_8Gb_4267_DDP_1x16 #0b0000 SPD_SOURCES += empty #0b0001 romstage-y += memory.c + +ramstage-y += variant.c diff --git a/src/mainboard/google/dedede/variants/waddledee/variant.c b/src/mainboard/google/dedede/variants/waddledee/variant.c new file mode 100644 index 0000000000..ac3cf581d9 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/variant.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +void variant_isst_override(void) +{ + config_t *cfg = config_of_soc(); + uint32_t board_ver; + + /* Override/Disable ISST in boards where board version is not populated. */ + if (google_chromeec_get_board_version(&board_ver)) + cfg->speed_shift_enable = 0; +} diff --git a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc index 922c314ee3..11bbbd60cc 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc @@ -4,3 +4,5 @@ SPD_SOURCES = empty #0b0000 SPD_SOURCES += SPD_LPDDR4X_200b_8Gb_4267_DDP_1x16 #0b0001 romstage-y += memory.c + +ramstage-y += variant.c diff --git a/src/mainboard/google/dedede/variants/waddledoo/variant.c b/src/mainboard/google/dedede/variants/waddledoo/variant.c new file mode 100644 index 0000000000..ac3cf581d9 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledoo/variant.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +void variant_isst_override(void) +{ + config_t *cfg = config_of_soc(); + uint32_t board_ver; + + /* Override/Disable ISST in boards where board version is not populated. */ + if (google_chromeec_get_board_version(&board_ver)) + cfg->speed_shift_enable = 0; +} From 0018d0f0de6517c0182137eff97ad96335bd69a8 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Tue, 19 May 2020 20:11:13 +0530 Subject: [PATCH 329/405] soc/intel/jasperlake: Use coreboot lock down config Allow lockdown configuration from using CHIPSET_LOCKDOWN_COREBOOT config. TEST=Build and boot waddledoo board Change-Id: I3abaa737580ef45b98cabfa23edd84162037dd70 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/41534 Reviewed-by: Karthik Ramasubramanian Reviewed-by: Maulik V Vaghela Tested-by: build bot (Jenkins) --- src/soc/intel/jasperlake/fsp_params.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 45162f91f2..eafc374584 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -105,8 +106,18 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; } - /* Unlock upper 8 bytes of RTC RAM */ - params->RtcMemoryLock = 0; + /* Chipset Lockdown */ + if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { + params->PchLockDownGlobalSmi = 0; + params->PchLockDownBiosInterface = 0; + params->PchUnlockGpioPads = 1; + params->RtcMemoryLock = 0; + } else { + params->PchLockDownGlobalSmi = 1; + params->PchLockDownBiosInterface = 1; + params->PchUnlockGpioPads = 0; + params->RtcMemoryLock = 1; + } /* Enable End of Post in PEI phase */ params->EndOfPostMessage = EOP_PEI; From 02a1344921a6cd848fe4f766e64e602632435ea8 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 26 May 2020 18:18:43 +0200 Subject: [PATCH 330/405] docker/coreboot-jenkins-node: Add meson and ninja Our jenkins instance is also used for flashrom, which can be built with meson, a mode that we want to be able to test, so add that. ninja can be used as a backend to both meson and cmake (which coreboot will use to build cmocka for its unit tests) and may provide some additional coverage. Plus it's tiny but fast. Change-Id: If454164852303144eaa72c4071c03ee89e863318 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/41731 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- util/docker/coreboot-jenkins-node/Dockerfile | 1 + 1 file changed, 1 insertion(+) diff --git a/util/docker/coreboot-jenkins-node/Dockerfile b/util/docker/coreboot-jenkins-node/Dockerfile index 73f7f1829d..554ebd2654 100644 --- a/util/docker/coreboot-jenkins-node/Dockerfile +++ b/util/docker/coreboot-jenkins-node/Dockerfile @@ -19,6 +19,7 @@ USER root RUN apt-get -y update && \ apt-get -y install \ + meson ninja-build \ lua5.3 liblua5.3-dev default-jre-headless openssh-server && \ apt-get clean From a121f953937eb718cc579ce2c428937d00a91287 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 26 May 2020 15:48:10 -0600 Subject: [PATCH 331/405] lib/cbfs: refactor code culling compression checks Provide helper functions to determine if a compression algorithm is supported in a given stage. Future patches can use those functions to amend which algorithms to include in the final link. BUG=b:155322763,b:150746858,b:152909132 Change-Id: I898c939cec73d1f300ea38b165f379038877f05e Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/41754 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Arthur Heymans Reviewed-by: Julius Werner Reviewed-by: Angel Pons --- src/lib/cbfs.c | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index a3294de63e..74df3c5b39 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -91,6 +91,27 @@ int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, return ret; } +static inline bool cbfs_lz4_enabled(void) +{ + if ((ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) && !CONFIG(COMPRESS_PRERAM_STAGES)) + return false; + + return true; +} + +static inline bool cbfs_lzma_enabled(void) +{ + /* We assume here romstage and postcar are never compressed. */ + if (ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) + return false; + if (ENV_ROMSTAGE && CONFIG(POSTCAR_STAGE)) + return false; + if ((ENV_ROMSTAGE || ENV_POSTCAR) + && !CONFIG(COMPRESS_RAMSTAGE)) + return false; + return true; +} + size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, size_t in_size, void *buffer, size_t buffer_size, uint32_t compression) { @@ -105,8 +126,7 @@ size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, return in_size; case CBFS_COMPRESS_LZ4: - if ((ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) && - !CONFIG(COMPRESS_PRERAM_STAGES)) + if (!cbfs_lz4_enabled()) return 0; /* Load the compressed image to the end of the available memory @@ -123,13 +143,7 @@ size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, return out_size; case CBFS_COMPRESS_LZMA: - /* We assume here romstage and postcar are never compressed. */ - if (ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) - return 0; - if (ENV_ROMSTAGE && CONFIG(POSTCAR_STAGE)) - return 0; - if ((ENV_ROMSTAGE || ENV_POSTCAR) - && !CONFIG(COMPRESS_RAMSTAGE)) + if (!cbfs_lzma_enabled()) return 0; void *map = rdev_mmap(rdev, offset, in_size); if (map == NULL) From 78e8db1eebaf4e90c0de2b38a0cc8832057766a7 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Fri, 19 Jul 2019 16:31:37 +0200 Subject: [PATCH 332/405] sb/intel/{bd82x6x|ibexpeak}: Clear flush_* in FADT Both fields are ignored if WBINVD is set, which is true for all processors since i486. Change-Id: Ibad56046e2c1b8595dc31e5861b9fd1fd7d2d6f3 Signed-off-by: Patrick Rudolph Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/34453 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/southbridge/intel/bd82x6x/lpc.c | 6 +++--- src/southbridge/intel/ibexpeak/lpc.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 987db360e2..55e2573eff 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -726,12 +726,12 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) } fadt->p_lvl2_lat = c2_latency; fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; + /* flush_* is ignored if ACPI_FADT_WBINVD is set */ + fadt->flush_size = 0; + fadt->flush_stride = 0; /* P_CNT not supported */ fadt->duty_offset = 0; fadt->duty_width = 0; - fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x00; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 0d15b5d8fa..54b2621bca 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -620,12 +620,12 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) } fadt->p_lvl2_lat = c2_latency; fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; + /* flush_* is ignored if ACPI_FADT_WBINVD is set */ + fadt->flush_size = 0; + fadt->flush_stride = 0; /* P_CNT not supported */ fadt->duty_offset = 0; fadt->duty_width = 0; - fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x32; From bf72dcbd2f1b0138a329f0c9adac33c387e8cd9f Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 12 May 2020 16:04:47 +0200 Subject: [PATCH 333/405] soc/intel/common: Improve Type16 SMBIOS tables Use CAPID0_A to provide information closer to reality. * Correctly advertise ECC support, max DIMM count and max capacity * CAPID0_A hasn't changed since SNB, but most EDS mark the bits as reserved even though they are still used by FSP. * Assume the same bits for Tiger Lake as for Ice Lake * Assume the same bits for Skylake as for Coffee Lake * Add CAPID0_A to Icelake headers The lastest complete documentation can be found in Document: 341078-002. Change-Id: I0d8fbb512fccbd99a6cfdacadc496d8266ae4cc7 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/41334 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Christian Walter Reviewed-by: Philipp Deppenwiese --- src/soc/intel/apollolake/systemagent.c | 6 ++++ src/soc/intel/cannonlake/systemagent.c | 14 +++++++++ .../block/include/intelblocks/systemagent.h | 4 +++ .../common/block/systemagent/systemagent.c | 31 ++++++++++++++++--- .../block/systemagent/systemagent_def.h | 5 +++ .../intel/icelake/include/soc/systemagent.h | 1 + src/soc/intel/icelake/systemagent.c | 14 +++++++++ src/soc/intel/skylake/systemagent.c | 14 +++++++++ src/soc/intel/tigerlake/systemagent.c | 14 +++++++++ 9 files changed, 99 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/apollolake/systemagent.c b/src/soc/intel/apollolake/systemagent.c index 258376a999..e05a470d50 100644 --- a/src/soc/intel/apollolake/systemagent.c +++ b/src/soc/intel/apollolake/systemagent.c @@ -88,3 +88,9 @@ int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base, return 0; } + +uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) +{ + /* Max 4GiB per rank, 2 ranks per channel. Intel Document: 332092-002 */ + return 8192; +} diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c index c225651649..d57b3e9219 100644 --- a/src/soc/intel/cannonlake/systemagent.c +++ b/src/soc/intel/cannonlake/systemagent.c @@ -73,3 +73,17 @@ void soc_systemagent_init(struct device *dev) soc_config = &config->power_limits_config; set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); } + +uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) +{ + switch (capid0_a_ddrsz) { + case 1: + return 8192; + case 2: + return 4096; + case 3: + return 2048; + default: + return 32768; + } +} diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index 30c892ba13..ae7211697e 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -90,4 +90,8 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *resource_cnt); /* SoC specific APIs to get UNCORE PRMRR base and mask values * returns 0, if able to get base and mask values; otherwise returns -1 */ int soc_get_uncore_prmmr_base_and_mask(uint64_t *base, uint64_t *mask); + +/* Returns the maximum supported capacity of a channel as encoded by DDRSZ in MiB */ +uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz); + #endif /* SOC_INTEL_COMMON_BLOCK_SA_H */ diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 269236ba32..d25e1aa46c 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -41,6 +41,11 @@ __weak unsigned long sa_write_acpi_tables(const struct device *dev, return current; } +__weak uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) +{ + return 32768; /* 32 GiB per channel */ +} + /* * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. @@ -258,11 +263,27 @@ static void systemagent_read_resources(struct device *dev) } #if CONFIG(GENERATE_SMBIOS_TABLES) +static bool sa_supports_ecc(const uint32_t capida) +{ + return !(capida & CAPID_ECCDIS); +} + +static size_t sa_slots_per_channel(const uint32_t capida) +{ + return !(capida & CAPID_DDPCD) + 1; +} + +static size_t sa_number_of_channels(const uint32_t capida) +{ + return !(capida & CAPID_PDCD) + 1; +} + static int sa_smbios_write_type_16(struct device *dev, int *handle, unsigned long *current) { struct smbios_type16 *t = (struct smbios_type16 *)*current; int len = sizeof(struct smbios_type16); + const uint32_t capida = pci_read_config32(dev, CAPID0_A); struct memory_info *meminfo; meminfo = cbmem_find(CBMEM_ID_MEMINFO); @@ -275,12 +296,14 @@ static int sa_smbios_write_type_16(struct device *dev, int *handle, t->length = len - 2; t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD; t->use = MEMORY_ARRAY_USE_SYSTEM; - /* TBD, meminfo hob have information about ECC */ - t->memory_error_correction = MEMORY_ARRAY_ECC_NONE; + t->memory_error_correction = sa_supports_ecc(capida) ? MEMORY_ARRAY_ECC_SINGLE_BIT : + MEMORY_ARRAY_ECC_NONE; /* no error information handle available */ t->memory_error_information_handle = 0xFFFE; - t->maximum_capacity = 32 * (GiB / KiB); /* 32GB as default */ - t->number_of_memory_devices = meminfo->dimm_cnt; + t->maximum_capacity = soc_systemagent_max_chan_capacity_mib(CAPID_DDRSZ(capida)) * + sa_number_of_channels(capida) * (MiB / KiB); + t->number_of_memory_devices = sa_slots_per_channel(capida) * + sa_number_of_channels(capida); *current += len; *handle += 1; diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h index a652dfd9a2..a7823c347c 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_def.h +++ b/src/soc/intel/common/block/systemagent/systemagent_def.h @@ -17,6 +17,11 @@ #define DPR_EPM (1 << 2) #define DPR_PRS (1 << 1) #define DPR_SIZE_MASK 0xff0 +/* CAPID0_A */ +#define CAPID_ECCDIS (1 << 25) +#define CAPID_DDPCD (1 << 14) +#define CAPID_PDCD (1 << 12) +#define CAPID_DDRSZ(x) (((x) >> 19) & 0x3) #define PCIEXBAR_LENGTH_64MB 2 #define PCIEXBAR_LENGTH_128MB 1 diff --git a/src/soc/intel/icelake/include/soc/systemagent.h b/src/soc/intel/icelake/include/soc/systemagent.h index 297ee5d56c..90465a248b 100644 --- a/src/soc/intel/icelake/include/soc/systemagent.h +++ b/src/soc/intel/icelake/include/soc/systemagent.h @@ -15,6 +15,7 @@ #define D_LCK (1 << 4) #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define CAPID0_A 0xe4 #define BIOS_RESET_CPL 0x5da8 #define EDRAMBAR 0x5408 diff --git a/src/soc/intel/icelake/systemagent.c b/src/soc/intel/icelake/systemagent.c index ac96d81adf..c9fe0a97eb 100644 --- a/src/soc/intel/icelake/systemagent.c +++ b/src/soc/intel/icelake/systemagent.c @@ -52,3 +52,17 @@ void soc_systemagent_init(struct device *dev) /* Enable BIOS Reset CPL */ enable_bios_reset_cpl(); } + +uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) +{ + switch (capid0_a_ddrsz) { + case 1: + return 8192; + case 2: + return 4096; + case 3: + return 2048; + default: + return 65536; + } +} diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index 8e58bf6669..f28bd257fe 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -87,3 +87,17 @@ int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base, *prmrr_mask = (uint64_t) msr.hi << 32 | msr.lo; return 0; } + +uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) +{ + switch (capid0_a_ddrsz) { + case 1: + return 8192; + case 2: + return 4096; + case 3: + return 2048; + default: + return 32768; + } +} diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index 8c0a42a71a..08d1ef387c 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -67,3 +67,17 @@ void soc_systemagent_init(struct device *dev) soc_config = &config->power_limits_config; set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); } + +uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) +{ + switch (capid0_a_ddrsz) { + case 1: + return 8192; + case 2: + return 4096; + case 3: + return 2048; + default: + return 65536; + } +} From 40bcdba65219b28b3bf76bd97cb2906359554af3 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 20 Mar 2020 12:08:40 +0100 Subject: [PATCH 334/405] cpu/intel/common: Fix typo in comment Change-Id: I9ff49adebc1156d33c648efb8e9854b13c0ef859 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39696 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- src/cpu/intel/common/common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h index e38e068112..57a5fe602c 100644 --- a/src/cpu/intel/common/common.h +++ b/src/cpu/intel/common/common.h @@ -12,7 +12,7 @@ void set_feature_ctrl_lock(void); /* * Init CPPC block with MSRs for Intel Enhanced Speed Step Technology. * Version 2 is suggested--this function's implementation of version 3 - * may have room for improvment. + * may have room for improvement. */ struct cppc_config; void cpu_init_cppc_config(struct cppc_config *config, u32 version); From 45761c5e998316ba37c84fa1d26ba7ccde5ca7d8 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 25 May 2020 18:32:33 -0700 Subject: [PATCH 335/405] mb/google/volteer: Select SX9310 driver in Kconfig There are SX9310 devices present in devicetree.cb but the driver is not enabled so it is not getting used. Change-Id: I625233013a2e14eaf758e56027774fbf5df3bc83 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/41700 Reviewed-by: Furquan Shaikh Reviewed-by: HAOUAS Elyes Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 143a1eeccc..2a7212b064 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -4,6 +4,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID + select DRIVERS_I2C_SX9310 select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_SPI_ACPI select DRIVERS_SOUNDWIRE_ALC5682 From 1fcb238d6262acfccd4f6ef68d100d812c2831b2 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 21 May 2020 23:53:07 -0700 Subject: [PATCH 336/405] mb/google/hatch: Split Kconfigs into BASEBOARD_HATCH and BASEBOARD_PUFF mb/google/hatch supports two different reference platforms - Hatch and Puff. This change adds Kconfigs BOARD_GOOGLE_BASEBOARD_PUFF in addition to BOARD_GOOGLE_BASEBOARD_HATCH to better organize the Kconfig selections and reduce redundancy. In addition to this, a new config BOARD_GOOGLE_HATCH_COMMON is added that selects all the common configs for both baseboards. TEST=Verified using abuild --timeless option that all hatch variants generate the same coreboot.rom image with and without this change. Change-Id: I46f8b2ed924c10228fa55e5168bf4fe6b41ec36c Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41660 Reviewed-by: V Sowmya Reviewed-by: Angel Pons Reviewed-by: Edward O'Callaghan Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/Kconfig | 34 +++++++++--------- src/mainboard/google/hatch/Kconfig.name | 46 ++++++++++--------------- 2 files changed, 36 insertions(+), 44 deletions(-) diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index fc4424bd47..d36c152f04 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -1,5 +1,21 @@ config BOARD_GOOGLE_BASEBOARD_HATCH + def_bool n + select BOARD_GOOGLE_HATCH_COMMON + select RT8168_GET_MAC_FROM_VPD + select RT8168_SET_LED_MODE + select SYSTEM_TYPE_LAPTOP + select VBOOT_LID_SWITCH + +config BOARD_GOOGLE_BASEBOARD_PUFF + def_bool n + select BOARD_GOOGLE_HATCH_COMMON + select RT8168_GET_MAC_FROM_VPD + select RT8168_SET_LED_MODE + select ROMSTAGE_SPD_SMBUS + select SPD_READ_BY_WORD + +config BOARD_GOOGLE_HATCH_COMMON def_bool n select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENERIC_MAX98357A @@ -22,15 +38,8 @@ config BOARD_GOOGLE_BASEBOARD_HATCH select MAINBOARD_HAS_TPM2 select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE select SOC_INTEL_COMETLAKE - select RT8168_GET_MAC_FROM_VPD - select RT8168_SET_LED_MODE -config BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP - select BOARD_GOOGLE_BASEBOARD_HATCH - select SYSTEM_TYPE_LAPTOP - def_bool n - -if BOARD_GOOGLE_BASEBOARD_HATCH +if BOARD_GOOGLE_HATCH_COMMON config CHROMEOS bool @@ -157,11 +166,4 @@ config VBOOT select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_EARLY_EC_SYNC -endif # BOARD_GOOGLE_BASEBOARD_HATCH - -if BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP - -config VBOOT - select VBOOT_LID_SWITCH - -endif # BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP +endif # BOARD_GOOGLE_HATCH_COMMON diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 195a4ea544..7acc11d484 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -2,114 +2,104 @@ comment "Hatch" config BOARD_GOOGLE_AKEMI bool "-> Akemi" - select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP + select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_DRATINI bool "-> Dratini" - select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP + select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_DUFFY_LEGACY bool "-> Duffy Legacy (32MB)" - select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_PUFF select BOARD_ROMSIZE_KB_32768 - select ROMSTAGE_SPD_SMBUS - select SPD_READ_BY_WORD select VBOOT_EC_EFS config BOARD_GOOGLE_DUFFY bool "-> Duffy" - select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_PUFF select BOARD_ROMSIZE_KB_16384 - select ROMSTAGE_SPD_SMBUS - select SPD_READ_BY_WORD select VBOOT_EC_EFS config BOARD_GOOGLE_HATCH bool "-> Hatch" - select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP + select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_32768 config BOARD_GOOGLE_JINLON bool "-> Jinlon" - select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP + select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 select DRIVERS_GFX_GENERIC config BOARD_GOOGLE_KAISA_LEGACY bool "-> Kaisa Legacy (32MB)" - select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_PUFF select BOARD_ROMSIZE_KB_32768 - select ROMSTAGE_SPD_SMBUS - select SPD_READ_BY_WORD select VBOOT_EC_EFS config BOARD_GOOGLE_KAISA bool "-> Kaisa" - select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_PUFF select BOARD_ROMSIZE_KB_16384 - select ROMSTAGE_SPD_SMBUS - select SPD_READ_BY_WORD select VBOOT_EC_EFS config BOARD_GOOGLE_KOHAKU bool "-> Kohaku" - select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP + select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_KINDRED bool "-> Kindred" - select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP + select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 select SOC_INTEL_COMMON_MMC_OVERRIDE config BOARD_GOOGLE_HELIOS bool "-> Helios" - select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP + select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 config BOARD_GOOGLE_MUSHU bool "-> Mushu" - select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP + select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_PALKIA bool "-> Palkia" - select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP + select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 config BOARD_GOOGLE_NIGHTFURY bool "-> Nightfury" - select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP + select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_MAX98390 config BOARD_GOOGLE_PUFF bool "-> Puff" - select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_PUFF select BOARD_ROMSIZE_KB_32768 - select ROMSTAGE_SPD_SMBUS - select SPD_READ_BY_WORD config BOARD_GOOGLE_HELIOS_DISKSWAP bool "-> Helios_Diskswap" - select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP + select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 config BOARD_GOOGLE_STRYKE bool "-> Stryke" - select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP + select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_SUSHI bool "-> Sushi" - select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP + select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 From 8666643d06f1ebec98dba447b884d5834227273d Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 22 May 2020 00:01:27 -0700 Subject: [PATCH 337/405] mb/google/hatch: Drop rt8168 Kconfigs for baseboard hatch This change drops rt8168 ethernet Kconfig options for baseboard hatch since it does not really support an ethernet device. Change-Id: I7c19dbeb2f64b0643b082a9c588f8b14db4dfb8a Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41661 Reviewed-by: Edward O'Callaghan Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index d36c152f04..853f72b6f9 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -2,8 +2,6 @@ config BOARD_GOOGLE_BASEBOARD_HATCH def_bool n select BOARD_GOOGLE_HATCH_COMMON - select RT8168_GET_MAC_FROM_VPD - select RT8168_SET_LED_MODE select SYSTEM_TYPE_LAPTOP select VBOOT_LID_SWITCH From d1a76c58e7c9d29d3b3366cc6e0e00f7958ea07c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 26 May 2020 07:32:38 +0300 Subject: [PATCH 338/405] soc/intel/xeon_sp/cpx: Remove redundant declaration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The declaration is autogenerated inside static.c file from the pathname. Change-Id: I6eda101a69522d6d526da7c174aa3085ca0fb221 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/41709 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/xeon_sp/cpx/chip.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/soc/intel/xeon_sp/cpx/chip.h b/src/soc/intel/xeon_sp/cpx/chip.h index aa0b8d2978..87dd2b30b5 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.h +++ b/src/soc/intel/xeon_sp/cpx/chip.h @@ -17,8 +17,6 @@ struct soc_intel_xeon_sp_cpx_config { uint32_t gen4_dec; }; -extern struct chip_operations soc_intel_xeon_sp_cpx_ops; - typedef struct soc_intel_xeon_sp_cpx_config config_t; #endif From ffd480fac2953b1536edb9dd59b69644001f7325 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 26 May 2020 07:32:38 +0300 Subject: [PATCH 339/405] soc/intel/xeon_sp/skx: Remove invalid declaration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The declaration is autogenerated inside static.c file from the pathname. The declaration here also lacked _skx_ part from the name. Change-Id: I3adce9147e9376f6d73e410fdd4c0ee800178b58 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/41710 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/xeon_sp/skx/chip.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/soc/intel/xeon_sp/skx/chip.h b/src/soc/intel/xeon_sp/skx/chip.h index 63e1ed39be..c7f19ec811 100644 --- a/src/soc/intel/xeon_sp/skx/chip.h +++ b/src/soc/intel/xeon_sp/skx/chip.h @@ -71,8 +71,6 @@ struct soc_intel_xeon_sp_skx_config { uint32_t gen4_dec; }; -extern struct chip_operations soc_intel_xeon_sp_ops; - typedef struct soc_intel_xeon_sp_skx_config config_t; #endif From 3ae17a42c1f5d8cbf20b6bc7a4e24505651f1754 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 26 May 2020 08:27:42 +0300 Subject: [PATCH 340/405] mb/emulation: Remove fake devicetree.cb components MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I31853e3ede786eb9e10704674e42dd56c3a48688 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/41717 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Philipp Hug --- src/mainboard/emulation/qemu-aarch64/devicetree.cb | 5 ++--- src/mainboard/emulation/qemu-aarch64/mainboard.c | 2 ++ src/mainboard/emulation/qemu-armv7/devicetree.cb | 4 +--- src/mainboard/emulation/qemu-riscv/devicetree.cb | 3 --- src/mainboard/emulation/spike-riscv/devicetree.cb | 3 --- 5 files changed, 5 insertions(+), 12 deletions(-) diff --git a/src/mainboard/emulation/qemu-aarch64/devicetree.cb b/src/mainboard/emulation/qemu-aarch64/devicetree.cb index 533e451cbb..d887837a52 100644 --- a/src/mainboard/emulation/qemu-aarch64/devicetree.cb +++ b/src/mainboard/emulation/qemu-aarch64/devicetree.cb @@ -1,6 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-or-later -# This file exists only to avoid a compile error. It needs a devicetree.cb that is not empty. -chip drivers/generic/generic # I2C0 controller - device i2c 6 on end # Fake component for testing +chip mainboard/emulation/qemu-aarch64 + device cpu_cluster 0 on end end diff --git a/src/mainboard/emulation/qemu-aarch64/mainboard.c b/src/mainboard/emulation/qemu-aarch64/mainboard.c index eb5c11dcc4..e6da3a6cac 100644 --- a/src/mainboard/emulation/qemu-aarch64/mainboard.c +++ b/src/mainboard/emulation/qemu-aarch64/mainboard.c @@ -27,3 +27,5 @@ struct chip_operations mainboard_ops = { .name = "qemu_aarch64", .enable_dev = mainboard_enable, }; + +struct chip_operations mainboard_emulation_qemu_aarch64_ops = { }; diff --git a/src/mainboard/emulation/qemu-armv7/devicetree.cb b/src/mainboard/emulation/qemu-armv7/devicetree.cb index 18ec632d22..f9efb48683 100644 --- a/src/mainboard/emulation/qemu-armv7/devicetree.cb +++ b/src/mainboard/emulation/qemu-armv7/devicetree.cb @@ -2,7 +2,5 @@ # TODO fill with Versatile Express board data in QEMU. chip cpu/armltd/cortex-a9 - chip drivers/generic/generic # I2C0 controller - device i2c 6 on end # Fake component for testing - end + device cpu_cluster 0 on end end diff --git a/src/mainboard/emulation/qemu-riscv/devicetree.cb b/src/mainboard/emulation/qemu-riscv/devicetree.cb index 2b0d520b2b..120af99156 100644 --- a/src/mainboard/emulation/qemu-riscv/devicetree.cb +++ b/src/mainboard/emulation/qemu-riscv/devicetree.cb @@ -2,7 +2,4 @@ chip soc/ucb/riscv device cpu_cluster 0 on end - chip drivers/generic/generic # I2C0 controller - device i2c 6 on end # Fake component for testing - end end diff --git a/src/mainboard/emulation/spike-riscv/devicetree.cb b/src/mainboard/emulation/spike-riscv/devicetree.cb index 2b0d520b2b..120af99156 100644 --- a/src/mainboard/emulation/spike-riscv/devicetree.cb +++ b/src/mainboard/emulation/spike-riscv/devicetree.cb @@ -2,7 +2,4 @@ chip soc/ucb/riscv device cpu_cluster 0 on end - chip drivers/generic/generic # I2C0 controller - device i2c 6 on end # Fake component for testing - end end From 333ba2aadd9f2f619d0961ed270f9c83e6e048d6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 26 May 2020 08:01:38 +0300 Subject: [PATCH 341/405] mb/biostar/a68n_5200: Remove spurious SPD eeprom entries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I1996c1b57310c4c0542c9ed47d1638ddd9c55680 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/41713 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/biostar/a68n_5200/devicetree.cb | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/src/mainboard/biostar/a68n_5200/devicetree.cb b/src/mainboard/biostar/a68n_5200/devicetree.cb index a5ae59f136..c036b65259 100644 --- a/src/mainboard/biostar/a68n_5200/devicetree.cb +++ b/src/mainboard/biostar/a68n_5200/devicetree.cb @@ -28,14 +28,7 @@ chip northbridge/amd/agesa/family16kb/root_complex device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM + device pci 14.0 on end # SM device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d chip superio/ite/it8728f From de27499b520fb8bf5ec63da8dd582e7b1ef023c3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 26 May 2020 09:31:41 +0300 Subject: [PATCH 342/405] soc/ucb/riscv: Add chip_operations stub MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ie4f70429c516fff613d372fec7c1c955645f1c6d Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/41715 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Angel Pons Reviewed-by: Philipp Hug --- src/soc/ucb/riscv/Makefile.inc | 2 ++ src/soc/ucb/riscv/chip.c | 7 +++++++ 2 files changed, 9 insertions(+) create mode 100644 src/soc/ucb/riscv/chip.c diff --git a/src/soc/ucb/riscv/Makefile.inc b/src/soc/ucb/riscv/Makefile.inc index 80899d570f..6d2c36a340 100644 --- a/src/soc/ucb/riscv/Makefile.inc +++ b/src/soc/ucb/riscv/Makefile.inc @@ -4,4 +4,6 @@ romstage-y += cbmem.c ramstage-y += cbmem.c +ramstage-y += chip.c + endif diff --git a/src/soc/ucb/riscv/chip.c b/src/soc/ucb/riscv/chip.c new file mode 100644 index 0000000000..187e96d274 --- /dev/null +++ b/src/soc/ucb/riscv/chip.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +struct chip_operations soc_ucb_riscv_ops = { + CHIP_NAME("UCB RISC-V") +}; From bd4e6e38b4448aee815862ce8e4dc213ccd2a8cd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 26 May 2020 09:31:41 +0300 Subject: [PATCH 343/405] soc/sifive/fu540: Add chip_operations stub MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: If06695745bb72f883314e5514c616223b0210a2f Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/41716 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Angel Pons Reviewed-by: Philipp Hug --- src/soc/sifive/fu540/Makefile.inc | 1 + src/soc/sifive/fu540/chip.c | 7 +++++++ 2 files changed, 8 insertions(+) create mode 100644 src/soc/sifive/fu540/chip.c diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc index 734b4a258a..807c390bb3 100644 --- a/src/soc/sifive/fu540/Makefile.inc +++ b/src/soc/sifive/fu540/Makefile.inc @@ -23,6 +23,7 @@ ramstage-y += sdram.c ramstage-y += cbmem.c ramstage-y += otp.c ramstage-y += clock.c +ramstage-y += chip.c CPPFLAGS_common += -Isrc/soc/sifive/fu540/include diff --git a/src/soc/sifive/fu540/chip.c b/src/soc/sifive/fu540/chip.c new file mode 100644 index 0000000000..6eab45c61c --- /dev/null +++ b/src/soc/sifive/fu540/chip.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +struct chip_operations soc_sifive_fu540_ops = { + CHIP_NAME("SIFIVE FU540") +}; From 25ae99fe65374357729fc61a0d8a10b7a7b62710 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 26 May 2020 05:16:06 +0300 Subject: [PATCH 344/405] mb/google/deltaur: Remove devicetree chip drivers/net MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ia56305e9554b666f8eaf590a91be84e5cac4c75c Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/41701 Reviewed-by: EricR Lai Tested-by: build bot (Jenkins) --- .../google/deltaur/variants/baseboard/devicetree.cb | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 8d847f73fc..14516a01bb 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -283,12 +283,7 @@ chip soc/intel/tigerlake device pci 1c.4 on end # PCIe Root Port #5 (LTE) device pci 1c.5 off end # PCIe Root Port #6 (WiFi) device pci 1c.6 on end # PCIe Root Port #7 (Card reader) - device pci 1c.7 on - chip drivers/net - register "wake" = "GPE0_PME_B0" - device pci 00.0 on end - end - end # PCIe Root Port #8 (LAN) + device pci 1c.7 on end # PCIe Root Port #8 (LAN) device pci 1d.0 on end # PCIe Root Port #9 (NVMe) device pci 1d.1 off end # PCIe Root Port #10 (NVMe) device pci 1d.2 off end # PCIe Root Port #11 (NVMe) From c43a09b1186c36f72f6edcac37ce17cefd34f241 Mon Sep 17 00:00:00 2001 From: Amit Caleechurn Date: Sat, 16 May 2020 16:46:59 +0400 Subject: [PATCH 345/405] mb/lenovo/t440p: Include ACPI for battery threshold This fixes ACPI errors below when invoking tlp-stat and allows setting battery thresholds as natacpi is now enabled. thinkpad_acpi: acpi_evalf(BCTG, dd, ...) failed: AE_NOT_FOUND thinkpad_acpi: acpi_evalf(BCTG, dd, ...) failed: AE_NOT_FOUND Test: Fedora 32 [also on Fedora 31 before the upgrade] Kernel 5.6.12-300 Signed-off-by: Amit Caleechurn Change-Id: Ie345cdd05e38a8b7f646f44d814446543baeed3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/41472 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/lenovo/t440p/Kconfig | 1 + src/mainboard/lenovo/t440p/acpi/ec.asl | 1 + 2 files changed, 2 insertions(+) diff --git a/src/mainboard/lenovo/t440p/Kconfig b/src/mainboard/lenovo/t440p/Kconfig index 7310dc106b..adb1722d66 100644 --- a/src/mainboard/lenovo/t440p/Kconfig +++ b/src/mainboard/lenovo/t440p/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select SOUTHBRIDGE_INTEL_LYNXPOINT select SYSTEM_TYPE_LAPTOP select MAINBOARD_USES_IFD_GBE_REGION + select H8_HAS_BAT_TRESHOLDS_IMPL config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/lenovo/t440p/acpi/ec.asl b/src/mainboard/lenovo/t440p/acpi/ec.asl index c4a43a1c2f..8dea152079 100644 --- a/src/mainboard/lenovo/t440p/acpi/ec.asl +++ b/src/mainboard/lenovo/t440p/acpi/ec.asl @@ -1,3 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include From 8f2737476805ee9629af1ad16646e6258825a24b Mon Sep 17 00:00:00 2001 From: Harshit Sharma Date: Fri, 22 May 2020 13:07:17 +0530 Subject: [PATCH 346/405] payloads/libpayload/libc: Do cosmetic fixes Make the code follow the coding style. Signed-off-by: Harshit Sharma Change-Id: I4ca168c4aedddef51103b270f105feab93739ecc Reviewed-on: https://review.coreboot.org/c/coreboot/+/41649 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- payloads/libpayload/libc/string.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/payloads/libpayload/libc/string.c b/payloads/libpayload/libc/string.c index b1d89d3fcc..c05a012f51 100644 --- a/payloads/libpayload/libc/string.c +++ b/payloads/libpayload/libc/string.c @@ -361,7 +361,7 @@ char *strsep(char **stringp, const char *delim) token = walk = *stringp; /* Walk, search for delimiters */ - while(*walk && !strchr(delim, *walk)) + while (*walk && !strchr(delim, *walk)) walk++; if (*walk) { @@ -424,7 +424,7 @@ long long int strtoll(const char *orig_ptr, char **endptr, int base) /* Purge whitespace */ - for( ; *ptr && isspace(*ptr); ptr++); + for ( ; *ptr && isspace(*ptr); ptr++); if (ptr[0] == '-') { is_negative = 1; @@ -478,7 +478,7 @@ unsigned long long int strtoull(const char *ptr, char **endptr, int base) /* Purge whitespace */ - for( ; *ptr && isspace(*ptr); ptr++); + for ( ; *ptr && isspace(*ptr); ptr++); if (!*ptr) return 0; @@ -491,9 +491,9 @@ unsigned long long int strtoull(const char *ptr, char **endptr, int base) else if (ptr[0] == '0') { base = 8; ptr++; - } - else + } else { base = 10; + } } /* Base 16 allows the 0x on front - so skip over it */ @@ -504,7 +504,7 @@ unsigned long long int strtoull(const char *ptr, char **endptr, int base) ptr += 2; } - for( ; *ptr && _valid(*ptr, base); ptr++) + for ( ; *ptr && _valid(*ptr, base); ptr++) ret = (ret * base) + _offset(*ptr, base); if (endptr != NULL) @@ -516,7 +516,8 @@ unsigned long long int strtoull(const char *ptr, char **endptr, int base) unsigned long int strtoul(const char *ptr, char **endptr, int base) { unsigned long long val = strtoull(ptr, endptr, base); - if (val > ULONG_MAX) return ULONG_MAX; + if (val > ULONG_MAX) + return ULONG_MAX; return val; } @@ -577,7 +578,7 @@ size_t strcspn(const char *s, const char *a) * @param ptr A pointer to a string pointer to keep state of the tokenizer * @return Pointer to token */ -char* strtok_r(char *str, const char *delim, char **ptr) +char *strtok_r(char *str, const char *delim, char **ptr) { /* start new tokenizing job or continue existing one? */ if (str == NULL) @@ -607,7 +608,7 @@ static char **strtok_global; * @param delim A pointer to an array of characters that delimit the token * @return Pointer to token */ -char* strtok(char *str, const char *delim) +char *strtok(char *str, const char *delim) { return strtok_r(str, delim, strtok_global); } From 0d512179c5e33de51620973250c9e3acf18ad082 Mon Sep 17 00:00:00 2001 From: Harshit Sharma Date: Tue, 26 May 2020 00:29:53 +0530 Subject: [PATCH 347/405] payloads/libpayload/libc: Avoid NULL pointer dereference Avoid dereferencing a NULL pointer in case of function parameter 'ptr'. Signed-off-by: Harshit Sharma Change-Id: I5dba27d9757fb55476f3d5848f0ed26ae9494bee Reviewed-on: https://review.coreboot.org/c/coreboot/+/41698 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- payloads/libpayload/libc/string.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/libc/string.c b/payloads/libpayload/libc/string.c index c05a012f51..a481fef7eb 100644 --- a/payloads/libpayload/libc/string.c +++ b/payloads/libpayload/libc/string.c @@ -599,8 +599,6 @@ char *strtok_r(char *str, const char *delim, char **ptr) return start; } -static char **strtok_global; - /** * Extract first token in string str that is delimited by a character in tokens. * Destroys str, eliminates the token delimiter and uses global state. @@ -610,7 +608,9 @@ static char **strtok_global; */ char *strtok(char *str, const char *delim) { - return strtok_r(str, delim, strtok_global); + static char *strtok_ptr; + + return strtok_r(str, delim, &strtok_ptr); } /** From 825005ac3d5357b1b3add5c8f15b82610b17edd4 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 26 May 2020 17:31:52 +0200 Subject: [PATCH 348/405] drivers/smmstore/Kconfig: Add a proper dependency This feature is only available if properly hooked up to an smihandler. Change-Id: I99baef07b0623f9a6b41e8b8e000a89589c298d0 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/41730 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/drivers/smmstore/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/smmstore/Kconfig b/src/drivers/smmstore/Kconfig index 019666b1ff..7ee8676014 100644 --- a/src/drivers/smmstore/Kconfig +++ b/src/drivers/smmstore/Kconfig @@ -2,7 +2,7 @@ config SMMSTORE bool "Support for flash based, SMM mediated data store" - depends on BOOT_DEVICE_SUPPORTS_WRITES + depends on BOOT_DEVICE_SUPPORTS_WRITES && HAVE_SMI_HANDLER default y if PAYLOAD_TIANOCORE select SPI_FLASH_SMM if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP From b4ab1e78cdda18fffb4dffd611300e3537315c17 Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 26 May 2020 15:28:09 +0800 Subject: [PATCH 349/405] mb/google/volteer: Create terrador variant Create the terrador variant of the volteer reference board BUG=b:156435028 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_TERRADOR Signed-off-by: David Wu Change-Id: I088861d1f8b7b4ee8de1e5ab6c7d3109ffd0531b Reviewed-on: https://review.coreboot.org/c/coreboot/+/41718 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg --- src/mainboard/google/volteer/Kconfig | 2 ++ src/mainboard/google/volteer/Kconfig.name | 4 +++ .../volteer/variants/terrador/Makefile.inc | 7 ++++ .../google/volteer/variants/terrador/gpio.c | 36 +++++++++++++++++++ .../terrador/include/variant/acpi/dptf.asl | 3 ++ .../variants/terrador/include/variant/ec.h | 8 +++++ .../variants/terrador/include/variant/gpio.h | 10 ++++++ .../volteer/variants/terrador/overridetree.cb | 4 +++ 8 files changed, 74 insertions(+) create mode 100644 src/mainboard/google/volteer/variants/terrador/Makefile.inc create mode 100644 src/mainboard/google/volteer/variants/terrador/gpio.c create mode 100644 src/mainboard/google/volteer/variants/terrador/include/variant/acpi/dptf.asl create mode 100644 src/mainboard/google/volteer/variants/terrador/include/variant/ec.h create mode 100644 src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h create mode 100644 src/mainboard/google/volteer/variants/terrador/overridetree.cb diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 2a7212b064..9c7292f6d6 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -64,6 +64,7 @@ config MAINBOARD_PART_NUMBER default "Halvor" if BOARD_GOOGLE_HALVOR default "Malefor" if BOARD_GOOGLE_MALEFOR default "Ripto" if BOARD_GOOGLE_RIPTO + default "Terrador" if BOARD_GOOGLE_TERRADOR default "Trondo" if BOARD_GOOGLE_TRONDO default "Volteer" if BOARD_GOOGLE_VOLTEER @@ -80,6 +81,7 @@ config VARIANT_DIR default "halvor" if BOARD_GOOGLE_HALVOR default "malefor" if BOARD_GOOGLE_MALEFOR default "ripto" if BOARD_GOOGLE_RIPTO + default "terrador" if BOARD_GOOGLE_TERRADOR default "trondo" if BOARD_GOOGLE_TRONDO default "volteer" if BOARD_GOOGLE_VOLTEER diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 5c674d85fd..479b118e99 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -13,6 +13,10 @@ config BOARD_GOOGLE_RIPTO select BOARD_GOOGLE_BASEBOARD_VOLTEER select VARIANT_HAS_MIPI_CAMERA +config BOARD_GOOGLE_TERRADOR + bool "-> Terrador" + select BOARD_GOOGLE_BASEBOARD_VOLTEER + config BOARD_GOOGLE_TRONDO bool "-> Trondo" select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/terrador/Makefile.inc b/src/mainboard/google/volteer/variants/terrador/Makefile.inc new file mode 100644 index 0000000000..c9a128d72a --- /dev/null +++ b/src/mainboard/google/volteer/variants/terrador/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +SPD_SOURCES = + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/terrador/gpio.c b/src/mainboard/google/volteer/variants/terrador/gpio.c new file mode 100644 index 0000000000..a54aeca16a --- /dev/null +++ b/src/mainboard/google/volteer/variants/terrador/gpio.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + +}; + +const struct pad_config *variant_base_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/google/volteer/variants/terrador/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/terrador/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..189cafea4c --- /dev/null +++ b/src/mainboard/google/volteer/variants/terrador/include/variant/acpi/dptf.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/volteer/variants/terrador/include/variant/ec.h b/src/mainboard/google/volteer/variants/terrador/include/variant/ec.h new file mode 100644 index 0000000000..4a9a461191 --- /dev/null +++ b/src/mainboard/google/volteer/variants/terrador/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h b/src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h new file mode 100644 index 0000000000..0075826350 --- /dev/null +++ b/src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Copied from baseboard and may need to change for the new variant. */ + +#endif diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb new file mode 100644 index 0000000000..75422d80bb --- /dev/null +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -0,0 +1,4 @@ +chip soc/intel/tigerlake + device domain 0 on + end +end From d2fea1ab2112185ce73b1730ddb5a093066c063a Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Mon, 18 May 2020 13:25:18 -0600 Subject: [PATCH 350/405] util/lint: Check for SPDX identifiers by default The majority of the codebase has been converted to use SPDX identifiers now, so let's enforce those by default. The only exceptions are src/include and src/lib, which are not being checked since many of the files there do not have license headers at all. Files with custom licenses that aren't covered by SPDX can be listed as exceptions at the top of lint-000-license-headers. Change-Id: Ie6642153793d5735c74c5950bc9e27ee7eecacbc Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/41602 Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- util/lint/lint-000-license-headers | 22 +--------------------- util/lint/lint-stable-000-license-headers | 19 +++---------------- 2 files changed, 4 insertions(+), 37 deletions(-) diff --git a/util/lint/lint-000-license-headers b/util/lint/lint-000-license-headers index eb14a94632..3f62a9b105 100755 --- a/util/lint/lint-000-license-headers +++ b/util/lint/lint-000-license-headers @@ -60,8 +60,6 @@ cmos\.layout|\ cmos\.default\ " -HEADER_TEXT="license header" - #space separated list of directories to test if [ "$1" = "" ]; then HEADER_DIRS="src util" @@ -69,11 +67,6 @@ else HEADER_DIRS="$1" fi -if [ "$2" = "SPDX_ONLY" ]; then - SPDX_ONLY=1 - HEADER_TEXT="SPDX identifier" -fi - LC_ALL=C export LC_ALL #get initial list from git, removing HEADER_EXCLUDED files. @@ -122,24 +115,11 @@ check_for_license 'SPDX-License-Identifier: X11' # differentiate between this license with or without advertising. check_for_license 'SPDX-License-Identifier: BSD-4-Clause-UC' -if [ ! "${SPDX_ONLY}" = "1" ]; then -check_for_license "under the terms of the GNU General Public License" \ - "WITHOUT ANY WARRANTY" -check_for_license 'IS PROVIDED .*"AS IS"' -check_for_license 'IS DISTRIBUTED .*"AS IS"' -check_for_license "IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE" -check_for_license '"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES' -check_for_license 'assumes any liability or responsibility for the use' -check_for_license 'THE AUTHORS DISCLAIM.*ALL WARRANTIES WITH REGARD TO THIS SOFTWARE' -check_for_license 'No license required' -check_for_license 'GNU Lesser General Public' -fi - for file in $headerlist; do # Verify the file exists, and has content that requires a header # This assumes that a file that has 4 lines or fewer is not notable # enough to require a license. if [ -f "$file" ] && [ "$(wc -l < "$file")" -gt 4 ]; then - echo "$file has no recognized ${HEADER_TEXT}." + echo "$file has no recognized SPDX identifier." fi done diff --git a/util/lint/lint-stable-000-license-headers b/util/lint/lint-stable-000-license-headers index 7b14b45477..a29c5d42dc 100755 --- a/util/lint/lint-stable-000-license-headers +++ b/util/lint/lint-stable-000-license-headers @@ -3,20 +3,7 @@ # # DESCR: Check that files have license headers -# Directories requiring SPDX Identifiers only -util/lint/lint-000-license-headers "src/acpi" SPDX_ONLY -util/lint/lint-000-license-headers "src/arch" SPDX_ONLY -util/lint/lint-000-license-headers "src/superio" SPDX_ONLY - # Top level -util/lint/lint-000-license-headers "src/commonlib src/console \ - src/cpu src/device src/ec src/mainboard src/northbridge src/soc \ - src/southbridge" - -# src/drivers -util/lint/lint-000-license-headers "src/drivers/ams src/drivers/aspeed src/drivers/dec src/drivers/elog \ - src/drivers/emulation src/drivers/gic src/drivers/ics src/drivers/ipmi src/drivers/maxim \ - src/drivers/parade src/drivers/ricoh src/drivers/sil src/drivers/ti src/drivers/usb src/drivers/xgi" - -# src/security -util/lint/lint-000-license-headers "src/security/vboot" +util/lint/lint-000-license-headers "src/acpi src/arch src/commonlib src/console \ + src/cpu src/device src/drivers src/ec src/mainboard src/northbridge \ + src/security src/soc src/southbridge src/superio" From be7507db29c7d4471878b1fa767da47901060223 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 21 May 2020 07:09:52 +0200 Subject: [PATCH 351/405] Remove new additions of "this file is part of" lines Change-Id: I6c69dcad82ee217ed4760dea1792dd1a6612cd8b Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41606 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- src/include/device/mipi_ids.h | 1 - src/include/spd_cache.h | 1 - .../google/hatch/variants/mushu/include/variant/acpi/dptf.asl | 1 - src/soc/intel/jasperlake/me.c | 1 - tests/commonlib/Makefile.inc | 1 - tests/commonlib/region-test.c | 1 - tests/include/tests/test.h | 1 - 7 files changed, 7 deletions(-) diff --git a/src/include/device/mipi_ids.h b/src/include/device/mipi_ids.h index 2d3cd4af44..86b5116005 100644 --- a/src/include/device/mipi_ids.h +++ b/src/include/device/mipi_ids.h @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ /* * MIPI Alliance Manufacturer IDs from https://mid.mipi.org diff --git a/src/include/spd_cache.h b/src/include/spd_cache.h index 3270defba8..f8d7d68622 100644 --- a/src/include/spd_cache.h +++ b/src/include/spd_cache.h @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ #ifndef __SPD_CACHE_H #define __SPD_CACHE_H diff --git a/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl index 505a11f377..eb23601191 100644 --- a/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ #define DPTF_CPU_PASSIVE 93 #define DPTF_CPU_CRITICAL 99 diff --git a/src/soc/intel/jasperlake/me.c b/src/soc/intel/jasperlake/me.c index c8496f9645..e4dc93feb4 100644 --- a/src/soc/intel/jasperlake/me.c +++ b/src/soc/intel/jasperlake/me.c @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ #include #include diff --git a/tests/commonlib/Makefile.inc b/tests/commonlib/Makefile.inc index ce3499cb2b..c620754e33 100644 --- a/tests/commonlib/Makefile.inc +++ b/tests/commonlib/Makefile.inc @@ -1,5 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only -# This file is part of the coreboot project. tests-y += region-test diff --git a/tests/commonlib/region-test.c b/tests/commonlib/region-test.c index 2c960e099a..219ed31f79 100644 --- a/tests/commonlib/region-test.c +++ b/tests/commonlib/region-test.c @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ #include #include diff --git a/tests/include/tests/test.h b/tests/include/tests/test.h index b4e0dd2b5e..4dc9988fde 100644 --- a/tests/include/tests/test.h +++ b/tests/include/tests/test.h @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ #ifndef _TESTS_TEST_H #define _TESTS_TEST_H From 087064f471650e90677fd990a84e976e601bd32a Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Tue, 26 May 2020 20:10:22 +0800 Subject: [PATCH 352/405] soc/intel/tigerlake: Correct GPIO community PID configuration Current implementation returns the incorrect GPIO community PID. The GPIO community index 3 should return PID for COMM_4 and index 4 should return PID for COMM_5. TEST=Verify PCR port id is correct for each community. Signed-off-by: Eric Lai Change-Id: I5dc48e5b31f43853b3a613c17f13f7df71f1fbfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/41725 Reviewed-by: Tim Wawrzynczak Reviewed-by: Aamir Bohra Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/acpi/gpio.asl | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/tigerlake/acpi/gpio.asl b/src/soc/intel/tigerlake/acpi/gpio.asl index 6206eb79ba..b17abfe483 100644 --- a/src/soc/intel/tigerlake/acpi/gpio.asl +++ b/src/soc/intel/tigerlake/acpi/gpio.asl @@ -106,19 +106,19 @@ Method (GPID, 1, Serialized) { Switch (ToInteger (Arg0)) { - Case (0) { + Case (COMM_0) { Local0 = PID_GPIOCOM0 } - Case (1) { + Case (COMM_1) { Local0 = PID_GPIOCOM1 } - Case (2) { + Case (COMM_2) { Local0 = PID_GPIOCOM2 } - Case (4) { + Case (COMM_4) { Local0 = PID_GPIOCOM4 } - Case (5) { + Case (COMM_5) { Local0 = PID_GPIOCOM5 } Default { From c351f57dcc070eb0365ab3bb05e0e65c770307ed Mon Sep 17 00:00:00 2001 From: Paul Fagerburg Date: Wed, 20 May 2020 13:21:13 -0600 Subject: [PATCH 353/405] util/mb/google: remove zork template The templates for the zork reference boards are still being actively worked on in the trembyle-bringup branch. Remove the zork template from the main branch to avoid confusion when trembyle-bringup is merged. BUG=b:157099580 BRANCH=none TEST=N/A Signed-off-by: Paul Fagerburg Change-Id: I0ff9de959c7b2646b90e68df05f0b2e9bdd60cf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41569 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- util/mainboard/google/zork/template/Makefile.inc | 4 ---- 1 file changed, 4 deletions(-) delete mode 100644 util/mainboard/google/zork/template/Makefile.inc diff --git a/util/mainboard/google/zork/template/Makefile.inc b/util/mainboard/google/zork/template/Makefile.inc deleted file mode 100644 index 61b23ede99..0000000000 --- a/util/mainboard/google/zork/template/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -## -## SPDX-License-Identifier: GPL-2.0-only - -SPD_SOURCES = From 1bb05ef30b2dc5ccfbc26a185f350fdc8ee4f904 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 15 May 2020 17:33:52 -0700 Subject: [PATCH 354/405] device: Enable resource allocation above 4G boundary with allocator v4 This change adds back CB:39487 which was reverted as part of CB:41412. Now that the resource allocator is split into old(v3) and new(v4), this change adds support for allocating resources above 4G boundary with the new allocator v4. Original commit message: This change adds support for allocating resources above the 4G boundary by making use of memranges for resource windows enabled in the previous CL. It adds a new resource flag IORESOURCE_ABOVE_4G which is used in the following ways: a) Downstream device resources can set this flag to indicate that they would like to have their resource allocation above the 4G boundary. These semantics will have to be enabled in the drivers managing the devices. It can also be extended to be enabled via devicetree. This flag is automatically propagated by the resource allocator from downstream devices to the upstream bridges in pass 1. It is done to ensure that the resource allocator has a global view of downstream requirements during pass 2 at domain level. b) Bridges have a single resource window for each of mem and prefmem resource types. Thus, if any downstream resource of the bridge requests allocation above 4G boundary, all the other downstream resources of the same type under the bridge will be allocated above 4G boundary. c) During pass 2, resource allocator at domain level splits IORESOURCE_MEM into two different memory ranges -- one for the window below 4G and other above 4G. Resource allocation happens separately for each of these windows. d) At the bridge level, there is no extra logic required since the resource will live entirely above or below the 4G boundary. Hence, all downstream devices of any bridge will fall within the window allocated to the bridge resource. To handle this case separately from that of domain, initializing of memranges for a bridge is done differently than the domain. Limitation: Resources of a given type at the bridge or downstream devices cannot live both above and below 4G boundary. Thus, if a bridge has some downstream resources requesting allocation for a given type above 4G boundary and other resources of the same type requesting allocation below 4G boundary, then all these resources of the same type get allocated above 4G boundary. Change-Id: I92a5cf7cd1457f2f713e1ffd8ea31796ce3d0cce Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41466 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/device/resource_allocator_v4.c | 149 ++++++++++++++++++++++++++--- src/include/device/resource.h | 2 + 2 files changed, 139 insertions(+), 12 deletions(-) diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c index b65fc8bf37..ae3c764c4c 100644 --- a/src/device/resource_allocator_v4.c +++ b/src/device/resource_allocator_v4.c @@ -103,6 +103,19 @@ static void update_bridge_resource(const struct device *bridge, struct resource if (child_res->limit && (child_res->limit < bridge_res->limit)) bridge_res->limit = child_res->limit; + /* + * Propagate the downstream resource request to allocate above 4G boundary to + * upstream bridge resource. This ensures that during pass 2, the resource + * allocator at domain level has a global view of all the downstream device + * requirements and thus address space is allocated as per updated flags in the + * bridge resource. + * + * Since the bridge resource is a single window, all the downstream resources of + * this bridge resource will be allocated space above 4G boundary. + */ + if (child_res->flags & IORESOURCE_ABOVE_4G) + bridge_res->flags |= IORESOURCE_ABOVE_4G; + /* * Alignment value of 0 means that the child resource has no alignment * requirements and so the base value remains unchanged here. @@ -207,22 +220,119 @@ static unsigned char get_alignment_by_resource_type(const struct resource *res) die("Unexpected resource type: flags(%d)!\n", res->flags); } -static void initialize_memranges(struct memranges *ranges, const struct resource *res, - unsigned long memrange_type) +/* + * If the resource is NULL or if the resource is not assigned, then it cannot be used for + * allocation for downstream devices. + */ +static bool is_resource_invalid(const struct resource *res) +{ + return (res == NULL) || !(res->flags & IORESOURCE_ASSIGNED); +} + +static void initialize_domain_io_resource_memranges(struct memranges *ranges, + const struct resource *res, + unsigned long memrange_type) +{ + memranges_insert(ranges, res->base, res->limit - res->base + 1, memrange_type); +} + +static void initialize_domain_mem_resource_memranges(struct memranges *ranges, + const struct resource *res, + unsigned long memrange_type) { resource_t res_base; resource_t res_limit; - unsigned char align = get_alignment_by_resource_type(res); - memranges_init_empty_with_alignment(ranges, NULL, 0, align); - - if ((res == NULL) || !(res->flags & IORESOURCE_ASSIGNED)) - return; + const resource_t limit_4g = 0xffffffff; res_base = res->base; res_limit = res->limit; - memranges_insert(ranges, res_base, res_limit - res_base + 1, memrange_type); + /* + * Split the resource into two separate ranges if it crosses the 4G boundary. Memrange + * type is set differently to ensure that memrange does not merge these two ranges. For + * the range above 4G boundary, given memrange type is ORed with IORESOURCE_ABOVE_4G. + */ + if (res_base <= limit_4g) { + + resource_t range_limit; + + /* Clip the resource limit at 4G boundary if necessary. */ + range_limit = MIN(res_limit, limit_4g); + memranges_insert(ranges, res_base, range_limit - res_base + 1, memrange_type); + + /* + * If the resource lies completely below the 4G boundary, nothing more needs to + * be done. + */ + if (res_limit <= limit_4g) + return; + + /* + * If the resource window crosses the 4G boundary, then update res_base to add + * another entry for the range above the boundary. + */ + res_base = limit_4g + 1; + } + + if (res_base > res_limit) + return; + + /* + * If resource lies completely above the 4G boundary or if the resource was clipped to + * add two separate ranges, the range above 4G boundary has the resource flag + * IORESOURCE_ABOVE_4G set. This allows domain to handle any downstream requests for + * resource allocation above 4G differently. + */ + memranges_insert(ranges, res_base, res_limit - res_base + 1, + memrange_type | IORESOURCE_ABOVE_4G); +} + +/* + * This function initializes memranges for domain device. If the resource crosses 4G boundary, + * then this function splits it into two ranges -- one for the window below 4G and the other for + * the window above 4G. The latter range has IORESOURCE_ABOVE_4G flag set to satisfy resource + * requests from downstream devices for allocations above 4G. + */ +static void initialize_domain_memranges(struct memranges *ranges, const struct resource *res, + unsigned long memrange_type) +{ + unsigned char align = get_alignment_by_resource_type(res); + + memranges_init_empty_with_alignment(ranges, NULL, 0, align); + + if (is_resource_invalid(res)) + return; + + if (res->flags & IORESOURCE_IO) + initialize_domain_io_resource_memranges(ranges, res, memrange_type); + else + initialize_domain_mem_resource_memranges(ranges, res, memrange_type); +} + +/* + * This function initializes memranges for bridge device. Unlike domain, bridge does not need to + * care about resource window crossing 4G boundary. This is handled by the resource allocator at + * domain level to ensure that all downstream bridges are allocated space either above or below + * 4G boundary as per the state of IORESOURCE_ABOVE_4G for the respective bridge resource. + * + * So, this function creates a single range of the entire resource window available for the + * bridge resource. Thus all downstream resources of the bridge for the given resource type get + * allocated space from the same window. If there is any downstream resource of the bridge which + * requests allocation above 4G, then all other downstream resources of the same type under the + * bridge get allocated above 4G. + */ +static void initialize_bridge_memranges(struct memranges *ranges, const struct resource *res, + unsigned long memrange_type) +{ + unsigned char align = get_alignment_by_resource_type(res); + + memranges_init_empty_with_alignment(ranges, NULL, 0, align); + + if (is_resource_invalid(res)) + return; + + memranges_insert(ranges, res->base, res->limit - res->base + 1, memrange_type); } static void print_resource_ranges(const struct memranges *ranges) @@ -360,10 +470,12 @@ static void setup_resource_ranges(const struct device *dev, const struct resourc dev_path(dev), resource2str(res), res->base, res->size, res->align, res->gran, res->limit); - initialize_memranges(ranges, res, type); - - if (dev->path.type == DEVICE_PATH_DOMAIN) + if (dev->path.type == DEVICE_PATH_DOMAIN) { + initialize_domain_memranges(ranges, res, type); constrain_domain_resources(dev, ranges, type); + } else { + initialize_bridge_memranges(ranges, res, type); + } print_resource_ranges(ranges); } @@ -469,12 +581,25 @@ static void allocate_domain_resources(const struct device *domain) * Domain does not distinguish between mem and prefmem resources. Thus, the resource * allocation at domain level considers mem and prefmem together when finding the best * fit based on the biggest resource requirement. + * + * However, resource requests for allocation above 4G boundary need to be handled + * separately if the domain resource window crosses this boundary. There is a single + * window for resource of type IORESOURCE_MEM. When creating memranges, this resource + * is split into two separate ranges -- one for the window below 4G boundary and other + * for the window above 4G boundary (with IORESOURCE_ABOVE_4G flag set). Thus, when + * allocating child resources, requests for below and above the 4G boundary are handled + * separately by setting the type_mask and type_match to allocate_child_resources() + * accordingly. */ res = find_domain_resource(domain, IORESOURCE_MEM); if (res) { setup_resource_ranges(domain, res, IORESOURCE_MEM, &ranges); - allocate_child_resources(domain->link_list, &ranges, IORESOURCE_TYPE_MASK, + allocate_child_resources(domain->link_list, &ranges, + IORESOURCE_TYPE_MASK | IORESOURCE_ABOVE_4G, IORESOURCE_MEM); + allocate_child_resources(domain->link_list, &ranges, + IORESOURCE_TYPE_MASK | IORESOURCE_ABOVE_4G, + IORESOURCE_MEM | IORESOURCE_ABOVE_4G); cleanup_resource_ranges(domain, &ranges, res); } diff --git a/src/include/device/resource.h b/src/include/device/resource.h index c97b01d22f..42c7e6ae45 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -24,6 +24,8 @@ #define IORESOURCE_SUBTRACTIVE 0x00040000 /* The IO resource has a bus below it. */ #define IORESOURCE_BRIDGE 0x00080000 +/* This is a request to allocate resource about 4G boundary. */ +#define IORESOURCE_ABOVE_4G 0x00100000 /* The resource needs to be reserved in the coreboot table */ #define IORESOURCE_RESERVE 0x10000000 /* The IO resource assignment has been stored in the device */ From 32f385ebfabe0b33c8c026c3972e4af880e39a5a Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 15 May 2020 23:35:00 -0700 Subject: [PATCH 355/405] Revert "Revert "pciexp_device: Add option to allocate prefetch memory above 4G boundary"" This reverts commit e15f352039a371156ceef37f0434003228166e99. Reason for revert: Resource allocator is split into old(v3) and new(v4). So, this change to provide an option to allocate prefetch memory above 4G boundary can be added back. Since the support for allocating above 4G boundary is available only in resource allocator v4, Kconfig option is accordingly updated to add depends on RESOURCE_ALLOCATOR_V4. Change-Id: I94e5866458c79c2719fd780f336fb5da71a7df66 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41467 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/device/Kconfig | 16 ++++++++++++++++ src/device/pciexp_device.c | 10 +++++++--- 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index 55abfe89b2..79ce77d66e 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -583,6 +583,22 @@ config PCIEXP_HOTPLUG_PREFETCH_MEM child devices. This size should be page-aligned. The default is 256 MiB. +config PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G + bool + depends on RESOURCE_ALLOCATOR_V4 + default y if !PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G + default n + help + This enables prefetch memory allocation above 4G boundary for the + hotplug resources. + +config PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G + bool "PCI Express Hotplug Prefetch Memory Allocation below 4G boundary" + default n + help + This enables prefetch memory allocation below 4G boundary for the + hotplug resources. + config PCIEXP_HOTPLUG_IO hex "PCI Express Hotplug I/O Space" default 0x2000 diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 1189207539..f04d865152 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -512,7 +512,7 @@ static void pciexp_hotplug_dummy_read_resources(struct device *dev) { struct resource *resource; - // Add extra memory space + /* Add extra memory space */ resource = new_resource(dev, 0x10); resource->size = CONFIG_PCIEXP_HOTPLUG_MEM; resource->align = 12; @@ -520,7 +520,7 @@ static void pciexp_hotplug_dummy_read_resources(struct device *dev) resource->limit = 0xffffffff; resource->flags |= IORESOURCE_MEM; - // Add extra prefetchable memory space + /* Add extra prefetchable memory space */ resource = new_resource(dev, 0x14); resource->size = CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM; resource->align = 12; @@ -528,7 +528,11 @@ static void pciexp_hotplug_dummy_read_resources(struct device *dev) resource->limit = 0xffffffffffffffff; resource->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; - // Add extra I/O space + /* Set resource flag requesting allocation above 4G boundary. */ + if (CONFIG(PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G)) + resource->flags |= IORESOURCE_ABOVE_4G; + + /* Add extra I/O space */ resource = new_resource(dev, 0x18); resource->size = CONFIG_PCIEXP_HOTPLUG_IO; resource->align = 12; From 918ee62977394e7a5b0b20554d9f9017cfe602c3 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 15 May 2020 17:37:07 -0700 Subject: [PATCH 356/405] Revert "Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports"" This reverts commit 1726fa1f0ce474cde32e8b32be34a212aff3ffba. Reason for revert: Resource allocator is split into old(v3) and new(v4). So, this change to enable hotplug resource allocator for volteer can land back. BUG=b:149186922 Change-Id: Ib6a4df610b045fbc885c70bff3698a032b79f770 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41468 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons --- src/mainboard/google/volteer/Kconfig | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 9c7292f6d6..7ed685a8e5 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -19,6 +19,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 + select PCIEXP_HOTPLUG select SOC_INTEL_TIGERLAKE if BOARD_GOOGLE_BASEBOARD_VOLTEER @@ -72,6 +73,20 @@ config MAX_CPUS int default 8 +# Reserving resources for PCIe Hotplug as per TGL BIOS Spec (doc #611569) +# Revision 0.7.6 Section 7.2.5.1.5 +config PCIEXP_HOTPLUG_BUSES + int + default 42 + +config PCIEXP_HOTPLUG_MEM + hex + default 0xc200000 # 194 MiB + +config PCIEXP_HOTPLUG_PREFETCH_MEM + hex + default 0x1c000000 # 448 MiB + config TPM_TIS_ACPI_INTERRUPT int default 21 # GPE0_DW0_21 (GPP_C21) From c0dc1e1bbe76fd960f2cb9b17468ed66f17de479 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 16 May 2020 13:54:37 -0700 Subject: [PATCH 357/405] device/resource_allocator_v4: Change BIOS_SPEW to BIOS_DEBUG This change updates the log level for prints in resource allocator v4 to BIOS_DEBUG instead of BIOS_SPEW. These are critical in debugging issues and should be enabled at log level BIOS_DEBUG. Signed-off-by: Furquan Shaikh Change-Id: Ib863619f5e1214e4fe6f05c52be6fa2de36e6c3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/41477 Reviewed-by: HAOUAS Elyes Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/device/resource_allocator_v4.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c index ae3c764c4c..75e8392a9a 100644 --- a/src/device/resource_allocator_v4.c +++ b/src/device/resource_allocator_v4.c @@ -67,7 +67,7 @@ static void update_bridge_resource(const struct device *bridge, struct resource */ base = 0; - printk(BIOS_SPEW, "%s %s: size: %llx align: %d gran: %d limit: %llx\n", + printk(BIOS_DEBUG, "%s %s: size: %llx align: %d gran: %d limit: %llx\n", dev_path(bridge), resource2str(bridge_res), bridge_res->size, bridge_res->align, bridge_res->gran, bridge_res->limit); @@ -122,7 +122,7 @@ static void update_bridge_resource(const struct device *bridge, struct resource */ base = round(base, child_res->align); - printk(BIOS_SPEW, "%s %02lx * [0x%llx - 0x%llx] %s\n", + printk(BIOS_DEBUG, "%s %02lx * [0x%llx - 0x%llx] %s\n", dev_path(child), child_res->index, base, base + child_res->size - 1, resource2str(child_res)); @@ -137,7 +137,7 @@ static void update_bridge_resource(const struct device *bridge, struct resource */ bridge_res->size = round(base, bridge_res->gran); - printk(BIOS_SPEW, "%s %s: size: %llx align: %d gran: %d limit: %llx done\n", + printk(BIOS_DEBUG, "%s %s: size: %llx align: %d gran: %d limit: %llx done\n", dev_path(bridge), resource2str(bridge_res), bridge_res->size, bridge_res->align, bridge_res->gran, bridge_res->limit); } @@ -371,7 +371,7 @@ static void allocate_child_resources(struct bus *bus, struct memranges *ranges, if (memranges_steal(ranges, resource->limit, resource->size, resource->align, type_match, &resource->base) == false) { printk(BIOS_ERR, "ERROR: Resource didn't fit!!! "); - printk(BIOS_SPEW, "%s %02lx * size: 0x%llx limit: %llx %s\n", + printk(BIOS_DEBUG, "%s %02lx * size: 0x%llx limit: %llx %s\n", dev_path(dev), resource->index, resource->size, resource->limit, resource2str(resource)); continue; @@ -380,7 +380,7 @@ static void allocate_child_resources(struct bus *bus, struct memranges *ranges, resource->limit = resource->base + resource->size - 1; resource->flags |= IORESOURCE_ASSIGNED; - printk(BIOS_SPEW, "%s %02lx * [0x%llx - 0x%llx] limit: %llx %s\n", + printk(BIOS_DEBUG, "%s %02lx * [0x%llx - 0x%llx] limit: %llx %s\n", dev_path(dev), resource->index, resource->base, resource->size ? resource->base + resource->size - 1 : resource->base, resource->limit, resource2str(resource)); @@ -393,7 +393,7 @@ static void update_constraints(struct memranges *ranges, const struct device *de if (!res->size) return; - printk(BIOS_SPEW, "%s: %s %02lx base %08llx limit %08llx %s (fixed)\n", + printk(BIOS_DEBUG, "%s: %s %02lx base %08llx limit %08llx %s (fixed)\n", __func__, dev_path(dev), res->index, res->base, res->base + res->size - 1, resource2str(res)); @@ -466,7 +466,7 @@ static void constrain_domain_resources(const struct device *domain, struct memra static void setup_resource_ranges(const struct device *dev, const struct resource *res, unsigned long type, struct memranges *ranges) { - printk(BIOS_SPEW, "%s %s: base: %llx size: %llx align: %d gran: %d limit: %llx\n", + printk(BIOS_DEBUG, "%s %s: base: %llx size: %llx align: %d gran: %d limit: %llx\n", dev_path(dev), resource2str(res), res->base, res->size, res->align, res->gran, res->limit); @@ -484,7 +484,7 @@ static void cleanup_resource_ranges(const struct device *dev, struct memranges * const struct resource *res) { memranges_teardown(ranges); - printk(BIOS_SPEW, "%s %s: base: %llx size: %llx align: %d gran: %d limit: %llx done\n", + printk(BIOS_DEBUG, "%s %s: base: %llx size: %llx align: %d gran: %d limit: %llx done\n", dev_path(dev), resource2str(res), res->base, res->size, res->align, res->gran, res->limit); } From c3568612391a5079f87acc0ea069a263e08be069 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 16 May 2020 15:18:23 -0700 Subject: [PATCH 358/405] device/resource_allocator_v4: Improve the logging in resource allocator This change makes the following improvements to debug logging in resource allocator: 1. Print depth is added to functions in pass 1 to better represent how the resource requirements of child devices impact the resource windows for parent bridge. 2. Device path is added to resource ranges to make it easier to understand what device the resouce ranges are associated with. 3. Prints in pass 2 (update constraints, resource ranges, resource assignment) are shifted left by 1 to make it easier to visualize resource allocation for each bridge including domain. Signed-off-by: Furquan Shaikh Change-Id: I3356a7278060e281d1a57d253537b097472827a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41478 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/device/resource_allocator_v4.c | 50 +++++++++++++++++------------- 1 file changed, 29 insertions(+), 21 deletions(-) diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c index 75e8392a9a..3a11032629 100644 --- a/src/device/resource_allocator_v4.c +++ b/src/device/resource_allocator_v4.c @@ -34,6 +34,8 @@ static bool dev_has_children(const struct device *dev) return bus && bus->children; } +#define res_printk(depth, str, ...) printk(BIOS_DEBUG, "%*c"str, depth, ' ', __VA_ARGS__) + /* * During pass 1, once all the requirements for downstream devices of a bridge are gathered, * this function calculates the overall resource requirement for the bridge. It starts by @@ -46,7 +48,7 @@ static bool dev_has_children(const struct device *dev) * on the tightest constraints downstream. */ static void update_bridge_resource(const struct device *bridge, struct resource *bridge_res, - unsigned long type_match) + unsigned long type_match, int print_depth) { const struct device *child; struct resource *child_res; @@ -67,7 +69,7 @@ static void update_bridge_resource(const struct device *bridge, struct resource */ base = 0; - printk(BIOS_DEBUG, "%s %s: size: %llx align: %d gran: %d limit: %llx\n", + res_printk(print_depth, "%s %s: size: %llx align: %d gran: %d limit: %llx\n", dev_path(bridge), resource2str(bridge_res), bridge_res->size, bridge_res->align, bridge_res->gran, bridge_res->limit); @@ -122,7 +124,7 @@ static void update_bridge_resource(const struct device *bridge, struct resource */ base = round(base, child_res->align); - printk(BIOS_DEBUG, "%s %02lx * [0x%llx - 0x%llx] %s\n", + res_printk(print_depth + 1, "%s %02lx * [0x%llx - 0x%llx] %s\n", dev_path(child), child_res->index, base, base + child_res->size - 1, resource2str(child_res)); @@ -137,7 +139,7 @@ static void update_bridge_resource(const struct device *bridge, struct resource */ bridge_res->size = round(base, bridge_res->gran); - printk(BIOS_DEBUG, "%s %s: size: %llx align: %d gran: %d limit: %llx done\n", + res_printk(print_depth, "%s %s: size: %llx align: %d gran: %d limit: %llx done\n", dev_path(bridge), resource2str(bridge_res), bridge_res->size, bridge_res->align, bridge_res->gran, bridge_res->limit); } @@ -146,7 +148,8 @@ static void update_bridge_resource(const struct device *bridge, struct resource * During pass 1, resource allocator at bridge level gathers requirements from downstream * devices and updates its own resource windows for the provided resource type. */ -static void compute_bridge_resources(const struct device *bridge, unsigned long type_match) +static void compute_bridge_resources(const struct device *bridge, unsigned long type_match, + int print_depth) { const struct device *child; struct resource *res; @@ -167,14 +170,14 @@ static void compute_bridge_resources(const struct device *bridge, unsigned long for (child = bus->children; child; child = child->sibling) { if (!dev_has_children(child)) continue; - compute_bridge_resources(child, type_match); + compute_bridge_resources(child, type_match, print_depth + 1); } /* * Update the window for current bridge resource now that all downstream * requirements are gathered. */ - update_bridge_resource(bridge, res, type_match); + update_bridge_resource(bridge, res, type_match, print_depth); } } @@ -194,6 +197,7 @@ static void compute_bridge_resources(const struct device *bridge, unsigned long static void compute_domain_resources(const struct device *domain) { const struct device *child; + const int print_depth = 1; if (domain->link_list == NULL) return; @@ -204,9 +208,10 @@ static void compute_domain_resources(const struct device *domain) if (!dev_has_children(child)) continue; - compute_bridge_resources(child, IORESOURCE_IO); - compute_bridge_resources(child, IORESOURCE_MEM); - compute_bridge_resources(child, IORESOURCE_MEM | IORESOURCE_PREFETCH); + compute_bridge_resources(child, IORESOURCE_IO, print_depth); + compute_bridge_resources(child, IORESOURCE_MEM, print_depth); + compute_bridge_resources(child, IORESOURCE_MEM | IORESOURCE_PREFETCH, + print_depth); } } @@ -335,17 +340,17 @@ static void initialize_bridge_memranges(struct memranges *ranges, const struct r memranges_insert(ranges, res->base, res->limit - res->base + 1, memrange_type); } -static void print_resource_ranges(const struct memranges *ranges) +static void print_resource_ranges(const struct device *dev, const struct memranges *ranges) { const struct range_entry *r; - printk(BIOS_INFO, "Resource ranges:\n"); + printk(BIOS_INFO, " %s: Resource ranges:\n", dev_path(dev)); if (memranges_is_empty(ranges)) - printk(BIOS_INFO, "EMPTY!!\n"); + printk(BIOS_INFO, " * EMPTY!!\n"); memranges_each_entry(r, ranges) { - printk(BIOS_INFO, "Base: %llx, Size: %llx, Tag: %lx\n", + printk(BIOS_INFO, " * Base: %llx, Size: %llx, Tag: %lx\n", range_entry_base(r), range_entry_size(r), range_entry_tag(r)); } } @@ -370,8 +375,8 @@ static void allocate_child_resources(struct bus *bus, struct memranges *ranges, if (memranges_steal(ranges, resource->limit, resource->size, resource->align, type_match, &resource->base) == false) { - printk(BIOS_ERR, "ERROR: Resource didn't fit!!! "); - printk(BIOS_DEBUG, "%s %02lx * size: 0x%llx limit: %llx %s\n", + printk(BIOS_ERR, " ERROR: Resource didn't fit!!! "); + printk(BIOS_DEBUG, " %s %02lx * size: 0x%llx limit: %llx %s\n", dev_path(dev), resource->index, resource->size, resource->limit, resource2str(resource)); continue; @@ -380,7 +385,7 @@ static void allocate_child_resources(struct bus *bus, struct memranges *ranges, resource->limit = resource->base + resource->size - 1; resource->flags |= IORESOURCE_ASSIGNED; - printk(BIOS_DEBUG, "%s %02lx * [0x%llx - 0x%llx] limit: %llx %s\n", + printk(BIOS_DEBUG, " %s %02lx * [0x%llx - 0x%llx] limit: %llx %s\n", dev_path(dev), resource->index, resource->base, resource->size ? resource->base + resource->size - 1 : resource->base, resource->limit, resource2str(resource)); @@ -393,7 +398,7 @@ static void update_constraints(struct memranges *ranges, const struct device *de if (!res->size) return; - printk(BIOS_DEBUG, "%s: %s %02lx base %08llx limit %08llx %s (fixed)\n", + printk(BIOS_DEBUG, " %s: %s %02lx base %08llx limit %08llx %s (fixed)\n", __func__, dev_path(dev), res->index, res->base, res->base + res->size - 1, resource2str(res)); @@ -477,7 +482,7 @@ static void setup_resource_ranges(const struct device *dev, const struct resourc initialize_bridge_memranges(ranges, res, type); } - print_resource_ranges(ranges); + print_resource_ranges(dev, ranges); } static void cleanup_resource_ranges(const struct device *dev, struct memranges *ranges, @@ -665,13 +670,16 @@ void allocate_resources(const struct device *root) post_log_path(child); /* Pass 1 - Gather requirements. */ - printk(BIOS_INFO, "Resource allocator: %s - Pass 1 (gathering requirements)\n", + printk(BIOS_INFO, "==== Resource allocator: %s - Pass 1 (gathering requirements) ===\n", dev_path(child)); compute_domain_resources(child); /* Pass 2 - Allocate resources as per gathered requirements. */ - printk(BIOS_INFO, "Resource allocator: %s - Pass 2 (allocating resources)\n", + printk(BIOS_INFO, "=== Resource allocator: %s - Pass 2 (allocating resources) ===\n", dev_path(child)); allocate_domain_resources(child); + + printk(BIOS_INFO, "=== Resource allocator: %s - resource allocation complete ===\n", + dev_path(child)); } } From 4cabf789fd7615318cd0552e490c252ba0f142a6 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Wed, 20 May 2020 13:09:39 -0700 Subject: [PATCH 359/405] soc/intel/tigerlake: Configure THC Enable/Disable THCx though devicetree BUG=None BRANCH=None TEST=Boot and check FSP log for THC setting Signed-off-by: Wonkyu Kim Change-Id: If7683969161be67f68f441c28c80503de39079b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41571 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/fsp_params.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 611a61035d..bdcd357173 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -17,6 +17,11 @@ #include #include +/* THC assignment definition */ +#define THC_NONE 0 +#define THC_0 1 +#define THC_1 2 + /* * Chip config parameter PcieRpL1Substates uses (UPD value + 1) * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. @@ -221,6 +226,19 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) else params->VmdEnable = 0; + /* THC */ + dev = pcidev_path_on_root(PCH_DEVFN_THC0); + if (!dev) + params->ThcPort0Assignment = 0; + else + params->ThcPort0Assignment = dev->enabled ? THC_0 : THC_NONE; + + dev = pcidev_path_on_root(PCH_DEVFN_THC1); + if (!dev) + params->ThcPort1Assignment = 0; + else + params->ThcPort1Assignment = dev->enabled ? THC_1 : THC_NONE; + /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; From 5f17458cfbe90171bf6d20d9c36470ebbfb3842f Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 26 May 2020 19:03:31 -0700 Subject: [PATCH 360/405] drivers/vpd: Fix VPD speed regressions on non-x86 devices CB:34634 expanded the VPD code to also be usable from romstage, shuffling a few things around and adding some extra infrastructure in the process. Unfortunately, the changes seem to have only been written with x86 devices in mind and make coreboot always load the whole VPD FMAP section (not just the used part) on devices where rdev_mmap() is not a no-op. This patch rewrites the VPD code to be based on region_device structures that only represent the VPD area actually used (rather than the whole FMAP section), and that only get mapped when accessed. (It would be even better to pull this concept into the VPD decoder itself, but since that is taken from third-party code and accesses in early stages aren't very common, let's not go there for now.) It also moves the copying into CBMEM to romstage so that late romstage accesses can already benefit from it, and makes early decoding available in all stages because at this point, why not. Also fix a long-standing bug where the 'consumed' counter was not reset between vpd_decode_string() calls to the RO and the RW VPD. Signed-off-by: Julius Werner Change-Id: I55a103180b290c1563e35a25496188b6a82e49ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/41757 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/drivers/vpd/Makefile.inc | 9 +- src/drivers/vpd/vpd.c | 212 +++++++++++++++++++++-------------- src/drivers/vpd/vpd.h | 23 ---- src/drivers/vpd/vpd_cbmem.c | 81 ------------- src/drivers/vpd/vpd_premem.c | 13 --- 5 files changed, 137 insertions(+), 201 deletions(-) delete mode 100644 src/drivers/vpd/vpd_cbmem.c delete mode 100644 src/drivers/vpd/vpd_premem.c diff --git a/src/drivers/vpd/Makefile.inc b/src/drivers/vpd/Makefile.inc index cc276e4968..f54c4d0dd9 100644 --- a/src/drivers/vpd/Makefile.inc +++ b/src/drivers/vpd/Makefile.inc @@ -1,2 +1,7 @@ -romstage-$(CONFIG_VPD) += vpd_decode.c vpd_premem.c vpd.c -ramstage-$(CONFIG_VPD) += vpd_decode.c vpd_cbmem.c vpd.c +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-$(CONFIG_VPD) += vpd_decode.c vpd.c +verstage-$(CONFIG_VPD) += vpd_decode.c vpd.c +romstage-$(CONFIG_VPD) += vpd_decode.c vpd.c +postcar-$(CONFIG_VPD) += vpd_decode.c vpd.c +ramstage-$(CONFIG_VPD) += vpd_decode.c vpd.c diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c index 7314c35025..f5ac81ebfd 100644 --- a/src/drivers/vpd/vpd.c +++ b/src/drivers/vpd/vpd.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include @@ -11,6 +12,23 @@ #include "vpd_decode.h" #include "vpd_tables.h" +/* Currently we only support Google VPD 2.0, which has a fixed offset. */ +enum { + CROSVPD_CBMEM_MAGIC = 0x43524f53, + CROSVPD_CBMEM_VERSION = 0x0001, +}; + +struct vpd_cbmem { + uint32_t magic; + uint32_t version; + uint32_t ro_size; + uint32_t rw_size; + uint8_t blob[0]; + /* The blob contains both RO and RW data. It starts with RO (0 .. + * ro_size) and then RW (ro_size .. ro_size+rw_size). + */ +}; + struct vpd_gets_arg { const uint8_t *key; const uint8_t *value; @@ -18,110 +36,137 @@ struct vpd_gets_arg { int matched; }; -struct vpd_blob vpd_blob; +static struct region_device ro_vpd, rw_vpd; /* - * returns the size of data in a VPD 2.0 formatted fmap region, or 0. - * Also sets *base as the region's base address. + * Initializes a region_device to represent the requested VPD 2.0 formatted + * region on flash. On errors rdev->size will be set to 0. */ -static int32_t get_vpd_size(const char *fmap_name, int32_t *base) +static void init_vpd_rdev(const char *fmap_name, struct region_device *rdev) { struct google_vpd_info info; - struct region_device vpd; int32_t size; - if (fmap_locate_area_as_rdev(fmap_name, &vpd)) { + if (fmap_locate_area_as_rdev(fmap_name, rdev)) { printk(BIOS_ERR, "%s: No %s FMAP section.\n", __func__, fmap_name); - return 0; + goto fail; } - size = region_device_sz(&vpd); + size = region_device_sz(rdev); if ((size < GOOGLE_VPD_2_0_OFFSET + sizeof(info)) || - rdev_chain(&vpd, &vpd, GOOGLE_VPD_2_0_OFFSET, + rdev_chain(rdev, rdev, GOOGLE_VPD_2_0_OFFSET, size - GOOGLE_VPD_2_0_OFFSET)) { printk(BIOS_ERR, "%s: Too small (%d) for Google VPD 2.0.\n", __func__, size); - return 0; + goto fail; } /* Try if we can find a google_vpd_info, otherwise read whole VPD. */ - if (rdev_readat(&vpd, &info, *base, sizeof(info)) != sizeof(info)) { + if (rdev_readat(rdev, &info, 0, sizeof(info)) != sizeof(info)) { printk(BIOS_ERR, "ERROR: Failed to read %s header.\n", fmap_name); - return 0; + goto fail; } if (memcmp(info.header.magic, VPD_INFO_MAGIC, sizeof(info.header.magic)) - == 0 && size >= info.size + sizeof(info)) { - *base += sizeof(info); - size = info.size; + == 0) { + if (rdev_chain(rdev, rdev, sizeof(info), info.size)) { + printk(BIOS_ERR, "ERROR: %s info size too large.\n", + fmap_name); + goto fail; + } } else if (info.header.tlv.type == VPD_TYPE_TERMINATOR || info.header.tlv.type == VPD_TYPE_IMPLICIT_TERMINATOR) { printk(BIOS_WARNING, "WARNING: %s is uninitialized or empty.\n", fmap_name); - size = 0; - } else { - size -= GOOGLE_VPD_2_0_OFFSET; + goto fail; } - return size; + return; + +fail: + memset(rdev, 0, sizeof(*rdev)); } -static void vpd_get_blob(void) +static int init_vpd_rdevs_from_cbmem(void) { - int32_t ro_vpd_base = 0; - int32_t rw_vpd_base = 0; - int32_t ro_vpd_size = get_vpd_size("RO_VPD", &ro_vpd_base); - int32_t rw_vpd_size = get_vpd_size("RW_VPD", &rw_vpd_base); + if (!cbmem_possibly_online()) + return -1; - /* Return if no VPD at all */ - if (ro_vpd_size == 0 && rw_vpd_size == 0) + struct vpd_cbmem *cbmem = cbmem_find(CBMEM_ID_VPD); + if (!cbmem) + return -1; + + rdev_chain(&ro_vpd, &addrspace_32bit.rdev, + (uintptr_t)cbmem->blob, cbmem->ro_size); + rdev_chain(&rw_vpd, &addrspace_32bit.rdev, + (uintptr_t)cbmem->blob + cbmem->ro_size, cbmem->rw_size); + + return 0; +} + +static void init_vpd_rdevs(void) +{ + static bool done = false; + + if (done) return; - vpd_blob.ro_base = NULL; - vpd_blob.ro_size = 0; - vpd_blob.rw_base = NULL; - vpd_blob.rw_size = 0; - - struct region_device vpd; - - if (ro_vpd_size) { - if (fmap_locate_area_as_rdev("RO_VPD", &vpd)) { - /* shouldn't happen, but let's be extra defensive */ - printk(BIOS_ERR, "%s: No RO_VPD FMAP section.\n", - __func__); - return; - } - rdev_chain(&vpd, &vpd, GOOGLE_VPD_2_0_OFFSET, - region_device_sz(&vpd) - GOOGLE_VPD_2_0_OFFSET); - vpd_blob.ro_base = (uint8_t *)(rdev_mmap_full(&vpd) + - sizeof(struct google_vpd_info)); - vpd_blob.ro_size = ro_vpd_size; + if (init_vpd_rdevs_from_cbmem() != 0) { + init_vpd_rdev("RO_VPD", &ro_vpd); + init_vpd_rdev("RW_VPD", &rw_vpd); } - if (rw_vpd_size) { - if (fmap_locate_area_as_rdev("RW_VPD", &vpd)) { - /* shouldn't happen, but let's be extra defensive */ - printk(BIOS_ERR, "%s: No RW_VPD FMAP section.\n", - __func__); - return; - } - rdev_chain(&vpd, &vpd, GOOGLE_VPD_2_0_OFFSET, - region_device_sz(&vpd) - GOOGLE_VPD_2_0_OFFSET); - vpd_blob.rw_base = (uint8_t *)(rdev_mmap_full(&vpd) + - sizeof(struct google_vpd_info)); - vpd_blob.rw_size = rw_vpd_size; - } - vpd_blob.initialized = true; + + done = true; } -const struct vpd_blob *vpd_load_blob(void) +static void cbmem_add_cros_vpd(int is_recovery) { - if (vpd_blob.initialized == false) - vpd_get_blob(); + struct vpd_cbmem *cbmem; - return &vpd_blob; + timestamp_add_now(TS_START_COPYVPD); + + init_vpd_rdevs(); + + /* Return if no VPD at all */ + if (region_device_sz(&ro_vpd) == 0 && region_device_sz(&rw_vpd) == 0) + return; + + size_t ro_size = region_device_sz(&ro_vpd); + size_t rw_size = region_device_sz(&rw_vpd); + + cbmem = cbmem_add(CBMEM_ID_VPD, sizeof(*cbmem) + ro_size + rw_size); + if (!cbmem) { + printk(BIOS_ERR, "%s: Failed to allocate CBMEM (%zu+%zu).\n", + __func__, ro_size, rw_size); + return; + } + + cbmem->magic = CROSVPD_CBMEM_MAGIC; + cbmem->version = CROSVPD_CBMEM_VERSION; + cbmem->ro_size = ro_size; + cbmem->rw_size = rw_size; + + if (ro_size) { + if (rdev_readat(&ro_vpd, cbmem->blob, 0, ro_size) != ro_size) { + printk(BIOS_ERR, "ERROR: Couldn't read RO VPD\n"); + cbmem->ro_size = ro_size = 0; + } + timestamp_add_now(TS_END_COPYVPD_RO); + } + + if (rw_size) { + if (rdev_readat(&rw_vpd, cbmem->blob + ro_size, 0, rw_size) + != rw_size) { + printk(BIOS_ERR, "ERROR: Couldn't read RW VPD\n"); + cbmem->rw_size = rw_size = 0; + } + timestamp_add_now(TS_END_COPYVPD_RW); + } + + init_vpd_rdevs_from_cbmem(); } static int vpd_gets_callback(const uint8_t *key, uint32_t key_len, @@ -141,33 +186,34 @@ static int vpd_gets_callback(const uint8_t *key, uint32_t key_len, return VPD_DECODE_FAIL; } +static void vpd_find_in(struct region_device *rdev, struct vpd_gets_arg *arg) +{ + if (region_device_sz(rdev) == 0) + return; + + uint32_t consumed = 0; + void *mapping = rdev_mmap_full(rdev); + while (vpd_decode_string(region_device_sz(rdev), mapping, + &consumed, vpd_gets_callback, arg) == VPD_DECODE_OK) { + /* Iterate until found or no more entries. */ + } + rdev_munmap(rdev, mapping); +} + const void *vpd_find(const char *key, int *size, enum vpd_region region) { - struct vpd_blob blob = {0}; - - vpd_get_buffers(&blob); - if (blob.ro_size == 0 && blob.rw_size == 0) - return NULL; - struct vpd_gets_arg arg = {0}; - uint32_t consumed = 0; arg.key = (const uint8_t *)key; arg.key_len = strlen(key); - if ((region == VPD_ANY || region == VPD_RO) && blob.ro_size != 0) { - while (vpd_decode_string(blob.ro_size, blob.ro_base, - &consumed, vpd_gets_callback, &arg) == VPD_DECODE_OK) { - /* Iterate until found or no more entries. */ - } - } + init_vpd_rdevs(); - if ((!arg.matched && region != VPD_RO) && blob.rw_size != 0) { - while (vpd_decode_string(blob.rw_size, blob.rw_base, - &consumed, vpd_gets_callback, &arg) == VPD_DECODE_OK) { - /* Iterate until found or no more entries. */ - } - } + if (region != VPD_RW) + vpd_find_in(&ro_vpd, &arg); + + if (!arg.matched && region != VPD_RO) + vpd_find_in(&rw_vpd, &arg); if (!arg.matched) return NULL; @@ -223,3 +269,5 @@ bool vpd_get_bool(const char *key, enum vpd_region region, uint8_t *val) } else return false; } + +ROMSTAGE_CBMEM_INIT_HOOK(cbmem_add_cros_vpd) diff --git a/src/drivers/vpd/vpd.h b/src/drivers/vpd/vpd.h index a78662579a..d54cef8df1 100644 --- a/src/drivers/vpd/vpd.h +++ b/src/drivers/vpd/vpd.h @@ -13,29 +13,6 @@ enum vpd_region { VPD_RW = 2 }; -/* VPD 2.0 data blob structure */ -struct vpd_blob { - bool initialized; - uint8_t *ro_base; - uint32_t ro_size; - uint8_t *rw_base; - uint32_t rw_size; -}; -extern struct vpd_blob g_vpd_blob; - -/* - * This function loads g_vpd_blob global variable. - * The variable is initialized if it was not. - */ -const struct vpd_blob *vpd_load_blob(void); - -/* - * This function gets the base address and size of - * buffers for RO_VPD/RW_VPD binary blobs, and sets - * the struct. - */ -void vpd_get_buffers(struct vpd_blob *blob); - /* * Reads VPD string value by key. * diff --git a/src/drivers/vpd/vpd_cbmem.c b/src/drivers/vpd/vpd_cbmem.c deleted file mode 100644 index eadda525d6..0000000000 --- a/src/drivers/vpd/vpd_cbmem.c +++ /dev/null @@ -1,81 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ - -#include -#include -#include -#include -#include - -#include "vpd_tables.h" -#include "vpd.h" - -/* Currently we only support Google VPD 2.0, which has a fixed offset. */ -enum { - CROSVPD_CBMEM_MAGIC = 0x43524f53, - CROSVPD_CBMEM_VERSION = 0x0001, -}; - -struct vpd_cbmem { - uint32_t magic; - uint32_t version; - uint32_t ro_size; - uint32_t rw_size; - uint8_t blob[0]; - /* The blob contains both RO and RW data. It starts with RO (0 .. - * ro_size) and then RW (ro_size .. ro_size+rw_size). - */ -}; - -static void cbmem_add_cros_vpd(int is_recovery) -{ - struct vpd_cbmem *cbmem; - const struct vpd_blob *blob; - - timestamp_add_now(TS_START_COPYVPD); - - blob = vpd_load_blob(); - - /* Return if no VPD at all */ - if (blob->ro_size == 0 && blob->rw_size == 0) - return; - - cbmem = cbmem_add(CBMEM_ID_VPD, sizeof(*cbmem) + blob->ro_size + - blob->rw_size); - if (!cbmem) { - printk(BIOS_ERR, "%s: Failed to allocate CBMEM (%u+%u).\n", - __func__, blob->ro_size, blob->rw_size); - return; - } - - cbmem->magic = CROSVPD_CBMEM_MAGIC; - cbmem->version = CROSVPD_CBMEM_VERSION; - cbmem->ro_size = blob->ro_size; - cbmem->rw_size = blob->rw_size; - - if (blob->ro_size) { - memcpy(cbmem->blob, blob->ro_base, blob->ro_size); - timestamp_add_now(TS_END_COPYVPD_RO); - } - - if (blob->rw_size) { - memcpy(cbmem->blob + blob->ro_size, blob->rw_base, - blob->rw_size); - timestamp_add_now(TS_END_COPYVPD_RW); - } -} - -void vpd_get_buffers(struct vpd_blob *blob) -{ - const struct vpd_cbmem *vpd; - - vpd = cbmem_find(CBMEM_ID_VPD); - if (!vpd || !vpd->ro_size) - return; - - blob->ro_base = (void *)vpd->blob; - blob->ro_size = vpd->ro_size; - blob->rw_base = (void *)vpd->blob + vpd->ro_size; - blob->rw_size = vpd->rw_size; -} - -RAMSTAGE_CBMEM_INIT_HOOK(cbmem_add_cros_vpd) diff --git a/src/drivers/vpd/vpd_premem.c b/src/drivers/vpd/vpd_premem.c deleted file mode 100644 index 641bf898df..0000000000 --- a/src/drivers/vpd/vpd_premem.c +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -#include "vpd.h" - -void vpd_get_buffers(struct vpd_blob *blob) -{ - const struct vpd_blob *b; - - b = vpd_load_blob(); - memcpy(blob, b, sizeof(*b)); -} From a3402973abcc7bfee513ebf9bb58f3d9a4d18225 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 27 May 2020 10:53:01 +0200 Subject: [PATCH 361/405] tests: Move cmocka binary into $(obj) Put it in $(objutil) so that it's shared between board builds with abuild even if that doesn't matter right now. Change-Id: I5670d9b661891262ad936980f63fa93b07c27e95 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/41770 Tested-by: build bot (Jenkins) Reviewed-by: Jan Dabros Reviewed-by: Martin Roth Reviewed-by: Angel Pons --- tests/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/Makefile.inc b/tests/Makefile.inc index a6689a2d06..f84fa30d52 100644 --- a/tests/Makefile.inc +++ b/tests/Makefile.inc @@ -3,7 +3,7 @@ testsrc = $(top)/tests testobj = $(obj)/tests cmockasrc = 3rdparty/cmocka -cmockaobj = $(cmockasrc)/build +cmockaobj = $(objutil)/cmocka CMOCKA_LIB := $(cmockaobj)/src/libcmocka.so From a0a198f7792e1c3eead192f73abf2d75fa723936 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 27 May 2020 10:59:09 +0200 Subject: [PATCH 362/405] tests: Allow emitting junit output for unit tests Change-Id: Iab0c4250b1baa77d4eab7538ec1fd3310f9e63e4 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/41771 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Angel Pons Reviewed-by: Jan Dabros --- tests/Makefile.inc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tests/Makefile.inc b/tests/Makefile.inc index f84fa30d52..2da29c3768 100644 --- a/tests/Makefile.inc +++ b/tests/Makefile.inc @@ -135,7 +135,13 @@ $(TEST_KCONFIG_AUTOCONFIG): $(TEST_KCONFIG_AUTOHEADER) .PHONY: $(alltests) $(addprefix clean-,$(alltests)) .PHONY: unit-tests build-unit-tests run-unit-tests clean-unit-tests +ifeq ($(JUNIT_OUTPUT),y) +$(alltests): export CMOCKA_MESSAGE_OUTPUT=xml +$(alltests): export CMOCKA_XML_FILE=$(testobj)/junit-$(subst /,_,$^).xml +endif + $(alltests): $$($$(@)-bin) + rm -f $(testobj)/junit-$(subst /,_,$^).xml ./$^ unit-tests: build-unit-tests run-unit-tests From 95226b3e74309650325b2e2199a90d670a99c452 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 27 May 2020 10:41:45 +0200 Subject: [PATCH 363/405] testing: Add unit tests to what-jenkins-does procedure They're not added as a dependency, even though that should be possible, because we want the build tests to run even when the unit tests fail. Change-Id: Ia3391d7b289160178fa773dfd7b7c51c6ef77805 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/41772 Tested-by: build bot (Jenkins) Reviewed-by: Jan Dabros Reviewed-by: Martin Roth Reviewed-by: Angel Pons --- util/testing/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc index 7c820f59ea..fb36c71a54 100644 --- a/util/testing/Makefile.inc +++ b/util/testing/Makefile.inc @@ -89,6 +89,7 @@ what-jenkins-does: (cd payloads/libpayload; unset COREBOOT_BUILD_DIR; $(MAKE) $(if $(JENKINS_NOCCACHE),,CONFIG_LP_CCACHE=y) V=$(V) Q=$(Q) junit.xml) $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=src/soc/nvidia/tegra124/lp0 BLD=tegra124_lp0 MFLAGS= MAKEFLAGS= MAKETARGET=all junit.xml $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=src/soc/nvidia/tegra210/lp0 BLD=tegra120_lp0 MFLAGS= MAKEFLAGS= MAKETARGET=all junit.xml + $(MAKE) unit-tests JUNIT_OUTPUT=y test-basic: test-lint test-tools test-abuild test-payloads test-cleanup From 1b35ec97cc54337680e239c7ad10fa1acc716a2f Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 27 May 2020 11:39:32 +0200 Subject: [PATCH 364/405] tests: Always run all unit tests So far, the semantics have been that run-unit-tests stopped at the first test suite that failed. This hides useful signal in later tests, so always run all tests and collect the result. Change-Id: I407715f85513c2c95a1cf89cfb427317dff9fbab Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/41773 Tested-by: build bot (Jenkins) Reviewed-by: Jan Dabros Reviewed-by: Martin Roth Reviewed-by: Angel Pons --- tests/Makefile.inc | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/tests/Makefile.inc b/tests/Makefile.inc index 2da29c3768..bfd18060ab 100644 --- a/tests/Makefile.inc +++ b/tests/Makefile.inc @@ -141,17 +141,25 @@ $(alltests): export CMOCKA_XML_FILE=$(testobj)/junit-$(subst /,_,$^).xml endif $(alltests): $$($$(@)-bin) - rm -f $(testobj)/junit-$(subst /,_,$^).xml - ./$^ + rm -f $(testobj)/junit-$(subst /,_,$^).xml $(testobj)/$(subst /,_,$^).failed + -./$^ || echo failed > $(testobj)/$(subst /,_,$^).failed unit-tests: build-unit-tests run-unit-tests build-unit-tests: $(test-bins) run-unit-tests: $(alltests) - echo "**********************" - echo " ALL TESTS PASSED" - echo "**********************" + if [ `find $(testobj) -name '*.failed' | wc -l` -gt 0 ]; then \ + echo "**********************"; \ + echo " TESTS FAILED"; \ + echo "**********************"; \ + exit 1; \ + else \ + echo "**********************"; \ + echo " ALL TESTS PASSED"; \ + echo "**********************"; \ + exit 0; \ + fi $(addprefix clean-,$(alltests)): clean-%: rm -rf $(obj)/$* From 316c180c413d08713795c7ae943b84d799deedfd Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Tue, 26 May 2020 14:52:31 +0530 Subject: [PATCH 365/405] soc/intel/jasperlake: Correct GPIO community PID configuration Current implementation returns the incorrect GPIO community PID. The GPIO community index 3 should return PID for COMM_4 and index 4 should return PID for COMM_5. TEST=Verify GPIO PM bits are correctly set through MS0x ACPI method. Signed-off-by: Aamir Bohra Change-Id: I3da4945e93605a297baff076295433164fdf613d Reviewed-on: https://review.coreboot.org/c/coreboot/+/41721 Reviewed-by: Maulik V Vaghela Reviewed-by: EricR Lai Tested-by: build bot (Jenkins) --- src/soc/intel/jasperlake/acpi/gpio.asl | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/jasperlake/acpi/gpio.asl b/src/soc/intel/jasperlake/acpi/gpio.asl index 60951f0b6b..f8b180df11 100644 --- a/src/soc/intel/jasperlake/acpi/gpio.asl +++ b/src/soc/intel/jasperlake/acpi/gpio.asl @@ -115,19 +115,19 @@ Method (GPID, 1, Serialized) { Switch (ToInteger (Arg0)) { - Case (0) { + Case (COMM_0) { Local0 = PID_GPIOCOM0 } - Case (1) { + Case (COMM_1) { Local0 = PID_GPIOCOM1 } - Case (2) { + Case (COMM_2) { Local0 = PID_GPIOCOM2 } - Case (4) { + Case (COMM_4) { Local0 = PID_GPIOCOM4 } - Case (5) { + Case (COMM_5) { Local0 = PID_GPIOCOM5 } Default { From 69589294c205b616e80cafbbfb0b33e105a75386 Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Wed, 27 May 2020 11:25:45 +0530 Subject: [PATCH 366/405] soc/intel/jasperlake: Disable PAVP UPD This patch will disable PAVP UPD, which is by default enabled in FSP. BUG=b:155595624 BRANCH=None TEST=Build, boot JSLRVP, Verified UPD values from FSP log Change-Id: I8e103ad11ae6ffa6b9efe4bf249bbe344bc10a30 Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/41763 Reviewed-by: Karthik Ramasubramanian Reviewed-by: Justin TerAvest Tested-by: build bot (Jenkins) --- src/soc/intel/jasperlake/fsp_params.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index eafc374584..75e1c64513 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -210,6 +210,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->XdciEnable = 0; } + /* Disable Pavp */ + params->PavpEnable = 0; + /* Provide correct UART number for FSP debug logs */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; From df771c1ee4329389968a76396ab5f43ae5478748 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 21 Dec 2019 10:17:56 +0200 Subject: [PATCH 367/405] arch/x86: Remove more romcc leftovers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The sections .rom.* were for romcc and no longer used. Some romcc comments were left behind when guards were removed. Change-Id: I060ad7af2f03c67946f9796e625c072b887280c1 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37955 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Reviewed-by: Arthur Heymans --- src/arch/x86/bootblock_crt0.S | 3 ++- src/arch/x86/prologue.inc | 6 ------ src/cpu/intel/fit/fit.S | 2 +- src/cpu/x86/16bit/entry16.inc | 1 + src/lib/program.ld | 6 ------ 5 files changed, 4 insertions(+), 14 deletions(-) delete mode 100644 src/arch/x86/prologue.inc diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 7291c47b92..9f45413e70 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -10,11 +10,12 @@ #include +.section .text + /* * Include the old code for reset vector and protected mode entry. That code has * withstood the test of time. */ -#include #include #include #include diff --git a/src/arch/x86/prologue.inc b/src/arch/x86/prologue.inc deleted file mode 100644 index 6d2ae1e039..0000000000 --- a/src/arch/x86/prologue.inc +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -.section ".rom.data", "a", @progbits -.section ".rom.text", "ax", @progbits diff --git a/src/cpu/intel/fit/fit.S b/src/cpu/intel/fit/fit.S index 149d2d0384..3b7396c5ce 100644 --- a/src/cpu/intel/fit/fit.S +++ b/src/cpu/intel/fit/fit.S @@ -8,7 +8,7 @@ fit_pointer: .long 0 .previous -.section ".rom.data", "a", @progbits +.section .text .align 16 .global fit_table .global fit_table_end diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index c71acb0bff..13d12beb66 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -26,6 +26,7 @@ */ #include +#include /* Symbol _start16bit must be aligned to 4kB to start AP CPUs with * Startup IPI message without RAM. diff --git a/src/lib/program.ld b/src/lib/program.ld index 734f040fcd..17aa3db72c 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -13,12 +13,6 @@ .text . : { _program = .; _text = .; - /* - * The .rom.* sections are to acommodate x86 romstage. romcc as well - * as the assembly files put their text and data in these sections. - */ - *(.rom.text); - *(.rom.data); *(.text._start); *(.text.stage_entry); #if (ENV_DECOMPRESSOR || ENV_BOOTBLOCK && \ From 58b8054ccacd0877bd52b640c7938f7582f6d69a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 19 Apr 2020 05:53:44 +0300 Subject: [PATCH 368/405] arch/x86: Fix id section in linker script MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Builds where RESET_X86_VECTOR is adjusted would create unintentionally large bootblock files since id section can move far away from .reset and .text. Some builds segfault or may try to create close to 4 GB large intermediate build objects. For cases where build is successful, id section would not reside within REGION(program) or REGION(bootblock). A proper fix to always place the ID data at the end of the coreboot.rom file is left as follow-up work. For now, just place id section below .reset. Change-Id: Idf0e4defcde6d5e264d4752cc93f4ffb6749d287 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/40583 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Arthur Heymans --- src/arch/x86/id.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/id.ld b/src/arch/x86/id.ld index b69a8dc1a5..ea8d7e9dbd 100644 --- a/src/arch/x86/id.ld +++ b/src/arch/x86/id.ld @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ SECTIONS { - . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; + . = (CONFIG_X86_RESET_VECTOR - CONFIG_ID_SECTION_OFFSET) + 0x10 - (__id_end - __id_start); .id (.): { KEEP(*(.id)) } From 7a6f27ce1ed8ad535aaff13cc36af30b228556cc Mon Sep 17 00:00:00 2001 From: harshit Date: Fri, 15 May 2020 10:40:02 +0530 Subject: [PATCH 369/405] lib: Add strtok() and strtok_r() Add strtok() and strtok_r() to the library. Signed-off-by: Harshit Sharma Change-Id: Ic855b31669be1c274cbf247c53ffa6f74ec5bf35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41420 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- src/include/string.h | 2 ++ src/lib/string.c | 25 +++++++++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/src/include/string.h b/src/include/string.h index f923ca5c02..8eef0680cb 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -29,6 +29,8 @@ int strcmp(const char *s1, const char *s2); int strncmp(const char *s1, const char *s2, int maxlen); int strspn(const char *str, const char *spn); int strcspn(const char *str, const char *spn); +char *strtok_r(char *str, const char *delim, char **ptr); +char *strtok(char *str, const char *delim); long atol(const char *str); /** diff --git a/src/lib/string.c b/src/lib/string.c index f0c24edcfc..e8f72a28e8 100644 --- a/src/lib/string.c +++ b/src/lib/string.c @@ -163,6 +163,31 @@ int strcspn(const char *str, const char *spn) return ret; } +char *strtok_r(char *str, const char *delim, char **ptr) +{ + char *start; + char *end; + + if (str == NULL) + str = *ptr; + start = str + strspn(str, delim); + if (start[0] == '\0') + return NULL; + + end = start + strcspn(start, delim); + *ptr = end; + if (end[0] != '\0') + *(*ptr)++ = '\0'; + return start; +} + +char *strtok(char *str, const char *delim) +{ + static char *strtok_ptr; + + return strtok_r(str, delim, &strtok_ptr); +} + long atol(const char *str) { long ret = 0; From 7f21ad0cba0d45fdd4cd1059780345ec055b5a35 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 28 May 2020 12:30:45 +0200 Subject: [PATCH 370/405] mb/google/zork/berknip: Replace full GPL header with SPDX line Change-Id: I858f870db0babcb51c594570e8136436ecbb0d1d Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/41823 Reviewed-by: Paul Menzel Reviewed-by: Nico Huber Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- .../google/zork/variants/berknip/romstage.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/src/mainboard/google/zork/variants/berknip/romstage.c b/src/mainboard/google/zork/variants/berknip/romstage.c index 6d93b5e91e..67ad31c6d8 100644 --- a/src/mainboard/google/zork/variants/berknip/romstage.c +++ b/src/mainboard/google/zork/variants/berknip/romstage.c @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include From 3b8284f37a20ce47d89f37bb22d1f312da4f40eb Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Wed, 27 May 2020 20:40:59 -0600 Subject: [PATCH 371/405] include/uuid.h: Add missing include uuid.h uses uint8_t which is provided by stdint.h. BUG=b:153675915 TEST=Fixed my compiler error. Signed-off-by: Raul E Rangel Change-Id: Idbec40f444d9df7587b9066faac65499415dae6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41803 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Felix Held Reviewed-by: Paul Menzel Reviewed-by: Furquan Shaikh --- src/include/uuid.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/include/uuid.h b/src/include/uuid.h index f6e3450558..c38b0fe469 100644 --- a/src/include/uuid.h +++ b/src/include/uuid.h @@ -4,6 +4,7 @@ #define _UUID_H_ #include +#include #define UUID_LEN 16 #define UUID_STRLEN 36 From 84f394e9c0cd9a82948f0027a76c8b41b14a11bc Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 26 May 2020 16:16:42 -0600 Subject: [PATCH 372/405] lib/cbfs: add cbfs_stage_load_and_decompress helper The LZ4 compressed stages assume in-place decompression. The constraints are validated in cbfstool for _stages_ such that they can be decompressed in place. However, that is only true for stages. As such, add a wrapper, cbfs_stage_load_and_decompress(), that handles the LZ4 stage loading case. BUG=b:155322763,b:150746858,b:152909132 Change-Id: I9525a266250aa6c775283b598c09d4f40692db55 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/41755 Reviewed-by: Arthur Heymans Reviewed-by: Furquan Shaikh Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/lib/cbfs.c | 49 ++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 40 insertions(+), 9 deletions(-) diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 74df3c5b39..e05ea801c8 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -116,6 +116,7 @@ size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, size_t in_size, void *buffer, size_t buffer_size, uint32_t compression) { size_t out_size; + void *map; switch (compression) { case CBFS_COMPRESS_NONE: @@ -129,23 +130,24 @@ size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, if (!cbfs_lz4_enabled()) return 0; - /* Load the compressed image to the end of the available memory - * area for in-place decompression. It is the responsibility of - * the caller to ensure that buffer_size is large enough - * (see compression.h, guaranteed by cbfstool for stages). */ - void *compr_start = buffer + buffer_size - in_size; - if (rdev_readat(rdev, compr_start, offset, in_size) != in_size) + /* cbfs_stage_load_and_decompress() takes care of in-place + lz4 decompression by setting up the rdev to be in memory. */ + map = rdev_mmap(rdev, offset, in_size); + if (map == NULL) return 0; timestamp_add_now(TS_START_ULZ4F); - out_size = ulz4fn(compr_start, in_size, buffer, buffer_size); + out_size = ulz4fn(map, in_size, buffer, buffer_size); timestamp_add_now(TS_END_ULZ4F); + + rdev_munmap(rdev, map); + return out_size; case CBFS_COMPRESS_LZMA: if (!cbfs_lzma_enabled()) return 0; - void *map = rdev_mmap(rdev, offset, in_size); + map = rdev_mmap(rdev, offset, in_size); if (map == NULL) return 0; @@ -163,6 +165,35 @@ size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, } } +static size_t cbfs_stage_load_and_decompress(const struct region_device *rdev, + size_t offset, size_t in_size, void *buffer, size_t buffer_size, + uint32_t compression) +{ + struct region_device rdev_src; + + if (compression == CBFS_COMPRESS_LZ4) { + if (!cbfs_lz4_enabled()) + return 0; + /* Load the compressed image to the end of the available memory + * area for in-place decompression. It is the responsibility of + * the caller to ensure that buffer_size is large enough + * (see compression.h, guaranteed by cbfstool for stages). */ + void *compr_start = buffer + buffer_size - in_size; + if (rdev_readat(rdev, compr_start, offset, in_size) != in_size) + return 0; + /* Create a region device backed by memory. */ + rdev_chain(&rdev_src, &addrspace_32bit.rdev, + (uintptr_t)compr_start, in_size); + + return cbfs_load_and_decompress(&rdev_src, 0, in_size, buffer, + buffer_size, compression); + } + + /* All other algorithms can use the generic implementation. */ + return cbfs_load_and_decompress(rdev, offset, in_size, buffer, + buffer_size, compression); +} + static inline int tohex4(unsigned int c) { return (c <= 9) ? (c + '0') : (c - 10 + 'a'); @@ -257,7 +288,7 @@ int cbfs_prog_stage_load(struct prog *pstage) goto out; } - fsize = cbfs_load_and_decompress(fh, foffset, fsize, load, + fsize = cbfs_stage_load_and_decompress(fh, foffset, fsize, load, stage.memlen, stage.compression); if (!fsize) return -1; From a85febcb1cfd31bd4d27e955fc2bcf9f8ef16cd5 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 15 May 2020 15:09:10 -0600 Subject: [PATCH 373/405] drivers/intel/fsp2_0: add option to compress FSP-S in cbfs Allow the ability for chipset or mainboard to choose to compress FSP-S in cbfs using LZMA or LZ4 routines. To accomplish this fsp_load_component() is added as an assist for performing the necessary logic and allow the caller to provide the destination selection. Since the main cbfs decompression paths are utilized add the appropriate checks for including compression algorithms under the FSP-S compression options. On picasso FSP-S (debug builds) the following savings were measured: no-compression: fsps.bin 327680 none FSP_COMPRESS_FSP_S_LZ4: fsps.bin 98339 LZ4 (327680 decompressed) -70% FSP_COMPRESS_FSP_S_LZMA: fsps.bin 71275 LZMA (327680 decompressed) -78% BUG=b:155322763,b:150746858,b:152909132 Change-Id: I8aa5d8c1cbaf4d08f38a918a9031a2570bc5247e Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/41449 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/drivers/intel/fsp2_0/Kconfig | 6 ++ src/drivers/intel/fsp2_0/Makefile.inc | 6 ++ src/drivers/intel/fsp2_0/include/fsp/util.h | 16 +++++ src/drivers/intel/fsp2_0/silicon_init.c | 60 +++++++----------- src/drivers/intel/fsp2_0/util.c | 69 +++++++++++++++++++++ src/lib/cbfs.c | 13 ++++ 6 files changed, 131 insertions(+), 39 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index cad652b905..6c4344e472 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -181,6 +181,12 @@ config FSP2_0_LOGO_FILE_NAME depends on FSP2_0_DISPLAY_LOGO default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/logo.bmp" +config FSP_COMPRESS_FSP_S_LZMA + bool + +config FSP_COMPRESS_FSP_S_LZ4 + bool + if FSP_PEIM_TO_PEIM_INTERFACE source "src/drivers/intel/fsp2_0/ppi/Kconfig" endif diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index a46f9b88a2..6c82b28d21 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -56,6 +56,12 @@ endif cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(FSP_S_CBFS) $(FSP_S_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_S_FILE)) $(FSP_S_CBFS)-type := fsp +ifeq ($(CONFIG_FSP_COMPRESS_FSP_S_LZMA),y) +$(FSP_S_CBFS)-compression := LZMA +endif +ifeq ($(CONFIG_FSP_COMPRESS_FSP_S_LZ4),y) +$(FSP_S_CBFS)-compression := LZ4 +endif ifeq ($(CONFIG_FSP_USE_REPO),y) $(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index ed2a2ae81d..f531e36bee 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -9,6 +9,7 @@ #include #include #include +#include #include struct hob_header { @@ -79,6 +80,21 @@ void fsp_find_bootloader_tolum(struct range_entry *re); enum cb_err fsp_validate_component(struct fsp_header *hdr, const struct region_device *rdev); +struct fsp_load_descriptor { + /* fsp_prog object will have region_device initialized to final + * load location in memory. */ + struct prog fsp_prog; + /* Fill in destination location given final load size. Return 0 on + * success, < 0 on error. */ + int (*get_destination)(const struct fsp_load_descriptor *fspld, + void **dest, size_t final_load_size, + const struct region_device *source); +}; + +/* Load the FSP component described by fsp_load_descriptor from cbfs. The FSP + * header object will be validated and filled in on successful load. */ +enum cb_err fsp_load_component(struct fsp_load_descriptor *fspld, struct fsp_header *hdr); + /* Get igd framebuffer bar from SoC */ uintptr_t fsp_soc_get_igd_bar(void); diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 6af445c19e..6f3781afaf 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -80,15 +80,24 @@ static void do_silicon_init(struct fsp_header *hdr) } } +static int fsps_get_dest(const struct fsp_load_descriptor *fspld, void **dest, + size_t size, const struct region_device *source) +{ + *dest = cbmem_add(CBMEM_ID_REFCODE, size); + + if (*dest == NULL) + return -1; + + return 0; +} + void fsps_load(bool s3wake) { - struct fsp_header *hdr = &fsps_hdr; - struct cbfsf file_desc; - struct region_device rdev; - const char *name = CONFIG_FSP_S_CBFS; - void *dest; - size_t size; - struct prog fsps = PROG_INIT(PROG_REFCODE, name); + struct fsp_load_descriptor fspld = { + .fsp_prog = PROG_INIT(PROG_REFCODE, CONFIG_FSP_S_CBFS), + .get_destination = fsps_get_dest, + }; + struct prog *fsps = &fspld.fsp_prog; static int load_done; if (load_done) @@ -96,45 +105,18 @@ void fsps_load(bool s3wake) if (s3wake && !CONFIG(NO_STAGE_CACHE)) { printk(BIOS_DEBUG, "Loading FSPS from stage_cache\n"); - stage_cache_load_stage(STAGE_REFCODE, &fsps); - if (fsp_validate_component(hdr, prog_rdev(&fsps)) != CB_SUCCESS) + stage_cache_load_stage(STAGE_REFCODE, fsps); + if (fsp_validate_component(&fsps_hdr, prog_rdev(fsps)) != CB_SUCCESS) die("On resume fsps header is invalid\n"); load_done = 1; return; } - if (cbfs_boot_locate(&file_desc, name, NULL)) { - printk(BIOS_ERR, "Could not locate %s in CBFS\n", name); - die("FSPS not available!\n"); - } + if (fsp_load_component(&fspld, &fsps_hdr) != CB_SUCCESS) + die("FSP-S failed to load\n"); - cbfs_file_data(&rdev, &file_desc); + stage_cache_add(STAGE_REFCODE, fsps); - /* Load and relocate into CBMEM. */ - size = region_device_sz(&rdev); - dest = cbmem_add(CBMEM_ID_REFCODE, size); - - if (dest == NULL) - die("Could not add FSPS to CBMEM!\n"); - - if (rdev_readat(&rdev, dest, 0, size) < 0) - die("Failed to read FSPS!\n"); - - if (fsp_component_relocate((uintptr_t)dest, dest, size) < 0) - die("Unable to relocate FSPS!\n"); - - /* Create new region device in memory after relocation. */ - rdev_chain(&rdev, &addrspace_32bit.rdev, (uintptr_t)dest, size); - - if (fsp_validate_component(hdr, &rdev) != CB_SUCCESS) - die("Invalid FSPS header!\n"); - - prog_set_area(&fsps, dest, size); - - stage_cache_add(STAGE_REFCODE, &fsps); - - /* Signal that FSP component has been loaded. */ - prog_segment_loaded(hdr->image_base, hdr->image_size, SEG_FINAL); load_done = 1; } diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index 4050862849..3b7516ab06 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -1,9 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include #include +#include +#include #include #include +#include #include #include @@ -114,3 +118,68 @@ void fsp_handle_reset(uint32_t status) break; } } + +static void *fsp_get_dest_and_load(struct fsp_load_descriptor *fspld, size_t size, + const struct region_device *source_rdev, + uint32_t compression_algo) +{ + void *dest; + + if (fspld->get_destination(fspld, &dest, size, source_rdev) < 0) { + printk(BIOS_ERR, "FSP Destination not obtained.\n"); + return NULL; + } + + if (cbfs_load_and_decompress(source_rdev, 0, region_device_sz(source_rdev), + dest, size, compression_algo) != size) { + printk(BIOS_ERR, "Failed to load FSP component.\n"); + return NULL; + } + + if (fsp_component_relocate((uintptr_t)dest, dest, size) < 0) { + printk(BIOS_ERR, "Unable to relocate FSP component!\n"); + return NULL; + } + + return dest; +} + +/* Load the FSP component described by fsp_load_descriptor from cbfs. The FSP + * header object will be validated and filled in on successful load. */ +enum cb_err fsp_load_component(struct fsp_load_descriptor *fspld, struct fsp_header *hdr) +{ + struct cbfsf file_desc; + uint32_t compression_algo; + size_t output_size; + void *dest; + struct region_device source_rdev; + struct prog *fsp_prog = &fspld->fsp_prog; + + if (fspld->get_destination == NULL) + return CB_ERR; + + if (cbfs_boot_locate(&file_desc, prog_name(fsp_prog), &fsp_prog->cbfs_type) < 0) + return CB_ERR; + + if (cbfsf_decompression_info(&file_desc, &compression_algo, &output_size) < 0) + return CB_ERR; + + cbfs_file_data(&source_rdev, &file_desc); + + dest = fsp_get_dest_and_load(fspld, output_size, &source_rdev, compression_algo); + + if (dest == NULL) + return CB_ERR; + + prog_set_area(fsp_prog, dest, output_size); + + if (fsp_validate_component(hdr, prog_rdev(fsp_prog)) != CB_SUCCESS) { + printk(BIOS_ERR, "Invalid FSP header after load!\n"); + return CB_ERR; + } + + /* Signal that FSP component has been loaded. */ + prog_segment_loaded(hdr->image_base, hdr->image_size, SEG_FINAL); + + return CB_SUCCESS; +} diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index e05ea801c8..ec5156c09c 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -91,8 +91,19 @@ int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, return ret; } +static inline bool fsps_env(void) +{ + /* FSP-S is assumed to be loaded in ramstage. */ + if (ENV_RAMSTAGE) + return true; + return false; +} + static inline bool cbfs_lz4_enabled(void) { + if (fsps_env() && CONFIG(FSP_COMPRESS_FSP_S_LZ4)) + return true; + if ((ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) && !CONFIG(COMPRESS_PRERAM_STAGES)) return false; @@ -101,6 +112,8 @@ static inline bool cbfs_lz4_enabled(void) static inline bool cbfs_lzma_enabled(void) { + if (fsps_env() && CONFIG(FSP_COMPRESS_FSP_S_LZMA)) + return true; /* We assume here romstage and postcar are never compressed. */ if (ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) return false; From 0013623b7c976b8f79778cecf3f146dc7aeab6e9 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 27 May 2020 08:31:26 -0600 Subject: [PATCH 374/405] mb/google/dragonegg: remove abandoned project Dragonegg is no longer in development nor used. Remove it. Change-Id: Ida30dba662bc517671824f8b70b73b4856836e97 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/41783 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/google/dragonegg/Kconfig | 75 ---- src/mainboard/google/dragonegg/Kconfig.name | 5 - src/mainboard/google/dragonegg/Makefile.inc | 23 -- src/mainboard/google/dragonegg/board_info.txt | 6 - src/mainboard/google/dragonegg/bootblock.c | 15 - src/mainboard/google/dragonegg/chromeos.c | 37 -- src/mainboard/google/dragonegg/chromeos.fmd | 44 --- src/mainboard/google/dragonegg/dsdt.asl | 47 --- src/mainboard/google/dragonegg/ec.c | 17 - src/mainboard/google/dragonegg/mainboard.c | 31 -- .../google/dragonegg/romstage_fsp_params.c | 73 ---- src/mainboard/google/dragonegg/smihandler.c | 26 -- .../spd/Hynix_H9HCNNN8KUMLHR_2GB.spd.hex | 32 -- .../spd/Hynix_H9HCNNNCPMMLHR_4GB.spd.hex | 32 -- .../google/dragonegg/spd/Makefile.inc | 26 -- .../spd/Micron_MT53E2G32D8QD_8GB.spd.hex | 32 -- .../spd/Micron_MT53E512M32D2NP_2GB.spd.hex | 32 -- .../dragonegg/variants/baseboard/Makefile.inc | 7 - .../variants/baseboard/devicetree.cb | 329 ------------------ .../dragonegg/variants/baseboard/gpio.c | 87 ----- .../variants/baseboard/include/baseboard/ec.h | 69 ---- .../baseboard/include/baseboard/gpio.h | 27 -- .../baseboard/include/baseboard/variants.h | 30 -- .../dragonegg/variants/baseboard/memory.c | 57 --- .../variants/dragonegg/include/variant/ec.h | 8 - .../variants/dragonegg/include/variant/gpio.h | 8 - 26 files changed, 1175 deletions(-) delete mode 100644 src/mainboard/google/dragonegg/Kconfig delete mode 100644 src/mainboard/google/dragonegg/Kconfig.name delete mode 100644 src/mainboard/google/dragonegg/Makefile.inc delete mode 100644 src/mainboard/google/dragonegg/board_info.txt delete mode 100644 src/mainboard/google/dragonegg/bootblock.c delete mode 100644 src/mainboard/google/dragonegg/chromeos.c delete mode 100644 src/mainboard/google/dragonegg/chromeos.fmd delete mode 100644 src/mainboard/google/dragonegg/dsdt.asl delete mode 100644 src/mainboard/google/dragonegg/ec.c delete mode 100644 src/mainboard/google/dragonegg/mainboard.c delete mode 100644 src/mainboard/google/dragonegg/romstage_fsp_params.c delete mode 100644 src/mainboard/google/dragonegg/smihandler.c delete mode 100644 src/mainboard/google/dragonegg/spd/Hynix_H9HCNNN8KUMLHR_2GB.spd.hex delete mode 100644 src/mainboard/google/dragonegg/spd/Hynix_H9HCNNNCPMMLHR_4GB.spd.hex delete mode 100644 src/mainboard/google/dragonegg/spd/Makefile.inc delete mode 100644 src/mainboard/google/dragonegg/spd/Micron_MT53E2G32D8QD_8GB.spd.hex delete mode 100644 src/mainboard/google/dragonegg/spd/Micron_MT53E512M32D2NP_2GB.spd.hex delete mode 100644 src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc delete mode 100644 src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb delete mode 100644 src/mainboard/google/dragonegg/variants/baseboard/gpio.c delete mode 100644 src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h delete mode 100644 src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h delete mode 100644 src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h delete mode 100644 src/mainboard/google/dragonegg/variants/baseboard/memory.c delete mode 100644 src/mainboard/google/dragonegg/variants/dragonegg/include/variant/ec.h delete mode 100644 src/mainboard/google/dragonegg/variants/dragonegg/include/variant/gpio.h diff --git a/src/mainboard/google/dragonegg/Kconfig b/src/mainboard/google/dragonegg/Kconfig deleted file mode 100644 index 550d83a7df..0000000000 --- a/src/mainboard/google/dragonegg/Kconfig +++ /dev/null @@ -1,75 +0,0 @@ -config BOARD_GOOGLE_BASEBOARD_DRAGONEGG - def_bool n - select BOARD_ROMSIZE_KB_32768 - select DRIVERS_I2C_GENERIC - select DRIVERS_I2C_HID - select DRIVERS_SPI_ACPI - select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_ESPI - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select INTEL_LPSS_UART_FOR_CONSOLE - select MAINBOARD_HAS_CHROMEOS - select SOC_INTEL_ICELAKE - -if BOARD_GOOGLE_BASEBOARD_DRAGONEGG - -config CHROMEOS - bool - default y - select GBB_FLAG_FORCE_MANUAL_RECOVERY - -config DEVICETREE - string - default "variants/baseboard/devicetree.cb" - -config DIMM_SPD_SIZE - int - default 512 - -# Select this option to enable use of cr50 SPI TPM on dragon egg. -config DRAGONEGG_USE_SPI_TPM - bool - default y - select MAINBOARD_HAS_SPI_TPM_CR50 - select MAINBOARD_HAS_TPM2 - -config DRIVER_TPM_SPI_BUS - depends on DRAGONEGG_USE_SPI_TPM - default 0x1 - -config MAINBOARD_DIR - string - default "google/dragonegg" - -config MAINBOARD_PART_NUMBER - string - default "Dragonegg" - -config MAINBOARD_FAMILY - string - default "Google_Dragonegg" - -config MAX_CPUS - int - default 8 - -config TPM_TIS_ACPI_INTERRUPT - int - default 48 # GPE0_DW1_16 (GPP_D16) - -config VARIANT_DIR - string - default "dragonegg" if BOARD_GOOGLE_DRAGONEGG - -config UART_FOR_CONSOLE - int - default 0 - -config VBOOT - select VBOOT_LID_SWITCH - select EC_GOOGLE_CHROMEEC_SWITCHES - select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN - -endif # BOARD_GOOGLE_BASEBOARD_DRAGONEGG diff --git a/src/mainboard/google/dragonegg/Kconfig.name b/src/mainboard/google/dragonegg/Kconfig.name deleted file mode 100644 index 8b1bbb1775..0000000000 --- a/src/mainboard/google/dragonegg/Kconfig.name +++ /dev/null @@ -1,5 +0,0 @@ -comment "DragonEgg" - -config BOARD_GOOGLE_DRAGONEGG - bool "-> DragonEgg" - select BOARD_GOOGLE_BASEBOARD_DRAGONEGG diff --git a/src/mainboard/google/dragonegg/Makefile.inc b/src/mainboard/google/dragonegg/Makefile.inc deleted file mode 100644 index 818df63c84..0000000000 --- a/src/mainboard/google/dragonegg/Makefile.inc +++ /dev/null @@ -1,23 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -bootblock-y += bootblock.c -bootblock-$(CONFIG_CHROMEOS) += chromeos.c - -verstage-$(CONFIG_CHROMEOS) += chromeos.c - -romstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-y += romstage_fsp_params.c - -ramstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c -ramstage-y += mainboard.c - -smm-y += smihandler.c - -subdirs-y += variants/baseboard -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include - -subdirs-y += variants/$(VARIANT_DIR) -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include - -subdirs-y += spd diff --git a/src/mainboard/google/dragonegg/board_info.txt b/src/mainboard/google/dragonegg/board_info.txt deleted file mode 100644 index 3fb6f21d55..0000000000 --- a/src/mainboard/google/dragonegg/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Vendor name: google -Board name: Dragon Egg -Category: eval -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/google/dragonegg/bootblock.c b/src/mainboard/google/dragonegg/bootblock.c deleted file mode 100644 index 22d63b973c..0000000000 --- a/src/mainboard/google/dragonegg/bootblock.c +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include - -void bootblock_mainboard_init(void) -{ - const struct pad_config *pads; - size_t num; - - pads = variant_early_gpio_table(&num); - gpio_configure_pads(pads, num); -} diff --git a/src/mainboard/google/dragonegg/chromeos.c b/src/mainboard/google/dragonegg/chromeos.c deleted file mode 100644 index 5a7efefdee..0000000000 --- a/src/mainboard/google/dragonegg/chromeos.c +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include - -#include - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, - {-1, ACTIVE_HIGH, 0, "power"}, - {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), - "EC in RW"}, - }; - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} - -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} - -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} diff --git a/src/mainboard/google/dragonegg/chromeos.fmd b/src/mainboard/google/dragonegg/chromeos.fmd deleted file mode 100644 index 7bdeb17ac8..0000000000 --- a/src/mainboard/google/dragonegg/chromeos.fmd +++ /dev/null @@ -1,44 +0,0 @@ -FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x3F0000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x36F000 - } - SI_BIOS@0x1400000 0xC00000 { - RW_SECTION_A@0x0 0x2d0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x2bffc0 - RW_FWID_A@0x2cffc0 0x40 - } - RW_SECTION_B@0x2d0000 0x2d0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x2bffc0 - RW_FWID_B@0x2cffc0 0x40 - } - RW_MISC@0x5a0000 0x30000 { - UNIFIED_MRC_CACHE@0x0 0x20000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - } - RW_ELOG(PRESERVE)@0x20000 0x4000 - RW_SHARED@0x24000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 - } - RW_LEGACY(CBFS)@0x5d0000 0x230000 - # Make WP_RO region align with SPI vendor - # memory protected range specification. - WP_RO@0x800000 0x400000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x3fc000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x30c000 - } - } - } -} diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl deleted file mode 100644 index 15e0498a1e..0000000000 --- a/src/mainboard/google/dragonegg/dsdt.asl +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include "variant/ec.h" -#include "variant/gpio.h" - -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision -) -{ - #include - - // global NVS and variables - #include - - // CPU - #include - - Scope (\_SB) { - Device (PCI0) - { - #include - #include - } - } - -#if CONFIG(CHROMEOS) - // Chrome OS specific - #include -#endif - - #include - - /* Chrome OS Embedded Controller */ - Scope (\_SB.PCI0.LPCB) - { - /* ACPI code for EC SuperIO functions */ - #include - /* ACPI code for EC functions */ - #include - } -} diff --git a/src/mainboard/google/dragonegg/ec.c b/src/mainboard/google/dragonegg/ec.c deleted file mode 100644 index a2fc275219..0000000000 --- a/src/mainboard/google/dragonegg/ec.c +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include - -void mainboard_ec_init(void) -{ - const struct google_chromeec_event_info info = { - .log_events = MAINBOARD_EC_LOG_EVENTS, - .sci_events = MAINBOARD_EC_SCI_EVENTS, - .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, - .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, - }; - - google_chromeec_events_init(&info, acpi_is_wakeup_s3()); -} diff --git a/src/mainboard/google/dragonegg/mainboard.c b/src/mainboard/google/dragonegg/mainboard.c deleted file mode 100644 index 90889ae81d..0000000000 --- a/src/mainboard/google/dragonegg/mainboard.c +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include - -static void mainboard_init(void *chip_info) -{ - size_t num; - const struct pad_config *gpio_table; - - gpio_table = variant_gpio_table(&num); - gpio_configure_pads(gpio_table, num); - - mainboard_ec_init(); -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->write_acpi_tables = NULL; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - -struct chip_operations mainboard_ops = { - .init = mainboard_init, - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/google/dragonegg/romstage_fsp_params.c b/src/mainboard/google/dragonegg/romstage_fsp_params.c deleted file mode 100644 index a70c432e28..0000000000 --- a/src/mainboard/google/dragonegg/romstage_fsp_params.c +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include - -static uintptr_t mainboard_get_spd_data(void) -{ - char *spd_file; - size_t spd_file_len; - int spd_index; - const size_t spd_len = CONFIG_DIMM_SPD_SIZE; - const char *spd_bin = "spd.bin"; - - spd_index = variant_memory_sku(); - assert(spd_index >= 0); - printk(BIOS_INFO, "SPD index %d\n", spd_index); - - /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak(spd_bin, CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - /* make sure we have at least one SPD in the file. */ - if (spd_file_len < spd_len) - die("Missing SPD data."); - - /* Make sure we did not overrun the buffer */ - if (spd_file_len < ((spd_index + 1) * spd_len)) - die("Invalid SPD index."); - - spd_index *= spd_len; - - return (uintptr_t)(spd_file + spd_index); -} - -void mainboard_memory_init_params(FSPM_UPD *mupd) -{ - FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; - struct lpddr4_config mem_params; - - memset(&mem_params, 0, sizeof(mem_params)); - variant_memory_params(&mem_params); - - if (mem_params.dq_map && mem_params.dq_map_size) - memcpy(&mem_cfg->DqByteMapCh0, mem_params.dq_map, - mem_params.dq_map_size); - - if (mem_params.dqs_map && mem_params.dqs_map_size) - memcpy(&mem_cfg->DqsMapCpu2DramCh0, mem_params.dqs_map, - mem_params.dqs_map_size); - - memcpy(&mem_cfg->RcompResistor, mem_params.rcomp_resistor, - mem_params.rcomp_resistor_size); - - memcpy(&mem_cfg->RcompTarget, mem_params.rcomp_target, - mem_params.rcomp_target_size); - - mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); - mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; - mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; - mem_cfg->DqPinsInterleaved = 0; - mem_cfg->CaVrefConfig = 0x2; - mem_cfg->ECT = 1; /* Early Command Training Enabled */ - mem_cfg->RefClk = 0; /* Auto Select CLK freq */ - mem_cfg->SpdAddressTable[0] = 0x0; - mem_cfg->SpdAddressTable[1] = 0x0; - mem_cfg->SpdAddressTable[2] = 0x0; - mem_cfg->SpdAddressTable[3] = 0x0; -} diff --git a/src/mainboard/google/dragonegg/smihandler.c b/src/mainboard/google/dragonegg/smihandler.c deleted file mode 100644 index 59e70018f3..0000000000 --- a/src/mainboard/google/dragonegg/smihandler.c +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include - -void mainboard_smi_espi_handler(void) -{ - chromeec_smi_process_events(); -} - -void mainboard_smi_sleep(u8 slp_typ) -{ - chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, - MAINBOARD_EC_S5_WAKE_EVENTS); -} - -int mainboard_smi_apmc(u8 apmc) -{ - chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, - MAINBOARD_EC_SMI_EVENTS); - return 0; -} diff --git a/src/mainboard/google/dragonegg/spd/Hynix_H9HCNNN8KUMLHR_2GB.spd.hex b/src/mainboard/google/dragonegg/spd/Hynix_H9HCNNN8KUMLHR_2GB.spd.hex deleted file mode 100644 index d9014dc1ed..0000000000 --- a/src/mainboard/google/dragonegg/spd/Hynix_H9HCNNN8KUMLHR_2GB.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 11 0E 15 21 91 08 00 40 00 00 02 22 00 00 -00 00 05 32 92 55 00 00 8C 00 90 A8 90 C0 08 60 -04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 9E 00 A7 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/dragonegg/spd/Hynix_H9HCNNNCPMMLHR_4GB.spd.hex b/src/mainboard/google/dragonegg/spd/Hynix_H9HCNNNCPMMLHR_4GB.spd.hex deleted file mode 100644 index 2f2b18ad08..0000000000 --- a/src/mainboard/google/dragonegg/spd/Hynix_H9HCNNNCPMMLHR_4GB.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 11 0E 15 21 B1 08 00 40 00 00 0A 22 00 00 -48 00 05 32 92 55 00 00 8C 00 90 A8 90 C0 08 60 -04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 9E 00 A7 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/dragonegg/spd/Makefile.inc b/src/mainboard/google/dragonegg/spd/Makefile.inc deleted file mode 100644 index b5dc608707..0000000000 --- a/src/mainboard/google/dragonegg/spd/Makefile.inc +++ /dev/null @@ -1,26 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -SPD_BIN = $(obj)/spd.bin - -SPD_SOURCES = Hynix_H9HCNNN8KUMLHR_2GB # 0b000 -SPD_SOURCES += Hynix_H9HCNNNCPMMLHR_4GB # 0b001 -SPD_SOURCES += Micron_MT53E512M32D2NP_2GB # 0b010 -SPD_SOURCES += Micron_MT53E2G32D8QD_8GB # 0b011 - -ifeq ($(SPD_SOURCES),) - SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this) -else - SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) -endif - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/dragonegg/spd/Micron_MT53E2G32D8QD_8GB.spd.hex b/src/mainboard/google/dragonegg/spd/Micron_MT53E2G32D8QD_8GB.spd.hex deleted file mode 100644 index 856c05e422..0000000000 --- a/src/mainboard/google/dragonegg/spd/Micron_MT53E2G32D8QD_8GB.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 11 0E 15 29 F0 08 00 40 00 00 09 22 00 00 -00 00 05 0F 12 29 05 00 8A 00 90 A8 90 C0 08 60 -04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 92 00 A7 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 -20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/dragonegg/spd/Micron_MT53E512M32D2NP_2GB.spd.hex b/src/mainboard/google/dragonegg/spd/Micron_MT53E512M32D2NP_2GB.spd.hex deleted file mode 100644 index 71e5456542..0000000000 --- a/src/mainboard/google/dragonegg/spd/Micron_MT53E512M32D2NP_2GB.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 11 0E 15 21 90 08 00 40 00 00 02 22 00 00 -00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 -04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 E1 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 -20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc b/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc deleted file mode 100644 index fb7eaf11e9..0000000000 --- a/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc +++ /dev/null @@ -1,7 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -bootblock-y += gpio.c - -romstage-y += memory.c - -ramstage-y += gpio.c diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb deleted file mode 100644 index d77633ddd7..0000000000 --- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb +++ /dev/null @@ -1,329 +0,0 @@ -chip soc/intel/icelake - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "PMC_GPP_B" - register "gpe0_dw1" = "PMC_GPP_D" - register "gpe0_dw2" = "PMC_GPP_C" - - device cpu_cluster 0 on - device lapic 0 on end - end - - register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkSsp0" = "1" - register "PchHdaAudioLinkSsp1" = "1" - - # FSP configuration - register "SaGv" = "SaGv_Enabled" - register "SmbusEnable" = "1" - register "ScsEmmcHs400Enabled" = "1" - - register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 2 - register "usb2_ports[2]" = "USB2_PORT_LONG(OC2)" # Type-C Port 3 - register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" - - # Enable Pch iSCLK - register "pch_isclk" = "1" - - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieRpEnable[7]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "1" - register "PcieRpEnable[13]" = "1" - register "PcieRpEnable[14]" = "1" - register "PcieRpEnable[15]" = "1" - - register "PcieClkSrcUsage[0]" = "0x80" - register "PcieClkSrcUsage[1]" = "7" - register "PcieClkSrcUsage[2]" = "8" - register "PcieClkSrcUsage[3]" = "0x80" - register "PcieClkSrcUsage[4]" = "0x80" - register "PcieClkSrcUsage[5]" = "0x80" - register "PcieClkSrcUsage[6]" = "0x80" - register "PcieClkSrcUsage[7]" = "0x80" - register "PcieClkSrcUsage[8]" = "0x80" - register "PcieClkSrcUsage[9]" = "0x80" - register "PcieClkSrcUsage[10]" = "0x80" - register "PcieClkSrcUsage[11]" = "0x80" - register "PcieClkSrcUsage[12]" = "0x80" - register "PcieClkSrcUsage[13]" = "0x80" - register "PcieClkSrcUsage[14]" = "0x80" - register "PcieClkSrcUsage[15]" = "0x80" - - register "PcieClkSrcClkReq[0]" = "0" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieClkSrcClkReq[4]" = "4" - register "PcieClkSrcClkReq[5]" = "5" - register "PcieClkSrcClkReq[6]" = "6" - register "PcieClkSrcClkReq[7]" = "7" - register "PcieClkSrcClkReq[8]" = "8" - register "PcieClkSrcClkReq[9]" = "9" - register "PcieClkSrcClkReq[10]" = "10" - register "PcieClkSrcClkReq[11]" = "11" - register "PcieClkSrcClkReq[12]" = "12" - register "PcieClkSrcClkReq[13]" = "13" - register "PcieClkSrcClkReq[14]" = "14" - register "PcieClkSrcClkReq[15]" = "15" - - register "SerialIoI2cMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoSkipInit, - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, - }" - - register "SerialIoGSpiMode" = "{ - [PchSerialIoIndexGSPI0] = PchSerialIoPci, - [PchSerialIoIndexGSPI1] = PchSerialIoPci, - [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, - }" - - register "SerialIoGSpiCsMode" = "{ - [PchSerialIoIndexGSPI0] = 1, - [PchSerialIoIndexGSPI1] = 1, - [PchSerialIoIndexGSPI2] = 1, - }" - - register "SerialIoGSpiCsState" = "{ - [PchSerialIoIndexGSPI0] = 0, - [PchSerialIoIndexGSPI1] = 0, - [PchSerialIoIndexGSPI2] = 0, - }" - - register "SerialIoUartMode" = "{ - [PchSerialIoIndexUART0] = PchSerialIoSkipInit, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoSkipInit, - }" - - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "GPP_G5" - - # Enable S0ix - register "s0ix_enable" = "0" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| pch_thermal_trip | PCH Trip Temperature | - #+-------------------+---------------------------+ - - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 176, - .scl_hcnt = 95, - .sda_hold = 36, - } - }, - .pch_thermal_trip = 77, - }" - - # GPIO PM programming - register "gpio_override_pm" = "1" - - # GPIO community PM configuration - register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" - register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on - chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Right"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Rear Left"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Front Left"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Right"" - register "type" = "UPC_TYPE_USB3_A" - device usb 2.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Camera"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.5 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Right"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Rear Left"" - register "type" = "UPC_TYPE_USB3_A" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Front Right"" - register "type" = "UPC_TYPE_USB3_A" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Right"" - register "type" = "UPC_TYPE_USB3_A" - device usb 3.3 on end - end - end - end - end # USB xHCI - device pci 14.2 off end # PMC SRAM - device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi wifi - end - device pci 14.5 on end # SDCard - device pci 15.0 on end # I2C #0 - device pci 15.1 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D1_IRQ)" - register "wake" = "GPE0_DW1_00" - device i2c 15 on end - end - end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 on - chip drivers/i2c/max98373 - register "vmon_slot_no" = "4" - register "imon_slot_no" = "5" - register "uid" = "0" - register "desc" = ""RIGHT SPEAKER AMP"" - register "name" = ""MAXR"" - device i2c 31 on end - end - chip drivers/i2c/max98373 - register "vmon_slot_no" = "6" - register "imon_slot_no" = "7" - register "uid" = "1" - register "desc" = ""LEFT SPEAKER AMP"" - register "name" = ""MAXL"" - device i2c 32 on end - end - end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC - device pci 1c.0 on - chip drivers/intel/wifi - register "wake" = "GPE0_DW0_06" - device pci 00.0 on end - end - end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 off end # PCI Express Port 5 x1 SLOT2/LAN - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 on - chip drivers/spi/acpi - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "compat_string" = ""google,cr50"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - device spi 0 on end - end - end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/google/dragonegg/variants/baseboard/gpio.c b/src/mainboard/google/dragonegg/variants/baseboard/gpio.c deleted file mode 100644 index b0efd00698..0000000000 --- a/src/mainboard/google/dragonegg/variants/baseboard/gpio.c +++ /dev/null @@ -1,87 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include - -/* Pad configuration in ramstage*/ -static const struct pad_config gpio_table[] = { -/* I2S2_SCLK */ PAD_CFG_GPI(GPP_A7, NONE, PLTRST), -/* I2S2_RXD */ PAD_CFG_GPI(GPP_A10, NONE, PLTRST), -/* ONBOARD_X4_PCIE_SLOT1_PWREN_N */ PAD_CFG_GPO(GPP_A14, 0, DEEP), -/* USB_OC_ODL */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), -/* WLAN_PCIE_WAKE_L */ PAD_CFG_GPI_SCI(GPP_B6, NONE, DEEP, EDGE_SINGLE, - INVERT), -/* PCH_WP_OD */ PAD_CFG_GPI(GPP_B7, UP_20K, DEEP), -/* PCH_SPI_FPMCU_F7_CS_L */ PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1), -/* PEN_INT_ODL */ PAD_CFG_GPI(GPP_C2, NONE, PLTRST), -/* GPP_C5_STRAP */ PAD_CFG_GPO(GPP_C5, 1, DEEP), -/* TCH_INT_ODL */ PAD_CFG_GPI(GPP_C10, NONE, PLTRST), -/* TCH_RST_ODL */ PAD_CFG_GPO(GPP_C11, 0, PLTRST), -/* M2_SHUTDOWN+L */ PAD_CFG_GPO(GPP_C12, 1, PLTRST), -/* M2_RESET_L */ PAD_CFG_GPO(GPP_C13, 1, PLTRST), -/* M2_INT_L */ PAD_CFG_GPI(GPP_C14, NONE, PLTRST), -/* HP_INT_L */ PAD_CFG_GPI(GPP_C15, NONE, PLTRST), -/* PCH_DEV_INT_ODL */ PAD_CFG_GPI(GPP_C22, NONE, PLTRST), -/* PCH_DEV_RESET_L */ PAD_CFG_GPO(GPP_C23, 0, PLTRST), -/* TRACKPAD_WAKE */ PAD_CFG_GPI_SCI(GPP_D0, NONE, DEEP, EDGE_SINGLE, - INVERT), -/* TRACKPAD_INT_ODL */ PAD_CFG_GPI_APIC(GPP_D1, NONE, DEEP, EDGE_SINGLE, - INVERT), -/* PCI_NVME_CLKREQ_ODL */ PAD_CFG_NF(GPP_D7, UP_20K, PWROK, NF1), -/* H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_D16, UP_20K, PLTRST, LEVEL, - INVERT), -/* GPP_E6_STRAP */ PAD_CFG_GPO(GPP_E6, 1, DEEP), -/* USB_C0_SBU_1_DC */ PAD_CFG_GPO(GPP_E22, 1, PLTRST), -/* USB_C0_SBU_2_DC */ PAD_CFG_GPO(GPP_E23, 0, DEEP), -/* CNV_RF_RESET_N */ PAD_CFG_NF(GPP_F4, DN_20K, PWROK, NF1), -/* CNV_CLKREQ0 */ PAD_CFG_NF(GPP_F5, DN_20K, PWROK, NF2), -/* SPKR_IRQ_L */ PAD_CFG_GPI_APIC(GPP_F6, NONE, DEEP, LEVEL, NONE), -/* SPKR_RST_L */ PAD_CFG_GPO(GPP_F19, 1, DEEP), -/* SD_CD# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_G5, UP_20K, DEEP), -/* SD_WP */ PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), -/* I2C3_SDA */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), -/* I2C3_SCL */ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), -/* PCH_MEM_STRAP0 */ PAD_CFG_GPI(GPP_H12, DN_20K, PLTRST), -/* PCH_MEM_STRAP1 */ PAD_CFG_GPI(GPP_H13, DN_20K, PLTRST), -/* PCH_MEM_STRAP2 */ PAD_CFG_GPI(GPP_H14, DN_20K, PLTRST), -/* PCH_MEM_STRAP3 */ PAD_CFG_GPI(GPP_H15, DN_20K, PLTRST), -/* I2S0_SCLK */ PAD_CFG_GPO(GPP_R0, 1, DEEP), -/* I2S0_SFRM */ PAD_CFG_GPO(GPP_R1, 1, DEEP), -/* I2S0_TXD */ PAD_CFG_GPO(GPP_R2, 1, DEEP), -/* I2S0_RXD */ PAD_CFG_GPI(GPP_R3, NONE, DEEP), -}; -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { -/* PCH_WP_OD */ PAD_CFG_GPI(GPP_B7, UP_20K, DEEP), -/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), -/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), -/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), -/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), -/* H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_D16, UP_20K, PLTRST, LEVEL, - INVERT), -}; - -const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -const struct pad_config *__attribute__((weak)) - variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(39, CROS_GPIO_DEVICE_NAME), -}; - -const struct cros_gpio *__attribute__((weak)) variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} diff --git a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h deleted file mode 100644 index 6471385660..0000000000 --- a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h +++ /dev/null @@ -1,69 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __BASEBOARD_EC_H__ -#define __BASEBOARD_EC_H__ - -#include -#include - -#include - - -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) - -#define MAINBOARD_EC_SMI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) - -/* EC can wake from S5 with lid or power button */ -#define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -/* - * EC can wake from S3 with lid or power button or key press or - * mode change event. - */ -#define MAINBOARD_EC_S3_WAKE_EVENTS \ - (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) - -/* Log EC wake events plus EC shutdown events */ -#define MAINBOARD_EC_LOG_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) - -/* - * ACPI related definitions for ASL code. - */ - -/* Enable EC backed ALS device in ACPI */ -#define EC_ENABLE_ALS_DEVICE - -/* Enable EC backed PD MCU device in ACPI */ -#define EC_ENABLE_PD_MCU_DEVICE - -/* Enable LID switch and provide wake pin for EC */ -#define EC_ENABLE_LID_SWITCH -#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE - -#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ -#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ -#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ - -#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h deleted file mode 100644 index fc7e94a114..0000000000 --- a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __BASEBOARD_GPIO_H__ -#define __BASEBOARD_GPIO_H__ - -#include -#include - -/* EC in RW */ -#define GPIO_EC_IN_RW GPP_B8 - -/* BIOS Flash Write Protect */ -#define GPIO_PCH_WP GPP_B7 - -/* eSPI virtual wire reporting */ -#define EC_SCI_GPI GPE0_ESPI - -/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ -#define GPE_EC_WAKE GPE0_LAN_WAK - -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_H12 -#define GPIO_MEM_CONFIG_1 GPP_H13 -#define GPIO_MEM_CONFIG_2 GPP_H14 -#define GPIO_MEM_CONFIG_3 GPP_H15 - -#endif /* BASEBOARD_GPIO_H */ diff --git a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h deleted file mode 100644 index 83f9d9583f..0000000000 --- a/src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __BASEBOARD_VARIANTS_H__ -#define __BASEBOARD_VARIANTS_H__ - -#include -#include -#include - -/* - * The next set of functions return the gpio table and fill in the number of - * entries for each table. - */ -const struct pad_config *variant_gpio_table(size_t *num); -const struct pad_config *variant_early_gpio_table(size_t *num); -const struct cros_gpio *variant_cros_gpios(size_t *num); - -struct lpddr4_config { - const void *dq_map; - size_t dq_map_size; - const void *dqs_map; - size_t dqs_map_size; - const void *rcomp_resistor; - size_t rcomp_resistor_size; - const void *rcomp_target; - size_t rcomp_target_size; -}; -void variant_memory_params(struct lpddr4_config *mem_config); -int variant_memory_sku(void); -#endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/dragonegg/variants/baseboard/memory.c b/src/mainboard/google/dragonegg/variants/baseboard/memory.c deleted file mode 100644 index adb9ba63fe..0000000000 --- a/src/mainboard/google/dragonegg/variants/baseboard/memory.c +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include - -/* DQ byte map */ -static const u8 dq_map[][12] = { - { 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, - { 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } -}; - -/* DQS CPU<>DRAM map */ -static const u8 dqs_map[][8] = { - { 0, 1, 2, 3, 4, 5, 6, 7 }, - { 0, 1, 2, 3, 5, 4, 7, 6 }, -}; - -/* Rcomp resistor */ -static const u16 rcomp_resistor[] = { 100, 100, 100 }; - -void __weak variant_memory_params(struct lpddr4_config *mem_config) -{ - /* Rcomp target */ - static const u16 rcomp_target_es0[] = { 80, 40, 40, 40, 30 }; - static const u16 rcomp_target_es1[] = { 60, 20, 20, 20, 20 }; - - mem_config->dq_map = dq_map; - mem_config->dq_map_size = sizeof(dq_map); - mem_config->dqs_map = dqs_map; - mem_config->dqs_map_size = sizeof(dqs_map); - mem_config->rcomp_resistor = rcomp_resistor; - mem_config->rcomp_resistor_size = sizeof(rcomp_resistor); - if (cpu_get_cpuid() == CPUID_ICELAKE_A0) { - mem_config->rcomp_target = rcomp_target_es0; - mem_config->rcomp_target_size = sizeof(rcomp_target_es0); - } else { - mem_config->rcomp_target = rcomp_target_es1; - mem_config->rcomp_target_size = sizeof(rcomp_target_es1); - } -} - -int __weak variant_memory_sku(void) -{ - gpio_t spd_gpios[] = { - GPIO_MEM_CONFIG_0, - GPIO_MEM_CONFIG_1, - GPIO_MEM_CONFIG_2, - GPIO_MEM_CONFIG_3, - }; - - return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); -} diff --git a/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/ec.h b/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/ec.h deleted file mode 100644 index 61288a4009..0000000000 --- a/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/ec.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __MAINBOARD_EC_H__ -#define __MAINBOARD_EC_H__ - -#include - -#endif /* __MAINBOARD_EC_H__ */ diff --git a/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/gpio.h b/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/gpio.h deleted file mode 100644 index 33ccb11351..0000000000 --- a/src/mainboard/google/dragonegg/variants/dragonegg/include/variant/gpio.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __MAINBOARD_GPIO_H__ -#define __MAINBOARD_GPIO_H__ - -#include - -#endif /* __MAINBOARD_GPIO_H__ */ From 7729b29a589ca971a3122731ffc043039813279d Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Thu, 14 May 2020 16:21:09 -0600 Subject: [PATCH 375/405] soc/intel/tigerlake: Generate PMC ACPI device at runtime In an attempt to help reduce the amount of static ASL files that are littered throughout the codebase, pmc.asl was converted to runtime SSDT generation instead. If future SoCs reuse the same PMC, then this function can be moved to soc/intel/common/block/pmc for example. TEST=Verified the following was in the decompiled SSDT: Scope (\_SB.PCI0) { Device (PMC) { Name (_HID, "INTC1026") // _HID: Hardware ID Name (_DDN, "Intel(R) Tiger Lake IPC Controller") Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xFE000000, // Address Base 0x00010000, // Address Length ) }) } } Also the following found in linux's /var/log/messages: "acpi INTC1026:00: GPIO: looking up 0 in _CRS", indicating the PMC ACPI device was found and its _CRS was locatable. Change-Id: I665c873d8a80bd503acc4a9f0241c7a6ea425e16 Signed-off-by: Tim Wawrzynczak Reviewed-by: Duncan Laurie --- src/soc/intel/tigerlake/acpi/pmc.asl | 26 ----------------- src/soc/intel/tigerlake/acpi/southbridge.asl | 3 -- src/soc/intel/tigerlake/pmc.c | 30 ++++++++++++++++++++ 3 files changed, 30 insertions(+), 29 deletions(-) delete mode 100644 src/soc/intel/tigerlake/acpi/pmc.asl diff --git a/src/soc/intel/tigerlake/acpi/pmc.asl b/src/soc/intel/tigerlake/acpi/pmc.asl deleted file mode 100644 index 1dec1f876d..0000000000 --- a/src/soc/intel/tigerlake/acpi/pmc.asl +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -Scope (\_SB.PCI0) { - - Device (PMC) - { - Name (_HID, "INTC1026") - Name (_DDN, "Intel(R) Tiger Lake IPC Controller") - /* - * PCH preserved 32 MB MMIO range from 0xFC800000 to 0xFE7FFFFF. - * 64KB (0xFE000000 - 0xFE00FFFF) for PMC MBAR. - */ - Name (_CRS, ResourceTemplate () { - Memory32Fixed (ReadWrite, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE) - }) - - /* The OS mux driver will be bound to this device node. */ - Device (MUX) - { - Name (_HID, "INTC105C") - Name (_DDN, "Intel(R) Tiger Lake North Mux-Agent") - } - } -} diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 0d303e87b7..ff683cf4f6 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -26,9 +26,6 @@ /* PCIE Ports */ #include "pcie.asl" -/* pmc 0:1f.2 */ -#include "pmc.asl" - /* Serial IO */ #include "serialio.asl" diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 62e37114f3..c24898faf3 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -6,6 +6,7 @@ * Chapter number: 4 */ +#include #include #include #include @@ -17,6 +18,8 @@ #include #include +#define PMC_HID "INTC1026" + enum pch_pmc_xtal pmc_get_xtal_freq(void) { uint8_t *const pmcbase = pmc_mmio_regs(); @@ -96,9 +99,36 @@ static void soc_pmc_read_resources(struct device *dev) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } +static void soc_pmc_fill_ssdt(const struct device *dev) +{ + acpigen_write_scope(acpi_device_scope(dev)); + acpigen_write_device(acpi_device_name(dev)); + + acpigen_write_name_string("_HID", PMC_HID); + acpigen_write_name_string("_DDN", "Intel(R) Tiger Lake IPC Controller"); + + /* + * Part of the PCH's reserved 32 MB MMIO range (0xFC800000 - 0xFE7FFFFF). + * The PMC gets 0xFE000000 - 0xFE00FFFF. + */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpigen_write_mem32fixed(1, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE); + acpigen_write_resourcetemplate_footer(); + + acpigen_pop_len(); /* PMC Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name, + dev_path(dev)); +} + struct device_operations pmc_ops = { .read_resources = soc_pmc_read_resources, .set_resources = noop_set_resources, .enable = pmc_init, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt = soc_pmc_fill_ssdt, +#endif .scan_bus = scan_static_bus, }; From ecbfa99f64c117f45dc6d1b0c50947f46daa3280 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 15 May 2020 17:01:58 -0600 Subject: [PATCH 376/405] drivers/intel/fsp2_0: add option to compress FSP-M in cbfs Allow the ability for chipset or mainboard to choose to compress FSP-M in cbfs using LZMA or LZ4 routines. However, only non-XIP platforms will support FSP-M compression. Since the main cbfs decompression paths are utilized add the appropriate checks for including compression algorithms under the FSP-M compression options. On picasso FSP-M (debug builds) the following savings were measured: no-compression: fspm.bin 720896 none FSP_COMPRESS_FSP_M_LZ4: fspm.bin 138379 LZ4 (720896 decompressed) -80% FSP_COMPRESS_FSP_M_LZMA: fspm.bin 98921 LZMA (720896 decompressed) -86% BUG=b:155322763,b:150746858,b:152909132 Change-Id: I5c88510c134b56a36ff1cd97a64b51ab2fea0ab0 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/41450 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/drivers/intel/fsp2_0/Kconfig | 13 +++ src/drivers/intel/fsp2_0/Makefile.inc | 6 + src/drivers/intel/fsp2_0/include/fsp/util.h | 2 + src/drivers/intel/fsp2_0/memory_init.c | 117 ++++++++------------ src/drivers/intel/fsp2_0/util.c | 23 ++++ src/lib/cbfs.c | 12 ++ 6 files changed, 105 insertions(+), 68 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 6c4344e472..0344116370 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -187,6 +187,19 @@ config FSP_COMPRESS_FSP_S_LZMA config FSP_COMPRESS_FSP_S_LZ4 bool +config FSP_COMPRESS_FSP_M_LZMA + bool + depends on !FSP_M_XIP + +config FSP_COMPRESS_FSP_M_LZ4 + bool + depends on !FSP_M_XIP + +config FSP_M_ADDR + hex + help + The address FSP-M will be relocated to during build time + if FSP_PEIM_TO_PEIM_INTERFACE source "src/drivers/intel/fsp2_0/ppi/Kconfig" endif diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 6c82b28d21..e954a462a1 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -52,6 +52,12 @@ $(FSP_M_CBFS)-type := fsp ifeq ($(CONFIG_FSP_M_XIP),y) $(FSP_M_CBFS)-options := --xip $(TXTIBB) endif +ifeq ($(CONFIG_FSP_COMPRESS_FSP_M_LZMA),y) +$(FSP_M_CBFS)-compression := LZMA +endif +ifeq ($(CONFIG_FSP_COMPRESS_FSP_M_LZ4),y) +$(FSP_M_CBFS)-compression := LZ4 +endif cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(FSP_S_CBFS) $(FSP_S_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_S_FILE)) diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index f531e36bee..29c393b09c 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -89,6 +89,8 @@ struct fsp_load_descriptor { int (*get_destination)(const struct fsp_load_descriptor *fspld, void **dest, size_t final_load_size, const struct region_device *source); + /* Optional argument to be utilized by get_destination() callback. */ + void *arg; }; /* Load the FSP component described by fsp_load_descriptor from cbfs. The FSP diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index ebd5213503..d90b181e78 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -254,14 +254,20 @@ static uint32_t fsp_memory_settings_version(const struct fsp_header *hdr) return ver; } -static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, - const struct memranges *memmap) +struct fspm_context { + struct fsp_header header; + struct memranges memmap; +}; + +static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake) { uint32_t status; fsp_memory_init_fn fsp_raminit; FSPM_UPD fspm_upd, *upd; FSPM_ARCH_UPD *arch_upd; uint32_t fsp_version; + const struct fsp_header *hdr = &context->header; + const struct memranges *memmap = &context->memmap; post_code(POST_MEM_PREINIT_PREP_START); @@ -323,94 +329,69 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, fsp_debug_after_memory_init(status); } -/* Load the binary into the memory specified by the info header. */ -static enum cb_err load_fspm_mem(struct fsp_header *hdr, - const struct region_device *rdev, - const struct memranges *memmap) +static int fspm_get_dest(const struct fsp_load_descriptor *fspld, void **dest, + size_t size, const struct region_device *source) { + struct fspm_context *context = fspld->arg; + struct fsp_header *hdr = &context->header; + struct memranges *memmap = &context->memmap; uintptr_t fspm_begin; uintptr_t fspm_end; - if (fsp_validate_component(hdr, rdev) != CB_SUCCESS) - return CB_ERR; + if (CONFIG(FSP_M_XIP)) { + if (fsp_validate_component(hdr, source) != CB_SUCCESS) + return -1; - fspm_begin = hdr->image_base; - fspm_end = fspm_begin + hdr->image_size; - - if (check_region_overlap(memmap, "FSPM", fspm_begin, fspm_end) != - CB_SUCCESS) - return CB_ERR; - - /* Load binary into memory at provided address. */ - if (rdev_readat(rdev, (void *)fspm_begin, 0, fspm_end - fspm_begin) < 0) - return CB_ERR; - - return CB_SUCCESS; -} - -/* Handle the case when FSPM is running XIP. */ -static enum cb_err load_fspm_xip(struct fsp_header *hdr, - const struct region_device *rdev) -{ - void *base; - - if (fsp_validate_component(hdr, rdev) != CB_SUCCESS) - return CB_ERR; - - base = rdev_mmap_full(rdev); - if ((uintptr_t)base != hdr->image_base) { - printk(BIOS_CRIT, "FSPM XIP base does not match: %p vs %p\n", - (void *)(uintptr_t)hdr->image_base, base); - return CB_ERR; + *dest = rdev_mmap_full(source); + if ((uintptr_t)*dest != hdr->image_base) { + printk(BIOS_CRIT, "FSPM XIP base does not match: %p vs %p\n", + (void *)(uintptr_t)hdr->image_base, *dest); + return -1; + } + /* Since the component is XIP it's already in the address space. + Thus, there's no need to rdev_munmap(). */ + return 0; } - /* - * Since the component is XIP it's already in the address space. Thus, - * there's no need to rdev_munmap(). - */ - return CB_SUCCESS; + /* Non XIP FSP-M uses FSP-M address */ + fspm_begin = (uintptr_t)CONFIG_FSP_M_ADDR; + fspm_end = fspm_begin + size; + + if (check_region_overlap(memmap, "FSPM", fspm_begin, fspm_end) != CB_SUCCESS) + return -1; + + *dest = (void *)fspm_begin; + + return 0; } void fsp_memory_init(bool s3wake) { - struct fsp_header hdr; - enum cb_err status; - struct cbfsf file_desc; - struct region_device file_data; - const char *name = CONFIG_FSP_M_CBFS; - struct memranges memmap; struct range_entry prog_ranges[2]; + struct fspm_context context; + struct fsp_load_descriptor fspld = { + .fsp_prog = PROG_INIT(PROG_REFCODE, CONFIG_FSP_M_CBFS), + .get_destination = fspm_get_dest, + .arg = &context, + }; + struct fsp_header *hdr = &context.header; + struct memranges *memmap = &context.memmap; elog_boot_notify(s3wake); - if (cbfs_boot_locate(&file_desc, name, NULL)) { - printk(BIOS_CRIT, "Could not locate %s in CBFS\n", name); - die("FSPM not available!\n"); - } - - cbfs_file_data(&file_data, &file_desc); - /* Build up memory map of romstage address space including CAR. */ - memranges_init_empty(&memmap, &prog_ranges[0], ARRAY_SIZE(prog_ranges)); + memranges_init_empty(memmap, &prog_ranges[0], ARRAY_SIZE(prog_ranges)); if (ENV_CACHE_AS_RAM) - memranges_insert(&memmap, (uintptr_t)_car_region_start, + memranges_insert(memmap, (uintptr_t)_car_region_start, _car_unallocated_start - _car_region_start, 0); - memranges_insert(&memmap, (uintptr_t)_program, REGION_SIZE(program), 0); + memranges_insert(memmap, (uintptr_t)_program, REGION_SIZE(program), 0); - if (!CONFIG(FSP_M_XIP)) - status = load_fspm_mem(&hdr, &file_data, &memmap); - else - status = load_fspm_xip(&hdr, &file_data); - - if (status != CB_SUCCESS) - die("Loading FSPM failed!\n"); - - /* Signal that FSP component has been loaded. */ - prog_segment_loaded(hdr.image_base, hdr.image_size, SEG_FINAL); + if (fsp_load_component(&fspld, hdr) != CB_SUCCESS) + die("FSPM not available or failed to load!\n"); timestamp_add_now(TS_BEFORE_INITRAM); - do_fsp_memory_init(&hdr, s3wake, &memmap); + do_fsp_memory_init(&context, s3wake); timestamp_add_now(TS_AFTER_INITRAM); } diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index 3b7516ab06..a00b684624 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -119,6 +119,21 @@ void fsp_handle_reset(uint32_t status) } } +static inline bool fspm_env(void) +{ + if (ENV_ROMSTAGE) + return true; + return false; +} + +static inline bool fspm_xip(void) +{ + /* FSP-M is assumed to be loaded in romstage. */ + if (fspm_env() && CONFIG(FSP_M_XIP)) + return true; + return false; +} + static void *fsp_get_dest_and_load(struct fsp_load_descriptor *fspld, size_t size, const struct region_device *source_rdev, uint32_t compression_algo) @@ -130,12 +145,20 @@ static void *fsp_get_dest_and_load(struct fsp_load_descriptor *fspld, size_t siz return NULL; } + /* Don't load when executing in place. */ + if (fspm_xip()) + return dest; + if (cbfs_load_and_decompress(source_rdev, 0, region_device_sz(source_rdev), dest, size, compression_algo) != size) { printk(BIOS_ERR, "Failed to load FSP component.\n"); return NULL; } + /* Don't allow FSP-M relocation. */ + if (fspm_env()) + return dest; + if (fsp_component_relocate((uintptr_t)dest, dest, size) < 0) { printk(BIOS_ERR, "Unable to relocate FSP component!\n"); return NULL; diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index ec5156c09c..cb66f81d99 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -99,10 +99,20 @@ static inline bool fsps_env(void) return false; } +static inline bool fspm_env(void) +{ + /* FSP-M is assumed to be loaded in romstage. */ + if (ENV_ROMSTAGE) + return true; + return false; +} + static inline bool cbfs_lz4_enabled(void) { if (fsps_env() && CONFIG(FSP_COMPRESS_FSP_S_LZ4)) return true; + if (fspm_env() && CONFIG(FSP_COMPRESS_FSP_M_LZ4)) + return true; if ((ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) && !CONFIG(COMPRESS_PRERAM_STAGES)) return false; @@ -114,6 +124,8 @@ static inline bool cbfs_lzma_enabled(void) { if (fsps_env() && CONFIG(FSP_COMPRESS_FSP_S_LZMA)) return true; + if (fspm_env() && CONFIG(FSP_COMPRESS_FSP_M_LZMA)) + return true; /* We assume here romstage and postcar are never compressed. */ if (ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) return false; From 94c2f76616f5c3da5370e770614aef3a4df51826 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 27 May 2020 23:17:10 +0200 Subject: [PATCH 377/405] soc/amd/picasso/soc_util: remove unused functions soc_is_pollock() and soc_is_picasso() aren't used by any mainboard or soc code. The same fuctionality is still provided by get_soc_type(). Change-Id: I046b4925bfeb4b31d11e2548ac87b7bbca0f6475 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/41795 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/include/soc/soc_util.h | 4 +--- src/soc/amd/picasso/soc_util.c | 10 ---------- 2 files changed, 1 insertion(+), 13 deletions(-) diff --git a/src/soc/amd/picasso/include/soc/soc_util.h b/src/soc/amd/picasso/include/soc/soc_util.h index 6399e42bb9..2459207f08 100644 --- a/src/soc/amd/picasso/include/soc/soc_util.h +++ b/src/soc/amd/picasso/include/soc/soc_util.h @@ -33,10 +33,8 @@ void print_socket_type(void); void print_silicon_type(void); void print_soc_type(void); -/* functions to determine the connectivity feature set */ -bool soc_is_pollock(void); +/* function to determine the connectivity feature set */ bool soc_is_dali(void); -bool soc_is_picasso(void); /* function to determine the iGPU type */ bool soc_is_raven2(void); diff --git a/src/soc/amd/picasso/soc_util.c b/src/soc/amd/picasso/soc_util.c index 9c256ae703..2d10cff6a1 100644 --- a/src/soc/amd/picasso/soc_util.c +++ b/src/soc/amd/picasso/soc_util.c @@ -197,21 +197,11 @@ void print_soc_type(void) } } -bool soc_is_pollock(void) -{ - return get_soc_type() == SOC_POLLOCK; -} - bool soc_is_dali(void) { return get_soc_type() == SOC_DALI; } -bool soc_is_picasso(void) -{ - return get_soc_type() == SOC_PICASSO; -} - bool soc_is_raven2(void) { return get_silicon_type() == SILICON_RV2; From 3c93b7e166bb2bcaf1bf17754194604452628c28 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 27 May 2020 23:25:38 +0200 Subject: [PATCH 378/405] soc/amd/picasso/soc_util: add comment on socket detection problems At least some Pollock engineering samples return FP5 socket type while they are in fact FT5 socket type. Change-Id: I06a19c19374532bfb367fc15c734707d8c7f65a3 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/41796 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/soc_util.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/amd/picasso/soc_util.c b/src/soc/amd/picasso/soc_util.c index 2d10cff6a1..2aa9daa2bc 100644 --- a/src/soc/amd/picasso/soc_util.c +++ b/src/soc/amd/picasso/soc_util.c @@ -12,6 +12,7 @@ #define SOCKET_TYPE_SHIFT 28 #define SOCKET_TYPSE_MASK (0xf << SOCKET_TYPE_SHIFT) +/* some Pollock engineering samples return the wrong socket type */ enum socket_type get_socket_type(void) { uint32_t ebx = cpuid_ebx(0x80000001); @@ -132,6 +133,7 @@ enum silicon_type get_silicon_type(void) return SILICON_UNKNOWN; } +/* some Pollock engineering samples return the wrong socket type and get detected as Dali */ enum soc_type get_soc_type(void) { switch (get_socket_type()) { From 90e683b3071030c7f0f56b6bd52dc3bb0d3d9578 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Thu, 14 May 2020 14:36:25 -0600 Subject: [PATCH 379/405] mb/google/volteer: Add PMC.MUX.CONx devices to devicetree for Volteer Volteer's MUX connections are known, and can now be described in ACPI tables. Port 1 has the only oddity, with SBU lines staying fixed in the CC1 orientation. TEST=Dump SSDT tables on Volteer, and confirm (coalesced for brevity): Scope (\_SB.PCI0.PMC) { Device (MUX) { Name (_HID, "INTC105C") Device (CON0) { Name (_ADR, 0) Name (_DSD, Package() { Package () { "usb2-port-number", 9 }, Package () { "usb3-port-number", 1 }, }) } Device (CON1) { Name (_ADR, 1) Name (_DSD, Package() { Package () { "usb2-port-number", 4 }, Package () { "usb3-port-number", 2 }, Package () { "sbu-orientation", "normal" }, ... } } } Change-Id: Id361b2df07e87ad72b6a59a686977b3f424e8ecf Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/41414 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/mainboard/google/volteer/Kconfig | 1 + .../volteer/variants/volteer/overridetree.cb | 21 +++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 7ed685a8e5..63e70c5fc8 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -5,6 +5,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_I2C_SX9310 + select DRIVERS_INTEL_PMC select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_SPI_ACPI select DRIVERS_SOUNDWIRE_ALC5682 diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index aa2c8fb12f..d941f5fd2f 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -21,5 +21,26 @@ chip soc/intel/tigerlake end end end + device pci 1f.2 hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/con + register "usb2_port_number" = "9" + register "usb3_port_number" = "1" + # SBU & HSL follow CC + device generic 0 on end + end + chip drivers/intel/pmc_mux/con + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 on end + end + end + end + end # PMC end end From c7854b064f7d245f8f25c95f8775c0cfd66f086f Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Mon, 18 May 2020 13:43:19 -0600 Subject: [PATCH 380/405] soc/intel/tigerlake: Implement soc_get_pmc_mux_device() The ChromeOS EC is adding new entries to its USBC.CONx devices (see later patch), and it needs to get access to the PMC.MUX device so that its ACPI path can be retrieved. This provides a weak function to return NULL for all Intel SoCs except for Tiger Lake, which locates the device if it is found in the devicetree. Change-Id: I3fe3ef25e9fac8748142f5b1bd870c9bc70b97ff Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/40948 Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- src/drivers/intel/pmc_mux/chip.h | 2 ++ .../common/block/include/intelblocks/pmc.h | 9 +++++++++ src/soc/intel/tigerlake/pmc.c | 20 +++++++++++++++++++ 3 files changed, 31 insertions(+) diff --git a/src/drivers/intel/pmc_mux/chip.h b/src/drivers/intel/pmc_mux/chip.h index dcca2a3ecc..f73a07047f 100644 --- a/src/drivers/intel/pmc_mux/chip.h +++ b/src/drivers/intel/pmc_mux/chip.h @@ -3,6 +3,8 @@ #ifndef __DRIVERS_INTEL_PMC_MUX_H__ #define __DRIVERS_INTEL_PMC_MUX_H__ +extern struct chip_operations drivers_intel_pmc_mux_ops; + struct drivers_intel_pmc_mux_config { }; diff --git a/src/soc/intel/common/block/include/intelblocks/pmc.h b/src/soc/intel/common/block/include/intelblocks/pmc.h index 329bbe9bd7..75e212740d 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmc.h +++ b/src/soc/intel/common/block/include/intelblocks/pmc.h @@ -51,4 +51,13 @@ int pmc_soc_get_resources(struct pmc_resource_config *cfg); /* API to set ACPI mode */ void pmc_set_acpi_mode(void); +/* + * Returns a reference to the PMC MUX device for the given port number. + * Returns NULL if not found or SoC does not support PMC MUX. + * + * Input: Port number (0-based) + * Output: Const pointer to PMC MUX device + */ +const struct device *soc_get_pmc_mux_device(int port_number); + #endif /* SOC_INTEL_COMMON_BLOCK_PMC_H */ diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index c24898faf3..84a18e3865 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -123,6 +124,25 @@ static void soc_pmc_fill_ssdt(const struct device *dev) dev_path(dev)); } +/* By default, TGL uses the PMC MUX for all ports, so port_number is unused */ +const struct device *soc_get_pmc_mux_device(int port_number) +{ + const struct device *pmc; + struct device *child; + + child = NULL; + pmc = pcidev_path_on_root(PCH_DEVFN_PMC); + if (!pmc || !pmc->link_list) + return NULL; + + while ((child = dev_bus_each_child(pmc->link_list, child)) != NULL) + if (child->chip_ops == &drivers_intel_pmc_mux_ops) + break; + + /* child will either be the correct device or NULL if not found */ + return child; +} + struct device_operations pmc_ops = { .read_resources = soc_pmc_read_resources, .set_resources = noop_set_resources, From 6046739b9d349d43f6d064660aaf9df49a99cc5f Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Mon, 18 May 2020 13:45:43 -0600 Subject: [PATCH 381/405] ec/google/chromeec: Add new *-switch properties to USBC.CONx devices The Linux ChromeOS EC driver now looks for 3 new properties under each USBC.CONx device contained within the ChromeOS EC device. These properties are just a reference to the device that controls the switches for USB 2/3 muxing, SBU lines, and CC lines. It uses the new function, soc_get_pmc_mux_device() to retrieve the device. Change-Id: I03cd83f9b2901b5583053fac8ab6eab64717a07d Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/40618 Reviewed-by: Duncan Laurie Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/ec/google/chromeec/ec_acpi.c | 33 ++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 7b859e95af..d87a49c88d 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -19,6 +19,14 @@ #define GOOGLE_CHROMEEC_USBC_DEVICE_HID "GOOG0014" #define GOOGLE_CHROMEEC_USBC_DEVICE_NAME "USBC" +/* Avoid adding a false dependency on an SoC or intel/common */ +extern const struct device *soc_get_pmc_mux_device(int port_number); + +__weak const struct device *soc_get_pmc_mux_device(int port_number) +{ + return NULL; +} + const char *google_chromeec_acpi_name(const struct device *dev) { /* @@ -186,6 +194,30 @@ static void add_usb_port_references(struct acpi_dp *dsd, int port_number) } } +/* + * Another helper for fill_ssdt_typec_device(). For each port, this one adds references to the + * ACPI device which control the orientation, USB data role and data muxing. + */ +static void add_switch_references(struct acpi_dp *dsd, int port_number) +{ + const struct device *dev; + const char *path; + + dev = soc_get_pmc_mux_device(port_number); + if (!dev) { + printk(BIOS_ERR, "ERROR: %s: No SOC PMC MUX device found", __func__); + return; + } + + path = acpi_device_path(dev); + if (!path) + return; + + acpi_dp_add_reference(dsd, "orientation-switch", path); + acpi_dp_add_reference(dsd, "usb-role-switch", path); + acpi_dp_add_reference(dsd, "mode-switch", path); +} + static void fill_ssdt_typec_device(const struct device *dev) { struct usb_pd_port_caps port_caps; @@ -218,6 +250,7 @@ static void fill_ssdt_typec_device(const struct device *dev) acpi_dp_add_integer(dsd, "port-number", i); add_port_caps(dsd, &port_caps); add_usb_port_references(dsd, i); + add_switch_references(dsd, i); acpi_dp_write(dsd); acpigen_pop_len(); /* Device CONx */ From 92d96e84c4f115a5b2ffdc2a20b456170b08752a Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Tue, 19 May 2020 12:38:43 -0600 Subject: [PATCH 382/405] acpi: Add new file for implementing Type-C Connector class The USB Type-C Connector Class in the Linux kernel is not specific to the ChromeOS EC, so this functionality is now split out into a separate file, acpigen_usb.c. Documentation about the kernel side is available at https://www.kernel.org/doc/html/latest/driver-api/usb/typec.html. Change-Id: Ife5b8b517b261e7c0068c862ea65039c20382c5a Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/41539 Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- src/acpi/Makefile.inc | 1 + src/acpi/acpigen_usb.c | 136 +++++++++++++++++++++++++++++++++ src/include/acpi/acpigen_usb.h | 61 +++++++++++++++ 3 files changed, 198 insertions(+) create mode 100644 src/acpi/acpigen_usb.c create mode 100644 src/include/acpi/acpigen_usb.h diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc index 5e83bc5678..ffffb860c6 100644 --- a/src/acpi/Makefile.inc +++ b/src/acpi/Makefile.inc @@ -6,6 +6,7 @@ ramstage-y += acpi.c ramstage-y += acpigen.c ramstage-y += acpigen_dsm.c ramstage-y += acpigen_ps2_keybd.c +ramstage-y += acpigen_usb.c ramstage-y += device.c ramstage-y += pld.c ramstage-y += sata.c diff --git a/src/acpi/acpigen_usb.c b/src/acpi/acpigen_usb.c new file mode 100644 index 0000000000..90a9b77c60 --- /dev/null +++ b/src/acpi/acpigen_usb.c @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +static const char *power_role_to_str(enum usb_typec_power_role power_role) +{ + switch (power_role) { + case TYPEC_POWER_ROLE_SOURCE: + return "source"; + case TYPEC_POWER_ROLE_SINK: + return "sink"; + case TYPEC_POWER_ROLE_DUAL: + return "dual"; + default: + return "unknown"; + } +} + +static const char *try_power_role_to_str(enum usb_typec_try_power_role try_power_role) +{ + switch (try_power_role) { + case TYPEC_TRY_POWER_ROLE_NONE: + /* + * This should never get returned; if there is no try-power role for a device, + * then the try-power-role field is not added to the DSD. Thus, this is just + * for completeness. + */ + return "none"; + case TYPEC_TRY_POWER_ROLE_SINK: + return "sink"; + case TYPEC_TRY_POWER_ROLE_SOURCE: + return "source"; + default: + return "unknown"; + } +} + +static const char *data_role_to_str(enum usb_typec_data_role data_role) +{ + switch (data_role) { + case TYPEC_DATA_ROLE_DFP: + return "host"; + case TYPEC_DATA_ROLE_UFP: + return "device"; + case TYPEC_DATA_ROLE_DUAL: + return "dual"; + default: + return "unknown"; + } +} + +/* Add port capabilities as DP properties */ +static void add_port_caps(struct acpi_dp *dsd, + const struct typec_connector_class_config *config) +{ + acpi_dp_add_string(dsd, "power-role", power_role_to_str(config->power_role)); + acpi_dp_add_string(dsd, "data-role", data_role_to_str(config->data_role)); + + if (config->try_power_role != TYPEC_TRY_POWER_ROLE_NONE) + acpi_dp_add_string(dsd, "try-power-role", + try_power_role_to_str(config->try_power_role)); +} + +static void add_device_ref(struct acpi_dp *dsd, + const char *prop_name, + const struct device *dev) +{ + const char *path; + char *fresh; + + if (!dev) + return; + + /* + * Unfortunately, the acpi_dp_* API doesn't write out the data immediately, thus we need + * different storage areas for all of the strings, so strdup() is used for that. It is + * safe to use strdup() here, because the strings are generated at build-time and are + * guaranteed to be NUL-terminated (they come from the devicetree). + */ + path = acpi_device_path(dev); + if (path) { + fresh = strdup(path); + if (fresh) + acpi_dp_add_reference(dsd, prop_name, fresh); + } +} + +static void add_device_references(struct acpi_dp *dsd, + const struct typec_connector_class_config *config) +{ + /* + * Add references to the USB port objects so that the consumer of this information can + * know whether the port supports USB2, USB3, and/or USB4. + */ + add_device_ref(dsd, "usb2-port", config->usb2_port); + add_device_ref(dsd, "usb3-port", config->usb3_port); + add_device_ref(dsd, "usb4-port", config->usb4_port); + + /* + * Add references to the ACPI device(s) which control the orientation, USB data role and + * data muxing. + */ + add_device_ref(dsd, "orientation-switch", config->orientation_switch); + add_device_ref(dsd, "usb-role-switch", config->usb_role_switch); + add_device_ref(dsd, "mode-switch", config->mode_switch); +} + +void acpigen_write_typec_connector(const struct typec_connector_class_config *config, + int port_number, + add_custom_dsd_property_cb add_custom_dsd_property) +{ + struct acpi_dp *dsd; + char name[5]; + + /* Create a CONx device */ + snprintf(name, sizeof(name), "CON%1X", port_number); + acpigen_write_device(name); + acpigen_write_name_integer("_ADR", port_number); + + dsd = acpi_dp_new_table("_DSD"); + + /* Write out the _DSD table */ + acpi_dp_add_integer(dsd, "port-number", port_number); + add_port_caps(dsd, config); + add_device_references(dsd, config); + + /* Allow client to add custom properties if desired */ + if (add_custom_dsd_property) + add_custom_dsd_property(dsd, port_number); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ +} diff --git a/src/include/acpi/acpigen_usb.h b/src/include/acpi/acpigen_usb.h new file mode 100644 index 0000000000..efc31f349b --- /dev/null +++ b/src/include/acpi/acpigen_usb.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef ACPI_ACPIGEN_USB_H +#define ACPI_ACPIGEN_USB_H + +enum usb_typec_power_role { + TYPEC_POWER_ROLE_SOURCE, + TYPEC_POWER_ROLE_SINK, + TYPEC_POWER_ROLE_DUAL, +}; + +enum usb_typec_try_power_role { + TYPEC_TRY_POWER_ROLE_NONE, + TYPEC_TRY_POWER_ROLE_SINK, + TYPEC_TRY_POWER_ROLE_SOURCE, +}; + +enum usb_typec_data_role { + TYPEC_DATA_ROLE_DFP, + TYPEC_DATA_ROLE_UFP, + TYPEC_DATA_ROLE_DUAL, +}; + +/** + * Configuration required to write out a Type-C Connector ACPI object. + * + * @power_role: DUAL if device supports being both a source and a sink, otherwise choose + * the device's default power role + * @try_power_role: SINK if device supports Try.SNK, SOURCE if device supports Try.SRC, + * otherwise choose NONE + * @data_role: Choose DUAL if device can alternate between UFP (host) & DFP (device), + * otherwise specify UFP or DFP. + * @usb2_port: Reference to the ACPI device that represents the USB2 signals + * @usb3_port: Reference to the ACPI device that represents the USB3 signals + * @usb4_port: Reference to the ACPI device that represents the USB4 signals + * @orientation_switch: Reference to the ACPI device that controls the switching of + * the orientation/polarity for Data and SBU lines. + * @usb_role_switch: Reference to the ACPI device that can select the USB role, + * host or device, for the USB port + * @mode_switch: Reference to the ACPI device that controls routing of data lines to + * various endpoints (xHCI, DP, etc.) on the SoC. + */ +struct typec_connector_class_config { + enum usb_typec_power_role power_role; + enum usb_typec_try_power_role try_power_role; + enum usb_typec_data_role data_role; + const struct device *usb2_port; + const struct device *usb3_port; + const struct device *usb4_port; + const struct device *orientation_switch; + const struct device *usb_role_switch; + const struct device *mode_switch; +}; + +typedef void (*add_custom_dsd_property_cb)(struct acpi_dp *dsd, int port_number); + +void acpigen_write_typec_connector(const struct typec_connector_class_config *config, + int port_number, + add_custom_dsd_property_cb add_custom_dsd_property); + +#endif /* ACPI_ACPIGEN_USB_H */ From 6da82139c3541d196c447696db4d1518c3ee2265 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Tue, 19 May 2020 12:46:04 -0600 Subject: [PATCH 383/405] ec/google/chromeec: Switch to use new acpigen_usb module Implementation of the ACPI objects for the Type-C Connector Class was added in the previous patch. This patch removes the functionality from the ChromeEC's SSDT generator, and uses acpigen_usb instead. TEST=Verified contents of SSDT are the same. Change-Id: Icdbcee1f989ee3146f7495e08fc13f9386791858 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/41540 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/ec/google/chromeec/ec_acpi.c | 220 ++++++++++--------------------- 1 file changed, 66 insertions(+), 154 deletions(-) diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index d87a49c88d..0dbaa9c456 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -1,16 +1,12 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include #include #include +#include #include #include -#include #include "chip.h" #include "ec.h" @@ -41,50 +37,50 @@ const char *google_chromeec_acpi_name(const struct device *dev) return "EC0.CREC"; } -static const char *power_role_to_str(enum ec_pd_power_role_caps power_role) +/* + * Helper for fill_ssdt_generator. This adds references to the USB + * port objects so that the consumer of this information can know + * whether the port supports USB2 and/or USB3. + */ +static void get_usb_port_references(int port_number, struct device **usb2_port, + struct device **usb3_port, struct device **usb4_port) { - switch (power_role) { - case EC_PD_POWER_ROLE_SOURCE: - return "source"; - case EC_PD_POWER_ROLE_SINK: - return "sink"; - case EC_PD_POWER_ROLE_DUAL: - return "dual"; - default: - return "unknown"; - } -} + struct drivers_usb_acpi_config *config; + struct device *port = NULL; + + /* Search through the devicetree for matching USB Type-C ports */ + while ((port = dev_find_path(port, DEVICE_PATH_USB)) != NULL) { + if (!port->enabled || port->path.type != DEVICE_PATH_USB) + continue; + + config = port->chip_info; + + /* Look at only USB Type-C ports */ + if ((config->type != UPC_TYPE_C_USB2_ONLY) && + (config->type != UPC_TYPE_C_USB2_SS_SWITCH) && + (config->type != UPC_TYPE_C_USB2_SS)) + continue; -static const char *try_power_role_to_str(enum ec_pd_try_power_role_caps try_power_role) -{ - switch (try_power_role) { - case EC_PD_TRY_POWER_ROLE_NONE: /* - * This should never get returned; if there is no try-power role for a device, - * then the try-power-role field is not added to the DSD. Thus, this is just - * for completeness. + * Check for a matching port number (the 'token' field in 'group'). Note that + * 'port_number' is 0-based, whereas the 'token' field is 1-based. */ - return "none"; - case EC_PD_TRY_POWER_ROLE_SINK: - return "sink"; - case EC_PD_TRY_POWER_ROLE_SOURCE: - return "source"; - default: - return "unknown"; - } -} + if (config->group.token != (port_number + 1)) + continue; -static const char *data_role_to_str(enum ec_pd_data_role_caps data_role) -{ - switch (data_role) { - case EC_PD_DATA_ROLE_DFP: - return "host"; - case EC_PD_DATA_ROLE_UFP: - return "device"; - case EC_PD_DATA_ROLE_DUAL: - return "dual"; - default: - return "unknown"; + switch (port->path.usb.port_type) { + case 2: + *usb2_port = port; + break; + case 3: + *usb3_port = port; + break; + case 4: + *usb4_port = port; + break; + default: + break; + } } } @@ -121,110 +117,21 @@ static const char *port_location_to_str(enum ec_pd_port_location port_location) } } -/* Add port capabilities as DP properties */ -static void add_port_caps(struct acpi_dp *dsd, const struct usb_pd_port_caps *port_caps) +static struct usb_pd_port_caps port_caps; +static void add_port_location(struct acpi_dp *dsd, int port_number) { - acpi_dp_add_string(dsd, "power-role", power_role_to_str(port_caps->power_role_cap)); - - if (port_caps->try_power_role_cap != EC_PD_TRY_POWER_ROLE_NONE) - acpi_dp_add_string(dsd, "try-power-role", - try_power_role_to_str(port_caps->try_power_role_cap)); - - acpi_dp_add_string(dsd, "data-role", data_role_to_str(port_caps->data_role_cap)); - acpi_dp_add_string(dsd, "port-location", port_location_to_str( - port_caps->port_location)); -} - -/* - * Helper for fill_ssdt_generator. This adds references to the USB - * port objects so that the consumer of this information can know - * whether the port supports USB2 and/or USB3. - */ -static void add_usb_port_references(struct acpi_dp *dsd, int port_number) -{ - static const char usb2_port[] = "usb2-port"; - static const char usb3_port[] = "usb3-port"; - struct device *port = NULL; - const char *path; - const char *usb_port_type; - struct drivers_usb_acpi_config *config; - - /* - * Unfortunately, the acpi_dp_* API doesn't write out the data immediately, thus we need - * different storage areas for all of the strings, so strdup() is used for that. It is - * safe to use strdup() here, because the strings are generated at build-time and are - * guaranteed to be NUL-terminated (they come from the devicetree). - */ - while ((port = dev_find_path(port, DEVICE_PATH_USB)) != NULL) { - if (!port->enabled || port->path.type != DEVICE_PATH_USB) - continue; - - /* Looking for USB 2 & 3 port devices only */ - if (port->path.usb.port_type == 2) - usb_port_type = usb2_port; - else if (port->path.usb.port_type == 3) - usb_port_type = usb3_port; - else - continue; - - config = port->chip_info; - - /* - * Look at only USB Type-C ports, making sure they match the - * port number we're looking for (the 'token' field in 'group'). - * Also note that 'port_number' is 0-based, whereas the 'token' - * field is 1-based. - */ - if ((config->type != UPC_TYPE_C_USB2_ONLY) && - (config->type != UPC_TYPE_C_USB2_SS_SWITCH) && - (config->type != UPC_TYPE_C_USB2_SS)) - continue; - - if (config->group.token != (port_number + 1)) - continue; - - path = acpi_device_path(port); - if (path) { - path = strdup(path); - if (!path) - continue; - - acpi_dp_add_reference(dsd, usb_port_type, path); - } - } -} - -/* - * Another helper for fill_ssdt_typec_device(). For each port, this one adds references to the - * ACPI device which control the orientation, USB data role and data muxing. - */ -static void add_switch_references(struct acpi_dp *dsd, int port_number) -{ - const struct device *dev; - const char *path; - - dev = soc_get_pmc_mux_device(port_number); - if (!dev) { - printk(BIOS_ERR, "ERROR: %s: No SOC PMC MUX device found", __func__); - return; - } - - path = acpi_device_path(dev); - if (!path) - return; - - acpi_dp_add_reference(dsd, "orientation-switch", path); - acpi_dp_add_reference(dsd, "usb-role-switch", path); - acpi_dp_add_reference(dsd, "mode-switch", path); + acpi_dp_add_string(dsd, "port-location", + port_location_to_str(port_caps.port_location)); } static void fill_ssdt_typec_device(const struct device *dev) { - struct usb_pd_port_caps port_caps; - char con_name[] = "CONx"; - struct acpi_dp *dsd; int rv; int i, num_ports; + struct device *usb2_port; + struct device *usb3_port; + struct device *usb4_port; + const struct device *mux; if (google_chromeec_get_num_pd_ports(&num_ports)) return; @@ -240,20 +147,25 @@ static void fill_ssdt_typec_device(const struct device *dev) if (rv) continue; - con_name[3] = (char)i + '0'; - acpigen_write_device(con_name); - acpigen_write_name_integer("_ADR", i); + mux = soc_get_pmc_mux_device(i); + usb2_port = NULL; + usb3_port = NULL; + usb4_port = NULL; + get_usb_port_references(i, &usb2_port, &usb3_port, &usb4_port); - /* _DSD, Device-Specific Data */ - dsd = acpi_dp_new_table("_DSD"); + struct typec_connector_class_config config = { + .power_role = port_caps.power_role_cap, + .try_power_role = port_caps.try_power_role_cap, + .data_role = port_caps.data_role_cap, + .usb2_port = usb2_port, + .usb3_port = usb3_port, + .usb4_port = usb4_port, + .orientation_switch = mux, + .usb_role_switch = mux, + .mode_switch = mux, + }; - acpi_dp_add_integer(dsd, "port-number", i); - add_port_caps(dsd, &port_caps); - add_usb_port_references(dsd, i); - add_switch_references(dsd, i); - - acpi_dp_write(dsd); - acpigen_pop_len(); /* Device CONx */ + acpigen_write_typec_connector(&config, i, add_port_location); } acpigen_pop_len(); /* Device GOOGLE_CHROMEEC_USBC_DEVICE_NAME */ From 8952d1c573eddd7a50e9e19f16232e5836b918fa Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Wed, 27 May 2020 20:18:16 -0700 Subject: [PATCH 384/405] Puff: Disable EFS1 for variants VBOOT_EC_EFS is for EFS1 and EFS1 is deprecated. Puff uses EFS2 and its variants should follow. BUG=b:157372086 BRANCH=none TEST=emerge-puff coreboot Signed-off-by: Daisuke Nojiri Change-Id: I581f137b506a96df45e5bed21833856bb4f6aaa3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41806 Tested-by: build bot (Jenkins) Reviewed-by: Sam McNally Reviewed-by: Edward O'Callaghan --- src/mainboard/google/hatch/Kconfig.name | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 7acc11d484..1194f82a3f 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -14,13 +14,11 @@ config BOARD_GOOGLE_DUFFY_LEGACY bool "-> Duffy Legacy (32MB)" select BOARD_GOOGLE_BASEBOARD_PUFF select BOARD_ROMSIZE_KB_32768 - select VBOOT_EC_EFS config BOARD_GOOGLE_DUFFY bool "-> Duffy" select BOARD_GOOGLE_BASEBOARD_PUFF select BOARD_ROMSIZE_KB_16384 - select VBOOT_EC_EFS config BOARD_GOOGLE_HATCH bool "-> Hatch" @@ -37,13 +35,11 @@ config BOARD_GOOGLE_KAISA_LEGACY bool "-> Kaisa Legacy (32MB)" select BOARD_GOOGLE_BASEBOARD_PUFF select BOARD_ROMSIZE_KB_32768 - select VBOOT_EC_EFS config BOARD_GOOGLE_KAISA bool "-> Kaisa" select BOARD_GOOGLE_BASEBOARD_PUFF select BOARD_ROMSIZE_KB_16384 - select VBOOT_EC_EFS config BOARD_GOOGLE_KOHAKU bool "-> Kohaku" From 8a017aa394f40e6712f006eda2cdfe647c7a1172 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Fri, 29 May 2020 02:48:42 +0200 Subject: [PATCH 385/405] AGESA boards: Fix typo in *OVERRIDES* in comment MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Run the command below to fix all occurrences. git grep -l OVERIDES | xargs sed -i 's/OVERIDES/OVERRIDES/g' Change-Id: I5ca237500a0ecff59203480ecc3c992991f08130 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/41856 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/mainboard/amd/inagua/OemCustomize.c | 2 +- src/mainboard/amd/olivehill/OemCustomize.c | 2 +- src/mainboard/amd/parmer/OemCustomize.c | 2 +- src/mainboard/amd/persimmon/OemCustomize.c | 2 +- src/mainboard/amd/south_station/OemCustomize.c | 2 +- src/mainboard/amd/thatcher/OemCustomize.c | 2 +- src/mainboard/amd/union_station/OemCustomize.c | 2 +- src/mainboard/asrock/e350m1/OemCustomize.c | 2 +- src/mainboard/asrock/imb-a180/OemCustomize.c | 2 +- src/mainboard/asus/am1i-a/OemCustomize.c | 2 +- src/mainboard/asus/f2a85-m/OemCustomize.c | 2 +- src/mainboard/bap/ode_e20XX/OemCustomize.c | 2 +- src/mainboard/biostar/a68n_5200/OemCustomize.c | 2 +- src/mainboard/biostar/am1ml/OemCustomize.c | 2 +- src/mainboard/elmex/pcm205400/OemCustomize.c | 2 +- src/mainboard/gizmosphere/gizmo/OemCustomize.c | 2 +- src/mainboard/gizmosphere/gizmo2/OemCustomize.c | 2 +- src/mainboard/hp/abm/OemCustomize.c | 2 +- src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c | 2 +- src/mainboard/lenovo/g505s/OemCustomize.c | 2 +- src/mainboard/lippert/frontrunner-af/OemCustomize.c | 2 +- src/mainboard/lippert/toucan-af/OemCustomize.c | 2 +- src/mainboard/msi/ms7721/OemCustomize.c | 2 +- src/mainboard/pcengines/apu1/OemCustomize.c | 2 +- 24 files changed, 24 insertions(+), 24 deletions(-) diff --git a/src/mainboard/amd/inagua/OemCustomize.c b/src/mainboard/amd/inagua/OemCustomize.c index 24790765d3..f9cf2ca3f5 100644 --- a/src/mainboard/amd/inagua/OemCustomize.c +++ b/src/mainboard/amd/inagua/OemCustomize.c @@ -77,7 +77,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERRIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ diff --git a/src/mainboard/amd/olivehill/OemCustomize.c b/src/mainboard/amd/olivehill/OemCustomize.c index 94cab514b1..18db54049e 100644 --- a/src/mainboard/amd/olivehill/OemCustomize.c +++ b/src/mainboard/amd/olivehill/OemCustomize.c @@ -98,7 +98,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERRIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ diff --git a/src/mainboard/amd/parmer/OemCustomize.c b/src/mainboard/amd/parmer/OemCustomize.c index bf23990b35..e10da6f1b7 100644 --- a/src/mainboard/amd/parmer/OemCustomize.c +++ b/src/mainboard/amd/parmer/OemCustomize.c @@ -170,7 +170,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERRIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ diff --git a/src/mainboard/amd/persimmon/OemCustomize.c b/src/mainboard/amd/persimmon/OemCustomize.c index 34acf67bd5..167a85790f 100644 --- a/src/mainboard/amd/persimmon/OemCustomize.c +++ b/src/mainboard/amd/persimmon/OemCustomize.c @@ -88,7 +88,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERRIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ diff --git a/src/mainboard/amd/south_station/OemCustomize.c b/src/mainboard/amd/south_station/OemCustomize.c index 34ce4e881e..14574f0e1c 100644 --- a/src/mainboard/amd/south_station/OemCustomize.c +++ b/src/mainboard/amd/south_station/OemCustomize.c @@ -87,7 +87,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERRIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ diff --git a/src/mainboard/amd/thatcher/OemCustomize.c b/src/mainboard/amd/thatcher/OemCustomize.c index 3faafe32cb..ec1f0ae4dc 100644 --- a/src/mainboard/amd/thatcher/OemCustomize.c +++ b/src/mainboard/amd/thatcher/OemCustomize.c @@ -170,7 +170,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERRIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ diff --git a/src/mainboard/amd/union_station/OemCustomize.c b/src/mainboard/amd/union_station/OemCustomize.c index ca7ef64fe1..16b2db2425 100644 --- a/src/mainboard/amd/union_station/OemCustomize.c +++ b/src/mainboard/amd/union_station/OemCustomize.c @@ -86,7 +86,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERRIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ diff --git a/src/mainboard/asrock/e350m1/OemCustomize.c b/src/mainboard/asrock/e350m1/OemCustomize.c index 8877e67f61..30e9f7e5c5 100644 --- a/src/mainboard/asrock/e350m1/OemCustomize.c +++ b/src/mainboard/asrock/e350m1/OemCustomize.c @@ -57,7 +57,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERRIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ diff --git a/src/mainboard/asrock/imb-a180/OemCustomize.c b/src/mainboard/asrock/imb-a180/OemCustomize.c index 26286c56a8..b1e3e88d59 100644 --- a/src/mainboard/asrock/imb-a180/OemCustomize.c +++ b/src/mainboard/asrock/imb-a180/OemCustomize.c @@ -99,7 +99,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERRIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ diff --git a/src/mainboard/asus/am1i-a/OemCustomize.c b/src/mainboard/asus/am1i-a/OemCustomize.c index 3d809cf046..6590883353 100644 --- a/src/mainboard/asus/am1i-a/OemCustomize.c +++ b/src/mainboard/asus/am1i-a/OemCustomize.c @@ -103,7 +103,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERRIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ diff --git a/src/mainboard/asus/f2a85-m/OemCustomize.c b/src/mainboard/asus/f2a85-m/OemCustomize.c index 6bb6ca2aac..930f1fcca2 100644 --- a/src/mainboard/asus/f2a85-m/OemCustomize.c +++ b/src/mainboard/asus/f2a85-m/OemCustomize.c @@ -132,7 +132,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERRIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ diff --git a/src/mainboard/bap/ode_e20XX/OemCustomize.c b/src/mainboard/bap/ode_e20XX/OemCustomize.c index fbc3e4399f..0099e1d797 100644 --- a/src/mainboard/bap/ode_e20XX/OemCustomize.c +++ b/src/mainboard/bap/ode_e20XX/OemCustomize.c @@ -84,7 +84,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERRIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ diff --git a/src/mainboard/biostar/a68n_5200/OemCustomize.c b/src/mainboard/biostar/a68n_5200/OemCustomize.c index 94cab514b1..18db54049e 100644 --- a/src/mainboard/biostar/a68n_5200/OemCustomize.c +++ b/src/mainboard/biostar/a68n_5200/OemCustomize.c @@ -98,7 +98,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERRIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ diff --git a/src/mainboard/biostar/am1ml/OemCustomize.c b/src/mainboard/biostar/am1ml/OemCustomize.c index 353050fb68..9de2813f8e 100644 --- a/src/mainboard/biostar/am1ml/OemCustomize.c +++ b/src/mainboard/biostar/am1ml/OemCustomize.c @@ -103,7 +103,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERRIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ diff --git a/src/mainboard/elmex/pcm205400/OemCustomize.c b/src/mainboard/elmex/pcm205400/OemCustomize.c index 742f2bda76..7fc9e0569d 100644 --- a/src/mainboard/elmex/pcm205400/OemCustomize.c +++ b/src/mainboard/elmex/pcm205400/OemCustomize.c @@ -87,7 +87,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERRIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ diff --git a/src/mainboard/gizmosphere/gizmo/OemCustomize.c b/src/mainboard/gizmosphere/gizmo/OemCustomize.c index 60c060e1dd..a969eea087 100644 --- a/src/mainboard/gizmosphere/gizmo/OemCustomize.c +++ b/src/mainboard/gizmosphere/gizmo/OemCustomize.c @@ -87,7 +87,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERRIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ diff --git a/src/mainboard/gizmosphere/gizmo2/OemCustomize.c b/src/mainboard/gizmosphere/gizmo2/OemCustomize.c index 6bdbc2ca07..99cf088c00 100644 --- a/src/mainboard/gizmosphere/gizmo2/OemCustomize.c +++ b/src/mainboard/gizmosphere/gizmo2/OemCustomize.c @@ -92,7 +92,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERRIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ diff --git a/src/mainboard/hp/abm/OemCustomize.c b/src/mainboard/hp/abm/OemCustomize.c index adfeec51e2..019fff2a88 100644 --- a/src/mainboard/hp/abm/OemCustomize.c +++ b/src/mainboard/hp/abm/OemCustomize.c @@ -92,7 +92,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERRIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c index 5ed4c250f2..95f2c93004 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c @@ -171,7 +171,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERRIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ diff --git a/src/mainboard/lenovo/g505s/OemCustomize.c b/src/mainboard/lenovo/g505s/OemCustomize.c index 18513cfc65..2cca51e0a5 100644 --- a/src/mainboard/lenovo/g505s/OemCustomize.c +++ b/src/mainboard/lenovo/g505s/OemCustomize.c @@ -171,7 +171,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERRIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ diff --git a/src/mainboard/lippert/frontrunner-af/OemCustomize.c b/src/mainboard/lippert/frontrunner-af/OemCustomize.c index 006c4e34e6..c1b571e713 100644 --- a/src/mainboard/lippert/frontrunner-af/OemCustomize.c +++ b/src/mainboard/lippert/frontrunner-af/OemCustomize.c @@ -87,7 +87,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERRIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ diff --git a/src/mainboard/lippert/toucan-af/OemCustomize.c b/src/mainboard/lippert/toucan-af/OemCustomize.c index 61ab5fb216..e3ffe9b39b 100644 --- a/src/mainboard/lippert/toucan-af/OemCustomize.c +++ b/src/mainboard/lippert/toucan-af/OemCustomize.c @@ -87,7 +87,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERRIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ diff --git a/src/mainboard/msi/ms7721/OemCustomize.c b/src/mainboard/msi/ms7721/OemCustomize.c index 90d6a2be81..1df5b8c7ba 100644 --- a/src/mainboard/msi/ms7721/OemCustomize.c +++ b/src/mainboard/msi/ms7721/OemCustomize.c @@ -146,7 +146,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERRIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c index 3ee675f10d..dcc81c9f8a 100644 --- a/src/mainboard/pcengines/apu1/OemCustomize.c +++ b/src/mainboard/pcengines/apu1/OemCustomize.c @@ -72,7 +72,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERRIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */ From 1a438f33ffe5482c7a995cb1b25cc70db9b1e7fa Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 22 May 2020 00:06:33 -0700 Subject: [PATCH 386/405] mb/google/hatch: Select BOARD_ROMSIZE_KB_16384 by default All hatch and puff variants use 16MiB SPI flash except the legacy ones which used 32MiB flash. Kconfig.name is updated to select BOARD_ROMSIZE_KB_32768 only for the legacy variants and BOARD_GOOGLE_HATCH_COMMON selects BOARD_ROMSIZE_KB_16384 by default if BOARD_ROMSIZE_KB_32768 is not selected. TEST=Verified using abuild --timeless that all hatch variants generate the same coreboot.rom image with and without this change. Change-Id: I708506182966936ea38562db8b0325470e34c908 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41662 Reviewed-by: Edward O'Callaghan Reviewed-by: V Sowmya Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/Kconfig | 1 + src/mainboard/google/hatch/Kconfig.name | 14 -------------- 2 files changed, 1 insertion(+), 14 deletions(-) diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 853f72b6f9..7e3b9e3948 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -15,6 +15,7 @@ config BOARD_GOOGLE_BASEBOARD_PUFF config BOARD_GOOGLE_HATCH_COMMON def_bool n + select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_DA7219 diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 1194f82a3f..c4490c601d 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -3,12 +3,10 @@ comment "Hatch" config BOARD_GOOGLE_AKEMI bool "-> Akemi" select BOARD_GOOGLE_BASEBOARD_HATCH - select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_DRATINI bool "-> Dratini" select BOARD_GOOGLE_BASEBOARD_HATCH - select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_DUFFY_LEGACY bool "-> Duffy Legacy (32MB)" @@ -18,7 +16,6 @@ config BOARD_GOOGLE_DUFFY_LEGACY config BOARD_GOOGLE_DUFFY bool "-> Duffy" select BOARD_GOOGLE_BASEBOARD_PUFF - select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_HATCH bool "-> Hatch" @@ -28,7 +25,6 @@ config BOARD_GOOGLE_HATCH config BOARD_GOOGLE_JINLON bool "-> Jinlon" select BOARD_GOOGLE_BASEBOARD_HATCH - select BOARD_ROMSIZE_KB_16384 select DRIVERS_GFX_GENERIC config BOARD_GOOGLE_KAISA_LEGACY @@ -39,42 +35,35 @@ config BOARD_GOOGLE_KAISA_LEGACY config BOARD_GOOGLE_KAISA bool "-> Kaisa" select BOARD_GOOGLE_BASEBOARD_PUFF - select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_KOHAKU bool "-> Kohaku" select BOARD_GOOGLE_BASEBOARD_HATCH - select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_KINDRED bool "-> Kindred" select BOARD_GOOGLE_BASEBOARD_HATCH - select BOARD_ROMSIZE_KB_16384 select SOC_INTEL_COMMON_MMC_OVERRIDE config BOARD_GOOGLE_HELIOS bool "-> Helios" select BOARD_GOOGLE_BASEBOARD_HATCH - select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 config BOARD_GOOGLE_MUSHU bool "-> Mushu" select BOARD_GOOGLE_BASEBOARD_HATCH - select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_PALKIA bool "-> Palkia" select BOARD_GOOGLE_BASEBOARD_HATCH - select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 config BOARD_GOOGLE_NIGHTFURY bool "-> Nightfury" select BOARD_GOOGLE_BASEBOARD_HATCH - select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_MAX98390 @@ -86,16 +75,13 @@ config BOARD_GOOGLE_PUFF config BOARD_GOOGLE_HELIOS_DISKSWAP bool "-> Helios_Diskswap" select BOARD_GOOGLE_BASEBOARD_HATCH - select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 config BOARD_GOOGLE_STRYKE bool "-> Stryke" select BOARD_GOOGLE_BASEBOARD_HATCH - select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_SUSHI bool "-> Sushi" select BOARD_GOOGLE_BASEBOARD_HATCH - select BOARD_ROMSIZE_KB_16384 From 36a67e1f3c4e06f24bf340025e39f938bac33f19 Mon Sep 17 00:00:00 2001 From: V Sowmya Date: Wed, 20 May 2020 16:44:21 +0530 Subject: [PATCH 387/405] mb/google/hatch: Select the fmd files for hatch baseboard This patch selects the fmd files based on config BOARD_GOOGLE_BASEBOARD_HATCH and also renames them to add the baseboard name and layout size tags. BUG=b:154561163 TEST=Built hatch variants and verified that they select the right fmd files. Signed-off-by: V Sowmya Change-Id: I5d99ae28cc972ffa635adf100b756c36e168a8f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41567 Tested-by: build bot (Jenkins) Reviewed-by: Maulik V Vaghela Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/Kconfig | 6 +++--- .../hatch/{chromeos-16MiB.fmd => chromeos-hatch-16MiB.fmd} | 0 .../google/hatch/{chromeos.fmd => chromeos-hatch-32MiB.fmd} | 0 3 files changed, 3 insertions(+), 3 deletions(-) rename src/mainboard/google/hatch/{chromeos-16MiB.fmd => chromeos-hatch-16MiB.fmd} (100%) rename src/mainboard/google/hatch/{chromeos.fmd => chromeos-hatch-32MiB.fmd} (100%) diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 7e3b9e3948..5f6ca70ec9 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -87,11 +87,11 @@ config DRIVER_TPM_SPI_BUS config UART_FOR_CONSOLE default 0 -if ROMSTAGE_SPD_CBFS +if BOARD_GOOGLE_BASEBOARD_HATCH config FMDFILE string - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if BOARD_ROMSIZE_KB_32768 + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-hatch-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-hatch-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 endif if ROMSTAGE_SPD_SMBUS diff --git a/src/mainboard/google/hatch/chromeos-16MiB.fmd b/src/mainboard/google/hatch/chromeos-hatch-16MiB.fmd similarity index 100% rename from src/mainboard/google/hatch/chromeos-16MiB.fmd rename to src/mainboard/google/hatch/chromeos-hatch-16MiB.fmd diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos-hatch-32MiB.fmd similarity index 100% rename from src/mainboard/google/hatch/chromeos.fmd rename to src/mainboard/google/hatch/chromeos-hatch-32MiB.fmd From 44e683d6dd4a80426eb12e5e09579d9a05ee7077 Mon Sep 17 00:00:00 2001 From: V Sowmya Date: Wed, 20 May 2020 23:07:01 +0530 Subject: [PATCH 388/405] mb/google/hatch: Select the fmd files for puff baseboard This patch selects the fmd files based on config BOARD_GOOGLE_BASEBOARD_PUFF and also renames the files to align with basebaord name and layout size. BUG=b:154561163 TEST=Built puff and verified that it selects the right fmd file. Change-Id: Ice6196ca778c6c118ce89e1510a445339a5c3455 Signed-off-by: V Sowmya Reviewed-on: https://review.coreboot.org/c/coreboot/+/41568 Tested-by: build bot (Jenkins) Reviewed-by: Sridhar Siricilla Reviewed-by: Maulik V Vaghela Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/Kconfig | 6 +++--- .../{chromeos-16MiB-spd.fmd => chromeos-puff-16MiB.fmd} | 0 .../hatch/{chromeos-spd.fmd => chromeos-puff-32MiB.fmd} | 0 3 files changed, 3 insertions(+), 3 deletions(-) rename src/mainboard/google/hatch/{chromeos-16MiB-spd.fmd => chromeos-puff-16MiB.fmd} (100%) rename src/mainboard/google/hatch/{chromeos-spd.fmd => chromeos-puff-32MiB.fmd} (100%) diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 5f6ca70ec9..b2bcabb306 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -94,11 +94,11 @@ config FMDFILE default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-hatch-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 endif -if ROMSTAGE_SPD_SMBUS +if BOARD_GOOGLE_BASEBOARD_PUFF config FMDFILE string - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB-spd.fmd" if BOARD_ROMSIZE_KB_16384 - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-spd.fmd" if BOARD_ROMSIZE_KB_32768 + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-puff-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-puff-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 endif config MAINBOARD_DIR diff --git a/src/mainboard/google/hatch/chromeos-16MiB-spd.fmd b/src/mainboard/google/hatch/chromeos-puff-16MiB.fmd similarity index 100% rename from src/mainboard/google/hatch/chromeos-16MiB-spd.fmd rename to src/mainboard/google/hatch/chromeos-puff-16MiB.fmd diff --git a/src/mainboard/google/hatch/chromeos-spd.fmd b/src/mainboard/google/hatch/chromeos-puff-32MiB.fmd similarity index 100% rename from src/mainboard/google/hatch/chromeos-spd.fmd rename to src/mainboard/google/hatch/chromeos-puff-32MiB.fmd From 0c6abd786df61072f8dd2ec738bb05a5f8375775 Mon Sep 17 00:00:00 2001 From: Marco Chen Date: Thu, 28 May 2020 13:54:39 +0800 Subject: [PATCH 389/405] mb/google/dedede: add new SPD SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16 The first DRAM part supported by SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16 is NT6AP256T32AV-J2 so the SPD content is generally extracted from it's SPD. On the other hand, SPD bytes 4 / 6 / 13 were amended to follow SoC's requirement. BUG=b:152277273 BRANCH=None TEST=build the image successfully. Change-Id: If6fb0855a961d1c68315a727466bf45569cf2597 Signed-off-by: Marco Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/41813 Reviewed-by: Furquan Shaikh Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- ...SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16.spd.hex | 32 +++++++++++++++++++ .../dedede/variants/waddledee/Makefile.inc | 2 +- 2 files changed, 33 insertions(+), 1 deletion(-) create mode 100644 src/mainboard/google/dedede/spd/SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16.spd.hex diff --git a/src/mainboard/google/dedede/spd/SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16.spd.hex b/src/mainboard/google/dedede/spd/SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16.spd.hex new file mode 100644 index 0000000000..ab171f2952 --- /dev/null +++ b/src/mainboard/google/dedede/spd/SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 14 19 90 08 00 00 00 00 02 22 00 00 +00 00 05 0A 80 54 01 00 89 00 90 A8 90 A0 05 D0 +02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 FB 00 A6 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc index aaa65e2a2a..1813377292 100644 --- a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc @@ -1,7 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later SPD_SOURCES = SPD_LPDDR4X_200b_8Gb_4267_DDP_1x16 #0b0000 -SPD_SOURCES += empty #0b0001 +SPD_SOURCES += SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16 #0b0001 romstage-y += memory.c From c6d89fba7a404684110a792a78dae86ec44b0738 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 28 May 2020 11:21:26 -0700 Subject: [PATCH 390/405] soc/amd/picasso: Relocate FSP-M to address in DRAM On Picasso, DRAM is up by the time FSP-M runs. This change relocates FSP-M binary to a specific address (0x90000000) in DRAM. Currently, this address is randomly chosen to ensure it does not overlap any of the other stages. Once we have a unified memory map set up for Picasso, this address can be updated along with it. BUG=b:155322763,b:150746858,b:152909132 Change-Id: I1a49765f00de9f97fa3dbd5bc288a3ed0d7087f6 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41828 Reviewed-by: Aaron Durbin Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Kconfig | 4 ++++ src/soc/amd/picasso/Makefile.inc | 2 ++ 2 files changed, 6 insertions(+) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index ddbc6c3137..bfa029b2d2 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -228,6 +228,10 @@ config MAINBOARD_POWER_RESTORE return to S0. Otherwise the system will remain in S5 once power is restored. +config FSP_M_ADDR + hex + default 0x90000000 + config X86_RESET_VECTOR hex default 0x807fff0 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index d0046eaf10..d62ccda74d 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -458,4 +458,6 @@ apu/amdfw-type := raw endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) +$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) + endif # ($(CONFIG_SOC_AMD_PICASSO),y) From c3063c556702defc0401d7d82280ee20af8300d0 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 28 May 2020 11:58:20 -0700 Subject: [PATCH 391/405] soc/amd/picasso: Enable FSP compression This change enables LZMA compression for both FSP-M and FSP-S. This results in significant savings in the FSP size in each CBFS: cbfstool firmware/image-trembyle.bin print -r COREBOOT | grep fsp fspm.bin 0x9cdc0 fsp 132404 LZMA (720896 decompressed) fsps.bin 0xbdfc0 fsp 86146 LZMA (327680 decompressed) LZ4 works too, but the savings are smaller as compared to LZMA: cbfstool firmware/image-trembyle.bin print -r COREBOOT | grep fsp fspm.bin 0x9cdc0 fsp 189530 LZ4 (720896 decompressed) fsps.bin 0xcbfc0 fsp 118952 LZ4 (327680 decompressed) BUG=b:155322763,b:150746858,b:152909132 TEST=Verified that Trembyle boots to OS. No FSP-M or FSP-S errors in boot logs. Signed-off-by: Furquan Shaikh Change-Id: Ie5e4d58e671e936aa525d3000f890e9e5ae45ec3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41830 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Raul Rangel --- src/soc/amd/picasso/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index bfa029b2d2..e3d145d80f 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -49,6 +49,8 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select RTC select PLATFORM_USES_FSP2_0 + select FSP_COMPRESS_FSP_M_LZMA + select FSP_COMPRESS_FSP_S_LZMA select FSP_USES_CB_STACK select UDK_2017_BINDING select CACHE_MRC_SETTINGS From 11217de375598c7a6f6288d0bc04dec115e41df5 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Thu, 21 May 2020 10:39:58 -0700 Subject: [PATCH 392/405] fit: Swap compat matching priorities for board-revX and board-skuY Matching the same behavior change in depthcharge's FIT image code (CL:2212466), this patch changes the order in which compat strings involving revision and SKU numbers are matched when looking for a compatible device tree. The most precise match (board-revX-skuY) is still the highest priority, but after that we will now first check for revision only (board-revX) and then for SKU only (board-skuY). The reason for this is that SKU differentiation is often added later to a project, so device trees for earlier revisions may not have SKU numbers defined. So if we have a rev0 board (with sku0 as the "default SKU", because the board only started having different SKUs with rev1) we want it to match the board-rev0 device tree, not board-sku0 which was added as an alias to board-rev1-sku0 to provide the best known default for potential later revisions of that SKU. Signed-off-by: Julius Werner Change-Id: Ia3cf7cbb165170e2ab0bba633fec01f9f509b874 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41633 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/lib/fit.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/lib/fit.c b/src/lib/fit.c index 90cbfcacee..748cd611a4 100644 --- a/src/lib/fit.c +++ b/src/lib/fit.c @@ -50,14 +50,6 @@ static void fit_add_default_compat_strings(void) fit_add_compat_string(compat_string); } - if (sku_id() != UNDEFINED_STRAPPING_ID) { - snprintf(compat_string, sizeof(compat_string), "%s,%s-sku%u", - CONFIG_MAINBOARD_VENDOR, CONFIG_MAINBOARD_PART_NUMBER, - sku_id()); - - fit_add_compat_string(compat_string); - } - if (board_id() != UNDEFINED_STRAPPING_ID) { snprintf(compat_string, sizeof(compat_string), "%s,%s-rev%u", CONFIG_MAINBOARD_VENDOR, CONFIG_MAINBOARD_PART_NUMBER, @@ -66,6 +58,14 @@ static void fit_add_default_compat_strings(void) fit_add_compat_string(compat_string); } + if (sku_id() != UNDEFINED_STRAPPING_ID) { + snprintf(compat_string, sizeof(compat_string), "%s,%s-sku%u", + CONFIG_MAINBOARD_VENDOR, CONFIG_MAINBOARD_PART_NUMBER, + sku_id()); + + fit_add_compat_string(compat_string); + } + snprintf(compat_string, sizeof(compat_string), "%s,%s", CONFIG_MAINBOARD_VENDOR, CONFIG_MAINBOARD_PART_NUMBER); From 74b1919f1779a3a3b1a0320482784bb31234b175 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Thu, 28 May 2020 10:00:16 +0530 Subject: [PATCH 393/405] mb/google/dedede: Enable Heci1 device Enable heci1 device from devicetree for PCI enumeration. This is required for ME status dump using HFSTSx resgisters in PCI config space. Heci1 device is later disabled through heci disable flow. TEST=Build, boot waddledoo. ME status dump is seen in console logs. Signed-off-by: Aamir Bohra Change-Id: Icb77db3f0666c2d14ebef2c3214564346d1fd3c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41807 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 1b42dfb81a..fc4397689e 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -258,7 +258,7 @@ chip soc/intel/jasperlake device pci 15.1 on end # I2C 1 device pci 15.2 on end # I2C 2 device pci 15.3 on end # I2C 3 - device pci 16.0 off end # HECI 1 + device pci 16.0 on end # HECI 1 device pci 16.1 off end # HECI 2 device pci 16.4 off end # HECI 3 device pci 16.5 off end # HECI 4 From 23e8b5b4949063319c339120f13e392a90493b58 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Wed, 27 May 2020 23:11:19 -0700 Subject: [PATCH 394/405] soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En Determine the TcssDma0 and TcssDma1 enabling based on TBT DMA controllers setting. BUG=:b:146624360 TEST=Booted on Volteer and verified TcssDma0 and TcssDma1 enabling. lspci shows TcssDma0(0d.2) and TcssDma1(0d.3). Signed-off-by: John Zhao Change-Id: I61ac4131481374e9a2a34d1a30f822046c3897fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/41812 Reviewed-by: Wonkyu Kim Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/chip.h | 4 ---- src/soc/intel/tigerlake/romstage/fsp_params.c | 13 +++++++++++-- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 5892829ef4..ed09aaa936 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -216,10 +216,6 @@ struct soc_intel_tigerlake_config { uint8_t TcssXhciEn; uint8_t TcssXdciEn; - /* TCSS DMA */ - uint8_t TcssDma0En; - uint8_t TcssDma1En; - /* * IOM Port Config * If a port orientation needs to be controlled by the SOC this setting must be diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index ede5059a5e..f7956c80be 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -116,8 +116,17 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->TcssXdciEn = config->TcssXdciEn; /* TCSS DMA */ - m_cfg->TcssDma0En = config->TcssDma0En; - m_cfg->TcssDma1En = config->TcssDma1En; + dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA0); + if (dev) + m_cfg->TcssDma0En = dev->enabled; + else + m_cfg->TcssDma0En = 0; + + dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA1); + if (dev) + m_cfg->TcssDma1En = dev->enabled; + else + m_cfg->TcssDma1En = 0; /* USB4/TBT */ dev = pcidev_path_on_root(SA_DEVFN_TBT0); From 5694342a8136e85fe474c09e425d0476d9fc4d2b Mon Sep 17 00:00:00 2001 From: Jan Dabros Date: Tue, 26 May 2020 15:05:00 +0200 Subject: [PATCH 395/405] Documentation/tutorial: Add tutorial for writing unit tests Signed-off-by: Jan Dabros Change-Id: I1ebd2786a49ec8bc25e209d67ecc4c94b475442d Reviewed-on: https://review.coreboot.org/c/coreboot/+/41727 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg Reviewed-by: Patrick Georgi --- .../2020-03-unit-testing-coreboot.md | 39 +- Documentation/tutorial/index.md | 1 + Documentation/tutorial/part3.md | 384 ++++++++++++++++++ 3 files changed, 387 insertions(+), 37 deletions(-) create mode 100644 Documentation/tutorial/part3.md diff --git a/Documentation/technotes/2020-03-unit-testing-coreboot.md b/Documentation/technotes/2020-03-unit-testing-coreboot.md index 0d1d8ece49..02c2e30ee0 100644 --- a/Documentation/technotes/2020-03-unit-testing-coreboot.md +++ b/Documentation/technotes/2020-03-unit-testing-coreboot.md @@ -279,41 +279,6 @@ tests/lib/string-test and tests/device/i2c-test: ├── i2c.o ``` -### Adding new tests -For purpose of this description, let's assume that we want to add a new unit test -for src/device/i2c.c module. Since this module is rather simple, it will be enough -to have only one test module. - -Firstly (assuming there is no tests/device/Makefile.inc file) we need to create -Makefile.inc in main unit test module directory. Inside this Makefile.inc, one -need to register new test and can specify multiple different attributes for it. - -```bash -# Register new test, by adding its name to tests variable -tests-y += i2c-test - -# All attributes are defined by - variables -# -srcs is used to register all input files (test harness, unit under -# test and others) for this particular test. Remember to add relative paths. -i2c-test-srcs += tests/device/i2c-test.c -i2c-test-srcs += src/device/i2c.c - -# We can define extra cflags for this particular test -i2c-test-cflags += -DSOME_DEFINE=1 - -# For mocking out external dependencies (functions which cannot be resolved by -# linker), it is possible to register a mock function. To register new mock, it -# is enough to add function-to-be-mocked name to -mocks variable. -i2c-test-mocks += platform_i2c_transfer - -# Similar to coreboot concept, unit tests also runs in the context of stages. -# By default all unit tests are compiled to be ramstage executables. If one want -# to overwrite this setting, there is -stage variable available. -i2c-test-stage:= bootblock -``` - ### Writing new tests -Full description of how to write unit tests and Cmocka API description is out of -the scope of this document. There are other documents related to this -[Cmocka API](https://api.cmocka.org/) and -[Mocks](https://lwn.net/Articles/558106/). +Our tutorial series has [detailed guidelines](../tutorial/part3.md) for writing +unit tests. diff --git a/Documentation/tutorial/index.md b/Documentation/tutorial/index.md index 48dfbe5da6..b8fb82737d 100644 --- a/Documentation/tutorial/index.md +++ b/Documentation/tutorial/index.md @@ -2,3 +2,4 @@ * [Part 1: Starting from scratch](part1.md) * [Part 2: Submitting a patch to coreboot.org](part2.md) +* [Part 3: Writing unit tests](part3.md) diff --git a/Documentation/tutorial/part3.md b/Documentation/tutorial/part3.md new file mode 100644 index 0000000000..7ccee87754 --- /dev/null +++ b/Documentation/tutorial/part3.md @@ -0,0 +1,384 @@ +# Writing unit tests for coreboot + +## Introduction +General thoughts about unit testing coreboot can be found in +[Unit testing coreboot](../technotes/2020-03-unit-testing-coreboot.md). + +This document aims to guide developers through the process of adding and writing +unit tests for coreboot modules. + +As an example of unit under test, `src/device/i2c.c` (referred hereafter as UUT +"Unit Under Test") will be used. This is simple module, thus it should be easy +for the reader to focus solely on the testing logic, without the need to spend +too much time on digging deeply into the source code details and flow of +operations. That being said, a good understanding of what the unit under test is +doing is crucial for writing unit tests. + +This tutorial should also be helpful for developers who want to follow +[TDD](https://en.wikipedia.org/wiki/Test-driven_development). Even though TDD +has a different work flow of building tests first, followed by the code that +satisfies them, the process of writing tests and adding them to the tree is the +same. + +## Analysis of unit under test +First of all, it is necessary to precisely establish what we want to test in a +particular module. Usually this will be an externally exposed API, which can be +used by other modules. + +```eval_rst +.. admonition:: i2c-test example + + In case of our UUT, API consist of two methods: + + .. code-block:: c + + int i2c_read_field(unsigned int bus, uint8_t chip, uint8_t reg, uint8_t *data, + uint8_t mask, uint8_t shift) + int i2c_write_field(unsigned int bus, uint8_t chip, uint8_t reg, uint8_t data, + uint8_t mask, uint8_t shift) + + For sake of simplicity, let's focus on `i2c_read_field` in this document. +``` + +Once the API is defined, the next question is __what__ this API is doing (or +what it will be doing in case of TDD). In other words, what outputs we are +expecting from particular functions, when providing particular input parameters. + +```eval_rst +.. admonition:: i2c-test example + + .. code-block:: c + + int i2c_read_field(unsigned int bus, uint8_t chip, uint8_t reg, uint8_t *data, + uint8_t mask, uint8_t shift) + + This is a method which means to read content of register `reg` from i2c device + on i2c `bus` and slave address `chip`, applying bit `mask` and offset `shift` + to it. Returned data should be placed in `data`. +``` + +The next step is to determine all external dependencies of UUT in order to mock +them out. Usually we want to isolate the UUT as much as possible, so that the +test result depends __only__ on the behavior of UUT and not on the other +modules. While some software dependencies may be hard to be mock (for example +due to complicated dependencies) and thus should be simply linked into the test +binaries, all hardware dependencies need to be mocked out, since in the +user-space host environment, targets hardware is not available. + +```eval_rst +.. admonition:: i2c-test example + + `i2c_read_field` is calling `i2c_readb`, which eventually invokes + `i2c_transfer`. This method simply calls `platform_i2c_transfer`. The last + function in the chain is a hardware-touching one, and defined separately for + different SOCs. It is responsible for issuing transactions on the i2c bus. + For the purpose of writing unit test, we should mock this function. +``` + +## Adding new tests +In order to keep the tree clean, the `tests/` directory should mimic the `src/` +directory, so that test harness code is placed in a location corresponding to +UUT. Furthermore, the naming convention is to add the suffix `-test` to the UUT +name when creating a new test harness file. + +```eval_rst +.. admonition:: i2c-test example + + Considering that UUT is `src/device/i2c.c`, test file should be named + `tests/device/i2c-test.c`. When adding a new test file, it needs to be + registered with the coreboot unit testing infrastructure. +``` + +Every directory under `tests/` should contain a Makefile.inc, similar to what +can be seen under the `src/`. Register a new test in Makefile.inc, by +__appending__ test name to the `tests-y` variable. + +```eval_rst +.. admonition:: i2c-test example + + .. code-block:: c + + tests-y += i2c-test +``` + +Next step is to list all source files, which should be linked together in order +to create test binary. Usually a tests requires only two files - UUT and test +harness code, but sometimes more is needed to provide the test environment. +Source files are registered in `-srcs` variable. + +```eval_rst +.. admonition:: i2c-test example + + .. code-block:: c + + i2c-test-srcs += tests/device/i2c-test.c + i2c-test-srcs += src/device/i2c.c +``` + +Above minimal configuration is a basis for further work. One can try to build +and run test binary either by invoking `make tests//` or by +running all unit tests (whole suite) for coreboot `make unit-tests`. + +```eval_rst +.. admonition:: i2c-test example + + .. code-block:: c + + make tests/device/i2c-test + + or + + .. code-block:: c + + make unit-tests +``` + +When trying to build test binary, one can often see linker complains about +`undefined reference` to couple of symbols. This is one of solutions to +determine all external dependencies of UUT - iteratively build test and resolve +errors one by one. At this step, developer should decide either it's better to +add an extra module to provide necessary definitions or rather mock such +dependency. Quick guide through adding mocks is provided later in this doc. + +## Writing new tests +In coreboot, [Cmocka](https://cmocka.org/) is used as unit test framework. The +project has exhaustive [API documentation](https://api.cmocka.org/). Let's see +how we may incorporate it when writing tests. + +### Assertions +Testing the UUT consists of calling the functions in the UUT and comparing the +returned values to the expected values. Cmocka implements +[a set of assert macros](https://api.cmocka.org/group__cmocka__asserts.html) to +compare a value with an expected value. If the two values do not match, the test +fails with an error message. + +```eval_rst +.. admonition:: i2c-test example + + In our example, the simplest test is to call UUT for reading our fake devices + registers and do all calculation in the test harness itself. At the end, let's + compare integers with `assert_int_equal`. + + .. code-block:: c + + #define MASK 0x3 + #define SHIFT 0x1 + + static void i2c_read_field_test(void **state) + { + int bus, slave, reg; + int i, j; + uint8_t buf; + + mock_expect_params_platform_i2c_transfer(); + + /* Read particular bits in all registers in all devices, then compare + with expected value. */ + for (i = 0; i < ARRAY_SIZE(i2c_ex_devs); i++) + for (j = 0; j < ARRAY_SIZE(i2c_ex_devs[0].regs); j++) { + i2c_read_field(i2c_ex_devs[i].bus, + i2c_ex_devs[i].slave, + i2c_ex_devs[i].regs[j].reg, + &buf, MASK, SHIFT); + assert_int_equal((i2c_ex_devs[i].regs[j].data & + (MASK << SHIFT)) >> SHIFT, buf); + }; + } +``` + +### Mocks + +#### Overview +Many coreboot modules are low level software that touch hardware directly. +Because of this, one of the most important and challenging part of +writing tests is to design and implement mocks. A mock is a software component +which implements the API of another component so that the test can verify that +certain functions are called (or not called), verify the parameters passed to +those functions, and specify the return values from those functions. Mocks are +especially useful when the API to be implemented is one that accesses hardware +components. + +When writing a mock, the developer implements the same API as the module being +mocked. Such a mock may, for example, register a set of driver methods. Behind +this API, there is usually a simulation of real hardware. + +```eval_rst +.. admonition:: i2c-test example + + For purpose of our i2c test, we may introduce two i2c devices with set of + registers, which simply are structs in memory. + + .. code-block:: c + + /* Simulate two i2c devices, both on bus 0, each with three uint8_t regs + implemented. */ + typedef struct { + uint8_t reg; + uint8_t data; + } i2c_ex_regs_t; + + typedef struct { + unsigned int bus; + uint8_t slave; + i2c_ex_regs_t regs[3]; + } i2c_ex_devs_t; + + i2c_ex_devs_t i2c_ex_devs[] = { + {.bus = 0, .slave = 0xA, .regs = { + {.reg = 0x0, .data = 0xB}, + {.reg = 0x1, .data = 0x6}, + {.reg = 0x2, .data = 0xF}, + } }, + {.bus = 0, .slave = 0x3, .regs = { + {.reg = 0x0, .data = 0xDE}, + {.reg = 0x1, .data = 0xAD}, + {.reg = 0x2, .data = 0xBE}, + } }, + }; + + These fake devices will be accessed instead of hardware ones: + + .. code-block:: c + + reg = tmp->buf[0]; + + /* Find object for requested device */ + for (i = 0; i < ARRAY_SIZE(i2c_ex_devs); i++, i2c_dev++) + if (i2c_ex_devs[i].slave == tmp->slave) { + i2c_dev = &i2c_ex_devs[i]; + break; + } + + if (i2c_dev == NULL) + return -1; + + /* Write commands */ + if (tmp->len > 1) { + i2c_dev->regs[reg].data = tmp->buf[1]; + }; + + /* Read commands */ + for (i = 0; i < count; i++, tmp++) + if (tmp->flags & I2C_M_RD) { + *(tmp->buf) = i2c_dev->regs[reg].data; + }; +``` + +Cmocka uses a feature that gcc provides for breaking dependencies at the link +time. It is possible to override implementation of some function, with the +method from test harness. This allows test harness to take control of execution +from binary (during the execution of test), and stimulate UUT as required +without changing the source code. + +coreboot unit test infrastructure supports overriding of functions at link time. +This is as simple as adding a `name_of_function` to be mocked into +-mocks variable in Makefile.inc. The result is that every time the +function is called, `wrap_name_of_function` will be called instead. + +```eval_rst +.. admonition:: i2c-test example + + .. code-block:: c + + i2c-test-mocks += platform_i2c_transfer + + Now, dev can write own implementation of `platform_i2c_transfer` and define it + as `wrap_platform_i2c_transfer`. This implementation instead of accessing real + i2c bus, will write/read from fake structs. + + .. code-block:: c + + int __wrap_platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, + int count) + { + } +``` + +#### Checking mock's arguments +A test can verify the parameters provided by the UUT to the mock function. The +developer may also verify that number of calls to mock is correct and the order +of calls to particular mocks is as expected (See +[this](https://api.cmocka.org/group__cmocka__call__order.html)). The Cmocka +macros for checking parameters are described +[here](https://api.cmocka.org/group__cmocka__param.html). In general, in mock +function, one makes a call to `check_expected()` and in the +corresponding test function, `expect*()` macro, with description which parameter +in which mock should have particular value, or be inside a described range. + +```eval_rst +.. admonition:: i2c-test example + + In our example, we may want to check that `platform_i2c_transfer` is fed with + number of segments bigger than 0, each segment has flags which are in + supported range and each segment has buf which is non-NULL. We are expecting + such values for _every_ call, thus the last parameter in `expect*` macros is + -1. + + .. code-block:: c + + static void mock_expect_params_platform_i2c_transfer(void) + { + unsigned long int expected_flags[] = {0, I2C_M_RD, I2C_M_TEN, + I2C_M_RECV_LEN, I2C_M_NOSTART}; + + /* Flags should always be only within supported range */ + expect_in_set_count(__wrap_platform_i2c_transfer, segments->flags, + expected_flags, -1); + + expect_not_value_count(__wrap_platform_i2c_transfer, segments->buf, + NULL, -1); + + expect_in_range_count(__wrap_platform_i2c_transfer, count, 1, INT_MAX, + -1); + } + + And the checks below should be added to our mock + + .. code-block:: c + + check_expected(count); + + for (i = 0; i < count; i++, segments++) { + check_expected_ptr(segments->buf); + check_expected(segments->flags); + } +``` + +#### Instrument mocks +It is possible for the test function to instrument what the mock will return to +the UUT. This can be done by using the `will_return*()` and `mock()` macros. +These are described in +[the Mock Object section](https://api.cmocka.org/group__cmocka__mock.html) of +the Cmocka API documentation. + +```eval_rst +.. admonition:: Example + + There is an non-coreboot example for using Cmocka available + `here `_. +``` + +### Test runner +Finally, the developer needs to implement the test `main()` function. All tests +should be registered there and cmocka test runner invoked. All methods for +invoking Cmocka test are described +[here](https://api.cmocka.org/group__cmocka__exec.html). + +```eval_rst +.. admonition:: i2c-test example + + We don't need any extra setup and teardown functions for i2c-test, so let's + simply register test for `i2c_read_field` and return from main value which is + output of Cmocka's runner (it returns number of tests that failed). + + .. code-block:: c + + int main(void) + { + const struct CMUnitTest tests[] = { + cmocka_unit_test(i2c_read_field_test), + }; + + return cmocka_run_group_tests(tests, NULL, NULL); + } +``` From 03a05b47e06392e028dbdb73900219d45084b2fd Mon Sep 17 00:00:00 2001 From: Venkata Krishna Nimmagadda Date: Wed, 27 May 2020 14:20:21 -0700 Subject: [PATCH 396/405] soc/intel/tigerlake/acpi: Update camera_clock_ctl.asl to ASL2.0 This change updates camera_clock_ctl.asl to use ASL2.0 syntax. This increases the readability of the ASL code. BUG=none BRANCH=none TEST="BUILD for volteer" Signed-off-by: Venkata Krishna Nimmagadda Change-Id: I6370e4b268331bfba5bc0392f27c560836b6ea72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41798 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Subrata Banik --- src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl b/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl index 3d31502526..f9f48bf04a 100644 --- a/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl +++ b/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl @@ -11,8 +11,7 @@ Scope (\_SB.PCI0) { /* IsCLK PCH base register for clock settings */ Name (ICKB, 0) - Store (PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1, ICKB) - + ICKB = PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1 /* * Arg0 : Clock Number * Return : Offset of register to control the clock in Arg0 From fc3eb1ca1d07b0c864e0f7f6c51c40c5977d4dd3 Mon Sep 17 00:00:00 2001 From: Venkata Krishna Nimmagadda Date: Wed, 27 May 2020 14:26:03 -0700 Subject: [PATCH 397/405] soc/intel/tigerlake/acpi: Update pch_hda.asl to ASL2.0 syntax This change updates pch_hda.asl to use ASL2.0 syntax. This increases the readability of the ASL code. BUG=none BRANCH=none TEST="BUILD for Volteer" Signed-off-by: Venkata Krishna Nimmagadda Change-Id: Ia2bab6dcbac9eae76ac4258c44bb19425c8b5c80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41799 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Subrata Banik --- src/soc/intel/tigerlake/acpi/pch_hda.asl | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/src/soc/intel/tigerlake/acpi/pch_hda.asl b/src/soc/intel/tigerlake/acpi/pch_hda.asl index f292901b05..08fce8c1f1 100644 --- a/src/soc/intel/tigerlake/acpi/pch_hda.asl +++ b/src/soc/intel/tigerlake/acpi/pch_hda.asl @@ -26,19 +26,17 @@ Device (HDAS) */ Method (_DSM, 4) { - If (LEqual (Arg0, ^UUID)) { + If (Arg0 == ^UUID) { /* * Function 0: Function Support Query * Returns a bitmask of functions supported. */ - If (LEqual (Arg2, Zero)) { + If (Arg2 == 0) { /* * NHLT Query only supported for revision 1 and * if NHLT address and length are set in NVS. */ - If (LAnd (LEqual (Arg1, One), - LAnd (LNotEqual (NHLA, Zero), - LNotEqual (NHLL, Zero)))) { + If ((Arg1 == 1) && (NHLA != 0) && (NHLL != 0)) { Return (Buffer (One) { 0x03 }) } Else { Return (Buffer (One) { 0x01 }) @@ -57,9 +55,9 @@ Device (HDAS) CreateQWordField (NBUF, ^NHLT._MAX, NMAS) CreateQWordField (NBUF, ^NHLT._LEN, NLEN) - Store (NHLA, NBAS) - Store (NHLA, NMAS) - Store (NHLL, NLEN) + NBAS = NHLA + NMAS = NHLA + NLEN = NHLL Return (NBUF) } From a81be27dc535f5177cf97ddd88458fa3946c125d Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Fri, 29 May 2020 14:13:08 +1000 Subject: [PATCH 398/405] mb/google/hatch: Add Noibat variant A verbatim copy of variants/puff. BUG=b:156429564 BRANCH=none TEST=none Change-Id: I8c76d468177e1f3fcab53e0790599041b1a944d8 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/41851 Reviewed-by: Sam McNally Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/Kconfig | 2 + src/mainboard/google/hatch/Kconfig.name | 4 + .../google/hatch/variants/noibat/Makefile.inc | 5 + .../google/hatch/variants/noibat/gpio.c | 115 +++++ .../noibat/include/variant/acpi/dptf.asl | 114 +++++ .../variants/noibat/include/variant/ec.h | 59 +++ .../variants/noibat/include/variant/gpio.h | 8 + .../google/hatch/variants/noibat/mainboard.c | 143 +++++++ .../hatch/variants/noibat/overridetree.cb | 392 ++++++++++++++++++ 9 files changed, 842 insertions(+) create mode 100644 src/mainboard/google/hatch/variants/noibat/Makefile.inc create mode 100644 src/mainboard/google/hatch/variants/noibat/gpio.c create mode 100644 src/mainboard/google/hatch/variants/noibat/include/variant/acpi/dptf.asl create mode 100644 src/mainboard/google/hatch/variants/noibat/include/variant/ec.h create mode 100644 src/mainboard/google/hatch/variants/noibat/include/variant/gpio.h create mode 100644 src/mainboard/google/hatch/variants/noibat/mainboard.c create mode 100644 src/mainboard/google/hatch/variants/noibat/overridetree.cb diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index b2bcabb306..ed478f810a 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -124,6 +124,7 @@ config MAINBOARD_PART_NUMBER default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU default "Mushu" if BOARD_GOOGLE_MUSHU + default "Noibat" if BOARD_GOOGLE_NOIBAT default "Palkia" if BOARD_GOOGLE_PALKIA default "Nightfury" if BOARD_GOOGLE_NIGHTFURY default "Puff" if BOARD_GOOGLE_PUFF @@ -154,6 +155,7 @@ config VARIANT_DIR default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU default "mushu" if BOARD_GOOGLE_MUSHU + default "noibat" if BOARD_GOOGLE_NOIBAT default "palkia" if BOARD_GOOGLE_PALKIA default "nightfury" if BOARD_GOOGLE_NIGHTFURY default "puff" if BOARD_GOOGLE_PUFF diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index c4490c601d..0688e09d79 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -67,6 +67,10 @@ config BOARD_GOOGLE_NIGHTFURY select CHROMEOS_DSM_CALIB select DRIVERS_I2C_MAX98390 +config BOARD_GOOGLE_NOIBAT + bool "-> Noibat" + select BOARD_GOOGLE_BASEBOARD_PUFF + config BOARD_GOOGLE_PUFF bool "-> Puff" select BOARD_GOOGLE_BASEBOARD_PUFF diff --git a/src/mainboard/google/hatch/variants/noibat/Makefile.inc b/src/mainboard/google/hatch/variants/noibat/Makefile.inc new file mode 100644 index 0000000000..2afd49410a --- /dev/null +++ b/src/mainboard/google/hatch/variants/noibat/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += gpio.c +ramstage-y += mainboard.c +bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/noibat/gpio.c b/src/mainboard/google/hatch/variants/noibat/gpio.c new file mode 100644 index 0000000000..5a911fc4f9 --- /dev/null +++ b/src/mainboard/google/hatch/variants/noibat/gpio.c @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static const struct pad_config gpio_table[] = { + /* A16 : SD_OC_ODL */ + PAD_CFG_GPI(GPP_A16, NONE, DEEP), + /* A18 : LAN_PE_ISOLATE_ODL */ + PAD_CFG_GPO(GPP_A18, 1, DEEP), + /* A23 : M2_WLAN_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), + + /* B5 : LAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + + /* C0 : SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1 : SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C6: M2_WLAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), + /* C7 : LAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), + /* C10 : PCH_PCON_RST_ODL */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C11 : PCH_PCON_PDB_ODL */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), + /* C15 : WLAN_OFF_L */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), + + /* E2 : EN_PP_MST_OD */ + PAD_CFG_GPO(GPP_E2, 1, DEEP), + /* E9 : USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : USB_A1_OC_ODL */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + + /* F11 : EMMC_CMD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA0 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA1 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA2 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA3 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA4 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA5 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA6 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA7 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_CLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + + /* H4: PCH_I2C_PCON_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5: PCH_I2C_PCON_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H22 : PWM_PP3300_BIOZZER */ + PAD_CFG_GPO(GPP_H22, 0, DEEP), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* B14 : GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B22 : GPP_B22_STRAP */ + PAD_NC(GPP_B22, NONE), + /* E19 : GPP_E19_STRAP */ + PAD_NC(GPP_E19, NONE), + /* E21 : GPP_E21_STRAP */ + PAD_NC(GPP_E21, NONE), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/noibat/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/noibat/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..86bd8fc866 --- /dev/null +++ b/src/mainboard/google/hatch/variants/noibat/include/variant/acpi/dptf.asl @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define DPTF_CPU_PASSIVE 93 +#define DPTF_CPU_CRITICAL 100 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 80 +#define DPTF_CPU_ACTIVE_AC3 75 +#define DPTF_CPU_ACTIVE_AC4 70 +#define DPTF_CPU_ACTIVE_AC5 65 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 75 +#define DPTF_TSR0_ACTIVE_AC0 50 +#define DPTF_TSR0_ACTIVE_AC1 47 +#define DPTF_TSR0_ACTIVE_AC2 45 +#define DPTF_TSR0_ACTIVE_AC3 42 +#define DPTF_TSR0_ACTIVE_AC4 39 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 75 +#define DPTF_TSR1_ACTIVE_AC0 50 +#define DPTF_TSR1_ACTIVE_AC1 47 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 39 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 95, 85, 75, 65, 55, 45, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 95, 85, 75, 65, 55, 45, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 95, 85, 75, 65, 55, 45, 0, 0, + 0, 0, 0 + } +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 15000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 25000, /* PowerLimitMinimum */ + 64000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/noibat/include/variant/ec.h b/src/mainboard/google/hatch/variants/noibat/include/variant/ec.h new file mode 100644 index 0000000000..7af174daa3 --- /dev/null +++ b/src/mainboard/google/hatch/variants/noibat/include/variant/ec.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include +#include + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + +#define MAINBOARD_EC_SMI_EVENTS 0 + +/* EC can wake from S5 with power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with power button */ +#define MAINBOARD_EC_S3_WAKE_EVENTS (MAINBOARD_EC_S5_WAKE_EVENTS) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ + (MAINBOARD_EC_S3_WAKE_EVENTS | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable cros_ec_keyb device */ +#define EC_ENABLE_MKBP_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* + * Defines EC wake pin route. + * Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE# + * on the PCH or as the line EC_PCH_WAKE_ODL on the schematic. + */ +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ + +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + +#endif /* VARIANT_EC_H */ diff --git a/src/mainboard/google/hatch/variants/noibat/include/variant/gpio.h b/src/mainboard/google/hatch/variants/noibat/include/variant/gpio.h new file mode 100644 index 0000000000..79a141008f --- /dev/null +++ b/src/mainboard/google/hatch/variants/noibat/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/noibat/mainboard.c b/src/mainboard/google/hatch/variants/noibat/mainboard.c new file mode 100644 index 0000000000..b5bc699ca0 --- /dev/null +++ b/src/mainboard/google/hatch/variants/noibat/mainboard.c @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define GPIO_HDMI_HPD GPP_E13 +#define GPIO_DP_HPD GPP_E14 + +/* TODO: This can be moved to common directory */ +static void wait_for_hpd(gpio_t gpio, long timeout) +{ + struct stopwatch sw; + + printk(BIOS_INFO, "Waiting for HPD\n"); + stopwatch_init_msecs_expire(&sw, timeout); + while (!gpio_get(gpio)) { + if (stopwatch_expired(&sw)) { + printk(BIOS_WARNING, + "HPD not ready after %ldms. Abort.\n", timeout); + return; + } + mdelay(200); + } + printk(BIOS_INFO, "HPD ready after %lu ms\n", + stopwatch_duration_msecs(&sw)); +} + +/* + * For type-C chargers, set PL2 to 90% of max power to account for + * cable loss and FET Rdson loss in the path from the source. + */ +#define SET_PSYSPL2(w) (9 * (w) / 10) + +#define PUFF_PL2 (35) + +#define PUFF_PSYSPL2 (58) + +#define PUFF_MAX_TIME_WINDOW 6 +#define PUFF_MIN_DUTYCYCLE 4 + +/* + * mainboard_set_power_limits + * + * Set Pl2 and SysPl2 values based on detected charger. + * Values are defined below but we use U22 value for all SKUs for now. + * definitions: + * x = no value entered. Use default value in parenthesis. + * will set 0 to anything that shouldn't be set. + * n = max value of power adapter. + * +-------------+-----+---------+-----------+-------+ + * | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 | + * +-------------+-----+---------+-----------+-------+ + * | i7 U42 | 51 | 81 | x(.85PL4) | x(82) | + * | celeron U22 | 35 | 58 | x(.85PL4) | x(51) | + * +-------------+-----+---------+-----------+-------+ + * For USB C charger: + * +-------------+-----+---------+---------+-------+ + * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 | + * +-------------+-----+---------+---------+-------+ + * | 60 (U42) | 44 | 54 | 54 | 54 | + * | 60 (U22) | 29 | 54 | 54 | x(43) | + * | n (U42) | 44 | .9n | .9n | .9n | + * | n (U22) | 29 | .9n | .9n | x(43) | + * +-------------+-----+---------+---------+-------+ + */ + +/* + * Psys_pmax considerations + * + * Given the hardware design in puff, the serial shunt resistor is 0.01ohm. + * The full scale of hardware PSYS signal 0.8v maps to system current 9.6A + * instead of real system power. The equation is shown below: + * PSYS = 0.8v = (0.01ohm x Iinput) x 50 (INA213, gain 50V/V) x 15k/(15k + 75k) + * Hence, Iinput (Amps) = 9.6A + * Since there is no voltage information from PSYS, different voltage input + * would map to different Psys_pmax settings: + * For Type-C 15V, the Psys_pmax sholud be 15v x 9.6A = 144W + * For Type-C 20V, the Psys_pmax should be 20v x 9.6A = 192W + * For a barral jack, the Psys_pmax should be 19v x 9.6A = 182.4W + */ +#define PSYS_IMAX 9600 +#define BJ_VOLTS_MV 19000 + +static void mainboard_set_power_limits(struct soc_power_limits_config *conf) +{ + enum usb_chg_type type; + u32 watts; + u16 volts_mv, current_ma; + u32 psyspl2 = PUFF_PSYSPL2; // default barrel jack value for U22 + int rv = google_chromeec_get_usb_pd_power_info(&type, ¤t_ma, &volts_mv); + + /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/ + conf->tdp_psyspl3 = 0; + conf->tdp_pl4 = 0; + + if (rv == 0 && type == USB_CHG_TYPE_PD) { + /* Detected USB-PD. Base on max value of adapter */ + watts = ((u32)current_ma * volts_mv) / 1000000; + psyspl2 = watts; + conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2); + /* set max possible time window */ + conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW; + /* set minimum duty cycle */ + conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE; + conf->tdp_pl4 = SET_PSYSPL2(psyspl2); + } else { + /* Input type is barrel jack */ + volts_mv = BJ_VOLTS_MV; + } + /* voltage unit is milliVolts and current is in milliAmps */ + conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000); + + conf->tdp_pl2_override = PUFF_PL2; + /* set psyspl2 to 90% of max adapter power */ + conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2); +} + +void variant_ramstage_init(void) +{ + static const long display_timeout_ms = 3000; + struct soc_power_limits_config *soc_config; + config_t *conf = config_of_soc(); + + /* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */ + gpio_input(GPIO_HDMI_HPD); + gpio_input(GPIO_DP_HPD); + if (display_init_required() + && !gpio_get(GPIO_HDMI_HPD) + && !gpio_get(GPIO_DP_HPD)) { + /* This has to be done before FSP-S runs. */ + if (google_chromeec_wait_for_displayport(display_timeout_ms)) + wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); + } + /* Psys_pmax needs to be setup before FSP-S */ + soc_config = &conf->power_limits_config; + mainboard_set_power_limits(soc_config); +} diff --git a/src/mainboard/google/hatch/variants/noibat/overridetree.cb b/src/mainboard/google/hatch/variants/noibat/overridetree.cb new file mode 100644 index 0000000000..83fcf9a76c --- /dev/null +++ b/src/mainboard/google/hatch/variants/noibat/overridetree.cb @@ -0,0 +1,392 @@ +chip soc/intel/cannonlake + # Enable heci communication + register "HeciEnabled" = "1" + + # Auto-switch between X4 NVMe and X2 NVMe. + register "TetonGlacierMode" = "1" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # USB configuration + # NOTE: This only applies to Puff, + # usb2_ports[1] and usb2_ports[3] were swapped on + # reference schematics after Puff has been built. + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 2 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC3, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 3 + register "usb2_ports[3]" = "{ + .enable = 1, + .ocpin = OC1, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 1 + register "usb2_ports[4]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 4 + register "usb2_ports[5]" = "{ + .enable = 1, + .ocpin = OC0, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A port 0 + register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 + + # Enable eMMC HS400 + register "ScsEmmcHs400Enabled" = "1" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-14.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-14.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-14.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-14.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-14.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-14.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" + + # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. + register "PchHdaAudioLinkSsp1" = "0" + register "PchHdaAudioLinkDmic0" = "0" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | RFU | + #| I2C2 | PS175 | + #| I2C3 | MST | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + }" + + # PCIe port 7 for LAN + register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + # PCIe port 11 (x2) for NVMe hybrid storage devices + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # Uses CLK SRC 0 + register "PcieClkSrcUsage[0]" = "6" + register "PcieClkSrcClkReq[0]" = "0" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + # SATA port 1 Gen3 Strength + # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB + register "sata_port[1].TxGen3DeEmphEnable" = "1" + register "sata_port[1].TxGen3DeEmph" = "0x20" + + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Left"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Right"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Right"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Middle"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Left"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 2.5 on end + end + chip drivers/usb/acpi + device usb 2.6 off end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Left"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Right"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Right"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Left"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Middle"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.5 on end + end + end + end + end # USB xHCI + device pci 15.0 off + # RFU - Reserved for Future Use. + end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 on end # I2C #2, PCON PS175. + device pci 15.3 on end # I2C #3, Realtek RTD2142. + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1a.0 on end # eMMC + device pci 1c.6 on + chip drivers/net + register "customized_leds" = "0x05af" + register "wake" = "GPE0_DW1_07" # GPP_C7 + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" + register "stop_delay_ms" = "12" # NIC needs time to quiesce + register "stop_off_delay_ms" = "1" + register "has_power_resource" = "1" + register "device_index" = "0" + device pci 00.0 on end + end + end # RTL8111H Ethernet NIC + device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1e.3 off end # GSPI #1 + end + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | + #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | + #+----------------+-------+-------+-------+-------+ + #Note: IccMax settings are moved to SoC code + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 1004, + .dc_loadline = 1004, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 181, + .dc_loadline = 181, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 319, + .dc_loadline = 319, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 319, + .dc_loadline = 319, + }" + +end From db2e11841ad69d52a610577abb0aab288eb094b7 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 22 May 2020 21:34:10 +0200 Subject: [PATCH 399/405] AGESA f14/f15tn/f16kb: Clean up buildOpts.c files Until now, the buildOpts.c files were primarily made out of copy-pasted AGESA options, commented-out definitions and several useless comments; that is, the materialization of technical debt in GCC-parsable form... Until now. It is assumed that the boards in the tree still boot. So, by comparing their settings, we can extract saner defaults to place into AGESA. Many of the settings were common across all boards of the same family, so we promote those values to default settings. In some cases flipping a flag was required, so the macros to alter that option had to be adapted as well. Since those AGESA versions are expected to never receive updates, it should not be a problem to change their files to suit our needs. As a result, all but two buildOpts.c files now have less than 100 lines. AGESA f14 boards need less than 50 lines, and f15tn/f16kb just require about 60 or 70 lines in those files. Hopefully, this will make porting more mainboards using AGESA f14/f15tn/f16kb a substantially easier task. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Ife1ca5177d85441b9a7b24d64d7fcbabde6e0409 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41667 Tested-by: build bot (Jenkins) Reviewed-by: Mike Banon --- src/mainboard/amd/inagua/buildOpts.c | 142 +-------- src/mainboard/amd/olivehill/buildOpts.c | 252 ++-------------- src/mainboard/amd/parmer/buildOpts.c | 254 ++--------------- src/mainboard/amd/persimmon/buildOpts.c | 169 ++--------- src/mainboard/amd/south_station/buildOpts.c | 170 ++--------- src/mainboard/amd/thatcher/buildOpts.c | 254 ++--------------- src/mainboard/amd/union_station/buildOpts.c | 170 ++--------- src/mainboard/asrock/e350m1/buildOpts.c | 177 ++---------- src/mainboard/asrock/imb-a180/buildOpts.c | 253 ++-------------- src/mainboard/asus/am1i-a/buildOpts.c | 269 ++---------------- src/mainboard/asus/f2a85-m/buildOpts.c | 263 ++--------------- src/mainboard/bap/ode_e20XX/buildOpts.c | 253 ++-------------- src/mainboard/biostar/a68n_5200/buildOpts.c | 253 ++-------------- src/mainboard/biostar/am1ml/buildOpts.c | 257 ++--------------- src/mainboard/elmex/pcm205400/buildOpts.c | 169 ++--------- src/mainboard/gizmosphere/gizmo/buildOpts.c | 169 ++--------- src/mainboard/gizmosphere/gizmo2/buildOpts.c | 253 ++-------------- src/mainboard/hp/abm/buildOpts.c | 259 ++--------------- .../hp/pavilion_m6_1035dx/buildOpts.c | 265 +++-------------- src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 187 +++--------- src/mainboard/lenovo/g505s/buildOpts.c | 263 +++-------------- .../lippert/frontrunner-af/buildOpts.c | 169 ++--------- src/mainboard/lippert/toucan-af/buildOpts.c | 169 ++--------- src/mainboard/msi/ms7721/buildOpts.c | 268 +++-------------- src/mainboard/pcengines/apu1/buildOpts.c | 171 ++--------- .../amd/agesa/f14/Config/PlatformInstall.h | 60 ++-- .../amd/agesa/f15tn/Config/OptionFchInstall.h | 41 +++ .../amd/agesa/f15tn/Config/PlatformInstall.h | 91 +++--- .../amd/agesa/f15tn/Proc/CPU/cpuLateInit.h | 2 +- .../amd/agesa/f16kb/Config/OptionFchInstall.h | 41 +++ .../amd/agesa/f16kb/Config/OptionGnbInstall.h | 4 +- .../amd/agesa/f16kb/Config/PlatformInstall.h | 67 ++--- .../amd/agesa/f16kb/Proc/CPU/cpuLateInit.h | 2 +- 33 files changed, 786 insertions(+), 5000 deletions(-) diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index aecc9a5b08..73216349ce 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -1,160 +1,32 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - */ +/* Select the CPU family */ +#define INSTALL_FAMILY_14_SUPPORT TRUE -/* Select the CPU family. */ -#define INSTALL_FAMILY_14_SUPPORT TRUE - -/* Select the CPU socket type. */ +/* Select the CPU socket type */ #define INSTALL_FT1_SOCKET_SUPPORT TRUE -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - +/* Agesa optional capabilities selection */ #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE -#define BLDOPT_REMOVE_DQS_TRAINING FALSE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE -#define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE -#define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE -#define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE -#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE -#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -#define BLDOPT_REMOVE_SRAT FALSE -#define BLDOPT_REMOVE_SLIT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_DMI TRUE -#define BLDOPT_REMOVE_HT_ASSIST TRUE -#define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE -#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE -#define BLDOPT_REMOVE_GFX_RECOVERY TRUE -#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -#define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm #define BLDCFG_S3_LATE_RESTORE FALSE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 #define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE #define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_UMA_ALLOCATION_SIZE 0 -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 -/* - * Agesa configuration values selection. - * Uncomment and specify the value for the configuration options - * needed by the system. - */ +/* Agesa configuration values selection */ #include -/* Include the files that instantiate the configuration definitions. */ - +/* Include the files that instantiate the configuration definitions */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" #include "cpuFamilyTranslation.h" @@ -167,5 +39,5 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -// Instantiate all solution relevant data. +/* Instantiate all solution relevant data */ #include diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index f5ac742727..0e09739f03 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -1,196 +1,34 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - */ - #include -#define INSTALL_FT3_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE +#define INSTALL_FT3_SOCKET_SUPPORT TRUE +#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP2_SOCKET_SUPPORT FALSE -#define INSTALL_FT1_SOCKET_SUPPORT FALSE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE -#define INSTALL_FM2_SOCKET_SUPPORT FALSE - -#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT - #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE - #undef INSTALL_FT3_SOCKET_SUPPORT - #define INSTALL_FT3_SOCKET_SUPPORT FALSE - #endif -#endif - -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_CDIT TRUE -#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE +#define BLDOPT_REMOVE_CDIT TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. +/* Build configuration values here. */ +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -/* Build configuration values here. - */ -#define BLDCFG_VRM_CURRENT_LIMIT 15000 -#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 -#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 -#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_SLEW_RATE 10000 -#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_SYNC_FLOOD TRUE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the - // core for C-state entry requests. A value - // of 0 in this field specifies that the core - // does not trap any IO addresses for C-state entry. - // Values greater than 0xFFF8 results in undefined behavior. -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 +#define BLDCFG_IOMMU_SUPPORT FALSE -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYNC_FLOOD TRUE -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled -#define BLDCFG_IOMMU_SUPPORT FALSE -#define OPTION_GFX_INIT_SVIEW FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife - -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL -#define BLDCFG_CFG_ABM_SUPPORT TRUE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID - -#ifdef PCIEX_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20) -#endif - -#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed - -/* Process the options... - * This file include MUST occur AFTER the user option selection settings - */ -/* - * Customized OEM build configurations for FCH component - */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" @@ -205,54 +43,4 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 -#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_SD_SSID 0x78061022 -#define DFLT_XHCI_SSID 0x78121022 -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE - -GPIO_CONTROL olivehill_gpio[] = { - {183, Function1, GpioIn | GpioOutEnB | PullUpB}, - {-1} -}; -//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&olivehill_gpio[0]) - #include diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 694eda7a1b..5ab39a13b2 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -1,198 +1,38 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - */ - #include -/* Select the CPU family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT FALSE -#define INSTALL_FAMILY_14_SUPPORT FALSE -#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE +/* Select the CPU family */ +#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE -/* Select the CPU socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT TRUE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP2_SOCKET_SUPPORT TRUE -#define INSTALL_FT1_SOCKET_SUPPORT FALSE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE +/* Select the CPU socket type */ +#define INSTALL_FS1_SOCKET_SUPPORT TRUE +#define INSTALL_FP2_SOCKET_SUPPORT TRUE -#define INSTALL_FM2_SOCKET_SUPPORT FALSE - -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. +/* Build configuration values here. */ +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_SYNC_FLOOD FALSE -/* Build configuration values here. - */ -#define BLDCFG_VRM_CURRENT_LIMIT 90000 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0 -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 +#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000 /* (0x2000 << 16) = 512M */ -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +#define BLDCFG_IOMMU_SUPPORT FALSE -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_ECC_SYNC_FLOOD FALSE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 - -#define BLDOPT_REMOVE_ALIB FALSE -#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled -#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 - -#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 -#define BLDCFG_CFG_ABM_SUPPORT 0 - -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 - -// Specify the default values for the VRM controlling the VDDNB plane. -// If not specified, the values used for the core VRM will be applied -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity - -#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 - -#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 -#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 - -#if CONFIG(GFXUMA) -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M */ -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#endif - -#define BLDCFG_IOMMU_SUPPORT FALSE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID - -/* Process the options... - * This file include MUST occur AFTER the user option selection settings - */ -/* - * Customized OEM build configurations for FCH component - */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" @@ -207,54 +47,10 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 -#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_SD_SSID 0x78061022 -#define DFLT_XHCI_SSID 0x78121022 -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE - -GPIO_CONTROL parmer_gpio[] = { +GPIO_CONTROL parmer_gpio[] = { {183, Function1, GpioIn | GpioOutEnB | PullUpB}, {-1} }; -#define BLDCFG_FCH_GPIO_CONTROL_LIST (&parmer_gpio[0]) +#define BLDCFG_FCH_GPIO_CONTROL_LIST (parmer_gpio) #include diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 91c2182361..d8d46d499e 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -1,160 +1,31 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - */ +/* Select the CPU family */ +#define INSTALL_FAMILY_14_SUPPORT TRUE -/* Select the CPU family. */ -#define INSTALL_FAMILY_14_SUPPORT TRUE +/* Select the CPU socket type */ +#define INSTALL_FT1_SOCKET_SUPPORT TRUE -/* Select the CPU socket type. */ -#define INSTALL_FT1_SOCKET_SUPPORT TRUE +/* Agesa optional capabilities selection */ +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_WHEA FALSE -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE -#define BLDOPT_REMOVE_DQS_TRAINING FALSE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ACPI_PSTATES FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE - #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -#define BLDOPT_REMOVE_SRAT FALSE -#define BLDOPT_REMOVE_SLIT FALSE -#define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_DMI TRUE -#define BLDOPT_REMOVE_HT_ASSIST TRUE -#define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE -#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE -#define BLDOPT_REMOVE_GFX_RECOVERY TRUE -#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +#define BLDCFG_CFG_GNB_HD_AUDIO FALSE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 - -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE TRUE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 -#define BLDCFG_CFG_GNB_HD_AUDIO FALSE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_UMA_ALLOCATION_SIZE 0 -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 - -/* - * Agesa configuration values selection. - * Uncomment and specify the value for the configuration options - * needed by the system. - */ +/* Agesa configuration values selection */ #include -/* Include the files that instantiate the configuration definitions. */ - +/* Include the files that instantiate the configuration definitions */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" #include "cpuFamilyTranslation.h" @@ -167,5 +38,5 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -// Instantiate all solution relevant data. +/* Instantiate all solution relevant data */ #include diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index 44248a25e5..453102aa6a 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -1,160 +1,32 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - */ +/* Select the CPU family */ +#define INSTALL_FAMILY_14_SUPPORT TRUE -/* Select the CPU family. */ -#define INSTALL_FAMILY_14_SUPPORT TRUE +/* Select the CPU socket type */ +#define INSTALL_FT1_SOCKET_SUPPORT TRUE -/* Select the CPU socket type. */ -#define INSTALL_FT1_SOCKET_SUPPORT TRUE +/* Agesa optional capabilities selection */ +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_WHEA TRUE -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE -#define BLDOPT_REMOVE_DQS_TRAINING FALSE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ACPI_PSTATES FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE - #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -#define BLDOPT_REMOVE_SRAT TRUE -#define BLDOPT_REMOVE_SLIT TRUE -#define BLDOPT_REMOVE_WHEA TRUE -#define BLDOPT_REMOVE_DMI TRUE -#define BLDOPT_REMOVE_HT_ASSIST TRUE -#define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE -#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE -#define BLDOPT_REMOVE_GFX_RECOVERY TRUE -#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +#define BLDCFG_S3_LATE_RESTORE FALSE +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 - -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE FALSE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_UMA_ALLOCATION_SIZE 0 -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 - -/* - * Agesa configuration values selection. - * Uncomment and specify the value for the configuration options - * needed by the system. - */ +/* Agesa configuration values selection */ #include -/* Include the files that instantiate the configuration definitions. */ - +/* Include the files that instantiate the configuration definitions */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" #include "cpuFamilyTranslation.h" @@ -167,5 +39,5 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -// Instantiate all solution relevant data. +/* Instantiate all solution relevant data */ #include diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index f9908ef309..433a9f428e 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -1,198 +1,38 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - */ - #include -/* Select the CPU family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT FALSE -#define INSTALL_FAMILY_14_SUPPORT FALSE -#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE +/* Select the CPU family */ +#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE -/* Select the CPU socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT TRUE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP2_SOCKET_SUPPORT TRUE -#define INSTALL_FT1_SOCKET_SUPPORT FALSE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE +/* Select the CPU socket type */ +#define INSTALL_FS1_SOCKET_SUPPORT TRUE +#define INSTALL_FP2_SOCKET_SUPPORT TRUE -#define INSTALL_FM2_SOCKET_SUPPORT FALSE - -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. +/* Build configuration values here. */ +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_SYNC_FLOOD FALSE -/* Build configuration values here. - */ -#define BLDCFG_VRM_CURRENT_LIMIT 90000 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0 -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 +#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000 /* (0x2000 << 16) = 512M */ -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +#define BLDCFG_IOMMU_SUPPORT FALSE -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_ECC_SYNC_FLOOD FALSE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 - -#define BLDOPT_REMOVE_ALIB FALSE -#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled -#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 - -#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 -#define BLDCFG_CFG_ABM_SUPPORT 0 - -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 - -// Specify the default values for the VRM controlling the VDDNB plane. -// If not specified, the values used for the core VRM will be applied -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity - -#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 - -#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 -#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 - -#if CONFIG(GFXUMA) -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M */ -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#endif - -#define BLDCFG_IOMMU_SUPPORT FALSE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID - -/* Process the options... - * This file include MUST occur AFTER the user option selection settings - */ -/* - * Customized OEM build configurations for FCH component - */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" @@ -207,54 +47,12 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 -#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_SD_SSID 0x78061022 -#define DFLT_XHCI_SSID 0x78121022 -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE #define FCH_NO_XHCI_SUPPORT TRUE -GPIO_CONTROL thatcher_gpio[] = { + +GPIO_CONTROL thatcher_gpio[] = { {183, Function1, PullUpB}, {-1} }; -#define BLDCFG_FCH_GPIO_CONTROL_LIST (&thatcher_gpio[0]) +#define BLDCFG_FCH_GPIO_CONTROL_LIST (thatcher_gpio) #include diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index 44248a25e5..453102aa6a 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -1,160 +1,32 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - */ +/* Select the CPU family */ +#define INSTALL_FAMILY_14_SUPPORT TRUE -/* Select the CPU family. */ -#define INSTALL_FAMILY_14_SUPPORT TRUE +/* Select the CPU socket type */ +#define INSTALL_FT1_SOCKET_SUPPORT TRUE -/* Select the CPU socket type. */ -#define INSTALL_FT1_SOCKET_SUPPORT TRUE +/* Agesa optional capabilities selection */ +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_WHEA TRUE -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE -#define BLDOPT_REMOVE_DQS_TRAINING FALSE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ACPI_PSTATES FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE - #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -#define BLDOPT_REMOVE_SRAT TRUE -#define BLDOPT_REMOVE_SLIT TRUE -#define BLDOPT_REMOVE_WHEA TRUE -#define BLDOPT_REMOVE_DMI TRUE -#define BLDOPT_REMOVE_HT_ASSIST TRUE -#define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE -#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE -#define BLDOPT_REMOVE_GFX_RECOVERY TRUE -#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +#define BLDCFG_S3_LATE_RESTORE FALSE +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 - -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE FALSE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_UMA_ALLOCATION_SIZE 0 -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 - -/* - * Agesa configuration values selection. - * Uncomment and specify the value for the configuration options - * needed by the system. - */ +/* Agesa configuration values selection */ #include -/* Include the files that instantiate the configuration definitions. */ - +/* Include the files that instantiate the configuration definitions */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" #include "cpuFamilyTranslation.h" @@ -167,5 +39,5 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -// Instantiate all solution relevant data. +/* Instantiate all solution relevant data */ #include diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index 701d7ee196..7a2cc3b499 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -1,160 +1,31 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - */ +/* Select the CPU family */ +#define INSTALL_FAMILY_14_SUPPORT TRUE +/* Select the CPU socket type */ +#define INSTALL_FT1_SOCKET_SUPPORT TRUE + +/* Agesa optional capabilities selection */ +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_WHEA TRUE + +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE + +/* Agesa configuration values selection */ #include -/* Select the CPU family. */ -#define INSTALL_FAMILY_14_SUPPORT TRUE - -/* Select the CPU socket type. */ -#define INSTALL_FT1_SOCKET_SUPPORT TRUE - -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE -#define BLDOPT_REMOVE_DQS_TRAINING FALSE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ACPI_PSTATES FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE - #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -#define BLDOPT_REMOVE_SRAT TRUE -#define BLDOPT_REMOVE_SLIT TRUE -#define BLDOPT_REMOVE_WHEA TRUE -#define BLDOPT_REMOVE_DMI TRUE -#define BLDOPT_REMOVE_HT_ASSIST TRUE -#define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE -#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE -#define BLDOPT_REMOVE_GFX_RECOVERY TRUE -#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE - -/* - * Agesa configuration values selection. - * Uncomment and specify the value for the configuration options - * needed by the system. - */ - -#define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 - -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE TRUE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 -//#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_UMA_ALLOCATION_SIZE 0 -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 - -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" #include "cpuFamilyTranslation.h" @@ -173,5 +44,5 @@ // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} -// Instantiate all solution relevant data. +/* Instantiate all solution relevant data */ #include diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c index 34561210f7..d7558f0091 100644 --- a/src/mainboard/asrock/imb-a180/buildOpts.c +++ b/src/mainboard/asrock/imb-a180/buildOpts.c @@ -1,196 +1,33 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - */ - #include -#define INSTALL_FT3_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE +#define INSTALL_FT3_SOCKET_SUPPORT TRUE +#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP2_SOCKET_SUPPORT FALSE -#define INSTALL_FT1_SOCKET_SUPPORT FALSE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE -#define INSTALL_FM2_SOCKET_SUPPORT FALSE - -#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT - #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE - #undef INSTALL_FT3_SOCKET_SUPPORT - #define INSTALL_FT3_SOCKET_SUPPORT FALSE - #endif -#endif - -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_CDIT TRUE -#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE +#define BLDOPT_REMOVE_CDIT TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. +/* Build configuration values here. */ +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -/* Build configuration values here. - */ -#define BLDCFG_VRM_CURRENT_LIMIT 15000 -#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 -#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 -#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_SLEW_RATE 10000 -#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_SYNC_FLOOD TRUE +#define BLDCFG_IOMMU_SUPPORT FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the - // core for C-state entry requests. A value - // of 0 in this field specifies that the core - // does not trap any IO addresses for C-state entry. - // Values greater than 0xFFF8 results in undefined behavior. -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYNC_FLOOD TRUE -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled -#define BLDCFG_IOMMU_SUPPORT FALSE -#define OPTION_GFX_INIT_SVIEW FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife - -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL -#define BLDCFG_CFG_ABM_SUPPORT TRUE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID - -#ifdef PCIEX_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20) -#endif - -#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed - -/* Process the options... - * This file include MUST occur AFTER the user option selection settings - */ -/* - * Customized OEM build configurations for FCH component - */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" @@ -205,54 +42,4 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 -#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_SD_SSID 0x78061022 -#define DFLT_XHCI_SSID 0x78121022 -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE - -GPIO_CONTROL imba180_gpio[] = { - {183, Function1, GpioIn | GpioOutEnB | PullUpB}, - {-1} -}; -//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&imba180_gpio[0]) - #include diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index d0a8a433ef..fe0915b8e5 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -1,16 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - */ - #include /* Include the files that instantiate the configuration definitions. */ @@ -22,251 +11,49 @@ #include #include #include -/* AGESA nonesense: the next three headers depend on heapManager.h */ +/* AGESA nonsense: the next three headers depend on heapManager.h */ #include #include #include -/* Select the CPU family. */ -#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE +/* Select the CPU family */ +#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE -/* Select the CPU socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP2_SOCKET_SUPPORT FALSE -#define INSTALL_FT1_SOCKET_SUPPORT FALSE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE -#define INSTALL_FM2_SOCKET_SUPPORT FALSE -#define INSTALL_FT3_SOCKET_SUPPORT TRUE +/* Select the CPU socket type */ +#define INSTALL_FT3_SOCKET_SUPPORT TRUE -#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT - #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE - #undef INSTALL_FT3_SOCKET_SUPPORT - #define INSTALL_FT3_SOCKET_SUPPORT FALSE - #endif -#endif +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_WHEA FALSE +#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CDIT TRUE -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE -#define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_CDIT TRUE -#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE +/* Build configuration values here. */ +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_DESKTOP -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. - -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE - -/* Build configuration values here. - */ -#define BLDCFG_VRM_CURRENT_LIMIT 15000 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 -#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_DESKTOP - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1600_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM TRUE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE FALSE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_ECC_SYNC_FLOOD FALSE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_1GB_ALIGN FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the - // core for C-state entry requests. A value - // of 0 in this field specifies that the core - // does not trap any IO addresses for C-state entry. - // Values greater than 0xFFF8 results in undefined behavior. - -#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled - -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL -#define BLDCFG_CFG_ABM_SUPPORT TRUE - -#ifdef PCIEX_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20) -#endif - -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1600_FREQUENCY +#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY /* FIXME: Turtle RAM? */ +#define BLDCFG_IGNORE_SPD_CHECKSUM TRUE +#define BLDCFG_ENABLE_ECC_FEATURE FALSE +#define BLDCFG_ECC_SYNC_FLOOD FALSE /* * Specify the default values for the VRM controlling the VDDNB plane. * If not specified, the values used for the core VRM will be applied */ -#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_SLEW_RATE 10000 -#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE -#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 -#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -#if CONFIG(GFXUMA) -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define OPTION_GFX_INIT_SVIEW FALSE -#endif +#define BLDCFG_IOMMU_SUPPORT FALSE -#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed - -#define BLDCFG_IOMMU_SUPPORT FALSE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID - -/* Process the options... - * This file include MUST occur AFTER the user option selection settings - */ -/* - * Customized OEM build configurations for FCH component - */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE - -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 -#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_SD_SSID 0x78061022 -#define DFLT_XHCI_SSID 0x78121022 -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE - -GPIO_CONTROL imba180_gpio[] = { - {183, Function1, GpioIn | GpioOutEnB | PullUpB}, - {-1} -}; -//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&imba180_gpio[0]) +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE /* AGESA nonsense: this header depends on the definitions above */ #include diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 65731aae86..6b57711507 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -1,16 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - */ - #include /* Include the files that instantiate the configuration definitions. */ @@ -18,245 +7,55 @@ #include #include #include -/* the next two headers depend on heapManager.h */ +/* AGESA nonsense: the next two headers depend on heapManager.h */ #include #include /* These tables are optional and may be used to adjust memory timing settings */ #include #include -/* Select the CPU family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT FALSE -#define INSTALL_FAMILY_14_SUPPORT FALSE -#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE +/* Select the CPU family */ +#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE -/* Select the CPU socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP2_SOCKET_SUPPORT FALSE -#define INSTALL_FT1_SOCKET_SUPPORT FALSE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE +/* Select the CPU socket type */ +#define INSTALL_FM2_SOCKET_SUPPORT TRUE -#define INSTALL_FM2_SOCKET_SUPPORT TRUE - -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. +/* Build configuration values here. */ +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY +#define BLDCFG_ENABLE_ECC_FEATURE FALSE +#define BLDCFG_ECC_SYNC_FLOOD FALSE -/* Build configuration values here. - */ -#define BLDCFG_VRM_CURRENT_LIMIT 90000 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0 -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 +#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000 /* (0x2000 << 16) = 512M */ -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +#define BLDCFG_IOMMU_SUPPORT TRUE -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE FALSE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_ECC_SYNC_FLOOD FALSE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -#define BLDOPT_REMOVE_ALIB FALSE -#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled -#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 +/* Customized OEM build configurations for FCH component */ +#define BLDCFG_FCH_GPP_LINK_CONFIG PortA1B1C1D1 +#define BLDCFG_FCH_GPP_PORT0_PRESENT TRUE +#define BLDCFG_FCH_GPP_PORT1_PRESENT TRUE -#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 -#define BLDCFG_CFG_ABM_SUPPORT 0 - -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 - -// Specify the default values for the VRM controlling the VDDNB plane. -// If not specified, the values used for the core VRM will be applied -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity - -#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 - -#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 -#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 - -#if CONFIG(GFXUMA) -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M */ -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#endif - -#define BLDCFG_IOMMU_SUPPORT TRUE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID - -/* Process the options... - * This file include MUST occur AFTER the user option selection settings - */ -/* - * Customized OEM build configurations for FCH component - */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE - -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -/* The AGESA likes to enable 512 bytes region on this base for LPC bus */ -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 -#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_SD_SSID 0x78061022 -#define DFLT_XHCI_SSID 0x78121022 -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA1B1C1D1 -#define DFLT_FCH_GPP_PORT0_PRESENT TRUE -#define DFLT_FCH_GPP_PORT1_PRESENT TRUE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define FCH_NO_XHCI_SUPPORT FALSE -GPIO_CONTROL f2a85_m_gpio[] = { -// {183, Function1, PullUpB}, +GPIO_CONTROL f2a85_m_gpio[] = { {-1} }; -#define BLDCFG_FCH_GPIO_CONTROL_LIST (&f2a85_m_gpio[0]) +#define BLDCFG_FCH_GPIO_CONTROL_LIST (f2a85_m_gpio) /* Moving this include up will break AGESA. */ #include diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c index d4c398adba..d7558f0091 100644 --- a/src/mainboard/bap/ode_e20XX/buildOpts.c +++ b/src/mainboard/bap/ode_e20XX/buildOpts.c @@ -1,196 +1,33 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - */ - #include -#define INSTALL_FT3_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE +#define INSTALL_FT3_SOCKET_SUPPORT TRUE +#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP2_SOCKET_SUPPORT FALSE -#define INSTALL_FT1_SOCKET_SUPPORT FALSE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE -#define INSTALL_FM2_SOCKET_SUPPORT FALSE - -#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT - #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE - #undef INSTALL_FT3_SOCKET_SUPPORT - #define INSTALL_FT3_SOCKET_SUPPORT FALSE - #endif -#endif - -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_CDIT TRUE -#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE +#define BLDOPT_REMOVE_CDIT TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. +/* Build configuration values here. */ +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -/* Build configuration values here. - */ -#define BLDCFG_VRM_CURRENT_LIMIT 15000 -#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 -#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 -#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_SLEW_RATE 10000 -#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_SYNC_FLOOD TRUE +#define BLDCFG_IOMMU_SUPPORT FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the - // core for C-state entry requests. A value - // of 0 in this field specifies that the core - // does not trap any IO addresses for C-state entry. - // Values greater than 0xFFF8 results in undefined behavior. -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYNC_FLOOD TRUE -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled -#define BLDCFG_IOMMU_SUPPORT FALSE -#define OPTION_GFX_INIT_SVIEW FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife - -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL -#define BLDCFG_CFG_ABM_SUPPORT TRUE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID - -#ifdef PCIEX_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20) -#endif - -#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed - -/* Process the options... - * This file include MUST occur AFTER the user option selection settings - */ -/* - * Customized OEM build configurations for FCH component - */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" @@ -205,54 +42,4 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 -#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_SD_SSID 0x78061022 -#define DFLT_XHCI_SSID 0x78121022 -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE - -GPIO_CONTROL gizmo2_gpio[] = { - {183, Function1, GpioIn | GpioOutEnB | PullUpB}, - {-1} -}; -//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&gizmo2_gpio[0]) - #include diff --git a/src/mainboard/biostar/a68n_5200/buildOpts.c b/src/mainboard/biostar/a68n_5200/buildOpts.c index f5ac742727..d7558f0091 100644 --- a/src/mainboard/biostar/a68n_5200/buildOpts.c +++ b/src/mainboard/biostar/a68n_5200/buildOpts.c @@ -1,196 +1,33 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - */ - #include -#define INSTALL_FT3_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE +#define INSTALL_FT3_SOCKET_SUPPORT TRUE +#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP2_SOCKET_SUPPORT FALSE -#define INSTALL_FT1_SOCKET_SUPPORT FALSE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE -#define INSTALL_FM2_SOCKET_SUPPORT FALSE - -#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT - #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE - #undef INSTALL_FT3_SOCKET_SUPPORT - #define INSTALL_FT3_SOCKET_SUPPORT FALSE - #endif -#endif - -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_CDIT TRUE -#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE +#define BLDOPT_REMOVE_CDIT TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. +/* Build configuration values here. */ +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -/* Build configuration values here. - */ -#define BLDCFG_VRM_CURRENT_LIMIT 15000 -#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 -#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 -#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_SLEW_RATE 10000 -#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_SYNC_FLOOD TRUE +#define BLDCFG_IOMMU_SUPPORT FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the - // core for C-state entry requests. A value - // of 0 in this field specifies that the core - // does not trap any IO addresses for C-state entry. - // Values greater than 0xFFF8 results in undefined behavior. -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYNC_FLOOD TRUE -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled -#define BLDCFG_IOMMU_SUPPORT FALSE -#define OPTION_GFX_INIT_SVIEW FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife - -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL -#define BLDCFG_CFG_ABM_SUPPORT TRUE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID - -#ifdef PCIEX_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20) -#endif - -#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed - -/* Process the options... - * This file include MUST occur AFTER the user option selection settings - */ -/* - * Customized OEM build configurations for FCH component - */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" @@ -205,54 +42,4 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 -#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_SD_SSID 0x78061022 -#define DFLT_XHCI_SSID 0x78121022 -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE - -GPIO_CONTROL olivehill_gpio[] = { - {183, Function1, GpioIn | GpioOutEnB | PullUpB}, - {-1} -}; -//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&olivehill_gpio[0]) - #include diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c index 54f92466b3..461561d2e0 100644 --- a/src/mainboard/biostar/am1ml/buildOpts.c +++ b/src/mainboard/biostar/am1ml/buildOpts.c @@ -1,196 +1,37 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - */ - #include -#define INSTALL_FT3_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE +#define INSTALL_FT3_SOCKET_SUPPORT TRUE +#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP2_SOCKET_SUPPORT FALSE -#define INSTALL_FT1_SOCKET_SUPPORT FALSE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE -#define INSTALL_FM2_SOCKET_SUPPORT FALSE - -#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT - #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE - #undef INSTALL_FT3_SOCKET_SUPPORT - #define INSTALL_FT3_SOCKET_SUPPORT FALSE - #endif -#endif - -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_CDIT TRUE -#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE +#define BLDOPT_REMOVE_CDIT TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. +/* Build configuration values here. */ +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -/* Build configuration values here. - */ -#define BLDCFG_VRM_CURRENT_LIMIT 15000 -#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 -#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 -#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_SLEW_RATE 10000 -#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1600_FREQUENCY +#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY /* FIXME: Turtle RAM? */ +#define BLDCFG_IGNORE_SPD_CHECKSUM TRUE +#define BLDCFG_ENABLE_ECC_FEATURE FALSE +#define BLDCFG_ECC_SYNC_FLOOD FALSE +#define BLDCFG_IOMMU_SUPPORT FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the - // core for C-state entry requests. A value - // of 0 in this field specifies that the core - // does not trap any IO addresses for C-state entry. - // Values greater than 0xFFF8 results in undefined behavior. -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1600_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM TRUE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE FALSE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYNC_FLOOD FALSE -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled -#define BLDCFG_IOMMU_SUPPORT FALSE -#define OPTION_GFX_INIT_SVIEW FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife - -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL -#define BLDCFG_CFG_ABM_SUPPORT TRUE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID - -#ifdef PCIEX_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20) -#endif - -#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed - -/* Process the options... - * This file include MUST occur AFTER the user option selection settings - */ -/* - * Customized OEM build configurations for FCH component - */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" @@ -205,54 +46,4 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 -#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_SD_SSID 0x78061022 -#define DFLT_XHCI_SSID 0x78121022 -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE - -GPIO_CONTROL imba180_gpio[] = { - {183, Function1, GpioIn | GpioOutEnB | PullUpB}, - {-1} -}; -//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&imba180_gpio[0]) - #include diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c index be07053185..d8d46d499e 100644 --- a/src/mainboard/elmex/pcm205400/buildOpts.c +++ b/src/mainboard/elmex/pcm205400/buildOpts.c @@ -1,160 +1,31 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - */ +/* Select the CPU family */ +#define INSTALL_FAMILY_14_SUPPORT TRUE -/* Select the CPU family. */ -#define INSTALL_FAMILY_14_SUPPORT TRUE +/* Select the CPU socket type */ +#define INSTALL_FT1_SOCKET_SUPPORT TRUE -/* Select the cpu socket type. */ -#define INSTALL_FT1_SOCKET_SUPPORT TRUE +/* Agesa optional capabilities selection */ +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_WHEA FALSE -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE -#define BLDOPT_REMOVE_DQS_TRAINING FALSE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ACPI_PSTATES FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE - #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -#define BLDOPT_REMOVE_SRAT FALSE -#define BLDOPT_REMOVE_SLIT FALSE -#define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_DMI TRUE -#define BLDOPT_REMOVE_HT_ASSIST TRUE -#define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE -#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE -#define BLDOPT_REMOVE_GFX_RECOVERY TRUE -#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +#define BLDCFG_CFG_GNB_HD_AUDIO FALSE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 - -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE TRUE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 -#define BLDCFG_CFG_GNB_HD_AUDIO FALSE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_UMA_ALLOCATION_SIZE 0 -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 - -/* - * Agesa configuration values selection. - * Uncomment and specify the value for the configuration options - * needed by the system. - */ +/* Agesa configuration values selection */ #include -/* Include the files that instantiate the configuration definitions. */ - +/* Include the files that instantiate the configuration definitions */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" #include "cpuFamilyTranslation.h" @@ -167,5 +38,5 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -// Instantiate all solution relevant data. +/* Instantiate all solution relevant data */ #include diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c index 91c2182361..d8d46d499e 100644 --- a/src/mainboard/gizmosphere/gizmo/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c @@ -1,160 +1,31 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - */ +/* Select the CPU family */ +#define INSTALL_FAMILY_14_SUPPORT TRUE -/* Select the CPU family. */ -#define INSTALL_FAMILY_14_SUPPORT TRUE +/* Select the CPU socket type */ +#define INSTALL_FT1_SOCKET_SUPPORT TRUE -/* Select the CPU socket type. */ -#define INSTALL_FT1_SOCKET_SUPPORT TRUE +/* Agesa optional capabilities selection */ +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_WHEA FALSE -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE -#define BLDOPT_REMOVE_DQS_TRAINING FALSE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ACPI_PSTATES FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE - #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -#define BLDOPT_REMOVE_SRAT FALSE -#define BLDOPT_REMOVE_SLIT FALSE -#define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_DMI TRUE -#define BLDOPT_REMOVE_HT_ASSIST TRUE -#define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE -#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE -#define BLDOPT_REMOVE_GFX_RECOVERY TRUE -#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +#define BLDCFG_CFG_GNB_HD_AUDIO FALSE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 - -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE TRUE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 -#define BLDCFG_CFG_GNB_HD_AUDIO FALSE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_UMA_ALLOCATION_SIZE 0 -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 - -/* - * Agesa configuration values selection. - * Uncomment and specify the value for the configuration options - * needed by the system. - */ +/* Agesa configuration values selection */ #include -/* Include the files that instantiate the configuration definitions. */ - +/* Include the files that instantiate the configuration definitions */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" #include "cpuFamilyTranslation.h" @@ -167,5 +38,5 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -// Instantiate all solution relevant data. +/* Instantiate all solution relevant data */ #include diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c index d4c398adba..d7558f0091 100644 --- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c @@ -1,196 +1,33 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - */ - #include -#define INSTALL_FT3_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE +#define INSTALL_FT3_SOCKET_SUPPORT TRUE +#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP2_SOCKET_SUPPORT FALSE -#define INSTALL_FT1_SOCKET_SUPPORT FALSE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE -#define INSTALL_FM2_SOCKET_SUPPORT FALSE - -#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT - #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE - #undef INSTALL_FT3_SOCKET_SUPPORT - #define INSTALL_FT3_SOCKET_SUPPORT FALSE - #endif -#endif - -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_CDIT TRUE -#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE +#define BLDOPT_REMOVE_CDIT TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. +/* Build configuration values here. */ +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -/* Build configuration values here. - */ -#define BLDCFG_VRM_CURRENT_LIMIT 15000 -#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 -#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 -#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_SLEW_RATE 10000 -#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_SYNC_FLOOD TRUE +#define BLDCFG_IOMMU_SUPPORT FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the - // core for C-state entry requests. A value - // of 0 in this field specifies that the core - // does not trap any IO addresses for C-state entry. - // Values greater than 0xFFF8 results in undefined behavior. -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYNC_FLOOD TRUE -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled -#define BLDCFG_IOMMU_SUPPORT FALSE -#define OPTION_GFX_INIT_SVIEW FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife - -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL -#define BLDCFG_CFG_ABM_SUPPORT TRUE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID - -#ifdef PCIEX_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20) -#endif - -#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed - -/* Process the options... - * This file include MUST occur AFTER the user option selection settings - */ -/* - * Customized OEM build configurations for FCH component - */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" @@ -205,54 +42,4 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 -#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_SD_SSID 0x78061022 -#define DFLT_XHCI_SSID 0x78121022 -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE - -GPIO_CONTROL gizmo2_gpio[] = { - {183, Function1, GpioIn | GpioOutEnB | PullUpB}, - {-1} -}; -//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&gizmo2_gpio[0]) - #include diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index 12974844ec..2d1128644b 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -1,201 +1,34 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ - */ - #include -#define INSTALL_FT3_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE +#define INSTALL_FT3_SOCKET_SUPPORT TRUE +#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP2_SOCKET_SUPPORT FALSE -#define INSTALL_FT1_SOCKET_SUPPORT FALSE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE -#define INSTALL_FM2_SOCKET_SUPPORT FALSE +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_WHEA FALSE +#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CDIT TRUE -#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT - #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE - #undef INSTALL_FT3_SOCKET_SUPPORT - #define INSTALL_FT3_SOCKET_SUPPORT FALSE - #endif -#endif +/* Build configuration values here. */ +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE -#define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_CDIT TRUE -#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_SYNC_FLOOD TRUE +#define BLDCFG_UMA_ALLOCATION_MODE UMA_NONE +#define BLDCFG_IOMMU_SUPPORT FALSE -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE - -/* Build configuration values here. - */ -#define BLDCFG_VRM_CURRENT_LIMIT 15000 -#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 -#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 -#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_SLEW_RATE 10000 -#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE - -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the - // core for C-state entry requests. A value - // of 0 in this field specifies that the core - // does not trap any IO addresses for C-state entry. - // Values greater than 0xFFF8 results in undefined behavior. -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYNC_FLOOD TRUE -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_NONE -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled -#define BLDCFG_IOMMU_SUPPORT FALSE -#define OPTION_GFX_INIT_SVIEW FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife - -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL -#define BLDCFG_CFG_ABM_SUPPORT TRUE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID - -#ifdef PCIEX_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20) -#endif - -#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed - -/* Process the options... - * This file include MUST occur AFTER the user option selection settings - */ -/* - * Customized OEM build configurations for FCH component - */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" @@ -210,51 +43,7 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 -#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_SD_SSID 0x78061022 -#define DFLT_XHCI_SSID 0x78121022 -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE - -GPIO_CONTROL hp_abm_gpio[] = { +GPIO_CONTROL hp_abm_gpio[] = { { 45, Function2, GpioOutEnB | Sticky }, // Signal input APU_SD_LED { 49, Function2, PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_UID { 50, Function2, PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_HEALTH @@ -267,6 +56,6 @@ GPIO_CONTROL hp_abm_gpio[] = { { 71, Function0, GpioOut | PullUpB | PullDown | Sticky }, // Signal output APU_PROCHOT_L_R {-1} }; -#define BLDCFG_FCH_GPIO_CONTROL_LIST (&hp_abm_gpio[0]) +#define BLDCFG_FCH_GPIO_CONTROL_LIST (hp_abm_gpio) #include diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 107c9937dc..3aad89c15e 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -1,16 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - */ - #include "mainboard.h" #include @@ -20,237 +9,44 @@ #include #include #include -/* AGESA nonesense: the next two headers depend on heapManager.h */ +/* AGESA nonsense: the next two headers depend on heapManager.h */ #include #include /* These tables are optional and may be used to adjust memory timing settings */ #include #include -/* Select the CPU family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT FALSE -#define INSTALL_FAMILY_14_SUPPORT FALSE -#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE +/* Select the CPU family */ +#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE -/* Select the CPU socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT TRUE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP2_SOCKET_SUPPORT TRUE -#define INSTALL_FT1_SOCKET_SUPPORT FALSE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE +/* Select the CPU socket type */ +#define INSTALL_FS1_SOCKET_SUPPORT TRUE +#define INSTALL_FP2_SOCKET_SUPPORT TRUE -#define INSTALL_FM2_SOCKET_SUPPORT FALSE - -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. +/* Build configuration values here. */ +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_SYNC_FLOOD FALSE -/* Build configuration values here. - */ -#define BLDCFG_VRM_CURRENT_LIMIT 90000 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0 -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 +#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000 /* (0x2000 << 16) = 512M */ -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +#define BLDCFG_IOMMU_SUPPORT TRUE -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_ECC_SYNC_FLOOD FALSE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 - -#define BLDOPT_REMOVE_ALIB FALSE -#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled -#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 - -#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 -#define BLDCFG_CFG_ABM_SUPPORT 0 - -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 - -// Specify the default values for the VRM controlling the VDDNB plane. -// If not specified, the values used for the core VRM will be applied -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity - -#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 - -#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 -#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 - -#if CONFIG(GFXUMA) -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M */ -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#endif - -#define BLDCFG_IOMMU_SUPPORT TRUE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID - -/* Process the options... - * This file include MUST occur AFTER the user option selection settings - */ -/* - * Customized OEM build configurations for FCH component - */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE - -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 -#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_SD_SSID 0x78061022 -#define DFLT_XHCI_SSID 0x78121022 -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE /* * The GPIO control is not well documented in AGESA, but is in the BKDG @@ -279,9 +75,10 @@ GPIO_CONTROL pavilion_m6_1035dx_gpio[] = { {57, Function1, OUTPUT_HIGH | PULL_NONE}, /* WLAN enable */ {-1} }; -#define BLDCFG_FCH_GPIO_CONTROL_LIST (&pavilion_m6_1035dx_gpio[0]) +#define BLDCFG_FCH_GPIO_CONTROL_LIST (pavilion_m6_1035dx_gpio) -/* These definitions could be moved to a common Hudson header, should we decide +/* + * These definitions could be moved to a common Hudson header, should we decide * to provide our own, saner SCI mapping function */ #define GEVENT_PIN(gpe) ((gpe) + 0x40) @@ -299,7 +96,11 @@ SCI_MAP_CONTROL m6_1035dx_sci_map[] = { {SCI_MAP_XHCI_10_0, PME_GPE}, {SCI_MAP_PWRBTN, PME_GPE}, }; -#define BLDCFG_FCH_SCI_MAP_LIST (&m6_1035dx_sci_map[0]) +#define BLDCFG_FCH_SCI_MAP_LIST (m6_1035dx_sci_map) -/* AGESA nonsense: this header depends on the definitions above */ +/* + * Process the options... + * This file include MUST occur AFTER the user option selection settings. + * AGESA nonsense: Moving this include up will break AGESA. + */ #include diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index 3bc97ea97a..d8d46d499e 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -1,165 +1,42 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - */ +/* Select the CPU family */ +#define INSTALL_FAMILY_14_SUPPORT TRUE -#include +/* Select the CPU socket type */ +#define INSTALL_FT1_SOCKET_SUPPORT TRUE -/* Include the files that instantiate the configuration definitions. */ -#include -#include -#include -#include -/* AGESA nonesense: the next two headers depend on heapManager.h */ -#include -#include -/* These tables are optional and may be used to adjust memory timing settings */ -#include -#include +/* Agesa optional capabilities selection */ +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_WHEA FALSE -/* Select the CPU family. */ -#define INSTALL_FAMILY_14_SUPPORT TRUE +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -/* Select the CPU socket type. */ -#define INSTALL_FT1_SOCKET_SUPPORT TRUE +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +#define BLDCFG_CFG_GNB_HD_AUDIO FALSE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -/** - * AGESA optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ +/* Agesa configuration values selection */ +#include -#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE -#define BLDOPT_REMOVE_DQS_TRAINING FALSE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE - #define BLDOPT_REMOVE_ACPI_PSTATES FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE - #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -#define BLDOPT_REMOVE_SRAT FALSE -#define BLDOPT_REMOVE_SLIT FALSE -#define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_DMI TRUE -#define BLDOPT_REMOVE_HT_ASSIST TRUE -#define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE -#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE -#define BLDOPT_REMOVE_GFX_RECOVERY TRUE -#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE +/* Include the files that instantiate the configuration definitions */ +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" -#define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 - -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE TRUE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 -#define BLDCFG_CFG_GNB_HD_AUDIO FALSE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_UMA_ALLOCATION_SIZE 0 -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 - -/* AGESA nonsense: this header depends on the definitions above */ -/* Instantiate all solution relevant data. */ +/* Instantiate all solution relevant data */ #include diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index c78c5c5374..c0a87ddb21 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -1,16 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - */ - #include "mainboard.h" #include @@ -20,237 +9,44 @@ #include #include #include -/* AGESA nonesense: the next two headers depend on heapManager.h */ +/* AGESA nonsense: the next two headers depend on heapManager.h */ #include #include /* These tables are optional and may be used to adjust memory timing settings */ #include #include -/* Select the CPU family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT FALSE -#define INSTALL_FAMILY_14_SUPPORT FALSE -#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE +/* Select the CPU family */ +#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE -/* Select the CPU socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT TRUE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP2_SOCKET_SUPPORT TRUE -#define INSTALL_FT1_SOCKET_SUPPORT FALSE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE +/* Select the CPU socket type */ +#define INSTALL_FS1_SOCKET_SUPPORT TRUE +#define INSTALL_FP2_SOCKET_SUPPORT TRUE -#define INSTALL_FM2_SOCKET_SUPPORT FALSE - -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. +/* Build configuration values here */ +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_SYNC_FLOOD FALSE -/* Build configuration values here. - */ -#define BLDCFG_VRM_CURRENT_LIMIT 90000 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0 -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_ECC_SYNC_FLOOD FALSE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 - -#define BLDOPT_REMOVE_ALIB FALSE -#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled -#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 - -#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 -#define BLDCFG_CFG_ABM_SUPPORT 0 - -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 - -// Specify the default values for the VRM controlling the VDDNB plane. -// If not specified, the values used for the core VRM will be applied -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity - -#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 - -#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 -#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 - -#if CONFIG(GFXUMA) -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M */ -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#endif +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000 /* (0x2000 << 16) = 512M */ -#define BLDCFG_IOMMU_SUPPORT TRUE +#define BLDCFG_IOMMU_SUPPORT TRUE -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID - -/* Process the options... - * This file include MUST occur AFTER the user option selection settings - */ -/* - * Customized OEM build configurations for FCH component - */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE - -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 -#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_SD_SSID 0x78061022 -#define DFLT_XHCI_SSID 0x78121022 -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE /* * The GPIO control is not well documented in AGESA, but is in the BKDG @@ -279,9 +75,10 @@ GPIO_CONTROL lenovo_g505s_gpio[] = { {57, Function1, OUTPUT_HIGH | PULL_NONE}, /* WLAN enable */ {-1} }; -#define BLDCFG_FCH_GPIO_CONTROL_LIST (&lenovo_g505s_gpio[0]) +#define BLDCFG_FCH_GPIO_CONTROL_LIST (lenovo_g505s_gpio) -/* These definitions could be moved to a common Hudson header, should we decide +/* + * These definitions could be moved to a common Hudson header, should we decide * to provide our own, saner SCI mapping function */ #define GEVENT_PIN(gpe) ((gpe) + 0x40) @@ -299,7 +96,11 @@ SCI_MAP_CONTROL lenovo_g505s_sci_map[] = { {SCI_MAP_XHCI_10_0, PME_GPE}, {SCI_MAP_PWRBTN, PME_GPE}, }; -#define BLDCFG_FCH_SCI_MAP_LIST (&lenovo_g505s_sci_map[0]) +#define BLDCFG_FCH_SCI_MAP_LIST (lenovo_g505s_sci_map) -/* AGESA nonsense: this header depends on the definitions above */ +/* + * Process the options... + * This file include MUST occur AFTER the user option selection settings. + * AGESA nonsense: Moving this include up will break AGESA. + */ #include diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c index 91c2182361..d8d46d499e 100644 --- a/src/mainboard/lippert/frontrunner-af/buildOpts.c +++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c @@ -1,160 +1,31 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - */ +/* Select the CPU family */ +#define INSTALL_FAMILY_14_SUPPORT TRUE -/* Select the CPU family. */ -#define INSTALL_FAMILY_14_SUPPORT TRUE +/* Select the CPU socket type */ +#define INSTALL_FT1_SOCKET_SUPPORT TRUE -/* Select the CPU socket type. */ -#define INSTALL_FT1_SOCKET_SUPPORT TRUE +/* Agesa optional capabilities selection */ +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_WHEA FALSE -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE -#define BLDOPT_REMOVE_DQS_TRAINING FALSE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ACPI_PSTATES FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE - #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -#define BLDOPT_REMOVE_SRAT FALSE -#define BLDOPT_REMOVE_SLIT FALSE -#define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_DMI TRUE -#define BLDOPT_REMOVE_HT_ASSIST TRUE -#define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE -#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE -#define BLDOPT_REMOVE_GFX_RECOVERY TRUE -#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +#define BLDCFG_CFG_GNB_HD_AUDIO FALSE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 - -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE TRUE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 -#define BLDCFG_CFG_GNB_HD_AUDIO FALSE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_UMA_ALLOCATION_SIZE 0 -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 - -/* - * Agesa configuration values selection. - * Uncomment and specify the value for the configuration options - * needed by the system. - */ +/* Agesa configuration values selection */ #include -/* Include the files that instantiate the configuration definitions. */ - +/* Include the files that instantiate the configuration definitions */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" #include "cpuFamilyTranslation.h" @@ -167,5 +38,5 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -// Instantiate all solution relevant data. +/* Instantiate all solution relevant data */ #include diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c index 91c2182361..d8d46d499e 100644 --- a/src/mainboard/lippert/toucan-af/buildOpts.c +++ b/src/mainboard/lippert/toucan-af/buildOpts.c @@ -1,160 +1,31 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - */ +/* Select the CPU family */ +#define INSTALL_FAMILY_14_SUPPORT TRUE -/* Select the CPU family. */ -#define INSTALL_FAMILY_14_SUPPORT TRUE +/* Select the CPU socket type */ +#define INSTALL_FT1_SOCKET_SUPPORT TRUE -/* Select the CPU socket type. */ -#define INSTALL_FT1_SOCKET_SUPPORT TRUE +/* Agesa optional capabilities selection */ +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_WHEA FALSE -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE -#define BLDOPT_REMOVE_DQS_TRAINING FALSE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ACPI_PSTATES FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE - #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -#define BLDOPT_REMOVE_SRAT FALSE -#define BLDOPT_REMOVE_SLIT FALSE -#define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_DMI TRUE -#define BLDOPT_REMOVE_HT_ASSIST TRUE -#define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE -#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE -#define BLDOPT_REMOVE_GFX_RECOVERY TRUE -#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +#define BLDCFG_CFG_GNB_HD_AUDIO FALSE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 - -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE TRUE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 -#define BLDCFG_CFG_GNB_HD_AUDIO FALSE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_UMA_ALLOCATION_SIZE 0 -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 - -/* - * Agesa configuration values selection. - * Uncomment and specify the value for the configuration options - * needed by the system. - */ +/* Agesa configuration values selection */ #include -/* Include the files that instantiate the configuration definitions. */ - +/* Include the files that instantiate the configuration definitions */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" #include "cpuFamilyTranslation.h" @@ -167,5 +38,5 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -// Instantiate all solution relevant data. +/* Instantiate all solution relevant data */ #include diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index 61858940c0..5740382985 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -1,16 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - */ - #include /* Include the files that instantiate the configuration definitions. */ @@ -18,245 +7,60 @@ #include #include #include -/* the next two headers depend on heapManager.h */ +/* AGESA nonsense: the next two headers depend on heapManager.h */ #include #include /* These tables are optional and may be used to adjust memory timing settings */ #include #include -/* Select the CPU family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT FALSE -#define INSTALL_FAMILY_14_SUPPORT FALSE -#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE +/* Select the CPU family */ +#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE -/* Select the CPU socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP2_SOCKET_SUPPORT FALSE -#define INSTALL_FT1_SOCKET_SUPPORT FALSE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE +/* Select the CPU socket type */ +#define INSTALL_FM2_SOCKET_SUPPORT TRUE -#define INSTALL_FM2_SOCKET_SUPPORT TRUE - -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE -//This element selects whether P-States should be forced to be independent, -// as reported by the ACPI _PSD object. For single-link processors, -// setting TRUE for OS to support this feature. +/* Build configuration values here */ +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY +#define BLDCFG_ENABLE_ECC_FEATURE FALSE +#define BLDCFG_ECC_SYNC_FLOOD FALSE -/* Build configuration values here. - */ -#define BLDCFG_VRM_CURRENT_LIMIT 90000 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0 -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE FALSE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_ECC_SYNC_FLOOD FALSE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 - -#define BLDOPT_REMOVE_ALIB FALSE -#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled -#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 - -#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 -#define BLDCFG_CFG_ABM_SUPPORT 0 - -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 - -// Specify the default values for the VRM controlling the VDDNB plane. -// If not specified, the values used for the core VRM will be applied -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity - -#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 - -#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 -#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 - -#if CONFIG(GFXUMA) -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M */ -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#endif +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000 /* (0x2000 << 16) = 512M */ -#define BLDCFG_IOMMU_SUPPORT TRUE +#define BLDCFG_IOMMU_SUPPORT TRUE -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID -//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID -//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -/* Process the options... - * This file include MUST occur AFTER the user option selection settings - */ -/* - * Customized OEM build configurations for FCH component - */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE +/* Customized OEM build configurations for FCH component */ +#define BLDCFG_FCH_GPP_LINK_CONFIG PortA1B1C1D1 +#define BLDCFG_FCH_GPP_PORT0_PRESENT TRUE +#define BLDCFG_FCH_GPP_PORT1_PRESENT TRUE -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ - -#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -/* The AGESA likes to enable 512 bytes region on this base for LPC bus */ -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 -#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_SD_SSID 0x78061022 -#define DFLT_XHCI_SSID 0x78121022 -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA1B1C1D1 -#define DFLT_FCH_GPP_PORT0_PRESENT TRUE -#define DFLT_FCH_GPP_PORT1_PRESENT TRUE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -//#define FCH_NO_XHCI_SUPPORT FALSE -GPIO_CONTROL ms7721_m_gpio[] = { -// {183, Function1, PullUpB}, +GPIO_CONTROL ms7721_m_gpio[] = { {-1} }; -#define BLDCFG_FCH_GPIO_CONTROL_LIST (&ms7721_m_gpio[0]) -/* Moving this include up will break AGESA. */ +#define BLDCFG_FCH_GPIO_CONTROL_LIST (ms7721_m_gpio) + +/* + * Process the options... + * This file include MUST occur AFTER the user option selection settings. + * AGESA nonsense: Moving this include up will break AGESA. + */ #include diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c index 3a14ce5a25..255893833c 100644 --- a/src/mainboard/pcengines/apu1/buildOpts.c +++ b/src/mainboard/pcengines/apu1/buildOpts.c @@ -1,160 +1,33 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/** - * @file - * - * AMD User options selection for a Brazos platform solution system - * - * This file is placed in the user's platform directory and contains the - * build option selections desired for that platform. - * - * For Information about this file, see @ref platforminstall. - */ +/* Select the CPU family */ +#define INSTALL_FAMILY_14_SUPPORT TRUE -/* Select the CPU family. */ -#define INSTALL_FAMILY_14_SUPPORT TRUE +/* Select the CPU socket type */ +#define INSTALL_FT1_SOCKET_SUPPORT TRUE -/* Select the CPU socket type. */ -#define INSTALL_FT1_SOCKET_SUPPORT TRUE +/* Agesa optional capabilities selection */ +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_WHEA FALSE +#define BLDOPT_ENABLE_DMI TRUE -/* - * Agesa optional capabilities selection. - * Uncomment and mark FALSE those features you wish to include in the build. - * Comment out or mark TRUE those features you want to REMOVE from the build. - */ +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE -#define BLDOPT_REMOVE_DQS_TRAINING FALSE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ACPI_PSTATES FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE - #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -#define BLDOPT_REMOVE_SRAT FALSE -#define BLDOPT_REMOVE_SLIT FALSE -#define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_DMI FALSE -#define BLDOPT_REMOVE_HT_ASSIST TRUE -#define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE -#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE -#define BLDOPT_REMOVE_GFX_RECOVERY TRUE -#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +#define BLDCFG_CFG_GNB_HD_AUDIO FALSE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE +#define BLDCFG_UMA_ALLOCATION_MODE UMA_NONE -#define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 - -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE TRUE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 -#define BLDCFG_CFG_GNB_HD_AUDIO FALSE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALLOCATION_MODE UMA_NONE -#define BLDCFG_UMA_ALLOCATION_SIZE 0 -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 - -/* - * Agesa configuration values selection. - * Uncomment and specify the value for the configuration options - * needed by the system. - */ +/* Agesa configuration values selection */ #include -/* Include the files that instantiate the configuration definitions. */ - +/* Include the files that instantiate the configuration definitions */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" #include "cpuFamilyTranslation.h" @@ -167,5 +40,5 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -// Instantiate all solution relevant data. +/* Instantiate all solution relevant data */ #include diff --git a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h index 883d509bca..31472b2c2e 100644 --- a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h @@ -206,8 +206,6 @@ static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define OPTION_SW_DRAM_INIT TRUE #undef OPTION_S3_MEM_SUPPORT #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_GFX_RECOVERY - #define OPTION_GFX_RECOVERY TRUE #undef OPTION_C6_STATE #define OPTION_C6_STATE TRUE #undef OPTION_CPB @@ -238,7 +236,7 @@ static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define OPTION_ACPI_PSTATES TRUE #define OPTION_WHEA TRUE -#define OPTION_DMI TRUE +#define OPTION_DMI FALSE #define OPTION_EARLY_SAMPLES FALSE #define CFG_ACPI_PSTATES_PPC TRUE #define CFG_ACPI_PSTATES_PCT TRUE @@ -246,7 +244,7 @@ static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define CFG_ACPI_PSTATES_PSS TRUE #define CFG_ACPI_PSTATES_XPSS TRUE #define CFG_ACPI_PSTATE_PSD_INDPX FALSE -#define CFG_VRM_HIGH_SPEED_ENABLE FALSE +#define CFG_VRM_HIGH_SPEED_ENABLE TRUE #define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE #define OPTION_ALIB TRUE /*--------------------------------------------------------------------------- @@ -312,10 +310,11 @@ static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define OPTION_PARALLEL_TRAINING FALSE #endif #endif -#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT - #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE +/* Originally BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT, but inverted alongside the default value */ +#ifdef BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT + #if BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT == TRUE #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE FALSE + #define OPTION_ONLINE_SPARE TRUE #endif #endif #ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT @@ -348,10 +347,11 @@ static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define OPTION_WHEA FALSE #endif #endif -#ifdef BLDOPT_REMOVE_DMI - #if BLDOPT_REMOVE_DMI == TRUE +/* Originally BLDOPT_REMOVE_DMI, but inverted alongside the default value */ +#ifdef BLDOPT_ENABLE_DMI + #if BLDOPT_ENABLE_DMI == TRUE #undef OPTION_DMI - #define OPTION_DMI FALSE + #define OPTION_DMI TRUE #endif #endif #ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR @@ -389,10 +389,11 @@ static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #endif #endif -#ifdef BLDOPT_REMOVE_GFX_RECOVERY - #if BLDOPT_REMOVE_GFX_RECOVERY == TRUE +/* Originally BLDOPT_REMOVE_GFX_RECOVERY, but inverted alongside the default value */ +#ifdef BLDOPT_ENABLE_GFX_RECOVERY + #if BLDOPT_ENABLE_GFX_RECOVERY == TRUE #undef OPTION_GFX_RECOVERY - #define OPTION_GFX_RECOVERY FALSE + #define OPTION_GFX_RECOVERY TRUE #endif #endif @@ -438,10 +439,11 @@ static const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #endif #endif -#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE - #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE +/* Originally BLDCFG_VRM_HIGH_SPEED_ENABLE, but inverted alongside the default value */ +#ifdef BLDCFG_VRM_HIGH_SPEED_DISABLE + #if BLDCFG_VRM_HIGH_SPEED_DISABLE == TRUE #undef CFG_VRM_HIGH_SPEED_ENABLE - #define CFG_VRM_HIGH_SPEED_ENABLE TRUE + #define CFG_VRM_HIGH_SPEED_ENABLE FALSE #endif #endif @@ -571,13 +573,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_VRM_CURRENT_LIMIT #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT #else - #define CFG_VRM_CURRENT_LIMIT 0 + #define CFG_VRM_CURRENT_LIMIT 24000 #endif #ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD #define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD #else - #define CFG_VRM_LOW_POWER_THRESHOLD 0 + #define CFG_VRM_LOW_POWER_THRESHOLD 24000 #endif #ifdef BLDCFG_VRM_SLEW_RATE @@ -589,7 +591,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT #define CFG_VRM_INRUSH_CURRENT_LIMIT BLDCFG_VRM_INRUSH_CURRENT_LIMIT #else - #define CFG_VRM_INRUSH_CURRENT_LIMIT 0 + #define CFG_VRM_INRUSH_CURRENT_LIMIT (6000) #endif #ifdef BLDCFG_VRM_NB_ADDITIONAL_DELAY @@ -626,7 +628,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_PLAT_NUM_IO_APICS #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS #else - #define CFG_PLAT_NUM_IO_APICS 0 + #define CFG_PLAT_NUM_IO_APICS 3 #endif #ifdef BLDCFG_MEM_INIT_PSTATE @@ -662,19 +664,19 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_PLATFORM_CSTATE_MODE #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE #else - #define CFG_CSTATE_MODE CStateModeDisabled + #define CFG_CSTATE_MODE CStateModeC6 #endif #ifdef BLDCFG_PLATFORM_CSTATE_OPDATA #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA #else - #define CFG_CSTATE_OPDATA 0 + #define CFG_CSTATE_OPDATA 0x840 #endif #ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS #else - #define CFG_CSTATE_IO_BASE_ADDRESS 0 + #define CFG_CSTATE_IO_BASE_ADDRESS 0x840 #endif #ifdef BLDCFG_PLATFORM_CPB_MODE @@ -686,7 +688,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_CORE_LEVELING_MODE #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE #else - #define CFG_CORE_LEVELING_MODE 0 + #define CFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #endif #ifdef BLDCFG_AMD_PSTATE_CAP_VALUE @@ -704,7 +706,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT #else - #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY + #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY #endif #ifdef BLDCFG_MEMORY_MODE_UNGANGED @@ -770,13 +772,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_MEMORY_POWER_DOWN #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN #else - #define CFG_MEMORY_POWER_DOWN FALSE + #define CFG_MEMORY_POWER_DOWN TRUE #endif #ifdef BLDCFG_POWER_DOWN_MODE #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE #else - #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO + #define CFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT #endif #ifdef BLDCFG_ONLINE_SPARE @@ -806,7 +808,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_MEMORY_CLOCK_SELECT #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT #else - #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY + #define CFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY #endif #ifdef BLDCFG_DQS_TRAINING_CONTROL @@ -878,7 +880,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_ECC_SYNC_FLOOD #define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD #else - #define CFG_ECC_SYNC_FLOOD 0 + #define CFG_ECC_SYNC_FLOOD FALSE #endif #ifdef BLDCFG_ECC_SYMBOL_SIZE diff --git a/src/vendorcode/amd/agesa/f15tn/Config/OptionFchInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/OptionFchInstall.h index 4a8237a210..5ea5fd1595 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/OptionFchInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/OptionFchInstall.h @@ -48,6 +48,47 @@ #define FCH_SUPPORT FALSE #endif +/* Define the default values for the FCH configuration settings */ +#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 +#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 +/* The AGESA likes to enable 512 bytes region on this base for LPC bus */ +#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 +#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 +#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 +#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 +#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 +#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 +#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 +#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 +#define DFLT_HPET_BASE_ADDRESS 0xFED00000 +#define DFLT_SMI_CMD_PORT 0xB0 +#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +#define DFLT_GEC_BASE_ADDRESS 0xFED61000 +#define DFLT_AZALIA_SSID 0x780D1022 +#define DFLT_SMBUS_SSID 0x780B1022 +#define DFLT_IDE_SSID 0x780C1022 +#define DFLT_SATA_AHCI_SSID 0x78011022 +#define DFLT_SATA_IDE_SSID 0x78001022 +#define DFLT_SATA_RAID5_SSID 0x78031022 +#define DFLT_SATA_RAID_SSID 0x78021022 +#define DFLT_EHCI_SSID 0x78081022 +#define DFLT_OHCI_SSID 0x78071022 +#define DFLT_LPC_SSID 0x780E1022 +#define DFLT_SD_SSID 0x78061022 +#define DFLT_XHCI_SSID 0x78121022 +#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE +#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE + +#define DFLT_FCH_GPP_LINK_CONFIG PortA4 +#define DFLT_FCH_GPP_PORT0_PRESENT FALSE +#define DFLT_FCH_GPP_PORT1_PRESENT FALSE +#define DFLT_FCH_GPP_PORT2_PRESENT FALSE +#define DFLT_FCH_GPP_PORT3_PRESENT FALSE + +#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE /* ACPI block register offset definitions */ #define PM1_STATUS_OFFSET 0x00 diff --git a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h index 1bca388000..8bdbb92165 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h @@ -424,6 +424,7 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define OPTION_NODE_INTERLEAVE FALSE #define OPTION_PARALLEL_TRAINING FALSE #define OPTION_ONLINE_SPARE FALSE +#define OPTION_ONLINE_SPARE_CAPABLE FALSE #define OPTION_MEM_RESTORE FALSE #define OPTION_DIMM_EXCLUDE FALSE @@ -503,8 +504,8 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define OPTION_PARALLEL_TRAINING TRUE #undef OPTION_MEM_RESTORE #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE + #undef OPTION_ONLINE_SPARE_CAPABLE + #define OPTION_ONLINE_SPARE_CAPABLE TRUE #undef OPTION_DIMM_EXCLUDE #define OPTION_DIMM_EXCLUDE TRUE #endif @@ -579,8 +580,8 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define OPTION_NODE_INTERLEAVE TRUE #undef OPTION_MEM_RESTORE #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE + #undef OPTION_ONLINE_SPARE_CAPABLE + #define OPTION_ONLINE_SPARE_CAPABLE TRUE #undef OPTION_DIMM_EXCLUDE #define OPTION_DIMM_EXCLUDE TRUE #endif @@ -640,8 +641,8 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define OPTION_PARALLEL_TRAINING TRUE #undef OPTION_MEM_RESTORE #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE + #undef OPTION_ONLINE_SPARE_CAPABLE + #define OPTION_ONLINE_SPARE_CAPABLE TRUE #undef OPTION_DIMM_EXCLUDE #define OPTION_DIMM_EXCLUDE TRUE #endif @@ -718,8 +719,8 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define OPTION_NODE_INTERLEAVE TRUE #undef OPTION_MEM_RESTORE #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE + #undef OPTION_ONLINE_SPARE_CAPABLE + #define OPTION_ONLINE_SPARE_CAPABLE TRUE #undef OPTION_DIMM_EXCLUDE #define OPTION_DIMM_EXCLUDE TRUE #endif @@ -767,8 +768,8 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define OPTION_PARALLEL_TRAINING TRUE #undef OPTION_MEM_RESTORE #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE + #undef OPTION_ONLINE_SPARE_CAPABLE + #define OPTION_ONLINE_SPARE_CAPABLE TRUE #undef OPTION_DIMM_EXCLUDE #define OPTION_DIMM_EXCLUDE TRUE #endif @@ -1123,8 +1124,8 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define OPTION_DCT_INTERLEAVE TRUE #undef OPTION_MEM_RESTORE #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE + #undef OPTION_ONLINE_SPARE_CAPABLE + #define OPTION_ONLINE_SPARE_CAPABLE TRUE #undef OPTION_DIMM_EXCLUDE #define OPTION_DIMM_EXCLUDE TRUE #endif @@ -1301,8 +1302,8 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define OPTION_PARALLEL_TRAINING TRUE #undef OPTION_MEM_RESTORE #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE + #undef OPTION_ONLINE_SPARE_CAPABLE + #define OPTION_ONLINE_SPARE_CAPABLE TRUE #undef OPTION_DIMM_EXCLUDE #define OPTION_DIMM_EXCLUDE TRUE #endif @@ -1367,8 +1368,8 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define OPTION_NODE_INTERLEAVE TRUE #undef OPTION_MEM_RESTORE #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE + #undef OPTION_ONLINE_SPARE_CAPABLE + #define OPTION_ONLINE_SPARE_CAPABLE TRUE #undef OPTION_DIMM_EXCLUDE #define OPTION_DIMM_EXCLUDE TRUE #endif @@ -1384,7 +1385,7 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define OPTION_ACPI_PSTATES TRUE #define OPTION_WHEA TRUE -#define OPTION_DMI TRUE +#define OPTION_DMI FALSE #define OPTION_EARLY_SAMPLES FALSE #define CFG_ACPI_PSTATES_PPC TRUE #define CFG_ACPI_PSTATES_PCT TRUE @@ -1392,7 +1393,7 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define CFG_ACPI_PSTATES_PSS TRUE #define CFG_ACPI_PSTATES_XPSS TRUE #define CFG_ACPI_PSTATE_PSD_INDPX FALSE -#define CFG_VRM_HIGH_SPEED_ENABLE FALSE +#define CFG_VRM_HIGH_SPEED_ENABLE TRUE #define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE #define OPTION_ALIB TRUE /*--------------------------------------------------------------------------- @@ -1464,10 +1465,11 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define OPTION_PARALLEL_TRAINING FALSE #endif #endif -#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT - #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE +/* Originally BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT, but inverted alongside the default value */ +#ifdef BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT + #if BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT == TRUE #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE FALSE + #define OPTION_ONLINE_SPARE OPTION_ONLINE_SPARE_CAPABLE #endif #endif #ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT @@ -1506,10 +1508,11 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define OPTION_WHEA FALSE #endif #endif -#ifdef BLDOPT_REMOVE_DMI - #if BLDOPT_REMOVE_DMI == TRUE +/* Originally BLDOPT_REMOVE_DMI, but inverted alongside the default value */ +#ifdef BLDOPT_ENABLE_DMI + #if BLDOPT_ENABLE_DMI == TRUE #undef OPTION_DMI - #define OPTION_DMI FALSE + #define OPTION_DMI TRUE #endif #endif #ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR @@ -1611,10 +1614,11 @@ static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #endif #endif -#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE - #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE +/* Originally BLDCFG_VRM_HIGH_SPEED_ENABLE, but inverted alongside the default value */ +#ifdef BLDCFG_VRM_HIGH_SPEED_DISABLE + #if BLDCFG_VRM_HIGH_SPEED_DISABLE == TRUE #undef CFG_VRM_HIGH_SPEED_ENABLE - #define CFG_VRM_HIGH_SPEED_ENABLE TRUE + #define CFG_VRM_HIGH_SPEED_ENABLE FALSE #endif #endif @@ -1762,7 +1766,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_VRM_CURRENT_LIMIT #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT #else - #define CFG_VRM_CURRENT_LIMIT 0 + #define CFG_VRM_CURRENT_LIMIT 90000 #endif #ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD @@ -1824,7 +1828,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_VRM_NB_CURRENT_LIMIT #define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT #else - #define CFG_VRM_NB_CURRENT_LIMIT (0) + #define CFG_VRM_NB_CURRENT_LIMIT (60000) #endif #ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD @@ -1842,7 +1846,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_PLAT_NUM_IO_APICS #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS #else - #define CFG_PLAT_NUM_IO_APICS 0 + #define CFG_PLAT_NUM_IO_APICS 3 #endif #ifdef BLDCFG_MEM_INIT_PSTATE @@ -1896,19 +1900,19 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS #else - #define CFG_CSTATE_IO_BASE_ADDRESS 0 + #define CFG_CSTATE_IO_BASE_ADDRESS 0x1770 #endif #ifdef BLDCFG_PLATFORM_CPB_MODE #define CFG_CPB_MODE BLDCFG_PLATFORM_CPB_MODE #else - #define CFG_CPB_MODE CpbModeAuto + #define CFG_CPB_MODE CpbModeDisabled #endif #ifdef BLDCFG_CORE_LEVELING_MODE #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE #else - #define CFG_CORE_LEVELING_MODE 0 + #define CFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #endif #ifdef BLDCFG_AMD_PSTATE_CAP_VALUE @@ -1926,7 +1930,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT #else - #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY + #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY #endif #ifdef BLDCFG_MEMORY_MODE_UNGANGED @@ -1998,13 +2002,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_MEMORY_POWER_DOWN #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN #else - #define CFG_MEMORY_POWER_DOWN FALSE + #define CFG_MEMORY_POWER_DOWN TRUE #endif #ifdef BLDCFG_POWER_DOWN_MODE #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE #else - #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO + #define CFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT #endif #ifdef BLDCFG_ONLINE_SPARE @@ -2034,7 +2038,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_MEMORY_CLOCK_SELECT #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT #else - #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY + #define CFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY #endif #ifdef BLDCFG_DQS_TRAINING_CONTROL @@ -2112,7 +2116,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_ECC_SYMBOL_SIZE #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE #else - #define CFG_ECC_SYMBOL_SIZE 0 + #define CFG_ECC_SYMBOL_SIZE 4 #endif #ifdef BLDCFG_1GB_ALIGN @@ -2148,7 +2152,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_UMA_ALIGNMENT #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT #else - #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED + #define CFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #endif #ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB @@ -2208,7 +2212,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL #define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL #else - #define CFG_LCD_BACK_LIGHT_CONTROL 0 + #define CFG_LCD_BACK_LIGHT_CONTROL 200 #endif #ifdef BLDCFG_STEREO_3D_PINOUT @@ -2273,10 +2277,11 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0 #endif +/* PCIe Spread Spectrum default value: 0.36% */ #ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM #else - #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 0 + #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 #endif #ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS @@ -2348,13 +2353,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON #else - #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 0 + #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 #endif #ifdef BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL #else - #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 0 + #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 #endif #ifdef BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h index 3e5137c655..a965a1d7d9 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h @@ -236,7 +236,7 @@ CpuLateInitApTask ( #endif #define SCOPE_NAME_VALUE OEM_SCOPE_NAME #else - #define SCOPE_NAME_VALUE SCOPE_NAME_C + #define SCOPE_NAME_VALUE SCOPE_NAME_P #endif // OEM_SCOPE_NAME #ifdef OEM_SCOPE_NAME1 diff --git a/src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h index 4725504159..64b71ef713 100644 --- a/src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h @@ -48,6 +48,47 @@ #define FCH_SUPPORT FALSE #endif +/* Define the default values for the FCH configuration settings */ +#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 +#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 +/* The AGESA likes to enable 512 bytes region on this base for LPC bus */ +#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 +#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 +#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 +#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 +#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 +#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 +#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 +#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 +#define DFLT_HPET_BASE_ADDRESS 0xFED00000 +#define DFLT_SMI_CMD_PORT 0xB0 +#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +#define DFLT_GEC_BASE_ADDRESS 0xFED61000 +#define DFLT_AZALIA_SSID 0x780D1022 +#define DFLT_SMBUS_SSID 0x780B1022 +#define DFLT_IDE_SSID 0x780C1022 +#define DFLT_SATA_AHCI_SSID 0x78011022 +#define DFLT_SATA_IDE_SSID 0x78001022 +#define DFLT_SATA_RAID5_SSID 0x78031022 +#define DFLT_SATA_RAID_SSID 0x78021022 +#define DFLT_EHCI_SSID 0x78081022 +#define DFLT_OHCI_SSID 0x78071022 +#define DFLT_LPC_SSID 0x780E1022 +#define DFLT_SD_SSID 0x78061022 +#define DFLT_XHCI_SSID 0x78121022 +#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE +#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE + +#define DFLT_FCH_GPP_LINK_CONFIG PortA4 +#define DFLT_FCH_GPP_PORT0_PRESENT FALSE +#define DFLT_FCH_GPP_PORT1_PRESENT FALSE +#define DFLT_FCH_GPP_PORT2_PRESENT FALSE +#define DFLT_FCH_GPP_PORT3_PRESENT FALSE + +#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE /* ACPI block register offset definitions */ #define PM1_STATUS_OFFSET 0x00 diff --git a/src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h index a648cc4ec3..7b1447199a 100644 --- a/src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h @@ -160,7 +160,7 @@ #ifdef BLDCFG_PCIE_TRAINING_ALGORITHM #define CFG_GNB_PCIE_TRAINING_ALGORITHM BLDCFG_PCIE_TRAINING_ALGORITHM #else - #define CFG_GNB_PCIE_TRAINING_ALGORITHM PcieTrainingStandard + #define CFG_GNB_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed #endif #ifndef CFG_GNB_FORCE_CABLESAFE_OFF @@ -871,7 +871,7 @@ #if (AGESA_ENTRY_INIT_S3SAVE == TRUE) //--------------------------------------------------------------------------------------------------- #ifndef OPTION_GFX_INIT_SVIEW - #define OPTION_GFX_INIT_SVIEW TRUE + #define OPTION_GFX_INIT_SVIEW FALSE #endif #if (OPTION_GFX_INIT_SVIEW == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE) OPTION_GNB_FEATURE GfxInitSview; diff --git a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h index 686dfb153a..4606443632 100644 --- a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h @@ -310,7 +310,7 @@ static const AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define OPTION_ACPI_PSTATES TRUE #define OPTION_WHEA TRUE -#define OPTION_DMI TRUE +#define OPTION_DMI FALSE #define OPTION_EARLY_SAMPLES FALSE #define CFG_ACPI_PSTATES_PPC TRUE #define CFG_ACPI_PSTATES_PCT TRUE @@ -318,7 +318,7 @@ static const AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define CFG_ACPI_PSTATES_PSS TRUE #define CFG_ACPI_PSTATES_XPSS TRUE #define CFG_ACPI_PSTATE_PSD_INDPX FALSE -#define CFG_VRM_HIGH_SPEED_ENABLE FALSE +#define CFG_VRM_HIGH_SPEED_ENABLE TRUE #define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE #define OPTION_ALIB TRUE /*--------------------------------------------------------------------------- @@ -393,10 +393,11 @@ static const AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define OPTION_PARALLEL_TRAINING FALSE #endif #endif -#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT - #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE +/* Originally BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT, but inverted alongside the default value */ +#ifdef BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT + #if BLDOPT_ENABLE_ONLINE_SPARE_SUPPORT == TRUE #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE FALSE + #define OPTION_ONLINE_SPARE TRUE #endif #endif #ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT @@ -447,10 +448,11 @@ static const AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define OPTION_WHEA FALSE #endif #endif -#ifdef BLDOPT_REMOVE_DMI - #if BLDOPT_REMOVE_DMI == TRUE +/* Originally BLDOPT_REMOVE_DMI, but inverted alongside the default value */ +#ifdef BLDOPT_ENABLE_DMI + #if BLDOPT_ENABLE_DMI == TRUE #undef OPTION_DMI - #define OPTION_DMI FALSE + #define OPTION_DMI TRUE #endif #endif #ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR @@ -601,10 +603,11 @@ static const AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define CFG_ACPI_PSTATES_PSD_POLICY PsdPolicyProcessorDefault #endif -#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE - #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE +/* Originally BLDCFG_VRM_HIGH_SPEED_ENABLE, but inverted alongside the default value */ +#ifdef BLDCFG_VRM_HIGH_SPEED_DISABLE + #if BLDCFG_VRM_HIGH_SPEED_DISABLE == TRUE #undef CFG_VRM_HIGH_SPEED_ENABLE - #define CFG_VRM_HIGH_SPEED_ENABLE TRUE + #define CFG_VRM_HIGH_SPEED_ENABLE FALSE #endif #endif @@ -752,7 +755,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_VRM_CURRENT_LIMIT #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT #else - #define CFG_VRM_CURRENT_LIMIT 0 + #define CFG_VRM_CURRENT_LIMIT 15000 #endif #ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD @@ -764,37 +767,37 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_VRM_SLEW_RATE #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE #else - #define CFG_VRM_SLEW_RATE (5000) + #define CFG_VRM_SLEW_RATE (10000) #endif #ifdef BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT #define CFG_VRM_MAXIMUM_CURRENT_LIMIT BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT #else - #define CFG_VRM_MAXIMUM_CURRENT_LIMIT (0) + #define CFG_VRM_MAXIMUM_CURRENT_LIMIT (21000) #endif #ifdef BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT #else - #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT (0) + #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT (17000) #endif #ifdef BLDCFG_VRM_SVI_OCP_LEVEL #define CFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_SVI_OCP_LEVEL #else - #define CFG_VRM_SVI_OCP_LEVEL 0 + #define CFG_VRM_SVI_OCP_LEVEL CFG_VRM_MAXIMUM_CURRENT_LIMIT #endif #ifdef BLDCFG_VRM_NB_SVI_OCP_LEVEL #define CFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_SVI_OCP_LEVEL #else - #define CFG_VRM_NB_SVI_OCP_LEVEL 0 + #define CFG_VRM_NB_SVI_OCP_LEVEL CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT #endif #ifdef BLDCFG_VRM_NB_CURRENT_LIMIT #define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT #else - #define CFG_VRM_NB_CURRENT_LIMIT (0) + #define CFG_VRM_NB_CURRENT_LIMIT (13000) #endif #ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD @@ -806,13 +809,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_VRM_NB_SLEW_RATE #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE #else - #define CFG_VRM_NB_SLEW_RATE (5000) + #define CFG_VRM_NB_SLEW_RATE CFG_VRM_SLEW_RATE #endif #ifdef BLDCFG_PLAT_NUM_IO_APICS #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS #else - #define CFG_PLAT_NUM_IO_APICS 0 + #define CFG_PLAT_NUM_IO_APICS 3 #endif #ifdef BLDCFG_MEM_INIT_PSTATE @@ -854,19 +857,19 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_PLATFORM_CSTATE_MODE #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE #else - #define CFG_CSTATE_MODE CStateModeC6 + #define CFG_CSTATE_MODE CStateModeDisabled #endif #ifdef BLDCFG_PLATFORM_CSTATE_OPDATA #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA #else - #define CFG_CSTATE_OPDATA 0 + #define CFG_CSTATE_OPDATA 0x1770 #endif #ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS #else - #define CFG_CSTATE_IO_BASE_ADDRESS 0 + #define CFG_CSTATE_IO_BASE_ADDRESS 0x1770 #endif #ifdef BLDCFG_PLATFORM_CPB_MODE @@ -878,7 +881,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_CORE_LEVELING_MODE #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE #else - #define CFG_CORE_LEVELING_MODE 0 + #define CFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #endif #ifdef BLDCFG_AMD_TDP_LIMIT @@ -896,7 +899,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT #else - #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY + #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY #endif #ifdef BLDCFG_MEMORY_MODE_UNGANGED @@ -968,13 +971,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_MEMORY_POWER_DOWN #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN #else - #define CFG_MEMORY_POWER_DOWN FALSE + #define CFG_MEMORY_POWER_DOWN TRUE #endif #ifdef BLDCFG_POWER_DOWN_MODE #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE #else - #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO + #define CFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT #endif #ifdef BLDCFG_ONLINE_SPARE @@ -1004,7 +1007,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_MEMORY_CLOCK_SELECT #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT #else - #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY + #define CFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY #endif #ifdef BLDCFG_DQS_TRAINING_CONTROL @@ -1082,7 +1085,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_ECC_SYMBOL_SIZE #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE #else - #define CFG_ECC_SYMBOL_SIZE 0 + #define CFG_ECC_SYMBOL_SIZE 4 #endif #ifdef BLDCFG_1GB_ALIGN @@ -1118,7 +1121,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_UMA_ALIGNMENT #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT #else - #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED + #define CFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #endif #ifdef BLDCFG_DIMM_TYPE_USED_IN_MIXED_CONFIG @@ -1172,7 +1175,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_CFG_ABM_SUPPORT #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT #else - #define CFG_ABM_SUPPORT FALSE + #define CFG_ABM_SUPPORT TRUE #endif #ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE @@ -1468,7 +1471,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_GNB_IOAPIC_ADDRESS #define CFG_GNB_IOAPIC_ADDRESS BLDCFG_GNB_IOAPIC_ADDRESS #else - #define CFG_GNB_IOAPIC_ADDRESS NULL + #define CFG_GNB_IOAPIC_ADDRESS 0xFEC20000 #endif #ifdef BLDCFG_GNB_IOMMU_ADDRESS diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h index b27ed00057..00ea0d7e9b 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h @@ -229,7 +229,7 @@ AGESA_FORWARD_DECLARATION (PROC_FAMILY_TABLE); #endif #define SCOPE_NAME_VALUE OEM_SCOPE_NAME #else - #define SCOPE_NAME_VALUE SCOPE_NAME_C + #define SCOPE_NAME_VALUE SCOPE_NAME_P #endif // OEM_SCOPE_NAME #ifdef OEM_SCOPE_NAME1 From db0d949380beb37c0dcb5256c9c6682c564f2ebb Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 24 May 2020 10:54:40 +0200 Subject: [PATCH 400/405] mb/asrock/e350m1: Do not redefine AGESA_VERSION_STRING This is the only AGESA f14 board which has a different version string. As it is most likely a copy-paste error, drop the redefinition of this macro from buildOpts.c and use the value defined in AGESA f14 headers. Change-Id: I384bd96db51457e68a320b99ecdbb2ada0dfbdd5 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41621 Tested-by: build bot (Jenkins) Reviewed-by: Mike Banon Reviewed-by: Paul Menzel --- src/mainboard/asrock/e350m1/buildOpts.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index 7a2cc3b499..1c4d62c250 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -38,11 +38,5 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* FIXME: This is most likely wrong */ -#undef AGESA_VERSION_STRING - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} - /* Instantiate all solution relevant data */ #include From 95d429b1cd0c2ac9f29e55d78f3f50bd6f4f72e2 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 29 May 2020 00:03:57 +0200 Subject: [PATCH 401/405] mb/asrock/b85m_pro4/cmos.layout: Remove copyright notices Change-Id: I2aaabec17073c0a2ccd40de068223a9215186db3 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41834 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Arthur Heymans --- src/mainboard/asrock/b85m_pro4/cmos.layout | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout index 5b9157c539..ed022330dd 100644 --- a/src/mainboard/asrock/b85m_pro4/cmos.layout +++ b/src/mainboard/asrock/b85m_pro4/cmos.layout @@ -1,8 +1,3 @@ -## -## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko -## ## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- From 4b975bb79fb438c4451eda88a2fcf1c09e074a00 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 30 May 2020 20:05:37 +0200 Subject: [PATCH 402/405] soc/intel/common/block: Remove unused headers Change-Id: I8877a70661cacc57ea893da172d9a4b6d19ba06a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41926 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: HAOUAS Elyes --- src/soc/intel/common/block/cpu/cpulib.c | 4 ---- src/soc/intel/common/block/power_limit/power_limit.c | 1 - 2 files changed, 5 deletions(-) diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index c39b453d12..7201432301 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -9,10 +9,6 @@ #include #include #include -#include -#include -#include -#include #include /* diff --git a/src/soc/intel/common/block/power_limit/power_limit.c b/src/soc/intel/common/block/power_limit/power_limit.c index 2ac82b3d3d..e6c65c3a82 100644 --- a/src/soc/intel/common/block/power_limit/power_limit.c +++ b/src/soc/intel/common/block/power_limit/power_limit.c @@ -5,7 +5,6 @@ #include #include #include -#include #include /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ From d49690bbe87134a67dc9efab11eadc96944fa15f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 29 May 2020 00:01:27 +0200 Subject: [PATCH 403/405] src: Fix up ##-commented SPDX headers Delete leading empty comment lines. Change-Id: If1c5f568af3290c329d22dfc054d10d01c079065 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41833 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Arthur Heymans --- src/vendorcode/cavium/Kconfig | 3 --- src/vendorcode/cavium/Makefile.inc | 3 --- src/vendorcode/eltan/security/Kconfig | 2 -- src/vendorcode/eltan/security/Makefile.inc | 2 -- src/vendorcode/eltan/security/mboot/Kconfig | 2 -- src/vendorcode/eltan/security/mboot/Makefile.inc | 3 --- src/vendorcode/eltan/security/verified_boot/Kconfig | 2 -- src/vendorcode/eltan/security/verified_boot/Makefile.inc | 3 --- src/vendorcode/google/Kconfig | 2 -- src/vendorcode/google/Makefile.inc | 3 --- src/vendorcode/google/chromeos/Kconfig | 2 -- src/vendorcode/google/chromeos/Makefile.inc | 3 --- src/vendorcode/intel/Kconfig | 3 --- src/vendorcode/intel/Makefile.inc | 3 --- src/vendorcode/siemens/Kconfig | 3 --- src/vendorcode/siemens/Makefile.inc | 3 --- src/vendorcode/siemens/hwilib/Makefile.inc | 3 --- 17 files changed, 45 deletions(-) diff --git a/src/vendorcode/cavium/Kconfig b/src/vendorcode/cavium/Kconfig index ca32157568..15b9ef598d 100644 --- a/src/vendorcode/cavium/Kconfig +++ b/src/vendorcode/cavium/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only config CAVIUM_BDK diff --git a/src/vendorcode/cavium/Makefile.inc b/src/vendorcode/cavium/Makefile.inc index cfe4c25447..bf2fe0458d 100644 --- a/src/vendorcode/cavium/Makefile.inc +++ b/src/vendorcode/cavium/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_CAVIUM_BDK),y) diff --git a/src/vendorcode/eltan/security/Kconfig b/src/vendorcode/eltan/security/Kconfig index 45a6fba7e6..0d8d04cd84 100644 --- a/src/vendorcode/eltan/security/Kconfig +++ b/src/vendorcode/eltan/security/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only config USE_VENDORCODE_ELTAN diff --git a/src/vendorcode/eltan/security/Makefile.inc b/src/vendorcode/eltan/security/Makefile.inc index d9c40efb56..7db68c87c9 100644 --- a/src/vendorcode/eltan/security/Makefile.inc +++ b/src/vendorcode/eltan/security/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only subdirs-y += verified_boot diff --git a/src/vendorcode/eltan/security/mboot/Kconfig b/src/vendorcode/eltan/security/mboot/Kconfig index 9563ae0e0a..91898fc401 100644 --- a/src/vendorcode/eltan/security/mboot/Kconfig +++ b/src/vendorcode/eltan/security/mboot/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only menu "Measured Boot (mboot)" diff --git a/src/vendorcode/eltan/security/mboot/Makefile.inc b/src/vendorcode/eltan/security/mboot/Makefile.inc index b8c60207a0..22729aff36 100644 --- a/src/vendorcode/eltan/security/mboot/Makefile.inc +++ b/src/vendorcode/eltan/security/mboot/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBOOT)),) diff --git a/src/vendorcode/eltan/security/verified_boot/Kconfig b/src/vendorcode/eltan/security/verified_boot/Kconfig index 2c29107ca1..11574dd543 100644 --- a/src/vendorcode/eltan/security/verified_boot/Kconfig +++ b/src/vendorcode/eltan/security/verified_boot/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only menu "Verified Boot (verified_boot)" diff --git a/src/vendorcode/eltan/security/verified_boot/Makefile.inc b/src/vendorcode/eltan/security/verified_boot/Makefile.inc index 3ed4da3e11..9158760322 100644 --- a/src/vendorcode/eltan/security/verified_boot/Makefile.inc +++ b/src/vendorcode/eltan/security/verified_boot/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBOOT)),) diff --git a/src/vendorcode/google/Kconfig b/src/vendorcode/google/Kconfig index be1f32c035..60c0c228a7 100644 --- a/src/vendorcode/google/Kconfig +++ b/src/vendorcode/google/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only source "src/vendorcode/google/chromeos/Kconfig" diff --git a/src/vendorcode/google/Makefile.inc b/src/vendorcode/google/Makefile.inc index 1e0164b020..c67ea20268 100644 --- a/src/vendorcode/google/Makefile.inc +++ b/src/vendorcode/google/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only subdirs-$(CONFIG_CHROMEOS) += chromeos diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 8621e6641f..f48069ff86 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only config MAINBOARD_HAS_CHROMEOS diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index fc0037496a..a25700f8bb 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_ELOG) += elog.c diff --git a/src/vendorcode/intel/Kconfig b/src/vendorcode/intel/Kconfig index a0f9b7aff2..8612ebab7e 100644 --- a/src/vendorcode/intel/Kconfig +++ b/src/vendorcode/intel/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only config UEFI_2_4_BINDING diff --git a/src/vendorcode/intel/Makefile.inc b/src/vendorcode/intel/Makefile.inc index 41c1882ad0..d08ae2ac96 100644 --- a/src/vendorcode/intel/Makefile.inc +++ b/src/vendorcode/intel/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_UEFI_2_4_BINDING),y) diff --git a/src/vendorcode/siemens/Kconfig b/src/vendorcode/siemens/Kconfig index f1df8194c5..d7c16ff920 100644 --- a/src/vendorcode/siemens/Kconfig +++ b/src/vendorcode/siemens/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only config USE_SIEMENS_HWILIB diff --git a/src/vendorcode/siemens/Makefile.inc b/src/vendorcode/siemens/Makefile.inc index 40623dc8c0..88fd1c3911 100644 --- a/src/vendorcode/siemens/Makefile.inc +++ b/src/vendorcode/siemens/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only subdirs-$(CONFIG_USE_SIEMENS_HWILIB) += hwilib diff --git a/src/vendorcode/siemens/hwilib/Makefile.inc b/src/vendorcode/siemens/hwilib/Makefile.inc index b4152c17a5..2456db2427 100644 --- a/src/vendorcode/siemens/hwilib/Makefile.inc +++ b/src/vendorcode/siemens/hwilib/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only CFLAGS_x86_32 += -Isrc/vendorcode/siemens/hwilib From d5d4fbc072c489e469df2c703a289be0d5f3bbac Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 31 May 2020 01:03:59 +0200 Subject: [PATCH 404/405] sb/intel/lynxpoint: Restore lost PCI_COMMAND_MASTER bits Commit 73ae076 "fixed" accesses to the PCI command register that were not 16 bits, but also lost some bits to be written in the process. Change-Id: I4eb62a0433a4563827a69c9e39c17ddd2eb8cd23 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41945 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Matt DeVillier --- src/southbridge/intel/lynxpoint/early_usb.c | 2 +- src/southbridge/intel/lynxpoint/me_9.x.c | 2 +- src/southbridge/intel/lynxpoint/serialio.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c index 06ddd0821d..a753681ce0 100644 --- a/src/southbridge/intel/lynxpoint/early_usb.c +++ b/src/southbridge/intel/lynxpoint/early_usb.c @@ -25,7 +25,7 @@ static void enable_usb_bar_on_device(pci_devfn_t dev, u32 bar) { pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar); - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } void enable_usb_bar(void) diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 8914edf9ce..6223a3d583 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -735,7 +735,7 @@ static int intel_mei_setup(struct device *dev) mei_base_address = (u32 *)(uintptr_t)res->base; /* Ensure Memory and Bus Master bits are set */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* Clean up status for next message */ read_host_csr(&host); diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index e093508e01..adb9067dbc 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -137,7 +137,7 @@ static void serialio_init(struct device *dev) printk(BIOS_DEBUG, "Initializing Serial IO device\n"); /* Ensure memory and bus master are enabled */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* Find BAR0 and BAR1 */ bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); From 8d09a06aa6ad92f7e31a38ccdc42ecbbe2d45e00 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 29 May 2020 00:09:00 +0200 Subject: [PATCH 405/405] src: Fix up #-commented SPDX headers Delete leading empty comment lines. Change-Id: I8e14a0ad1e1e2227e4fb201f5d157f56f289f286 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41838 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Arthur Heymans --- src/mainboard/amd/inagua/cmos.layout | 3 --- src/mainboard/amd/olivehill/cmos.layout | 3 --- src/mainboard/amd/parmer/cmos.layout | 3 --- src/mainboard/amd/persimmon/cmos.layout | 3 --- src/mainboard/amd/south_station/cmos.layout | 3 --- src/mainboard/amd/thatcher/cmos.layout | 3 --- src/mainboard/amd/union_station/cmos.layout | 3 --- src/mainboard/asrock/e350m1/cmos.layout | 3 --- src/mainboard/asrock/imb-a180/cmos.layout | 3 --- src/mainboard/asus/am1i-a/cmos.layout | 3 --- src/mainboard/asus/f2a85-m/cmos.layout | 3 --- src/mainboard/bap/ode_e20XX/cmos.layout | 3 --- src/mainboard/bap/ode_e21XX/cmos.layout | 3 --- src/mainboard/biostar/a68n_5200/cmos.layout | 3 --- src/mainboard/biostar/am1ml/cmos.layout | 3 --- src/mainboard/elmex/pcm205400/cmos.layout | 3 --- src/mainboard/gizmosphere/gizmo/cmos.layout | 3 --- src/mainboard/gizmosphere/gizmo2/cmos.layout | 3 --- src/mainboard/google/foster/bct/cfg2inc.sh | 3 --- src/mainboard/google/nyan/bct/cfg2inc.sh | 3 --- src/mainboard/google/smaug/bct/cfg2inc.sh | 3 --- src/mainboard/hp/abm/cmos.layout | 3 --- src/mainboard/jetway/nf81-t56n-lf/cmos.layout | 3 --- src/mainboard/lenovo/g505s/cmos.layout | 3 --- src/mainboard/lippert/frontrunner-af/cmos.layout | 3 --- src/mainboard/lippert/toucan-af/cmos.layout | 3 --- src/mainboard/msi/ms7721/cmos.layout | 3 --- src/mainboard/pcengines/apu2/cmos.layout | 3 --- src/vendorcode/amd/Kconfig | 3 --- src/vendorcode/amd/cimx/sb800/Makefile.inc | 2 -- src/vendorcode/amd/cimx/sb900/Makefile.inc | 2 -- src/vendorcode/eltan/Makefile.inc | 3 --- 32 files changed, 94 deletions(-) diff --git a/src/mainboard/amd/inagua/cmos.layout b/src/mainboard/amd/inagua/cmos.layout index 19efc38627..beedaa7930 100644 --- a/src/mainboard/amd/inagua/cmos.layout +++ b/src/mainboard/amd/inagua/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/mainboard/amd/olivehill/cmos.layout b/src/mainboard/amd/olivehill/cmos.layout index d450f6c5a1..ade4c04bf3 100644 --- a/src/mainboard/amd/olivehill/cmos.layout +++ b/src/mainboard/amd/olivehill/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/mainboard/amd/parmer/cmos.layout b/src/mainboard/amd/parmer/cmos.layout index d450f6c5a1..ade4c04bf3 100644 --- a/src/mainboard/amd/parmer/cmos.layout +++ b/src/mainboard/amd/parmer/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/mainboard/amd/persimmon/cmos.layout b/src/mainboard/amd/persimmon/cmos.layout index 19efc38627..beedaa7930 100644 --- a/src/mainboard/amd/persimmon/cmos.layout +++ b/src/mainboard/amd/persimmon/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/mainboard/amd/south_station/cmos.layout b/src/mainboard/amd/south_station/cmos.layout index 19efc38627..beedaa7930 100644 --- a/src/mainboard/amd/south_station/cmos.layout +++ b/src/mainboard/amd/south_station/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/mainboard/amd/thatcher/cmos.layout b/src/mainboard/amd/thatcher/cmos.layout index d450f6c5a1..ade4c04bf3 100644 --- a/src/mainboard/amd/thatcher/cmos.layout +++ b/src/mainboard/amd/thatcher/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/mainboard/amd/union_station/cmos.layout b/src/mainboard/amd/union_station/cmos.layout index 19efc38627..beedaa7930 100644 --- a/src/mainboard/amd/union_station/cmos.layout +++ b/src/mainboard/amd/union_station/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/mainboard/asrock/e350m1/cmos.layout b/src/mainboard/asrock/e350m1/cmos.layout index 390c94c300..75526c6227 100644 --- a/src/mainboard/asrock/e350m1/cmos.layout +++ b/src/mainboard/asrock/e350m1/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/mainboard/asrock/imb-a180/cmos.layout b/src/mainboard/asrock/imb-a180/cmos.layout index d450f6c5a1..ade4c04bf3 100644 --- a/src/mainboard/asrock/imb-a180/cmos.layout +++ b/src/mainboard/asrock/imb-a180/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/mainboard/asus/am1i-a/cmos.layout b/src/mainboard/asus/am1i-a/cmos.layout index 7dcd7986e9..9f9ee80faa 100644 --- a/src/mainboard/asus/am1i-a/cmos.layout +++ b/src/mainboard/asus/am1i-a/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/mainboard/asus/f2a85-m/cmos.layout b/src/mainboard/asus/f2a85-m/cmos.layout index d450f6c5a1..ade4c04bf3 100644 --- a/src/mainboard/asus/f2a85-m/cmos.layout +++ b/src/mainboard/asus/f2a85-m/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/mainboard/bap/ode_e20XX/cmos.layout b/src/mainboard/bap/ode_e20XX/cmos.layout index d450f6c5a1..ade4c04bf3 100644 --- a/src/mainboard/bap/ode_e20XX/cmos.layout +++ b/src/mainboard/bap/ode_e20XX/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/mainboard/bap/ode_e21XX/cmos.layout b/src/mainboard/bap/ode_e21XX/cmos.layout index d450f6c5a1..ade4c04bf3 100644 --- a/src/mainboard/bap/ode_e21XX/cmos.layout +++ b/src/mainboard/bap/ode_e21XX/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/mainboard/biostar/a68n_5200/cmos.layout b/src/mainboard/biostar/a68n_5200/cmos.layout index d450f6c5a1..ade4c04bf3 100644 --- a/src/mainboard/biostar/a68n_5200/cmos.layout +++ b/src/mainboard/biostar/a68n_5200/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/mainboard/biostar/am1ml/cmos.layout b/src/mainboard/biostar/am1ml/cmos.layout index c42e3b0897..0cf4ede05a 100644 --- a/src/mainboard/biostar/am1ml/cmos.layout +++ b/src/mainboard/biostar/am1ml/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/mainboard/elmex/pcm205400/cmos.layout b/src/mainboard/elmex/pcm205400/cmos.layout index 138b75d5d9..bc5b428588 100644 --- a/src/mainboard/elmex/pcm205400/cmos.layout +++ b/src/mainboard/elmex/pcm205400/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/mainboard/gizmosphere/gizmo/cmos.layout b/src/mainboard/gizmosphere/gizmo/cmos.layout index 19efc38627..beedaa7930 100644 --- a/src/mainboard/gizmosphere/gizmo/cmos.layout +++ b/src/mainboard/gizmosphere/gizmo/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/mainboard/gizmosphere/gizmo2/cmos.layout b/src/mainboard/gizmosphere/gizmo2/cmos.layout index d450f6c5a1..ade4c04bf3 100644 --- a/src/mainboard/gizmosphere/gizmo2/cmos.layout +++ b/src/mainboard/gizmosphere/gizmo2/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/mainboard/google/foster/bct/cfg2inc.sh b/src/mainboard/google/foster/bct/cfg2inc.sh index 6fd8d2f111..46c4922185 100644 --- a/src/mainboard/google/foster/bct/cfg2inc.sh +++ b/src/mainboard/google/foster/bct/cfg2inc.sh @@ -1,7 +1,4 @@ #!/bin/sh -# -# -# # SPDX-License-Identifier: GPL-2.0-only bct_cfg2inc() { diff --git a/src/mainboard/google/nyan/bct/cfg2inc.sh b/src/mainboard/google/nyan/bct/cfg2inc.sh index 6fd8d2f111..46c4922185 100755 --- a/src/mainboard/google/nyan/bct/cfg2inc.sh +++ b/src/mainboard/google/nyan/bct/cfg2inc.sh @@ -1,7 +1,4 @@ #!/bin/sh -# -# -# # SPDX-License-Identifier: GPL-2.0-only bct_cfg2inc() { diff --git a/src/mainboard/google/smaug/bct/cfg2inc.sh b/src/mainboard/google/smaug/bct/cfg2inc.sh index 6fd8d2f111..46c4922185 100644 --- a/src/mainboard/google/smaug/bct/cfg2inc.sh +++ b/src/mainboard/google/smaug/bct/cfg2inc.sh @@ -1,7 +1,4 @@ #!/bin/sh -# -# -# # SPDX-License-Identifier: GPL-2.0-only bct_cfg2inc() { diff --git a/src/mainboard/hp/abm/cmos.layout b/src/mainboard/hp/abm/cmos.layout index d450f6c5a1..ade4c04bf3 100644 --- a/src/mainboard/hp/abm/cmos.layout +++ b/src/mainboard/hp/abm/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/mainboard/jetway/nf81-t56n-lf/cmos.layout b/src/mainboard/jetway/nf81-t56n-lf/cmos.layout index 19efc38627..beedaa7930 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/cmos.layout +++ b/src/mainboard/jetway/nf81-t56n-lf/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/mainboard/lenovo/g505s/cmos.layout b/src/mainboard/lenovo/g505s/cmos.layout index 1b3363a7aa..fa4f10be44 100644 --- a/src/mainboard/lenovo/g505s/cmos.layout +++ b/src/mainboard/lenovo/g505s/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/mainboard/lippert/frontrunner-af/cmos.layout b/src/mainboard/lippert/frontrunner-af/cmos.layout index 19efc38627..beedaa7930 100644 --- a/src/mainboard/lippert/frontrunner-af/cmos.layout +++ b/src/mainboard/lippert/frontrunner-af/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/mainboard/lippert/toucan-af/cmos.layout b/src/mainboard/lippert/toucan-af/cmos.layout index 19efc38627..beedaa7930 100644 --- a/src/mainboard/lippert/toucan-af/cmos.layout +++ b/src/mainboard/lippert/toucan-af/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/mainboard/msi/ms7721/cmos.layout b/src/mainboard/msi/ms7721/cmos.layout index d450f6c5a1..ade4c04bf3 100644 --- a/src/mainboard/msi/ms7721/cmos.layout +++ b/src/mainboard/msi/ms7721/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/mainboard/pcengines/apu2/cmos.layout b/src/mainboard/pcengines/apu2/cmos.layout index 98b5c09fa9..8663fcc1ae 100644 --- a/src/mainboard/pcengines/apu2/cmos.layout +++ b/src/mainboard/pcengines/apu2/cmos.layout @@ -1,7 +1,4 @@ #***************************************************************************** -# -# -# # SPDX-License-Identifier: GPL-2.0-only #***************************************************************************** diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig index 812217c1d3..e080170bf5 100644 --- a/src/vendorcode/amd/Kconfig +++ b/src/vendorcode/amd/Kconfig @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only if CPU_AMD_AGESA || CPU_AMD_PI || SOC_AMD_PI diff --git a/src/vendorcode/amd/cimx/sb800/Makefile.inc b/src/vendorcode/amd/cimx/sb800/Makefile.inc index 5e95ac801e..8eb72fab29 100644 --- a/src/vendorcode/amd/cimx/sb800/Makefile.inc +++ b/src/vendorcode/amd/cimx/sb800/Makefile.inc @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only CPPFLAGS_x86_32 += -I$(src)/southbridge/amd/cimx/sb800 diff --git a/src/vendorcode/amd/cimx/sb900/Makefile.inc b/src/vendorcode/amd/cimx/sb900/Makefile.inc index f7dedaaba0..416df7e214 100644 --- a/src/vendorcode/amd/cimx/sb900/Makefile.inc +++ b/src/vendorcode/amd/cimx/sb900/Makefile.inc @@ -1,5 +1,3 @@ -# -# # SPDX-License-Identifier: GPL-2.0-only CPPFLAGS_x86_32 += -I$(src)/southbridge/amd/cimx/sb900 diff --git a/src/vendorcode/eltan/Makefile.inc b/src/vendorcode/eltan/Makefile.inc index 1cc43a2cc4..4195d95758 100644 --- a/src/vendorcode/eltan/Makefile.inc +++ b/src/vendorcode/eltan/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only subdirs-y += security