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cpu/intel/common: rework code previously moved to common cpu code

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Rework the code moved to common code in CB:46274. This involves
simplification by using appropriate helpers for MSR and CPUID, using
macros instead of plain values for MSRs and cpu features and adding
documentation to the header.

Change-Id: I7615fc26625c44931577216ea42f0a733b99e131
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Michael Niewöhner
2020-10-20 14:27:09 +02:00
committed by Nico Huber
parent 10ae1cf2cd
commit 062b92ef65
4 changed files with 18 additions and 28 deletions
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1
src/include/cpu/intel/msr.h
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@@ -10,5 +10,6 @@
#define AESNI_LOCK (1 << 0)
#define MSR_PIC_MSG_CONTROL 0x2e
#define TPR_UPDATES_DISABLE (1 << 10)
#endif /* CPU_INTEL_MSR_H */

3
src/include/cpu/x86/msr.h
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@@ -48,11 +48,12 @@
#define ENERGY_POLICY_PERFORMANCE 0
#define ENERGY_POLICY_NORMAL 6
#define ENERGY_POLICY_POWERSAVE 15
#define ENERGY_POLICY_MASK 0xf
#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define SMRR_PHYSBASE_MSR 0x1F2
#define SMRR_PHYSMASK_MSR 0x1F3
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define DCA_TYPE0_EN (1 << 0)
#define IA32_PAT 0x277
#define IA32_MC0_CTL 0x400
#define IA32_MC0_STATUS 0x401