vc/intel/fsp: Change line endings to unix
These files have windows line endings. Change to unix to match the rest of the tree. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5bb3338745a6a47b6714aa268d16866aada27790 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Martin Roth
Martin Roth
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@ -1,68 +1,68 @@
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/** @file
|
/** @file
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||||||
Header file for Firmware Version Information
|
Header file for Firmware Version Information
|
||||||
|
|
||||||
@copyright
|
@copyright
|
||||||
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
|
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
|
||||||
|
|
||||||
This program and the accompanying materials are licensed and made available under
|
This program and the accompanying materials are licensed and made available under
|
||||||
the terms and conditions of the BSD License which accompanies this distribution.
|
the terms and conditions of the BSD License which accompanies this distribution.
|
||||||
The full text of the license may be found at
|
The full text of the license may be found at
|
||||||
http://opensource.org/licenses/bsd-license.php
|
http://opensource.org/licenses/bsd-license.php
|
||||||
|
|
||||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||||
|
|
||||||
**/
|
**/
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||||||
|
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||||||
#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
|
#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
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#define _FIRMWARE_VERSION_INFO_HOB_H_
|
#define _FIRMWARE_VERSION_INFO_HOB_H_
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|
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#include <Uefi/UefiMultiPhase.h>
|
#include <Uefi/UefiMultiPhase.h>
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#include <Pi/PiBootMode.h>
|
#include <Pi/PiBootMode.h>
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#include <Pi/PiHob.h>
|
#include <Pi/PiHob.h>
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|
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||||||
#pragma pack(1)
|
#pragma pack(1)
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///
|
///
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/// Firmware Version Structure
|
/// Firmware Version Structure
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||||||
///
|
///
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||||||
typedef struct {
|
typedef struct {
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UINT8 MajorVersion;
|
UINT8 MajorVersion;
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UINT8 MinorVersion;
|
UINT8 MinorVersion;
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||||||
UINT8 Revision;
|
UINT8 Revision;
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||||||
UINT16 BuildNumber;
|
UINT16 BuildNumber;
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||||||
} FIRMWARE_VERSION;
|
} FIRMWARE_VERSION;
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|
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||||||
///
|
///
|
||||||
/// Firmware Version Information Structure
|
/// Firmware Version Information Structure
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||||||
///
|
///
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||||||
typedef struct {
|
typedef struct {
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UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
|
UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
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UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
|
UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
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FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
|
FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
|
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} FIRMWARE_VERSION_INFO;
|
} FIRMWARE_VERSION_INFO;
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|
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#ifndef __SMBIOS_STANDARD_H__
|
#ifndef __SMBIOS_STANDARD_H__
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///
|
///
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||||||
/// The Smbios structure header.
|
/// The Smbios structure header.
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///
|
///
|
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typedef struct {
|
typedef struct {
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UINT8 Type;
|
UINT8 Type;
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||||||
UINT8 Length;
|
UINT8 Length;
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UINT16 Handle;
|
UINT16 Handle;
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||||||
} SMBIOS_STRUCTURE;
|
} SMBIOS_STRUCTURE;
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#endif
|
#endif
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|
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///
|
///
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||||||
/// Firmware Version Information HOB Structure
|
/// Firmware Version Information HOB Structure
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///
|
///
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typedef struct {
|
typedef struct {
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EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
|
EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
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SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
|
SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
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UINT8 Count; ///< Offset 28 Number of FVI elements included.
|
UINT8 Count; ///< Offset 28 Number of FVI elements included.
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///
|
///
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/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
|
/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
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///
|
///
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} FIRMWARE_VERSION_INFO_HOB;
|
} FIRMWARE_VERSION_INFO_HOB;
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#pragma pack()
|
#pragma pack()
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|
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#endif // _FIRMWARE_VERSION_INFO_HOB_H_
|
#endif // _FIRMWARE_VERSION_INFO_HOB_H_
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@ -1,48 +1,48 @@
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/** @file
|
/** @file
|
||||||
|
|
||||||
Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
|
Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
* Redistributions of source code must retain the above copyright notice, this
|
* Redistributions of source code must retain the above copyright notice, this
|
||||||
list of conditions and the following disclaimer.
|
list of conditions and the following disclaimer.
|
||||||
* Redistributions in binary form must reproduce the above copyright notice, this
|
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||||
list of conditions and the following disclaimer in the documentation and/or
|
list of conditions and the following disclaimer in the documentation and/or
|
||||||
other materials provided with the distribution.
|
other materials provided with the distribution.
|
||||||
* Neither the name of Intel Corporation nor the names of its contributors may
|
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||||
be used to endorse or promote products derived from this software without
|
be used to endorse or promote products derived from this software without
|
||||||
specific prior written permission.
|
specific prior written permission.
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||||
THE POSSIBILITY OF SUCH DAMAGE.
|
THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
|
||||||
This file is automatically generated. Please do NOT modify !!!
|
This file is automatically generated. Please do NOT modify !!!
|
||||||
|
|
||||||
**/
|
**/
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|
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#ifndef __FSPUPD_H__
|
#ifndef __FSPUPD_H__
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#define __FSPUPD_H__
|
#define __FSPUPD_H__
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|
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#include <FspEas.h>
|
#include <FspEas.h>
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|
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#pragma pack(1)
|
#pragma pack(1)
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|
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#define FSPT_UPD_SIGNATURE 0x545F4450554C4845 /* 'EHLUPD_T' */
|
#define FSPT_UPD_SIGNATURE 0x545F4450554C4845 /* 'EHLUPD_T' */
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|
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#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4845 /* 'EHLUPD_M' */
|
#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4845 /* 'EHLUPD_M' */
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|
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#define FSPS_UPD_SIGNATURE 0x535F4450554C4845 /* 'EHLUPD_S' */
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#define FSPS_UPD_SIGNATURE 0x535F4450554C4845 /* 'EHLUPD_S' */
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|
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#pragma pack()
|
#pragma pack()
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|
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#endif
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#endif
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/** @file
|
/** @file
|
||||||
|
|
||||||
Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
|
Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
* Redistributions of source code must retain the above copyright notice, this
|
* Redistributions of source code must retain the above copyright notice, this
|
||||||
list of conditions and the following disclaimer.
|
list of conditions and the following disclaimer.
|
||||||
* Redistributions in binary form must reproduce the above copyright notice, this
|
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||||
list of conditions and the following disclaimer in the documentation and/or
|
list of conditions and the following disclaimer in the documentation and/or
|
||||||
other materials provided with the distribution.
|
other materials provided with the distribution.
|
||||||
* Neither the name of Intel Corporation nor the names of its contributors may
|
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||||
be used to endorse or promote products derived from this software without
|
be used to endorse or promote products derived from this software without
|
||||||
specific prior written permission.
|
specific prior written permission.
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||||
THE POSSIBILITY OF SUCH DAMAGE.
|
THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
|
||||||
This file is automatically generated. Please do NOT modify !!!
|
This file is automatically generated. Please do NOT modify !!!
|
||||||
|
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __FSPTUPD_H__
|
#ifndef __FSPTUPD_H__
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#define __FSPTUPD_H__
|
#define __FSPTUPD_H__
|
||||||
|
|
||||||
#include <FspUpd.h>
|
#include <FspUpd.h>
|
||||||
|
|
||||||
#pragma pack(1)
|
#pragma pack(1)
|
||||||
|
|
||||||
|
|
||||||
/** Fsp T Core UPD
|
/** Fsp T Core UPD
|
||||||
**/
|
**/
|
||||||
typedef struct {
|
typedef struct {
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||||||
|
|
||||||
/** Offset 0x0020
|
/** Offset 0x0020
|
||||||
**/
|
**/
|
||||||
UINT32 MicrocodeRegionBase;
|
UINT32 MicrocodeRegionBase;
|
||||||
|
|
||||||
/** Offset 0x0024
|
/** Offset 0x0024
|
||||||
**/
|
**/
|
||||||
UINT32 MicrocodeRegionSize;
|
UINT32 MicrocodeRegionSize;
|
||||||
|
|
||||||
/** Offset 0x0028
|
/** Offset 0x0028
|
||||||
**/
|
**/
|
||||||
UINT32 CodeRegionBase;
|
UINT32 CodeRegionBase;
|
||||||
|
|
||||||
/** Offset 0x002C
|
/** Offset 0x002C
|
||||||
**/
|
**/
|
||||||
UINT32 CodeRegionSize;
|
UINT32 CodeRegionSize;
|
||||||
|
|
||||||
/** Offset 0x0030
|
/** Offset 0x0030
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved[16];
|
UINT8 Reserved[16];
|
||||||
} FSPT_CORE_UPD;
|
} FSPT_CORE_UPD;
|
||||||
|
|
||||||
/** Fsp T Configuration
|
/** Fsp T Configuration
|
||||||
**/
|
**/
|
||||||
typedef struct {
|
typedef struct {
|
||||||
|
|
||||||
/** Offset 0x0040 - PcdSerialIoUartDebugEnable
|
/** Offset 0x0040 - PcdSerialIoUartDebugEnable
|
||||||
Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
|
Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
|
||||||
0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
|
0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
|
||||||
**/
|
**/
|
||||||
UINT8 PcdSerialIoUartDebugEnable;
|
UINT8 PcdSerialIoUartDebugEnable;
|
||||||
|
|
||||||
/** Offset 0x0041 - PcdSerialIoUartNumber
|
/** Offset 0x0041 - PcdSerialIoUartNumber
|
||||||
Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
|
Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
|
||||||
Core interface, it cannot be used for debug purpose.
|
Core interface, it cannot be used for debug purpose.
|
||||||
0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
|
0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
|
||||||
**/
|
**/
|
||||||
UINT8 PcdSerialIoUartNumber;
|
UINT8 PcdSerialIoUartNumber;
|
||||||
|
|
||||||
/** Offset 0x0042 - PcdSerialIoUartMode - FSPT
|
/** Offset 0x0042 - PcdSerialIoUartMode - FSPT
|
||||||
Select SerialIo Uart Controller mode
|
Select SerialIo Uart Controller mode
|
||||||
0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
|
0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
|
||||||
4:SerialIoUartSkipInit
|
4:SerialIoUartSkipInit
|
||||||
**/
|
**/
|
||||||
UINT8 PcdSerialIoUartMode;
|
UINT8 PcdSerialIoUartMode;
|
||||||
|
|
||||||
/** Offset 0x0043
|
/** Offset 0x0043
|
||||||
**/
|
**/
|
||||||
UINT8 UnusedUpdSpace0;
|
UINT8 UnusedUpdSpace0;
|
||||||
|
|
||||||
/** Offset 0x0044 - PcdSerialIoUartBaudRate - FSPT
|
/** Offset 0x0044 - PcdSerialIoUartBaudRate - FSPT
|
||||||
Set default BaudRate Supported from 0 - default to 6000000
|
Set default BaudRate Supported from 0 - default to 6000000
|
||||||
**/
|
**/
|
||||||
UINT32 PcdSerialIoUartBaudRate;
|
UINT32 PcdSerialIoUartBaudRate;
|
||||||
|
|
||||||
/** Offset 0x0048 - Pci Express Base Address
|
/** Offset 0x0048 - Pci Express Base Address
|
||||||
Base address to be programmed for Pci Express
|
Base address to be programmed for Pci Express
|
||||||
**/
|
**/
|
||||||
UINT64 PcdPciExpressBaseAddress;
|
UINT64 PcdPciExpressBaseAddress;
|
||||||
|
|
||||||
/** Offset 0x0050 - Pci Express Region Length
|
/** Offset 0x0050 - Pci Express Region Length
|
||||||
Region Length to be programmed for Pci Express
|
Region Length to be programmed for Pci Express
|
||||||
**/
|
**/
|
||||||
UINT32 PcdPciExpressRegionLength;
|
UINT32 PcdPciExpressRegionLength;
|
||||||
|
|
||||||
/** Offset 0x0054 - PcdSerialIoUartParity - FSPT
|
/** Offset 0x0054 - PcdSerialIoUartParity - FSPT
|
||||||
Set default Parity.
|
Set default Parity.
|
||||||
0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
|
0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
|
||||||
**/
|
**/
|
||||||
UINT8 PcdSerialIoUartParity;
|
UINT8 PcdSerialIoUartParity;
|
||||||
|
|
||||||
/** Offset 0x0055 - PcdSerialIoUartDataBits - FSPT
|
/** Offset 0x0055 - PcdSerialIoUartDataBits - FSPT
|
||||||
Set default word length. 0: Default, 5,6,7,8
|
Set default word length. 0: Default, 5,6,7,8
|
||||||
**/
|
**/
|
||||||
UINT8 PcdSerialIoUartDataBits;
|
UINT8 PcdSerialIoUartDataBits;
|
||||||
|
|
||||||
/** Offset 0x0056 - PcdSerialIoUartStopBits - FSPT
|
/** Offset 0x0056 - PcdSerialIoUartStopBits - FSPT
|
||||||
Set default stop bits.
|
Set default stop bits.
|
||||||
0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
|
0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
|
||||||
**/
|
**/
|
||||||
UINT8 PcdSerialIoUartStopBits;
|
UINT8 PcdSerialIoUartStopBits;
|
||||||
|
|
||||||
/** Offset 0x0057 - PcdSerialIoUartAutoFlow - FSPT
|
/** Offset 0x0057 - PcdSerialIoUartAutoFlow - FSPT
|
||||||
Enables UART hardware flow control, CTS and RTS lines.
|
Enables UART hardware flow control, CTS and RTS lines.
|
||||||
0: Disable, 1:Enable
|
0: Disable, 1:Enable
|
||||||
**/
|
**/
|
||||||
UINT8 PcdSerialIoUartAutoFlow;
|
UINT8 PcdSerialIoUartAutoFlow;
|
||||||
|
|
||||||
/** Offset 0x0058 - PcdSerialIoUartRxPinMux - FSPT
|
/** Offset 0x0058 - PcdSerialIoUartRxPinMux - FSPT
|
||||||
Select RX pin muxing for SerialIo UART used for debug
|
Select RX pin muxing for SerialIo UART used for debug
|
||||||
**/
|
**/
|
||||||
UINT32 PcdSerialIoUartRxPinMux;
|
UINT32 PcdSerialIoUartRxPinMux;
|
||||||
|
|
||||||
/** Offset 0x005C - PcdSerialIoUartTxPinMux - FSPT
|
/** Offset 0x005C - PcdSerialIoUartTxPinMux - FSPT
|
||||||
Select TX pin muxing for SerialIo UART used for debug
|
Select TX pin muxing for SerialIo UART used for debug
|
||||||
**/
|
**/
|
||||||
UINT32 PcdSerialIoUartTxPinMux;
|
UINT32 PcdSerialIoUartTxPinMux;
|
||||||
|
|
||||||
/** Offset 0x0060 - PcdSerialIoUartRtsPinMux - FSPT
|
/** Offset 0x0060 - PcdSerialIoUartRtsPinMux - FSPT
|
||||||
Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
|
Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
|
||||||
for possible values.
|
for possible values.
|
||||||
**/
|
**/
|
||||||
UINT32 PcdSerialIoUartRtsPinMux;
|
UINT32 PcdSerialIoUartRtsPinMux;
|
||||||
|
|
||||||
/** Offset 0x0064 - PcdSerialIoUartCtsPinMux - FSPT
|
/** Offset 0x0064 - PcdSerialIoUartCtsPinMux - FSPT
|
||||||
Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
|
Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
|
||||||
for possible values.
|
for possible values.
|
||||||
**/
|
**/
|
||||||
UINT32 PcdSerialIoUartCtsPinMux;
|
UINT32 PcdSerialIoUartCtsPinMux;
|
||||||
|
|
||||||
/** Offset 0x0068 - PcdSerialIoUartDebugMmioBase - FSPT
|
/** Offset 0x0068 - PcdSerialIoUartDebugMmioBase - FSPT
|
||||||
Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
|
Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
|
||||||
= SerialIoUartPci.
|
= SerialIoUartPci.
|
||||||
**/
|
**/
|
||||||
UINT32 PcdSerialIoUartDebugMmioBase;
|
UINT32 PcdSerialIoUartDebugMmioBase;
|
||||||
|
|
||||||
/** Offset 0x006C - PcdLpcUartDebugEnable
|
/** Offset 0x006C - PcdLpcUartDebugEnable
|
||||||
Enable to initialize LPC Uart device in FSP.
|
Enable to initialize LPC Uart device in FSP.
|
||||||
0:Disable, 1:Enable
|
0:Disable, 1:Enable
|
||||||
**/
|
**/
|
||||||
UINT8 PcdLpcUartDebugEnable;
|
UINT8 PcdLpcUartDebugEnable;
|
||||||
|
|
||||||
/** Offset 0x006D
|
/** Offset 0x006D
|
||||||
**/
|
**/
|
||||||
UINT8 UnusedUpdSpace1[7];
|
UINT8 UnusedUpdSpace1[7];
|
||||||
|
|
||||||
/** Offset 0x0074
|
/** Offset 0x0074
|
||||||
**/
|
**/
|
||||||
UINT8 ReservedFsptUpd1[20];
|
UINT8 ReservedFsptUpd1[20];
|
||||||
} FSP_T_CONFIG;
|
} FSP_T_CONFIG;
|
||||||
|
|
||||||
/** Fsp T UPD Configuration
|
/** Fsp T UPD Configuration
|
||||||
**/
|
**/
|
||||||
typedef struct {
|
typedef struct {
|
||||||
|
|
||||||
/** Offset 0x0000
|
/** Offset 0x0000
|
||||||
**/
|
**/
|
||||||
FSP_UPD_HEADER FspUpdHeader;
|
FSP_UPD_HEADER FspUpdHeader;
|
||||||
|
|
||||||
/** Offset 0x0020
|
/** Offset 0x0020
|
||||||
**/
|
**/
|
||||||
FSPT_CORE_UPD FsptCoreUpd;
|
FSPT_CORE_UPD FsptCoreUpd;
|
||||||
|
|
||||||
/** Offset 0x0040
|
/** Offset 0x0040
|
||||||
**/
|
**/
|
||||||
FSP_T_CONFIG FsptConfig;
|
FSP_T_CONFIG FsptConfig;
|
||||||
|
|
||||||
/** Offset 0x0088
|
/** Offset 0x0088
|
||||||
**/
|
**/
|
||||||
UINT8 UnusedUpdSpace2[6];
|
UINT8 UnusedUpdSpace2[6];
|
||||||
|
|
||||||
/** Offset 0x008E
|
/** Offset 0x008E
|
||||||
**/
|
**/
|
||||||
UINT16 UpdTerminator;
|
UINT16 UpdTerminator;
|
||||||
} FSPT_UPD;
|
} FSPT_UPD;
|
||||||
|
|
||||||
#pragma pack()
|
#pragma pack()
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
@ -1,252 +1,252 @@
|
|||||||
/** @file
|
/** @file
|
||||||
This file contains definitions required for creation of
|
This file contains definitions required for creation of
|
||||||
Memory S3 Save data, Memory Info data and Memory Platform
|
Memory S3 Save data, Memory Info data and Memory Platform
|
||||||
data hobs.
|
data hobs.
|
||||||
|
|
||||||
@copyright
|
@copyright
|
||||||
Copyright (c) 1999 - 2020, Intel Corporation. All rights reserved.<BR>
|
Copyright (c) 1999 - 2020, Intel Corporation. All rights reserved.<BR>
|
||||||
This program and the accompanying materials are licensed and made available under
|
This program and the accompanying materials are licensed and made available under
|
||||||
the terms and conditions of the BSD License that accompanies this distribution.
|
the terms and conditions of the BSD License that accompanies this distribution.
|
||||||
The full text of the license may be found at
|
The full text of the license may be found at
|
||||||
http://opensource.org/licenses/bsd-license.php.
|
http://opensource.org/licenses/bsd-license.php.
|
||||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||||
|
|
||||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||||
|
|
||||||
@par Specification Reference:
|
@par Specification Reference:
|
||||||
**/
|
**/
|
||||||
#ifndef _MEM_INFO_HOB_H_
|
#ifndef _MEM_INFO_HOB_H_
|
||||||
#define _MEM_INFO_HOB_H_
|
#define _MEM_INFO_HOB_H_
|
||||||
|
|
||||||
#include <Uefi/UefiMultiPhase.h>
|
#include <Uefi/UefiMultiPhase.h>
|
||||||
#include <Pi/PiBootMode.h>
|
#include <Pi/PiBootMode.h>
|
||||||
#include <Pi/PiHob.h>
|
#include <Pi/PiHob.h>
|
||||||
|
|
||||||
#pragma pack (push, 1)
|
#pragma pack (push, 1)
|
||||||
|
|
||||||
extern EFI_GUID gSiMemoryS3DataGuid;
|
extern EFI_GUID gSiMemoryS3DataGuid;
|
||||||
extern EFI_GUID gSiMemoryInfoDataGuid;
|
extern EFI_GUID gSiMemoryInfoDataGuid;
|
||||||
extern EFI_GUID gSiMemoryPlatformDataGuid;
|
extern EFI_GUID gSiMemoryPlatformDataGuid;
|
||||||
|
|
||||||
#define MAX_TRACE_CACHE_TYPE 3
|
#define MAX_TRACE_CACHE_TYPE 3
|
||||||
|
|
||||||
#define MAX_NODE 1
|
#define MAX_NODE 1
|
||||||
#define MAX_CH 2
|
#define MAX_CH 2
|
||||||
#define MAX_DIMM 2
|
#define MAX_DIMM 2
|
||||||
|
|
||||||
///
|
///
|
||||||
/// Host reset states from MRC.
|
/// Host reset states from MRC.
|
||||||
///
|
///
|
||||||
#define WARM_BOOT 2
|
#define WARM_BOOT 2
|
||||||
|
|
||||||
#define R_MC_CHNL_RANK_PRESENT 0x7C
|
#define R_MC_CHNL_RANK_PRESENT 0x7C
|
||||||
#define B_RANK0_PRS BIT0
|
#define B_RANK0_PRS BIT0
|
||||||
#define B_RANK1_PRS BIT1
|
#define B_RANK1_PRS BIT1
|
||||||
#define B_RANK2_PRS BIT4
|
#define B_RANK2_PRS BIT4
|
||||||
#define B_RANK3_PRS BIT5
|
#define B_RANK3_PRS BIT5
|
||||||
|
|
||||||
///
|
///
|
||||||
/// Defines taken from MRC so avoid having to include MrcInterface.h
|
/// Defines taken from MRC so avoid having to include MrcInterface.h
|
||||||
///
|
///
|
||||||
|
|
||||||
//
|
//
|
||||||
// Matches MAX_SPD_SAVE define in MRC
|
// Matches MAX_SPD_SAVE define in MRC
|
||||||
//
|
//
|
||||||
#ifndef MAX_SPD_SAVE
|
#ifndef MAX_SPD_SAVE
|
||||||
#define MAX_SPD_SAVE 29
|
#define MAX_SPD_SAVE 29
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
//
|
//
|
||||||
// MRC version description.
|
// MRC version description.
|
||||||
//
|
//
|
||||||
typedef struct {
|
typedef struct {
|
||||||
UINT8 Major; ///< Major version number
|
UINT8 Major; ///< Major version number
|
||||||
UINT8 Minor; ///< Minor version number
|
UINT8 Minor; ///< Minor version number
|
||||||
UINT8 Rev; ///< Revision number
|
UINT8 Rev; ///< Revision number
|
||||||
UINT8 Build; ///< Build number
|
UINT8 Build; ///< Build number
|
||||||
} SiMrcVersion;
|
} SiMrcVersion;
|
||||||
|
|
||||||
//
|
//
|
||||||
// Matches MrcDimmSts enum in MRC
|
// Matches MrcDimmSts enum in MRC
|
||||||
//
|
//
|
||||||
#ifndef DIMM_ENABLED
|
#ifndef DIMM_ENABLED
|
||||||
#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
|
#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
|
||||||
#endif
|
#endif
|
||||||
#ifndef DIMM_DISABLED
|
#ifndef DIMM_DISABLED
|
||||||
#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
|
#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
|
||||||
#endif
|
#endif
|
||||||
#ifndef DIMM_PRESENT
|
#ifndef DIMM_PRESENT
|
||||||
#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
|
#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
|
||||||
#endif
|
#endif
|
||||||
#ifndef DIMM_NOT_PRESENT
|
#ifndef DIMM_NOT_PRESENT
|
||||||
#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
|
#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
//
|
//
|
||||||
// Matches MrcBootMode enum in MRC
|
// Matches MrcBootMode enum in MRC
|
||||||
//
|
//
|
||||||
#ifndef __MRC_BOOT_MODE__
|
#ifndef __MRC_BOOT_MODE__
|
||||||
#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h
|
#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h
|
||||||
#ifndef INT32_MAX
|
#ifndef INT32_MAX
|
||||||
#define INT32_MAX (0x7FFFFFFF)
|
#define INT32_MAX (0x7FFFFFFF)
|
||||||
#endif //INT32_MAX
|
#endif //INT32_MAX
|
||||||
typedef enum {
|
typedef enum {
|
||||||
bmCold, ///< Cold boot
|
bmCold, ///< Cold boot
|
||||||
bmWarm, ///< Warm boot
|
bmWarm, ///< Warm boot
|
||||||
bmS3, ///< S3 resume
|
bmS3, ///< S3 resume
|
||||||
bmFast, ///< Fast boot
|
bmFast, ///< Fast boot
|
||||||
MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value.
|
MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value.
|
||||||
MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI.
|
MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI.
|
||||||
} MRC_BOOT_MODE;
|
} MRC_BOOT_MODE;
|
||||||
#endif //__MRC_BOOT_MODE__
|
#endif //__MRC_BOOT_MODE__
|
||||||
|
|
||||||
//
|
//
|
||||||
// Matches MrcDdrType enum in MRC
|
// Matches MrcDdrType enum in MRC
|
||||||
//
|
//
|
||||||
#ifndef MRC_DDR_TYPE_DDR4
|
#ifndef MRC_DDR_TYPE_DDR4
|
||||||
#define MRC_DDR_TYPE_DDR4 0
|
#define MRC_DDR_TYPE_DDR4 0
|
||||||
#endif
|
#endif
|
||||||
#ifndef MRC_DDR_TYPE_DDR3
|
#ifndef MRC_DDR_TYPE_DDR3
|
||||||
#define MRC_DDR_TYPE_DDR3 1
|
#define MRC_DDR_TYPE_DDR3 1
|
||||||
#endif
|
#endif
|
||||||
#ifndef MRC_DDR_TYPE_LPDDR3
|
#ifndef MRC_DDR_TYPE_LPDDR3
|
||||||
#define MRC_DDR_TYPE_LPDDR3 2
|
#define MRC_DDR_TYPE_LPDDR3 2
|
||||||
#endif
|
#endif
|
||||||
#ifndef MRC_DDR_TYPE_UNKNOWN
|
#ifndef MRC_DDR_TYPE_UNKNOWN
|
||||||
#define MRC_DDR_TYPE_UNKNOWN 3
|
#define MRC_DDR_TYPE_UNKNOWN 3
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define MAX_PROFILE_NUM 4 // number of memory profiles supported
|
#define MAX_PROFILE_NUM 4 // number of memory profiles supported
|
||||||
#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
|
#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
|
||||||
|
|
||||||
//
|
//
|
||||||
// DIMM timings
|
// DIMM timings
|
||||||
//
|
//
|
||||||
typedef struct {
|
typedef struct {
|
||||||
UINT32 tCK; ///< Memory cycle time, in femtoseconds.
|
UINT32 tCK; ///< Memory cycle time, in femtoseconds.
|
||||||
UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
|
UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
|
||||||
UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
|
UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
|
||||||
UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
|
UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
|
||||||
UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
|
UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
|
||||||
UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
|
UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
|
||||||
UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
|
UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
|
||||||
UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
|
UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
|
||||||
UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||||
UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
|
UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
|
||||||
UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||||
UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||||
UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
|
UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
|
||||||
UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
|
UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
|
||||||
UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
|
UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
|
||||||
UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
|
UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
|
||||||
UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
|
UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
|
||||||
UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
|
UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
|
||||||
UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
|
UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
|
||||||
UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
|
UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
|
||||||
UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
|
UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
|
||||||
UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
|
UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
|
||||||
} MRC_CH_TIMING;
|
} MRC_CH_TIMING;
|
||||||
|
|
||||||
///
|
///
|
||||||
/// Memory SMBIOS & OC Memory Data Hob
|
/// Memory SMBIOS & OC Memory Data Hob
|
||||||
///
|
///
|
||||||
typedef struct {
|
typedef struct {
|
||||||
UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
|
UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
|
||||||
UINT8 DimmId;
|
UINT8 DimmId;
|
||||||
UINT32 DimmCapacity; ///< DIMM size in MBytes.
|
UINT32 DimmCapacity; ///< DIMM size in MBytes.
|
||||||
UINT16 MfgId;
|
UINT16 MfgId;
|
||||||
UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
|
UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
|
||||||
UINT8 RankInDimm; ///< The number of ranks in this DIMM.
|
UINT8 RankInDimm; ///< The number of ranks in this DIMM.
|
||||||
UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
|
UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
|
||||||
UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
|
UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
|
||||||
UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
|
UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
|
||||||
UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
|
UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
|
||||||
UINT16 Speed; ///< The maximum capable speed of the device, in MHz
|
UINT16 Speed; ///< The maximum capable speed of the device, in MHz
|
||||||
UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
|
UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
|
||||||
} DIMM_INFO;
|
} DIMM_INFO;
|
||||||
|
|
||||||
typedef struct {
|
typedef struct {
|
||||||
UINT8 Status; ///< Indicates whether this channel should be used.
|
UINT8 Status; ///< Indicates whether this channel should be used.
|
||||||
UINT8 ChannelId;
|
UINT8 ChannelId;
|
||||||
UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
|
UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
|
||||||
MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
|
MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
|
||||||
DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
|
DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
|
||||||
} CHANNEL_INFO;
|
} CHANNEL_INFO;
|
||||||
|
|
||||||
typedef struct {
|
typedef struct {
|
||||||
UINT8 Status; ///< Indicates whether this controller should be used.
|
UINT8 Status; ///< Indicates whether this controller should be used.
|
||||||
UINT16 DeviceId; ///< The PCI device id of this memory controller.
|
UINT16 DeviceId; ///< The PCI device id of this memory controller.
|
||||||
UINT8 RevisionId; ///< The PCI revision id of this memory controller.
|
UINT8 RevisionId; ///< The PCI revision id of this memory controller.
|
||||||
UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
|
UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
|
||||||
CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
|
CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
|
||||||
} CONTROLLER_INFO;
|
} CONTROLLER_INFO;
|
||||||
|
|
||||||
typedef struct {
|
typedef struct {
|
||||||
UINT64 BaseAddress; ///< Trace Base Address
|
UINT64 BaseAddress; ///< Trace Base Address
|
||||||
UINT64 TotalSize; ///< Total Trace Region of Same Cache type
|
UINT64 TotalSize; ///< Total Trace Region of Same Cache type
|
||||||
UINT8 CacheType; ///< Trace Cache Type
|
UINT8 CacheType; ///< Trace Cache Type
|
||||||
UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code
|
UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code
|
||||||
UINT8 Rsvd[2];
|
UINT8 Rsvd[2];
|
||||||
} PSMI_MEM_INFO;
|
} PSMI_MEM_INFO;
|
||||||
|
|
||||||
typedef struct {
|
typedef struct {
|
||||||
UINT8 Revision;
|
UINT8 Revision;
|
||||||
UINT16 DataWidth; ///< Data width, in bits, of this memory device
|
UINT16 DataWidth; ///< Data width, in bits, of this memory device
|
||||||
/** As defined in SMBIOS 3.0 spec
|
/** As defined in SMBIOS 3.0 spec
|
||||||
Section 7.18.2 and Table 75
|
Section 7.18.2 and Table 75
|
||||||
**/
|
**/
|
||||||
UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
|
UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
|
||||||
UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
|
UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
|
||||||
UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
|
UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
|
||||||
/** As defined in SMBIOS 3.0 spec
|
/** As defined in SMBIOS 3.0 spec
|
||||||
Section 7.17.3 and Table 72
|
Section 7.17.3 and Table 72
|
||||||
**/
|
**/
|
||||||
UINT8 ErrorCorrectionType;
|
UINT8 ErrorCorrectionType;
|
||||||
|
|
||||||
SiMrcVersion Version;
|
SiMrcVersion Version;
|
||||||
BOOLEAN EccSupport;
|
BOOLEAN EccSupport;
|
||||||
UINT8 MemoryProfile;
|
UINT8 MemoryProfile;
|
||||||
UINT32 TotalPhysicalMemorySize;
|
UINT32 TotalPhysicalMemorySize;
|
||||||
UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
|
UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
|
||||||
UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
|
UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
|
||||||
UINT8 Ratio;
|
UINT8 Ratio;
|
||||||
UINT8 RefClk;
|
UINT8 RefClk;
|
||||||
UINT32 VddVoltage[MAX_PROFILE_NUM];
|
UINT32 VddVoltage[MAX_PROFILE_NUM];
|
||||||
CONTROLLER_INFO Controller[MAX_NODE];
|
CONTROLLER_INFO Controller[MAX_NODE];
|
||||||
} MEMORY_INFO_DATA_HOB;
|
} MEMORY_INFO_DATA_HOB;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
Memory Platform Data Hob
|
Memory Platform Data Hob
|
||||||
|
|
||||||
<b>Revision 1:</b>
|
<b>Revision 1:</b>
|
||||||
- Initial version.
|
- Initial version.
|
||||||
<b>Revision 2:</b>
|
<b>Revision 2:</b>
|
||||||
- Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
|
- Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
|
||||||
**/
|
**/
|
||||||
typedef struct {
|
typedef struct {
|
||||||
UINT8 Revision;
|
UINT8 Revision;
|
||||||
UINT8 Reserved[3];
|
UINT8 Reserved[3];
|
||||||
UINT32 BootMode;
|
UINT32 BootMode;
|
||||||
UINT32 TsegSize;
|
UINT32 TsegSize;
|
||||||
UINT32 TsegBase;
|
UINT32 TsegBase;
|
||||||
UINT32 PrmrrSize;
|
UINT32 PrmrrSize;
|
||||||
UINT64 PrmrrBase;
|
UINT64 PrmrrBase;
|
||||||
UINT32 PramSize;
|
UINT32 PramSize;
|
||||||
UINT64 PramBase;
|
UINT64 PramBase;
|
||||||
UINT64 DismLimit;
|
UINT64 DismLimit;
|
||||||
UINT64 DismBase;
|
UINT64 DismBase;
|
||||||
UINT32 GttBase;
|
UINT32 GttBase;
|
||||||
UINT32 MmioSize;
|
UINT32 MmioSize;
|
||||||
UINT32 PciEBaseAddress;
|
UINT32 PciEBaseAddress;
|
||||||
PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE];
|
PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE];
|
||||||
} MEMORY_PLATFORM_DATA;
|
} MEMORY_PLATFORM_DATA;
|
||||||
|
|
||||||
typedef struct {
|
typedef struct {
|
||||||
EFI_HOB_GUID_TYPE EfiHobGuidType;
|
EFI_HOB_GUID_TYPE EfiHobGuidType;
|
||||||
MEMORY_PLATFORM_DATA Data;
|
MEMORY_PLATFORM_DATA Data;
|
||||||
UINT8 *Buffer;
|
UINT8 *Buffer;
|
||||||
} MEMORY_PLATFORM_DATA_HOB;
|
} MEMORY_PLATFORM_DATA_HOB;
|
||||||
|
|
||||||
#pragma pack (pop)
|
#pragma pack (pop)
|
||||||
|
|
||||||
#endif // _MEM_INFO_HOB_H_
|
#endif // _MEM_INFO_HOB_H_
|
||||||
|
|||||||
@ -1,72 +1,72 @@
|
|||||||
/** @file
|
/** @file
|
||||||
|
|
||||||
Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
|
Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
* Redistributions of source code must retain the above copyright notice, this
|
* Redistributions of source code must retain the above copyright notice, this
|
||||||
list of conditions and the following disclaimer.
|
list of conditions and the following disclaimer.
|
||||||
* Redistributions in binary form must reproduce the above copyright notice, this
|
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||||
list of conditions and the following disclaimer in the documentation and/or
|
list of conditions and the following disclaimer in the documentation and/or
|
||||||
other materials provided with the distribution.
|
other materials provided with the distribution.
|
||||||
* Neither the name of Intel Corporation nor the names of its contributors may
|
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||||
be used to endorse or promote products derived from this software without
|
be used to endorse or promote products derived from this software without
|
||||||
specific prior written permission.
|
specific prior written permission.
|
||||||
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||||
THE POSSIBILITY OF SUCH DAMAGE.
|
THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
|
||||||
This file is automatically generated. Please do NOT modify !!!
|
This file is automatically generated. Please do NOT modify !!!
|
||||||
|
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __FIRMWARE_VERSION_INFO_H__
|
#ifndef __FIRMWARE_VERSION_INFO_H__
|
||||||
#define __FIRMWARE_VERSION_INFO_H__
|
#define __FIRMWARE_VERSION_INFO_H__
|
||||||
|
|
||||||
#include <IndustryStandard/SmBios.h>
|
#include <IndustryStandard/SmBios.h>
|
||||||
|
|
||||||
#define INTEL_FIRMWARE_VERSION_INFO_GROUP_NAME "Firmware Version Info"
|
#define INTEL_FIRMWARE_VERSION_INFO_GROUP_NAME "Firmware Version Info"
|
||||||
|
|
||||||
#pragma pack(1)
|
#pragma pack(1)
|
||||||
|
|
||||||
///
|
///
|
||||||
/// Firmware Version Structure
|
/// Firmware Version Structure
|
||||||
///
|
///
|
||||||
typedef struct {
|
typedef struct {
|
||||||
UINT8 MajorVersion;
|
UINT8 MajorVersion;
|
||||||
UINT8 MinorVersion;
|
UINT8 MinorVersion;
|
||||||
UINT8 Revision;
|
UINT8 Revision;
|
||||||
UINT16 BuildNumber;
|
UINT16 BuildNumber;
|
||||||
} INTEL_FIRMWARE_VERSION;
|
} INTEL_FIRMWARE_VERSION;
|
||||||
|
|
||||||
///
|
///
|
||||||
/// Firmware Version Info (FVI) Structure
|
/// Firmware Version Info (FVI) Structure
|
||||||
///
|
///
|
||||||
typedef struct {
|
typedef struct {
|
||||||
SMBIOS_TABLE_STRING ComponentName; ///< String Index of Component Name
|
SMBIOS_TABLE_STRING ComponentName; ///< String Index of Component Name
|
||||||
SMBIOS_TABLE_STRING VersionString; ///< String Index of Version String
|
SMBIOS_TABLE_STRING VersionString; ///< String Index of Version String
|
||||||
INTEL_FIRMWARE_VERSION Version; ///< Firmware version
|
INTEL_FIRMWARE_VERSION Version; ///< Firmware version
|
||||||
} INTEL_FIRMWARE_VERSION_INFO;
|
} INTEL_FIRMWARE_VERSION_INFO;
|
||||||
|
|
||||||
///
|
///
|
||||||
/// SMBIOS OEM Type Intel Firmware Version Info (FVI) Structure
|
/// SMBIOS OEM Type Intel Firmware Version Info (FVI) Structure
|
||||||
///
|
///
|
||||||
typedef struct {
|
typedef struct {
|
||||||
SMBIOS_STRUCTURE Header; ///< SMBIOS structure header
|
SMBIOS_STRUCTURE Header; ///< SMBIOS structure header
|
||||||
UINT8 Count; ///< Number of FVI entries in this structure
|
UINT8 Count; ///< Number of FVI entries in this structure
|
||||||
INTEL_FIRMWARE_VERSION_INFO Fvi[1]; ///< FVI structure(s)
|
INTEL_FIRMWARE_VERSION_INFO Fvi[1]; ///< FVI structure(s)
|
||||||
} SMBIOS_TABLE_TYPE_OEM_INTEL_FVI;
|
} SMBIOS_TABLE_TYPE_OEM_INTEL_FVI;
|
||||||
|
|
||||||
#pragma pack()
|
#pragma pack()
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
Reference in New Issue
Block a user