diff --git a/.gitignore b/.gitignore index 97cc9ce95d..11a6173283 100644 --- a/.gitignore +++ b/.gitignore @@ -1,6 +1,3 @@ -payloads/libpayload/install/ -payloads/nvramcui/build -payloads/nvramcui/libpayload junit.xml abuild*.xml .config @@ -11,46 +8,8 @@ defconfig .ccwrap build/ coreboot-builds/ -payloads/coreinfo/lpbuild/ -payloads/coreinfo/lp.config* -payloads/external/depthcharge/depthcharge/ -payloads/external/FILO/filo/ -payloads/external/GRUB2/grub2/ -payloads/external/LinuxBoot/linuxboot/ -payloads/external/SeaBIOS/seabios/ -payloads/external/tianocore/tianocore/ -payloads/external/tint/tint/ -payloads/external/U-Boot/u-boot/ -payloads/external/Memtest86Plus/memtest86plus/ -payloads/external/iPXE/ipxe/ -util/crossgcc/acpica-unix-*/ -util/crossgcc/binutils-*/ -util/crossgcc/build-*BINUTILS/ -util/crossgcc/build-*EXPAT/ -util/crossgcc/build-*GCC/ -util/crossgcc/build-*GDB/ -util/crossgcc/build-*GMP/ -util/crossgcc/build-*LIBELF/ -util/crossgcc/build-*MPC/ -util/crossgcc/build-*MPFR/ -util/crossgcc/build-*PYTHON/ -util/crossgcc/build-*LVM/ -util/crossgcc/build-*IASL/ -util/crossgcc/expat-*/ -util/crossgcc/gcc-*/ -util/crossgcc/gdb-*/ -util/crossgcc/gmp-*/ -util/crossgcc/libelf-*/ -util/crossgcc/mingwrt-*/ -util/crossgcc/mpc-*/ -util/crossgcc/mpfr-*/ -util/crossgcc/Python-*/ -util/crossgcc/*.src/ -util/crossgcc/tarballs/ -util/crossgcc/w32api-*/ -util/crossgcc/xgcc/ -util/crossgcc/xgcc-*/ -util/crossgcc/xgcc +coreboot-builds*/ + site-local *.\# @@ -66,7 +25,8 @@ site-local *.pyc *.sw[po] /*.rom -coreboot-builds*/ +.test +.dependencies # Development friendly files tags @@ -76,60 +36,9 @@ tags xgcc/ tarballs/ -# -# KDE editors create lots of backup files whenever -# a file is edited, so just ignore them +# editor backup files, temporary files, IDE project files *~ *.kate-swp -# Ignore Kdevelop project file *.kdev4 -util/*/.dependencies -util/*/.test -util/amdfwtool/amdfwtool -util/archive/archive -util/bincfg/bincfg -util/board_status/board-status -util/bucts/bucts -util/cbfstool/cbfs-compression-tool -util/cbfstool/cbfstool -util/cbfstool/fmaptool -util/cbfstool/ifwitool -util/cbfstool/rmodtool -util/cbmem/.dependencies -util/cbmem/cbmem -util/ectool/ectool -util/futility/futility -util/genprof/genprof -util/getpir/getpir -util/ifdtool/ifdtool -util/intelmetool/intelmetool -util/inteltool/.dependencies -util/inteltool/inteltool -util/intelp2m/intelp2m -util/intelp2m/generate/gpio.h -util/intelvbttool/intelvbttool -util/msrtool/Makefile -util/msrtool/Makefile.deps -util/msrtool/msrtool -util/nvramtool/.dependencies -util/nvramtool/nvramtool -util/pmh7tool/pmh7tool -util/runfw/googlesnow -util/superiotool/superiotool -util/vgabios/testbios -util/autoport/autoport -util/kbc1126/kbc1126_ec_dump -util/kbc1126/kbc1126_ec_insert -util/spd_tools/*/gen_spd -util/spd_tools/*/gen_part_id - -Documentation/*.aux -Documentation/*.idx -Documentation/*.log -Documentation/*.toc -Documentation/*.out -Documentation/*.pdf -Documentation/_build - doxygen/* diff --git a/Documentation/.gitignore b/Documentation/.gitignore new file mode 100644 index 0000000000..a8f5d5f6fa --- /dev/null +++ b/Documentation/.gitignore @@ -0,0 +1,7 @@ +*.aux +*.idx +*.log +*.toc +*.out +*.pdf +_build diff --git a/Documentation/lib/fw_config.md b/Documentation/lib/fw_config.md index 63a56dcd7b..dcf1bb4e95 100644 --- a/Documentation/lib/fw_config.md +++ b/Documentation/lib/fw_config.md @@ -73,18 +73,18 @@ return true. ## Firmware Configuration Value -The 32bit value used as the firmware configuration bitmask is meant to be determined at runtime +The 64-bit value used as the firmware configuration bitmask is meant to be determined at runtime but could also be defined at compile time if needed. There are two supported sources for providing this information to coreboot. ### CBFS -The value can be provided with a 32bit raw value in CBFS that is read by coreboot. The value +The value can be provided with a 64-bit raw value in CBFS that is read by coreboot. The value can be set at build time but also adjusted in an existing image with `cbfstool`. To enable this select the `CONFIG_FW_CONFIG_CBFS` option in the build configuration and add a -raw 32bit value to CBFS with the name of the current prefix at `CONFIG_FW_PREFIX/fw_config`. +raw 64-bit value to CBFS with the name of the current prefix at `CONFIG_FW_PREFIX/fw_config`. When `fw_config_probe_device()` or `fw_config_probe()` is called it will look for the specified file in CBFS use the value it contains when matching fields and options. @@ -291,8 +291,8 @@ field and option to check. struct fw_config { const char *field_name; const char *option_name; - uint32_t mask; - uint32_t value; + uint64_t mask; + uint64_t value; }; ``` diff --git a/Documentation/mainboard/purism/librem_mini.md b/Documentation/mainboard/purism/librem_mini.md index be9a3e5632..e098a24778 100644 --- a/Documentation/mainboard/purism/librem_mini.md +++ b/Documentation/mainboard/purism/librem_mini.md @@ -4,7 +4,7 @@ This page describes how to run coreboot on the [Purism Librem Mini]. ```eval_rst +------------------+--------------------------------------------------+ -| CPU | Intel Core i7-8565U | +| CPU | Intel Core i7-8565U/8665U | +------------------+--------------------------------------------------+ | PCH | Whiskey Lake / Cannon Point LP | +------------------+--------------------------------------------------+ @@ -91,14 +91,15 @@ desoldering it from the mainboard. ## Known issues * SeaBIOS can be finicky with detecting USB devices - * Booting can sometimes hang when a bootsplash image is used with SeaBIOS - and VGA option ROM display init, related to display mode changing - * Issues with some SATA devices have been mitigated by limiting the SATA speed to 3Gbps - until the correct HSIO PHY settings can be determined. + * Mode switching with VGA option ROM display init can be slow and sometimes hangs + * Some SATA devices on the 2.5" interface can have issues operating at 6 Gbps, + despite the HSIO PHY settings being set optimally via experimentation. These devices + may show errors in dmesg and drop down to 3 Gbps, but should not fail to boot. + The same issue is present on the AMI vendor firmware. ## Working - * External displays via HDMI/DislpayPort with VGA option ROM or FSP/GOP init + * External displays via HDMI/DisplayPort with VGA option ROM or FSP/GOP init (no libgfxinit support yet) * SeaBIOS (1.13.x), Tianocore (CorebootPayloadpkg), Heads (Purism downstream) payloads * Ethernet, m.2 2230 Wi-Fi diff --git a/MAINTAINERS b/MAINTAINERS index d867c78465..ba88813509 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -694,8 +694,13 @@ OPTION ROM EXECUTION & X86EMU F: src/device/oprom/ CBFS -F: src/include/cbfs.h -F: src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h +M: Julius Werner +F: src/include/cbfs* +F: src/commonlib/bsd/include/commonlib/bsd/cbfs* +F: src/commonlib/bsd/cbfs* +F: src/lib/cbfs.c + +CBFSTOOL F: util/cbfstool/ CBMEM diff --git a/Makefile b/Makefile index 2705c66b51..1b7cb9b8d6 100644 --- a/Makefile +++ b/Makefile @@ -440,10 +440,10 @@ doxygen_simple: doxyplatform doxygen_platform: $(obj)/project_filelist.txt echo echo "Building doxygen documentation for $(CONFIG_MAINBOARD_PART_NUMBER)" - export DOXYGEN_OUTPUT_DIR="$(DOXYGEN_OUTPUT_DIR)/$(CONFIG_MAINBOARD_VENDOR)/$(CONFIG_MAINBOARD_PART_NUMBER)"; \ + export DOXYGEN_OUTPUT_DIR="$$( echo $(DOXYGEN_OUTPUT_DIR)/$(call strip_quotes, $(CONFIG_MAINBOARD_VENDOR))_$(call strip_quotes, $(CONFIG_MAINBOARD_PART_NUMBER)) | sed 's|[^A-Za-z0-9/]|_|g' )"; \ mkdir -p "$$DOXYGEN_OUTPUT_DIR"; \ export DOXYFILES="$$(cat $(obj)/project_filelist.txt | grep -v '\.ld$$' | sed 's/\.aml/\.dsl/' | tr '\n' ' ')"; \ - export DOXYGEN_PLATFORM="$(CONFIG_MAINBOARD_DIR) ($(CONFIG_MAINBOARD_PART_NUMBER)) version $(KERNELVERSION)"; \ + export DOXYGEN_PLATFORM="$(call strip_quotes, $(CONFIG_MAINBOARD_DIR)) \($(call strip_quotes, $(CONFIG_MAINBOARD_PART_NUMBER))\) version $(KERNELVERSION)"; \ $(DOXYGEN) Documentation/doxygen/Doxyfile.coreboot_platform doxyclean: doxygen-clean diff --git a/configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100 b/configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100 index 11a27bf671..563f83ac5e 100644 --- a/configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100 +++ b/configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100 @@ -1,4 +1,7 @@ -# Not meant for actual use. Exercises, among other things: +# Not meant for actual use, but rather to build-test individual options. +# If keeping this combination of options buildable becomes too hard in +# the future, then this config can be split into several smaller chunks. +# Exercises, among other things: # + Code coverage # + UBSAN # + Debug options @@ -6,6 +9,7 @@ # + Silicon Image SIL3114 driver # + Genesys Logic GL9763E driver # + EM100 support +# + SMM module loader V2 CONFIG_COVERAGE=y CONFIG_UBSAN=y CONFIG_VENDOR_ASROCK=y @@ -41,4 +45,5 @@ CONFIG_DEBUG_COVERAGE=y CONFIG_DEBUG_BOOT_STATE=y CONFIG_DEBUG_ADA_CODE=y CONFIG_HAVE_EM100_SUPPORT=y +CONFIG_X86_SMM_LOADER_VERSION2=y CONFIG_EM100=y diff --git a/configs/config.portwell_m107.debug_smmstore_oxpcie_em100spi b/configs/config.portwell_m107.debug_smmstore_oxpcie_em100spi new file mode 100644 index 0000000000..09dfbe35cf --- /dev/null +++ b/configs/config.portwell_m107.debug_smmstore_oxpcie_em100spi @@ -0,0 +1,41 @@ +# Not meant for actual use, but rather to build-test individual options. +# If keeping this combination of options buildable becomes too hard in +# the future, then this config can be split into several smaller chunks. +# Exercises, among other things: +# + SMMSTORE +# + OXPCIE support +# + FSP MP init +# + EM100Pro SPI console +# + Debug options +CONFIG_VENDOR_PORTWELL=y +CONFIG_CONSOLE_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_ENABLE_BUILTIN_COM1=y +CONFIG_ONBOARD_MEM_KINGSTON=y +CONFIG_USE_INTEL_FSP_MP_INIT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE=y +CONFIG_SOC_INTEL_DEBUG_CONSENT=y +CONFIG_PCIEXP_HOTPLUG=y +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y +CONFIG_SOFTWARE_I2C=y +CONFIG_SMMSTORE=y +CONFIG_SPI_FLASH_NO_FAST_READ=y +CONFIG_DRIVERS_UART_OXPCIE=y +CONFIG_DRIVERS_GENESYSLOGIC_GL9755=y +CONFIG_DISPLAY_HOBS=y +CONFIG_DISPLAY_VBT=y +CONFIG_DISPLAY_FSP_ENTRY_POINTS=y +CONFIG_DISPLAY_UPD_DATA=y +CONFIG_EM100PRO_SPI_CONSOLE=y +CONFIG_DISPLAY_MTRRS=y +CONFIG_GDB_STUB=y +CONFIG_GDB_WAIT=y +CONFIG_FATAL_ASSERTS=y +CONFIG_DEBUG_CBFS=y +CONFIG_DEBUG_SMBUS=y +CONFIG_DEBUG_SMI=y +CONFIG_DEBUG_PERIODIC_SMI=y +CONFIG_DEBUG_MALLOC=y +CONFIG_DEBUG_CONSOLE_INIT=y +CONFIG_REALMODE_DEBUG=y +CONFIG_DEBUG_BOOT_STATE=y diff --git a/payloads/coreinfo/.gitignore b/payloads/coreinfo/.gitignore new file mode 100644 index 0000000000..101045e012 --- /dev/null +++ b/payloads/coreinfo/.gitignore @@ -0,0 +1,2 @@ +lpbuild/ +lp.config* diff --git a/payloads/coreinfo/Kconfig b/payloads/coreinfo/Kconfig index eafb879363..2c1f91c874 100644 --- a/payloads/coreinfo/Kconfig +++ b/payloads/coreinfo/Kconfig @@ -42,6 +42,15 @@ config PAYLOAD_INFO_VERSION help The version number of this payload. +config LTO + bool "Use link time optimization (LTO)" + default n + help + Compile with link time optimization. This can often decrease the + final binary size, but may increase compilation time. This option + is most effective when LTO is also enabled in libpayload, which + is done separately. + endmenu menu "Modules" diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index d842b469c4..cd58f392dd 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -76,9 +76,13 @@ ifneq ($(strip $(HAVE_DOTCONFIG)),) include $(src)/.config real-all: $(TARGET) +ifeq ($(CONFIG_LTO),y) +CFLAGS += -flto +endif + $(TARGET): $(src)/.config $(coreinfo_obj)/config.h $(OBJS) libpayload printf " LPCC $(subst $(CURDIR)/,,$(@)) (LINK)\n" - $(LPCC) -o $@ $(OBJS) + $(LPCC) $(CFLAGS) -o $@ $(OBJS) $(OBJCOPY) --only-keep-debug $@ $(TARGET).debug $(OBJCOPY) --strip-debug $@ $(OBJCOPY) --add-gnu-debuglink=$(TARGET).debug $@ diff --git a/payloads/external/.gitignore b/payloads/external/.gitignore new file mode 100644 index 0000000000..ebca42908b --- /dev/null +++ b/payloads/external/.gitignore @@ -0,0 +1,10 @@ +depthcharge/depthcharge/ +FILO/filo/ +GRUB2/grub2/ +LinuxBoot/linuxboot/ +SeaBIOS/seabios/ +tianocore/tianocore/ +tint/tint/ +U-Boot/u-boot/ +Memtest86Plus/memtest86plus/ +iPXE/ipxe/ diff --git a/payloads/external/FILO/Kconfig b/payloads/external/FILO/Kconfig index 94d5e18df0..1cf171d2cf 100644 --- a/payloads/external/FILO/Kconfig +++ b/payloads/external/FILO/Kconfig @@ -5,9 +5,9 @@ choice default FILO_STABLE config FILO_STABLE - bool "0.6.0" + bool "tested" help - Stable FILO version + Tested FILO version config FILO_MASTER bool "HEAD" diff --git a/payloads/external/FILO/Makefile b/payloads/external/FILO/Makefile index a89ea2af59..6175cfe62c 100644 --- a/payloads/external/FILO/Makefile +++ b/payloads/external/FILO/Makefile @@ -1,6 +1,6 @@ TAG-$(CONFIG_FILO_MASTER)=origin/master NAME-$(CONFIG_FILO_MASTER)=MASTER -TAG-$(CONFIG_FILO_STABLE)=22baa6bde9339029edfafa421b3d4a7be159edad +TAG-$(CONFIG_FILO_STABLE)=c2fa1ea6125c63e84cdf7779c37d76da8c5bc412 NAME-$(CONFIG_FILO_STABLE)=STABLE project_git_repo=https://review.coreboot.org/filo.git diff --git a/payloads/libpayload/.gitignore b/payloads/libpayload/.gitignore new file mode 100644 index 0000000000..c7b20fc357 --- /dev/null +++ b/payloads/libpayload/.gitignore @@ -0,0 +1 @@ +install/ diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index b5dc9a3c8b..f5b81a9f00 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -79,6 +79,14 @@ config COMPILER_LLVM_CLANG endchoice +config LTO + bool "Use link time optimization (LTO)" + default n + depends on COMPILER_GCC + help + Compile with link time optimization. This can often decrease the + final binary size, but may increase compilation time. + config REMOTEGDB bool "Remote GDB stub" default n diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index 2acf2266da..1b2a883b16 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -64,6 +64,10 @@ CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wvla CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough CFLAGS += -Wstrict-aliasing -Wshadow -Werror +ifeq ($(CONFIG_LP_LTO),y) +CFLAGS += -flto +endif + $(obj)/libpayload-config.h: $(KCONFIG_AUTOHEADER) cmp $@ $< 2>/dev/null || cp $< $@ diff --git a/payloads/libpayload/arch/x86/timer.c b/payloads/libpayload/arch/x86/timer.c index 1ff2cd6d55..6dcfd5b27f 100644 --- a/payloads/libpayload/arch/x86/timer.c +++ b/payloads/libpayload/arch/x86/timer.c @@ -33,6 +33,10 @@ #include #include +#include +#include + +#define MSR_PLATFORM_INFO 0xce /** * @ingroup arch @@ -41,11 +45,11 @@ uint32_t cpu_khz; /** - * Calculate the speed of the processor for use in delays. + * @brief Measure the speed of the processor for use in delays * * @return The CPU speed in kHz. */ -unsigned int get_cpu_speed(void) +static unsigned int calibrate_pit(void) { unsigned long long start, end; const uint32_t clock_rate = 1193182; // 1.193182 MHz @@ -71,7 +75,116 @@ unsigned int get_cpu_speed(void) * clock_rate / (interval * 1000). Multiply that by the number of * measured clocks to get the kHz value. */ - cpu_khz = (end - start) * clock_rate / (1000 * interval); + return (end - start) * clock_rate / (1000 * interval); +} + +/** + * @brief Calculates the core clock frequency via CPUID 0x15 + * + * Newer Intel CPUs report their core clock in CPUID leaf 0x15. Early models + * supporting this leaf didn't provide the nominal crystal frequency in ecx, + * hence we use hard coded values for them. + */ +static int get_cpu_khz_xtal(void) +{ + uint32_t ecx, edx, num, denom; + uint64_t nominal; + + if (cpuid_max() < 0x15) + return -1; + cpuid(0x15, denom, num, ecx, edx); + + if (denom == 0 || num == 0) + return -1; + + if (ecx != 0) { + nominal = ecx; + } else { + if (cpuid_family() != 6) + return -1; + + switch (cpuid_model()) { + case SKYLAKE_U_Y: + case SKYLAKE_S_H: + case KABYLAKE_U_Y: + case KABYLAKE_S_H: + nominal = 24000000; + break; + case APOLLOLAKE: + nominal = 19200000; + break; + default: + return -1; + } + } + + return nominal * num / denom / 1000; +} + +/** + * @brief Returns three times the bus clock in kHz + * + * The result of calculations with the returned value shall be divided by 3. + * This helps to avoid rounding errors. + */ +static int get_bus_khz_x3(void) +{ + if (cpuid_family() != 6) + return -1; + + switch (cpuid_model()) { + case NEHALEM: + return 400 * 1000; /* 133 MHz */ + case SANDYBRIDGE: + case IVYBRIDGE: + case HASWELL: + case HASWELL_U: + case HASWELL_GT3E: + case BROADWELL: + case BROADWELL_U: + return 300 * 1000; /* 100 MHz */ + default: + return -1; + } +} + +/** + * @brief Returns the calculated CPU frequency + * + * Over the years, multiple ways to discover the CPU frequency have been + * exposed through CPUID and MSRs. Try the most recent and accurate first + * (crystal information in CPUID leaf 0x15) and then fall back to older + * methods. + * + * This should cover all Intel Core i processors at least. For older + * processors we fall back to the PIT calibration. + */ +static int get_cpu_khz_fast(void) +{ + /* Try core crystal clock frequency first (supposed to be more accurate). */ + const int cpu_khz_xtal = get_cpu_khz_xtal(); + if (cpu_khz_xtal > 0) + return cpu_khz_xtal; + + /* Try `bus clock * speedstep multiplier`. */ + const int bus_x3 = get_bus_khz_x3(); + if (bus_x3 <= 0) + return -1; + /* + * Systems with an invariant TSC report the multiplier (maximum + * non-turbo ratio) in MSR_PLATFORM_INFO[15:8]. + */ + const unsigned int mult = _rdmsr(MSR_PLATFORM_INFO) >> 8 & 0xff; + return bus_x3 * mult / 3; +} + +unsigned int get_cpu_speed(void) +{ + const int cpu_khz_fast = get_cpu_khz_fast(); + if (cpu_khz_fast > 0) + cpu_khz = (unsigned int)cpu_khz_fast; + else + cpu_khz = calibrate_pit(); return cpu_khz; } diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index bfdd21e692..64db83bbd4 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -80,6 +80,7 @@ enum { CB_TAG_TCPA_LOG = 0x0036, CB_TAG_FMAP = 0x0037, CB_TAG_SMMSTOREV2 = 0x0039, + CB_TAG_BOARD_CONFIG = 0x0040, CB_TAG_CMOS_OPTION_TABLE = 0x00c8, CB_TAG_OPTION = 0x00c9, CB_TAG_OPTION_ENUM = 0x00ca, @@ -260,12 +261,6 @@ struct cb_x86_rom_mtrr { uint32_t index; }; -struct cb_strapping_id { - uint32_t tag; - uint32_t size; - uint32_t id_code; -}; - struct cb_spi_flash { uint32_t tag; uint32_t size; @@ -317,6 +312,16 @@ struct cb_mmc_info { int32_t early_cmd1_status; }; +struct cb_board_config { + uint32_t tag; + uint32_t size; + + struct cbuint64 fw_config; + uint32_t board_id; + uint32_t ram_code; + uint32_t sku_id; +}; + #define CB_MAX_SERIALNO_LENGTH 32 struct cb_cmos_option_table { diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index a3f61e7ffa..dd739abab4 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -107,11 +107,18 @@ struct sysinfo_t { uintptr_t mrc_cache; uintptr_t acpi_gnvs; -#define UNDEFINED_STRAPPING_ID (~0) +#define UNDEFINED_STRAPPING_ID (~0) +#define UNDEFINED_FW_CONFIG ~((uint64_t)0) u32 board_id; u32 ram_code; u32 sku_id; + /* + * A payload using this field is responsible for ensuring it checks its + * value against UNDEFINED_FW_CONFIG before using it. + */ + u64 fw_config; + uintptr_t wifi_calibration; uint64_t ramoops_buffer; uint32_t ramoops_buffer_size; diff --git a/payloads/libpayload/include/x86/arch/cpuid.h b/payloads/libpayload/include/x86/arch/cpuid.h index c77be9cff2..ddd606a072 100644 --- a/payloads/libpayload/include/x86/arch/cpuid.h +++ b/payloads/libpayload/include/x86/arch/cpuid.h @@ -64,4 +64,20 @@ static inline unsigned int cpuid_model(void) return (eax & 0xf0000) >> (16 - 4) | (eax & 0xf0) >> 4; } +enum intel_fam6_model { + NEHALEM = 0x25, + SANDYBRIDGE = 0x2a, + IVYBRIDGE = 0x3a, + HASWELL = 0x3c, + BROADWELL_U = 0x3d, + HASWELL_U = 0x45, + HASWELL_GT3E = 0x46, + BROADWELL = 0x47, + SKYLAKE_U_Y = 0x4e, + APOLLOLAKE = 0x5c, + SKYLAKE_S_H = 0x5e, + KABYLAKE_U_Y = 0x8e, + KABYLAKE_S_H = 0x9e, +}; + #endif diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index c48b6cffd8..b7d2a537b5 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -143,22 +143,13 @@ static void cb_parse_acpi_gnvs(unsigned char *ptr, struct sysinfo_t *info) info->acpi_gnvs = get_cbmem_addr(ptr); } -static void cb_parse_board_id(unsigned char *ptr, struct sysinfo_t *info) +static void cb_parse_board_config(unsigned char *ptr, struct sysinfo_t *info) { - struct cb_strapping_id *const cbbid = (struct cb_strapping_id *)ptr; - info->board_id = cbbid->id_code; -} - -static void cb_parse_ram_code(unsigned char *ptr, struct sysinfo_t *info) -{ - struct cb_strapping_id *const ram_code = (struct cb_strapping_id *)ptr; - info->ram_code = ram_code->id_code; -} - -static void cb_parse_sku_id(unsigned char *ptr, struct sysinfo_t *info) -{ - struct cb_strapping_id *const sku_id = (struct cb_strapping_id *)ptr; - info->sku_id = sku_id->id_code; + struct cb_board_config *const config = (struct cb_board_config *)ptr; + info->fw_config = cb_unpack64(config->fw_config); + info->board_id = config->board_id; + info->ram_code = config->ram_code; + info->sku_id = config->sku_id; } #if CONFIG(LP_NVRAM) @@ -290,6 +281,7 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) info->board_id = UNDEFINED_STRAPPING_ID; info->ram_code = UNDEFINED_STRAPPING_ID; info->sku_id = UNDEFINED_STRAPPING_ID; + info->fw_config = UNDEFINED_FW_CONFIG; /* Now, walk the tables. */ ptr += header->header_bytes; @@ -381,14 +373,8 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_ACPI_GNVS: cb_parse_acpi_gnvs(ptr, info); break; - case CB_TAG_BOARD_ID: - cb_parse_board_id(ptr, info); - break; - case CB_TAG_RAM_CODE: - cb_parse_ram_code(ptr, info); - break; - case CB_TAG_SKU_ID: - cb_parse_sku_id(ptr, info); + case CB_TAG_BOARD_CONFIG: + cb_parse_board_config(ptr, info); break; case CB_TAG_WIFI_CALIBRATION: cb_parse_wifi_calibration(ptr, info); diff --git a/payloads/nvramcui/.gitignore b/payloads/nvramcui/.gitignore new file mode 100644 index 0000000000..4885853d42 --- /dev/null +++ b/payloads/nvramcui/.gitignore @@ -0,0 +1,2 @@ +build +libpayload diff --git a/src/Kconfig b/src/Kconfig index d265da7797..dc98ca2c05 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -915,6 +915,15 @@ config DEBUG_MALLOC If unsure, say N. +# Only visible if DEBUG_SPEW (8) is set. +config DEBUG_RESOURCES + bool "Output verbose PCI MEM and IO resource debug messages" if DEFAULT_CONSOLE_LOGLEVEL_8 + default n + help + This option enables additional PCI memory and IO debug messages. + Note: This option will increase the size of the coreboot image. + If unsure, say N. + config DEBUG_CONSOLE_INIT bool "Debug console initialisation code" default n @@ -1114,6 +1123,16 @@ config TRACE of calling function. Please note some printk related functions are omitted from trace to have good looking console dumps. +config DEBUG_FUNC + bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8 + default n + help + This option enables additional function entry and exit debug messages + for select functions. If supported, this is less output than + the TRACE option. + Note: This option will increase the size of the coreboot image. + If unsure, say N. + config DEBUG_COVERAGE bool "Debug code coverage" default n diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index 5bd6cf9e65..b2225cb114 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -30,6 +30,13 @@ ramstage-y += cbfs.c smm-y += cbfs.c postcar-y += cbfs.c +bootblock-y += bsd/cbfs_private.c +verstage-y += bsd/cbfs_private.c +romstage-y += bsd/cbfs_private.c +postcar-y += bsd/cbfs_private.c +ramstage-y += bsd/cbfs_private.c +smm-y += bsd/cbfs_private.c + decompressor-y += bsd/lz4_wrapper.c bootblock-y += bsd/lz4_wrapper.c verstage-y += bsd/lz4_wrapper.c diff --git a/src/commonlib/bsd/cbfs_private.c b/src/commonlib/bsd/cbfs_private.c new file mode 100644 index 0000000000..035684b91e --- /dev/null +++ b/src/commonlib/bsd/cbfs_private.c @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */ + +#include +#include + +static cb_err_t read_next_header(cbfs_dev_t dev, size_t *offset, struct cbfs_file *buffer) +{ + const size_t devsize = cbfs_dev_size(dev); + DEBUG("Looking for next file @%#zx...\n", *offset); + *offset = ALIGN_UP(*offset, CBFS_ALIGNMENT); + while (*offset + sizeof(*buffer) < devsize) { + if (cbfs_dev_read(dev, buffer, *offset, sizeof(*buffer)) != sizeof(*buffer)) + return CB_CBFS_IO; + + if (memcmp(buffer->magic, CBFS_FILE_MAGIC, sizeof(buffer->magic)) == 0) + return CB_SUCCESS; + + *offset += CBFS_ALIGNMENT; + } + + DEBUG("End of CBFS reached\n"); + return CB_CBFS_NOT_FOUND; +} + +cb_err_t cbfs_walk(cbfs_dev_t dev, cb_err_t (*walker)(cbfs_dev_t dev, size_t offset, + const union cbfs_mdata *mdata, + size_t already_read, void *arg), + void *arg, struct vb2_hash *metadata_hash, enum cbfs_walk_flags flags) +{ + const bool do_hash = CBFS_ENABLE_HASHING && metadata_hash; + struct vb2_digest_context dc; + vb2_error_t vbrv; + + assert(CBFS_ENABLE_HASHING || (!metadata_hash && !(flags & CBFS_WALK_WRITEBACK_HASH))); + if (do_hash && (vbrv = vb2_digest_init(&dc, metadata_hash->algo))) { + ERROR("Metadata hash digest (%d) init error: %#x\n", metadata_hash->algo, vbrv); + return CB_ERR_ARG; + } + + size_t offset = 0; + cb_err_t ret_header; + cb_err_t ret_walker = CB_CBFS_NOT_FOUND; + union cbfs_mdata mdata; + while ((ret_header = read_next_header(dev, &offset, &mdata.h)) == CB_SUCCESS) { + const uint32_t attr_offset = be32toh(mdata.h.attributes_offset); + const uint32_t data_offset = be32toh(mdata.h.offset); + const uint32_t data_length = be32toh(mdata.h.len); + const uint32_t type = be32toh(mdata.h.type); + const bool empty = (type == CBFS_TYPE_DELETED || type == CBFS_TYPE_DELETED2); + + DEBUG("Found CBFS header @%#zx (type %d, attr +%#x, data +%#x, length %#x)\n", + offset, type, attr_offset, data_offset, data_length); + if (data_offset > sizeof(mdata)) { + ERROR("File metadata @%#zx too large\n", offset); + goto next_file; + } + + if (empty && !(flags & CBFS_WALK_INCLUDE_EMPTY)) + goto next_file; + + /* When hashing we need to read everything. Otherwise skip the attributes. + attr_offset may be 0, which means there are no attributes. */ + ssize_t todo; + if (do_hash || attr_offset == 0) + todo = data_offset - sizeof(mdata.h); + else + todo = attr_offset - sizeof(mdata.h); + if (todo <= 0 || data_offset < attr_offset) { + ERROR("Corrupt file header @%#zx\n", offset); + goto next_file; + } + + /* Read the rest of the metadata (filename, and possibly attributes). */ + assert(todo > 0 && todo <= sizeof(mdata) - sizeof(mdata.h)); + if (cbfs_dev_read(dev, mdata.raw + sizeof(mdata.h), + offset + sizeof(mdata.h), todo) != todo) + return CB_CBFS_IO; + DEBUG("File name: '%s'\n", mdata.filename); + + if (do_hash && !empty && vb2_digest_extend(&dc, mdata.raw, data_offset)) + return CB_ERR; + + if (walker && ret_walker == CB_CBFS_NOT_FOUND) + ret_walker = walker(dev, offset, &mdata, sizeof(mdata.h) + todo, arg); + + /* Return IO errors immediately. For others, finish the hash first if needed. */ + if (ret_walker == CB_CBFS_IO || (ret_walker != CB_CBFS_NOT_FOUND && !do_hash)) + return ret_walker; + +next_file: + offset += data_offset + data_length; + } + + if (ret_header != CB_CBFS_NOT_FOUND) + return ret_header; + + if (do_hash) { + uint8_t real_hash[VB2_MAX_DIGEST_SIZE]; + size_t hash_size = vb2_digest_size(metadata_hash->algo); + if (vb2_digest_finalize(&dc, real_hash, hash_size)) + return CB_ERR; + if (flags & CBFS_WALK_WRITEBACK_HASH) + memcpy(metadata_hash->raw, real_hash, hash_size); + else if (memcmp(metadata_hash->raw, real_hash, hash_size) != 0) + return CB_CBFS_HASH_MISMATCH; + } + + return ret_walker; +} + +cb_err_t cbfs_copy_fill_metadata(union cbfs_mdata *dst, const union cbfs_mdata *src, + size_t already_read, cbfs_dev_t dev, size_t offset) +{ + /* First, copy the stuff that cbfs_walk() already read for us. */ + memcpy(dst, src, already_read); + + /* Then read in whatever metadata may be left (will only happen in non-hashing case). */ + const size_t todo = be32toh(src->h.offset) - already_read; + assert(todo <= sizeof(*dst) - already_read); + if (todo && cbfs_dev_read(dev, dst->raw + already_read, offset + already_read, + todo) != todo) + return CB_CBFS_IO; + return CB_SUCCESS; +} + +struct cbfs_lookup_args { + union cbfs_mdata *mdata_out; + const char *name; + size_t namesize; + size_t *data_offset_out; +}; + +static cb_err_t lookup_walker(cbfs_dev_t dev, size_t offset, const union cbfs_mdata *mdata, + size_t already_read, void *arg) +{ + struct cbfs_lookup_args *args = arg; + + /* Check if the name we're looking for could fit, then we can safely memcmp() it. */ + if (args->namesize > already_read - offsetof(union cbfs_mdata, filename) || + memcmp(args->name, mdata->filename, args->namesize) != 0) + return CB_CBFS_NOT_FOUND; + + LOG("Found '%s' @%#zx size %#x\n", args->name, offset, be32toh(mdata->h.len)); + if (cbfs_copy_fill_metadata(args->mdata_out, mdata, already_read, dev, offset)) + return CB_CBFS_IO; + + *args->data_offset_out = offset + be32toh(mdata->h.offset); + return CB_SUCCESS; +} + +cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out, + size_t *data_offset_out, struct vb2_hash *metadata_hash) +{ + struct cbfs_lookup_args args = { + .mdata_out = mdata_out, + .name = name, + .namesize = strlen(name) + 1, /* Count trailing \0 so we can memcmp() it. */ + .data_offset_out = data_offset_out, + }; + return cbfs_walk(dev, lookup_walker, &args, metadata_hash, 0); +} diff --git a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h index ab419a7709..e5aa852617 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h @@ -34,6 +34,11 @@ enum cb_err { CB_I2C_PROTOCOL_ERROR = -302, /**< Data lost or spurious slave device response, try again? */ CB_I2C_TIMEOUT = -303, /**< Transmission timed out */ + + /* CBFS errors */ + CB_CBFS_IO = -400, /**< Underlying I/O error */ + CB_CBFS_NOT_FOUND = -401, /**< File not found in directory */ + CB_CBFS_HASH_MISMATCH = -402, /**< Master hash validation failed */ }; /* Don't typedef the enum directly, so the size is unambiguous for serialization. */ diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h new file mode 100644 index 0000000000..aaee62f4c3 --- /dev/null +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */ + +#ifndef _COMMONLIB_BSD_CBFS_PRIVATE_H_ +#define _COMMONLIB_BSD_CBFS_PRIVATE_H_ + + +#include +#include +#include +#include +#include +#include + +/* + * This header implements low-level CBFS access APIs that can be shared across different + * host applications (e.g. coreboot, libpayload, cbfstool). For verification purposes it + * implements the metadata hashing part but not the file hashing part, so the host application + * will need to verify file hashes itself after loading each file. Host applications that use + * verification should implement wrapper APIs that combine the lookup, loading and hashing steps + * into a single, safe function call and outside of the code implementing those APIs should not + * be accessing the low-level APIs in this file directly (e.g. coreboot SoC/driver code should + * never directly #include this file, and always use the higher level APIs in src/lib/cbfs.c). + * + * needs to be provided by the host application using this CBFS library. It must + * define the following type, macros and functions: + * + * cbfs_dev_t An opaque type representing a CBFS storage backend. + * CBFS_ENABLE_HASHING Should be 0 to avoid linking hashing features, 1 otherwise. (Only for + * metadata hashing. Host application needs to check file hashes itself.) + * ERROR(...) printf-style macro to print errors. + * LOG(...) printf-style macro to print normal-operation log messages. + * DEBUG(...) printf-style macro to print detailed debug output. + * + * ssize_t cbfs_dev_read(cbfs_dev_t dev, void *buffer, size_t offset, size_t size); + * Read |size| bytes starting at |offset| from |dev| into |buffer|. + * Returns amount of bytes read on success and < 0 on error. + * This function *MUST* sanity-check offset/size on its own. + * + * size_t cbfs_dev_size(cbfs_dev_t dev); + * Return the total size in bytes of the CBFS storage (actual CBFS area). + */ +#include + +/* + * Helper structure to allocate space for a blob of metadata on the stack. + * NOTE: The fields in any union cbfs_mdata or any of its substructures from cbfs_serialized.h + * should always remain in the same byte order as they are stored on flash (= big endian). To + * avoid byte-order confusion, fields should always and only be converted to host byte order at + * exactly the time they are read from one of these structures into their own separate variable. + */ +#define CBFS_METADATA_MAX_SIZE 256 +union cbfs_mdata { + struct { + struct cbfs_file h; + char filename[]; + }; + uint8_t raw[CBFS_METADATA_MAX_SIZE]; +}; + +/* Flags that modify behavior of cbfs_walk(). */ +enum cbfs_walk_flags { + /* Write the calculated hash back out to |metadata_hash->hash| rather than comparing it. + |metadata_hash->algo| must still have been initialized by the caller. */ + CBFS_WALK_WRITEBACK_HASH = (1 << 0), + /* Call |walker| for empty file entries (i.e. entries with one of the CBFS_TYPE_DELETED + types that mark free space in the CBFS). Otherwise, those entries will be skipped. + Either way, these entries are never included in the metadata_hash calculation. */ + CBFS_WALK_INCLUDE_EMPTY = (1 << 1), +}; + +/* + * Traverse a CBFS and call a |walker| callback function for every file. Can additionally + * calculate a hash over the metadata of all files in the CBFS. If |metadata_hash| is NULL, + * hashing is disabled. If |walker| is NULL, will just traverse and hash the CBFS without + * invoking any callbacks (and always return CB_CBFS_NOT_FOUND unless there was another error). + * + * |arg| and |dev| will be passed through to |walker| unmodified. |offset| is the absolute + * offset in |dev| at which the current file metadata starts. |mdata| is a temporary buffer + * (only valid for the duration of this call to |walker|) containing already read metadata from + * the current file, up to |already_read| bytes. This will always at least contain the header + * fields and filename, but may contain more (i.e. attributes), depending on whether hashing is + * enabled. |walker| should call into cbfs_copy_fill_medadata() to copy the metadata of a file + * to a persistent buffer and automatically load remaining metadata from |dev| as needed based + * on the value of |already_read|. + * + * |walker| should return CB_CBFS_NOT_FOUND if it wants to continue being called for further + * files. Any other return code will be used as the final return code for cbfs_walk(). It will + * return immediately unless it needs to calculate a hash in which case it will still traverse + * the remaining CBFS (but not call |walker| anymore). + * + * Returns, from highest to lowest priority: + * CB_CBFS_IO - There was an IO error with the CBFS device (always considered fatal) + * CB_CBFS_HASH_MISMATCH - |metadata_hash| was provided and did not match the CBFS + * CB_SUCCESS/ - First non-CB_CBFS_NOT_FOUND code returned by walker() + * CB_CBFS_NOT_FOUND - walker() returned CB_CBFS_NOT_FOUND for every file in the CBFS + */ +cb_err_t cbfs_walk(cbfs_dev_t dev, cb_err_t (*walker)(cbfs_dev_t dev, size_t offset, + const union cbfs_mdata *mdata, + size_t already_read, void *arg), + void *arg, struct vb2_hash *metadata_hash, enum cbfs_walk_flags); + +/* + * Helper function that can be used by a |walker| callback to cbfs_walk() to copy the metadata + * of a file into a permanent buffer. Will copy the |already_read| metadata from |src| into + * |dst| and load remaining metadata from |dev| as required. + */ +cb_err_t cbfs_copy_fill_metadata(union cbfs_mdata *dst, const union cbfs_mdata *src, + size_t already_read, cbfs_dev_t dev, size_t offset); + +/* Find a file named |name| in the CBFS on |dev|. Copy its metadata (including attributes) + * into |mdata_out| and pass out the offset to the file data on the CBFS device. + * Verify the metadata with |metadata_hash| if provided. */ +cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out, + size_t *data_offset_out, struct vb2_hash *metadata_hash); + +#endif /* _COMMONLIB_BSD_CBFS_PRIVATE_H_ */ diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h index 3c76a49f55..7171634c8e 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h @@ -4,6 +4,7 @@ #define _CBFS_SERIALIZED_H_ #include +#include /** These are standard values for the known compression algorithms that coreboot knows about for stages and @@ -124,12 +125,11 @@ struct cbfs_file_attr_compression { uint32_t decompressed_size; } __packed; +/* Actual size in CBFS may be larger/smaller than struct size! */ struct cbfs_file_attr_hash { uint32_t tag; uint32_t len; - uint32_t hash_type; - /* hash_data is len - sizeof(struct) bytes */ - uint8_t hash_data[]; + struct vb2_hash hash; } __packed; struct cbfs_file_attr_position { diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c index 115f99a68e..999c35e52a 100644 --- a/src/commonlib/cbfs.c +++ b/src/commonlib/cbfs.c @@ -7,21 +7,6 @@ #include #include -#if !defined(LOG) -#define LOG(x...) printk(BIOS_INFO, "CBFS: " x) -#endif -#if defined(CONFIG) - -#if CONFIG(DEBUG_CBFS) -#define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x) -#else -#define DEBUG(x...) -#endif - -#elif !defined(DEBUG) -#define DEBUG(x...) -#endif - static size_t cbfs_next_offset(const struct region_device *cbfs, const struct cbfsf *f) { diff --git a/src/commonlib/include/commonlib/cbfs.h b/src/commonlib/include/commonlib/cbfs.h index 90aa0b2571..6565c1dcd3 100644 --- a/src/commonlib/include/commonlib/cbfs.h +++ b/src/commonlib/include/commonlib/cbfs.h @@ -3,7 +3,7 @@ #ifndef _COMMONLIB_CBFS_H_ #define _COMMONLIB_CBFS_H_ -#include +#include #include #include @@ -11,6 +11,7 @@ struct cbfsf { struct region_device metadata; struct region_device data; + union cbfs_mdata mdata; }; /* Locate file by name and optional type. Returns 0 on success else < 0 on diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 44060025b3..3e74e6b59c 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -62,15 +62,15 @@ enum { LB_TAG_DMA = 0x0022, LB_TAG_RAM_OOPS = 0x0023, LB_TAG_ACPI_GNVS = 0x0024, - LB_TAG_BOARD_ID = 0x0025, + LB_TAG_BOARD_ID = 0x0025, /* deprecated */ LB_TAG_VERSION_TIMESTAMP = 0x0026, LB_TAG_WIFI_CALIBRATION = 0x0027, - LB_TAG_RAM_CODE = 0x0028, + LB_TAG_RAM_CODE = 0x0028, /* deprecated */ LB_TAG_SPI_FLASH = 0x0029, LB_TAG_SERIALNO = 0x002a, LB_TAG_MTC = 0x002b, LB_TAG_VPD = 0x002c, - LB_TAG_SKU_ID = 0x002d, + LB_TAG_SKU_ID = 0x002d, /* deprecated */ LB_TAG_BOOT_MEDIA_PARAMS = 0x0030, LB_TAG_CBMEM_ENTRY = 0x0031, LB_TAG_TSC_INFO = 0x0032, @@ -81,6 +81,8 @@ enum { LB_TAG_FMAP = 0x0037, LB_TAG_PLATFORM_BLOB_VERSION = 0x0038, LB_TAG_SMMSTOREV2 = 0x0039, + LB_TAG_BOARD_CONFIG = 0x0040, + /* The following options are CMOS-related */ LB_TAG_CMOS_OPTION_TABLE = 0x00c8, LB_TAG_OPTION = 0x00c9, LB_TAG_OPTION_ENUM = 0x00ca, @@ -347,12 +349,6 @@ struct lb_x86_rom_mtrr { uint32_t index; }; -struct lb_strapping_id { - uint32_t tag; - uint32_t size; - uint32_t id_code; -}; - struct lb_spi_flash { uint32_t tag; uint32_t size; @@ -416,6 +412,16 @@ struct lb_macs { struct mac_address mac_addrs[0]; }; +struct lb_board_config { + uint32_t tag; + uint32_t size; + + struct lb_uint64 fw_config; + uint32_t board_id; + uint32_t ram_code; + uint32_t sku_id; +}; + #define MAX_SERIALNO_LENGTH 32 /* The following structures are for the CMOS definitions table */ diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 1849f19a3e..01913de312 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -10,9 +10,9 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559 subdirs-$(CONFIG_CPU_INTEL_SOCKET_M) += socket_m subdirs-$(CONFIG_CPU_INTEL_SOCKET_P) += socket_p subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604 -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IRONLAKE) += model_2065x -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell +subdirs-$(CONFIG_CPU_INTEL_MODEL_2065X) += model_2065x +subdirs-$(CONFIG_CPU_INTEL_MODEL_206AX) += model_206ax +subdirs-$(CONFIG_CPU_INTEL_HASWELL) += haswell subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775 diff --git a/src/cpu/intel/car/cache_as_ram_symbols.inc b/src/cpu/intel/car/cache_as_ram_symbols.inc new file mode 100644 index 0000000000..857e039952 --- /dev/null +++ b/src/cpu/intel/car/cache_as_ram_symbols.inc @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Trick the linker into supporting x86_64 relocations in 32bit code */ +#if ENV_X86_64 +#define uintptr_t quad +#else +#define uintptr_t long +#endif + +rom_mtrr_mask: +.uintptr_t _rom_mtrr_mask + +rom_mtrr_base: +.uintptr_t _rom_mtrr_base + +car_mtrr_mask: +.uintptr_t _car_mtrr_mask + +car_mtrr_start: +.uintptr_t _car_mtrr_start diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index d08736585d..cde1ca3d15 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -9,6 +9,8 @@ .global bootblock_pre_c_entry +#include + .code32 _cache_as_ram_setup: @@ -83,11 +85,10 @@ addrsize_set_high: movl $MTRR_PHYS_MASK(1), %ecx wrmsr - post_code(0x23) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx - movl $_car_mtrr_start, %eax + movl car_mtrr_start, %eax orl $MTRR_TYPE_WRBACK, %eax xorl %edx, %edx wrmsr @@ -96,20 +97,20 @@ addrsize_set_high: /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr - movl $_car_mtrr_mask, %eax + mov car_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr /* Enable cache for our code in Flash because we do XIP here */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx - movl $_rom_mtrr_base, %eax + mov rom_mtrr_base, %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $_rom_mtrr_mask, %eax + mov rom_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr @@ -207,8 +208,19 @@ end_microcode_update: /* Need to align stack to 16 bytes at call instruction. Account for the pushes below. */ andl $0xfffffff0, %esp - subl $4, %esp +#if ENV_X86_64 + + #include + + movd %mm2, %rdi + shlq $32, %rdi + movd %mm1, %rsi + or %rsi, %rdi + movd %mm0, %rsi + +#else + subl $4, %esp /* push TSC and BIST to stack */ movd %mm0, %eax pushl %eax /* BIST */ @@ -216,6 +228,7 @@ end_microcode_update: pushl %eax /* tsc[63:32] */ movd %mm1, %eax pushl %eax /* tsc[31:0] */ +#endif before_c_entry: post_code(0x29) diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 3ea8f36ea8..c5f43ef22e 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -130,13 +130,6 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) */ config->regs[CPPC_HIGHEST_PERF] = msr; - /* - * Nominal Performance -> Guaranteed Performance: - * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x771, 0x04,)}, - */ - msr.bit_offset = 8; - config->regs[CPPC_NOMINAL_PERF] = msr; - /* * Lowest Nonlinear Performance -> Most Efficient Performance: * ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x771, 0x04,)}, @@ -158,6 +151,15 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) msr.bit_offset = 8; config->regs[CPPC_GUARANTEED_PERF] = msr; + msr.addrl = MSR_PLATFORM_INFO; + + /* + * Nominal Performance -> Maximum Non-Turbo Ratio: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0xce, 0x04,)}, + */ + msr.bit_offset = 8; + config->regs[CPPC_NOMINAL_PERF] = msr; + msr.addrl = IA32_HWP_REQUEST; /* diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index fd1ce9e912..e0e1e1cdd3 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -84,7 +84,7 @@ /* PCODE MMIO communications live in the MCHBAR. */ #define BIOS_MAILBOX_INTERFACE 0x5da4 -#define MAILBOX_RUN_BUSY (1UL << 31) +#define MAILBOX_RUN_BUSY (1 << 31) #define MAILBOX_BIOS_CMD_READ_PCS 1 #define MAILBOX_BIOS_CMD_WRITE_PCS 2 #define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 04ce2261de..988d664c94 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -3,7 +3,7 @@ #include #include -void do_lapic_init(void) +void lapic_virtual_wire_mode_init(void) { /* this is so interrupts work. This is very limited scope -- * linux will do better later, we hope ... diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 4870529cfe..01c1d5fb83 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -112,7 +112,7 @@ extern char _binary_sipi_vector_start[]; /* The SIPI vector is loaded at the SMM_DEFAULT_BASE. The reason is at the * memory range is already reserved so the OS cannot use it. That region is * free to use for AP bringup before SMM is initialized. */ -static const uint32_t sipi_vector_location = SMM_DEFAULT_BASE; +static const uintptr_t sipi_vector_location = SMM_DEFAULT_BASE; static const int sipi_vector_location_size = SMM_DEFAULT_SIZE; struct mp_flight_plan { @@ -338,16 +338,16 @@ static atomic_t *load_sipi_vector(struct mp_params *mp_params) setup_default_sipi_vector_params(sp); /* Setup MSR table. */ - sp->msr_table_ptr = (uint32_t)&mod_loc[module_size]; + sp->msr_table_ptr = (uintptr_t)&mod_loc[module_size]; sp->msr_count = num_msrs; /* Provide pointer to microcode patch. */ - sp->microcode_ptr = (uint32_t)mp_params->microcode_pointer; + sp->microcode_ptr = (uintptr_t)mp_params->microcode_pointer; /* Pass on ability to load microcode in parallel. */ if (mp_params->parallel_microcode_load) sp->microcode_lock = 0; else sp->microcode_lock = ~0; - sp->c_handler = (uint32_t)&ap_init; + sp->c_handler = (uintptr_t)&ap_init; ap_count = &sp->ap_count; atomic_set(ap_count, 0); @@ -434,7 +434,7 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps) if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); if (apic_wait_timeout(1000 /* 1 ms */, 50)) { - printk(BIOS_DEBUG, "timed out. Aborting.\n"); + printk(BIOS_ERR, "timed out. Aborting.\n"); return -1; } printk(BIOS_DEBUG, "done.\n"); @@ -451,7 +451,7 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps) if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); if (apic_wait_timeout(1000 /* 1 ms */, 50)) { - printk(BIOS_DEBUG, "timed out. Aborting.\n"); + printk(BIOS_ERR, "timed out. Aborting.\n"); return -1; } printk(BIOS_DEBUG, "done.\n"); @@ -462,7 +462,7 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps) LAPIC_DM_STARTUP | sipi_vector); printk(BIOS_DEBUG, "Waiting for 1st SIPI to complete..."); if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) { - printk(BIOS_DEBUG, "timed out.\n"); + printk(BIOS_ERR, "timed out.\n"); return -1; } printk(BIOS_DEBUG, "done.\n"); @@ -477,7 +477,7 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps) if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); if (apic_wait_timeout(1000 /* 1 ms */, 50)) { - printk(BIOS_DEBUG, "timed out. Aborting.\n"); + printk(BIOS_ERR, "timed out. Aborting.\n"); return -1; } printk(BIOS_DEBUG, "done.\n"); @@ -488,14 +488,14 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps) LAPIC_DM_STARTUP | sipi_vector); printk(BIOS_DEBUG, "Waiting for 2nd SIPI to complete..."); if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) { - printk(BIOS_DEBUG, "timed out.\n"); + printk(BIOS_ERR, "timed out.\n"); return -1; } printk(BIOS_DEBUG, "done.\n"); /* Wait for CPUs to check in. */ - if (wait_for_aps(num_aps, ap_count, 10000 /* 10 ms */, 50 /* us */)) { - printk(BIOS_DEBUG, "Not all APs checked in: %d/%d.\n", + if (wait_for_aps(num_aps, ap_count, 100000 /* 100 ms */, 50 /* us */)) { + printk(BIOS_ERR, "Not all APs checked in: %d/%d.\n", atomic_read(num_aps), ap_count); return -1; } diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index ba1ecb7de6..054f30d2c4 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -121,7 +121,7 @@ _start: /* Protect microcode loading. */ lock_microcode: - lock bts $0, microcode_lock + lock btsl $0, microcode_lock jc lock_microcode load_microcode: diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 1273a6cf27..c2f49cf94d 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -20,7 +20,7 @@ smm-generic-ccopts += -D__SMM__ smm-c-deps:=$$(OPTION_TABLE_H) $(obj)/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) - $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(smm-objs) --no-whole-archive $(COMPILER_RT_smm) --end-group + $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(filter-out %.ld, $(smm-objs)) --no-whole-archive $(COMPILER_RT_smm) --end-group # change to the target path because objcopy will use the path name in its # ELF symbol names. @@ -76,8 +76,10 @@ $(obj)/smm/smm: $(obj)/smm/smm.elf.rmod else # CONFIG_SMM_TSEG -$(obj)/smm/smm: $(obj)/smm/smm.o $(src)/cpu/x86/smm/smm.ld - $(LD_smm) $(LDFLAGS_smm) -o $(obj)/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/smm/smm.o +smm-y += smm.ld + +$(obj)/smm/smm: $(obj)/smm/smm.o $(call src-to-obj,smm,$(src)/cpu/x86/smm/smm.ld) + $(LD_smm) $(LDFLAGS_smm) -o $(obj)/smm/smm.elf -T $(call src-to-obj,smm,$(src)/cpu/x86/smm/smm.ld) $(obj)/smm/smm.o $(NM_smm) -n $(obj)/smm/smm.elf | sort > $(obj)/smm/smm.map $(OBJCOPY_smm) -O binary $(obj)/smm/smm.elf $@ diff --git a/src/device/Kconfig b/src/device/Kconfig index cbe970f170..777f3f50d3 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -532,6 +532,17 @@ config PCI_ALLOW_BUS_MASTER instance, for libpayload based payloads as the drivers don't enable bus mastering for PCI bridges. +if PCI_ALLOW_BUS_MASTER + +config PCI_ALLOW_BUS_MASTER_ANY_DEVICE + bool "Any devices" + default y + help + Allow coreboot to enable PCI bus mastering for any device. The actual + selection of devices depends on the various PCI drivers in coreboot. + +endif # PCI_ALLOW_BUS_MASTER + endif # PCI if PCIEXP_PLUGIN_SUPPORT diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 279f8a1a0a..4ab45bcc09 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -40,7 +40,7 @@ static int codec_detect(u8 *base) int count; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) goto no_codec; /* clear STATESTS bits (BAR + 0xe)[2:0] */ @@ -62,11 +62,11 @@ static int codec_detect(u8 *base) goto no_codec; /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, 0) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, 0) < 0) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0] */ @@ -166,7 +166,7 @@ static void codec_init(struct device *dev, u8 *base, int addr) printk(BIOS_DEBUG, "azalia_audio: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) { + if (wait_for_ready(base) < 0) { printk(BIOS_DEBUG, " codec not ready.\n"); return; } @@ -174,7 +174,7 @@ static void codec_init(struct device *dev, u8 *base, int addr) reg32 = (addr << 28) | 0x000f0000; write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) { + if (wait_for_valid(base) < 0) { printk(BIOS_DEBUG, " codec not valid.\n"); return; } @@ -192,12 +192,12 @@ static void codec_init(struct device *dev, u8 *base, int addr) /* 3 */ for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, verb[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n"); diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index ad7afd8045..f12ff6e6a7 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -228,6 +228,7 @@ config FSP_STATUS_GLOBAL_RESET_REQUIRED_8 config FSP_STATUS_GLOBAL_RESET hex + depends on SOC_INTEL_COMMON_FSP_RESET default 0x40000003 if FSP_STATUS_GLOBAL_RESET_REQUIRED_3 default 0x40000004 if FSP_STATUS_GLOBAL_RESET_REQUIRED_4 default 0x40000005 if FSP_STATUS_GLOBAL_RESET_REQUIRED_5 @@ -240,6 +241,13 @@ config FSP_STATUS_GLOBAL_RESET reset type from SoC Kconfig based on available Kconfig options FSP_STATUS_GLOBAL_RESET_REQUIRED_X. Default is unsupported. +config SOC_INTEL_COMMON_FSP_RESET + bool + help + Common code block to handle platform reset request raised by FSP. The FSP + will use the FSP EAS v2.0 section 12.2.2 (OEM Status Code) to indicate that + a reset is required. + if FSP_PEIM_TO_PEIM_INTERFACE source "src/drivers/intel/fsp2_0/ppi/Kconfig" endif diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 32140f4228..46299ee470 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -2,6 +2,8 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) +bootblock-$(CONFIG_FSP_CAR) += fspt_report.c + romstage-y += debug.c romstage-y += hand_off_block.c romstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c diff --git a/src/drivers/intel/fsp2_0/fspt_report.c b/src/drivers/intel/fsp2_0/fspt_report.c new file mode 100644 index 0000000000..7fa3205e3d --- /dev/null +++ b/src/drivers/intel/fsp2_0/fspt_report.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* filled in assembly after FSP-T ran */ +uintptr_t temp_memory_start; +uintptr_t temp_memory_end; + +void report_fspt_output(void) +{ + const struct region fsp_car_region = { + .offset = temp_memory_start, + .size = temp_memory_end - temp_memory_start, + }; + const struct region coreboot_car_region = { + .offset = (uintptr_t)_car_region_start, + .size = (uintptr_t)_car_region_size, + }; + printk(BIOS_DEBUG, "FSP-T: reported temp_mem region: [0x%08lx,0x%08lx)\n", + temp_memory_start, temp_memory_end); + if (!region_is_subregion(&fsp_car_region, &coreboot_car_region)) { + printk(BIOS_ERR, "Wrong CAR region used!\n"); + printk(BIOS_ERR, "Adapt CONFIG_DCACHE_RAM_BASE and CONFIG_DCACHE_RAM_SIZE to match FSP-T\n"); + } +} diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index f154a34a34..a57b1bb942 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -89,6 +89,7 @@ bool fsp_guid_compare(const uint8_t guid1[16], const uint8_t guid2[16]); void fsp_find_bootloader_tolum(struct range_entry *re); void fsp_get_version(char *buf); void lb_string_platform_blob_version(struct lb_header *header); +void report_fspt_output(void); /* Fill in header and validate sanity of component within region device. */ enum cb_err fsp_validate_component(struct fsp_header *hdr, diff --git a/src/drivers/ocp/dmi/smbios.c b/src/drivers/ocp/dmi/smbios.c index 4e54af0b2a..d0ef11508d 100644 --- a/src/drivers/ocp/dmi/smbios.c +++ b/src/drivers/ocp/dmi/smbios.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include "ocp_dmi.h" diff --git a/src/drivers/soundwire/alc711/Kconfig b/src/drivers/soundwire/alc711/Kconfig new file mode 100644 index 0000000000..bdc02a9324 --- /dev/null +++ b/src/drivers/soundwire/alc711/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_SOUNDWIRE_ALC711 + bool diff --git a/src/drivers/soundwire/alc711/Makefile.inc b/src/drivers/soundwire/alc711/Makefile.inc new file mode 100644 index 0000000000..78e4d1b7fe --- /dev/null +++ b/src/drivers/soundwire/alc711/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_SOUNDWIRE_ALC711) += alc711.c diff --git a/src/drivers/soundwire/alc711/alc711.c b/src/drivers/soundwire/alc711/alc711.c new file mode 100644 index 0000000000..8382fc94fb --- /dev/null +++ b/src/drivers/soundwire/alc711/alc711.c @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" + +static struct soundwire_address alc711_address = { + .version = SOUNDWIRE_VERSION_1_1, + .manufacturer_id = MIPI_MFG_ID_REALTEK, + .part_id = MIPI_DEV_ID_REALTEK_ALC711, + .class = MIPI_CLASS_NONE +}; + +static struct soundwire_slave alc711_slave = { + .wake_up_unavailable = false, + .test_mode_supported = false, + .clock_stop_mode1_supported = true, + .simplified_clockstopprepare_sm_supported = true, + .clockstopprepare_hard_reset_behavior = false, + .highPHY_capable = false, + .paging_supported = false, + .bank_delay_supported = false, + .port15_read_behavior = false, + .source_port_list = SOUNDWIRE_PORT(2), + .sink_port_list = SOUNDWIRE_PORT(1), +}; + +static struct soundwire_audio_mode alc711_audio_mode = { + /* Bus frequency must be 1/2/4/8 divider of supported input frequencies. */ + .bus_frequency_configs_count = 12, + .bus_frequency_configs = { + 9600 * KHz, + 4800 * KHz, + 2400 * KHz, + 1200 * KHz, + 12000 * KHz, + 6000 * KHz, + 3000 * KHz, + 1500 * KHz, + 12288 * KHz, + 6144 * KHz, + 3072 * KHz, + 1536 * KHz + }, + /* Support 16 KHz to 192 KHz sampling frequency */ + .sampling_frequency_configs_count = 9, + .sampling_frequency_configs = { + 16 * KHz, + 22.05 * KHz, + 24 * KHz, + 32 * KHz, + 44.1 * KHz, + 48 * KHz, + 88.2 * KHz, + 96 * KHz, + 192 * KHz + }, + .prepare_channel_behavior = CHANNEL_PREPARE_ANY_FREQUENCY +}; + +static struct soundwire_dpn alc711_dp = { + .port_wordlength_configs_count = 1, + .port_wordlength_configs = { 32 }, + .data_port_type = FULL_DATA_PORT, + .max_grouping_supported = BLOCK_GROUP_COUNT_1, + .simplified_channelprepare_sm = false, + .imp_def_dpn_interrupts_supported = 0, + .min_channel_number = 1, + .max_channel_number = 2, + .modes_supported = MODE_ISOCHRONOUS | MODE_TX_CONTROLLED | + MODE_RX_CONTROLLED | MODE_FULL_ASYNCHRONOUS, + .block_packing_mode = true, + .port_audio_mode_count = 1, + .port_audio_mode_list = { 0 } +}; + +static const struct soundwire_codec alc711_codec = { + .slave = &alc711_slave, + .audio_mode = { &alc711_audio_mode }, + .dpn = { + { + /* Data Input for Speaker Path */ + .port = 1, + .sink = &alc711_dp + }, + { + /* Data Output for DSP Path */ + .port = 2, + .source = &alc711_dp + } + } + +}; + +static void soundwire_alc711_fill_ssdt(const struct device *dev) +{ + struct drivers_soundwire_alc711_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_dp *dsd; + + if (!dev->enabled || !scope) + return; + + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + + /* Set codec address IDs. */ + alc711_address.link_id = dev->path.generic.id; + alc711_address.unique_id = dev->path.generic.subid; + + acpigen_write_ADR_soundwire_device(&alc711_address); + acpigen_write_name_string("_DDN", config->desc ? : dev->chip_ops->name); + acpigen_write_STA(acpi_device_status(dev)); + + dsd = acpi_dp_new_table("_DSD"); + soundwire_gen_codec(dsd, &alc711_codec, NULL); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static const char *soundwire_alc711_acpi_name(const struct device *dev) +{ + struct drivers_soundwire_alc711_config *config = dev->chip_info; + static char name[5]; + + if (config->name) + return config->name; + snprintf(name, sizeof(name), "SW%1X%1X", dev->path.generic.id, dev->path.generic.subid); + return name; +} + +static struct device_operations soundwire_alc711_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = soundwire_alc711_acpi_name, + .acpi_fill_ssdt = soundwire_alc711_fill_ssdt, +}; + +static void soundwire_alc711_enable(struct device *dev) +{ + dev->ops = &soundwire_alc711_ops; +} + +struct chip_operations drivers_soundwire_alc711_ops = { + CHIP_NAME("Realtek ALC711 SoundWire Codec") + .enable_dev = soundwire_alc711_enable +}; diff --git a/src/drivers/soundwire/alc711/chip.h b/src/drivers/soundwire/alc711/chip.h new file mode 100644 index 0000000000..6d317fddfe --- /dev/null +++ b/src/drivers/soundwire/alc711/chip.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_SOUNDWIRE_ALC711_CHIP_H__ +#define __DRIVERS_SOUNDWIRE_ALC711_CHIP_H__ + +struct drivers_soundwire_alc711_config { + const char *name; + const char *desc; +}; + +#endif /* __DRIVERS_SOUNDWIRE_ALC711_CHIP_H__ */ diff --git a/src/drivers/wifi/generic/Makefile.inc b/src/drivers/wifi/generic/Makefile.inc index 407041afce..c17844993d 100644 --- a/src/drivers/wifi/generic/Makefile.inc +++ b/src/drivers/wifi/generic/Makefile.inc @@ -1,5 +1,12 @@ -ramstage-$(CONFIG_DRIVERS_WIFI_GENERIC) += generic.c + +ifeq ($(CONFIG_DRIVERS_WIFI_GENERIC),y) + +ramstage-y += generic.c +ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c cbfs-files-$(CONFIG_WIFI_SAR_CBFS) += wifi_sar_defaults.hex wifi_sar_defaults.hex-file := $(call strip_quotes,$(CONFIG_WIFI_SAR_CBFS_FILEPATH)) wifi_sar_defaults.hex-type := raw + +endif diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c new file mode 100644 index 0000000000..ac2c5eb5ba --- /dev/null +++ b/src/drivers/wifi/generic/acpi.c @@ -0,0 +1,258 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +#include "chip.h" +#include "wifi_private.h" + +/* WRDS Spec Revision */ +#define WRDS_REVISION 0x0 + +/* EWRD Spec Revision */ +#define EWRD_REVISION 0x0 + +/* WRDS Domain type */ +#define WRDS_DOMAIN_TYPE_WIFI 0x7 + +/* EWRD Domain type */ +#define EWRD_DOMAIN_TYPE_WIFI 0x7 + +/* WGDS Domain type */ +#define WGDS_DOMAIN_TYPE_WIFI 0x7 + +/* + * WIFI ACPI NAME = "WF" + hex value of last 8 bits of dev_path_encode + '\0' + * The above representation returns unique and consistent name every time + * generate_wifi_acpi_name is invoked. The last 8 bits of dev_path_encode is + * chosen since it contains the bus address of the device. + */ +#define WIFI_ACPI_NAME_MAX_LEN 5 + +__weak int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) +{ + return -1; +} + +static void emit_sar_acpi_structures(const struct device *dev) +{ + int i, j, package_size; + struct wifi_sar_limits sar_limits; + struct wifi_sar_delta_table *wgds; + + /* CBFS SAR and SAR ACPI tables are currently used only by Intel WiFi devices. */ + if (dev->vendor != PCI_VENDOR_ID_INTEL) + return; + + /* Retrieve the sar limits data */ + if (get_wifi_sar_limits(&sar_limits) < 0) { + printk(BIOS_ERR, "Error: failed from getting SAR limits!\n"); + return; + } + + /* + * Name ("WRDS", Package () { + * Revision, + * Package () { + * Domain Type, // 0x7:WiFi + * WiFi SAR BIOS, // BIOS SAR Enable/disable + * SAR Table Set // Set#1 of SAR Table (10 bytes) + * } + * }) + */ + acpigen_write_name("WRDS"); + acpigen_write_package(2); + acpigen_write_dword(WRDS_REVISION); + /* Emit 'Domain Type' + 'WiFi SAR BIOS' + 10 bytes for Set#1 */ + package_size = 1 + 1 + BYTES_PER_SAR_LIMIT; + acpigen_write_package(package_size); + acpigen_write_dword(WRDS_DOMAIN_TYPE_WIFI); + acpigen_write_dword(CONFIG(SAR_ENABLE)); + for (i = 0; i < BYTES_PER_SAR_LIMIT; i++) + acpigen_write_byte(sar_limits.sar_limit[0][i]); + acpigen_pop_len(); + acpigen_pop_len(); + + /* + * Name ("EWRD", Package () { + * Revision, + * Package () { + * Domain Type, // 0x7:WiFi + * Dynamic SAR Enable, // Dynamic SAR Enable/disable + * Extended SAR sets, // Number of optional SAR table sets + * SAR Table Set, // Set#2 of SAR Table (10 bytes) + * SAR Table Set, // Set#3 of SAR Table (10 bytes) + * SAR Table Set // Set#4 of SAR Table (10 bytes) + * } + * }) + */ + acpigen_write_name("EWRD"); + acpigen_write_package(2); + acpigen_write_dword(EWRD_REVISION); + /* + * Emit 'Domain Type' + "Dynamic SAR Enable' + 'Extended SAR sets' + * + number of bytes for Set#2 & 3 & 4 + */ + package_size = 1 + 1 + 1 + (NUM_SAR_LIMITS - 1) * BYTES_PER_SAR_LIMIT; + acpigen_write_package(package_size); + acpigen_write_dword(EWRD_DOMAIN_TYPE_WIFI); + acpigen_write_dword(CONFIG(DSAR_ENABLE)); + acpigen_write_dword(CONFIG_DSAR_SET_NUM); + for (i = 1; i < NUM_SAR_LIMITS; i++) + for (j = 0; j < BYTES_PER_SAR_LIMIT; j++) + acpigen_write_byte(sar_limits.sar_limit[i][j]); + acpigen_pop_len(); + acpigen_pop_len(); + + if (!CONFIG(GEO_SAR_ENABLE)) + return; + + /* + * Name ("WGDS", Package() { + * Revision, + * Package() { + * DomainType, // 0x7:WiFi + * WgdsWiFiSarDeltaGroup1PowerMax1, // Group 1 FCC 2400 Max + * WgdsWiFiSarDeltaGroup1PowerChainA1, // Group 1 FCC 2400 A Offset + * WgdsWiFiSarDeltaGroup1PowerChainB1, // Group 1 FCC 2400 B Offset + * WgdsWiFiSarDeltaGroup1PowerMax2, // Group 1 FCC 5200 Max + * WgdsWiFiSarDeltaGroup1PowerChainA2, // Group 1 FCC 5200 A Offset + * WgdsWiFiSarDeltaGroup1PowerChainB2, // Group 1 FCC 5200 B Offset + * WgdsWiFiSarDeltaGroup2PowerMax1, // Group 2 EC Jap 2400 Max + * WgdsWiFiSarDeltaGroup2PowerChainA1, // Group 2 EC Jap 2400 A Offset + * WgdsWiFiSarDeltaGroup2PowerChainB1, // Group 2 EC Jap 2400 B Offset + * WgdsWiFiSarDeltaGroup2PowerMax2, // Group 2 EC Jap 5200 Max + * WgdsWiFiSarDeltaGroup2PowerChainA2, // Group 2 EC Jap 5200 A Offset + * WgdsWiFiSarDeltaGroup2PowerChainB2, // Group 2 EC Jap 5200 B Offset + * WgdsWiFiSarDeltaGroup3PowerMax1, // Group 3 ROW 2400 Max + * WgdsWiFiSarDeltaGroup3PowerChainA1, // Group 3 ROW 2400 A Offset + * WgdsWiFiSarDeltaGroup3PowerChainB1, // Group 3 ROW 2400 B Offset + * WgdsWiFiSarDeltaGroup3PowerMax2, // Group 3 ROW 5200 Max + * WgdsWiFiSarDeltaGroup3PowerChainA2, // Group 3 ROW 5200 A Offset + * WgdsWiFiSarDeltaGroup3PowerChainB2, // Group 3 ROW 5200 B Offset + * } + * }) + */ + + wgds = &sar_limits.wgds; + acpigen_write_name("WGDS"); + acpigen_write_package(2); + acpigen_write_dword(wgds->version); + /* Emit 'Domain Type' + + * Group specific delta of power (6 bytes * NUM_WGDS_SAR_GROUPS) + */ + package_size = sizeof(sar_limits.wgds.group) + 1; + acpigen_write_package(package_size); + acpigen_write_dword(WGDS_DOMAIN_TYPE_WIFI); + for (i = 0; i < SAR_NUM_WGDS_GROUPS; i++) { + acpigen_write_byte(wgds->group[i].power_max_2400mhz); + acpigen_write_byte(wgds->group[i].power_chain_a_2400mhz); + acpigen_write_byte(wgds->group[i].power_chain_b_2400mhz); + acpigen_write_byte(wgds->group[i].power_max_5200mhz); + acpigen_write_byte(wgds->group[i].power_chain_a_5200mhz); + acpigen_write_byte(wgds->group[i].power_chain_b_5200mhz); + } + + acpigen_pop_len(); + acpigen_pop_len(); +} + +static void wifi_ssdt_write_device(const struct device *dev, const char *path) +{ + /* Device */ + acpigen_write_device(path); + acpi_device_write_uid(dev); + + if (dev->chip_ops) + acpigen_write_name_string("_DDN", dev->chip_ops->name); + + /* Address */ + acpigen_write_ADR_pci_device(dev); + + acpigen_pop_len(); /* Device */ +} + +static void wifi_ssdt_write_properties(const struct device *dev, const char *scope) +{ + const struct drivers_wifi_generic_config *config = dev->chip_info; + + /* Scope */ + acpigen_write_scope(scope); + + /* Wake capabilities */ + if (config) + acpigen_write_PRW(config->wake, ACPI_S3); + + /* Fill regulatory domain structure */ + if (CONFIG(HAVE_REGULATORY_DOMAIN)) { + /* + * Name ("WRDD", Package () { + * WRDD_REVISION, // Revision + * Package () { + * WRDD_DOMAIN_TYPE_WIFI, // Domain Type, 7:WiFi + * wifi_regulatory_domain() // Country Identifier + * } + * }) + */ + acpigen_write_name("WRDD"); + acpigen_write_package(2); + acpigen_write_integer(WRDD_REVISION); + acpigen_write_package(2); + acpigen_write_dword(WRDD_DOMAIN_TYPE_WIFI); + acpigen_write_dword(wifi_regulatory_domain()); + acpigen_pop_len(); + acpigen_pop_len(); + } + + /* Fill Wifi sar related ACPI structures */ + if (CONFIG(USE_SAR)) + emit_sar_acpi_structures(dev); + + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s %s\n", scope, dev->chip_ops ? dev->chip_ops->name : "", + dev_path(dev)); +} + +void wifi_pcie_fill_ssdt(const struct device *dev) +{ + const char *path; + + if (!is_dev_enabled(dev)) + return; + + path = acpi_device_path(dev); + if (!path) + return; + + wifi_ssdt_write_device(dev, path); + wifi_ssdt_write_properties(dev, path); +} + +const char *wifi_pcie_acpi_name(const struct device *dev) +{ + static char wifi_acpi_name[WIFI_ACPI_NAME_MAX_LEN]; + + /* ACPI 6.3, ASL 20.2.2: (Name Objects Encoding). */ + snprintf(wifi_acpi_name, sizeof(wifi_acpi_name), "WF%02X", + (dev_path_encode(dev) & 0xff)); + return wifi_acpi_name; +} + +void wifi_cnvi_fill_ssdt(const struct device *dev) +{ + const char *path; + + if (!is_dev_enabled(dev)) + return; + + path = acpi_device_path(dev->bus->dev); + if (!path) + return; + + wifi_ssdt_write_properties(dev, path); +} diff --git a/src/drivers/wifi/generic/generic.c b/src/drivers/wifi/generic/generic.c index e8184d8c13..31c681619b 100644 --- a/src/drivers/wifi/generic/generic.c +++ b/src/drivers/wifi/generic/generic.c @@ -1,245 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include -#include #include #include #include #include #include #include -#include -#include -#include -#include #include "chip.h" - -/* WRDS Spec Revision */ -#define WRDS_REVISION 0x0 - -/* EWRD Spec Revision */ -#define EWRD_REVISION 0x0 - -/* WRDS Domain type */ -#define WRDS_DOMAIN_TYPE_WIFI 0x7 - -/* EWRD Domain type */ -#define EWRD_DOMAIN_TYPE_WIFI 0x7 - -/* WGDS Domain type */ -#define WGDS_DOMAIN_TYPE_WIFI 0x7 - -/* - * WIFI ACPI NAME = "WF" + hex value of last 8 bits of dev_path_encode + '\0' - * The above representation returns unique and consistent name every time - * generate_wifi_acpi_name is invoked. The last 8 bits of dev_path_encode is - * chosen since it contains the bus address of the device. - */ -#define WIFI_ACPI_NAME_MAX_LEN 5 - -#if CONFIG(HAVE_ACPI_TABLES) -__weak -int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) -{ - return -1; -} - -static void emit_sar_acpi_structures(const struct device *dev) -{ - int i, j, package_size; - struct wifi_sar_limits sar_limits; - struct wifi_sar_delta_table *wgds; - - /* CBFS SAR and SAR ACPI tables are currently used only by Intel WiFi devices. */ - if (dev->vendor != PCI_VENDOR_ID_INTEL) - return; - - /* Retrieve the sar limits data */ - if (get_wifi_sar_limits(&sar_limits) < 0) { - printk(BIOS_ERR, "Error: failed from getting SAR limits!\n"); - return; - } - - /* - * Name ("WRDS", Package () { - * Revision, - * Package () { - * Domain Type, // 0x7:WiFi - * WiFi SAR BIOS, // BIOS SAR Enable/disable - * SAR Table Set // Set#1 of SAR Table (10 bytes) - * } - * }) - */ - acpigen_write_name("WRDS"); - acpigen_write_package(2); - acpigen_write_dword(WRDS_REVISION); - /* Emit 'Domain Type' + 'WiFi SAR BIOS' + 10 bytes for Set#1 */ - package_size = 1 + 1 + BYTES_PER_SAR_LIMIT; - acpigen_write_package(package_size); - acpigen_write_dword(WRDS_DOMAIN_TYPE_WIFI); - acpigen_write_dword(CONFIG(SAR_ENABLE)); - for (i = 0; i < BYTES_PER_SAR_LIMIT; i++) - acpigen_write_byte(sar_limits.sar_limit[0][i]); - acpigen_pop_len(); - acpigen_pop_len(); - - /* - * Name ("EWRD", Package () { - * Revision, - * Package () { - * Domain Type, // 0x7:WiFi - * Dynamic SAR Enable, // Dynamic SAR Enable/disable - * Extended SAR sets, // Number of optional SAR table sets - * SAR Table Set, // Set#2 of SAR Table (10 bytes) - * SAR Table Set, // Set#3 of SAR Table (10 bytes) - * SAR Table Set // Set#4 of SAR Table (10 bytes) - * } - * }) - */ - acpigen_write_name("EWRD"); - acpigen_write_package(2); - acpigen_write_dword(EWRD_REVISION); - /* - * Emit 'Domain Type' + "Dynamic SAR Enable' + 'Extended SAR sets' - * + number of bytes for Set#2 & 3 & 4 - */ - package_size = 1 + 1 + 1 + (NUM_SAR_LIMITS - 1) * BYTES_PER_SAR_LIMIT; - acpigen_write_package(package_size); - acpigen_write_dword(EWRD_DOMAIN_TYPE_WIFI); - acpigen_write_dword(CONFIG(DSAR_ENABLE)); - acpigen_write_dword(CONFIG_DSAR_SET_NUM); - for (i = 1; i < NUM_SAR_LIMITS; i++) - for (j = 0; j < BYTES_PER_SAR_LIMIT; j++) - acpigen_write_byte(sar_limits.sar_limit[i][j]); - acpigen_pop_len(); - acpigen_pop_len(); - - if (!CONFIG(GEO_SAR_ENABLE)) - return; - - /* - * Name ("WGDS", Package() { - * Revision, - * Package() { - * DomainType, // 0x7:WiFi - * WgdsWiFiSarDeltaGroup1PowerMax1, // Group 1 FCC 2400 Max - * WgdsWiFiSarDeltaGroup1PowerChainA1, // Group 1 FCC 2400 A Offset - * WgdsWiFiSarDeltaGroup1PowerChainB1, // Group 1 FCC 2400 B Offset - * WgdsWiFiSarDeltaGroup1PowerMax2, // Group 1 FCC 5200 Max - * WgdsWiFiSarDeltaGroup1PowerChainA2, // Group 1 FCC 5200 A Offset - * WgdsWiFiSarDeltaGroup1PowerChainB2, // Group 1 FCC 5200 B Offset - * WgdsWiFiSarDeltaGroup2PowerMax1, // Group 2 EC Jap 2400 Max - * WgdsWiFiSarDeltaGroup2PowerChainA1, // Group 2 EC Jap 2400 A Offset - * WgdsWiFiSarDeltaGroup2PowerChainB1, // Group 2 EC Jap 2400 B Offset - * WgdsWiFiSarDeltaGroup2PowerMax2, // Group 2 EC Jap 5200 Max - * WgdsWiFiSarDeltaGroup2PowerChainA2, // Group 2 EC Jap 5200 A Offset - * WgdsWiFiSarDeltaGroup2PowerChainB2, // Group 2 EC Jap 5200 B Offset - * WgdsWiFiSarDeltaGroup3PowerMax1, // Group 3 ROW 2400 Max - * WgdsWiFiSarDeltaGroup3PowerChainA1, // Group 3 ROW 2400 A Offset - * WgdsWiFiSarDeltaGroup3PowerChainB1, // Group 3 ROW 2400 B Offset - * WgdsWiFiSarDeltaGroup3PowerMax2, // Group 3 ROW 5200 Max - * WgdsWiFiSarDeltaGroup3PowerChainA2, // Group 3 ROW 5200 A Offset - * WgdsWiFiSarDeltaGroup3PowerChainB2, // Group 3 ROW 5200 B Offset - * } - * }) - */ - - wgds = &sar_limits.wgds; - acpigen_write_name("WGDS"); - acpigen_write_package(2); - acpigen_write_dword(wgds->version); - /* Emit 'Domain Type' + - * Group specific delta of power (6 bytes * NUM_WGDS_SAR_GROUPS) - */ - package_size = sizeof(sar_limits.wgds.group) + 1; - acpigen_write_package(package_size); - acpigen_write_dword(WGDS_DOMAIN_TYPE_WIFI); - for (i = 0; i < SAR_NUM_WGDS_GROUPS; i++) { - acpigen_write_byte(wgds->group[i].power_max_2400mhz); - acpigen_write_byte(wgds->group[i].power_chain_a_2400mhz); - acpigen_write_byte(wgds->group[i].power_chain_b_2400mhz); - acpigen_write_byte(wgds->group[i].power_max_5200mhz); - acpigen_write_byte(wgds->group[i].power_chain_a_5200mhz); - acpigen_write_byte(wgds->group[i].power_chain_b_5200mhz); - } - - acpigen_pop_len(); - acpigen_pop_len(); -} - -static void wifi_generic_fill_ssdt(const struct device *dev) -{ - const char *path; - u32 address; - const struct drivers_wifi_generic_config *config = dev->chip_info; - - if (!dev->enabled) - return; - - path = acpi_device_path(dev->bus->dev); - if (!path) - return; - - /* Device */ - acpigen_write_scope(path); - acpigen_write_device(acpi_device_name(dev)); - acpi_device_write_uid(dev); - - if (dev->chip_ops) - acpigen_write_name_string("_DDN", dev->chip_ops->name); - - /* Address */ - address = PCI_SLOT(dev->path.pci.devfn) & 0xffff; - address <<= 16; - address |= PCI_FUNC(dev->path.pci.devfn) & 0xffff; - acpigen_write_name_dword("_ADR", address); - - /* Wake capabilities */ - if (config) - acpigen_write_PRW(config->wake, ACPI_S3); - - /* Fill regulatory domain structure */ - if (CONFIG(HAVE_REGULATORY_DOMAIN)) { - /* - * Name ("WRDD", Package () { - * WRDD_REVISION, // Revision - * Package () { - * WRDD_DOMAIN_TYPE_WIFI, // Domain Type, 7:WiFi - * wifi_regulatory_domain() // Country Identifier - * } - * }) - */ - acpigen_write_name("WRDD"); - acpigen_write_package(2); - acpigen_write_integer(WRDD_REVISION); - acpigen_write_package(2); - acpigen_write_dword(WRDD_DOMAIN_TYPE_WIFI); - acpigen_write_dword(wifi_regulatory_domain()); - acpigen_pop_len(); - acpigen_pop_len(); - } - - /* Fill Wifi sar related ACPI structures */ - if (CONFIG(USE_SAR)) - emit_sar_acpi_structures(dev); - - acpigen_pop_len(); /* Device */ - acpigen_pop_len(); /* Scope */ - - printk(BIOS_INFO, "%s.%s: %s %s\n", path, acpi_device_name(dev), - dev->chip_ops ? dev->chip_ops->name : "", dev_path(dev)); -} - -static const char *wifi_generic_acpi_name(const struct device *dev) -{ - static char wifi_acpi_name[WIFI_ACPI_NAME_MAX_LEN]; - - /* ACPI 6.3, ASL 20.2.2: (Name Objects Encoding). */ - snprintf(wifi_acpi_name, sizeof(wifi_acpi_name), "WF%02X", - (dev_path_encode(dev) & 0xff)); - return wifi_acpi_name; -} -#endif +#include "wifi_private.h" static void wifi_pci_dev_init(struct device *dev) { @@ -247,54 +15,29 @@ static void wifi_pci_dev_init(struct device *dev) elog_add_event_wake(ELOG_WAKE_SOURCE_PME_WIFI, 0); } -#if CONFIG(GENERATE_SMBIOS_TABLES) -static int smbios_write_intel_wifi(struct device *dev, int *handle, unsigned long *current) -{ - struct smbios_type_intel_wifi { - u8 type; - u8 length; - u16 handle; - u8 str; - u8 eos[2]; - } __packed; - - struct smbios_type_intel_wifi *t = (struct smbios_type_intel_wifi *)*current; - int len = sizeof(struct smbios_type_intel_wifi); - - memset(t, 0, sizeof(struct smbios_type_intel_wifi)); - t->type = 0x85; - t->length = len - 2; - t->handle = *handle; - /* Intel wifi driver expects this string to be in the table 0x85. */ - t->str = smbios_add_string(t->eos, "KHOIHGIUCCHHII"); - - len = t->length + smbios_string_table_len(t->eos); - *current += len; - *handle += 1; - return len; -} - -static int smbios_write_wifi(struct device *dev, int *handle, unsigned long *current) -{ - if (dev->vendor == PCI_VENDOR_ID_INTEL) - return smbios_write_intel_wifi(dev, handle, current); - - return 0; -} -#endif - -struct device_operations wifi_generic_ops = { +struct device_operations wifi_pcie_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = wifi_pci_dev_init, .ops_pci = &pci_dev_ops_pci, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = wifi_generic_acpi_name, - .acpi_fill_ssdt = wifi_generic_fill_ssdt, + .acpi_name = wifi_pcie_acpi_name, + .acpi_fill_ssdt = wifi_pcie_fill_ssdt, #endif #if CONFIG(GENERATE_SMBIOS_TABLES) - .get_smbios_data = smbios_write_wifi, + .get_smbios_data = smbios_write_wifi_pcie, +#endif +}; + +struct device_operations wifi_cnvi_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt = wifi_cnvi_fill_ssdt, +#endif +#if CONFIG(GENERATE_SMBIOS_TABLES) + .get_smbios_data = smbios_write_wifi_cnvi, #endif }; @@ -305,7 +48,10 @@ static void wifi_generic_enable(struct device *dev) if (!config) return; - dev->ops = &wifi_generic_ops; + if (dev->path.type == DEVICE_PATH_PCI) + dev->ops = &wifi_pcie_ops; + else + dev->ops = &wifi_cnvi_ops; } struct chip_operations drivers_wifi_generic_ops = { @@ -343,18 +89,8 @@ static const unsigned short intel_pci_device_ids[] = { PCI_DEVICE_ID_SFP_8260_SERIES_2_WIFI, /* Windstorm Peak */ PCI_DEVICE_ID_WSP_8275_SERIES_1_WIFI, - /* Jefferson Peak */ - PCI_DEVICE_ID_JP_9000_SERIES_1_WIFI, - PCI_DEVICE_ID_JP_9000_SERIES_2_WIFI, - PCI_DEVICE_ID_JP_9000_SERIES_3_WIFI, /* Thunder Peak 2 */ PCI_DEVICE_ID_TP_9260_SERIES_WIFI, - /* Harrison Peak */ - PCI_DEVICE_ID_HrP_9560_SERIES_1_WIFI, - PCI_DEVICE_ID_HrP_9560_SERIES_2_WIFI, - PCI_DEVICE_ID_HrP_9560_SERIES_3_WIFI, - PCI_DEVICE_ID_HrP_9560_SERIES_4_WIFI, - PCI_DEVICE_ID_HrP_6SERIES_WIFI, /* Cyclone Peak */ PCI_DEVICE_ID_CyP_6SERIES_WIFI, /* Typhoon Peak */ @@ -372,7 +108,7 @@ static const unsigned short intel_pci_device_ids[] = { * `wifi_generic_ops`. */ static const struct pci_driver intel_wifi_pci_driver __pci_driver = { - .ops = &wifi_generic_ops, + .ops = &wifi_pcie_ops, .vendor = PCI_VENDOR_ID_INTEL, .devices = intel_pci_device_ids, }; diff --git a/src/drivers/wifi/generic/smbios.c b/src/drivers/wifi/generic/smbios.c new file mode 100644 index 0000000000..a1a8e4f204 --- /dev/null +++ b/src/drivers/wifi/generic/smbios.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#include "wifi_private.h" + +static int smbios_write_intel_wifi(struct device *dev, int *handle, unsigned long *current) +{ + struct smbios_type_intel_wifi { + u8 type; + u8 length; + u16 handle; + u8 str; + u8 eos[2]; + } __packed; + + struct smbios_type_intel_wifi *t = (struct smbios_type_intel_wifi *)*current; + int len = sizeof(struct smbios_type_intel_wifi); + + memset(t, 0, sizeof(struct smbios_type_intel_wifi)); + t->type = 0x85; + t->length = len - 2; + t->handle = *handle; + /* Intel wifi driver expects this string to be in the table 0x85. */ + t->str = smbios_add_string(t->eos, "KHOIHGIUCCHHII"); + + len = t->length + smbios_string_table_len(t->eos); + *current += len; + *handle += 1; + return len; +} + +int smbios_write_wifi_pcie(struct device *dev, int *handle, unsigned long *current) +{ + if (dev->vendor == PCI_VENDOR_ID_INTEL) + return smbios_write_intel_wifi(dev, handle, current); + + return 0; +} + +int smbios_write_wifi_cnvi(struct device *dev, int *handle, unsigned long *current) +{ + return smbios_write_wifi_pcie(dev->bus->dev, handle, current); +} diff --git a/src/drivers/wifi/generic/wifi_private.h b/src/drivers/wifi/generic/wifi_private.h new file mode 100644 index 0000000000..4a2045db8d --- /dev/null +++ b/src/drivers/wifi/generic/wifi_private.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _WIFI_GENERIC_PRIVATE_H_ +#define _WIFI_GENERIC_PRIVATE_H_ + +int smbios_write_wifi_pcie(struct device *dev, int *handle, unsigned long *current); +int smbios_write_wifi_cnvi(struct device *dev, int *handle, unsigned long *current); + +const char *wifi_pcie_acpi_name(const struct device *dev); +void wifi_pcie_fill_ssdt(const struct device *dev); + +void wifi_cnvi_fill_ssdt(const struct device *dev); + +#endif diff --git a/src/ec/google/chromeec/chip.h b/src/ec/google/chromeec/chip.h index 9bfb1c4fd1..3915cf92e7 100644 --- a/src/ec/google/chromeec/chip.h +++ b/src/ec/google/chromeec/chip.h @@ -3,7 +3,14 @@ #ifndef EC_GOOGLE_CHROMEEC_CHIP_H #define EC_GOOGLE_CHROMEEC_CHIP_H +#include +#include + +#define MAX_TYPEC_PORTS 4 + struct ec_google_chromeec_config { + /* Pointer to PMC Mux connector for each Type-C port */ + DEVTREE_CONST struct device *mux_conn[MAX_TYPEC_PORTS]; }; #endif /* EC_GOOGLE_CHROMEEC_CHIP_H */ diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 39cf89512f..2ffccbc77c 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -841,9 +841,16 @@ int google_chromeec_cbi_get_sku_id(uint32_t *id) return cbi_get_uint32(id, CBI_TAG_SKU_ID); } -int google_chromeec_cbi_get_fw_config(uint32_t *fw_config) +int google_chromeec_cbi_get_fw_config(uint64_t *fw_config) { - return cbi_get_uint32(fw_config, CBI_TAG_FW_CONFIG); + uint32_t config; + + if (cbi_get_uint32(&config, CBI_TAG_FW_CONFIG)) + return -1; + + /* FIXME: Yet to determine source of other 32 bits... */ + *fw_config = (uint64_t)config; + return 0; } int google_chromeec_cbi_get_oem_id(uint32_t *id) diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index c2ceff831f..bed8594a8b 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -83,7 +83,7 @@ int google_chromeec_reboot(int dev_idx, enum ec_reboot_cmd type, uint8_t flags); */ int google_chromeec_cbi_get_oem_id(uint32_t *id); int google_chromeec_cbi_get_sku_id(uint32_t *id); -int google_chromeec_cbi_get_fw_config(uint32_t *fw_config); +int google_chromeec_cbi_get_fw_config(uint64_t *fw_config); int google_chromeec_cbi_get_dram_part_num(char *buf, size_t bufsize); int google_chromeec_cbi_get_oem_name(char *buf, size_t bufsize); /* version may be stored in CBI as a smaller integer width, but the EC code diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index b7683167af..344f5f42e5 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -16,14 +16,6 @@ #define GOOGLE_CHROMEEC_USBC_DEVICE_HID "GOOG0014" #define GOOGLE_CHROMEEC_USBC_DEVICE_NAME "USBC" -/* Avoid adding a false dependency on an SoC or intel/common */ -extern const struct device *soc_get_pmc_mux_device(int port_number); - -__weak const struct device *soc_get_pmc_mux_device(int port_number) -{ - return NULL; -} - const char *google_chromeec_acpi_name(const struct device *dev) { /* @@ -121,36 +113,18 @@ static const char *port_location_to_str(enum ec_pd_port_location port_location) static struct usb_pd_port_caps port_caps; static void add_port_location(struct acpi_dp *dsd, int port_number) { - acpi_dp_add_string(dsd, "port-location", - port_location_to_str(port_caps.port_location)); -} - -static int conn_id_to_match; - -/* A callback to match a port's connector for dev_find_matching_device_on_bus */ -static bool match_connector(DEVTREE_CONST struct device *dev) -{ - if (CONFIG(DRIVERS_INTEL_PMC)) { - extern struct chip_operations drivers_intel_pmc_mux_conn_ops; - - return (dev->chip_ops == &drivers_intel_pmc_mux_conn_ops && - dev->path.type == DEVICE_PATH_GENERIC && - dev->path.generic.id == conn_id_to_match); - } - - return false; + acpi_dp_add_string(dsd, "port-location", port_location_to_str(port_caps.port_location)); } static void fill_ssdt_typec_device(const struct device *dev) { + struct ec_google_chromeec_config *config = dev->chip_info; int rv; int i; unsigned int num_ports; struct device *usb2_port; struct device *usb3_port; struct device *usb4_port; - const struct device *mux; - const struct device *conn; if (google_chromeec_get_num_pd_ports(&num_ports)) return; @@ -166,32 +140,28 @@ static void fill_ssdt_typec_device(const struct device *dev) if (rv) continue; - /* Get the MUX device, and find the matching connector on its bus */ - conn = NULL; - mux = soc_get_pmc_mux_device(i); - if (mux) { - conn_id_to_match = i; - conn = dev_find_matching_device_on_bus(mux->link_list, match_connector); - } + if (!config->mux_conn[i]) + printk(BIOS_ERR, "ERROR: Mux connector info missing for Type-C port " + "#%d\n", i); usb2_port = NULL; usb3_port = NULL; usb4_port = NULL; get_usb_port_references(i, &usb2_port, &usb3_port, &usb4_port); - struct typec_connector_class_config config = { + struct typec_connector_class_config typec_config = { .power_role = port_caps.power_role_cap, .try_power_role = port_caps.try_power_role_cap, .data_role = port_caps.data_role_cap, .usb2_port = usb2_port, .usb3_port = usb3_port, .usb4_port = usb4_port, - .orientation_switch = conn, - .usb_role_switch = conn, - .mode_switch = conn, + .orientation_switch = config->mux_conn[i], + .usb_role_switch = config->mux_conn[i], + .mode_switch = config->mux_conn[i], }; - acpigen_write_typec_connector(&config, i, add_port_location); + acpigen_write_typec_connector(&typec_config, i, add_port_location); } acpigen_pop_len(); /* Device GOOGLE_CHROMEEC_USBC_DEVICE_NAME */ diff --git a/src/ec/hp/kbc1126/Kconfig b/src/ec/hp/kbc1126/Kconfig index fa2414adbc..cb4ddec7e4 100644 --- a/src/ec/hp/kbc1126/Kconfig +++ b/src/ec/hp/kbc1126/Kconfig @@ -5,6 +5,11 @@ config EC_HP_KBC1126 help Interface to SMSC KBC1126 embedded controller in HP laptops. +config EC_HP_KBC1126_GPE + hex + depends on EC_HP_KBC1126 + default 0x16 + config EC_HP_KBC1126_ECFW_IN_CBFS bool depends on EC_HP_KBC1126 diff --git a/src/ec/hp/kbc1126/acpi/ec.asl b/src/ec/hp/kbc1126/acpi/ec.asl index e5752a802d..81bdff969a 100644 --- a/src/ec/hp/kbc1126/acpi/ec.asl +++ b/src/ec/hp/kbc1126/acpi/ec.asl @@ -4,7 +4,7 @@ Device (EC0) { Name (_HID, EISAID("PNP0C09")) Name (_UID, 0) - Name (_GPE, 0x16) + Name (_GPE, CONFIG_EC_HP_KBC1126_GPE) Name (_CRS, ResourceTemplate () { diff --git a/src/ec/system76/ec/acpi/ec.asl b/src/ec/system76/ec/acpi/ec.asl index a43ad7be5b..b24137ca4f 100644 --- a/src/ec/system76/ec/acpi/ec.asl +++ b/src/ec/system76/ec/acpi/ec.asl @@ -35,7 +35,7 @@ Device (\_SB.PCI0.LPCB.EC0) Method (_REG, 2, Serialized) // _REG: Region Availability { Debug = Concatenate("EC: _REG", Concatenate(ToHexString(Arg0), Concatenate(" ", ToHexString(Arg1)))) - If (((Arg0 == 0x03) && (Arg1 == One))) { + If ((Arg0 == 0x03) && (Arg1 == One)) { // Enable hardware touchpad lock, airplane mode, and keyboard backlight keys ECOS = 1 diff --git a/src/ec/system76/ec/acpi/hid.asl b/src/ec/system76/ec/acpi/hid.asl index ce8fd3f28b..6610c2e1bc 100644 --- a/src/ec/system76/ec/acpi/hid.asl +++ b/src/ec/system76/ec/acpi/hid.asl @@ -30,13 +30,13 @@ Device (HIDD) Notify (HIDD, 0xC0) Local0 = Zero - While (((Local0 < 0xFA) && HBSY)) + While ((Local0 < 0xFA) && HBSY) { Sleep (0x04) Local0++ } - If ((HBSY == One)) + If (HBSY == One) { HBSY = Zero HIDX = Zero diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index d06d20c8e7..6360614c71 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -231,6 +231,10 @@ struct dsm_uuid { void *arg; }; +#define CPPC_VERSION_1 1 +#define CPPC_VERSION_2 2 +#define CPPC_VERSION_3 3 + /*version 1 has 15 fields, version 2 has 19, and version 3 has 21 */ enum cppc_fields { CPPC_HIGHEST_PERF, /* can be DWORD */ diff --git a/src/include/cbfs_glue.h b/src/include/cbfs_glue.h new file mode 100644 index 0000000000..ebfbc2e7ae --- /dev/null +++ b/src/include/cbfs_glue.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _CBFS_GLUE_H_ +#define _CBFS_GLUE_H_ + +#include +#include + +#define CBFS_ENABLE_HASHING 0 + +#define ERROR(...) printk(BIOS_ERR, "CBFS ERROR: " __VA_ARGS__) +#define LOG(...) printk(BIOS_ERR, "CBFS: " __VA_ARGS__) +#define DEBUG(...) do { \ + if (CONFIG(DEBUG_CBFS)) \ + printk(BIOS_SPEW, "CBFS DEBUG: " __VA_ARGS__); \ +} while (0) + +typedef const struct region_device *cbfs_dev_t; + +static inline ssize_t cbfs_dev_read(cbfs_dev_t dev, void *buffer, size_t offset, size_t size) +{ + return rdev_readat(dev, buffer, offset, size); +} + +static inline size_t cbfs_dev_size(cbfs_dev_t dev) +{ + return region_device_sz(dev); +} + +#endif /* _CBFS_GLUE_H_ */ diff --git a/src/include/console/debug.h b/src/include/console/debug.h new file mode 100644 index 0000000000..174c287c6a --- /dev/null +++ b/src/include/console/debug.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _CONSOLE_DEBUG_H_ +#define _CONSOLE_DEBUG_H_ + +#if CONFIG(DEBUG_FUNC) +#include + +#define FUNC_ENTER() \ + printk(BIOS_SPEW, "%s:%s:%d: ENTER\n", __FILE__, __func__, __LINE__) + +#define FUNC_EXIT() \ + printk(BIOS_SPEW, "%s:%s:%d: EXIT\n", __FILE__, __func__, __LINE__) + +#else /* FUNC_DEBUG */ + +#define FUNC_ENTER() +#define FUNC_EXIT() + +#endif /* FUNC_DEBUG */ + +#endif diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h index a2165f365a..da0f0bb68d 100644 --- a/src/include/cpu/intel/msr.h +++ b/src/include/cpu/intel/msr.h @@ -12,4 +12,6 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define TPR_UPDATES_DISABLE (1 << 10) +#define MSR_PLATFORM_INFO 0xce + #endif /* CPU_INTEL_MSR_H */ diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 5ab57554f2..f4291ab35b 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -73,7 +73,7 @@ static inline void lapic_write_atomic(unsigned long reg, uint32_t v) # define lapic_read_around(x) lapic_read(x) # define lapic_write_around(x, y) lapic_write_atomic((x), (y)) -void do_lapic_init(void); +void lapic_virtual_wire_mode_init(void); /* See if I need to initialize the local APIC */ static inline int need_lapic_init(void) @@ -84,7 +84,7 @@ static inline int need_lapic_init(void) static inline void setup_lapic(void) { if (need_lapic_init()) - do_lapic_init(); + lapic_virtual_wire_mode_init(); else disable_lapic(); } diff --git a/src/include/device/device.h b/src/include/device/device.h index 3a0795e526..8a481b2ca2 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -261,6 +261,38 @@ void show_one_resource(int debug_level, struct device *dev, struct resource *resource, const char *comment); void show_all_devs_resources(int debug_level, const char *msg); +/* Debug macros */ +#if CONFIG(DEBUG_RESOURCES) +#include +#define LOG_MEM_RESOURCE(type, dev, index, base_kb, size_kb) \ + printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \ + "end: 0x%llx, size_kb: 0x%llx\n", \ + __func__, __LINE__, type, dev_path(dev), index, (base_kb << 10), \ + (base_kb << 10) + (size_kb << 10) - 1, size_kb) + +#define LOG_IO_RESOURCE(type, dev, index, base, size) \ + printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \ + "end: 0x%llx, size: 0x%llx\n", \ + __func__, __LINE__, type, dev_path(dev), index, base, base + size - 1, size) +#else /* DEBUG_RESOURCES*/ +#define LOG_MEM_RESOURCE(type, dev, index, base_kb, size_kb) +#define LOG_IO_RESOURCE(type, dev, index, base, size) +#endif /* DEBUG_RESOURCES*/ + +#if CONFIG(DEBUG_FUNC) +#include +#define DEV_FUNC_ENTER(dev) \ + printk(BIOS_SPEW, "%s:%s:%d: ENTER (dev: %s)\n", \ + __FILE__, __func__, __LINE__, dev_path(dev)) + +#define DEV_FUNC_EXIT(dev) \ + printk(BIOS_SPEW, "%s:%s:%d: EXIT (dev: %s)\n", __FILE__, \ + __func__, __LINE__, dev_path(dev)) +#else /* DEBUG_FUNC */ +#define DEV_FUNC_ENTER(dev) +#define DEV_FUNC_EXIT(dev) +#endif /* DEBUG_FUNC */ + /* Rounding for boundaries. * Due to some chip bugs, go ahead and round IO to 16 */ diff --git a/src/include/device/mipi_ids.h b/src/include/device/mipi_ids.h index 86b5116005..951caaacaa 100644 --- a/src/include/device/mipi_ids.h +++ b/src/include/device/mipi_ids.h @@ -20,6 +20,7 @@ /* Contributing Members */ #define MIPI_MFG_ID_REALTEK 0x025d #define MIPI_DEV_ID_REALTEK_ALC5682 0x5682 +#define MIPI_DEV_ID_REALTEK_ALC711 0x0711 #define MIPI_MFG_ID_MAXIM 0x019f #define MIPI_DEV_ID_MAXIM_MAX98373 0x8373 diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 58f5904996..777f030355 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -144,7 +144,7 @@ void pci_dev_request_bus_master(pci_devfn_t dev) void pci_dev_request_bus_master(struct device *dev) #endif /* ENV_PCI_SIMPLE_DEVICE */ { - if (CONFIG(PCI_ALLOW_BUS_MASTER)) + if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE)) pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); } diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index d40d867ce2..36c5dc6d03 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3950,19 +3950,11 @@ #define PCI_DEVICE_ID_WP_7260_SERIES_2_WIFI 0x08b2 #define PCI_DEVICE_ID_SP_7265_SERIES_1_WIFI 0x095a #define PCI_DEVICE_ID_SP_7265_SERIES_2_WIFI 0x095b -#define PCI_DEVICE_ID_JP_9000_SERIES_1_WIFI 0x9df0 -#define PCI_DEVICE_ID_JP_9000_SERIES_2_WIFI 0x31dc -#define PCI_DEVICE_ID_JP_9000_SERIES_3_WIFI 0xa370 #define PCI_DEVICE_ID_SFP_8260_SERIES_1_WIFI 0x24f3 #define PCI_DEVICE_ID_SFP_8260_SERIES_2_WIFI 0x24f4 #define PCI_DEVICE_ID_WSP_8275_SERIES_1_WIFI 0x24fd #define PCI_DEVICE_ID_TP_9260_SERIES_WIFI 0x2526 -#define PCI_DEVICE_ID_HrP_9560_SERIES_1_WIFI 0x34f0 -#define PCI_DEVICE_ID_HrP_9560_SERIES_2_WIFI 0xa0f0 -#define PCI_DEVICE_ID_HrP_9560_SERIES_3_WIFI 0x02f0 -#define PCI_DEVICE_ID_HrP_9560_SERIES_4_WIFI 0x06f0 #define PCI_DEVICE_ID_CyP_6SERIES_WIFI 0x2723 -#define PCI_DEVICE_ID_HrP_6SERIES_WIFI 0x2720 #define PCI_DEVICE_ID_TyP_6SERIES_WIFI 0x2725 #define PCI_DEVICE_ID_GrP_6SERIES_1_WIFI 0x51f0 #define PCI_DEVICE_ID_GrP_6SERIES_2_WIFI 0x7af0 @@ -3977,6 +3969,26 @@ #define PCI_DEVICE_ID_INTEL_JSL_DTT 0x4E03 #define PCI_DEVICE_ID_INTEL_ADL_DTT 0x461d +/* Intel CNVi WiFi/BT device IDs */ +#define PCI_DEVICE_ID_INTEL_CML_LP_CNVI_WIFI 0x02f0 +#define PCI_DEVICE_ID_INTEL_CML_H_CNVI_WIFI 0x06f0 +#define PCI_DEVICE_ID_INTEL_CNL_LP_CNVI_WIFI 0x9df0 +#define PCI_DEVICE_ID_INTEL_CNL_H_CNVI_WIFI 0xa370 +#define PCI_DEVICE_ID_INTEL_GLK_CNVI_WIFI 0x31dc +#define PCI_DEVICE_ID_INTEL_ICL_CNVI_WIFI 0x34f0 +#define PCI_DEVICE_ID_INTEL_JSL_CNVI_WIFI_0 0x4df0 +#define PCI_DEVICE_ID_INTEL_JSL_CNVI_WIFI_1 0x4df1 +#define PCI_DEVICE_ID_INTEL_JSL_CNVI_WIFI_2 0x4df2 +#define PCI_DEVICE_ID_INTEL_JSL_CNVI_WIFI_3 0x4df3 +#define PCI_DEVICE_ID_INTEL_TGL_CNVI_WIFI_0 0xa0f0 +#define PCI_DEVICE_ID_INTEL_TGL_CNVI_WIFI_1 0xa0f1 +#define PCI_DEVICE_ID_INTEL_TGL_CNVI_WIFI_2 0xa0f2 +#define PCI_DEVICE_ID_INTEL_TGL_CNVI_WIFI_3 0xa0f3 +#define PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_0 0xa0f5 +#define PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_1 0xa0f6 +#define PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_2 0xa0f7 +#define PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_3 0xa0f8 + #define PCI_VENDOR_ID_COMPUTONE 0x8e0e #define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291 #define PCI_DEVICE_ID_COMPUTONE_PG 0x0302 diff --git a/src/include/fw_config.h b/src/include/fw_config.h index 81980b93ae..3c8772598e 100644 --- a/src/include/fw_config.h +++ b/src/include/fw_config.h @@ -8,6 +8,8 @@ #include #include +#define UNDEFINED_FW_CONFIG ~((uint64_t)0) + /** * struct fw_config - Firmware configuration field and option. * @field_name: Name of the field that this option belongs to. @@ -18,8 +20,8 @@ struct fw_config { const char *field_name; const char *option_name; - uint32_t mask; - uint32_t value; + uint64_t mask; + uint64_t value; }; /* Generate a pointer to a compound literal of the fw_config structure. */ @@ -30,6 +32,13 @@ struct fw_config { .value = FW_CONFIG_FIELD_##__field##_OPTION_##__option##_VALUE \ }) +/** + * fw_config_get() - Provide firmware configuration value. + * + * Return 64bit firmware configuration value determined for the system. + */ +uint64_t fw_config_get(void); + #if CONFIG(FW_CONFIG) /** @@ -53,7 +62,7 @@ void fw_config_for_each_found(void (*cb)(const struct fw_config *config, void *a * * Return pointer to cached `struct fw_config` if successfully probed, otherwise NULL. */ -const struct fw_config *fw_config_get_found(uint32_t field_mask); +const struct fw_config *fw_config_get_found(uint64_t field_mask); #else diff --git a/src/include/list.h b/src/include/list.h index 394487831c..6f0b54d818 100644 --- a/src/include/list.h +++ b/src/include/list.h @@ -16,10 +16,10 @@ void list_insert_after(struct list_node *node, struct list_node *after); // Insert list_node node before list_node before in a doubly linked list. void list_insert_before(struct list_node *node, struct list_node *before); -#define list_for_each(ptr, head, member) \ - for ((ptr) = container_of((head).next, typeof(*(ptr)), member); \ - &((ptr)->member); \ - (ptr) = container_of((ptr)->member.next, \ +#define list_for_each(ptr, head, member) \ + for ((ptr) = container_of((head).next, typeof(*(ptr)), member); \ + (uintptr_t)ptr + (uintptr_t)offsetof(typeof(*(ptr)), member); \ + (ptr) = container_of((ptr)->member.next, \ typeof(*(ptr)), member)) #endif /* __LIST_H__ */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 35193d0ecf..447d91f1be 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -15,14 +16,6 @@ #include #include -#define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) -#define LOG(x...) printk(BIOS_INFO, "CBFS: " x) -#if CONFIG(DEBUG_CBFS) -#define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x) -#else -#define DEBUG(x...) -#endif - int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) { struct region_device rdev; @@ -30,31 +23,35 @@ int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) if (cbfs_boot_region_device(&rdev)) return -1; - int ret = cbfs_locate(fh, &rdev, name, type); + size_t data_offset; + cb_err_t err = cbfs_lookup(&rdev, name, &fh->mdata, &data_offset, NULL); - if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && ret) { - - /* - * When VBOOT_ENABLE_CBFS_FALLBACK is enabled and a file is not available in the - * active RW region, the RO (COREBOOT) region will be used to locate the file. - * - * This functionality makes it possible to avoid duplicate files in the RO - * and RW partitions while maintaining updateability. - * - * Files can be added to the RO_REGION_ONLY config option to use this feature. - */ - printk(BIOS_DEBUG, "Fall back to RO region for %s\n", name); + if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && err == CB_CBFS_NOT_FOUND) { + printk(BIOS_INFO, "CBFS: Fall back to RO region for %s\n", + name); if (fmap_locate_area_as_rdev("COREBOOT", &rdev)) - ERROR("RO region not found\n"); - else - ret = cbfs_locate(fh, &rdev, name, type); + return -1; + err = cbfs_lookup(&rdev, name, &fh->mdata, &data_offset, NULL); + } + if (err) + return -1; + + size_t msize = be32toh(fh->mdata.h.offset); + if (rdev_chain(&fh->metadata, &addrspace_32bit.rdev, + (uintptr_t)&fh->mdata, msize) || + rdev_chain(&fh->data, &rdev, data_offset, be32toh(fh->mdata.h.len))) + return -1; + if (type) { + if (!*type) + *type = be32toh(fh->mdata.h.type); + else if (*type != be32toh(fh->mdata.h.type)) + return -1; } - if (!ret) - if (tspi_measure_cbfs_hook(fh, name)) - return -1; + if (tspi_measure_cbfs_hook(fh, name)) + return -1; - return ret; + return 0; } void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 857f5a52c3..69ded3c700 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -213,23 +214,7 @@ static void lb_vbnv(struct lb_header *header) __weak uint32_t board_id(void) { return UNDEFINED_STRAPPING_ID; } __weak uint32_t ram_code(void) { return UNDEFINED_STRAPPING_ID; } __weak uint32_t sku_id(void) { return UNDEFINED_STRAPPING_ID; } - -static void lb_board_id(struct lb_header *header) -{ - struct lb_strapping_id *rec; - uint32_t bid = board_id(); - - if (bid == UNDEFINED_STRAPPING_ID) - return; - - rec = (struct lb_strapping_id *)lb_new_record(header); - - rec->tag = LB_TAG_BOARD_ID; - rec->size = sizeof(*rec); - rec->id_code = bid; - - printk(BIOS_INFO, "Board ID: %d\n", bid); -} +__weak uint64_t fw_config_get(void) { return UNDEFINED_FW_CONFIG; } static void lb_boot_media_params(struct lb_header *header) { @@ -257,40 +242,6 @@ static void lb_boot_media_params(struct lb_header *header) bmp->fmap_offset = get_fmap_flash_offset(); } -static void lb_ram_code(struct lb_header *header) -{ - struct lb_strapping_id *rec; - uint32_t code = ram_code(); - - if (code == UNDEFINED_STRAPPING_ID) - return; - - rec = (struct lb_strapping_id *)lb_new_record(header); - - rec->tag = LB_TAG_RAM_CODE; - rec->size = sizeof(*rec); - rec->id_code = code; - - printk(BIOS_INFO, "RAM code: %d\n", code); -} - -static void lb_sku_id(struct lb_header *header) -{ - struct lb_strapping_id *rec; - uint32_t sid = sku_id(); - - if (sid == UNDEFINED_STRAPPING_ID) - return; - - rec = (struct lb_strapping_id *)lb_new_record(header); - - rec->tag = LB_TAG_SKU_ID; - rec->size = sizeof(*rec); - rec->id_code = sid; - - printk(BIOS_INFO, "SKU ID: %d\n", sid); -} - static void lb_mmc_info(struct lb_header *header) { struct lb_mmc_info *rec; @@ -370,6 +321,24 @@ static struct lb_mainboard *lb_mainboard(struct lb_header *header) return mainboard; } +static struct lb_board_config *lb_board_config(struct lb_header *header) +{ + struct lb_record *rec; + struct lb_board_config *config; + rec = lb_new_record(header); + config = (struct lb_board_config *)rec; + + config->tag = LB_TAG_BOARD_CONFIG; + config->size = sizeof(*config); + + config->board_id = board_id(); + config->ram_code = ram_code(); + config->sku_id = sku_id(); + config->fw_config = pack_lb64(fw_config_get()); + + return config; +} + #if CONFIG(USE_OPTION_TABLE) static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header) { @@ -536,11 +505,6 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) lb_vbnv(head); #endif - /* Add strapping IDs if available */ - lb_board_id(head); - lb_ram_code(head); - lb_sku_id(head); - /* Pass mmc early init status */ lb_mmc_info(head); @@ -563,6 +527,9 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) lb_boot_media_params(head); + /* Board configuration information (including straps) */ + lb_board_config(head); + /* Add architecture records. */ lb_arch_add_records(head); diff --git a/src/lib/fw_config.c b/src/lib/fw_config.c index ec3205958d..e17d40e58a 100644 --- a/src/lib/fw_config.c +++ b/src/lib/fw_config.c @@ -7,18 +7,14 @@ #include #include #include +#include #include #include #include -/** - * fw_config_get() - Provide firmware configuration value. - * - * Return 32bit firmware configuration value determined for the system. - */ -static uint32_t fw_config_get(void) +uint64_t fw_config_get(void) { - static uint32_t fw_config_value; + static uint64_t fw_config_value; static bool fw_config_value_initialized; /* Nothing to prepare if setup is already done. */ @@ -35,7 +31,7 @@ static uint32_t fw_config_get(void) __func__); fw_config_value = 0; } else { - printk(BIOS_INFO, "FW_CONFIG value from CBFS is 0x%08x\n", + printk(BIOS_INFO, "FW_CONFIG value from CBFS is 0x%" PRIx64 "\n", fw_config_value); return fw_config_value; } @@ -47,7 +43,7 @@ static uint32_t fw_config_get(void) printk(BIOS_WARNING, "%s: Could not get fw_config from EC\n", __func__); } - printk(BIOS_INFO, "FW_CONFIG value is 0x%08x\n", fw_config_value); + printk(BIOS_INFO, "FW_CONFIG value is 0x%" PRIx64 "\n", fw_config_value); return fw_config_value; } @@ -59,7 +55,8 @@ bool fw_config_probe(const struct fw_config *match) printk(BIOS_INFO, "fw_config match found: %s=%s\n", match->field_name, match->option_name); else - printk(BIOS_INFO, "fw_config match found: mask=0x%08x value=0x%08x\n", + printk(BIOS_INFO, "fw_config match found: mask=0x%" PRIx64 " value=0x%" + PRIx64 "\n", match->mask, match->value); return true; } @@ -70,20 +67,20 @@ bool fw_config_probe(const struct fw_config *match) #if ENV_RAMSTAGE /* - * The maximum number of fw_config fields is limited by the 32-bit mask that is used to + * The maximum number of fw_config fields is limited by the 64-bit mask that is used to * represent them. */ -#define MAX_CACHE_ELEMENTS (8 * sizeof(uint32_t)) +#define MAX_CACHE_ELEMENTS (8 * sizeof(uint64_t)) static const struct fw_config *cached_configs[MAX_CACHE_ELEMENTS]; -static size_t probe_index(uint32_t mask) +static size_t probe_index(uint64_t mask) { assert(mask); - return __ffs(mask); + return __ffs64(mask); } -const struct fw_config *fw_config_get_found(uint32_t field_mask) +const struct fw_config *fw_config_get_found(uint64_t field_mask) { const struct fw_config *config; config = cached_configs[probe_index(field_mask)]; diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index 3f9135c76d..4e124f28e3 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -45,70 +45,41 @@ chip northbridge/amd/agesa/family15tn/root_complex end device pnp 2e.6 off end # CIR device pnp 2e.7 on # GPIO6, GPIO7, GPIO8 - irq 0xe0 = 0x7f - irq 0xe1 = 0x10 - irq 0xe2 = 0x00 - irq 0xe3 = 0x00 - irq 0xe4 = 0xff - irq 0xe5 = 0xff - irq 0xe6 = 0xff - irq 0xe7 = 0xff - irq 0xec = 0x00 - irq 0xed = 0xff - irq 0xf4 = 0xff - irq 0xf5 = 0xff - irq 0xf6 = 0x00 - irq 0xf7 = 0x00 - irq 0xf8 = 0x00 + irq 0xf4 = 0xff # GPIO6 i/o + + irq 0xe0 = 0x7f # GPIO7 i/o + irq 0xe1 = 0x00 # GPIO7 data end - device pnp 2e.8 off # WDT1, GPIO0, GPIO1 - io 0x60 = 0x00 - irq 0xe0 = 0xff - irq 0xe1 = 0xff - irq 0xe2 = 0xff - irq 0xe3 = 0xff - irq 0xe4 = 0xff - irq 0xf0 = 0xff - irq 0xf1 = 0x28 - irq 0xf2 = 0x00 - irq 0xf3 = 0x00 - irq 0xf4 = 0x08 - irq 0xf5 = 0xff - irq 0xf6 = 0x00 - irq 0xf7 = 0xff + device pnp 2e.008 off # WDT1 + end + device pnp 2e.108 on # GPIO0, GPIO1 + irq 0xe0 = 0xff # GPIO0 i/o + irq 0xe2 = 0xff # GPIO0 inversion + irq 0xe4 = 0xff # GPIO0 multiplex + + irq 0xf0 = 0xff # GPIO1 i/o + irq 0xf4 = 0x08 # GPIO1 multiplex + + irq 0xf5 = 0xff # WDT1 control mode + irq 0xf6 = 0x00 # WDT1 counter + irq 0xf7 = 0xff # WDT1 control / status end device pnp 2e.009 off # GPIO8 end device pnp 2e.109 on # GPIO1 end device pnp 2e.209 on # GPIO2 - irq 0xe0 = 0xff - irq 0xe1 = 0x90 - irq 0xe2 = 0x00 - irq 0xe3 = 0x00 - irq 0xe9 = 0x00 + irq 0xe0 = 0xff # GPIO2 i/o end device pnp 2e.309 on # GPIO3 - irq 0xe4 = 0x7f - irq 0xe5 = 0x76 - irq 0xe6 = 0x00 - irq 0xe7 = 0x00 - irq 0xea = 0x00 - irq 0xfe = 0x00 + irq 0xe4 = 0x7f # GPIO3 i/o + irq 0xe5 = 0x00 # GPIO3 data end device pnp 2e.409 on # GPIO4 - irq 0xe8 = 0x00 - irq 0xf0 = 0xff - irq 0xf1 = 0x7b - irq 0xf2 = 0x00 - irq 0xee = 0x00 + irq 0xf0 = 0xff # GPIO4 i/o end device pnp 2e.509 on # GPIO5 - irq 0xeb = 0x00 - irq 0xf4 = 0xff - irq 0xf5 = 0xef - irq 0xf6 = 0x00 - irq 0xf7 = 0x00 + irq 0xf4 = 0xff # GPIO5 i/o end device pnp 2e.609 on # GPIO6 end @@ -126,10 +97,10 @@ chip northbridge/amd/agesa/family15tn/root_complex end device pnp 2e.d off end # WDT1 device pnp 2e.e off end # CIR WAKE-UP - device pnp 2e.f off # GPIO Push-pull/Open-drain selection + device pnp 2e.f on # GPIO Push-pull/Open-drain selection irq 0xe6 = 7f end - device pnp 2e.14 off # PORT80 UART + device pnp 2e.14 on # PORT80 UART irq 0xe0 = 0x00 end device pnp 2e.16 off end # Deep Sleep diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index e8827bf6de..f861503dda 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -86,10 +86,12 @@ chip soc/intel/cannonlake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 3 end device pci 14.1 off end # USB xDCI (OTG) - chip drivers/wifi/generic # CNVi wifi - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 off end # SDCard device pci 15.0 on # I2C #0 chip drivers/i2c/hid diff --git a/src/mainboard/example/Kconfig b/src/mainboard/example/Kconfig new file mode 100644 index 0000000000..5afc8ee5a9 --- /dev/null +++ b/src/mainboard/example/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_EXAMPLE + +choice + prompt "Mainboard model" + +source "src/mainboard/example/*/Kconfig.name" + +endchoice + +source "src/mainboard/example/*/Kconfig" + +config MAINBOARD_VENDOR + default "Example" + +endif # VENDOR_EXAMPLE diff --git a/src/mainboard/example/Kconfig.name b/src/mainboard/example/Kconfig.name new file mode 100644 index 0000000000..9ffc1738bc --- /dev/null +++ b/src/mainboard/example/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_EXAMPLE + bool "Example boards" diff --git a/src/mainboard/example/min86/Kconfig b/src/mainboard/example/min86/Kconfig new file mode 100644 index 0000000000..3a962e27f4 --- /dev/null +++ b/src/mainboard/example/min86/Kconfig @@ -0,0 +1,14 @@ +if BOARD_EXAMPLE_MIN86 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_EXAMPLE_MIN86 + select MISSING_BOARD_RESET + +config MAINBOARD_DIR + default "example/min86" + +config MAINBOARD_PART_NUMBER + default "Min86" + +endif diff --git a/src/mainboard/example/min86/Kconfig.name b/src/mainboard/example/min86/Kconfig.name new file mode 100644 index 0000000000..33131930f5 --- /dev/null +++ b/src/mainboard/example/min86/Kconfig.name @@ -0,0 +1,11 @@ +config BOARD_EXAMPLE_MIN86 + bool "Minimal x86 fake board" + help + This example mainboard code along with the example/min86 SoC + should serve as a minimal example how a buildable x86 SoC code + base can look like. + + This can serve, for instance, as a basis to add new SoCs to + coreboot. Starting with a buildable commit should help with + the review of the actual code, and also avoid any regressions + when common coreboot code changes. diff --git a/src/mainboard/example/min86/board_info.txt b/src/mainboard/example/min86/board_info.txt new file mode 100644 index 0000000000..c778859fab --- /dev/null +++ b/src/mainboard/example/min86/board_info.txt @@ -0,0 +1 @@ +Category: misc diff --git a/src/mainboard/example/min86/devicetree.cb b/src/mainboard/example/min86/devicetree.cb new file mode 100644 index 0000000000..9af04c091a --- /dev/null +++ b/src/mainboard/example/min86/devicetree.cb @@ -0,0 +1,6 @@ +chip soc/example/min86 + + device domain 0 on + end + +end diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index 09593b7b53..26a53366b4 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -26,7 +26,7 @@ chip soc/intel/broadwell device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # EC range is 0x800-0x9ff register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x00fc0901" @@ -83,6 +83,6 @@ chip soc/intel/broadwell device pci 1f.2 on end # SATA Controller device pci 1f.3 off end # SMBus device pci 1f.6 on end # Thermal -# end + end end end diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb index dc70085dd0..81110408c1 100644 --- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb @@ -8,10 +8,12 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5" -# end + + device pci 1f.2 on end # SATA Controller + end end end diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb index b46e34cf83..eb33d433e8 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb @@ -8,10 +8,12 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x7" register "sata_port1_gen3_dtle" = "0x5" -# end + + device pci 1f.2 on end # SATA Controller + end end end diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index 45229bad6d..60fb08cbf7 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -10,7 +10,7 @@ chip soc/intel/broadwell register "s0ix_enable" = "0" device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch register "sata_devslp_disable" = "0x1" register "sio_i2c0_voltage" = "1" # 1.8V @@ -34,7 +34,8 @@ chip soc/intel/broadwell device pci 1c.0 off end # PCIe Port #1 device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1) device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) + device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus -# end + end end end diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb index eae7999ea2..c7e2421ee8 100644 --- a/src/mainboard/google/auron/variants/gandof/overridetree.cb +++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb @@ -8,10 +8,12 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5" -# end + + device pci 1f.2 on end # SATA Controller + end end end diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb index dc70085dd0..81110408c1 100644 --- a/src/mainboard/google/auron/variants/lulu/overridetree.cb +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -8,10 +8,12 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5" -# end + + device pci 1f.2 on end # SATA Controller + end end end diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index 710fa95cac..d8aec0ae04 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -17,7 +17,7 @@ chip soc/intel/broadwell register "s0ix_enable" = "0" device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch register "sata_port0_gen3_tx" = "0x72" # Set I2C0 to 1.8V @@ -36,6 +36,7 @@ chip soc/intel/broadwell device pci 1c.0 off end # PCIe Port #1 device pci 1c.2 on end # PCIe Port #3 device pci 1d.0 off end # USB2 EHCI -# end + device pci 1f.2 on end # SATA Controller + end end end diff --git a/src/mainboard/google/dedede/board_info.c b/src/mainboard/google/dedede/board_info.c index fdb4b5ff64..22d35d7475 100644 --- a/src/mainboard/google/dedede/board_info.c +++ b/src/mainboard/google/dedede/board_info.c @@ -3,7 +3,7 @@ #include #include -int board_info_get_fw_config(uint32_t *fw_config) +int board_info_get_fw_config(uint64_t *fw_config) { return google_chromeec_cbi_get_fw_config(fw_config); } diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 4713589608..a5ff128079 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -302,10 +302,12 @@ chip soc/intel/jasperlake end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 on end # SDCard device pci 15.0 on end # I2C 0 device pci 15.1 on end # I2C 1 diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index dc855c63cd..bb41e45931 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -21,7 +21,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num); * @param fw_config Address where the fw_config is stored. * @return 0 on success or negative integer for errors. */ -int board_info_get_fw_config(uint32_t *fw_config); +int board_info_get_fw_config(uint64_t *fw_config); /* Return memory configuration structure. */ const struct mb_cfg *variant_memcfg_config(void); diff --git a/src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc b/src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc index b0ca2223a8..285df73c2e 100644 --- a/src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc @@ -1,5 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. -SPD_SOURCES = placeholder.spd.hex +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt index fa247902ee..100c322e91 100644 --- a/src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt @@ -1 +1,6 @@ DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E1G32D2NP-046 WT:A 1 (0001) +K4UBE3D4AA-MGCR 2 (0010) diff --git a/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt index 59381dcf5b..f05a5af118 100644 --- a/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt @@ -1,6 +1,5 @@ -# This is a CSV file containing a list of memory parts used by this variant. -# Generate an updated Makefile.inc and dram_id.generated.txt by running the -# gen_part_id tool from util/spd_tools/lp4x -# See util/spd_tools/lp4x/README.md for more details and instructions. - -# Part Name +MT53E512M32D2NP-046 WT:E +K4U6E3S4AA-MGCR +H9HCNNNBKMMLXR-NEE +MT53E1G32D2NP-046 WT:A +K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index bbb63bcc61..4a0c49f2aa 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -242,10 +242,12 @@ chip soc/intel/tigerlake device pci 14.1 off end # USB 3.2 1x1 xDCI HC device pci 14.2 on end # Shared SRAM - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi WiFi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi WiFi device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index de3b5ca8ea..aeacaa48dd 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -327,10 +327,12 @@ chip soc/intel/cannonlake end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 off end # SDCard device pci 15.0 on chip drivers/i2c/hid diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 257ad77a42..afc9de0192 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -143,6 +143,7 @@ config MAINBOARD_PART_NUMBER default "Stryke" if BOARD_GOOGLE_STRYKE default "Wyvern" if BOARD_GOOGLE_WYVERN default "Dooly" if BOARD_GOOGLE_DOOLY + default "Ambassador" if BOARD_GOOGLE_AMBASSADOR config OVERRIDE_DEVICETREE string @@ -176,6 +177,7 @@ config VARIANT_DIR default "stryke" if BOARD_GOOGLE_STRYKE default "wyvern" if BOARD_GOOGLE_WYVERN default "dooly" if BOARD_GOOGLE_DOOLY + default "ambassador" if BOARD_GOOGLE_AMBASSADOR config VBOOT select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 69bb28ac00..71166d0bcf 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -97,3 +97,7 @@ config BOARD_GOOGLE_WYVERN config BOARD_GOOGLE_DOOLY bool "-> Dooly" select BOARD_GOOGLE_BASEBOARD_PUFF + +config BOARD_GOOGLE_AMBASSADOR + bool "-> Ambassador" + select BOARD_GOOGLE_BASEBOARD_PUFF diff --git a/src/mainboard/google/hatch/variants/ambassador/Makefile.inc b/src/mainboard/google/hatch/variants/ambassador/Makefile.inc new file mode 100644 index 0000000000..3b5b7d000d --- /dev/null +++ b/src/mainboard/google/hatch/variants/ambassador/Makefile.inc @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += gpio.c +bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/ambassador/gpio.c b/src/mainboard/google/hatch/variants/ambassador/gpio.c new file mode 100644 index 0000000000..5a911fc4f9 --- /dev/null +++ b/src/mainboard/google/hatch/variants/ambassador/gpio.c @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static const struct pad_config gpio_table[] = { + /* A16 : SD_OC_ODL */ + PAD_CFG_GPI(GPP_A16, NONE, DEEP), + /* A18 : LAN_PE_ISOLATE_ODL */ + PAD_CFG_GPO(GPP_A18, 1, DEEP), + /* A23 : M2_WLAN_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), + + /* B5 : LAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + + /* C0 : SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1 : SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C6: M2_WLAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), + /* C7 : LAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), + /* C10 : PCH_PCON_RST_ODL */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C11 : PCH_PCON_PDB_ODL */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), + /* C15 : WLAN_OFF_L */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), + + /* E2 : EN_PP_MST_OD */ + PAD_CFG_GPO(GPP_E2, 1, DEEP), + /* E9 : USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : USB_A1_OC_ODL */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + + /* F11 : EMMC_CMD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA0 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA1 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA2 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA3 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA4 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA5 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA6 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA7 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_CLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + + /* H4: PCH_I2C_PCON_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5: PCH_I2C_PCON_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H22 : PWM_PP3300_BIOZZER */ + PAD_CFG_GPO(GPP_H22, 0, DEEP), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* B14 : GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B22 : GPP_B22_STRAP */ + PAD_NC(GPP_B22, NONE), + /* E19 : GPP_E19_STRAP */ + PAD_NC(GPP_E19, NONE), + /* E21 : GPP_E21_STRAP */ + PAD_NC(GPP_E21, NONE), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/ambassador/include/variant/ec.h b/src/mainboard/google/hatch/variants/ambassador/include/variant/ec.h new file mode 100644 index 0000000000..59fb3783c5 --- /dev/null +++ b/src/mainboard/google/hatch/variants/ambassador/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/ambassador/include/variant/gpio.h b/src/mainboard/google/hatch/variants/ambassador/include/variant/gpio.h new file mode 100644 index 0000000000..79a141008f --- /dev/null +++ b/src/mainboard/google/hatch/variants/ambassador/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb new file mode 100644 index 0000000000..adb00e485f --- /dev/null +++ b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb @@ -0,0 +1,480 @@ +chip soc/intel/cannonlake + # Enable heci communication + register "HeciEnabled" = "1" + + # Auto-switch between X4 NVMe and X2 NVMe. + register "TetonGlacierMode" = "1" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # USB configuration + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 2 + register "usb2_ports[1]" = "{ + .enable = 1, + .ocpin = OC1, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 1 + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC3, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 3 + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[4]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 4 + register "usb2_ports[5]" = "{ + .enable = 1, + .ocpin = OC0, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A port 0 + register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 + + # Bitmap for Wake Enable on USB attach/detach + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(5) | \ + USB_PORT_WAKE_ENABLE(6)" + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(5) | \ + USB_PORT_WAKE_ENABLE(6)" + + # Enable eMMC HS400 + register "ScsEmmcHs400Enabled" = "1" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-14.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-14.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-14.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-14.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-14.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-14.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" + + # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. + register "PchHdaAudioLinkSsp1" = "0" + register "PchHdaAudioLinkDmic0" = "0" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | RFU | + #| I2C2 | PS175 | + #| I2C3 | MST | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + }" + + # PCIe port 7 for LAN + register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + # PCIe port 11 (x2) for NVMe hybrid storage devices + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # Uses CLK SRC 0 + register "PcieClkSrcUsage[0]" = "6" + register "PcieClkSrcClkReq[0]" = "0" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + # SATA port 1 Gen3 Strength + # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB + register "sata_port[1].TxGen3DeEmphEnable" = "1" + register "sata_port[1].TxGen3DeEmph" = "0x20" + + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(90, 85), + TEMP_PCT(85, 75), + TEMP_PCT(80, 65), + TEMP_PCT(75, 55), + TEMP_PCT(70, 45),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(50, 85), + TEMP_PCT(47, 75), + TEMP_PCT(45, 65), + TEMP_PCT(42, 55), + TEMP_PCT(39, 45),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + + ## Power Limits Control + # PL1 is fixed at 15W, avg over 28-32s interval + # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 25000, + .max_power = 64000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Left"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Right"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Right"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Middle"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Left"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 2.5 on end + end + chip drivers/usb/acpi + device usb 2.6 off end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Left"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Right"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Right"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Left"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Middle"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.5 on end + end + end + end + end # USB xHCI + device pci 15.0 off + # RFU - Reserved for Future Use. + end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 on + chip drivers/i2c/generic + register "hid" = ""1AF80175"" + register "name" = ""PS17"" + register "desc" = ""Parade PS175"" + device i2c 4a on end + end + end # I2C #2, PCON PS175. + device pci 15.3 on + chip drivers/i2c/generic + register "hid" = ""10EC2142"" + register "name" = ""RTD2"" + register "desc" = ""Realtek RTD2142"" + device i2c 4a on end + end + end # I2C #3, Realtek RTD2142. + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1a.0 on end # eMMC + device pci 1c.6 on + chip drivers/net + register "customized_leds" = "0x05af" + register "wake" = "GPE0_DW1_07" # GPP_C7 + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" + register "stop_delay_ms" = "12" # NIC needs time to quiesce + register "stop_off_delay_ms" = "1" + register "has_power_resource" = "1" + register "device_index" = "0" + device pci 00.0 on end + end + end # RTL8111H Ethernet NIC + device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1e.3 off end # GSPI #1 + end + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | + #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | + #+----------------+-------+-------+-------+-------+ + #Note: IccMax settings are moved to SoC code + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 1004, + .dc_loadline = 1004, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 181, + .dc_loadline = 181, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 319, + .dc_loadline = 319, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 319, + .dc_loadline = 319, + }" + +end diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index cdd83df114..dddbca421d 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -295,10 +295,12 @@ chip soc/intel/cannonlake end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 on end # SDCard device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index c4707e0c00..94fd8044c1 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -9,27 +9,6 @@ chip soc/intel/broadwell # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # SuperIO range is 0x700-0x73f - register "gen2_dec" = "0x003c0701" - - register "alt_gp_smi_en" = "0x0000" - register "gpe0_en_1" = "0x00000000" - register "gpe0_en_2" = "0x00000000" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - register "sata_devslp_disable" = "0x1" - - # Force enable ASPM for PCIe Port 4 - register "pcie_port_force_aspm" = "0x10" - - # Enable port coalescing - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP - register "icc_clock_disable" = "0x01220000" - device cpu_cluster 0 on device lapic 0 on end end @@ -38,78 +17,102 @@ chip soc/intel/broadwell device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 off end # Serial I/O DMA - device pci 15.1 off end # I2C0 - device pci 15.2 off end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip superio/ite/it8772f - # Skip keyboard init - register "skip_keyboard" = "1" - # Enable PECI on TMPIN3 - register "peci_tmpin" = "3" - # Disable use of TMPIN1 - register "tmpin1_mode" = "0" - # Enable Thermal Diode on TMPIN2 - register "tmpin2_mode" = "1" - # Enable FAN2 - register "fan2_enable" = "1" - # Default FAN2 speed - register "fan2_speed" = "0x4d" - device pnp 2e.0 off end # FDC - device pnp 2e.1 on # Serial Port 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + chip soc/intel/broadwell/pch + # SuperIO range is 0x700-0x73f + register "gen2_dec" = "0x003c0701" + + register "alt_gp_smi_en" = "0x0000" + register "gpe0_en_1" = "0x00000000" + register "gpe0_en_2" = "0x00000000" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "sata_port_map" = "0x1" + register "sata_devslp_disable" = "0x1" + + # Force enable ASPM for PCIe Port 4 + register "pcie_port_force_aspm" = "0x10" + + # Enable port coalescing + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP + register "icc_clock_disable" = "0x01220000" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end end - device pnp 2e.4 on # Environment Controller - io 0x60 = 0x700 - io 0x62 = 0x710 - irq 0x70 = 0x09 - irq 0xf2 = 0x20 - irq 0xf4 = 0x0 - irq 0xfa = 0x12 + chip superio/ite/it8772f + # Skip keyboard init + register "skip_keyboard" = "1" + # Enable PECI on TMPIN3 + register "peci_tmpin" = "3" + # Disable use of TMPIN1 + register "tmpin1_mode" = "0" + # Enable Thermal Diode on TMPIN2 + register "tmpin2_mode" = "1" + # Enable FAN2 + register "fan2_enable" = "1" + # Default FAN2 speed + register "fan2_speed" = "0x4d" + + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x700 + io 0x62 = 0x710 + irq 0x70 = 0x09 + irq 0xf2 = 0x20 + irq 0xf4 = 0x0 + irq 0xfa = 0x12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x720 + io 0x62 = 0x730 + end + device pnp 2e.5 off + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end # Keyboard + device pnp 2e.6 off + irq 0x70 = 12 + end # Mouse + device pnp 2e.a off end # IR end - device pnp 2e.7 on # GPIO - io 0x60 = 0x720 - io 0x62 = 0x730 - end - device pnp 2e.5 off - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end # Keyboard - device pnp 2e.6 off - irq 0x70 = 12 - end # Mouse - device pnp 2e.a off end # IR - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal + end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal + end end end diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 23a41691f9..cff94daf20 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -36,7 +36,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER - select MT8183_DRAM_EMCP if BOARD_GOOGLE_KRANE + select MT8183_DRAM_EMCP if BOARD_GOOGLE_KRANE || BOARD_GOOGLE_KAKADU config MAINBOARD_DIR string diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 6d77116c89..cbcd48aab4 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -114,10 +114,12 @@ chip soc/intel/apollolake device pci 00.2 off end # - NPK device pci 02.0 on end # - Gen device pci 03.0 on end # - Gaussian Mixture Model (GMM) - chip drivers/wifi/generic - register "wake" = "GPE0A_CNVI_PME_STS" - device pci 0c.0 on end # - CNVi - end + device pci 0c.0 on + chip drivers/wifi/generic + register "wake" = "GPE0A_CNVI_PME_STS" + device generic 0 on end + end + end # - CNVi device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC device pci 0d.2 on end # - Fast SPI diff --git a/src/mainboard/google/octopus/variants/dood/overridetree.cb b/src/mainboard/google/octopus/variants/dood/overridetree.cb index e1f12cf08f..6e767dd7d3 100644 --- a/src/mainboard/google/octopus/variants/dood/overridetree.cb +++ b/src/mainboard/google/octopus/variants/dood/overridetree.cb @@ -144,6 +144,20 @@ chip soc/intel/apollolake register "has_power_resource" = "1" device i2c 39 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7502"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # - I2C 7 end diff --git a/src/mainboard/google/octopus/variants/fleex/Makefile.inc b/src/mainboard/google/octopus/variants/fleex/Makefile.inc index 51c9d39021..2835934d6e 100644 --- a/src/mainboard/google/octopus/variants/fleex/Makefile.inc +++ b/src/mainboard/google/octopus/variants/fleex/Makefile.inc @@ -3,3 +3,5 @@ bootblock-y += gpio.c ramstage-y += gpio.c ramstage-y += variant.c + +smm-y += variant.c diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb index 679b101037..2fd554ff88 100644 --- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb +++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb @@ -84,6 +84,10 @@ chip soc/intel/apollolake }, }" + # Disable compliance mode + register "DisableComplianceMode" = "1" + register "disable_xhci_lfps_pm" = "0" + device domain 0 on device pci 16.0 on chip drivers/i2c/hid @@ -181,7 +185,4 @@ chip soc/intel/apollolake end end # - I2C 7 end - - # Disable compliance mode - register "DisableComplianceMode" = "1" end diff --git a/src/mainboard/google/octopus/variants/fleex/variant.c b/src/mainboard/google/octopus/variants/fleex/variant.c index 522faa9d7b..5554fb3388 100644 --- a/src/mainboard/google/octopus/variants/fleex/variant.c +++ b/src/mainboard/google/octopus/variants/fleex/variant.c @@ -4,6 +4,7 @@ #include #include #include +#include #define MIN_LTE_SKU 4 @@ -31,3 +32,13 @@ const char *get_wifi_sar_cbfs_filename(void) return filename; } + +void variant_update_devtree(struct device *dev) +{ + struct soc_intel_apollolake_config *cfg = NULL; + + cfg = (struct soc_intel_apollolake_config *)dev->chip_info; + // Force disable_xhci_lfps_pm to update if it is LTE sku + if (cfg != NULL && is_lte_sku()) + cfg->disable_xhci_lfps_pm = 1; +} diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 3ff9b30637..8562046237 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -304,10 +304,12 @@ chip soc/intel/cannonlake end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 off end # SDCard device pci 15.0 on chip drivers/i2c/hid diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 17d0127ce6..1334749542 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -316,10 +316,12 @@ chip soc/intel/cannonlake end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 off end # SDCard device pci 15.0 on chip drivers/i2c/hid diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 69f58b5082..23dbf68fe9 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -24,7 +24,8 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_SPI_TPM_CR50 + select MAINBOARD_HAS_SPI_TPM_CR50 if !BOARD_GOOGLE_VOLTEER2_TI50 + select MAINBOARD_HAS_I2C_TPM_CR50 if BOARD_GOOGLE_VOLTEER2_TI50 select MAINBOARD_HAS_TPM2 select PCIEXP_HOTPLUG select SOC_INTEL_TIGERLAKE @@ -71,6 +72,14 @@ config OVERRIDE_DEVICETREE config DRIVER_TPM_SPI_BUS default 0x1 +config DRIVER_TPM_I2C_BUS + hex + default 0x1 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x50 + config MAINBOARD_DIR string default "google/volteer" @@ -91,9 +100,11 @@ config MAINBOARD_PART_NUMBER default "Trondo" if BOARD_GOOGLE_TRONDO default "Volteer" if BOARD_GOOGLE_VOLTEER default "Volteer2" if BOARD_GOOGLE_VOLTEER2 + default "Volteer2_Ti50" if BOARD_GOOGLE_VOLTEER2_TI50 default "Voxel" if BOARD_GOOGLE_VOXEL default "Boldar" if BOARD_GOOGLE_BOLDAR default "Elemi" if BOARD_GOOGLE_ELEMI + default "Voema" if BOARD_GOOGLE_VOEMA config MAX_CPUS int @@ -129,9 +140,11 @@ config VARIANT_DIR default "trondo" if BOARD_GOOGLE_TRONDO default "volteer" if BOARD_GOOGLE_VOLTEER default "volteer2" if BOARD_GOOGLE_VOLTEER2 + default "volteer2" if BOARD_GOOGLE_VOLTEER2_TI50 default "voxel" if BOARD_GOOGLE_VOXEL default "boldar" if BOARD_GOOGLE_BOLDAR default "elemi" if BOARD_GOOGLE_ELEMI + default "voema" if BOARD_GOOGLE_VOEMA config VARIANT_HAS_MIPI_CAMERA bool diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index f59d82b850..d8f1b4470c 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -58,6 +58,15 @@ config BOARD_GOOGLE_VOLTEER2 select USE_CAR_NEM_ENHANCED_V2 select DRIVERS_GENESYSLOGIC_GL9755 +# Reworked Volteer2 prototype, Haven chip replaced with Dauntless demo board +config BOARD_GOOGLE_VOLTEER2_TI50 + bool "-> Volteer2_Ti50" + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select VARIANT_HAS_MIPI_CAMERA + select SOC_INTEL_CSE_LITE_SKU + select USE_CAR_NEM_ENHANCED_V2 + select DRIVERS_GENESYSLOGIC_GL9755 + config BOARD_GOOGLE_VOXEL bool "-> Voxel" select BOARD_GOOGLE_BASEBOARD_VOLTEER @@ -71,3 +80,7 @@ config BOARD_GOOGLE_BOLDAR config BOARD_GOOGLE_ELEMI bool "-> Elemi" select BOARD_GOOGLE_BASEBOARD_VOLTEER + +config BOARD_GOOGLE_VOEMA + bool "-> Voema" + select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 03a78fd777..016572a39f 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -9,14 +9,65 @@ #include #include #include +#include #include #include #include #include +#include "drivers/intel/pmc_mux/conn/chip.h" + +extern struct chip_operations drivers_intel_pmc_mux_conn_ops; + +static bool is_port1(struct device *dev) +{ + return dev->path.type == DEVICE_PATH_GENERIC && dev->path.generic.id == 1 && + dev->chip_ops == &drivers_intel_pmc_mux_conn_ops; +} + +static void typec_orientation_fixup(void) +{ + /* + * TODO: This is an ugly hack, see if there's a better way to accomplish this same thing + * via fw_config + devicetree, i.e., change a register's value depending on fw_config + * probing. + */ + const struct device *pmc; + const struct device *mux; + const struct device *conn; + + pmc = pcidev_path_on_root(PCH_DEVFN_PMC); + if (!pmc || !pmc->link_list->children) { + printk(BIOS_ERR, "%s: unable to find PMC device or its mux\n", __func__); + return; + } + + /* + * Find port 1 underneath PMC.MUX; some variants may not have this defined, so it's okay + * to just silently return here. + */ + mux = pmc->link_list->children; + conn = dev_find_matching_device_on_bus(mux->link_list, is_port1); + if (!conn) + return; + + if (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) || + fw_config_probe(FW_CONFIG(DB_USB, USB3_ACTIVE)) || + fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3)) || + fw_config_probe(FW_CONFIG(DB_USB, USB3_NO_A))) { + struct drivers_intel_pmc_mux_conn_config *config = conn->chip_info; + + if (config) { + printk(BIOS_INFO, "Configure Right Type-C port orientation for retimer\n"); + config->sbu_orientation = TYPEC_ORIENTATION_NORMAL; + } + } +} + static void mainboard_init(struct device *dev) { mainboard_ec_init(); + typec_orientation_fixup(); } static void add_fw_config_oem_string(const struct fw_config *config, void *arg) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 2a62505757..20a3843439 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -6,6 +6,7 @@ fw_config option USB4_GEN3 3 option USB3_PASSIVE 4 option USB3_NO_A 5 + option USB3_NO_C 6 end field THERMAL 4 7 end field AUDIO 8 10 @@ -433,9 +434,11 @@ chip soc/intel/tigerlake device ref cnvi_bt on end device ref south_xhci on end device ref shared_ram on end - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device ref cnvi_wifi on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end end device ref heci1 on end device ref sata on end diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl index 51034c3d73..d0d1c2862a 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl @@ -146,64 +146,58 @@ Scope (\_SB.PCI0.IPU0) Scope (\_SB.PCI0.I2C3) { + /* Reference counter to track power control by RCAM and VCM */ + Name (REFC, 0) PowerResource (RCPR, 0x00, 0x0000) { - Name (STA, Zero) + Name (STA, 0) Method (_ON, 0, Serialized) /* Rear camera_ON_: Power On */ { - If ((STA == Zero)) + /* Enable IMG_CLK */ + MCON(3,1) /* Clock 3, 19.2MHz */ + + /* Pull RST low */ + CTXS(GPP_F15) + + /* Pull SNRPWR_EN high */ + STXS(GPP_H14) + + If (REFC == 0) { - /* Enable IMG_CLK */ - MCON(3,1) /* Clock 3, 19.2MHz */ - - /* Pull RST low */ -#if CONFIG(BOARD_GOOGLE_VOLTEER) - CTXS(GPP_F15) -#else - CTXS(GPP_D4) -#endif - - /* Pull SNRPWR_EN high */ - STXS(GPP_H14) - /* Pull PWREN high */ STXS(GPP_H20) - Sleep(2) /* reset pulse width */ - - /* Pull RST high */ -#if CONFIG(BOARD_GOOGLE_VOLTEER) - STXS(GPP_F15) -#else - STXS(GPP_D4) -#endif - Sleep(1) /* t2 */ - - Store(1,STA) } + Sleep(2) /* reset pulse width */ + + REFC++ + + /* Pull RST high */ + STXS(GPP_F15) + + Sleep(1) /* t2 */ + + STA = 1 } Method (_OFF, 0, Serialized) /* Rear camera _OFF: Power Off */ { - If ((STA == One)) + /* Disable IMG_CLK */ + Sleep(1) /* t0+t1 */ + MCOF(3) /* Clock 3 */ + + /* Pull RST low */ + CTXS(GPP_F15) + + If (REFC == 1) { - /* Disable IMG_CLK */ - Sleep(1) /* t0+t1 */ - MCOF(3) /* Clock 3 */ - - /* Pull RST low */ -#if CONFIG(BOARD_GOOGLE_VOLTEER) - CTXS(GPP_F15) -#else - CTXS(GPP_D4) -#endif - /* Pull PWREN low */ CTXS(GPP_H20) - - /* Pull SNRPWR_EN low */ - CTXS(GPP_H14) - - Store(0,STA) } + REFC-- + + /* Pull SNRPWR_EN low */ + CTXS(GPP_H14) + + STA = 0 } Method (_STA, 0, NotSerialized) /* _STA: Status */ { @@ -266,7 +260,7 @@ Scope (\_SB.PCI0.I2C3) { "i2c-allow-low-power-probe", 0x01 - } + } } }) Name (PRT0, Package (0x04) @@ -339,6 +333,35 @@ Scope (\_SB.PCI0.I2C3) }) } + PowerResource (VCPR, 0x00, 0x0000) + { + Name (STA, 0) + Method (_ON, 0, Serialized) /* VCPR_ON_: VCM Power On */ + { + If (REFC == 0) + { + /* Pull PWREN high */ + STXS(GPP_H20) + } + REFC++ + STA = 1 + } + Method (_OFF, 0, Serialized) /* VCPR_OFF: VCM Power Off */ + { + If (REFC == 1) + { + /* Pull PWREN low */ + CTXS(GPP_H20) + } + REFC-- + STA = 0 + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + Device (VCM0) { Name (_HID, "PRP0001") /* _HID: Hardware ID */ @@ -361,11 +384,11 @@ Scope (\_SB.PCI0.I2C3) }) Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ { - RCPR + VCPR }) Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ { - RCPR + VCPR }) Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ { @@ -381,7 +404,7 @@ Scope (\_SB.PCI0.I2C3) { "i2c-allow-low-power-probe", 0x01 - } + } } }) } @@ -455,12 +478,12 @@ Scope (\_SB.PCI0.I2C3) Scope (\_SB.PCI0.I2C2) { + Name (STA, Zero) PowerResource (FCPR, 0x00, 0x0000) { - Name (STA, Zero) Method (_ON, 0, Serialized) /* Front camera_ON_: Power On */ { - If ((STA == Zero)) + If (STA == 0) { /* Enable IMG_CLK */ MCON(2,1) /* Clock 2, 19.2MHz */ @@ -479,12 +502,12 @@ Scope (\_SB.PCI0.I2C2) STXS(GPP_D4) Sleep(1) /* t2 */ - Store(1,STA) + STA = 1 } } Method (_OFF, 0, Serialized) /* Front camera_OFF_: Power Off */ { - If ((STA == One)) + If (STA == 1) { /* Disable IMG_CLK */ Sleep(1) /* t0+t1 */ @@ -499,7 +522,7 @@ Scope (\_SB.PCI0.I2C2) /* Pull SNRPWR_EN low */ CTXS(GPP_D18) - Store(0,STA) + STA = 0 } } Method (_STA, 0, NotSerialized) /* _STA: Status */ diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index 5ecfccfba0..e2beb039f9 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -13,7 +13,78 @@ chip soc/intel/tigerlake register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" + register "tcc_offset" = "8" + + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + .tdp_pl4 = 105, + }" + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active" = "{ + [0] = {.target = DPTF_TEMP_SENSOR_3, + .thresholds = {TEMP_PCT(57, 90), + TEMP_PCT(47, 80), + TEMP_PCT(40, 70), + TEMP_PCT(36, 60), + TEMP_PCT(34, 50), + TEMP_PCT(30, 40),}}}" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 6000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 6000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 75, 6000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 6000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 6000)}" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 80, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 80, SHUTDOWN)}" + + ## Power Limits Control + # 3-15W PL1 in 200mW increments, avg over 28-32s interval + # PL2 is 15-51W, avg over 28-32s interval + register "controls.power_limits" = "{ + .pl1 = {.min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 15000, + .max_power = 51000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 5200, 220, 2200, }, + [1] = { 80, 4900, 180, 1800, }, + [2] = { 70, 4600, 145, 1450, }, + [3] = { 60, 4200, 115, 1150, }, + [4] = { 50, 3800, 90, 900, }, + [5] = { 40, 3400, 55, 550, }, + [6] = { 30, 2900, 30, 300, }, + [7] = { 20, 2300, 15, 150, }, + [8] = { 10, 1600, 10, 100, }, + [9] = { 0, 0, 0, 50, }}" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x9A03 device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -70,6 +141,13 @@ chip soc/intel/tigerlake device i2c 15 on end end end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -80,14 +158,77 @@ chip soc/intel/tigerlake register "usb3_port_number" = "1" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "4" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end + end + end + end + end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_ACTIVE + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on + probe DB_USB USB3_ACTIVE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end end end end diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 7fd65767fc..249505fc41 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -187,5 +187,68 @@ chip soc/intel/tigerlake end end end # PMC + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_ACTIVE + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on + probe DB_USB USB3_ACTIVE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/elemi/memory.c b/src/mainboard/google/volteer/variants/elemi/memory.c index d3de4be711..32b7abca17 100644 --- a/src/mainboard/google/volteer/variants/elemi/memory.c +++ b/src/mainboard/google/volteer/variants/elemi/memory.c @@ -21,10 +21,10 @@ const struct ddr_memory_cfg *variant_memory_params(void) int variant_memory_sku(void) { gpio_t spd_gpios[] = { - GPIO_MEM_CONFIG_3, - GPIO_MEM_CONFIG_2, - GPIO_MEM_CONFIG_1, GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, }; return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb index 32204c58e7..31e1927a91 100644 --- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -1,6 +1,81 @@ chip soc/intel/tigerlake device domain 0 on + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on + probe DB_USB USB3_ACTIVE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port2 on + probe DB_USB USB3_ACTIVE + end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/halvor/overridetree.cb b/src/mainboard/google/volteer/variants/halvor/overridetree.cb index f8b29212f8..a786bddd09 100644 --- a/src/mainboard/google/volteer/variants/halvor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/halvor/overridetree.cb @@ -119,5 +119,64 @@ chip soc/intel/tigerlake end end device ref hda on end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index 5f0f290a5b..87ca0a38cf 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -71,5 +71,68 @@ chip soc/intel/tigerlake device i2c 15 on end end end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_NO_A + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on + probe DB_USB USB3_NO_A + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/malefor/overridetree.cb b/src/mainboard/google/volteer/variants/malefor/overridetree.cb index 64b15b3dcc..c5c0180d2a 100644 --- a/src/mainboard/google/volteer/variants/malefor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/malefor/overridetree.cb @@ -113,5 +113,68 @@ chip soc/intel/tigerlake device generic 0 on end end end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_NO_A + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on + probe DB_USB USB3_NO_A + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index ae26e79558..efb2af822e 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -14,14 +14,15 @@ chip soc/intel/tigerlake register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1 - register "SaGv" = "SaGv_Disabled" - # Disable SRCCLKREQ1# register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" device domain 0 on device ref dptf on chip drivers/intel/dptf + ## Disable Active Policy + register "policies.active" = "{[0] = {.target=DPTF_NONE}}" + ## Passive Policy register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 85, 1000), @@ -172,6 +173,13 @@ chip soc/intel/tigerlake device i2c 15 on end end end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -182,14 +190,93 @@ chip soc/intel/tigerlake register "usb3_port_number" = "1" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "3" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end + end + end + end + end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB4_GEN3 + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port3 on + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port2 on + probe DB_USB USB4_GEN3 + end end end end diff --git a/src/mainboard/google/volteer/variants/todor/overridetree.cb b/src/mainboard/google/volteer/variants/todor/overridetree.cb index ae26e79558..fbf724f601 100644 --- a/src/mainboard/google/volteer/variants/todor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/todor/overridetree.cb @@ -22,6 +22,9 @@ chip soc/intel/tigerlake device domain 0 on device ref dptf on chip drivers/intel/dptf + ## Disable Active Policy + register "policies.active" = "{[0] = {.target=DPTF_NONE}}" + ## Passive Policy register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 85, 1000), @@ -172,6 +175,13 @@ chip soc/intel/tigerlake device i2c 15 on end end end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -182,14 +192,14 @@ chip soc/intel/tigerlake register "usb3_port_number" = "1" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "3" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end diff --git a/src/mainboard/google/volteer/variants/trondo/overridetree.cb b/src/mainboard/google/volteer/variants/trondo/overridetree.cb index d18bb10ff2..e1db3d6df0 100644 --- a/src/mainboard/google/volteer/variants/trondo/overridetree.cb +++ b/src/mainboard/google/volteer/variants/trondo/overridetree.cb @@ -75,5 +75,68 @@ chip soc/intel/tigerlake device i2c 15 on end end end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port2 on + probe DB_USB USB3_NO_C + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port2 on + probe DB_USB USB3_NO_C + end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/voema/include/variant/ec.h b/src/mainboard/google/volteer/variants/voema/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/volteer/variants/voema/include/variant/gpio.h b/src/mainboard/google/volteer/variants/voema/include/variant/gpio.h new file mode 100644 index 0000000000..b5fa8c5485 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/include/variant/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc b/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc new file mode 100644 index 0000000000..b0ca2223a8 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt new file mode 100644 index 0000000000..fa247902ee --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt new file mode 100644 index 0000000000..f51b3af398 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt @@ -0,0 +1,4 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4 or util/spd_tools/lp4x +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb new file mode 100644 index 0000000000..32204c58e7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/tigerlake + + device domain 0 on + end + +end diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index c5b4c72927..75dbc57a95 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -221,6 +221,13 @@ chip soc/intel/tigerlake end end end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -230,28 +237,116 @@ chip soc/intel/tigerlake register "usb2_port_number" = "9" register "usb3_port_number" = "1" # SBU & HSL follow CC - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "4" register "usb3_port_number" = "2" - # SBU is fixed, HSL follows CC - register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on - probe DB_USB USB4_GEN2 + device generic 1 alias conn1 on end + end + end + end + end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port2 on probe DB_USB USB3_ACTIVE - probe DB_USB USB4_GEN3 probe DB_USB USB3_NO_A + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 end end - chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" - # SBU & HSL follow CC - device generic 1 on + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on + probe DB_USB USB3_ACTIVE probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 end end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port4 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_NO_A + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port2 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port3 on end + end end end end diff --git a/src/mainboard/google/volteer/variants/volteer2/gpio.c b/src/mainboard/google/volteer/variants/volteer2/gpio.c index 6c67fc216e..069b2f0a98 100644 --- a/src/mainboard/google/volteer/variants/volteer2/gpio.c +++ b/src/mainboard/google/volteer/variants/volteer2/gpio.c @@ -243,6 +243,11 @@ static const struct pad_config early_gpio_table[] = { /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H11, 1, DEEP), + + /* The two signals used for I2C communication with Ti50 on the + * volteer2_ti50 variant. */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* PCH_I2C1_TOUCH_USI_SCL */ }; const struct pad_config *variant_override_gpio_table(size_t *num) diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 2db1f087ef..bb4db53e32 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -4,6 +4,52 @@ chip soc/intel/tigerlake register "IomTypeCPortPadCfg[1]" = "0x090E000D" register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + # Depending on whether we use I2C bus 1 or SPI bus 0 for TPM + # communication, that one needs early initialization. + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = CONFIG(MAINBOARD_HAS_SPI_TPM_CR50), + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .early_init = CONFIG(MAINBOARD_HAS_I2C_TPM_CR50), + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + }" register "HybridStorageMode" = "1" @@ -55,7 +101,7 @@ chip soc/intel/tigerlake TEMP_PCT(42, 36),}}}" device generic 0 on end end - end # DPTF 0x9A03 + end device ref ipu on end # IPU 0x9A19 device ref i2c0 on chip drivers/i2c/generic @@ -216,6 +262,13 @@ chip soc/intel/tigerlake end end end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -225,28 +278,116 @@ chip soc/intel/tigerlake register "usb2_port_number" = "9" register "usb3_port_number" = "1" # SBU & HSL follow CC - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "4" register "usb3_port_number" = "2" - # SBU is fixed, HSL follows CC - register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on - probe DB_USB USB4_GEN2 + device generic 1 alias conn1 on end + end + end + end + end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port2 on probe DB_USB USB3_ACTIVE - probe DB_USB USB4_GEN3 probe DB_USB USB3_NO_A + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 end end - chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" - # SBU & HSL follow CC - device generic 1 on + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on + probe DB_USB USB3_ACTIVE probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 end end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port4 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_NO_A + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port2 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port3 on end + end end end end diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index e8be8e3eb3..ef5e0b7987 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -187,6 +187,13 @@ chip soc/intel/tigerlake device i2c 15 on end end end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -197,14 +204,77 @@ chip soc/intel/tigerlake register "usb3_port_number" = "1" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "4" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end + end + end + end + end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port2 on + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port2 on + probe DB_USB USB4_GEN3 + end end end end diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index f0d9a2869d..9503d3762c 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -28,6 +29,12 @@ #include #include +#define METHOD_BACKLIGHT_ENABLE "\\_SB.BKEN" +#define METHOD_BACKLIGHT_DISABLE "\\_SB.BKDS" +#define METHOD_MAINBOARD_INI "\\_SB.MINI" +#define METHOD_MAINBOARD_WAK "\\_SB.MWAK" +#define METHOD_MAINBOARD_PTS "\\_SB.MPTS" + /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. * This table is responsible for physically routing the PIC and @@ -175,6 +182,50 @@ void mainboard_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, variant_get_dxio_ddi_descriptors(dxio_descs, dxio_num, ddi_descs, ddi_num); } +static void mainboard_write_blken(void) +{ + acpigen_write_method(METHOD_BACKLIGHT_ENABLE, 0); + acpigen_soc_clear_tx_gpio(GPIO_85); + acpigen_pop_len(); +} + +static void mainboard_write_blkdis(void) +{ + acpigen_write_method(METHOD_BACKLIGHT_DISABLE, 0); + acpigen_soc_set_tx_gpio(GPIO_85); + acpigen_pop_len(); +} + +static void mainboard_write_mini(void) +{ + acpigen_write_method(METHOD_MAINBOARD_INI, 0); + acpigen_emit_namestring(METHOD_BACKLIGHT_ENABLE); + acpigen_pop_len(); +} + +static void mainboard_write_mwak(void) +{ + acpigen_write_method(METHOD_MAINBOARD_WAK, 0); + acpigen_emit_namestring(METHOD_BACKLIGHT_ENABLE); + acpigen_pop_len(); +} + +static void mainboard_write_mpts(void) +{ + acpigen_write_method(METHOD_MAINBOARD_PTS, 0); + acpigen_emit_namestring(METHOD_BACKLIGHT_DISABLE); + acpigen_pop_len(); +} + +static void mainboard_fill_ssdt(const struct device *dev) +{ + mainboard_write_blken(); + mainboard_write_blkdis(); + mainboard_write_mini(); + mainboard_write_mpts(); + mainboard_write_mwak(); +} + /************************************************* * Dedicated mainboard function *************************************************/ @@ -186,6 +237,8 @@ static void zork_enable(struct device *dev) pirq_setup(); dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; + dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt; + } static void mainboard_final(void *chip_info) diff --git a/src/mainboard/google/zork/smihandler.c b/src/mainboard/google/zork/smihandler.c index 6ef2704de1..1c26d45bca 100644 --- a/src/mainboard/google/zork/smihandler.c +++ b/src/mainboard/google/zork/smihandler.c @@ -34,10 +34,5 @@ int mainboard_smi_apmc(u8 apmc) chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); - /* Temporary fix - Needs to go into ACPI instead */ - /* Turn on the backlight when we go to ACPI mode */ - if (apmc == APM_CNT_ACPI_ENABLE) - gpio_set(GPIO_85, 0); - return 0; } diff --git a/src/mainboard/google/zork/variants/baseboard/helpers.c b/src/mainboard/google/zork/variants/baseboard/helpers.c index cc07fe18d6..70710351d2 100644 --- a/src/mainboard/google/zork/variants/baseboard/helpers.c +++ b/src/mainboard/google/zork/variants/baseboard/helpers.c @@ -48,9 +48,9 @@ enum { FW_CONFIG_SHIFT_FAN = 27, }; -static int get_fw_config(uint32_t *val) +static int get_fw_config(uint64_t *val) { - static uint32_t known_value; + static uint64_t known_value; if (known_value) { *val = known_value; @@ -67,9 +67,9 @@ static int get_fw_config(uint32_t *val) return 0; } -static unsigned int extract_field(uint32_t mask, int shift) +static unsigned int extract_field(uint64_t mask, int shift) { - uint32_t fw_config; + uint64_t fw_config; /* On errors nothing is assumed to be set. */ if (get_fw_config(&fw_config)) diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index a61c027156..bca556cbee 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -105,14 +105,31 @@ chip soc/amd/picasso register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" register "generic.enable_delay_ms" = "10" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" - register "generic.reset_off_delay_ms" = "1" - register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "2" + register "generic.reset_delay_ms" = "20" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" - register "generic.stop_off_delay_ms" = "1" + register "generic.stop_delay_ms" = "100" + register "generic.stop_off_delay_ms" = "2" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" + register "enable_delay_ms" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + register "reset_delay_ms" = "20" + register "reset_off_delay_ms" = "2" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" + register "stop_off_delay_ms" = "2" + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + device i2c 10 on end + end chip drivers/generic/gpio_keys register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPIO_4)" diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 9d7cc9118f..209ee6a222 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -51,12 +51,10 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) switch (board_id) { case ADL_P_DDR4_1: case ADL_P_DDR4_2: - mupd->FspmConfig.DqPinsInterleaved = 1; memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_spd_info, half_populated); break; case ADL_P_LP4_1: case ADL_P_LP4_2: - mupd->FspmConfig.DqPinsInterleaved = 0; memcfg_init(&mupd->FspmConfig, mem_config, &lpddr4_spd_info, half_populated); break; default: diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index 73055010ca..ea75d5d161 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -216,10 +216,12 @@ chip soc/intel/alderlake end # USB3.1 xHCI device pci 14.1 off end # USB3.1 xDCI device pci 14.2 off end # Shared RAM - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi: WiFi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi: WiFi device pci 15.0 on end # I2C0 device pci 15.1 on end # I2C1 device pci 15.2 on end # I2C2 diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c index f8b366049f..c730b995bc 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c @@ -5,7 +5,21 @@ #include #include -static const struct mb_cfg mem_config = { +static const struct mb_cfg ddr4_mem_config = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + /* Baseboard Rcomp target values */ + .rcomp_targets = {40, 30, 33, 33, 30}, + + .dq_pins_interleaved = true, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + +static const struct mb_cfg lpddr4_mem_config = { /* DQ byte map */ .dq_map = { { 0, 2, 3, 1, 6, 7, 5, 4, /* Byte 0 */ @@ -33,13 +47,7 @@ static const struct mb_cfg mem_config = { { 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 } }, - /* Baseboard uses only 100ohm Rcomp resistors */ - .rcomp_resistor = {100, 100, 100}, - - /* - * Baseboard Rcomp target values. - */ - .rcomp_targets = {40, 30, 33, 33, 30}, + .dq_pins_interleaved = false, .ect = true, /* Early Command Training */ @@ -48,5 +56,12 @@ static const struct mb_cfg mem_config = { const struct mb_cfg *variant_memory_params(void) { - return &mem_config; + int board_id = get_board_id(); + + if (board_id == ADL_P_LP4_1 || board_id == ADL_P_LP4_2) + return &lpddr4_mem_config; + else if (board_id == ADL_P_DDR4_1 || board_id == ADL_P_DDR4_2) + return &ddr4_mem_config; + + die("unsupported board id : 0x%x\n", board_id); } diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index 1110bc1e32..535ae49da6 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -91,10 +91,12 @@ chip soc/intel/cannonlake device pci 12.6 off end # GSPI #2 device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 on end # SDCard device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index 42023149a9..bbdd38b534 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -72,10 +72,12 @@ chip soc/intel/cannonlake device pci 12.6 off end # GSPI #2 device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 on end # SDCard device pci 15.0 on chip drivers/i2c/hid diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb index 77e475aa9d..af5fc2de94 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb @@ -92,10 +92,12 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[10]" = "10" device domain 0 on - chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 on end # I2C #2 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb index 433a03a9e7..f4b82ab657 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb @@ -61,10 +61,12 @@ chip soc/intel/cannonlake }" device domain 0 on - chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb index 560a7c2dad..55b340caf3 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb @@ -80,10 +80,12 @@ chip soc/intel/cannonlake register "sdcard_cd_gpio" = "GPP_G5" device domain 0 on - chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 on end # SDCard device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb index 9592e90b5d..dc8874afe6 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb @@ -65,10 +65,12 @@ chip soc/intel/cannonlake register "sdcard_cd_gpio" = "GPP_G5" device domain 0 on - chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb index 1215628dbc..10284d411f 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb @@ -277,10 +277,12 @@ chip soc/intel/icelake end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 on end # SDCard device pci 15.0 on chip drivers/i2c/hid diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb index e8c6e8f5c4..cbee3ce65d 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb @@ -277,10 +277,12 @@ chip soc/intel/icelake end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 on end # SDCard device pci 15.0 on chip drivers/i2c/hid diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 61a5e70695..06cf4f6a63 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -296,10 +296,12 @@ chip soc/intel/jasperlake end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 on end # SDCard device pci 15.0 on chip drivers/i2c/max98373 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index de93c99aa2..57f36ab9d9 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -227,10 +227,12 @@ chip soc/intel/tigerlake device pci 14.0 on end # USB3.1 xHCI 0xA0ED device pci 14.1 on end # USB3.1 xDCI 0xA0EE device pci 14.2 on end # Shared RAM 0xA0EF - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi: WiFi 0xA0F0 - A0F3 device pci 15.0 on # I2C0 0xA0E8 chip drivers/i2c/generic @@ -306,6 +308,8 @@ chip soc/intel/tigerlake end # GSPI1 0xA0AB device pci 1f.0 on chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] device pnp 0c09.0 on end end end # eSPI 0xA080 - A09F @@ -320,14 +324,14 @@ chip soc/intel/tigerlake register "usb3_port_number" = "3" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "7" register "usb3_port_number" = "4" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 4078894bfd..56c3afa406 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -231,10 +231,12 @@ chip soc/intel/tigerlake device pci 14.0 on end # USB3.1 xHCI 0xA0ED device pci 14.1 on end # USB3.1 xDCI 0xA0EE device pci 14.2 on end # Shared RAM 0xA0EF - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi: WiFi 0xA0F0 - A0F3 device pci 15.0 on # I2C0 0xA0E8 chip drivers/i2c/generic @@ -310,6 +312,8 @@ chip soc/intel/tigerlake end # GSPI1 0xA0AB device pci 1f.0 on chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] device pnp 0c09.0 on end end end # eSPI 0xA080 - A09F @@ -324,14 +328,14 @@ chip soc/intel/tigerlake register "usb3_port_number" = "3" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "5" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index bff39b72eb..29041aaeca 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -9,15 +9,6 @@ chip soc/intel/broadwell # Enable DVI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - register "alt_gp_smi_en" = "0x0000" - register "gpe0_en_1" = "0x00000400" - register "gpe0_en_2" = "0x00000000" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x2" - register "sio_acpi_mode" = "1" - device cpu_cluster 0 on device lapic 0 on end end @@ -25,33 +16,45 @@ chip soc/intel/broadwell device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 - device pci 1d.0 off end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal + + chip soc/intel/broadwell/pch + register "alt_gp_smi_en" = "0x0000" + register "gpe0_en_1" = "0x00000400" + register "gpe0_en_2" = "0x00000000" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "sata_port_map" = "0x2" + register "sio_acpi_mode" = "1" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1d.0 off end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal + end end end diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index d5b7b42b13..ddc716093f 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -11,12 +11,8 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - // platform ACPI tables #include "acpi/platform.asl" - - // global NVS and variables #include - #include #include } diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 04e6774f65..2c0c26a92f 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -164,10 +164,12 @@ chip soc/intel/cannonlake device pci 02.0 on # Integrated Graphics Device register "InternalGfx" = "1" end - chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi # This device does not have any function on CNP-H, but it needs # to be here so that the resource allocator is aware of UART 2. diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index b7c6fe58ae..0d0fc720f7 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -16,10 +16,6 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms - # EC host command ranges are in 0x380-0x383 & 0x80-0x8f - register "gen1_dec" = "0x00000381" - register "gen2_dec" = "0x000c0081" - device cpu_cluster 0 on device lapic 0 on end end @@ -27,33 +23,40 @@ chip soc/intel/broadwell device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 off end # Serial I/O DMA - device pci 15.1 off end # I2C0 - device pci 15.2 off end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - LAN - device pci 1c.3 on end # PCIe Port #4 - WiFi - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe - device pci 1d.0 off end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 off end # Thermal + + chip soc/intel/broadwell/pch + # EC host command ranges are in 0x380-0x383 & 0x80-0x8f + register "gen1_dec" = "0x00000381" + register "gen2_dec" = "0x000c0081" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 - LAN + device pci 1c.3 on end # PCIe Port #4 - WiFi + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe + device pci 1d.0 off end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 off end # Thermal + end end end diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb index d3d0ae72d0..256077cbd9 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb @@ -1,14 +1,16 @@ chip soc/intel/broadwell - # Port 0 is HDD - # Port 3 is M.2 NGFF - register "sata_port_map" = "0x9" - - # Port tuning for link stability - register "sata_port0_gen3_dtle" = "9" - register "sata_port3_gen3_dtle" = "9" - device domain 0 on - device pci 1c.2 on end # PCIe Port #3 - LAN + chip soc/intel/broadwell/pch + # Port 0 is HDD + # Port 3 is M.2 NGFF + register "sata_port_map" = "0x9" + + # Port tuning for link stability + register "sata_port0_gen3_dtle" = "9" + register "sata_port3_gen3_dtle" = "9" + + device pci 1c.2 on end # PCIe Port #3 - LAN + end end end diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb index c0c8d0360f..d88c19c26a 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb @@ -1,14 +1,16 @@ chip soc/intel/broadwell - # Port 0 is HDD - # Port 1 is M.2 NGFF - register "sata_port_map" = "0x3" - - # Port tuning for link stability - register "sata_port0_gen3_dtle" = "7" - register "sata_port1_gen3_dtle" = "9" - device domain 0 on - device pci 1d.0 on end # USB2 EHCI + chip soc/intel/broadwell/pch + # Port 0 is HDD + # Port 1 is M.2 NGFF + register "sata_port_map" = "0x3" + + # Port tuning for link stability + register "sata_port0_gen3_dtle" = "7" + register "sata_port1_gen3_dtle" = "9" + + device pci 1d.0 on end # USB2 EHCI + end end end diff --git a/src/mainboard/system76/lemp10/romstage.c b/src/mainboard/system76/lemp10/romstage.c index e9ed4cf5e2..1866527ba7 100644 --- a/src/mainboard/system76/lemp10/romstage.c +++ b/src/mainboard/system76/lemp10/romstage.c @@ -16,12 +16,13 @@ static const struct mb_ddr4_cfg board_cfg = { }; static const struct spd_info spd = { - .topology = MIXED, + //.topology = MIXED, + .topology = MEMORY_DOWN, .md_spd_loc = SPD_CBFS, .cbfs_index = 0, - .smbus_info[1] = { - .addr_dimm0 = 0x52, - }, + //.smbus_info[1] = { + // .addr_dimm0 = 0x52, + //}, }; void mainboard_memory_init_params(FSPM_UPD *mupd) { diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 92e55c4246..762682f4a4 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -196,10 +196,12 @@ chip soc/intel/cannonlake device pci 13.0 off end # Integrated Sensor Hub device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - #chip drivers/intel/wifi - # register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - #end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 off end # SDCard device pci 15.0 on chip drivers/i2c/hid diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 1600a42625..b95b3fe3c9 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -22,10 +22,10 @@ void intel_northbridge_haswell_finalize_smm(void) MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */ - MCHBAR32_OR(DMIVCLIM, 1UL << 31); + MCHBAR32_OR(DMIVCLIM, 1 << 31); MCHBAR32_OR(CRDTLCK, 1 << 0); MCHBAR32_OR(MCARBLCK, 1 << 0); - MCHBAR32_OR(REQLIM, 1UL << 31); + MCHBAR32_OR(REQLIM, 1 << 31); MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 66c8d2d40d..0bca230b64 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -196,7 +196,7 @@ static void gma_pm_init_pre_vbios(struct device *dev) gtt_write_regs(haswell_gt_setup); /* Wait for Mailbox Ready */ - gtt_poll(0x138124, (1UL << 31), (0UL << 31)); + gtt_poll(0x138124, (1 << 31), (0 << 31)); /* Mailbox Data - RC6 VIDS */ gtt_write(0x138128, 0x00000000); @@ -205,7 +205,7 @@ static void gma_pm_init_pre_vbios(struct device *dev) gtt_write(0x138124, 0x80000004); /* Wait for Mailbox Ready */ - gtt_poll(0x138124, (1UL << 31), (0UL << 31)); + gtt_poll(0x138124, (1 << 31), (0 << 31)); /* Enable PM Interrupts */ gtt_write(GEN6_PMIER, GEN6_PM_MBOX_EVENT | GEN6_PM_THERMAL_EVENT | diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 88ccd710f3..2d19ccdda5 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -31,18 +31,18 @@ static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 * switch ((pciexbar_reg >> 1) & 3) { case 0: /* 256MB */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28); *base = pciexbar_reg & mask; *len = 256 * 1024 * 1024; return 1; case 1: /* 128M */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28); mask |= (1 << 27); *base = pciexbar_reg & mask; *len = 128 * 1024 * 1024; return 1; case 2: /* 64M */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28); mask |= (1 << 27) | (1 << 26); *base = pciexbar_reg & mask; *len = 64 * 1024 * 1024; diff --git a/src/soc/amd/common/acpi/platform.asl b/src/soc/amd/common/acpi/platform.asl new file mode 100644 index 0000000000..6db12e3d47 --- /dev/null +++ b/src/soc/amd/common/acpi/platform.asl @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Callback methods to be implemented by mainboard */ +External(\_SB.MPTS, MethodObj) +External(\_SB.MWAK, MethodObj) +External(\_SB.MINI, MethodObj) + +Scope (\_SB){ + /* Platform initialization methods */ + Method (_INI, 0, NotSerialized) + { + If (CondRefOf (\_SB.MINI)) { + \_SB.MINI() + } + } +} + +/* Platform-wide wake methods */ +Method (\_WAK, 1, NotSerialized) +{ + If (CondRefOf (\_SB.MWAK)) { + \_SB.MWAK() + } + Return (Package (){ 0, 0 }) +} + +/* Platform-wide Put To Sleep (suspend) methods */ +Method (\_PTS, 1, NotSerialized) +{ + If (CondRefOf (\_SB.MPTS)) { + \_SB.MPTS() + } +} diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 6a5b93244d..605b0eacea 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -24,7 +24,7 @@ config CPU_SPECIFIC_OPTIONS select IOAPIC select HAVE_EM100_SUPPORT select HAVE_USBDEBUG_OPTIONS - select TSC_MONOTONIC_TIMER + select COLLECT_TIMESTAMPS_NO_TSC select SOC_AMD_COMMON_BLOCK_SPI select TSC_SYNC_LFENCE select UDELAY_TSC @@ -446,9 +446,9 @@ comment "AMD Firmware Directory Table set to location for 8MB ROM" comment "AMD Firmware Directory Table set to location for 16MB ROM" depends on AMD_FWM_POSITION_INDEX = 5 -config AMD_PUBKEY_FILE +config AMDFW_CONFIG_FILE string - default "3rdparty/amd_blobs/picasso/PSP/AmdPubKeyRV.bin" + default "src/soc/amd/picasso/fw.cfg" config USE_PSPSECUREOS bool @@ -487,16 +487,6 @@ config PSP_WHITELIST_FILE depends on HAVE_PSP_WHITELIST_FILE default "3rdparty/amd_blobs/picasso/PSP/wtl-rvn.sbin" -config PSP_BOOTLOADER_FILE - string "Specify the PSP Bootloader file path" - default "3rdparty/amd_blobs/picasso/PSP/PspBootLoader_WL_RV.sbin" if HAVE_PSP_WHITELIST_FILE - default "3rdparty/amd_blobs/picasso/PSP/PspBootLoader_prod_RV.sbin" - help - Supply the name of the PSP bootloader file. - - Note that this option may conflict with the whitelist file if a - different PSP bootloader binary is specified. - config PSP_SHAREDMEM_SIZE hex "Maximum size of shared memory area" default 0x3000 if VBOOT diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 514b313a6d..f0c6ae52f2 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -18,6 +18,7 @@ bootblock-y += southbridge.c bootblock-y += i2c.c bootblock-y += uart.c bootblock-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c +bootblock-y += monotonic_timer.c bootblock-y += tsc_freq.c bootblock-y += gpio.c bootblock-y += smi_util.c @@ -34,6 +35,7 @@ romstage-y += reset.c romstage-y += memmap.c romstage-y += uart.c romstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c +romstage-y += monotonic_timer.c romstage-y += tsc_freq.c romstage-y += aoac.c romstage-y += southbridge.c @@ -49,6 +51,7 @@ verstage-y += aoac.c verstage_x86-y += gpio.c verstage_x86-y += uart.c verstage_x86-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c +verstage_x86-y += monotonic_timer.c verstage_x86-y += tsc_freq.c verstage_x86-y += reset.c @@ -72,6 +75,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c ramstage-y += uart.c ramstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c +ramstage-y += monotonic_timer.c ramstage-y += tsc_freq.c ramstage-y += finalize.c ramstage-y += soc_util.c @@ -86,6 +90,7 @@ ramstage-y += dmi.c smm-y += smihandler.c smm-y += smi_util.c +smm-y += monotonic_timer.c smm-y += tsc_freq.c ifeq ($(CONFIG_DEBUG_SMI),y) smm-y += uart.c @@ -125,77 +130,35 @@ PICASSO_FWM_POSITION=$(call int-add, \ # Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). # -# type = 0x0 -FIRMWARE_LOCATE=$(realpath $(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)))) - -# type = 0x1 -ifeq ($(CONFIG_PSP_BOOTLOADER_FILE),) -$(error CONFIG_PSP_BOOTLOADER_FILE was not defined) -endif -PSPBTLDR_FILE=$(realpath $(call strip_quotes, $(CONFIG_PSP_BOOTLOADER_FILE))) -$(info Adding PSP $(shell dd if=$(PSPBTLDR_FILE) | md5sum)) - -# types = 0x8 and 0x12 -PSP_SMUFW1_SUB1_FILE=$(FIRMWARE_LOCATE)/SmuFirmwareRV2.csbin -PSP_SMUFW1_SUB2_FILE=$(FIRMWARE_LOCATE)/SmuFirmwarePCO.csbin -PSP_SMUFW2_SUB1_FILE=$(FIRMWARE_LOCATE)/SmuFirmware2RV2.csbin -PSP_SMUFW2_SUB2_FILE=$(FIRMWARE_LOCATE)/SmuFirmware2PCO.csbin +FIRMWARE_LOCATE=$(shell grep -e FIRMWARE_LOCATE $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) -# type = 0x9 -PSP_SEC_DBG_KEY_FILE=$(FIRMWARE_LOCATE)/RavenSecureDebug_PublicKey.bin -# type = 0x13 -PSP_SEC_DEBUG_FILE=$(FIRMWARE_LOCATE)/secure_unlock_prod_RV.sbin # Enable secure debug unlock PSP_SOFTFUSE_BITS += 0 -PSP_TOKEN_UNLOCK="--token-unlock" +OPT_TOKEN_UNLOCK="--token-unlock" endif ifeq ($(CONFIG_USE_PSPSECUREOS),y) # types = 0x2 -PSPSECUREOS_FILE=$(FIRMWARE_LOCATE)/psp_os_combined_prod_RV.sbin +OPT_PSP_USE_PSPSECUREOS="--use-pspsecureos" endif -# type = 0x21 -PSP_IKEK_FILE=$(FIRMWARE_LOCATE)/PspIkekRV.bin - -# type = 0x24 -PSP_SECG1_FILE=$(FIRMWARE_LOCATE)/security_policy_RV2_FP5_AM4.sbin -PSP_SECG2_FILE=$(FIRMWARE_LOCATE)/security_policy_PCO_FP5_AM4.sbin ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) -# type = 0x25 -PSP_MP2FW1_FILE=$(FIRMWARE_LOCATE)/MP2I2CFWRV2.sbin -PSP_MP2FW2_FILE=$(FIRMWARE_LOCATE)/MP2I2CFWPCO.sbin -# BIOS type = 0x6a -PSP_MP2CFG_FILE=$(FIRMWARE_LOCATE)/MP2FWConfig.sbin +OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" else # Disable MP2 firmware loading PSP_SOFTFUSE_BITS += 29 endif -# type = 0x28 -PSP_DRIVERS_FILE=$(FIRMWARE_LOCATE)/drv_sys_prod_RV.sbin - ifeq ($(CONFIG_PSP_LOAD_S0I3_FW),y) -PSP_S0I3_FILE=$(FIRMWARE_LOCATE)/dr_agesa_prod_RV.sbin +OPT_PSP_LOAD_S0I3_FW="--load-s0i3" endif -# types = 0x30 - 0x37 -PSP_ABL0_FILE=$(FIRMWARE_LOCATE)/AgesaBootloader0_prod_RV.csbin -PSP_ABL1_FILE=$(FIRMWARE_LOCATE)/AgesaBootloader1_prod_RV.csbin -PSP_ABL2_FILE=$(FIRMWARE_LOCATE)/AgesaBootloader2_prod_RV.csbin -PSP_ABL3_FILE=$(FIRMWARE_LOCATE)/AgesaBootloader3_prod_RV.csbin -PSP_ABL4_FILE=$(FIRMWARE_LOCATE)/AgesaBootloader4_prod_RV.csbin -PSP_ABL5_FILE=$(FIRMWARE_LOCATE)/AgesaBootloader5_prod_RV.csbin -PSP_ABL6_FILE=$(FIRMWARE_LOCATE)/AgesaBootloader6_prod_RV.csbin -PSP_ABL7_FILE=$(FIRMWARE_LOCATE)/AgesaBootloader7_prod_RV.csbin - # type = 0x3a ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) endif - # # BIOS Directory Table items - proper ordering is managed by amdfwtool # @@ -216,16 +179,6 @@ PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | a APOB_NV_SIZE=$(shell grep "FMAP_SECTION_RW_MRC_CACHE_SIZE" $(obj)/fmap_config.h | awk '{print $$(NF)}') APOB_NV_BASE=$(shell grep "FMAP_SECTION_RW_MRC_CACHE_START" $(obj)/fmap_config.h | awk '{print $$(NF)}') -# type2 = 0x64, 0x65 -PSP_PMUI_FILE1=$(FIRMWARE_LOCATE)/Appb_Rv_1D_Ddr4_Udimm_Imem.csbin -PSP_PMUI_FILE2=$(FIRMWARE_LOCATE)/Appb_Rv_2D_Ddr4_Imem.csbin -PSP_PMUI_FILE3=$(FIRMWARE_LOCATE)/Appb_Rv2_1D_ddr4_Udimm_Imem.csbin -PSP_PMUI_FILE4=$(FIRMWARE_LOCATE)/Appb_Rv2_2D_ddr4_Udimm_Imem.csbin -PSP_PMUD_FILE1=$(FIRMWARE_LOCATE)/Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin -PSP_PMUD_FILE2=$(FIRMWARE_LOCATE)/Appb_Rv_2D_Ddr4_Dmem.csbin -PSP_PMUD_FILE3=$(FIRMWARE_LOCATE)/Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin -PSP_PMUD_FILE4=$(FIRMWARE_LOCATE)/Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin - # type = 0x66 PSP_UCODE_FILE1=$(FIRMWARE_LOCATE)/UcodePatch_PCO_B1.bin PSP_UCODE_FILE2=$(FIRMWARE_LOCATE)/UcodePatch_PCO_B0.bin @@ -259,33 +212,6 @@ PSP_SOFTFUSE=$(shell A=$(call int-add, \ add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) -OPT_AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey) -OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(PSPBTLDR_FILE), --bootloader) -OPT_SMUFW1_SUB1_FILE=$(call add_opt_prefix, $(PSP_SMUFW1_SUB1_FILE), --subprogram 1 --smufirmware) -OPT_SMUFW1_SUB2_FILE=$(call add_opt_prefix, $(PSP_SMUFW1_SUB2_FILE), --subprogram 2 --smufirmware) -OPT_SMUFW2_SUB1_FILE=$(call add_opt_prefix, $(PSP_SMUFW2_SUB1_FILE), --subprogram 1 --smufirmware2) -OPT_SMUFW2_SUB2_FILE=$(call add_opt_prefix, $(PSP_SMUFW2_SUB2_FILE), --subprogram 2 --smufirmware2) -OPT_PSP_SEC_DBG_KEY_FILE=$(call add_opt_prefix, $(PSP_SEC_DBG_KEY_FILE), --securedebug) -OPT_TOKEN_UNLOCK=$(call add_opt_prefix, $(PSP_TOKEN_UNLOCK), "") -OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) -OPT_PSPSECUREOS_FILE=$(call add_opt_prefix, $(PSPSECUREOS_FILE), --secureos) -OPT_SEC_DEBUG_FILE=$(call add_opt_prefix, $(PSP_SEC_DEBUG_FILE), --secdebug) -OPT_IKEK_FILE=$(call add_opt_prefix, $(PSP_IKEK_FILE), --ikek) -OPT_SECG1_FILE=$(call add_opt_prefix, $(PSP_SECG1_FILE), --subprog 1 --sec-gasket) -OPT_SECG2_FILE=$(call add_opt_prefix, $(PSP_SECG2_FILE), --subprog 2 --sec-gasket) -OPT_MP2FW1_FILE=$(call add_opt_prefix, $(PSP_MP2FW1_FILE), --subprog 1 --mp2-fw) -OPT_MP2FW2_FILE=$(call add_opt_prefix, $(PSP_MP2FW2_FILE), --subprog 2 --mp2-fw) -OPT_DRIVERS_FILE=$(call add_opt_prefix, $(PSP_DRIVERS_FILE), --drv-entry-pts) -OPT_PSP_S0I3_FILE=$(call add_opt_prefix, $(PSP_S0I3_FILE), --s0i3drv) -OPT_ABL0_FILE=$(call add_opt_prefix, $(PSP_ABL0_FILE), --abl-image) -OPT_ABL1_FILE=$(call add_opt_prefix, $(PSP_ABL1_FILE), --abl-image) -OPT_ABL2_FILE=$(call add_opt_prefix, $(PSP_ABL2_FILE), --abl-image) -OPT_ABL3_FILE=$(call add_opt_prefix, $(PSP_ABL3_FILE), --abl-image) -OPT_ABL4_FILE=$(call add_opt_prefix, $(PSP_ABL4_FILE), --abl-image) -OPT_ABL5_FILE=$(call add_opt_prefix, $(PSP_ABL5_FILE), --abl-image) -OPT_ABL6_FILE=$(call add_opt_prefix, $(PSP_ABL6_FILE), --abl-image) -OPT_ABL7_FILE=$(call add_opt_prefix, $(PSP_ABL7_FILE), --abl-image) -OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) @@ -297,15 +223,7 @@ OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) -OPT_PSP_PMUI_FILE1=$(call add_opt_prefix, $(PSP_PMUI_FILE1), --subprogram 0 --instance 1 --pmu-inst) -OPT_PSP_PMUI_FILE2=$(call add_opt_prefix, $(PSP_PMUI_FILE2), --subprogram 0 --instance 4 --pmu-inst) -OPT_PSP_PMUI_FILE3=$(call add_opt_prefix, $(PSP_PMUI_FILE3), --subprogram 1 --instance 1 --pmu-inst) -OPT_PSP_PMUI_FILE4=$(call add_opt_prefix, $(PSP_PMUI_FILE4), --subprogram 1 --instance 4 --pmu-inst) -OPT_PSP_PMUD_FILE1=$(call add_opt_prefix, $(PSP_PMUD_FILE1), --subprogram 0 --instance 1 --pmu-data) -OPT_PSP_PMUD_FILE2=$(call add_opt_prefix, $(PSP_PMUD_FILE2), --subprogram 0 --instance 4 --pmu-data) -OPT_PSP_PMUD_FILE3=$(call add_opt_prefix, $(PSP_PMUD_FILE3), --subprogram 1 --instance 1 --pmu-data) -OPT_PSP_PMUD_FILE4=$(call add_opt_prefix, $(PSP_PMUD_FILE4), --subprogram 1 --instance 4 --pmu-data) -OPT_MP2CFG_FILE=$(call add_opt_prefix, $(PSP_MP2CFG_FILE), --mp2-config) + OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) @@ -314,49 +232,28 @@ OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi- OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) +OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) + ifeq ($(CONFIG_VBOOT),) OPT_APOB0_NV_SIZE=$(OPT_APOB_NV_SIZE) OPT_APOB0_NV_BASE=$(OPT_APOB_NV_BASE) endif -AMDFW_COMMON_ARGS=$(OPT_AMD_PUBKEY_FILE) \ - $(OPT_PSPSECUREOS_FILE) \ - $(OPT_PSP_SEC_DBG_KEY_FILE) \ - $(OPT_SMUFW1_SUB2_FILE) \ - $(OPT_SMUFW2_SUB2_FILE) \ - $(OPT_SMUFW1_SUB1_FILE) \ - $(OPT_SMUFW2_SUB1_FILE) \ - $(OPT_PSP_APCB_FILES) \ +OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) + +# Add all the files listed in the config file +DEP_FILES=$(shell $(AMDFWTOOL) --config $(CONFIG_AMDFW_CONFIG_FILE) --depend) + +AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_APOB_ADDR) \ $(OPT_PSP_BIOSBIN_FILE) \ $(OPT_PSP_BIOSBIN_DEST) \ $(OPT_PSP_BIOSBIN_SIZE) \ $(OPT_PSP_SOFTFUSE) \ - $(OPT_PSP_PMUI_FILE1) \ - $(OPT_PSP_PMUI_FILE2) \ - $(OPT_PSP_PMUI_FILE3) \ - $(OPT_PSP_PMUI_FILE4) \ - $(OPT_PSP_PMUD_FILE1) \ - $(OPT_PSP_PMUD_FILE2) \ - $(OPT_PSP_PMUD_FILE3) \ - $(OPT_PSP_PMUD_FILE4) \ - $(OPT_MP2CFG_FILE) \ - $(OPT_ABL0_FILE) \ - $(OPT_ABL1_FILE) \ - $(OPT_ABL2_FILE) \ - $(OPT_ABL3_FILE) \ - $(OPT_ABL4_FILE) \ - $(OPT_ABL5_FILE) \ - $(OPT_ABL6_FILE) \ - $(OPT_ABL7_FILE) \ + $(OPT_PSP_USE_PSPSECUREOS) \ + $(OPT_PSP_LOAD_MP2_FW) \ + $(OPT_PSP_LOAD_S0I3_FW) \ $(OPT_WHITELIST_FILE) \ - $(OPT_SECG1_FILE) \ - $(OPT_SECG2_FILE) \ - $(OPT_MP2FW1_FILE) \ - $(OPT_MP2FW2_FILE) \ - $(OPT_DRIVERS_FILE) \ - $(OPT_PSP_S0I3_FILE) \ - $(OPT_IKEK_FILE) \ $(OPT_SEC_DEBUG_FILE) \ $(OPT_PSP_SHAREDMEM_BASE) \ $(OPT_PSP_SHAREDMEM_SIZE) \ @@ -365,45 +262,15 @@ AMDFW_COMMON_ARGS=$(OPT_AMD_PUBKEY_FILE) \ $(OPT_EFS_SPI_READ_MODE) \ $(OPT_EFS_SPI_SPEED) \ $(OPT_EFS_SPI_MICRON_FLAG) \ + --config $(CONFIG_AMDFW_CONFIG_FILE) \ --soc-name "Picasso" \ --flashsize $(CONFIG_ROM_SIZE) -$(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ - $(call strip_quotes, $(PSPBTLDR_FILE)) \ - $(call strip_quotes, $(PSPSECUREOS_FILE)) \ - $(call strip_quotes, $(PSP_SEC_DBG_KEY_FILE)) \ - $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ - $(call strip_quotes, $(PSP_PMUI_FILE1)) \ - $(call strip_quotes, $(PSP_PMUI_FILE2)) \ - $(call strip_quotes, $(PSP_PMUI_FILE3)) \ - $(call strip_quotes, $(PSP_PMUI_FILE4)) \ - $(call strip_quotes, $(PSP_PMUD_FILE1)) \ - $(call strip_quotes, $(PSP_PMUD_FILE2)) \ - $(call strip_quotes, $(PSP_PMUD_FILE3)) \ - $(call strip_quotes, $(PSP_PMUD_FILE4)) \ - $(call strip_quotes, $(PSP_MP2CFG_FILE)) \ - $(call strip_quotes, $(PSP_SMUFW1_SUB1_FILE)) \ - $(call strip_quotes, $(PSP_SMUFW1_SUB2_FILE)) \ - $(call strip_quotes, $(PSP_SMUFW2_SUB1_FILE)) \ - $(call strip_quotes, $(PSP_SMUFW2_SUB2_FILE)) \ - $(call strip_quotes, $(PSP_ABL0_FILE)) \ - $(call strip_quotes, $(PSP_ABL1_FILE)) \ - $(call strip_quotes, $(PSP_ABL2_FILE)) \ - $(call strip_quotes, $(PSP_ABL3_FILE)) \ - $(call strip_quotes, $(PSP_ABL4_FILE)) \ - $(call strip_quotes, $(PSP_ABL5_FILE)) \ - $(call strip_quotes, $(PSP_ABL6_FILE)) \ - $(call strip_quotes, $(PSP_ABL7_FILE)) \ - $(call strip_quotes, $(PSP_WHITELIST_FILE)) \ - $(call strip_quotes, $(PSP_SECG1_FILE)) \ - $(call strip_quotes, $(PSP_SECG2_FILE)) \ - $(call_strip_quotes, $(PSP_DRIVERS_FILE)) \ - $(call_strip_quotes, $(PSP_S0I3_FILE)) \ - $(call_strip_quotes, $(PSP_IKEK_FILE)) \ - $(call_strip_quotes, $(PSP_SEC_DEBUG_FILE)) \ +$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ $(PSP_VERSTAGE_FILE) \ $(PSP_VERSTAGE_SIG_FILE) \ $$(PSP_APCB_FILES) \ + $(DEP_FILES) \ $(AMDFWTOOL) \ $(obj)/fmap_config.h $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index f627a28039..cbb1b91782 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -22,6 +22,7 @@ Method(_OSC,4) /* 0:14.3 - LPC */ #include +#include Name(CRES, ResourceTemplate() { /* Set the Bus number and Secondary Bus number for the PCI0 device diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index c715324973..4bff042a91 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -10,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -108,12 +110,73 @@ static void write_resume_eip(void) wrmsr(S3_RESUME_EIP_MSR, s3_resume_entry); } +static int transfer_buffer_valid(const struct transfer_info_struct *ptr) +{ + if (ptr->magic_val == TRANSFER_MAGIC_VAL) + return 1; + else + return 0; +} + +static void boot_with_psp_timestamp(uint64_t base_timestamp) +{ + const struct transfer_info_struct *info = (const struct transfer_info_struct *) + (void *)(uintptr_t)_transfer_buffer; + + if (!transfer_buffer_valid(info) || info->timestamp == 0) + return; + + /* + * info->timestamp is PSP's timestamp (in microseconds) + * when x86 processor is released. + */ + uint64_t psp_last_ts = info->timestamp; + + int i; + struct timestamp_table *psp_ts_table = + (struct timestamp_table *)(void *) + ((uintptr_t)_transfer_buffer + info->timestamp_offset); + /* new base_timestamp will be offset for all PSP timestamps. */ + base_timestamp -= psp_last_ts; + + for (i = 0; i < psp_ts_table->num_entries; i++) { + struct timestamp_entry *tse = &psp_ts_table->entries[i]; + /* + * We ignore the time between x86 processor release and bootblock. + * Since timestamp_add subtracts base_time, we first add old base_time + * to make it absolute then add base_timestamp again since + * it'll be a new base_time. + * + * We don't need to convert unit since both PSP and coreboot + * will use 1us granularity. + * + */ + tse->entry_stamp += psp_ts_table->base_time + base_timestamp; + } + + bootblock_main_with_timestamp(base_timestamp, psp_ts_table->entries, + psp_ts_table->num_entries); +} + asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { set_caching(); write_resume_eip(); enable_pci_mmconf(); + /* + * base_timestamp is raw tsc value. We need to divide by tsc_freq_mhz + * when we use micro-seconds granularity for Zork + */ + base_timestamp /= tsc_freq_mhz(); + + if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + boot_with_psp_timestamp(base_timestamp); + + /* + * if VBOOT_STARTS_BEFORE_BOOTBLOCK is not selected or + * previous step did nothing, proceed with normal bootblock main. + */ bootblock_main_with_basetime(base_timestamp); } diff --git a/src/soc/amd/picasso/fw.cfg b/src/soc/amd/picasso/fw.cfg new file mode 100644 index 0000000000..e746d1e299 --- /dev/null +++ b/src/soc/amd/picasso/fw.cfg @@ -0,0 +1,39 @@ +# PSP fw config file + +FIRMWARE_LOCATE 3rdparty/amd_blobs/picasso/PSP + +# type file +AMD_PUBKEY_FILE AmdPubKeyRV.bin +PSPBTLDR_FILE PspBootLoader_prod_RV.sbin +PSPBTLDR_WL_FILE PspBootLoader_WL_RV.sbin +PSP_SMUFW1_SUB1_FILE SmuFirmwareRV2.csbin +PSP_SMUFW1_SUB2_FILE SmuFirmwarePCO.csbin +PSP_SMUFW2_SUB1_FILE SmuFirmware2RV2.csbin +PSP_SMUFW2_SUB2_FILE SmuFirmware2PCO.csbin +PSPSECUREOS_FILE psp_os_combined_prod_RV.sbin +PSP_SEC_DBG_KEY_FILE RavenSecureDebug_PublicKey.bin +PSP_SEC_DEBUG_FILE secure_unlock_prod_RV.sbin +PSP_ABL0_FILE AgesaBootloader0_prod_RV.csbin +PSP_ABL1_FILE AgesaBootloader1_prod_RV.csbin +PSP_ABL2_FILE AgesaBootloader2_prod_RV.csbin +PSP_ABL3_FILE AgesaBootloader3_prod_RV.csbin +PSP_ABL4_FILE AgesaBootloader4_prod_RV.csbin +PSP_ABL5_FILE AgesaBootloader5_prod_RV.csbin +PSP_ABL6_FILE AgesaBootloader6_prod_RV.csbin +PSP_ABL7_FILE AgesaBootloader7_prod_RV.csbin +PSP_IKEK_FILE PspIkekRV.bin +PSP_SECG1_FILE security_policy_RV2_FP5_AM4.sbin +PSP_SECG2_FILE security_policy_PCO_FP5_AM4.sbin +PSP_MP2FW1_FILE MP2I2CFWRV2.sbin +PSP_MP2FW2_FILE MP2I2CFWPCO.sbin +PSP_MP2CFG_FILE MP2FWConfig.sbin +PSP_DRIVERS_FILE drv_sys_prod_RV.sbin +# BDT +PSP_PMUI_FILE1 Appb_Rv_1D_Ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE2 Appb_Rv_2D_Ddr4_Imem.csbin +PSP_PMUI_FILE3 Appb_Rv2_1D_ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE4 Appb_Rv2_2D_ddr4_Udimm_Imem.csbin +PSP_PMUD_FILE1 Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE2 Appb_Rv_2D_Ddr4_Dmem.csbin +PSP_PMUD_FILE3 Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE4 Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index a629fc5541..0529ef6877 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -160,6 +160,7 @@ #define SMI_TIMER_EN (1 << 15) #define SMI_REG_SMITRIG0 0x98 +# define SMITRIG0_PSP (1 << 25) # define SMITRG0_EOS (1 << 28) # define SMI_TIMER_SEL (1 << 29) # define SMITRG0_SMIENB (1 << 31) diff --git a/src/soc/amd/picasso/memlayout_psp_verstage.ld b/src/soc/amd/picasso/memlayout_psp_verstage.ld index 4ad88b1108..e7a6c84000 100644 --- a/src/soc/amd/picasso/memlayout_psp_verstage.ld +++ b/src/soc/amd/picasso/memlayout_psp_verstage.ld @@ -51,16 +51,7 @@ SECTIONS ALIGN_COUNTER(64) _everstage = .; - ALIGN_COUNTER(64) - _transfer_buffer = .; - REGION(transfer_info, ., TRANSFER_INFO_SIZE, 4) - ALIGN_COUNTER(64) - REGION(vboot2_work, ., VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE, 64) - ALIGN_COUNTER(64) - PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) - TIMESTAMP(., TIMESTAMP_BUFFER_SIZE) - FMAP_CACHE(., FMAP_SIZE) - _etransfer_buffer = .; + #include "memlayout_transfer_buffer.inc" PSP_VERSTAGE_TEMP_STACK_END = (PSP_VERSTAGE_TEMP_STACK_START + PSP_VERSTAGE_TEMP_STACK_SIZE ); diff --git a/src/soc/amd/picasso/memlayout_transfer_buffer.inc b/src/soc/amd/picasso/memlayout_transfer_buffer.inc new file mode 100644 index 0000000000..a88e81ac32 --- /dev/null +++ b/src/soc/amd/picasso/memlayout_transfer_buffer.inc @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#if CONFIG(VBOOT) + ALIGN_COUNTER(64) + _transfer_buffer = .; + REGION(transfer_info, ., TRANSFER_INFO_SIZE, 4) + + ALIGN_COUNTER(64) + VBOOT2_WORK(., VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) +#endif + + ALIGN_COUNTER(64) + PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) + TIMESTAMP(., TIMESTAMP_BUFFER_SIZE) + FMAP_CACHE(., FMAP_SIZE) + +#if CONFIG(VBOOT) + _etransfer_buffer = .; +#endif diff --git a/src/soc/amd/picasso/memlayout_x86.ld b/src/soc/amd/picasso/memlayout_x86.ld index 00cdde6488..eeb6dda0cf 100644 --- a/src/soc/amd/picasso/memlayout_x86.ld +++ b/src/soc/amd/picasso/memlayout_x86.ld @@ -75,16 +75,11 @@ SECTIONS #if CONFIG(VBOOT) PSP_SHAREDMEM_DRAM_START(CONFIG_PSP_SHAREDMEM_BASE) - _transfer_buffer = .; - REGION(transfer_info, ., TRANSFER_INFO_SIZE, 4) - VBOOT2_WORK(., VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) #endif - PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) - TIMESTAMP(., TIMESTAMP_BUFFER_SIZE) - FMAP_CACHE(., FMAP_SIZE) +#include "memlayout_transfer_buffer.inc" + #if CONFIG(VBOOT) - _etransfer_buffer = .; PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE) #endif _ = ASSERT((CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10) == CONFIG_X86_RESET_VECTOR, "Reset vector should be -0x10 from end of bootblock"); diff --git a/src/soc/amd/picasso/monotonic_timer.c b/src/soc/amd/picasso/monotonic_timer.c new file mode 100644 index 0000000000..941532cca6 --- /dev/null +++ b/src/soc/amd/picasso/monotonic_timer.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +void timer_monotonic_get(struct mono_time *mt) +{ + mono_time_set_usecs(mt, timestamp_get()); +} + +uint64_t timestamp_get(void) +{ + return rdtscll() / tsc_freq_mhz(); +} diff --git a/src/soc/amd/picasso/psp.c b/src/soc/amd/picasso/psp.c index e40d395637..702b0d9d96 100644 --- a/src/soc/amd/picasso/psp.c +++ b/src/soc/amd/picasso/psp.c @@ -27,11 +27,11 @@ void soc_fill_smm_trig_info(struct smm_trigger_info *trig) if (!trig) return; - trig->address = (uintptr_t)acpimmio_smi + SMI_REG_CONTROL2; + trig->address = (uintptr_t)acpimmio_smi + SMI_REG_SMITRIG0; trig->address_type = SMM_TRIGGER_MEM; trig->value_width = SMM_TRIGGER_DWORD; - trig->value_and_mask = 0xfdffffff; - trig->value_or_mask = 0x02000000; + trig->value_and_mask = ~SMITRIG0_PSP; + trig->value_or_mask = SMITRIG0_PSP; } void soc_fill_smm_reg_info(struct smm_register_info *reg) diff --git a/src/soc/amd/picasso/psp_verstage/fch.c b/src/soc/amd/picasso/psp_verstage/fch.c index 7d0b856545..b813770b4a 100644 --- a/src/soc/amd/picasso/psp_verstage/fch.c +++ b/src/soc/amd/picasso/psp_verstage/fch.c @@ -124,13 +124,13 @@ static uint32_t map_fch_devices(void) bar_map[i].set_bar(bar); } - return BL_UAPP_OK; + return BL_OK; } uint32_t unmap_fch_devices(void) { void *bar; - uint32_t err, rtn = BL_UAPP_OK; + uint32_t err, rtn = BL_OK; unsigned int i; for (i = 0; i < ARRAY_SIZE(bar_map); ++i) { diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 2ef90eb5f4..0e32005fb0 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -190,12 +190,13 @@ config STONEYRIDGE_GEC_FWM_FILE string "GEC firmware path and filename" depends on STONEYRIDGE_GEC_FWM -config AMD_PUBKEY_FILE - string "AMD public Key" +config AMDFW_CONFIG_FILE + string + string "AMD PSP Firmware config file" default "" if !USE_AMD_BLOBS - default "3rdparty/amd_blobs/stoneyridge/PSP/CZ/AmdPubKeyCZ.bin" if AMD_APU_MERLINFALCON - default "3rdparty/amd_blobs/stoneyridge/PSP/ST/AmdPubKeyST.bin" if AMD_APU_PRAIRIEFALCON - default "3rdparty/amd_blobs/stoneyridge/PSP/ST/AmdPubKeyST.bin" if AMD_APU_STONEYRIDGE + default "src/soc/amd/stoneyridge/fw_cz.cfg" if AMD_APU_MERLINFALCON + default "src/soc/amd/stoneyridge/fw_st.cfg" if AMD_APU_PRAIRIEFALCON + default "src/soc/amd/stoneyridge/fw_st.cfg" if AMD_APU_STONEYRIDGE config STONEYRIDGE_SATA_MODE int "SATA Mode" diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 16597e1eda..9211e81476 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -101,7 +101,9 @@ STONEYRIDGE_FWM_POSITION=$(call int-add, \ 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) ### 0 -FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) + +FIRMWARE_LOCATE=$(shell grep -e FIRMWARE_LOCATE $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') + ifneq ($(FIRMWARE_LOCATE),) ifeq ($(CONFIG_AMD_APU_STONEYRIDGE),y) @@ -119,134 +121,47 @@ endif # CONFIG_AMD_APU_PRAIRIEFALCON endif # CONFIG_AMD_APU_MERLINFALCON endif # CONFIG_AMD_APU_STONEYRIDGE -###5 -PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key +add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) -###1 -PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_$(FIRMWARE_TYPE).sbin +OPT_STONEYRIDGE_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE), --xhci) +OPT_STONEYRIDGE_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE), --gec) -###3 -PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_$(FIRMWARE_TYPE).sbin +SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/$(shell awk '($$1=="PSP_SMUFW1_SUB0_FILE") {print $$2}' $(CONFIG_AMDFW_CONFIG_FILE)) +SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/$(shell awk '($$1=="PSP_SMUFW1_SUB1_FILE") {print $$2}' $(CONFIG_AMDFW_CONFIG_FILE)) -###4 -PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin - -###8 - Check for SMU firmware named either *.sbin or *.csbin. Both "signed" and -### "compressed signed" are used by generations supported by this file. -SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware_$(FIRMWARE_TYPE).csbin -SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware_$(FIRMWARE_TYPE)_FN.csbin -ifeq ("$(wildcard $(SMUFWM_FILE))","") -SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin -SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE)_FN.sbin -endif - -###95 -SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin - -###9 -PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key - -ifeq ($(CONFIG_USE_PSPSECUREOS),y) -###2 -PSPSECUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_$(FIRMWARE_TYPE).csbin - -###12 -PSPTRUSTLETS_FILE=$(wildcard $(top)/$(FIRMWARE_LOCATE)/PspTrustlets*_prod_$(FIRMWARE_TYPE).cbin) - -###13 -TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_$(FIRMWARE_TYPE).sbin -endif - -###18- Check for SMU firmware2 named either *.sbin or *.csbin -### TODO: Remove *.sbin section after the blobs repo is updated. -SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).csbin -SMUFIRMWARE2_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE)_FN.csbin -ifeq ("$(wildcard $(SMUFIRMWARE2_FILE))","") -SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).sbin -SMUFIRMWARE2_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE)_FN.sbin -endif +SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/$(shell awk '($$1=="PSP_SMUFW2_SUB0_FILE") {print $$2}' $(CONFIG_AMDFW_CONFIG_FILE)) +SMUFIRMWARE2_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/$(shell awk '($$1=="PSP_SMUFW2_SUB1_FILE") {print $$2}' $(CONFIG_AMDFW_CONFIG_FILE)) ifeq ("$(wildcard $(SMUFWM_FN_FILE))","") SMUFWM_FN_FILE= SMUFIRMWARE2_FN_FILE= endif -add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) - -OPT_STONEYRIDGE_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE), --xhci) -OPT_STONEYRIDGE_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_GEC_FWM_FILEddd), --gec) - -OPT_AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey) -OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(PSPBTLDR_FILE), --bootloader) -OPT_SMUFWM_FILE=$(call add_opt_prefix, $(SMUFWM_FILE), --smufirmware) -OPT_PSPRCVR_FILE=$(call add_opt_prefix, $(PSPRCVR_FILE), --recovery) -OPT_PUBSIGNEDKEY_FILE=$(call add_opt_prefix, $(PUBSIGNEDKEY_FILE), --rtmpubkey) -OPT_PSPNVRAM_FILE=$(call add_opt_prefix, $(PSPNVRAM_FILE), --nvram) -OPT_PSPSECUREDEBUG_FILE=$(call add_opt_prefix, $(PSPSECUREDEBUG_FILE), --securedebug) -ifeq ($(CONFIG_USE_PSPSECUREOS),y) -OPT_PSPSECUREOS_FILE=$(call add_opt_prefix, $(PSPSECUREOS_FILE), --secureos) -OPT_PSPTRUSTLETS_FILE=$(call add_opt_prefix, $(PSPTRUSTLETS_FILE), --trustlets) -OPT_TRUSTLETKEY_FILE=$(call add_opt_prefix, $(TRUSTLETKEY_FILE), --trustletkey) -endif -OPT_SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FILE), --smufirmware2) -OPT_SMUSCS_FILE=$(call add_opt_prefix, $(SMUSCS_FILE), --smuscs) -SUBPROG_FN_SMU_FW=1 -OPT_SMUFWM_FN_FILE=$(call add_opt_prefix, $(SMUFWM_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware) -OPT_SMUFIRMWARE2_FN_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware2) - ifeq ($(FIRMWARE_TYPE),ST) OPT_COMBOCAPABLE=--combo-capable endif +ifeq ($(CONFIG_USE_PSPSECUREOS),y) +PSP_USE_PSPSECUREOS="--use-pspsecureos" +endif + +OPT_PSP_USE_PSPSECUREOS=$(call strip_quotes, $(PSP_USE_PSPSECUREOS)) + +# Add all the files listed in the config file +DEP_FILES=$(shell $(AMDFWTOOL) --config $(CONFIG_AMDFW_CONFIG_FILE) --depend) + $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ - $(call strip_quotes, $(PUBSIGNEDKEY_FILE)) \ - $(call strip_quotes, $(PSPBTLDR_FILE)) \ - $(call strip_quotes, $(PSPRCVR_FILE)) \ - $(call strip_quotes, $(PSPSECUREOS_FILE)) \ - $(call strip_quotes, $(PSPNVRAM_FILE)) \ - $(call strip_quotes, $(SMUFWM_FILE)) \ - $(call strip_quotes, $(SMUFWM_FN_FILE)) \ - $(call strip_quotes, $(SMUSCS_FILE)) \ - $(call strip_quotes, $(PSPSECUREDEBUG_FILE)) \ - $(call strip_quotes, $(PSPTRUSTLETS_FILE)) \ - $(call strip_quotes, $(TRUSTLETKEY_FILE)) \ - $(call strip_quotes, $(SMUFIRMWARE2_FILE)) \ - $(call strip_quotes, $(SMUFIRMWARE2_FN_FILE)) \ + $(DEP_FILES) \ $(AMDFWTOOL) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ $(OPT_STONEYRIDGE_XHCI_FWM_FILE) \ $(OPT_STONEYRIDGE_GEC_FWM_FILE) \ - $(OPT_AMD_PUBKEY_FILE) \ - $(OPT_PSPBTLDR_FILE) \ - $(OPT_SMUFWM_FILE) \ - $(OPT_PSPRCVR_FILE) \ - $(OPT_PUBSIGNEDKEY_FILE) \ - $(OPT_PSPSECUREOS_FILE) \ - $(OPT_PSPNVRAM_FILE) \ - $(OPT_PSPSECUREDEBUG_FILE) \ - $(OPT_PSPTRUSTLETS_FILE) \ - $(OPT_TRUSTLETKEY_FILE) \ - $(OPT_SMUFIRMWARE2_FILE) \ - $(OPT_SMUSCS_FILE) \ - $(OPT_AMD_PUBKEY_FILE) \ - $(OPT_PSPBTLDR_FILE) \ - $(OPT_SMUFWM_FILE) \ - $(OPT_SMUFWM_FN_FILE) \ - $(OPT_PSPRCVR_FILE) \ - $(OPT_PUBSIGNEDKEY_FILE) \ - $(OPT_PSPSECUREOS_FILE) \ - $(OPT_PSPNVRAM_FILE) \ - $(OPT_PSPSECUREDEBUG_FILE) \ - $(OPT_PSPTRUSTLETS_FILE) \ - $(OPT_TRUSTLETKEY_FILE) \ - $(OPT_SMUFIRMWARE2_FILE) \ - $(OPT_SMUFIRMWARE2_FN_FILE) \ - $(OPT_SMUSCS_FILE) \ $(OPT_COMBOCAPABLE)\ + $(OPT_PSP_USE_PSPSECUREOS) \ + --config $(CONFIG_AMDFW_CONFIG_FILE) \ --flashsize $(CONFIG_ROM_SIZE) \ --location $(shell printf "0x%x" $(STONEYRIDGE_FWM_POSITION)) \ --output $@ diff --git a/src/soc/amd/stoneyridge/fw_cz.cfg b/src/soc/amd/stoneyridge/fw_cz.cfg new file mode 100644 index 0000000000..acbf13616b --- /dev/null +++ b/src/soc/amd/stoneyridge/fw_cz.cfg @@ -0,0 +1,18 @@ +# PSP fw config file + +FIRMWARE_LOCATE 3rdparty/amd_blobs/stoneyridge/PSP/CZ +#PSP +AMD_PUBKEY_FILE AmdPubKeyCZ.bin +PSPBTLDR_FILE PspBootLoader_prod_CZ.sbin +PSP_SMUFW1_SUB0_FILE SmuFirmwareCZ.sbin +#PSP_SMUFW1_SUB1_FILE SmuFirmware_CZ_FN.csbin +PSP_SMUFW2_SUB0_FILE SmuFirmware2_prod_CZ.sbin +#PSP_SMUFW2_SUB1_FILE SmuFirmware2_prod_CZ_FN.sbin +PSPRCVR_FILE PspRecoveryBootLoader_prod_CZ.sbin +PUBSIGNEDKEY_FILE RtmPubSignedCZ.key +PSPNVRAM_FILE PspNvramCZ.bin +PSPSECUREOS_FILE PspSecureOs_prod_CZ.csbin +SMUSCS_FILE SmuScsCZ.bin +PSPTRUSTLETS_FILE PspTrustlets_prod_CZ.cbin +TRUSTLETKEY_FILE TrustletKey_prod_CZ.sbin +PSPSECUREDEBUG_FILE PspSecureDebugCZ.Key diff --git a/src/soc/amd/stoneyridge/fw_st.cfg b/src/soc/amd/stoneyridge/fw_st.cfg new file mode 100644 index 0000000000..aa026683c0 --- /dev/null +++ b/src/soc/amd/stoneyridge/fw_st.cfg @@ -0,0 +1,20 @@ +# PSP fw config file + +FIRMWARE_LOCATE 3rdparty/amd_blobs/stoneyridge/PSP/ST + +#XHCI_FWM_FILE xhci.bin +#PSP +AMD_PUBKEY_FILE AmdPubKeyST.bin +PSPBTLDR_FILE PspBootLoader_prod_ST.sbin +PSP_SMUFW1_SUB0_FILE SmuFirmware_ST.csbin +PSP_SMUFW1_SUB1_FILE SmuFirmware_ST_FN.csbin +PSP_SMUFW2_SUB0_FILE SmuFirmware2_prod_ST.csbin +PSP_SMUFW2_SUB1_FILE SmuFirmware2_prod_ST_FN.sbin +PSPRCVR_FILE PspRecoveryBootLoader_prod_ST.sbin +PUBSIGNEDKEY_FILE RtmPubSignedST.key +PSPNVRAM_FILE PspNvramST.bin +PSPSECUREOS_FILE PspSecureOs_prod_ST.csbin +SMUSCS_FILE SmuScsST.bin +PSPTRUSTLETS_FILE PspTrustlets_prod_ST.cbin +TRUSTLETKEY_FILE TrustletKey_prod_ST.sbin +PSPSECUREDEBUG_FILE PspSecureDebugST.Key diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 63ab6b4e81..0f66927e45 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -170,7 +170,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - CONFIG_MMCONF_BUS_NUMBER); + CONFIG_MMCONF_BUS_NUMBER - 1); return current; } diff --git a/src/soc/example/Kconfig b/src/soc/example/Kconfig new file mode 100644 index 0000000000..5bc004aadb --- /dev/null +++ b/src/soc/example/Kconfig @@ -0,0 +1 @@ +source "src/soc/example/*/Kconfig" diff --git a/src/soc/example/min86/Kconfig b/src/soc/example/min86/Kconfig new file mode 100644 index 0000000000..38b23c0dd2 --- /dev/null +++ b/src/soc/example/min86/Kconfig @@ -0,0 +1,25 @@ +config SOC_EXAMPLE_MIN86 + bool + help + This example SoC code along with the example/min86 mainboard + should serve as a minimal example how a buildable x86 SoC code + base can look like. + + This can serve, for instance, as a basis to add new SoCs to + coreboot. Starting with a buildable commit should help with + the review of the actual code, and also avoid any regressions + when common coreboot code changes. + +if SOC_EXAMPLE_MIN86 + +config SOC_SPECIFIC_OPTIONS + def_bool y + select ARCH_ALL_STAGES_X86_32 + select NO_MONOTONIC_TIMER + select NO_MMCONF_SUPPORT + select UNKNOWN_TSC_RATE + +config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld + default 0x100 + +endif diff --git a/src/soc/example/min86/Makefile.inc b/src/soc/example/min86/Makefile.inc new file mode 100644 index 0000000000..9c1c7f0331 --- /dev/null +++ b/src/soc/example/min86/Makefile.inc @@ -0,0 +1,15 @@ +ifeq ($(CONFIG_SOC_EXAMPLE_MIN86),y) + +bootblock-y += cache_as_ram.S +bootblock-y += ../../../cpu/intel/car/bootblock.c + +postcar-y += exit_car.S + +romstage-y += romstage.c + +ramstage-y += chip.c +ramstage-y += timer.c + +subdirs-y += ../../../cpu/x86/mtrr + +endif diff --git a/src/soc/example/min86/cache_as_ram.S b/src/soc/example/min86/cache_as_ram.S new file mode 100644 index 0000000000..a350143834 --- /dev/null +++ b/src/soc/example/min86/cache_as_ram.S @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +.global bootblock_pre_c_entry + +.code32 +bootblock_pre_c_entry: + call bootblock_c_entry_bist + +.Lhlt: + hlt + jmp .Lhlt diff --git a/src/soc/example/min86/chip.c b/src/soc/example/min86/chip.c new file mode 100644 index 0000000000..dd09891e3c --- /dev/null +++ b/src/soc/example/min86/chip.c @@ -0,0 +1,3 @@ +#include + +struct chip_operations soc_example_min86_ops = { NULL }; diff --git a/src/soc/example/min86/exit_car.S b/src/soc/example/min86/exit_car.S new file mode 100644 index 0000000000..0f1b227c2d --- /dev/null +++ b/src/soc/example/min86/exit_car.S @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +.global chipset_teardown_car + +.code32 +chipset_teardown_car: + /* Return to caller. */ + jmp *%esp diff --git a/src/soc/example/min86/romstage.c b/src/soc/example/min86/romstage.c new file mode 100644 index 0000000000..91074b2012 --- /dev/null +++ b/src/soc/example/min86/romstage.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +asmlinkage void car_stage_entry(void) +{ +} diff --git a/src/soc/example/min86/timer.c b/src/soc/example/min86/timer.c new file mode 100644 index 0000000000..9054ffd972 --- /dev/null +++ b/src/soc/example/min86/timer.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void init_timer(void) +{ +} diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 1a3f0724ae..b10d88c5c1 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -16,6 +16,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_SUPPORTS_PM_TIMER_EMULATION select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP + select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 select GENERIC_GPIO_LIB select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE @@ -39,6 +40,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT @@ -49,9 +51,9 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET - select SOC_INTEL_COMMON_BLOCK_CAR select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 39a42651bd..9fab277781 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -23,7 +23,6 @@ #include #include #include -#include #include static void soc_fsp_load(void) @@ -62,25 +61,6 @@ static void configure_misc(void) wrmsr(MSR_POWER_CTL, msr); } -static void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { @@ -97,7 +77,6 @@ void soc_core_init(struct device *cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); /* Enable Direct Cache Access */ diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h index 76930be0e7..5fed5680c6 100644 --- a/src/soc/intel/alderlake/include/soc/meminit.h +++ b/src/soc/intel/alderlake/include/soc/meminit.h @@ -76,6 +76,12 @@ struct mb_cfg { /* Rcomp target values. */ uint16_t rcomp_targets[5]; + /* + * Dqs Pins Interleaved Setting. Enable/Disable Control + * TRUE = enable, FALSE = disable + */ + bool dq_pins_interleaved; + /* * Early Command Training Enable/Disable Control * TRUE = enable, FALSE = disable diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index e7084a5a16..f5f747d79b 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -180,4 +180,5 @@ void memcfg_init(FSP_M_CONFIG *mem_cfg, mem_cfg->ECT = board_cfg->ect; mem_cfg->UserBd = board_cfg->UserBd; + mem_cfg->DqPinsInterleaved = board_cfg->dq_pins_interleaved; } diff --git a/src/soc/intel/alderlake/reset.c b/src/soc/intel/alderlake/reset.c index 1f7ea3c180..bc5815ac7a 100644 --- a/src/soc/intel/alderlake/reset.c +++ b/src/soc/intel/alderlake/reset.c @@ -1,12 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include -#include #include -#include void do_global_reset(void) { @@ -18,17 +15,3 @@ void do_global_reset(void) pmc_global_reset_enable(1); do_full_reset(); } - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 69d42bdf19..3917feaf79 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -7,6 +7,7 @@ config SOC_INTEL_GEMINILAKE bool default n select SOC_INTEL_APOLLOLAKE + select SOC_INTEL_COMMON_BLOCK_CNVI select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_SGX select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 @@ -37,6 +38,7 @@ config CPU_SPECIFIC_OPTIONS # Misc options select CACHE_MRC_SETTINGS select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS + select FSP_STATUS_GLOBAL_RESET_REQUIRED_5 select GENERIC_GPIO_LIB select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER @@ -90,6 +92,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_CSE select SOC_INTEL_COMMON_BLOCK_SMBUS + select SOC_INTEL_COMMON_FSP_RESET select SOUTHBRIDGE_INTEL_COMMON_SMBUS select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 79fab1a9d1..64889e56f9 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -10,6 +10,7 @@ subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c +bootblock-y += ../common/block/cpu/pm_timer_emulation.c bootblock-$(CONFIG_FSP_CAR) += fspcar.c bootblock-y += car.c bootblock-y += heci.c diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index aaf62583e6..748f76adba 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -234,8 +234,6 @@ struct chipset_power_state { void pch_log_state(void); -void enable_pm_timer_emulation(void); - /* STM Support */ uint16_t get_pmbase(void); diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index e0de93eae4..6e96b57a07 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -178,24 +178,6 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps, return prev_sleep_state; } -void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + R_ACPI_PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - static int rtc_failed(uint32_t gen_pmcon1) { return !!(gen_pmcon1 & RPS); diff --git a/src/soc/intel/apollolake/reset.c b/src/soc/intel/apollolake/reset.c index 8641b63aaf..186a546388 100644 --- a/src/soc/intel/apollolake/reset.c +++ b/src/soc/intel/apollolake/reset.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include @@ -47,16 +46,3 @@ void cf9_reset_prepare(void) } printk(BIOS_SPEW, "CSE took %lu ms\n", stopwatch_duration_msecs(&sw)); } - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_5: /* Global Reset */ - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 35129af8b7..2430be61f5 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -33,9 +33,6 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select TSC_MONOTONIC_TIMER select SOC_INTEL_COMMON - select SOC_INTEL_COMMON_BLOCK - select SOC_INTEL_COMMON_BLOCK_CPU - select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index e24b949fb5..ce1dd9cbf6 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -9,52 +9,26 @@ subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common +subdirs-y += pch + bootblock-y += bootblock/cpu.c -bootblock-y += bootblock/pch.c bootblock-y += bootblock/systemagent.c bootblock-y += ../../../cpu/intel/car/bootblock.c bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S bootblock-y += ../../../cpu/x86/early_reset.S ramstage-y += acpi.c -ramstage-y += adsp.c ramstage-y += cpu.c -ramstage-y += cpu_info.c -smm-y += cpu_info.c -ramstage-$(CONFIG_ELOG) += elog.c ramstage-y += finalize.c -ramstage-y += gpio.c -romstage-y += gpio.c -smm-y += gpio.c -ramstage-y += hda.c ramstage-y += gma.c -ramstage-y += iobp.c -romstage-y += iobp.c -ramstage-y += fadt.c -ramstage-y += lpc.c -ramstage-y += me.c -ramstage-y += me_status.c -romstage-y += me_status.c ramstage-y += memmap.c romstage-y += memmap.c postcar-y += memmap.c ramstage-y += minihd.c -ramstage-y += pch.c -romstage-y += pch.c -ramstage-y += pcie.c ramstage-y += pei_data.c romstage-y += pei_data.c -ramstage-y += pmutil.c -romstage-y += pmutil.c -smm-y += pmutil.c -verstage-y += pmutil.c ramstage-y += ramstage.c ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c -ramstage-y += sata.c -ramstage-y += serialio.c -ramstage-y += smbus.c -ramstage-y += smi.c -smm-y += smihandler.c ramstage-y += smmrelocate.c ramstage-y += systemagent.c bootblock-y += tsc_freq.c @@ -63,17 +37,9 @@ romstage-y += tsc_freq.c smm-y += tsc_freq.c postcar-y += tsc_freq.c verstage-y += tsc_freq.c -bootblock-y += usb_debug.c -romstage-y += usb_debug.c -ramstage-y += usb_debug.c -ramstage-y += ehci.c -ramstage-y += xhci.c -smm-y += xhci.c postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c - cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin CPPFLAGS_common += -Isrc/soc/intel/broadwell/include diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 760842b2ab..1b4db1dae6 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -24,7 +24,6 @@ #include #include #include -#include /* * List of supported C-states in this processor. Only the ULT parts support C8, diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index ae433536cd..81c9780776 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -4,74 +4,9 @@ #define _SOC_INTEL_BROADWELL_CHIP_H_ #include -#include #include struct soc_intel_broadwell_config { - /* GPE configuration */ - uint32_t gpe0_en_1; - uint32_t gpe0_en_2; - uint32_t gpe0_en_3; - uint32_t gpe0_en_4; - - /* GPIO SMI configuration */ - uint32_t alt_gp_smi_en; - - /* IDE configuration */ - uint8_t sata_port_map; - uint32_t sata_port0_gen3_tx; - uint32_t sata_port1_gen3_tx; - uint32_t sata_port2_gen3_tx; - uint32_t sata_port3_gen3_tx; - uint32_t sata_port0_gen3_dtle; - uint32_t sata_port1_gen3_dtle; - uint32_t sata_port2_gen3_dtle; - uint32_t sata_port3_gen3_dtle; - - /* - * SATA DEVSLP Mux - * 0 = port 0 DEVSLP on DEVSLP0/GPIO33 - * 1 = port 3 DEVSLP on DEVSLP0/GPIO33 - */ - uint8_t sata_devslp_mux; - - /* - * DEVSLP Disable - * 0: DEVSLP is enabled - * 1: DEVSLP is disabled - */ - uint8_t sata_devslp_disable; - - /* Generic IO decode ranges */ - uint32_t gen1_dec; - uint32_t gen2_dec; - uint32_t gen3_dec; - uint32_t gen4_dec; - - /* Enable linear PCIe Root Port function numbers starting at zero */ - uint8_t pcie_port_coalesce; - - /* Force root port ASPM configuration with port bitmap */ - uint8_t pcie_port_force_aspm; - - /* Put SerialIO devices into ACPI mode instead of a PCI device */ - uint8_t sio_acpi_mode; - - /* I2C voltage select: 0=3.3V 1=1.8V */ - uint8_t sio_i2c0_voltage; - uint8_t sio_i2c1_voltage; - - /* Enable ADSP power gating features */ - uint8_t adsp_d3_pg_enable; - uint8_t adsp_sram_pg_enable; - - /* - * Clock Disable Map: - * [21:16] = CLKOUT_PCIE# 5-0 - * [24] = CLKOUT_ITPXDP - */ - uint32_t icc_clock_disable; - /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -108,9 +43,6 @@ struct soc_intel_broadwell_config { struct i915_gpu_controller_info gfx; - /* Enable S0iX support */ - int s0ix_enable; - /* * Minimum voltage for C6/C7 state: * 0x67 = 1.6V (full swing) @@ -133,9 +65,8 @@ struct soc_intel_broadwell_config { /* Enable slow VR ramp rate */ int vr_slow_ramp_rate_enable; - /* Deep SX enable */ - int deep_sx_enable_ac; - int deep_sx_enable_dc; + /* Enable S0iX support */ + int s0ix_enable; /* TCC activation offset */ uint32_t tcc_offset; diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 00460c6282..72efa3dc81 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -25,6 +24,64 @@ #include #include +/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ +static const u8 power_limit_time_sec_to_msr[] = { + [0] = 0x00, + [1] = 0x0a, + [2] = 0x0b, + [3] = 0x4b, + [4] = 0x0c, + [5] = 0x2c, + [6] = 0x4c, + [7] = 0x6c, + [8] = 0x0d, + [10] = 0x2d, + [12] = 0x4d, + [14] = 0x6d, + [16] = 0x0e, + [20] = 0x2e, + [24] = 0x4e, + [28] = 0x6e, + [32] = 0x0f, + [40] = 0x2f, + [48] = 0x4f, + [56] = 0x6f, + [64] = 0x10, + [80] = 0x30, + [96] = 0x50, + [112] = 0x70, + [128] = 0x11, +}; + +/* Convert POWER_LIMIT_1_TIME MSR value to seconds */ +static const u8 power_limit_time_msr_to_sec[] = { + [0x00] = 0, + [0x0a] = 1, + [0x0b] = 2, + [0x4b] = 3, + [0x0c] = 4, + [0x2c] = 5, + [0x4c] = 6, + [0x6c] = 7, + [0x0d] = 8, + [0x2d] = 10, + [0x4d] = 12, + [0x6d] = 14, + [0x0e] = 16, + [0x2e] = 20, + [0x4e] = 24, + [0x6e] = 28, + [0x0f] = 32, + [0x2f] = 40, + [0x4f] = 48, + [0x6f] = 56, + [0x10] = 64, + [0x30] = 80, + [0x50] = 96, + [0x70] = 112, + [0x11] = 128, +}; + /* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate * the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly * when a core is woken up. */ @@ -230,6 +287,90 @@ static void configure_pch_power_sharing(void) RCBA32(PMSYNC_CONFIG2) = pmsync2; } +int cpu_config_tdp_levels(void) +{ + msr_t platform_info; + + /* Bits 34:33 indicate how many levels supported */ + platform_info = rdmsr(MSR_PLATFORM_INFO); + return (platform_info.hi >> 1) & 3; +} + +/* + * Configure processor power limits if possible + * This must be done AFTER set of BIOS_RESET_CPL + */ +void set_power_limits(u8 power_limit_1_time) +{ + msr_t msr = rdmsr(MSR_PLATFORM_INFO); + msr_t limit; + unsigned int power_unit; + unsigned int tdp, min_power, max_power, max_time; + u8 power_limit_1_val; + + if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) + power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; + + if (!(msr.lo & PLATFORM_INFO_SET_TDP)) + return; + + /* Get units */ + msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = 2 << ((msr.lo & 0xf) - 1); + + /* Get power defaults for this SKU */ + msr = rdmsr(MSR_PKG_POWER_SKU); + tdp = msr.lo & 0x7fff; + min_power = (msr.lo >> 16) & 0x7fff; + max_power = msr.hi & 0x7fff; + max_time = (msr.hi >> 16) & 0x7f; + + printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); + + if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) + power_limit_1_time = power_limit_time_msr_to_sec[max_time]; + + if (min_power > 0 && tdp < min_power) + tdp = min_power; + + if (max_power > 0 && tdp > max_power) + tdp = max_power; + + power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; + + /* Set long term power limit to TDP */ + limit.lo = 0; + limit.lo |= tdp & PKG_POWER_LIMIT_MASK; + limit.lo |= PKG_POWER_LIMIT_EN; + limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << + PKG_POWER_LIMIT_TIME_SHIFT; + + /* Set short term power limit to 1.25 * TDP */ + limit.hi = 0; + limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; + limit.hi |= PKG_POWER_LIMIT_EN; + /* Power limit 2 time is only programmable on server SKU */ + + wrmsr(MSR_PKG_POWER_LIMIT, limit); + + /* Set power limit values in MCHBAR as well */ + MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo; + MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi; + + /* Set DDR RAPL power limit by copying from MMIO to MSR */ + msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO); + msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI); + wrmsr(MSR_DDR_RAPL_LIMIT, msr); + + /* Use nominal TDP values for CPUs with configurable TDP */ + if (cpu_config_tdp_levels()) { + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + limit.hi = 0; + limit.lo = msr.lo & 0xff; + wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); + } +} + static void configure_c_states(void) { msr_t msr; @@ -290,6 +431,28 @@ static void configure_c_states(void) wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } +static void configure_thermal_target(void) +{ + config_t *conf; + struct device *lapic; + msr_t msr; + + /* Find pointer to CPU configuration */ + lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + if (!lapic || !lapic->chip_info) + return; + conf = lapic->chip_info; + + /* Set TCC activation offset if supported */ + msr = rdmsr(MSR_PLATFORM_INFO); + if ((msr.lo & (1 << 30)) && conf->tcc_offset) { + msr = rdmsr(MSR_TEMPERATURE_TARGET); + msr.lo &= ~(0xf << 24); /* Bits 27:24 */ + msr.lo |= (conf->tcc_offset & 0xf) << 24; + wrmsr(MSR_TEMPERATURE_TARGET, msr); + } +} + static void configure_misc(void) { msr_t msr; @@ -372,7 +535,7 @@ static void cpu_core_init(struct device *cpu) configure_misc(); /* Thermal throttle activation offset */ - configure_tcc_thermal_target(); + configure_thermal_target(); /* Enable Direct Cache Access */ configure_dca_cap(); diff --git a/src/soc/intel/broadwell/cpu_info.c b/src/soc/intel/broadwell/cpu_info.c deleted file mode 100644 index 506b1a7985..0000000000 --- a/src/soc/intel/broadwell/cpu_info.c +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include - -u32 cpu_family_model(void) -{ - return cpuid_eax(1) & 0x0fff0ff0; -} - -u32 cpu_stepping(void) -{ - return cpuid_eax(1) & 0xf; -} - -/* Dynamically determine if the part is ULT. */ -int cpu_is_ult(void) -{ - static int ult = -1; - - if (ult < 0) { - u32 fm = cpu_family_model(); - if (fm == BROADWELL_FAMILY_ULT || fm == HASWELL_FAMILY_ULT) - ult = 1; - else - ult = 0; - } - - return ult; -} diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 4196144369..3dafc9defd 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -4,15 +4,9 @@ #include #include #include -#include -#include #include -#include -#include -#include -#include +#include #include -#include /* * 16.6 System Agent Configuration Locking @@ -55,48 +49,13 @@ static void broadwell_systemagent_finalize(void) MCHBAR32(0x6008) = MCHBAR32(0x6008); } -const struct reg_script pch_finalize_script[] = { -#if !CONFIG(EM100PRO_SPI_CONSOLE) - /* Lock SPIBAR */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS, - SPIBAR_HSFS_FLOCKDN), -#endif - - /* TC Lockdown */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0050, (1 << 31)), - - /* BIOS Interface Lockdown */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 0)), - - /* Function Disable SUS Well Lockdown */ - REG_MMIO_OR8(RCBA_BASE_ADDRESS + FDSW, (1 << 7)), - - /* Global SMI Lock */ - REG_PCI_OR16(GEN_PMCON_1, SMI_LOCK), - - /* GEN_PMCON Lock */ - REG_PCI_OR8(GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK), - - /* PMSYNC */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + PMSYNC_CONFIG, (1 << 31)), - - REG_SCRIPT_END -}; - static void broadwell_finalize(void *unused) { printk(BIOS_DEBUG, "Finalizing chipset.\n"); broadwell_systemagent_finalize(); - spi_finalize_ops(); - reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script); - - /* Lock */ - RCBA32_OR(0x3a6c, 0x00000001); - - /* Read+Write this R/WO register */ - RCBA32(LCAP) = RCBA32(LCAP); + broadwell_pch_finalize(); /* Indicate finalize step with post code */ post_code(POST_OS_BOOT); diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index c77f5c4476..3889be3513 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -364,6 +364,7 @@ static int igd_get_cdclk_haswell(u32 *const cdsel, int *const inform_pc, /* Check for ULX GT1 or GT2 */ const int devid = pci_read_config16(dev, PCI_DEVICE_ID); + const int cpu_is_ult = cpu_family_model() == HASWELL_FAMILY_ULT; const int gpu_is_ulx = devid == IGD_HASWELL_ULX_GT1 || devid == IGD_HASWELL_ULX_GT2; @@ -378,7 +379,7 @@ static int igd_get_cdclk_haswell(u32 *const cdsel, int *const inform_pc, */ if (gpu_is_ulx && cdclk <= GT_CDCLK_337) cdclk = GT_CDCLK_337; - else if (gpu_is_ulx || cpu_is_ult() || + else if (gpu_is_ulx || cpu_is_ult || cdclk == GT_CDCLK_337 || cdclk == GT_CDCLK_450) cdclk = GT_CDCLK_450; else @@ -398,6 +399,7 @@ static int igd_get_cdclk_broadwell(u32 *const cdsel, int *const inform_pc, /* Check for ULX */ const int devid = pci_read_config16(dev, PCI_DEVICE_ID); + const int cpu_is_ult = cpu_family_model() == BROADWELL_FAMILY_ULT; const int gpu_is_ulx = devid == IGD_BROADWELL_Y_GT2; /* Inform power controller of upcoming frequency change */ @@ -428,7 +430,7 @@ static int igd_get_cdclk_broadwell(u32 *const cdsel, int *const inform_pc, (gpu_is_ulx && cdclk == GT_CDCLK_DEFAULT)) cdclk = GT_CDCLK_450; else if (cdclk == GT_CDCLK_540 || gpu_is_ulx || - (cpu_is_ult() && cdclk == GT_CDCLK_DEFAULT)) + (cpu_is_ult && cdclk == GT_CDCLK_DEFAULT)) cdclk = GT_CDCLK_540; else cdclk = GT_CDCLK_675; diff --git a/src/soc/intel/broadwell/include/soc/cpu.h b/src/soc/intel/broadwell/include/soc/cpu.h index 9167736c00..bc5d2d76bd 100644 --- a/src/soc/intel/broadwell/include/soc/cpu.h +++ b/src/soc/intel/broadwell/include/soc/cpu.h @@ -3,7 +3,9 @@ #ifndef _BROADWELL_CPU_H_ #define _BROADWELL_CPU_H_ +#include #include +#include /* CPU types */ #define HASWELL_FAMILY_ULT 0x40650 @@ -37,9 +39,19 @@ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ (IRTL_1024_NS >> 10)) +/* Configure power limits for turbo mode */ +void set_power_limits(u8 power_limit_1_time); +int cpu_config_tdp_levels(void); + /* CPU identification */ -u32 cpu_family_model(void); -u32 cpu_stepping(void); -int cpu_is_ult(void); +static inline u32 cpu_family_model(void) +{ + return cpuid_eax(1) & 0x0fff0ff0; +} + +static inline u32 cpu_stepping(void) +{ + return cpuid_eax(1) & 0xf; +} #endif diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index b8ed3328cc..6a5f4dc5f1 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -3,8 +3,6 @@ #ifndef _BROADWELL_MSR_H_ #define _BROADWELL_MSR_H_ -#include - #define MSR_CORE_THREAD_COUNT 0x35 #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) @@ -46,6 +44,14 @@ #define IRTL_RESPONSE_MASK (0x3ff) #define MSR_COUNTER_24_MHZ 0x637 +/* Long duration in low dword, short duration in high dword */ +#define MSR_PKG_POWER_LIMIT 0x610 +#define PKG_POWER_LIMIT_MASK 0x7fff +#define PKG_POWER_LIMIT_EN (1 << 15) +#define PKG_POWER_LIMIT_CLAMP (1 << 16) +#define PKG_POWER_LIMIT_TIME_SHIFT 17 +#define PKG_POWER_LIMIT_TIME_MASK 0x7f + #define MSR_VR_CURRENT_CONFIG 0x601 #define MSR_VR_MISC_CONFIG 0x603 #define MSR_PKG_POWER_SKU_UNIT 0x606 diff --git a/src/soc/intel/broadwell/include/soc/pch.h b/src/soc/intel/broadwell/include/soc/pch.h index 59b5b18f17..cf27499fe5 100644 --- a/src/soc/intel/broadwell/include/soc/pch.h +++ b/src/soc/intel/broadwell/include/soc/pch.h @@ -30,4 +30,6 @@ int pch_is_wpt_ulx(void); u32 pch_read_soft_strap(int id); void pch_disable_devfn(struct device *dev); +void broadwell_pch_finalize(void); + #endif diff --git a/src/soc/intel/broadwell/include/soc/ramstage.h b/src/soc/intel/broadwell/include/soc/ramstage.h index 0b6ef0d61b..5d7eceb4a5 100644 --- a/src/soc/intel/broadwell/include/soc/ramstage.h +++ b/src/soc/intel/broadwell/include/soc/ramstage.h @@ -8,7 +8,6 @@ void broadwell_init_pre_device(void *chip_info); void broadwell_init_cpus(struct device *dev); -void broadwell_pch_enable_dev(struct device *dev); #if CONFIG(HAVE_REFCODE_BLOB) void broadwell_run_reference_code(void); diff --git a/src/soc/intel/broadwell/include/soc/soc_chip.h b/src/soc/intel/broadwell/include/soc/soc_chip.h deleted file mode 100644 index bbd556e55d..0000000000 --- a/src/soc/intel/broadwell/include/soc/soc_chip.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_BROADWELL_SOC_CHIP_H_ -#define _SOC_BROADWELL_SOC_CHIP_H_ - -#include "../../chip.h" - -#endif /* _SOC_BROADWELL_SOC_CHIP_H_ */ diff --git a/src/soc/intel/broadwell/pch/Makefile.inc b/src/soc/intel/broadwell/pch/Makefile.inc new file mode 100644 index 0000000000..1c196136c4 --- /dev/null +++ b/src/soc/intel/broadwell/pch/Makefile.inc @@ -0,0 +1,39 @@ +bootblock-y += bootblock.c + +ramstage-y += adsp.c +romstage-y += early_pch.c +ramstage-$(CONFIG_ELOG) += elog.c +ramstage-y += finalize.c +ramstage-y += gpio.c +romstage-y += gpio.c +smm-y += gpio.c +ramstage-y += hda.c +ramstage-y += iobp.c +romstage-y += iobp.c +ramstage-y += fadt.c +ramstage-y += lpc.c +ramstage-y += me.c +ramstage-y += me_status.c +romstage-y += me_status.c +ramstage-y += pch.c +romstage-y += pch.c +ramstage-y += pcie.c +ramstage-y += pmutil.c +romstage-y += pmutil.c +smm-y += pmutil.c +verstage-y += pmutil.c +romstage-y += power_state.c +ramstage-y += sata.c +ramstage-y += serialio.c +ramstage-y += smbus.c +ramstage-y += smi.c +smm-y += smihandler.c +romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c +bootblock-y += usb_debug.c +romstage-y += usb_debug.c +ramstage-y += usb_debug.c +ramstage-y += ehci.c +ramstage-y += xhci.c +smm-y += xhci.c + +ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/pch/adsp.c similarity index 97% rename from src/soc/intel/broadwell/adsp.c rename to src/soc/intel/broadwell/pch/adsp.c index 220ad6f269..06dd38bd8a 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/pch/adsp.c @@ -14,11 +14,11 @@ #include #include #include -#include +#include static void adsp_init(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); struct resource *bar0, *bar1; u32 tmp32; diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/pch/bootblock.c similarity index 100% rename from src/soc/intel/broadwell/bootblock/pch.c rename to src/soc/intel/broadwell/pch/bootblock.c diff --git a/src/soc/intel/broadwell/pch/chip.h b/src/soc/intel/broadwell/pch/chip.h new file mode 100644 index 0000000000..2164a31050 --- /dev/null +++ b/src/soc/intel/broadwell/pch/chip.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_BROADWELL_PCH_CHIP_H_ +#define _SOC_INTEL_BROADWELL_PCH_CHIP_H_ + +#include + +struct soc_intel_broadwell_pch_config { + /* GPE configuration */ + uint32_t gpe0_en_1; + uint32_t gpe0_en_2; + uint32_t gpe0_en_3; + uint32_t gpe0_en_4; + + /* GPIO SMI configuration */ + uint32_t alt_gp_smi_en; + + /* IDE configuration */ + uint8_t sata_port_map; + uint32_t sata_port0_gen3_tx; + uint32_t sata_port1_gen3_tx; + uint32_t sata_port2_gen3_tx; + uint32_t sata_port3_gen3_tx; + uint32_t sata_port0_gen3_dtle; + uint32_t sata_port1_gen3_dtle; + uint32_t sata_port2_gen3_dtle; + uint32_t sata_port3_gen3_dtle; + + /* + * SATA DEVSLP Mux + * 0 = port 0 DEVSLP on DEVSLP0/GPIO33 + * 1 = port 3 DEVSLP on DEVSLP0/GPIO33 + */ + uint8_t sata_devslp_mux; + + /* + * DEVSLP Disable + * 0: DEVSLP is enabled + * 1: DEVSLP is disabled + */ + uint8_t sata_devslp_disable; + + /* Generic IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; + + /* Enable linear PCIe Root Port function numbers starting at zero */ + uint8_t pcie_port_coalesce; + + /* Force root port ASPM configuration with port bitmap */ + uint8_t pcie_port_force_aspm; + + /* Put SerialIO devices into ACPI mode instead of a PCI device */ + uint8_t sio_acpi_mode; + + /* I2C voltage select: 0=3.3V 1=1.8V */ + uint8_t sio_i2c0_voltage; + uint8_t sio_i2c1_voltage; + + /* Enable ADSP power gating features */ + uint8_t adsp_d3_pg_enable; + uint8_t adsp_sram_pg_enable; + + /* + * Clock Disable Map: + * [21:16] = CLKOUT_PCIE# 5-0 + * [24] = CLKOUT_ITPXDP + */ + uint32_t icc_clock_disable; + + /* Deep SX enable */ + int deep_sx_enable_ac; + int deep_sx_enable_dc; +}; + +#endif diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/pch/early_pch.c similarity index 93% rename from src/soc/intel/broadwell/romstage/pch.c rename to src/soc/intel/broadwell/pch/early_pch.c index d68e17eee2..149dda1ca0 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/pch/early_pch.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include static void pch_route_interrupts(void) { @@ -52,9 +52,9 @@ static void pch_route_interrupts(void) static void pch_enable_lpc(void) { /* Lookup device tree in romstage */ - const config_t *config; + const struct device *const dev = pcidev_on_root(0x1f, 0); - config = config_of_soc(); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec); pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec); diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/pch/ehci.c similarity index 100% rename from src/soc/intel/broadwell/ehci.c rename to src/soc/intel/broadwell/pch/ehci.c diff --git a/src/soc/intel/broadwell/elog.c b/src/soc/intel/broadwell/pch/elog.c similarity index 100% rename from src/soc/intel/broadwell/elog.c rename to src/soc/intel/broadwell/pch/elog.c diff --git a/src/soc/intel/broadwell/fadt.c b/src/soc/intel/broadwell/pch/fadt.c similarity index 100% rename from src/soc/intel/broadwell/fadt.c rename to src/soc/intel/broadwell/pch/fadt.c diff --git a/src/soc/intel/broadwell/pch/finalize.c b/src/soc/intel/broadwell/pch/finalize.c new file mode 100644 index 0000000000..71f06390e0 --- /dev/null +++ b/src/soc/intel/broadwell/pch/finalize.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +void broadwell_pch_finalize(void) +{ + spi_finalize_ops(); + + /* Lock SPIBAR */ + if (!CONFIG(EM100PRO_SPI_CONSOLE)) + RCBA32_OR(SPIBAR_OFFSET + SPIBAR_HSFS, SPIBAR_HSFS_FLOCKDN); + + /* TC Lockdown */ + RCBA32_OR(0x0050, 1 << 31); + + /* BIOS Interface Lockdown */ + RCBA32_OR(GCS, 1 << 0); + + /* Function Disable SUS Well Lockdown */ + RCBA8(FDSW) |= 1 << 7; + + /* Global SMI Lock */ + pci_or_config16(PCH_DEV_LPC, GEN_PMCON_1, SMI_LOCK); + + /* GEN_PMCON Lock */ + pci_or_config8(PCH_DEV_LPC, GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK); + + /* PMSYNC */ + RCBA32_OR(PMSYNC_CONFIG, 1 << 31); + + /* Lock */ + RCBA32_OR(0x3a6c, 0x00000001); + + /* Read+Write this R/WO register */ + RCBA32(LCAP) = RCBA32(LCAP); +} diff --git a/src/soc/intel/broadwell/gpio.c b/src/soc/intel/broadwell/pch/gpio.c similarity index 100% rename from src/soc/intel/broadwell/gpio.c rename to src/soc/intel/broadwell/pch/gpio.c diff --git a/src/soc/intel/broadwell/hda.c b/src/soc/intel/broadwell/pch/hda.c similarity index 100% rename from src/soc/intel/broadwell/hda.c rename to src/soc/intel/broadwell/pch/hda.c diff --git a/src/soc/intel/broadwell/iobp.c b/src/soc/intel/broadwell/pch/iobp.c similarity index 100% rename from src/soc/intel/broadwell/iobp.c rename to src/soc/intel/broadwell/pch/iobp.c diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/pch/lpc.c similarity index 98% rename from src/soc/intel/broadwell/lpc.c rename to src/soc/intel/broadwell/pch/lpc.c index 8b85a0420d..2111913a0e 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include @@ -130,7 +130,7 @@ static void pch_power_options(struct device *dev) u16 reg16; const char *state; /* Get the chip configuration */ - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; /* Which state do we want to goto after g3 (power restored)? @@ -336,7 +336,7 @@ static void pch_enable_mphy(void) static void pch_init_deep_sx(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); if (config->deep_sx_enable_ac) { RCBA32_OR(DEEP_S3_POL, DEEP_S3_EN_AC); @@ -567,7 +567,7 @@ static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, static void pch_lpc_add_io_resources(struct device *dev) { struct resource *res; - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); /* Add the default claimed IO range for the LPC device. */ res = new_resource(dev, 0); diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/pch/me.c similarity index 99% rename from src/soc/intel/broadwell/me.c rename to src/soc/intel/broadwell/pch/me.c index 80ffe2b9ac..40a81d8810 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/pch/me.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #if CONFIG(CHROMEOS) #include @@ -950,7 +950,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) /* Check whether ME is present and do basic init */ static void intel_me_init(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); me_bios_path path = intel_me_path(dev); me_bios_payload mbp_data; int mbp_ret; diff --git a/src/soc/intel/broadwell/me_status.c b/src/soc/intel/broadwell/pch/me_status.c similarity index 100% rename from src/soc/intel/broadwell/me_status.c rename to src/soc/intel/broadwell/pch/me_status.c diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch/pch.c similarity index 94% rename from src/soc/intel/broadwell/pch.c rename to src/soc/intel/broadwell/pch/pch.c index 2a27d92152..e0c5bb0c4d 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch/pch.c @@ -166,10 +166,16 @@ void pch_disable_devfn(struct device *dev) } } -void broadwell_pch_enable_dev(struct device *dev) +static void broadwell_pch_enable_dev(struct device *dev) { u16 reg16; + if (dev->path.type != DEVICE_PATH_PCI) + return; + + if (dev->ops && dev->ops->enable) + return; + /* These devices need special enable/disable handling */ switch (PCI_SLOT(dev->path.pci.devfn)) { case PCH_DEV_SLOT_PCIE: @@ -195,4 +201,9 @@ void broadwell_pch_enable_dev(struct device *dev) } } +struct chip_operations soc_intel_broadwell_pch_ops = { + CHIP_NAME("Intel Broadwell PCH") + .enable_dev = &broadwell_pch_enable_dev, +}; + #endif diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pch/pcie.c similarity index 98% rename from src/soc/intel/broadwell/pcie.c rename to src/soc/intel/broadwell/pch/pcie.c index 0d41d42525..c98201e5ab 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include @@ -121,7 +121,7 @@ static void root_port_init_config(struct device *dev) root_port_config_update_gbe_port(); pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4)); - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); rpc.coalesce = config->pcie_port_coalesce; } @@ -436,7 +436,7 @@ static void pcie_add_0x0202000_iobp(u32 reg) static void pch_pcie_early(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); int do_aspm = 0; int rp = root_port_number(dev); diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pch/pmutil.c similarity index 100% rename from src/soc/intel/broadwell/pmutil.c rename to src/soc/intel/broadwell/pch/pmutil.c diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/pch/power_state.c similarity index 100% rename from src/soc/intel/broadwell/romstage/power_state.c rename to src/soc/intel/broadwell/pch/power_state.c diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/pch/sata.c similarity index 97% rename from src/soc/intel/broadwell/sata.c rename to src/soc/intel/broadwell/pch/sata.c index c9168325e2..b496e53e3d 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/pch/sata.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include static inline u32 sir_read(struct device *dev, int idx) { @@ -27,7 +27,7 @@ static inline void sir_write(struct device *dev, int idx, u32 value) static void sata_init(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); u32 reg32; u8 *abar; u16 reg16; @@ -256,7 +256,7 @@ static void sata_init(struct device *dev) static void sata_enable(struct device *dev) { /* Get the chip configuration */ - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); u16 map = 0x0060; map |= (config->sata_port_map ^ 0xf) << 8; diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/pch/serialio.c similarity index 98% rename from src/soc/intel/broadwell/serialio.c rename to src/soc/intel/broadwell/pch/serialio.c index 766f5dd048..d32a27ddca 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/pch/serialio.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include /* Set D3Hot Power State in ACPI mode */ static void serialio_enable_d3hot(struct resource *res) @@ -156,7 +156,7 @@ static void serialio_init_once(int acpi_mode) static void serialio_init(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); struct resource *bar0, *bar1; int sio_index = -1; diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/pch/smbus.c similarity index 100% rename from src/soc/intel/broadwell/smbus.c rename to src/soc/intel/broadwell/pch/smbus.c diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/pch/smi.c similarity index 100% rename from src/soc/intel/broadwell/smi.c rename to src/soc/intel/broadwell/pch/smi.c diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/pch/smihandler.c similarity index 100% rename from src/soc/intel/broadwell/smihandler.c rename to src/soc/intel/broadwell/pch/smihandler.c diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/pch/uart.c similarity index 100% rename from src/soc/intel/broadwell/romstage/uart.c rename to src/soc/intel/broadwell/pch/uart.c diff --git a/src/soc/intel/broadwell/usb_debug.c b/src/soc/intel/broadwell/pch/usb_debug.c similarity index 100% rename from src/soc/intel/broadwell/usb_debug.c rename to src/soc/intel/broadwell/pch/usb_debug.c diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/pch/xhci.c similarity index 100% rename from src/soc/intel/broadwell/xhci.c rename to src/soc/intel/broadwell/pch/xhci.c diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc index edfec30fdc..b77e7a579d 100644 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ b/src/soc/intel/broadwell/romstage/Makefile.inc @@ -1,9 +1,6 @@ romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += cpu.c -romstage-y += pch.c -romstage-y += power_state.c romstage-y += raminit.c romstage-y += report_platform.c romstage-y += romstage.c romstage-y += systemagent.c -romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c diff --git a/src/soc/intel/broadwell/romstage/cpu.c b/src/soc/intel/broadwell/romstage/cpu.c index 736487697d..c9f70a85d1 100644 --- a/src/soc/intel/broadwell/romstage/cpu.c +++ b/src/soc/intel/broadwell/romstage/cpu.c @@ -7,11 +7,6 @@ #include #include -u32 cpu_family_model(void) -{ - return cpuid_eax(1) & 0x0fff0ff0; -} - void set_max_freq(void) { msr_t msr, perf_ctl, platform_info; diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 4b4848b4ef..b9aeb388a1 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -406,7 +405,6 @@ static void systemagent_read_resources(struct device *dev) static void systemagent_init(struct device *dev) { - struct soc_power_limits_config *config; u8 bios_reset_cpl, pair; /* Enable Power Aware Interrupt Routing */ @@ -426,8 +424,7 @@ static void systemagent_init(struct device *dev) /* Configure turbo power limits 1ms after reset complete bit */ mdelay(1); - config = config_of_soc(); - set_power_limits(MOBILE_SKU_PL1_TIME_SEC, config); + set_power_limits(28); } static struct device_operations systemagent_ops = { @@ -475,12 +472,6 @@ static void broadwell_enable(struct device *dev) dev->ops = &pci_domain_ops; } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; - } else if (dev->path.type == DEVICE_PATH_PCI) { - /* Handle PCH device enable */ - if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_MINIHD && - (dev->ops == NULL || dev->ops->enable == NULL)) { - broadwell_pch_enable_dev(dev); - } } } diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 24f64b1887..2b862e7e86 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -82,6 +82,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_SUPPORTS_PM_TIMER_EMULATION select FSP_COMPRESS_FSP_S_LZMA select FSP_M_XIP + select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 select GENERIC_GPIO_LIB select HAVE_FSP_GOP select HAVE_FSP_LOGO_SUPPORT @@ -103,6 +104,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG + select SOC_INTEL_COMMON_BLOCK_CNVI select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT @@ -119,6 +121,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT + select SOC_INTEL_COMMON_FSP_RESET select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 20da942f84..61b19894eb 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -58,29 +57,6 @@ static void configure_misc(void) wrmsr(MSR_POWER_CTL, msr); } -/* - * The emulated ACPI timer allows replacing of the ACPI timer - * (PM1_TMR) to have no impart on the system. - */ -static void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - static void configure_c_states(void) { msr_t msr; @@ -135,7 +111,6 @@ void soc_core_init(struct device *cpu) set_aesni_lock(); - /* Enable ACPI Timer Emulation via MSR 0x121 */ enable_pm_timer_emulation(); /* Enable Direct Cache Access */ diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c index 1f7ea3c180..bc5815ac7a 100644 --- a/src/soc/intel/cannonlake/reset.c +++ b/src/soc/intel/cannonlake/reset.c @@ -1,12 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include -#include #include -#include void do_global_reset(void) { @@ -18,17 +15,3 @@ void do_global_reset(void) pmc_global_reset_enable(1); do_full_reset(); } - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 22d350ccdb..9993bceedf 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -27,6 +27,9 @@ romstage-$(CONFIG_TPM_CR50) += tpm_tis.c ramstage-$(CONFIG_TPM_CR50) += tpm_tis.c postcar-$(CONFIG_TPM_CR50) += tpm_tis.c +romstage-$(CONFIG_SOC_INTEL_COMMON_FSP_RESET) += fsp_reset.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_FSP_RESET) += fsp_reset.c + ifeq ($(CONFIG_MMA),y) MMA_BLOBS_PATH = $(call strip_quotes,$(CONFIG_MMA_BLOBS_PATH)) MMA_TEST_NAMES = $(notdir $(wildcard $(MMA_BLOBS_PATH)/tests/*)) diff --git a/src/soc/intel/common/block/cnvi/Kconfig b/src/soc/intel/common/block/cnvi/Kconfig new file mode 100644 index 0000000000..21402ab6a5 --- /dev/null +++ b/src/soc/intel/common/block/cnvi/Kconfig @@ -0,0 +1,4 @@ +config SOC_INTEL_COMMON_BLOCK_CNVI + bool + help + Common CNVI module for Intel PCH diff --git a/src/soc/intel/common/block/cnvi/Makefile.inc b/src/soc/intel/common/block/cnvi/Makefile.inc new file mode 100644 index 0000000000..01b9d1d0e9 --- /dev/null +++ b/src/soc/intel/common/block/cnvi/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CNVI) += cnvi.c diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c new file mode 100644 index 0000000000..0dafb82fa3 --- /dev/null +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static const char *cnvi_wifi_acpi_name(const struct device *dev) +{ + return "CNVW"; +} + +static struct device_operations cnvi_wifi_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &pci_dev_ops_pci, + .scan_bus = scan_static_bus, + .acpi_name = cnvi_wifi_acpi_name, + .acpi_fill_ssdt = acpi_device_write_pci_dev, +}; + +static const unsigned short wifi_pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_CML_LP_CNVI_WIFI, + PCI_DEVICE_ID_INTEL_CML_H_CNVI_WIFI, + PCI_DEVICE_ID_INTEL_CNL_LP_CNVI_WIFI, + PCI_DEVICE_ID_INTEL_CNL_H_CNVI_WIFI, + PCI_DEVICE_ID_INTEL_GLK_CNVI_WIFI, + PCI_DEVICE_ID_INTEL_ICL_CNVI_WIFI, + PCI_DEVICE_ID_INTEL_JSL_CNVI_WIFI_0, + PCI_DEVICE_ID_INTEL_JSL_CNVI_WIFI_1, + PCI_DEVICE_ID_INTEL_JSL_CNVI_WIFI_2, + PCI_DEVICE_ID_INTEL_JSL_CNVI_WIFI_3, + PCI_DEVICE_ID_INTEL_TGL_CNVI_WIFI_0, + PCI_DEVICE_ID_INTEL_TGL_CNVI_WIFI_1, + PCI_DEVICE_ID_INTEL_TGL_CNVI_WIFI_2, + PCI_DEVICE_ID_INTEL_TGL_CNVI_WIFI_3, + 0 +}; + +static const struct pci_driver pch_cnvi_wifi __pci_driver = { + .ops = &cnvi_wifi_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = wifi_pci_device_ids, +}; + +static const char *cnvi_bt_acpi_name(const struct device *dev) +{ + return "CNVB"; +} + +static struct device_operations cnvi_bt_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &pci_dev_ops_pci, + .scan_bus = scan_static_bus, + .acpi_name = cnvi_bt_acpi_name, + .acpi_fill_ssdt = acpi_device_write_pci_dev, +}; + +static const unsigned short bt_pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_0, + PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_1, + PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_2, + PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_3, + 0 +}; + +static const struct pci_driver pch_cnvi_bt __pci_driver = { + .ops = &cnvi_bt_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = bt_pci_device_ids, +}; diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc index deddb67a16..7692076375 100644 --- a/src/soc/intel/common/block/cpu/Makefile.inc +++ b/src/soc/intel/common/block/cpu/Makefile.inc @@ -11,3 +11,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) += mp_init.c +ramstage-$(CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION) += pm_timer_emulation.c diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index b9daf08b2f..04dc5331e1 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -71,7 +71,14 @@ CAR_init_done: jnz .halt_forever /* Setup bootblock stack */ - mov %edx, %esp + movl $_ecar_stack, %esp + /* + * temp_memory_start/end reside in the .bss section, which gets cleared + * below. Save the FSP return value to the stack before writing those + * variables. + */ + push %ecx + push %edx /* clear .bss section as it is not shared */ cld @@ -82,6 +89,11 @@ CAR_init_done: shrl $2, %ecx rep stosl + pop %edx + movl %edx, temp_memory_end + pop %ecx + movl %ecx, temp_memory_start + /* Restore the timestamp from bootblock_crt0.S (ebp:mm1) */ push %ebp movd %mm1, %eax diff --git a/src/soc/intel/common/block/cpu/pm_timer_emulation.c b/src/soc/intel/common/block/cpu/pm_timer_emulation.c new file mode 100644 index 0000000000..8f56da54c5 --- /dev/null +++ b/src/soc/intel/common/block/cpu/pm_timer_emulation.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +void enable_pm_timer_emulation(void) +{ + msr_t msr; + + if (!CONFIG_CPU_XTAL_HZ) + return; + + /* + * The derived frequency is calculated as follows: + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. + */ + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; + /* Set PM1 timer IO port and enable */ + msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | + EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); + wrmsr(MSR_EMULATE_PM_TIMER, msr); +} diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 1cb7d35fb0..a6511982de 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -22,18 +22,21 @@ config SOC_INTEL_CSE_LITE_SKU config SOC_INTEL_CSE_FMAP_NAME string "Name of CSE Region in FMAP" + depends on SOC_INTEL_CSE_LITE_SKU default "SI_ME" help Name of CSE region in FMAP config SOC_INTEL_CSE_RW_CBFS_NAME string "CBFS entry name for CSE RW blob" + depends on SOC_INTEL_CSE_LITE_SKU default "me_rw" help CBFS entry name for Intel CSE CBFS RW blob config SOC_INTEL_CSE_RW_FILE string "Intel CSE CBFS RW path and filename" + depends on SOC_INTEL_CSE_LITE_SKU default "" help Intel CSE CBFS RW blob path and file name diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index d2b00efb2f..4dfbef48f6 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -156,4 +156,10 @@ void cpu_lt_lock_memory(void *unused); /* Get a supported PRMRR size in bytes with respect to users choice */ int get_valid_prmrr_size(void); +/* + * Enable the emulated ACPI timer in case it's not available or to allow + * disabling the PM ACPI timer (PM1_TMR) for power saving. + */ +void enable_pm_timer_emulation(void); + #endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/pmc.h b/src/soc/intel/common/block/include/intelblocks/pmc.h index 75e212740d..329bbe9bd7 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmc.h +++ b/src/soc/intel/common/block/include/intelblocks/pmc.h @@ -51,13 +51,4 @@ int pmc_soc_get_resources(struct pmc_resource_config *cfg); /* API to set ACPI mode */ void pmc_set_acpi_mode(void); -/* - * Returns a reference to the PMC MUX device for the given port number. - * Returns NULL if not found or SoC does not support PMC MUX. - * - * Input: Port number (0-based) - * Output: Const pointer to PMC MUX device - */ -const struct device *soc_get_pmc_mux_device(int port_number); - #endif /* SOC_INTEL_COMMON_BLOCK_PMC_H */ diff --git a/src/soc/intel/common/block/usb4/Kconfig b/src/soc/intel/common/block/usb4/Kconfig index be0b3782b0..fb876e1fd9 100644 --- a/src/soc/intel/common/block/usb4/Kconfig +++ b/src/soc/intel/common/block/usb4/Kconfig @@ -11,3 +11,10 @@ config SOC_INTEL_COMMON_BLOCK_USB4_PCIE help Chip driver for adding PCI ops and SSDT generation for common Intel USB4/Thunderbolt root ports. + +config SOC_INTEL_COMMON_BLOCK_USB4_XHCI + bool + default n + help + Minimal PCI driver for adding PCI ops and SSDT generation for common + Intel USB4/Thunderbolt North XHCI ports. diff --git a/src/soc/intel/common/block/usb4/Makefile.inc b/src/soc/intel/common/block/usb4/Makefile.inc index 89ce426ae2..91f0991534 100644 --- a/src/soc/intel/common/block/usb4/Makefile.inc +++ b/src/soc/intel/common/block/usb4/Makefile.inc @@ -1,2 +1,3 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_USB4) += usb4.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_USB4_PCIE) += pcie.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_USB4_XHCI) += xhci.c diff --git a/src/soc/intel/common/block/usb4/xhci.c b/src/soc/intel/common/block/usb4/xhci.c new file mode 100644 index 0000000000..4fe60dd91a --- /dev/null +++ b/src/soc/intel/common/block/usb4/xhci.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static const char *usb4_xhci_acpi_name(const struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + return "TXHC"; +} + +static struct device_operations usb4_xhci_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &pci_dev_ops_pci, + .scan_bus = scan_static_bus, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = usb4_xhci_acpi_name, +#endif +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_TGP_TCSS_XHCI, + 0 +}; + +static const struct pci_driver usb4_xhci __pci_driver = { + .ops = &usb4_xhci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/soc/intel/common/fsp_reset.c b/src/soc/intel/common/fsp_reset.c new file mode 100644 index 0000000000..e89fe4cc53 --- /dev/null +++ b/src/soc/intel/common/fsp_reset.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void chipset_handle_reset(uint32_t status) +{ + if (status == CONFIG_FSP_STATUS_GLOBAL_RESET) { + printk(BIOS_DEBUG, "GLOBAL RESET!\n"); + global_reset(); + } + + printk(BIOS_ERR, "unhandled reset type %x\n", status); + die("unknown reset type"); +} diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index ba251a8048..b6bac0b9a5 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -138,6 +138,7 @@ #define PCH_DEV_SLOT_LPC 0x1f #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) +#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) #define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) #define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 05077ad316..89da0be2e7 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -16,6 +16,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_SUPPORTS_PM_TIMER_EMULATION select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP + select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 select GENERIC_GPIO_LIB select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE @@ -39,6 +40,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT @@ -50,9 +52,9 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET - select SOC_INTEL_COMMON_BLOCK_CAR select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index 720a295e15..d0fa019ef8 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -17,7 +17,6 @@ #include #include #include -#include #include static void soc_fsp_load(void) @@ -56,25 +55,6 @@ static void configure_misc(void) wrmsr(MSR_POWER_CTL, msr); } -static void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { @@ -91,7 +71,6 @@ void soc_core_init(struct device *cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); /* Enable Direct Cache Access */ diff --git a/src/soc/intel/elkhartlake/reset.c b/src/soc/intel/elkhartlake/reset.c index fe3d7690b5..bc5815ac7a 100644 --- a/src/soc/intel/elkhartlake/reset.c +++ b/src/soc/intel/elkhartlake/reset.c @@ -1,12 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include -#include #include #include #include -#include void do_global_reset(void) { @@ -18,17 +15,3 @@ void do_global_reset(void) pmc_global_reset_enable(1); do_full_reset(); } - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 3b3d4793ee..52e9a745f8 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -16,6 +16,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION select FSP_M_XIP + select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 select GENERIC_GPIO_LIB select HAVE_FSP_GOP select HAVE_INTEL_FSP_REPO @@ -40,7 +41,9 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG + select SOC_INTEL_COMMON_BLOCK_CNVI select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 @@ -50,9 +53,9 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_THERMAL + select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET - select SOC_INTEL_COMMON_BLOCK_CAR select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index ea2b3574b2..1734ba6c30 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -17,7 +17,6 @@ #include #include #include -#include #include static void soc_fsp_load(void) @@ -56,25 +55,6 @@ static void configure_misc(void) wrmsr(MSR_POWER_CTL, msr); } -static void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - static void configure_c_states(void) { msr_t msr; @@ -127,7 +107,6 @@ void soc_core_init(struct device *cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); /* Enable Direct Cache Access */ diff --git a/src/soc/intel/icelake/reset.c b/src/soc/intel/icelake/reset.c index 1f7ea3c180..bc5815ac7a 100644 --- a/src/soc/intel/icelake/reset.c +++ b/src/soc/intel/icelake/reset.c @@ -1,12 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include -#include #include -#include void do_global_reset(void) { @@ -18,17 +15,3 @@ void do_global_reset(void) pmc_global_reset_enable(1); do_full_reset(); } - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index d5adc600bb..e84add0644 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -17,6 +17,7 @@ config CPU_SPECIFIC_OPTIONS select COS_MAPPED_TO_MSB select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP + select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 select GENERIC_GPIO_LIB select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE @@ -38,7 +39,9 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG + select SOC_INTEL_COMMON_BLOCK_CNVI select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT @@ -49,9 +52,9 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET - select SOC_INTEL_COMMON_BLOCK_CAR select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index 312fc7d7af..6518945d8d 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -17,7 +17,6 @@ #include #include #include -#include #include static void soc_fsp_load(void) @@ -56,25 +55,6 @@ static void configure_misc(void) wrmsr(MSR_POWER_CTL, msr); } -static void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { @@ -91,7 +71,6 @@ void soc_core_init(struct device *cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); /* Enable Direct Cache Access */ diff --git a/src/soc/intel/jasperlake/reset.c b/src/soc/intel/jasperlake/reset.c index 1f7ea3c180..bc5815ac7a 100644 --- a/src/soc/intel/jasperlake/reset.c +++ b/src/soc/intel/jasperlake/reset.c @@ -1,12 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include -#include #include -#include void do_global_reset(void) { @@ -18,17 +15,3 @@ void do_global_reset(void) pmc_global_reset_enable(1); do_full_reset(); } - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index dccdebf304..528ef0fd21 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -116,6 +116,13 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Skip the CPU replacement check */ m_cfg->SkipCpuReplacementCheck = config->SkipCpuReplacementCheck; + + /* + * Set GpioOverride + * When GpioOverride is set FSP will not configure any GPIOs + * and rely on GPIO settings programmed before moved to FSP. + */ + m_cfg->GpioOverride = 1; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 2478113c35..20b302db14 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION select FSP_M_XIP + select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 select GENERIC_GPIO_LIB select HAVE_FSP_GOP select HAVE_FSP_LOGO_SUPPORT @@ -63,6 +64,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_THERMAL select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG + select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 1682503d4b..6872c12101 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include @@ -96,29 +95,6 @@ static void configure_c_states(void) wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } -/* - * The emulated ACPI timer allows disabling of the ACPI timer - * (PM1_TMR) to have no impart on the system. - */ -static void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c index 1076ad2ffa..8bf9db5830 100644 --- a/src/soc/intel/skylake/reset.c +++ b/src/soc/intel/skylake/reset.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include -#include #include #include #include @@ -30,17 +28,3 @@ void do_global_reset(void) do_force_global_reset(); } } - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 2b5f0baeb1..ed35bd6f2b 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -14,8 +14,10 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION + select DRIVERS_USB_ACPI select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP + select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 select GENERIC_GPIO_LIB select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE @@ -38,7 +40,9 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG + select SOC_INTEL_COMMON_BLOCK_CNVI select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_DTT @@ -50,9 +54,10 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_BLOCK_USB4_PCIE + select SOC_INTEL_COMMON_BLOCK_USB4_XHCI + select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET - select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 9f3216d95f..53fc528446 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -66,8 +66,7 @@ const char *soc_acpi_name(const struct device *dev) switch (dev->path.pci.devfn) { case SA_DEVFN_ROOT: return "MCHC"; - case SA_DEVFN_CPU_PCIE: return "PEG0"; - case SA_DEVFN_TCSS_XHCI: return "TXHC"; + case SA_DEVFN_CPU_PCIE: return "PEG0"; case SA_DEVFN_TCSS_XDCI: return "TXDC"; case SA_DEVFN_TBT0: return "TRP0"; case SA_DEVFN_TBT1: return "TRP1"; diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb index b60801c347..54f7924b37 100644 --- a/src/soc/intel/tigerlake/chipset.cb +++ b/src/soc/intel/tigerlake/chipset.cb @@ -32,7 +32,25 @@ chip soc/intel/tigerlake device pci 08.0 alias gna off end device pci 09.0 alias npk off end device pci 0a.0 alias crashlog off end - device pci 0d.0 alias north_xhci off end + device pci 0d.0 alias north_xhci off + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias tcss_root_hub off + chip drivers/usb/acpi + device usb 3.0 alias tcss_usb3_port1 off end + end + chip drivers/usb/acpi + device usb 3.1 alias tcss_usb3_port2 off end + end + chip drivers/usb/acpi + device usb 3.2 alias tcss_usb3_port3 off end + end + chip drivers/usb/acpi + device usb 3.3 alias tcss_usb3_port4 off end + end + end + end + end device pci 0d.1 alias north_xdci off end device pci 0d.2 alias tbt_dma0 off end device pci 0d.3 alias tbt_dma1 off end @@ -43,12 +61,58 @@ chip soc/intel/tigerlake device pci 12.0 alias ish off end device pci 12.6 alias gspi2 off end device pci 13.0 alias gspi3 off end - device pci 14.0 alias south_xhci off end + device pci 14.0 alias south_xhci off + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias xhci_root_hub off + chip drivers/usb/acpi + device usb 2.0 alias usb2_port1 off end + end + chip drivers/usb/acpi + device usb 2.1 alias usb2_port2 off end + end + chip drivers/usb/acpi + device usb 2.2 alias usb2_port3 off end + end + chip drivers/usb/acpi + device usb 2.3 alias usb2_port4 off end + end + chip drivers/usb/acpi + device usb 2.4 alias usb2_port5 off end + end + chip drivers/usb/acpi + device usb 2.5 alias usb2_port6 off end + end + chip drivers/usb/acpi + device usb 2.6 alias usb2_port7 off end + end + chip drivers/usb/acpi + device usb 2.7 alias usb2_port8 off end + end + chip drivers/usb/acpi + device usb 2.8 alias usb2_port9 off end + end + chip drivers/usb/acpi + device usb 2.9 alias usb2_port10 off end + end + chip drivers/usb/acpi + device usb 3.0 alias usb3_port1 off end + end + chip drivers/usb/acpi + device usb 3.1 alias usb3_port2 off end + end + chip drivers/usb/acpi + device usb 3.2 alias usb3_port3 off end + end + chip drivers/usb/acpi + device usb 3.3 alias usb3_port4 off end + end + end + end + end device pci 14.1 alias south_xdci off end device pci 14.2 alias shared_ram off end - chip drivers/wifi/generic - device pci 14.3 alias cnvi_wifi off end - end + device pci 14.3 alias cnvi_wifi off end device pci 15.0 alias i2c0 off end device pci 15.1 alias i2c1 off end device pci 15.2 alias i2c2 off end diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index d7234e7191..36dfa1b738 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -23,7 +23,6 @@ #include #include #include -#include #include static void soc_fsp_load(void) @@ -62,25 +61,6 @@ static void configure_misc(void) wrmsr(MSR_POWER_CTL, msr); } -static void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { @@ -97,7 +77,6 @@ void soc_core_init(struct device *cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); /* Enable Direct Cache Access */ diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index f2f8a06260..dbf3671af7 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -126,28 +126,6 @@ static void soc_pmc_fill_ssdt(const struct device *dev) dev_path(dev)); } -/* FIXME: Rewrite loop below without this. */ -extern struct chip_operations drivers_intel_pmc_mux_ops; - -/* By default, TGL uses the PMC MUX for all ports, so port_number is unused */ -const struct device *soc_get_pmc_mux_device(int port_number) -{ - const struct device *pmc; - struct device *child; - - child = NULL; - pmc = pcidev_path_on_root(PCH_DEVFN_PMC); - if (!pmc || !pmc->link_list) - return NULL; - - while ((child = dev_bus_each_child(pmc->link_list, child)) != NULL) - if (child->chip_ops == &drivers_intel_pmc_mux_ops) - break; - - /* child will either be the correct device or NULL if not found */ - return child; -} - static void soc_acpi_mode_init(struct device *dev) { /* diff --git a/src/soc/intel/tigerlake/reset.c b/src/soc/intel/tigerlake/reset.c index 1f7ea3c180..bc5815ac7a 100644 --- a/src/soc/intel/tigerlake/reset.c +++ b/src/soc/intel/tigerlake/reset.c @@ -1,12 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include -#include #include -#include void do_global_reset(void) { @@ -18,17 +15,3 @@ void do_global_reset(void) pmc_global_reset_enable(1); do_full_reset(); } - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index ffc55b6d4a..40a1020c5c 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -7,8 +7,9 @@ subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c -ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c ramstage.c +ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c ramstage.c chip_common.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c postcar-y += spi.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/acpi.c similarity index 89% rename from src/soc/intel/xeon_sp/cpx/acpi.c rename to src/soc/intel/xeon_sp/acpi.c index 3066dda22e..acf030b450 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -1,27 +1,25 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include #include #include -#include #include -#include -#include -#include -#include -#include -#include -#include #include -#include -#include +#include +#include +#include #include #include -#include -#include -#include #include -#include #include +#include +#include + +acpi_cstate_t *soc_get_cstate_map(size_t *entries) +{ + *entries = 0; + return NULL; +} static int acpi_sci_irq(void) { @@ -79,10 +77,16 @@ unsigned long acpi_fill_madt(unsigned long current) int cur_index; struct iiostack_resource stack_info = {0}; - /* With CPX-SP FSP, PCH IOAPIC is allocated with first 120 GSIs. */ - int gsi_bases[] = { 0, 0x78, 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 }; - int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 }; + /* With XEON-SP FSP, PCH IOAPIC is allocated with first 120 GSIs. */ +#if (CONFIG(SOC_INTEL_COOPERLAKE_SP)) + const int gsi_bases[] = { 0, 0x78, 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 }; + const int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 }; +#endif +#if (CONFIG(SOC_INTEL_SKYLAKE_SP)) + const int gsi_bases[] = { 0, 0x18, 0x20, 0x28, 0x30, 0x48, 0x50, 0x58, 0x60 }; + const int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 }; +#endif /* Local APICs */ current = xeonsp_acpi_create_madt_lapics(current); @@ -184,7 +188,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) } unsigned long southbridge_write_acpi_tables(const struct device *device, - unsigned long current, struct acpi_rsdp *rsdp) + unsigned long current, + struct acpi_rsdp *rsdp) { current = acpi_write_hpet(device, current, rsdp); current = (ALIGN(current, 16)); @@ -198,7 +203,7 @@ void southbridge_inject_dsdt(const struct device *device) gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (!gnvs) { - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, 0x2000); + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) memset(gnvs, 0, sizeof(*gnvs)); } @@ -237,6 +242,12 @@ int calculate_power(int tdp, int p1_ratio, int ratio) return (int)power; } +acpi_tstate_t *soc_get_tss_table(int *entries) +{ + *entries = 0; + return NULL; +} + void generate_cpu_entries(const struct device *device) { int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS; diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index f6653e2034..5adda44d93 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -10,6 +10,7 @@ #include #include #include +#include const FSPT_UPD temp_ram_init_params = { .FspUpdHeader = { @@ -54,5 +55,7 @@ void bootblock_soc_init(void) { if (CONFIG(BOOTBLOCK_CONSOLE)) printk(BIOS_DEBUG, "FSP TempRamInit successful...\n"); + if (CONFIG(FSP_CAR)) + report_fspt_output(); bootblock_pch_init(); } diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c new file mode 100644 index 0000000000..5c78780656 --- /dev/null +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -0,0 +1,527 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include + +struct pci_resource { + struct device *dev; + struct resource *res; + struct pci_resource *next; +}; + +struct stack_dev_resource { + uint8_t align; + struct pci_resource *children; + struct stack_dev_resource *next; +}; + +typedef enum { + RES_TYPE_IO = 0, + RES_TYPE_NONPREF_MEM, + RES_TYPE_PREF_MEM, + MAX_RES_TYPES +} RES_TYPE; + +static RES_TYPE get_res_type(uint64_t flags) +{ + if (flags & IORESOURCE_IO) + return RES_TYPE_IO; + if (flags & IORESOURCE_MEM) { + if (flags & IORESOURCE_PREFETCH) { + printk(BIOS_DEBUG, "%s:%d flags: 0x%llx\n", __func__, __LINE__, flags); + return RES_TYPE_PREF_MEM; + } + /* both 64-bit and 32-bit use below 4GB address space */ + return RES_TYPE_NONPREF_MEM; + } + printk(BIOS_ERR, "Invalid resource type 0x%llx\n", flags); + die(""); +} + +static bool need_assignment(uint64_t flags) +{ + if (flags & (IORESOURCE_STORED | IORESOURCE_RESERVE | IORESOURCE_FIXED | + IORESOURCE_ASSIGNED)) + return false; + else + return true; +} + +static uint64_t get_resource_base(STACK_RES *stack, RES_TYPE res_type) +{ + if (res_type == RES_TYPE_IO) { + assert(stack->PciResourceIoBase <= stack->PciResourceIoLimit); + return stack->PciResourceIoBase; + } + if (res_type == RES_TYPE_NONPREF_MEM) { + assert(stack->PciResourceMem32Base <= stack->PciResourceMem32Limit); + return stack->PciResourceMem32Base; + } + assert(stack->PciResourceMem64Base <= stack->PciResourceMem64Limit); + return stack->PciResourceMem64Base; +} + +static void set_resource_base(STACK_RES *stack, RES_TYPE res_type, uint64_t base) +{ + if (res_type == RES_TYPE_IO) { + assert(base <= (stack->PciResourceIoLimit + 1)); + stack->PciResourceIoBase = base; + } else if (res_type == RES_TYPE_NONPREF_MEM) { + assert(base <= (stack->PciResourceMem32Limit + 1)); + stack->PciResourceMem32Base = base; + } else { + assert(base <= (stack->PciResourceMem64Limit + 1)); + stack->PciResourceMem64Base = base; + } +} + +static void assign_stack_resources(struct iiostack_resource *stack_list, + struct device *dev, struct resource *bridge); + +void xeonsp_pci_domain_scan_bus(struct device *dev) +{ + DEV_FUNC_ENTER(dev); + struct bus *link = dev->link_list; + + printk(BIOS_SPEW, "%s:%s scanning buses under device %s\n", + __FILE__, __func__, dev_path(dev)); + while (link != NULL) { + if (link->secondary == 0) { // scan only PSTACK buses + struct device *d; + for (d = link->children; d; d = d->sibling) + pci_probe_dev(d, link, d->path.pci.devfn); + scan_bridges(link); + } else { + pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff); + } + link = link->next; + } + DEV_FUNC_EXIT(dev); +} + +static void xeonsp_pci_dev_iterator(struct bus *bus, + void (*dev_iterator)(struct device *, void *), + void (*res_iterator)(struct device *, struct resource *, void *), + void *data) +{ + struct device *curdev; + struct resource *res; + + /* Walk through all devices and find which resources they need. */ + for (curdev = bus->children; curdev; curdev = curdev->sibling) { + struct bus *link; + + if (!curdev->enabled) + continue; + + if (!curdev->ops || !curdev->ops->read_resources) { + if (curdev->path.type != DEVICE_PATH_APIC) + printk(BIOS_ERR, "%s missing read_resources\n", + dev_path(curdev)); + continue; + } + + if (dev_iterator) + dev_iterator(curdev, data); + + if (res_iterator) { + for (res = curdev->resource_list; res; res = res->next) + res_iterator(curdev, res, data); + } + + /* Read in the resources behind the current device's links. */ + for (link = curdev->link_list; link; link = link->next) + xeonsp_pci_dev_iterator(link, dev_iterator, res_iterator, data); + } +} + +static void xeonsp_pci_dev_read_resources(struct device *dev, void *data) +{ + post_log_path(dev); + dev->ops->read_resources(dev); +} + +static void xeonsp_pci_dev_dummy_func(struct device *dev) +{ +} + +static void xeonsp_reset_pci_op(struct device *dev, void *data) +{ + if (dev->ops) + dev->ops->read_resources = xeonsp_pci_dev_dummy_func; +} + +static STACK_RES *find_stack_for_bus(struct iiostack_resource *info, uint8_t bus) +{ + for (int i = 0; i < info->no_of_stacks; ++i) { + if (bus >= info->res[i].BusBase && bus <= info->res[i].BusLimit) + return &info->res[i]; + } + return NULL; +} + +static void add_res_to_stack(struct stack_dev_resource **root, + struct device *dev, struct resource *res) +{ + struct stack_dev_resource *cur = *root; + while (cur) { + if (cur->align == res->align || cur->next == NULL) /* equal or last record */ + break; + else if (cur->align > res->align) { + if (cur->next->align < res->align) /* need to insert new record here */ + break; + cur = cur->next; + } else { + break; + } + } + + struct stack_dev_resource *nr; + if (!cur || cur->align != res->align) { /* need to add new record */ + nr = malloc(sizeof(struct stack_dev_resource)); + if (nr == 0) + die("assign_resource_to_stack(): out of memory.\n"); + memset(nr, 0, sizeof(struct stack_dev_resource)); + nr->align = res->align; + if (!cur) { + *root = nr; /* head node */ + } else if (cur->align > nr->align) { + if (cur->next == NULL) { + cur->next = nr; + } else { + nr->next = cur->next; + cur->next = nr; + } + } else { /* insert in the beginning */ + nr->next = cur; + *root = nr; + } + } else { + nr = cur; + } + + assert(nr != NULL && nr->align == res->align); + + struct pci_resource *npr = malloc(sizeof(struct pci_resource)); + if (npr == NULL) + die("%s: out of memory.\n", __func__); + npr->res = res; + npr->dev = dev; + npr->next = NULL; + + if (nr->children == NULL) { + nr->children = npr; + } else { + struct pci_resource *pr = nr->children; + while (pr->next != NULL) + pr = pr->next; + pr->next = npr; + } +} + +static void reserve_dev_resources(STACK_RES *stack, RES_TYPE res_type, + struct stack_dev_resource *res_root, struct resource *bridge) +{ + uint8_t align; + uint64_t orig_base, base; + + orig_base = get_resource_base(stack, res_type); + + align = 0; + base = orig_base; + int first = 1; + while (res_root) { /* loop through all devices grouped by alignment requirements */ + struct pci_resource *pr = res_root->children; + while (pr) { + if (first) { + if (bridge) { /* takes highest alignment */ + if (bridge->align < pr->res->align) + bridge->align = pr->res->align; + orig_base = ALIGN_UP(orig_base, 1 << bridge->align); + } else { + orig_base = ALIGN_UP(orig_base, 1 << pr->res->align); + } + base = orig_base; + + if (bridge) + bridge->base = base; + pr->res->base = base; + first = 0; + } else { + pr->res->base = ALIGN_UP(base, 1 << pr->res->align); + } + pr->res->limit = pr->res->base + pr->res->size - 1; + base = pr->res->limit + 1; + pr->res->flags |= (IORESOURCE_ASSIGNED); + pr = pr->next; + } + res_root = res_root->next; + } + + if (bridge) { + /* this bridge doesn't have any resources, will set it to default window */ + if (first) { + orig_base = ALIGN_UP(orig_base, 1 << bridge->align); + bridge->base = orig_base; + base = orig_base + (1ULL << bridge->gran); + } + + bridge->size = ALIGN_UP(base, 1 << bridge->align) - bridge->base; + + bridge->limit = bridge->base + bridge->size - 1; + bridge->flags |= (IORESOURCE_ASSIGNED); + base = bridge->limit + 1; + } + + set_resource_base(stack, res_type, base); +} + +static void reclaim_resource_mem(struct stack_dev_resource *res_root) +{ + while (res_root) { /* loop through all devices grouped by alignment requirements */ + /* free pci_resource */ + struct pci_resource *pr = res_root->children; + while (pr) { + struct pci_resource *dpr = pr; + pr = pr->next; + free(dpr); + } + + /* free stack_dev_resource */ + struct stack_dev_resource *ddr = res_root; + res_root = res_root->next; + free(ddr); + } +} + +static void assign_bridge_resources(struct iiostack_resource *stack_list, + struct device *dev, struct resource *bridge) +{ + struct resource *res; + if (!dev->enabled) + return; + + for (res = dev->resource_list; res; res = res->next) { + if (!(res->flags & IORESOURCE_BRIDGE) || + (bridge && (get_res_type(bridge->flags) != get_res_type(res->flags)))) + continue; + + assign_stack_resources(stack_list, dev, res); + + if (!bridge) + continue; + + /* for 1st time update, overlading IORESOURCE_ASSIGNED */ + if (!(bridge->flags & IORESOURCE_ASSIGNED)) { + bridge->base = res->base; + bridge->limit = res->limit; + bridge->flags |= (IORESOURCE_ASSIGNED); + } else { + /* update bridge range from child bridge range */ + if (res->base < bridge->base) + bridge->base = res->base; + if (res->limit > bridge->limit) + bridge->limit = res->limit; + } + bridge->size = (bridge->limit - bridge->base + 1); + } +} + +static void assign_stack_resources(struct iiostack_resource *stack_list, + struct device *dev, struct resource *bridge) +{ + struct bus *bus; + + /* Read in the resources behind the current device's links. */ + for (bus = dev->link_list; bus; bus = bus->next) { + struct device *curdev; + STACK_RES *stack; + + /* get IIO stack for this bus */ + stack = find_stack_for_bus(stack_list, bus->secondary); + assert(stack != NULL); + + /* Assign resources to bridge */ + for (curdev = bus->children; curdev; curdev = curdev->sibling) + assign_bridge_resources(stack_list, curdev, bridge); + + /* Pick non-bridged resources for resource allocation for each resource type */ + RES_TYPE res_types[MAX_RES_TYPES] = { + RES_TYPE_IO, + RES_TYPE_NONPREF_MEM, + RES_TYPE_PREF_MEM + }; + + uint8_t no_res_types = MAX_RES_TYPES; + + /* if it is a bridge, only process matching bridge resource type */ + if (bridge) { + res_types[0] = get_res_type(bridge->flags); + no_res_types = 1; + } + + printk(BIOS_DEBUG, "%s:%d no_res_types: %d\n", __func__, __LINE__, + no_res_types); + + /* Process each resource type */ + for (int rt = 0; rt < no_res_types; ++rt) { + struct stack_dev_resource *res_root = NULL; + printk(BIOS_DEBUG, "%s:%d rt: %d\n", __func__, __LINE__, rt); + for (curdev = bus->children; curdev; curdev = curdev->sibling) { + struct resource *res; + printk(BIOS_DEBUG, "%s:%d dev: %s\n", + __func__, __LINE__, dev_path(curdev)); + if (!curdev->enabled) + continue; + + for (res = curdev->resource_list; res; res = res->next) { + printk(BIOS_DEBUG, "%s:%d dev: %s, flags: 0x%lx\n", + __func__, __LINE__, + dev_path(curdev), res->flags); + if (res->size == 0 || + get_res_type(res->flags) != res_types[rt] || + (res->flags & IORESOURCE_BRIDGE) || + !need_assignment(res->flags)) + continue; + else + add_res_to_stack(&res_root, curdev, res); + } + } + + /* Allocate resources and update bridge range */ + if (res_root || (bridge && !(bridge->flags & IORESOURCE_ASSIGNED))) { + reserve_dev_resources(stack, res_types[rt], res_root, bridge); + reclaim_resource_mem(res_root); + } + } + } +} + +static void xeonsp_pci_domain_read_resources(struct device *dev) +{ + struct bus *link; + + DEV_FUNC_ENTER(dev); + + pci_domain_read_resources(dev); + + /* + * Walk through all devices in this domain and read resources. + * Since there is no callback when read resource operation is + * complete for all devices, domain read resource function initiates + * read resources for all devices and swaps read resource operation + * with dummy function to avoid warning. + */ + for (link = dev->link_list; link; link = link->next) + xeonsp_pci_dev_iterator(link, xeonsp_pci_dev_read_resources, NULL, NULL); + + for (link = dev->link_list; link; link = link->next) + xeonsp_pci_dev_iterator(link, xeonsp_reset_pci_op, NULL, NULL); + + struct iiostack_resource stack_info = {0}; + uint8_t pci64bit_alloc_flag = get_iiostack_info(&stack_info); + if (!pci64bit_alloc_flag) { + /* + * Split 32 bit address space between prefetchable and + * non-prefetchable windows + */ + for (int s = 0; s < stack_info.no_of_stacks; ++s) { + STACK_RES *res = &stack_info.res[s]; + uint64_t length = (res->PciResourceMem32Limit - + res->PciResourceMem32Base + 1)/2; + res->PciResourceMem64Limit = res->PciResourceMem32Limit; + res->PciResourceMem32Limit = (res->PciResourceMem32Base + length - 1); + res->PciResourceMem64Base = res->PciResourceMem32Limit + 1; + } + } + + /* assign resources */ + assign_stack_resources(&stack_info, dev, NULL); + + DEV_FUNC_EXIT(dev); +} + +static void reset_resource_to_unassigned(struct device *dev, struct resource *res, void *data) +{ + if ((res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) && + !(res->flags & (IORESOURCE_FIXED | IORESOURCE_RESERVE))) { + res->flags &= ~IORESOURCE_ASSIGNED; + } +} + +void xeonsp_pci_domain_set_resources(struct device *dev) +{ + DEV_FUNC_ENTER(dev); + + print_resource_tree(dev, BIOS_SPEW, "Before xeonsp pci domain set resource"); + + /* reset bus 0 dev resource assignment - need to change them to FSP IIOStack window */ + xeonsp_pci_dev_iterator(dev->link_list, NULL, reset_resource_to_unassigned, NULL); + + /* update dev resources based on IIOStack IO/Mem32/Mem64 windows */ + xeonsp_pci_domain_read_resources(dev); + + struct bus *link = dev->link_list; + while (link != NULL) { + assign_resources(link); + link = link->next; + } + + print_resource_tree(dev, BIOS_SPEW, "After xeonsp pci domain set resource"); + + DEV_FUNC_EXIT(dev); +} + +/* Attach IIO stack bus numbers with dummy device to PCI DOMAIN 0000 device */ +void attach_iio_stacks(struct device *dev) +{ + struct bus *iiostack_bus; + struct device dummy; + struct iiostack_resource stack_info = {0}; + + DEV_FUNC_ENTER(dev); + + get_iiostack_info(&stack_info); + for (int s = 0; s < stack_info.no_of_stacks; ++s) { + /* only non zero bus no. needs to be enumerated */ + if (stack_info.res[s].BusBase == 0) + continue; + + iiostack_bus = malloc(sizeof(struct bus)); + if (iiostack_bus == NULL) + die("%s: out of memory.\n", __func__); + memset(iiostack_bus, 0, sizeof(*iiostack_bus)); + memcpy(iiostack_bus, dev->bus, sizeof(*iiostack_bus)); + iiostack_bus->secondary = stack_info.res[s].BusBase; + iiostack_bus->subordinate = stack_info.res[s].BusBase; + iiostack_bus->dev = NULL; + iiostack_bus->children = NULL; + iiostack_bus->next = NULL; + iiostack_bus->link_num = 1; + + dummy.bus = iiostack_bus; + dummy.path.type = DEVICE_PATH_PCI; + dummy.path.pci.devfn = 0; + uint32_t id = pci_read_config32(&dummy, PCI_VENDOR_ID); + if (id == 0xffffffff) + printk(BIOS_WARNING, "IIO Stack device %s not visible\n", + dev_path(&dummy)); + + if (dev->link_list == NULL) { + dev->link_list = iiostack_bus; + } else { + struct bus *nlink = dev->link_list; + while (nlink->next != NULL) + nlink = nlink->next; + nlink->next = iiostack_bus; + } + } + + DEV_FUNC_EXIT(dev); +} diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index 79a83b5416..b2e653e50e 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -12,7 +12,7 @@ romstage-y += romstage.c ddr.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c -ramstage-y += chip.c acpi.c cpu.c soc_util.c ramstage.c soc_acpi.c +ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index c5a8c1cb1c..0049616223 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -1,497 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include +#include #include #include -#include #include #include -#include #include +#include #include #include -#include #include -#include - -/* C620 IOAPIC has 120 redirection entries */ -#define C620_IOAPIC_REDIR_ENTRIES 120 - -struct pci_resource { - struct device *dev; - struct resource *res; - struct pci_resource *next; -}; - -struct stack_dev_resource { - uint8_t align; - struct pci_resource *children; - struct stack_dev_resource *next; -}; - -typedef enum { - RES_TYPE_IO = 0, - RES_TYPE_NONPREF_MEM, - RES_TYPE_PREF_MEM, - MAX_RES_TYPES -} ResType; - -static ResType get_res_type(uint64_t flags) -{ - if (flags & IORESOURCE_IO) - return RES_TYPE_IO; - if (flags & IORESOURCE_MEM) { - if (flags & IORESOURCE_PREFETCH) { - printk(BIOS_DEBUG, "%s:%d flags: 0x%llx\n", __func__, __LINE__, flags); - return RES_TYPE_PREF_MEM; - } - /* both 64-bit and 32-bit use below 4GB address space */ - return RES_TYPE_NONPREF_MEM; - } - printk(BIOS_ERR, "Invalid resource type 0x%llx\n", flags); - die("Invalida resource type"); -} - -static bool need_assignment(uint64_t flags) -{ - if (flags & (IORESOURCE_STORED | IORESOURCE_RESERVE | IORESOURCE_FIXED | - IORESOURCE_ASSIGNED)) - return false; - else - return true; -} - -static uint64_t get_resource_base(STACK_RES *stack, ResType res_type) -{ - if (res_type == RES_TYPE_IO) { - assert(stack->PciResourceIoBase <= stack->PciResourceIoLimit); - return stack->PciResourceIoBase; - } - if (res_type == RES_TYPE_NONPREF_MEM) { - assert(stack->PciResourceMem32Base <= stack->PciResourceMem32Limit); - return stack->PciResourceMem32Base; - } - assert(stack->PciResourceMem64Base <= stack->PciResourceMem64Limit); - return stack->PciResourceMem64Base; -} - -static void set_resource_base(STACK_RES *stack, ResType res_type, uint64_t base) -{ - if (res_type == RES_TYPE_IO) { - assert(base <= (stack->PciResourceIoLimit + 1)); - stack->PciResourceIoBase = base; - } else if (res_type == RES_TYPE_NONPREF_MEM) { - assert(base <= (stack->PciResourceMem32Limit + 1)); - stack->PciResourceMem32Base = base; - } else { - assert(base <= (stack->PciResourceMem64Limit + 1)); - stack->PciResourceMem64Base = base; - } -} - -static void assign_stack_resources(struct iiostack_resource *stack_list, - struct device *dev, struct resource *bridge); - -static void xeonsp_cpx_pci_domain_scan_bus(struct device *dev) -{ - DEV_FUNC_ENTER(dev); - struct bus *link = dev->link_list; - - printk(BIOS_SPEW, "%s:%s scanning buses under device %s\n", - __FILE__, __func__, dev_path(dev)); - while (link != NULL) { - if (link->secondary == 0) { // scan only PSTACK buses - struct device *d; - for (d = link->children; d; d = d->sibling) - pci_probe_dev(d, link, d->path.pci.devfn); - scan_bridges(link); - } else { - pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff); - } - link = link->next; - } - DEV_FUNC_EXIT(dev); -} - -static void xeonsp_pci_dev_iterator(struct bus *bus, - void (*dev_iterator)(struct device *, void *), - void (*res_iterator)(struct device *, struct resource *, void *), - void *data) -{ - struct device *curdev; - struct resource *res; - - /* Walk through all devices and find which resources they need. */ - for (curdev = bus->children; curdev; curdev = curdev->sibling) { - struct bus *link; - - if (!curdev->enabled) - continue; - - if (!curdev->ops || !curdev->ops->read_resources) { - if (curdev->path.type != DEVICE_PATH_APIC) - printk(BIOS_ERR, "%s missing read_resources\n", - dev_path(curdev)); - continue; - } - - if (dev_iterator) - dev_iterator(curdev, data); - - if (res_iterator) { - for (res = curdev->resource_list; res; res = res->next) - res_iterator(curdev, res, data); - } - - /* Read in the resources behind the current device's links. */ - for (link = curdev->link_list; link; link = link->next) - xeonsp_pci_dev_iterator(link, dev_iterator, res_iterator, data); - } -} - -static void xeonsp_pci_dev_read_resources(struct device *dev, void *data) -{ - post_log_path(dev); - dev->ops->read_resources(dev); -} - -static void xeonsp_pci_dev_dummy_func(struct device *dev) -{ -} - -static void xeonsp_reset_pci_op(struct device *dev, void *data) -{ - if (dev->ops) - dev->ops->read_resources = xeonsp_pci_dev_dummy_func; -} - -static STACK_RES *find_stack_for_bus(struct iiostack_resource *info, uint8_t bus) -{ - for (int i = 0; i < info->no_of_stacks; ++i) { - if (bus >= info->res[i].BusBase && bus <= info->res[i].BusLimit) - return &info->res[i]; - } - return NULL; -} - -static void add_res_to_stack(struct stack_dev_resource **root, - struct device *dev, struct resource *res) -{ - struct stack_dev_resource *cur = *root; - while (cur) { - if (cur->align == res->align || cur->next == NULL) /* equal or last record */ - break; - else if (cur->align > res->align) { - if (cur->next->align < res->align) /* need to insert new record here */ - break; - cur = cur->next; - } else { - break; - } - } - - struct stack_dev_resource *nr; - if (!cur || cur->align != res->align) { /* need to add new record */ - nr = malloc(sizeof(struct stack_dev_resource)); - if (nr == 0) - die("assign_resource_to_stack(): out of memory.\n"); - memset(nr, 0, sizeof(struct stack_dev_resource)); - nr->align = res->align; - if (!cur) { - *root = nr; /* head node */ - } else if (cur->align > nr->align) { - if (cur->next == NULL) { - cur->next = nr; - } else { - nr->next = cur->next; - cur->next = nr; - } - } else { /* insert in the beginning */ - nr->next = cur; - *root = nr; - } - } else { - nr = cur; - } - - assert(nr != NULL && nr->align == res->align); - - struct pci_resource *npr = malloc(sizeof(struct pci_resource)); - if (npr == NULL) - die("%s: out of memory.\n", __func__); - npr->res = res; - npr->dev = dev; - npr->next = NULL; - - if (nr->children == NULL) { - nr->children = npr; - } else { - struct pci_resource *pr = nr->children; - while (pr->next != NULL) - pr = pr->next; - pr->next = npr; - } -} - -static void reserve_dev_resources(STACK_RES *stack, ResType res_type, - struct stack_dev_resource *res_root, struct resource *bridge) -{ - uint8_t align; - uint64_t orig_base, base; - - orig_base = get_resource_base(stack, res_type); - - align = 0; - base = orig_base; - int first = 1; - while (res_root) { /* loop through all devices grouped by alignment requirements */ - struct pci_resource *pr = res_root->children; - while (pr) { - if (first) { - if (bridge) { /* takes highest alignment */ - if (bridge->align < pr->res->align) - bridge->align = pr->res->align; - orig_base = ALIGN_UP(orig_base, 1 << bridge->align); - } else { - orig_base = ALIGN_UP(orig_base, 1 << pr->res->align); - } - base = orig_base; - - if (bridge) - bridge->base = base; - pr->res->base = base; - first = 0; - } else { - pr->res->base = ALIGN_UP(base, 1 << pr->res->align); - } - pr->res->limit = pr->res->base + pr->res->size - 1; - base = pr->res->limit + 1; - pr->res->flags |= (IORESOURCE_ASSIGNED); - pr = pr->next; - } - res_root = res_root->next; - } - - if (bridge) { - /* this bridge doesn't have any resources, will set it to default window */ - if (first) { - orig_base = ALIGN_UP(orig_base, 1 << bridge->align); - bridge->base = orig_base; - base = orig_base + (1ULL << bridge->gran); - } - - bridge->size = ALIGN_UP(base, 1 << bridge->align) - bridge->base; - - bridge->limit = bridge->base + bridge->size - 1; - bridge->flags |= (IORESOURCE_ASSIGNED); - base = bridge->limit + 1; - } - - set_resource_base(stack, res_type, base); -} - -static void reclaim_resource_mem(struct stack_dev_resource *res_root) -{ - while (res_root) { /* loop through all devices grouped by alignment requirements */ - /* free pci_resource */ - struct pci_resource *pr = res_root->children; - while (pr) { - struct pci_resource *dpr = pr; - pr = pr->next; - free(dpr); - } - - /* free stack_dev_resource */ - struct stack_dev_resource *ddr = res_root; - res_root = res_root->next; - free(ddr); - } -} - -static void assign_bridge_resources(struct iiostack_resource *stack_list, - struct device *dev, struct resource *bridge) -{ - struct resource *res; - if (!dev->enabled) - return; - - for (res = dev->resource_list; res; res = res->next) { - if (!(res->flags & IORESOURCE_BRIDGE) || - (bridge && (get_res_type(bridge->flags) != get_res_type(res->flags)))) - continue; - - assign_stack_resources(stack_list, dev, res); - - if (!bridge) - continue; - - /* for 1st time update, overlading IORESOURCE_ASSIGNED */ - if (!(bridge->flags & IORESOURCE_ASSIGNED)) { - bridge->base = res->base; - bridge->limit = res->limit; - bridge->flags |= (IORESOURCE_ASSIGNED); - } else { - /* update bridge range from child bridge range */ - if (res->base < bridge->base) - bridge->base = res->base; - if (res->limit > bridge->limit) - bridge->limit = res->limit; - } - bridge->size = (bridge->limit - bridge->base + 1); - } -} - -static void assign_stack_resources(struct iiostack_resource *stack_list, - struct device *dev, struct resource *bridge) -{ - struct bus *bus; - - /* Read in the resources behind the current device's links. */ - for (bus = dev->link_list; bus; bus = bus->next) { - struct device *curdev; - STACK_RES *stack; - - /* get IIO stack for this bus */ - stack = find_stack_for_bus(stack_list, bus->secondary); - assert(stack != NULL); - - /* Assign resources to bridge */ - for (curdev = bus->children; curdev; curdev = curdev->sibling) - assign_bridge_resources(stack_list, curdev, bridge); - - /* Pick non-bridged resources for resource allocation for each resource type */ - ResType res_types[MAX_RES_TYPES] = { - RES_TYPE_IO, - RES_TYPE_NONPREF_MEM, - RES_TYPE_PREF_MEM - }; - - uint8_t no_res_types = MAX_RES_TYPES; - - /* if it is a bridge, only process matching brigge resource type */ - if (bridge) { - res_types[0] = get_res_type(bridge->flags); - no_res_types = 1; - } - - printk(BIOS_DEBUG, "%s:%d no_res_types: %d\n", __func__, __LINE__, - no_res_types); - - /* Process each resource type */ - for (int rt = 0; rt < no_res_types; ++rt) { - struct stack_dev_resource *res_root = NULL; - printk(BIOS_DEBUG, "%s:%d rt: %d\n", __func__, __LINE__, rt); - for (curdev = bus->children; curdev; curdev = curdev->sibling) { - struct resource *res; - printk(BIOS_DEBUG, "%s:%d dev: %s\n", - __func__, __LINE__, dev_path(curdev)); - if (!curdev->enabled) - continue; - - for (res = curdev->resource_list; res; res = res->next) { - printk(BIOS_DEBUG, "%s:%d dev: %s, flags: 0x%lx\n", - __func__, __LINE__, - dev_path(curdev), res->flags); - if (res->size == 0 || - get_res_type(res->flags) != res_types[rt] || - (res->flags & IORESOURCE_BRIDGE) || - !need_assignment(res->flags)) - continue; - else - add_res_to_stack(&res_root, curdev, res); - } - } - - /* Allocate resources and update bridge range */ - if (res_root || (bridge && !(bridge->flags & IORESOURCE_ASSIGNED))) { - reserve_dev_resources(stack, res_types[rt], res_root, bridge); - reclaim_resource_mem(res_root); - } - } - } -} - -static void xeonsp_pci_domain_read_resources(struct device *dev) -{ - struct bus *link; - - DEV_FUNC_ENTER(dev); - - pci_domain_read_resources(dev); - - /* - * Walk through all devices in this domain and read resources. - * Since there is no callback when read resource operation is - * complete for all devices, domain read resource function initiates - * read resources for all devices and swaps read resource operation - * with dummy function to avoid warning. - */ - for (link = dev->link_list; link; link = link->next) - xeonsp_pci_dev_iterator(link, xeonsp_pci_dev_read_resources, NULL, NULL); - - for (link = dev->link_list; link; link = link->next) - xeonsp_pci_dev_iterator(link, xeonsp_reset_pci_op, NULL, NULL); - - struct iiostack_resource stack_info = {0}; - uint8_t pci64bit_alloc_flag = get_iiostack_info(&stack_info); - if (!pci64bit_alloc_flag) { - /* - * Split 32 bit address space between prefetchable and - * non-prefetchable windows - */ - for (int s = 0; s < stack_info.no_of_stacks; ++s) { - STACK_RES *res = &stack_info.res[s]; - uint64_t length = (res->PciResourceMem32Limit - - res->PciResourceMem32Base + 1)/2; - res->PciResourceMem64Limit = res->PciResourceMem32Limit; - res->PciResourceMem32Limit = (res->PciResourceMem32Base + length - 1); - res->PciResourceMem64Base = res->PciResourceMem32Limit + 1; - } - } - - /* assign resources */ - assign_stack_resources(&stack_info, dev, NULL); - - DEV_FUNC_EXIT(dev); -} - -static void reset_resource_to_unassigned(struct device *dev, struct resource *res, void *data) -{ - if ((res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) && - !(res->flags & (IORESOURCE_FIXED | IORESOURCE_RESERVE))) { - res->flags &= ~IORESOURCE_ASSIGNED; - } -} - -static void xeonsp_cpx_pci_domain_set_resources(struct device *dev) -{ - DEV_FUNC_ENTER(dev); - - print_resource_tree(dev, BIOS_SPEW, "Before xeonsp pci domain set resource"); - - /* reset bus 0 dev resource assignment - need to change them to FSP IIOStack window */ - xeonsp_pci_dev_iterator(dev->link_list, NULL, reset_resource_to_unassigned, NULL); - - /* update dev resources based on IIOStack IO/Mem32/Mem64 windows */ - xeonsp_pci_domain_read_resources(dev); - - struct bus *link = dev->link_list; - while (link != NULL) { - assign_resources(link); - link = link->next; - } - - print_resource_tree(dev, BIOS_SPEW, "After xeonsp pci domain set resource"); - - DEV_FUNC_EXIT(dev); -} /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) { - mainboard_silicon_init_params(silupd); } @@ -506,8 +30,8 @@ static const char *soc_acpi_name(const struct device *dev) static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, - .set_resources = &xeonsp_cpx_pci_domain_set_resources, - .scan_bus = &xeonsp_cpx_pci_domain_scan_bus, + .set_resources = &xeonsp_pci_domain_set_resources, + .scan_bus = &xeonsp_pci_domain_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = &northbridge_write_acpi_tables, .acpi_name = soc_acpi_name @@ -521,45 +45,6 @@ static struct device_operations cpu_bus_ops = { .acpi_fill_ssdt = generate_cpu_entries, }; -/* Attach IIO stack bus numbers with dummy device to PCI DOMAIN 0000 device */ -static void attach_iio_stacks(struct device *dev) -{ - struct bus *iiostack_bus; - struct iiostack_resource stack_info = {0}; - - DEV_FUNC_ENTER(dev); - - get_iiostack_info(&stack_info); - for (int s = 0; s < stack_info.no_of_stacks; ++s) { - /* only non zero bus no. needs to be enumerated */ - if (stack_info.res[s].BusBase == 0) - continue; - - iiostack_bus = malloc(sizeof(struct bus)); - if (iiostack_bus == NULL) - die("%s: out of memory.\n", __func__); - memset(iiostack_bus, 0, sizeof(*iiostack_bus)); - memcpy(iiostack_bus, dev->bus, sizeof(*iiostack_bus)); - iiostack_bus->secondary = stack_info.res[s].BusBase; - iiostack_bus->subordinate = stack_info.res[s].BusBase; - iiostack_bus->dev = NULL; - iiostack_bus->children = NULL; - iiostack_bus->next = NULL; - iiostack_bus->link_num = 1; - - if (dev->link_list == NULL) { - dev->link_list = iiostack_bus; - } else { - struct bus *nlink = dev->link_list; - while (nlink->next != NULL) - nlink = nlink->next; - nlink->next = iiostack_bus; - } - } - - DEV_FUNC_EXIT(dev); -} - struct pci_operations soc_pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 0999f6d721..5bde819ec6 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -204,34 +205,3 @@ void cpx_init_cpus(struct device *dev) /* update numa domain for all cpu devices */ xeonsp_init_cpu_config(); } - -msr_t read_msr_ppin(void) -{ - msr_t ppin = {0}; - msr_t msr; - - /* If MSR_PLATFORM_INFO PPIN_CAP is 0, PPIN capability is not supported */ - msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & MSR_PPIN_CAP) == 0) { - printk(BIOS_ERR, "MSR_PPIN_CAP is 0, PPIN is not supported\n"); - return ppin; - } - - /* Access to MSR_PPIN is permitted only if MSR_PPIN_CTL LOCK is 0 and ENABLE is 1 */ - msr = rdmsr(MSR_PPIN_CTL); - if (msr.lo & MSR_PPIN_CTL_LOCK) { - printk(BIOS_ERR, "MSR_PPIN_CTL_LOCK is 1, PPIN access is not allowed\n"); - return ppin; - } - - if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) { - /* Set MSR_PPIN_CTL ENABLE to 1 */ - msr.lo |= MSR_PPIN_CTL_ENABLE; - wrmsr(MSR_PPIN_CTL, msr); - } - ppin = rdmsr(MSR_PPIN); - /* Set enable to 0 after reading MSR_PPIN */ - msr.lo &= ~MSR_PPIN_CTL_ENABLE; - wrmsr(MSR_PPIN_CTL, msr); - return ppin; -} diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h index 19f6e4c5d5..693de8fbcc 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h @@ -10,6 +10,5 @@ #define CPUID_COOPERLAKE_SP_A1 0x05065b void cpx_init_cpus(struct device *dev); -msr_t read_msr_ppin(void); #endif diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index 412730b647..f0c257508a 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -3,24 +3,8 @@ #ifndef _SOC_UTIL_H_ #define _SOC_UTIL_H_ -#include #include #include -#include - -#define DEV_FUNC_ENTER(dev) \ - printk(BIOS_SPEW, "%s:%s:%d: ENTER (dev: %s)\n", \ - __FILE__, __func__, __LINE__, dev_path(dev)) - -#define DEV_FUNC_EXIT(dev) \ - printk(BIOS_SPEW, "%s:%s:%d: EXIT (dev: %s)\n", __FILE__, \ - __func__, __LINE__, dev_path(dev)) - -#define FUNC_ENTER() \ - printk(BIOS_SPEW, "%s:%s:%d: ENTER\n", __FILE__, __func__, __LINE__) - -#define FUNC_EXIT() \ - printk(BIOS_SPEW, "%s:%s:%d: EXIT\n", __FILE__, __func__, __LINE__) struct iiostack_resource { uint8_t no_of_stacks; @@ -35,7 +19,7 @@ void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits); void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread); /* Return socket count, as obtained from FSP HOB */ -unsigned int xeon_sp_get_socket_count(void); +unsigned int soc_get_num_cpus(void); int get_platform_thread_count(void); int get_threads_per_package(void); diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 8debc6a236..bc4a1e15b1 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -22,7 +22,7 @@ int get_threads_per_package(void) int get_platform_thread_count(void) { - return xeon_sp_get_socket_count() * get_threads_per_package(); + return soc_get_num_cpus() * get_threads_per_package(); } const struct SystemMemoryMapHob *get_system_memory_map(void) @@ -86,7 +86,7 @@ const IIO_UDS *get_iio_uds(void) return hob; } -unsigned int xeon_sp_get_socket_count(void) +unsigned int soc_get_num_cpus(void) { /* The FSP IIO UDS HOB has field numCpus, it is actually socket count */ return get_iio_uds()->SystemStatus.numCpus; @@ -119,7 +119,7 @@ void xeonsp_init_cpu_config(void) if (num_apics > 1) bubblesort(apic_ids, num_apics, NUM_ASCENDING); - num_sockets = xeon_sp_get_socket_count(); + num_sockets = soc_get_num_cpus(); cpu_read_topology(&core_count, &thread_count); assert(num_apics == (num_sockets * thread_count)); @@ -310,7 +310,7 @@ void set_bios_init_completion(void) * to receive the BIOS init completion message. So, we send it to all non-SBSP * sockets first. */ - for (uint32_t socket = 0; socket < xeon_sp_get_socket_count(); ++socket) { + for (uint32_t socket = 0; socket < soc_get_num_cpus(); ++socket) { if (socket == sbsp_socket_id) continue; set_bios_init_completion_for_package(socket); diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h new file mode 100644 index 0000000000..339da07e4a --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _CHIP_COMMON_H_ +#define _CHIP_COMMON_H_ + +void xeonsp_pci_domain_set_resources(struct device *dev); +void xeonsp_pci_domain_scan_bus(struct device *dev); +void attach_iio_stacks(struct device *dev); + +#endif /* _CHIP_COMMON_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index 159efeba2c..51e2b69b00 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -3,36 +3,12 @@ #ifndef _XEON_SP_SOC_UTIL_H_ #define _XEON_SP_SOC_UTIL_H_ -#include +#include #include void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3); void unlock_pam_regions(void); void get_stack_busnos(uint32_t *bus); - -#define LOG_MEM_RESOURCE(type, dev, index, base_kb, size_kb) \ - printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \ - "end: 0x%llx, size_kb: 0x%llx\n", \ - __func__, __LINE__, type, dev_path(dev), index, (base_kb << 10), \ - (base_kb << 10) + (size_kb << 10) - 1, size_kb) - -#define LOG_IO_RESOURCE(type, dev, index, base, size) \ - printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \ - "end: 0x%llx, size: 0x%llx\n", \ - __func__, __LINE__, type, dev_path(dev), index, base, base + size - 1, size) - -#define DEV_FUNC_ENTER(dev) \ - printk(BIOS_SPEW, "%s:%s:%d: ENTER (dev: %s)\n", \ - __FILE__, __func__, __LINE__, dev_path(dev)) - -#define DEV_FUNC_EXIT(dev) \ - printk(BIOS_SPEW, "%s:%s:%d: EXIT (dev: %s)\n", __FILE__, \ - __func__, __LINE__, dev_path(dev)) - -#define FUNC_ENTER() \ - printk(BIOS_SPEW, "%s:%s:%d: ENTER\n", __FILE__, __func__, __LINE__) - -#define FUNC_EXIT() \ - printk(BIOS_SPEW, "%s:%s:%d: EXIT\n", __FILE__, __func__, __LINE__) +msr_t read_msr_ppin(void); #endif diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 1329feb0d6..5955fa0e31 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -121,13 +121,7 @@ static unsigned long acpi_fill_srat(unsigned long current) static unsigned long acpi_fill_slit(unsigned long current) { -#if (CONFIG(SOC_INTEL_COOPERLAKE_SP)) - unsigned int nodes = xeon_sp_get_socket_count(); -#endif /* SOC_INTEL_COOPERLAKE_SP */ - -#if (CONFIG(SOC_INTEL_SKYLAKE_SP)) - int nodes = get_cpu_count(); -#endif /* SOC_INTEL_SKYLAKE_SP */ + unsigned int nodes = soc_get_num_cpus(); uint8_t *p = (uint8_t *)current; memset(p, 0, 8 + nodes * nodes); diff --git a/src/soc/intel/xeon_sp/skx/Makefile.inc b/src/soc/intel/xeon_sp/skx/Makefile.inc index 1a7e3dd564..f042d36890 100644 --- a/src/soc/intel/xeon_sp/skx/Makefile.inc +++ b/src/soc/intel/xeon_sp/skx/Makefile.inc @@ -23,7 +23,6 @@ ramstage-y += soc_acpi.c ramstage-y += chip.c ramstage-y += soc_util.c ramstage-y += cpu.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-y += hob_display.c diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c deleted file mode 100644 index c14e7c8aea..0000000000 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ /dev/null @@ -1,280 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -acpi_cstate_t *soc_get_cstate_map(size_t *entries) -{ - *entries = 0; - return NULL; -} - -static int acpi_sci_irq(void) -{ - int sci_irq = 9; - int32_t scis; - - scis = soc_read_sci_irq_select(); - scis &= SCI_IRQ_SEL; - scis >>= SCI_IRQ_ADJUST; - - /* Determine how SCI is routed. */ - switch (scis) { - case SCIS_IRQ9: - case SCIS_IRQ10: - case SCIS_IRQ11: - sci_irq = scis - SCIS_IRQ9 + 9; - break; - case SCIS_IRQ20: - case SCIS_IRQ21: - case SCIS_IRQ22: - case SCIS_IRQ23: - sci_irq = scis - SCIS_IRQ20 + 20; - break; - default: - printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); - sci_irq = 9; - break; - } - - printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); - return sci_irq; -} - -static unsigned long acpi_madt_irq_overrides(unsigned long current) -{ - int sci = acpi_sci_irq(); - uint16_t flags = MP_IRQ_TRIGGER_LEVEL; - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); - - flags |= soc_madt_sci_irq_polarity(sci); - - /* SCI */ - current += acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags); - - current += - acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) current, 0xff, 0x0d, 1); - - return current; -} - -unsigned long acpi_fill_madt(unsigned long current) -{ - size_t hob_size = 0; - const uint8_t fsp_hob_iio_universal_data_guid[16] = - FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob; - int cur_stack; - - int gsi_bases[] = { 0, 0x18, 0x20, 0x28, 0x30, 0x48, 0x50, 0x58, 0x60 }; - int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 }; - - /* Local APICs */ - current = xeonsp_acpi_create_madt_lapics(current); - - hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - - cur_stack = 0; - for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { - for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { - const STACK_RES *ri = - &hob->PlatformData.IIO_resource[socket].StackRes[stack]; - // TODO: do we have situation with only bus 0 and one stack? - if (ri->BusBase != ri->BusLimit) { - assert(cur_stack < ARRAY_SIZE(ioapic_ids)); - assert(cur_stack < ARRAY_SIZE(gsi_bases)); - int ioapic_id = ioapic_ids[cur_stack]; - int gsi_base = gsi_bases[cur_stack]; - printk(BIOS_DEBUG, "Adding MADT IOAPIC for socket: %d, stack: %d, ioapic_id: 0x%x, " - "ioapic_base: 0x%x, gsi_base: 0x%x\n", - socket, stack, ioapic_id, ri->IoApicBase, gsi_base); - current += acpi_create_madt_ioapic( - (acpi_madt_ioapic_t *)current, - ioapic_id, ri->IoApicBase, gsi_base); - ++cur_stack; - - if (socket == 0 && stack == 0) { - assert(cur_stack < ARRAY_SIZE(ioapic_ids)); - assert(cur_stack < ARRAY_SIZE(gsi_bases)); - ioapic_id = ioapic_ids[cur_stack]; - gsi_base = gsi_bases[cur_stack]; - printk(BIOS_DEBUG, "Adding MADT IOAPIC for socket: %d, stack: %d, ioapic_id: 0x%x, " - "ioapic_base: 0x%x, gsi_base: 0x%x\n", - socket, stack, ioapic_id, - ri->IoApicBase + 0x1000, gsi_base); - current += acpi_create_madt_ioapic( - (acpi_madt_ioapic_t *)current, - ioapic_id, ri->IoApicBase + 0x1000, gsi_base); - ++cur_stack; - } - } - } - } - - return acpi_madt_irq_overrides(current); -} - -void acpi_fill_fadt(acpi_fadt_t *fadt) -{ - const uint16_t pmbase = ACPI_BASE_ADDRESS; - - fadt->header.revision = get_acpi_table_revision(FADT); - - fadt->sci_int = acpi_sci_irq(); - - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - - fadt->gpe0_blk = pmbase + GPE0_STS(0); - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - - /* GPE0 STS/EN pairs each 32 bits wide. */ - fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); - - fadt->duty_offset = 1; - fadt->day_alrm = 0xd; - - fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; - - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - - /* - * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. - * The bit_width field intentionally overflows here. - * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which - * seems to work fine on Linux 5.0 and Windows 10. - */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0; -} - -unsigned long southbridge_write_acpi_tables(const struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp) -{ - current = acpi_write_hpet(device, current, rsdp); - current = (ALIGN(current, 16)); - printk(BIOS_DEBUG, "current = %lx\n", current); - return current; -} - -void southbridge_inject_dsdt(const struct device *device) -{ - struct global_nvs *gnvs; - - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); - if (gnvs) - memset(gnvs, 0, sizeof(*gnvs)); - } - - if (gnvs) { - acpi_create_gnvs(gnvs); - /* TODO: tell SMI about it, if HAVE_SMI_HANDLER */ - // apm_control(APM_CNT_GNVS_UPDATE); - - /* Add it to DSDT. */ - printk(BIOS_SPEW, "%s injecting NVSA with 0x%x\n", __FILE__, (uint32_t)gnvs); - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (uint32_t)gnvs); - acpigen_pop_len(); - } -} - - - -static acpi_tstate_t xeon_sp_tss_table[] = { - { 100, 1000, 0, 0x00, 0 }, - { 88, 875, 0, 0x1e, 0 }, - { 75, 750, 0, 0x1c, 0 }, - { 63, 625, 0, 0x1a, 0 }, - { 50, 500, 0, 0x18, 0 }, - { 38, 375, 0, 0x16, 0 }, - { 25, 250, 0, 0x14, 0 }, - { 13, 125, 0, 0x12, 0 }, -}; - -acpi_tstate_t *soc_get_tss_table(int *entries) -{ - *entries = ARRAY_SIZE(xeon_sp_tss_table); - return xeon_sp_tss_table; -} - -void generate_t_state_entries(int core, int cores_per_package) -{ -} - -void generate_cpu_entries(const struct device *device) -{ - int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS; - int plen = 6; - int total_threads = dev_count_cpu(); - int threads_per_package = get_threads_per_package(); - int numcpus = total_threads / threads_per_package; - - printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each, totalcores: %d.\n", - numcpus, threads_per_package, total_threads); - - for (cpu_id = 0; cpu_id < numcpus; cpu_id++) { - for (core_id = 0; core_id < threads_per_package; core_id++) { - if (core_id > 0) { - pcontrol_blk = 0; - plen = 0; - } - - /* Generate processor \_PR.CPUx */ - acpigen_write_processor((cpu_id) * threads_per_package + - core_id, pcontrol_blk, plen); - - /* NOTE: Intel idle driver doesn't use ACPI C-state tables */ - - /* TODO: Soc specific power states generation */ - acpigen_pop_len(); - } - } - /* PPKG is usually used for thermal management - of the first and only package. */ - acpigen_write_processor_package("PPKG", 0, threads_per_package); - - /* Add a method to notify processor nodes */ - acpigen_write_processor_cnot(threads_per_package); -} diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index 4324660f47..a345c3ef6e 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -1,466 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include -#include -#include +#include #include #include +#include #include #include #include -struct pci_resource { - struct device *dev; - struct resource *res; - struct pci_resource *next; -}; - -struct stack_dev_resource { - uint8_t align; - struct pci_resource *children; - struct stack_dev_resource *next; -}; - -static void assign_stack_resources(struct iiostack_resource *stack_list, - struct device *dev, struct resource *bridge); - -static void xeonsp_pci_domain_scan_bus(struct device *dev) -{ - DEV_FUNC_ENTER(dev); - struct bus *link = dev->link_list; - - printk(BIOS_SPEW, "%s:%s scanning buses under device %s\n", - __FILE__, __func__, dev_path(dev)); - while (link != NULL) { - if (link->secondary == 0) { // scan only PSTACK buses - struct device *d; - for (d = link->children; d; d = d->sibling) - pci_probe_dev(d, link, d->path.pci.devfn); - scan_bridges(link); - } else { - pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff); - } - link = link->next; - } - DEV_FUNC_EXIT(dev); -} - -static void xeonsp_pci_dev_iterator(struct bus *bus, - void (*dev_iterator)(struct device *, void *), - void (*res_iterator)(struct device *, struct resource *, void *), - void *data) -{ - struct device *curdev; - struct resource *res; - - /* Walk through all devices and find which resources they need. */ - for (curdev = bus->children; curdev; curdev = curdev->sibling) { - struct bus *link; - - if (!curdev->enabled) - continue; - - if (!curdev->ops || !curdev->ops->read_resources) { - if (curdev->path.type != DEVICE_PATH_APIC) - printk(BIOS_ERR, "%s missing read_resources\n", - dev_path(curdev)); - continue; - } - - if (dev_iterator) - dev_iterator(curdev, data); - - if (res_iterator) { - for (res = curdev->resource_list; res; res = res->next) - res_iterator(curdev, res, data); - } - - /* Read in the resources behind the current device's links. */ - for (link = curdev->link_list; link; link = link->next) - xeonsp_pci_dev_iterator(link, dev_iterator, res_iterator, data); - } -} - -static void xeonsp_pci_dev_read_resources(struct device *dev, void *data) -{ - post_log_path(dev); - dev->ops->read_resources(dev); -} - -static void xeonsp_pci_dev_dummy_func(struct device *dev) -{ -} - -static void xeonsp_reset_pci_op(struct device *dev, void *data) -{ - if (dev->ops) - dev->ops->read_resources = xeonsp_pci_dev_dummy_func; -} - -static STACK_RES *find_stack_for_bus(struct iiostack_resource *info, uint8_t bus) -{ - for (int i = 0; i < info->no_of_stacks; ++i) { - if (bus >= info->res[i].BusBase && bus <= info->res[i].BusLimit) - return &info->res[i]; - } - return NULL; -} - -static void add_res_to_stack(struct stack_dev_resource **root, - struct device *dev, struct resource *res) -{ - struct stack_dev_resource *cur = *root; - while (cur) { - if (cur->align == res->align || cur->next == NULL) /* equal or last record */ - break; - else if (cur->align > res->align) { - if (cur->next->align < res->align) /* need to insert new record here */ - break; - cur = cur->next; - } else { - break; - } - } - - struct stack_dev_resource *nr; - if (!cur || cur->align != res->align) { /* need to add new record */ - nr = malloc(sizeof(struct stack_dev_resource)); - if (nr == 0) - die("assign_resource_to_stack(): out of memory.\n"); - memset(nr, 0, sizeof(struct stack_dev_resource)); - nr->align = res->align; - if (!cur) { - *root = nr; /* head node */ - } else if (cur->align > nr->align) { - if (cur->next == NULL) { - cur->next = nr; - } else { - nr->next = cur->next; - cur->next = nr; - } - } else { /* insert in the beginning */ - nr->next = cur; - *root = nr; - } - } else { - nr = cur; - } - - assert(nr != NULL && nr->align == res->align); - - struct pci_resource *npr = malloc(sizeof(struct pci_resource)); - if (npr == NULL) - die("%s: out of memory.\n", __func__); - npr->res = res; - npr->dev = dev; - npr->next = NULL; - - if (nr->children == NULL) { - nr->children = npr; - } else { - struct pci_resource *pr = nr->children; - while (pr->next != NULL) - pr = pr->next; - pr->next = npr; - } -} - -static void reserve_dev_resources(STACK_RES *stack, unsigned long res_type, - struct stack_dev_resource *res_root, struct resource *bridge) -{ - uint8_t align; - uint64_t orig_base, base; - - if (res_type & IORESOURCE_IO) - orig_base = stack->PciResourceIoBase; - else if ((res_type & IORESOURCE_MEM) && ((res_type & IORESOURCE_PCI64) || - (!res_root && bridge && (bridge->flags & IORESOURCE_PREFETCH)))) - orig_base = stack->PciResourceMem64Base; - else - orig_base = stack->PciResourceMem32Base; - - align = 0; - base = orig_base; - int first = 1; - while (res_root) { /* loop through all devices grouped by alignment requirements */ - struct pci_resource *pr = res_root->children; - while (pr) { - if (first) { - if (bridge) { /* takes highest alignment */ - if (bridge->align < pr->res->align) - bridge->align = pr->res->align; - orig_base = ALIGN_UP(orig_base, 1 << bridge->align); - } else { - orig_base = ALIGN_UP(orig_base, 1 << pr->res->align); - } - base = orig_base; - - if (bridge) - bridge->base = base; - pr->res->base = base; - first = 0; - } else { - pr->res->base = ALIGN_UP(base, 1 << pr->res->align); - } - pr->res->limit = pr->res->base + pr->res->size - 1; - base = pr->res->limit + 1; - pr->res->flags |= (IORESOURCE_ASSIGNED); - pr = pr->next; - } - res_root = res_root->next; - } - - if (bridge) { - /* this bridge doesn't have any resources, will set it to default window */ - if (first) { - orig_base = ALIGN_UP(orig_base, 1 << bridge->align); - bridge->base = orig_base; - base = orig_base + (1ULL << bridge->gran); - } - - bridge->size = ALIGN_UP(base, 1 << bridge->align) - bridge->base; - - bridge->limit = bridge->base + bridge->size - 1; - bridge->flags |= (IORESOURCE_ASSIGNED); - base = bridge->limit + 1; - } - - /* update new limits */ - if (res_type & IORESOURCE_IO) - stack->PciResourceIoBase = base; - else if ((res_type & IORESOURCE_MEM) && ((res_type & IORESOURCE_PCI64) || - (!res_root && bridge && (bridge->flags & IORESOURCE_PREFETCH)))) - stack->PciResourceMem64Base = base; - else - stack->PciResourceMem32Base = base; -} - -static void reclaim_resource_mem(struct stack_dev_resource *res_root) -{ - while (res_root) { /* loop through all devices grouped by alignment requirements */ - /* free pci_resource */ - struct pci_resource *pr = res_root->children; - while (pr) { - struct pci_resource *dpr = pr; - pr = pr->next; - free(dpr); - } - - /* free stack_dev_resource */ - struct stack_dev_resource *ddr = res_root; - res_root = res_root->next; - free(ddr); - } -} - -static void assign_bridge_resources(struct iiostack_resource *stack_list, - struct device *dev, struct resource *bridge) -{ - struct resource *res; - if (!dev->enabled) - return; - - for (res = dev->resource_list; res; res = res->next) { - if (!(res->flags & IORESOURCE_BRIDGE) || - (bridge && ((bridge->flags & (IORESOURCE_IO | IORESOURCE_MEM | - IORESOURCE_PREFETCH | IORESOURCE_PCI64)) != - (res->flags & (IORESOURCE_IO | IORESOURCE_MEM | - IORESOURCE_PREFETCH | IORESOURCE_PCI64))))) - continue; - - assign_stack_resources(stack_list, dev, res); - if (!bridge) - continue; - /* for 1st time update, overlading IORESOURCE_ASSIGNED */ - if (!(bridge->flags & IORESOURCE_ASSIGNED)) { - bridge->base = res->base; - bridge->limit = res->limit; - bridge->flags |= (IORESOURCE_ASSIGNED); - } else { - /* update bridge range from child bridge range */ - if (res->base < bridge->base) - bridge->base = res->base; - if (res->limit > bridge->limit) - bridge->limit = res->limit; - } - bridge->size = (bridge->limit - bridge->base + 1); - } -} - -static void assign_stack_resources(struct iiostack_resource *stack_list, - struct device *dev, struct resource *bridge) -{ - struct bus *bus; - - /* Read in the resources behind the current device's links. */ - for (bus = dev->link_list; bus; bus = bus->next) { - struct device *curdev; - STACK_RES *stack; - - /* get IIO stack for this bus */ - stack = find_stack_for_bus(stack_list, bus->secondary); - assert(stack != NULL); - - /* Assign resources to bridge */ - for (curdev = bus->children; curdev; curdev = curdev->sibling) - assign_bridge_resources(stack_list, curdev, bridge); - - /* Pick non-bridged resources for resource allocation for each resource type */ - unsigned long flags[5] = {IORESOURCE_IO, IORESOURCE_MEM, - (IORESOURCE_PCI64|IORESOURCE_MEM), (IORESOURCE_MEM|IORESOURCE_PREFETCH), - (IORESOURCE_PCI64|IORESOURCE_MEM|IORESOURCE_PREFETCH)}; - uint8_t no_res_types = 5; - if (bridge) { - flags[0] = bridge->flags & - (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH); - if ((bridge->flags & IORESOURCE_MEM) && - (bridge->flags & IORESOURCE_PREFETCH)) - flags[0] |= IORESOURCE_PCI64; - no_res_types = 1; - } - - /* Process each resource type */ - for (int rt = 0; rt < no_res_types; ++rt) { - struct stack_dev_resource *res_root = NULL; - - for (curdev = bus->children; curdev; curdev = curdev->sibling) { - struct resource *res; - if (!curdev->enabled) - continue; - - for (res = curdev->resource_list; res; res = res->next) { - if ((res->flags & IORESOURCE_BRIDGE) || (res->flags & - (IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_ASSIGNED) - ) || ((res->flags & (IORESOURCE_IO | - IORESOURCE_MEM | IORESOURCE_PCI64 - | IORESOURCE_PREFETCH)) - != flags[rt]) || res->size == 0) - continue; - else - add_res_to_stack(&res_root, curdev, res); - } - } - - /* Allocate resources and update bridge range */ - if (res_root || (bridge && !(bridge->flags & IORESOURCE_ASSIGNED))) { - reserve_dev_resources(stack, flags[rt], res_root, bridge); - reclaim_resource_mem(res_root); - } - } - } -} - -static void xeonsp_constrain_pci_resources(struct device *dev, struct resource *res, void *data) -{ - STACK_RES *stack = (STACK_RES *) data; - if (!(res->flags & IORESOURCE_FIXED)) - return; - - uint64_t base, limit; - if (res->flags & IORESOURCE_IO) { - base = stack->PciResourceIoBase; - limit = stack->PciResourceIoLimit; - } else if ((res->flags & IORESOURCE_MEM) && (res->flags & IORESOURCE_PCI64)) { - base = stack->PciResourceMem64Base; - limit = stack->PciResourceMem64Limit; - } else { - base = stack->PciResourceMem32Base; - limit = stack->PciResourceMem32Limit; - } - - if (((res->base + res->size - 1) < base) || (res->base > limit)) /* outside window */ - return; - - if (res->limit > limit) /* resource end is out of limit */ - limit = res->base - 1; - else - base = res->base + res->size; - - if (res->flags & IORESOURCE_IO) { - stack->PciResourceIoBase = base; - stack->PciResourceIoLimit = limit; - } else if ((res->flags & IORESOURCE_MEM) && (res->flags & IORESOURCE_PCI64)) { - stack->PciResourceMem64Base = base; - stack->PciResourceMem64Limit = limit; - } else { - stack->PciResourceMem32Base = base; - stack->PciResourceMem32Limit = limit; - } -} - -static void xeonsp_pci_domain_read_resources(struct device *dev) -{ - struct bus *link; - - DEV_FUNC_ENTER(dev); - - pci_domain_read_resources(dev); - - /* - * Walk through all devices in this domain and read resources. - * Since there is no callback when read resource operation is - * complete for all devices, domain read resource function initiates - * read resources for all devices and swaps read resource operation - * with dummy function to avoid warning. - */ - for (link = dev->link_list; link; link = link->next) - xeonsp_pci_dev_iterator(link, xeonsp_pci_dev_read_resources, NULL, NULL); - - for (link = dev->link_list; link; link = link->next) - xeonsp_pci_dev_iterator(link, xeonsp_reset_pci_op, NULL, NULL); - - /* - * 1. group devices, resources for each stack - * 2. order resources in descending order of requested resource allocation sizes - */ - struct iiostack_resource stack_info = {0}; - get_iiostack_info(&stack_info); - - /* constrain stack window */ - for (link = dev->link_list; link; link = link->next) { - STACK_RES *stack = find_stack_for_bus(&stack_info, link->secondary); - assert(stack != 0); - xeonsp_pci_dev_iterator(link, NULL, xeonsp_constrain_pci_resources, stack); - } - - /* assign resources */ - assign_stack_resources(&stack_info, dev, NULL); - - DEV_FUNC_EXIT(dev); -} - -static void reset_resource_to_unassigned(struct device *dev, struct resource *res, void *data) -{ - if ((res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) && - !(res->flags & (IORESOURCE_FIXED | IORESOURCE_RESERVE))) { - res->flags &= ~IORESOURCE_ASSIGNED; - } -} - -static void xeonsp_pci_domain_set_resources(struct device *dev) -{ - DEV_FUNC_ENTER(dev); - - print_resource_tree(dev, BIOS_SPEW, "Before xeonsp pci domain set resource"); - - /* reset bus 0 dev resource assignment - need to change them to FSP IIOStack window */ - xeonsp_pci_dev_iterator(dev->link_list, NULL, reset_resource_to_unassigned, NULL); - - /* update dev resources based on IIOStack IO/Mem32/Mem64 windows */ - xeonsp_pci_domain_read_resources(dev); - - struct bus *link = dev->link_list; - while (link != NULL) { - assign_resources(link); - link = link->next; - } - - print_resource_tree(dev, BIOS_SPEW, "After xeonsp pci domain set resource"); - - DEV_FUNC_EXIT(dev); -} - static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &xeonsp_pci_domain_set_resources, @@ -480,54 +28,6 @@ static struct device_operations cpu_bus_ops = { #endif }; -/* Attach IIO stack bus numbers with dummy device to PCI DOMAIN 0000 device */ -static void attach_iio_stacks(struct device *dev) -{ - struct bus *iiostack_bus; - struct device dummy; - struct iiostack_resource stack_info = {0}; - - DEV_FUNC_ENTER(dev); - - get_iiostack_info(&stack_info); - for (int s = 0; s < stack_info.no_of_stacks; ++s) { - /* only non zero bus no. needs to be enumerated */ - if (stack_info.res[s].BusBase == 0) - continue; - - iiostack_bus = malloc(sizeof(struct bus)); - if (iiostack_bus == NULL) - die("%s: out of memory.\n", __func__); - memset(iiostack_bus, 0, sizeof(*iiostack_bus)); - memcpy(iiostack_bus, dev->bus, sizeof(*iiostack_bus)); - iiostack_bus->secondary = stack_info.res[s].BusBase; - iiostack_bus->subordinate = stack_info.res[s].BusBase; - iiostack_bus->dev = NULL; - iiostack_bus->children = NULL; - iiostack_bus->next = NULL; - iiostack_bus->link_num = 1; - - dummy.bus = iiostack_bus; - dummy.path.type = DEVICE_PATH_PCI; - dummy.path.pci.devfn = 0; - uint32_t id = pci_read_config32(&dummy, PCI_VENDOR_ID); - if (id == 0xffffffff) - printk(BIOS_WARNING, "IIO Stack device %s not visible\n", - dev_path(&dummy)); - - if (dev->link_list == NULL) { - dev->link_list = iiostack_bus; - } else { - struct bus *nlink = dev->link_list; - while (nlink->next != NULL) - nlink = nlink->next; - nlink->next = iiostack_bus; - } - } - - DEV_FUNC_EXIT(dev); -} - static void soc_enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ @@ -552,10 +52,6 @@ static void soc_final(void *data) set_bios_init_completion(); } -static void soc_silicon_init_params(FSPS_UPD *silupd) -{ -} - void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) { const struct microcode *microcode_file; @@ -572,7 +68,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) (uint32_t)microcode_len; } - soc_silicon_init_params(silupd); mainboard_silicon_init_params(silupd); } diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index bf712c3618..874bcfd6d7 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include #include #include #include @@ -244,34 +245,3 @@ void xeon_sp_init_cpus(struct device *dev) FUNC_EXIT(); } - -msr_t read_msr_ppin(void) -{ - msr_t ppin = {0}; - msr_t msr; - - /* If MSR_PLATFORM_INFO PPIN_CAP is 0, PPIN capability is not supported */ - msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & MSR_PPIN_CAP) == 0) { - printk(BIOS_ERR, "MSR_PPIN_CAP is 0, PPIN is not supported\n"); - return ppin; - } - - /* Access to MSR_PPIN is permitted only if MSR_PPIN_CTL LOCK is 0 and ENABLE is 1 */ - msr = rdmsr(MSR_PPIN_CTL); - if (msr.lo & MSR_PPIN_CTL_LOCK) { - printk(BIOS_ERR, "MSR_PPIN_CTL_LOCK is 1, PPIN access is not allowed\n"); - return ppin; - } - - if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) { - /* Set MSR_PPIN_CTL ENABLE to 1 */ - msr.lo |= MSR_PPIN_CTL_ENABLE; - wrmsr(MSR_PPIN_CTL, msr); - } - ppin = rdmsr(MSR_PPIN); - /* Set enable to 0 after reading MSR_PPIN */ - msr.lo &= ~MSR_PPIN_CTL_ENABLE; - wrmsr(MSR_PPIN_CTL, msr); - return ppin; -} diff --git a/src/soc/intel/xeon_sp/skx/include/soc/cpu.h b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h index c2af265b91..433598b5c0 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h @@ -14,8 +14,6 @@ /* CPU bus clock is fixed at 100MHz */ #define CPU_BCLK 100 -int get_cpu_count(void); void xeon_sp_init_cpus(struct device *dev); -msr_t read_msr_ppin(void); #endif diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index 76f7c8be4b..25668301a4 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -26,5 +26,6 @@ int get_threads_per_package(void); const struct SystemMemoryMapHob *get_system_memory_map(void); void set_bios_init_completion(void); +unsigned int soc_get_num_cpus(void); #endif /* _SOC_UTIL_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 3b37ca3c48..7dd954fd66 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -264,7 +264,7 @@ void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thre *thread = (uint32_t)(apicid & ~((~0) << thread_bits)); } -int get_cpu_count(void) +unsigned int soc_get_num_cpus(void) { size_t hob_size; const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; @@ -285,7 +285,7 @@ int get_threads_per_package(void) int get_platform_thread_count(void) { - return get_cpu_count() * get_threads_per_package(); + return soc_get_num_cpus() * get_threads_per_package(); } uint8_t get_iiostack_info(struct iiostack_resource *info) @@ -353,7 +353,7 @@ void xeonsp_init_cpu_config(void) if (num_apics > 1) bubblesort(apic_ids, num_apics, NUM_ASCENDING); - num_cpus = get_cpu_count(); + num_cpus = soc_get_num_cpus(); cpu_read_topology(&core_count, &thread_count); assert(num_apics == (num_cpus * thread_count)); diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index 77fc1e4941..66b9ef11c1 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -3,6 +3,7 @@ #include #include #include +#include #include void get_stack_busnos(uint32_t *bus) @@ -53,3 +54,34 @@ void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus if (bus3) *bus3 = (bus >> 24) & 0xff; } + +msr_t read_msr_ppin(void) +{ + msr_t ppin = {0}; + msr_t msr; + + /* If MSR_PLATFORM_INFO PPIN_CAP is 0, PPIN capability is not supported */ + msr = rdmsr(MSR_PLATFORM_INFO); + if ((msr.lo & MSR_PPIN_CAP) == 0) { + printk(BIOS_ERR, "MSR_PPIN_CAP is 0, PPIN is not supported\n"); + return ppin; + } + + /* Access to MSR_PPIN is permitted only if MSR_PPIN_CTL LOCK is 0 and ENABLE is 1 */ + msr = rdmsr(MSR_PPIN_CTL); + if (msr.lo & MSR_PPIN_CTL_LOCK) { + printk(BIOS_ERR, "MSR_PPIN_CTL_LOCK is 1, PPIN access is not allowed\n"); + return ppin; + } + + if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) { + /* Set MSR_PPIN_CTL ENABLE to 1 */ + msr.lo |= MSR_PPIN_CTL_ENABLE; + wrmsr(MSR_PPIN_CTL, msr); + } + ppin = rdmsr(MSR_PPIN); + /* Set enable to 0 after reading MSR_PPIN */ + msr.lo &= ~MSR_PPIN_CTL_ENABLE; + wrmsr(MSR_PPIN_CTL, msr); + return ppin; +} diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 8b2831cc6b..13b5b21763 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -37,6 +37,16 @@ ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c usb.c +MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192 + +DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram +$(DRAM_CBFS)-file := $(MT8192_BLOB_DIR)/dram.elf +$(DRAM_CBFS)-type := stage +$(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +ifneq ($(wildcard $($(DRAM_CBFS)-file)),) + cbfs-files-y += $(DRAM_CBFS) +endif + BL31_MAKEARGS += PLAT=mt8192 CPPFLAGS_common += -Isrc/soc/mediatek/mt8192/include diff --git a/src/soc/mediatek/mt8192/memory.c b/src/soc/mediatek/mt8192/memory.c index 5820fbf294..549dede00d 100644 --- a/src/soc/mediatek/mt8192/memory.c +++ b/src/soc/mediatek/mt8192/memory.c @@ -7,6 +7,7 @@ #include #include #include +#include static int mt_mem_test(const struct dramc_data *dparam) { @@ -41,7 +42,7 @@ static u32 compute_checksum(const struct dramc_param *dparam) static int dram_run_fast_calibration(const struct dramc_param *dparam) { if (!is_valid_dramc_param(dparam)) { - printk(BIOS_WARNING, "Invalid DRAM calibration data from flash\n"); + printk(BIOS_WARNING, "DRAM-K: Invalid DRAM calibration data from flash\n"); dump_param_header((void *)dparam); return -1; } @@ -49,7 +50,7 @@ static int dram_run_fast_calibration(const struct dramc_param *dparam) const u32 checksum = compute_checksum(dparam); if (dparam->header.checksum != checksum) { printk(BIOS_ERR, - "Invalid DRAM calibration checksum from flash " + "DRAM-K: Invalid DRAM calibration checksum from flash " "(expected: %#x, saved: %#x)\n", checksum, dparam->header.checksum); return DRAMC_ERR_INVALID_CHECKSUM; @@ -58,13 +59,13 @@ static int dram_run_fast_calibration(const struct dramc_param *dparam) const u16 config = CONFIG(MT8192_DRAM_DVFS) ? DRAMC_ENABLE_DVFS : DRAMC_DISABLE_DVFS; if (dparam->dramc_datas.ddr_info.config_dvfs != config) { printk(BIOS_WARNING, - "Incompatible config for calibration data from flash " + "DRAM-K: Incompatible config for calibration data from flash " "(expected: %#x, saved: %#x)\n", config, dparam->dramc_datas.ddr_info.config_dvfs); return -1; } - printk(BIOS_INFO, "DRAM calibration data valid pass\n"); + printk(BIOS_INFO, "DRAM-K: DRAM calibration data valid pass\n"); mt_set_emi(&dparam->dramc_datas); if (mt_mem_test(&dparam->dramc_datas) == 0) return 0; @@ -72,6 +73,43 @@ static int dram_run_fast_calibration(const struct dramc_param *dparam) return DRAMC_ERR_FAST_CALIBRATION; } +static int dram_run_full_calibration(struct dramc_param *dparam) +{ + /* Load and run the provided blob for full-calibration if available */ + struct prog dram = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/dram"); + + initialize_dramc_param(dparam); + + if (prog_locate(&dram)) { + printk(BIOS_ERR, "DRAM-K: Locate program failed\n"); + return -1; + } + + if (cbfs_prog_stage_load(&dram)) { + printk(BIOS_ERR, "DRAM-K: CBFS load program failed\n"); + return -2; + } + + dparam->do_putc = do_putchar; + + prog_set_entry(&dram, prog_entry(&dram), dparam); + prog_run(&dram); + if (dparam->header.status != DRAMC_SUCCESS) { + printk(BIOS_ERR, "DRAM-K: Full calibration failed: status = %d\n", + dparam->header.status); + return -3; + } + + if (!(dparam->header.flags & DRAMC_FLAG_HAS_SAVED_DATA)) { + printk(BIOS_ERR, + "DRAM-K: Full calibration executed without saving parameters. " + "Please ensure the blob is built properly.\n"); + return -4; + } + + return 0; +} + static void mem_init_set_default_config(struct dramc_param *dparam, u32 ddr_geometry) { @@ -93,23 +131,51 @@ static void mem_init_set_default_config(struct dramc_param *dparam, static void mt_mem_init_run(struct dramc_param_ops *dparam_ops, u32 ddr_geometry) { struct dramc_param *dparam = dparam_ops->param; + struct stopwatch sw; + int ret; /* Load calibration params from flash and run fast calibration */ mem_init_set_default_config(dparam, ddr_geometry); if (dparam_ops->read_from_flash(dparam)) { printk(BIOS_INFO, "DRAM-K: Running fast calibration\n"); - if (dram_run_fast_calibration(dparam) != 0) { - printk(BIOS_ERR, "Failed to run fast calibration\n"); + stopwatch_init(&sw); + + ret = dram_run_fast_calibration(dparam); + if (ret != 0) { + printk(BIOS_ERR, "DRAM-K: Failed to run fast calibration " + "in %ld msecs, error: %d\n", + stopwatch_duration_msecs(&sw), ret); /* Erase flash data after fast calibration failed */ memset(dparam, 0xa5, sizeof(*dparam)); dparam_ops->write_to_flash(dparam); } else { - printk(BIOS_INFO, "Fast calibration passed\n"); + printk(BIOS_INFO, "DRAM-K: Fast calibration passed in %ld msecs\n", + stopwatch_duration_msecs(&sw)); return; } } else { - printk(BIOS_WARNING, "Failed to read calibration data from flash\n"); + printk(BIOS_WARNING, "DRAM-K: Failed to read calibration data from flash\n"); + } + + /* Run full calibration */ + printk(BIOS_INFO, "DRAM-K: Running full calibration\n"); + mem_init_set_default_config(dparam, ddr_geometry); + + stopwatch_init(&sw); + int err = dram_run_full_calibration(dparam); + if (err == 0) { + printk(BIOS_INFO, "DRAM-K: Full calibration passed in %ld msecs\n", + stopwatch_duration_msecs(&sw)); + + dparam->header.checksum = compute_checksum(dparam); + dparam_ops->write_to_flash(dparam); + printk(BIOS_DEBUG, "DRAM-K: Calibration params saved to flash: " + "version=%#x, size=%#x\n", + dparam->header.version, dparam->header.size); + } else { + printk(BIOS_ERR, "DRAM-K: Full calibration failed in %ld msecs\n", + stopwatch_duration_msecs(&sw)); } } diff --git a/src/soc/qualcomm/common/include/soc/mmu_common.h b/src/soc/qualcomm/common/include/soc/mmu_common.h index a38196fada..b6c8aabf4f 100644 --- a/src/soc/qualcomm/common/include/soc/mmu_common.h +++ b/src/soc/qualcomm/common/include/soc/mmu_common.h @@ -14,5 +14,6 @@ static struct region * const ddr_region = (struct region *)_ddr_information; void soc_mmu_dram_config_post_dram_init(void); void qc_mmu_dram_config_post_dram_init(void *ddr_base, size_t ddr_size); +bool soc_modem_carve_out(void **start, void **end); #endif /* _SOC_QUALCOMM_MMU_COMMON_H_ */ diff --git a/src/soc/qualcomm/common/mmu.c b/src/soc/qualcomm/common/mmu.c index 4f606be3e0..ba1173edf9 100644 --- a/src/soc/qualcomm/common/mmu.c +++ b/src/soc/qualcomm/common/mmu.c @@ -4,10 +4,19 @@ #include #include +__weak bool soc_modem_carve_out(void **start, void **end) { return false; } __weak void soc_mmu_dram_config_post_dram_init(void) { /* no-op */ } void qc_mmu_dram_config_post_dram_init(void *ddr_base, size_t ddr_size) { - mmu_config_range((void *)ddr_base, ddr_size, CACHED_RAM); + void *start = NULL; + void *end = NULL; + + if (!soc_modem_carve_out(&start, &end)) { + mmu_config_range((void *)ddr_base, ddr_size, CACHED_RAM); + } else { + mmu_config_range(ddr_base, start - ddr_base, CACHED_RAM); + mmu_config_range(end, ddr_base + ddr_size - end, CACHED_RAM); + } soc_mmu_dram_config_post_dram_init(); } diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 7f52a9a178..07d26529e9 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -45,6 +45,7 @@ romstage-y += qupv3_spi.c romstage-y += gpio.c romstage-y += qupv3_i2c.c romstage-y += clock.c +romstage-y += carve_out.c romstage-$(CONFIG_SC7180_QSPI) += qspi.c romstage-y += qcom_qup_se.c romstage-y += qupv3_config.c @@ -52,6 +53,7 @@ romstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c ################################################################################ ramstage-y += soc.c +ramstage-y += carve_out.c ramstage-y += timer.c ramstage-y += spi.c ramstage-y += qupv3_spi.c diff --git a/src/soc/qualcomm/sc7180/carve_out.c b/src/soc/qualcomm/sc7180/carve_out.c new file mode 100644 index 0000000000..960b923bcc --- /dev/null +++ b/src/soc/qualcomm/sc7180/carve_out.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#define MODEM_ID_LTE 0x004c5445 +#define MODEM_ID_WIFI 0x57494649 + +bool soc_modem_carve_out(void **start, void **end) +{ + uint32_t modem_id = read32(_modem_id); + + switch (modem_id) { + case MODEM_ID_LTE: + *start = _dram_modem_wifi_only; + *end = _edram_modem_extra; + return true; + case MODEM_ID_WIFI: + *start = _dram_modem_wifi_only; + *end = _edram_modem_wifi_only; + return true; + default: + return false; + } +} diff --git a/src/soc/qualcomm/sc7180/display/mdss.c b/src/soc/qualcomm/sc7180/display/mdss.c index 2d6bf6fcd3..ce46e8e880 100644 --- a/src/soc/qualcomm/sc7180/display/mdss.c +++ b/src/soc/qualcomm/sc7180/display/mdss.c @@ -6,7 +6,7 @@ #include #include -#define MDSS_MDP_MAX_PREFILL_FETCH 25 +#define MDSS_MDP_MAX_PREFILL_FETCH 24 static void mdss_source_pipe_config(struct edid *edid) { @@ -91,9 +91,10 @@ static void mdss_intf_fetch_start_config(struct edid *edid) /* * MDP programmable fetch is for MDP with rev >= 1.05. * Programmable fetch is not needed if vertical back porch - * plus vertical puls width is >= 25. + * plus vertical pulse width plus extra line for the extra h_total + * added during fetch start is >= 24. */ - if ((edid->mode.vbl - edid->mode.vso) >= MDSS_MDP_MAX_PREFILL_FETCH) + if ((edid->mode.vbl - edid->mode.vso + 1) >= MDSS_MDP_MAX_PREFILL_FETCH) return; /* diff --git a/src/soc/qualcomm/sc7180/include/soc/symbols.h b/src/soc/qualcomm/sc7180/include/soc/symbols.h index f15a8bbfef..207bc4377e 100644 --- a/src/soc/qualcomm/sc7180/include/soc/symbols.h +++ b/src/soc/qualcomm/sc7180/include/soc/symbols.h @@ -9,9 +9,12 @@ DECLARE_REGION(ssram) DECLARE_REGION(bsram) DECLARE_REGION(dram_aop) DECLARE_REGION(dram_soc) +DECLARE_REGION(dram_modem_wifi_only) +DECLARE_REGION(dram_modem_extra) DECLARE_REGION(dcb) DECLARE_REGION(pmic) DECLARE_REGION(limits_cfg) DECLARE_REGION(aop) +DECLARE_REGION(modem_id) #endif /* _SOC_QUALCOMM_SC7180_SYMBOLS_H_ */ diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld index ce084780c6..65e50d106e 100644 --- a/src/soc/qualcomm/sc7180/memlayout.ld +++ b/src/soc/qualcomm/sc7180/memlayout.ld @@ -24,6 +24,7 @@ SECTIONS SSRAM_START(0x14680000) OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14680000, 100K) REGION(qcsdi, 0x14699000, 52K, 4K) + REGION(modem_id, 0x146ABD00, 4, 4) SSRAM_END(0x146AE000) BSRAM_START(0x14800000) @@ -51,6 +52,8 @@ SECTIONS REGION(dram_aop, 0x80800000, 0x040000, 0x1000) REGION(dram_soc, 0x80900000, 0x200000, 0x1000) BL31(0x80B00000, 1M) + REGION(dram_modem_wifi_only, 0x86000000, 32M, 4) + REGION(dram_modem_extra, 0x88000000, 108M, 4) POSTRAM_CBFS_CACHE(0x9F800000, 16M) RAMSTAGE(0xA0800000, 16M) } diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c index 74f0868672..d8cade4249 100644 --- a/src/soc/qualcomm/sc7180/soc.c +++ b/src/soc/qualcomm/sc7180/soc.c @@ -9,12 +9,17 @@ static void soc_read_resources(struct device *dev) { + void *start = NULL; + void *end = NULL; + ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB, ddr_region->size / KiB); reserved_ram_resource(dev, 1, (uintptr_t)_dram_aop / KiB, REGION_SIZE(dram_aop) / KiB); reserved_ram_resource(dev, 2, (uintptr_t)_dram_soc / KiB, REGION_SIZE(dram_soc) / KiB); + if (soc_modem_carve_out(&start, &end)) + reserved_ram_resource(dev, 3, (uintptr_t)start / KiB, (end - start) / KiB); } static void soc_init(struct device *dev) diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index b56969008b..cfe85a1952 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -63,6 +63,10 @@ config HUDSON_PSP bool default y if CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 +config AMDFW_CONFIG_FILE + string "AMD PSP Firmware config file" + default "src/southbridge/amd/pi/hudson/fw_avl.cfg" if CPU_AMD_PI_00730F01 + config HUDSON_XHCI_FWM_FILE string "XHCI firmware path and filename" default "3rdparty/blobs/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 09bf1d6682..c845f846c7 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -78,14 +78,9 @@ endif ifeq ($(CONFIG_HUDSON_PSP), y) ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) +FIRMWARE_LOCATE=$(shell grep -e FIRMWARE_LOCATE $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') FIRMWARE_TYPE= -PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader.Bypass.sbin -#PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery.sbin -#PSPSECUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs.sbin -#PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin -#TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert endif ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) @@ -102,9 +97,6 @@ endif #PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key #PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin -SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin -SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE)_FN.sbin -SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin #PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key endif @@ -128,21 +120,12 @@ OPT_TRUSTLETKEY_FILE=$(call add_opt_prefix, $(TRUSTLETKEY_FILE), --trustletkey) OPT_SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FILE), --smufirmware2) OPT_SMUSCS_FILE=$(call add_opt_prefix, $(SMUSCS_FILE), --smuscs) +# Add all the files listed in the config file +DEP_FILES=$(shell $(AMDFWTOOL) --config $(CONFIG_AMDFW_CONFIG_FILE) --depend) + $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ - $(call strip_quotes, $(PUBSIGNEDKEY_FILE)) \ - $(call strip_quotes, $(PSPBTLDR_FILE)) \ - $(call strip_quotes, $(PSPRCVR_FILE)) \ - $(call strip_quotes, $(PSPSECUREOS_FILE)) \ - $(call strip_quotes, $(PSPNVRAM_FILE)) \ - $(call strip_quotes, $(SMUFWM_FILE)) \ - $(call strip_quotes, $(SMUSCS_FILE)) \ - $(call strip_quotes, $(PSPSECUREDEBUG_FILE)) \ - $(call strip_quotes, $(PSPTRUSTLETS_FILE)) \ - $(call strip_quotes, $(TRUSTLETKEY_FILE)) \ - $(call strip_quotes, $(SMUFIRMWARE2_FILE)) \ $(call strip_quotes, $(AMD_PUBKEY2_FILE)) \ $(call strip_quotes, $(PUBSIGNEDKEY2_FILE)) \ $(call strip_quotes, $(PSPBTLDR2_FILE)) \ @@ -157,6 +140,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(call strip_quotes, $(TRUSTLETKEY2_FILE)) \ $(call strip_quotes, $(SMUFIRMWARE2_2_FILE)) \ $(call strip_quotes, $(SMUFIRMWARE2_2_FN_FILE)) \ + $(DEP_FILES) \ $(AMDFWTOOL) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" @@ -164,18 +148,6 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(OPT_HUDSON_XHCI_FWM_FILE) \ $(OPT_HUDSON_IMC_FWM_FILE) \ $(OPT_HUDSON_GEC_FWM_FILE) \ - $(OPT_AMD_PUBKEY_FILE) \ - $(OPT_PSPBTLDR_FILE) \ - $(OPT_SMUFWM_FILE) \ - $(OPT_PSPRCVR_FILE) \ - $(OPT_PUBSIGNEDKEY_FILE) \ - $(OPT_PSPSECUREOS_FILE) \ - $(OPT_PSPNVRAM_FILE) \ - $(OPT_PSPSECUREDEBUG_FILE) \ - $(OPT_PSPTRUSTLETS_FILE) \ - $(OPT_TRUSTLETKEY_FILE) \ - $(OPT_SMUFIRMWARE2_FILE) \ - $(OPT_SMUSCS_FILE) \ $(OPT_2AMD_PUBKEY_FILE) \ $(OPT_2PSPBTLDR_FILE) \ $(OPT_2SMUFWM_FILE) \ @@ -192,6 +164,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(OPT_2SMUSCS_FILE) \ --flashsize $(CONFIG_ROM_SIZE) \ --location $(HUDSON_FWM_POSITION) \ + --config $(CONFIG_AMDFW_CONFIG_FILE) \ --output $@ ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) diff --git a/src/southbridge/amd/pi/hudson/fw_avl.cfg b/src/southbridge/amd/pi/hudson/fw_avl.cfg new file mode 100644 index 0000000000..f65d6b822f --- /dev/null +++ b/src/southbridge/amd/pi/hudson/fw_avl.cfg @@ -0,0 +1,8 @@ +# PSP fw config file + +FIRMWARE_LOCATE 3rdparty/blobs/southbridge/amd/avalon/PSP +#PSP +AMD_PUBKEY_FILE AmdPubKey.bin +PSPBTLDR_FILE PspBootLoader.Bypass.sbin +PSP_SMUFW1_SUB0_FILE SmuFirmware.sbin +SMUSCS_FILE SmuScs.bin diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index c884f209d3..b77548ecbb 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -324,7 +324,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - CONFIG_MMCONF_BUS_NUMBER); + CONFIG_MMCONF_BUS_NUMBER - 1); return current; } diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 15be4abaef..972b2531e2 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -46,7 +46,7 @@ static int codec_detect(u8 *base) u8 reg8; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec; /* Write back the value once reset bit is set. */ @@ -142,7 +142,7 @@ static void codec_init(struct device *dev, u8 *base, int addr) printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) { + if (wait_for_ready(base) < 0) { printk(BIOS_DEBUG, " codec not ready.\n"); return; } @@ -150,7 +150,7 @@ static void codec_init(struct device *dev, u8 *base, int addr) reg32 = (addr << 28) | 0x000f0000; write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) { + if (wait_for_valid(base) < 0) { printk(BIOS_DEBUG, " codec not valid.\n"); return; } @@ -168,12 +168,12 @@ static void codec_init(struct device *dev, u8 *base, int addr) /* 3 */ for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, verb[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); @@ -188,12 +188,12 @@ static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) } for (i = 0; i < pc_beep_verbs_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, pc_beep_verbs[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } } diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 99582b41d6..1927adc749 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -43,11 +43,11 @@ static int codec_detect(u8 *base) u32 reg32; /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, 0) == -1) + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0] */ @@ -140,7 +140,7 @@ static void codec_init(struct device *dev, u8 *base, int addr) printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) { + if (wait_for_ready(base) < 0) { printk(BIOS_DEBUG, " codec not ready.\n"); return; } @@ -148,7 +148,7 @@ static void codec_init(struct device *dev, u8 *base, int addr) reg32 = (addr << 28) | 0x000f0000; write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) { + if (wait_for_valid(base) < 0) { printk(BIOS_DEBUG, " codec not valid.\n"); return; } @@ -166,12 +166,12 @@ static void codec_init(struct device *dev, u8 *base, int addr) /* 3 */ for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, verb[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); diff --git a/src/southbridge/intel/i82801ix/azalia.c b/src/southbridge/intel/i82801ix/azalia.c index 1d1405ea46..d6c75339a8 100644 --- a/src/southbridge/intel/i82801ix/azalia.c +++ b/src/southbridge/intel/i82801ix/azalia.c @@ -43,11 +43,11 @@ static int codec_detect(u8 *base) u32 reg32; /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, 0) == -1) + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0] */ @@ -140,7 +140,7 @@ static void codec_init(struct device *dev, u8 *base, int addr) printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) { + if (wait_for_ready(base) < 0) { printk(BIOS_DEBUG, " codec not ready.\n"); return; } @@ -148,7 +148,7 @@ static void codec_init(struct device *dev, u8 *base, int addr) reg32 = (addr << 28) | 0x000f0000; write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) { + if (wait_for_valid(base) < 0) { printk(BIOS_DEBUG, " codec not valid.\n"); return; } @@ -166,12 +166,12 @@ static void codec_init(struct device *dev, u8 *base, int addr) /* 3 */ for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, verb[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); @@ -187,12 +187,12 @@ static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) } for (i = 0; i < pc_beep_verbs_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, pc_beep_verbs[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } } diff --git a/src/southbridge/intel/i82801jx/azalia.c b/src/southbridge/intel/i82801jx/azalia.c index 3fa344dd38..bf41490a00 100644 --- a/src/southbridge/intel/i82801jx/azalia.c +++ b/src/southbridge/intel/i82801jx/azalia.c @@ -43,11 +43,11 @@ static int codec_detect(u8 *base) u32 reg32; /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, 0) == -1) + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0] */ @@ -140,7 +140,7 @@ static void codec_init(struct device *dev, u8 *base, int addr) printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) { + if (wait_for_ready(base) < 0) { printk(BIOS_DEBUG, " codec not ready.\n"); return; } @@ -148,7 +148,7 @@ static void codec_init(struct device *dev, u8 *base, int addr) reg32 = (addr << 28) | 0x000f0000; write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) { + if (wait_for_valid(base) < 0) { printk(BIOS_DEBUG, " codec not valid.\n"); return; } @@ -166,12 +166,12 @@ static void codec_init(struct device *dev, u8 *base, int addr) /* 3 */ for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, verb[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); @@ -187,12 +187,12 @@ static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) } for (i = 0; i < pc_beep_verbs_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, pc_beep_verbs[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } } diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 011bde60b1..97e705e287 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -42,7 +42,7 @@ static int codec_detect(u8 *base) u8 reg8; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec; /* Write back the value once reset bit is set. */ @@ -138,7 +138,7 @@ static void codec_init(struct device *dev, u8 *base, int addr) printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) { + if (wait_for_ready(base) < 0) { printk(BIOS_DEBUG, " codec not ready.\n"); return; } @@ -146,7 +146,7 @@ static void codec_init(struct device *dev, u8 *base, int addr) reg32 = (addr << 28) | 0x000f0000; write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) { + if (wait_for_valid(base) < 0) { printk(BIOS_DEBUG, " codec not valid.\n"); return; } @@ -164,12 +164,12 @@ static void codec_init(struct device *dev, u8 *base, int addr) /* 3 */ for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, verb[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); @@ -185,12 +185,12 @@ static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) } for (i = 0; i < pc_beep_verbs_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, pc_beep_verbs[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } } diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 5abb286222..7ba86b8fcc 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -51,6 +51,10 @@ config SERIRQ_CONTINUOUS_MODE If you set this option to y, the serial IRQ machine will be operated in continuous mode. +config HPET_MIN_TICKS + hex + default 0x80 + config FINALIZE_USB_ROUTE_XHCI bool "Route all ports to XHCI controller in finalize step" default y diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index ce1b109342..e699c5d8e2 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -9,37 +9,6 @@ #include "pch.h" #include "nvs.h" -void acpi_create_intel_hpet(acpi_hpet_t * hpet) -{ - acpi_header_t *header = &(hpet->header); - acpi_addr_t *addr = &(hpet->addr); - - memset((void *)hpet, 0, sizeof(acpi_hpet_t)); - - /* fill out header fields */ - memcpy(header->signature, "HPET", 4); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - - header->length = sizeof(acpi_hpet_t); - header->revision = get_acpi_table_revision(HPET); - - /* fill out HPET address */ - addr->space_id = ACPI_ADDRESS_SPACE_MEMORY; - addr->bit_width = 64; - addr->bit_offset = 0; - addr->addrl = (unsigned long long)HPET_ADDR & 0xffffffff; - addr->addrh = (unsigned long long)HPET_ADDR >> 32; - - hpet->id = 0x8086a201; /* Intel */ - hpet->number = 0x00; - hpet->min_tick = 0x0080; - - header->checksum = - acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); -} - static void acpi_create_serialio_ssdt_entry(int id, struct global_nvs *gnvs) { char sio_name[5] = {}; diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index cf360ffc60..68958f08d0 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -33,7 +33,7 @@ static void azalia_pch_init(struct device *dev, u8 *base) u16 reg16; u32 reg32; - if (RCBA32(0x2030) & (1UL << 31)) { + if (RCBA32(0x2030) & (1 << 31)) { reg32 = pci_read_config32(dev, 0x120); reg32 &= 0xf8ffff01; reg32 |= (1 << 25); @@ -54,9 +54,9 @@ static void azalia_pch_init(struct device *dev, u8 *base) if (pci_read_config32(dev, 0x120) & ((1 << 24) | (1 << 25) | (1 << 26))) { reg32 = pci_read_config32(dev, 0x120); if (pch_is_lp()) - reg32 &= ~(1UL << 31); + reg32 &= ~(1 << 31); else - reg32 |= (1UL << 31); + reg32 |= (1 << 31); pci_write_config32(dev, 0x120, reg32); } @@ -79,7 +79,7 @@ static void azalia_pch_init(struct device *dev, u8 *base) pci_write_config32(dev, 0xc4, reg32); if (!pch_is_lp()) - pci_and_config32(dev, 0xd0, ~(1UL << 31)); + pci_and_config32(dev, 0xd0, ~(1 << 31)); // Select Azalia mode pci_or_config8(dev, 0x40, 1); // Audio Control diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index d142d3e6b7..802c58ef88 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -7,9 +7,7 @@ static void map_rcba(void) { - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - - pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); } static void enable_port80_on_lpc(void) diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c index b61115b02c..24897cab91 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.c +++ b/src/southbridge/intel/lynxpoint/hda_verb.c @@ -46,7 +46,7 @@ int hda_codec_detect(u8 *base) /* Write back the value once reset bit is set. */ write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG)); - /* Read in Codec location (BAR + 0xe)[2..0]*/ + /* Read in Codec location (BAR + 0xe)[2..0] */ reg8 = read8(base + HDA_STATESTS_REG); reg8 &= 0x0f; if (!reg8) diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h index fbad7d020e..d0bfab63bf 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.h +++ b/src/southbridge/intel/lynxpoint/lp_gpio.h @@ -40,9 +40,9 @@ #define GPI_LEVEL (1 << 30) #define GPO_LEVEL_SHIFT 31 -#define GPO_LEVEL_MASK (1UL << GPO_LEVEL_SHIFT) -#define GPO_LEVEL_LOW (0UL << GPO_LEVEL_SHIFT) -#define GPO_LEVEL_HIGH (1UL << GPO_LEVEL_SHIFT) +#define GPO_LEVEL_MASK (1 << GPO_LEVEL_SHIFT) +#define GPO_LEVEL_LOW (0 << GPO_LEVEL_SHIFT) +#define GPO_LEVEL_HIGH (1 << GPO_LEVEL_SHIFT) /* conf1 */ diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 29cd53f703..4286e6ca0a 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -289,58 +289,66 @@ static void lpt_lp_pm_init(struct device *dev) pci_write_config8(dev, 0xa9, 0x46); - RCBA32_AND_OR(0x232c, ~1, 0x00000000); + RCBA32_AND_OR(0x232c, ~1, 0); + RCBA32_AND_OR(0x1100, ~0xc000, 0xc000); - RCBA32_AND_OR(0x1100, ~0, 0x00000100); - RCBA32_AND_OR(0x1100, ~0, 0x0000003f); + RCBA32_OR(0x1100, 0x00000100); + RCBA32_OR(0x1100, 0x0000003f); + RCBA32_AND_OR(0x2320, ~0x60, 0x10); - RCBA32_AND_OR(0x3314, 0, 0x00012fff); - RCBA32_AND_OR(0x3318, 0, 0x0dcf0400); - RCBA32_AND_OR(0x3324, 0, 0x04000000); - RCBA32_AND_OR(0x3368, 0, 0x00041400); - RCBA32_AND_OR(0x3388, 0, 0x3f8ddbff); - RCBA32_AND_OR(0x33ac, 0, 0x00007001); - RCBA32_AND_OR(0x33b0, 0, 0x00181900); - RCBA32_AND_OR(0x33c0, 0, 0x00060A00); - RCBA32_AND_OR(0x33d0, 0, 0x06200840); - RCBA32_AND_OR(0x3a28, 0, 0x01010101); - RCBA32_AND_OR(0x3a2c, 0, 0x04040404); - RCBA32_AND_OR(0x2b1c, 0, 0x03808033); - RCBA32_AND_OR(0x2b34, 0, 0x80000009); - RCBA32_AND_OR(0x3348, 0, 0x022ddfff); - RCBA32_AND_OR(0x334c, 0, 0x00000001); - RCBA32_AND_OR(0x3358, 0, 0x0001c000); - RCBA32_AND_OR(0x3380, 0, 0x3f8ddbff); - RCBA32_AND_OR(0x3384, 0, 0x0001c7e1); - RCBA32_AND_OR(0x338c, 0, 0x0001c7e1); - RCBA32_AND_OR(0x3398, 0, 0x0001c000); - RCBA32_AND_OR(0x33a8, 0, 0x00181900); - RCBA32_AND_OR(0x33dc, 0, 0x00080000); - RCBA32_AND_OR(0x33e0, 0, 0x00000001); - RCBA32_AND_OR(0x3a20, 0, 0x00000404); - RCBA32_AND_OR(0x3a24, 0, 0x01010101); - RCBA32_AND_OR(0x3a30, 0, 0x01010101); - RCBA32_AND_OR(0x0410, ~0, 0x00000003); - RCBA32_AND_OR(0x2618, ~0, 0x08000000); - RCBA32_AND_OR(0x2300, ~0, 0x00000002); - RCBA32_AND_OR(0x2600, ~0, 0x00000008); - RCBA32_AND_OR(0x33b4, 0, 0x00007001); - RCBA32_AND_OR(0x3350, 0, 0x022ddfff); - RCBA32_AND_OR(0x3354, 0, 0x00000001); - RCBA32_AND_OR(0x33d4, ~0, 0x08000000); /* Power Optimizer */ - RCBA32_AND_OR(0x33c8, ~0, 0x00000080); /* Power Optimizer */ - RCBA32_AND_OR(0x2b10, 0, 0x0000883c); /* Power Optimizer */ - RCBA32_AND_OR(0x2b14, 0, 0x1e0a4616); /* Power Optimizer */ - RCBA32_AND_OR(0x2b24, 0, 0x40000005); /* Power Optimizer */ - RCBA32_AND_OR(0x2b20, 0, 0x0005db01); /* Power Optimizer */ - RCBA32_AND_OR(0x3a80, 0, 0x05145005); + + RCBA32(0x3314) = 0x00012fff; + RCBA32(0x3318) = 0x0dcf0400; + RCBA32(0x3324) = 0x04000000; + RCBA32(0x3368) = 0x00041400; + RCBA32(0x3388) = 0x3f8ddbff; + RCBA32(0x33ac) = 0x00007001; + RCBA32(0x33b0) = 0x00181900; + RCBA32(0x33c0) = 0x00060A00; + RCBA32(0x33d0) = 0x06200840; + RCBA32(0x3a28) = 0x01010101; + RCBA32(0x3a2c) = 0x04040404; + RCBA32(0x2b1c) = 0x03808033; + RCBA32(0x2b34) = 0x80000009; + RCBA32(0x3348) = 0x022ddfff; + RCBA32(0x334c) = 0x00000001; + RCBA32(0x3358) = 0x0001c000; + RCBA32(0x3380) = 0x3f8ddbff; + RCBA32(0x3384) = 0x0001c7e1; + RCBA32(0x338c) = 0x0001c7e1; + RCBA32(0x3398) = 0x0001c000; + RCBA32(0x33a8) = 0x00181900; + RCBA32(0x33dc) = 0x00080000; + RCBA32(0x33e0) = 0x00000001; + RCBA32(0x3a20) = 0x00000404; + RCBA32(0x3a24) = 0x01010101; + RCBA32(0x3a30) = 0x01010101; + + RCBA32_OR(0x0410, 0x00000003); + RCBA32_OR(0x2618, 0x08000000); + RCBA32_OR(0x2300, 0x00000002); + RCBA32_OR(0x2600, 0x00000008); + + RCBA32(0x33b4) = 0x00007001; + RCBA32(0x3350) = 0x022ddfff; + RCBA32(0x3354) = 0x00000001; + + /* Power Optimizer */ + RCBA32_OR(0x33d4, 0x08000000); + RCBA32_OR(0x33c8, 0x00000080); + + RCBA32(0x2b10) = 0x0000883c; + RCBA32(0x2b14) = 0x1e0a4616; + RCBA32(0x2b24) = 0x40000005; + RCBA32(0x2b20) = 0x0005db01; + RCBA32(0x3a80) = 0x05145005; pci_or_config32(dev, 0xac, 1 << 21); pch_iobp_update(0xED00015C, ~(1 << 11), 0x00003700); - pch_iobp_update(0xED000118, ~0UL, 0x00c00000); - pch_iobp_update(0xED000120, ~0UL, 0x00240000); - pch_iobp_update(0xCA000000, ~0UL, 0x00000009); + pch_iobp_update(0xED000118, ~0, 0x00c00000); + pch_iobp_update(0xED000120, ~0, 0x00240000); + pch_iobp_update(0xCA000000, ~0, 0x00000009); /* Set RCBA CIR28 0x3A84 based on SATA port enables */ data = 0x00001005; @@ -392,7 +400,7 @@ static void enable_clock_gating(struct device *dev) u16 reg16; /* DMI */ - RCBA32_AND_OR(0x2234, ~0UL, 0xf); + RCBA32_AND_OR(0x2234, ~0, 0xf); reg16 = pci_read_config16(dev, GEN_PMCON_1); reg16 |= (1 << 11) | (1 << 12) | (1 << 14); reg16 |= (1 << 2); // PCI CLKRUN# Enable @@ -401,7 +409,7 @@ static void enable_clock_gating(struct device *dev) reg32 = RCBA32(CG); reg32 |= (1 << 22); // HDA Dynamic - reg32 |= (1UL << 31); // LPC Dynamic + reg32 |= (1 << 31); // LPC Dynamic reg32 |= (1 << 16); // PCIe Dynamic reg32 |= (1 << 27); // HPET Dynamic reg32 |= (1 << 28); // GPIO Dynamic @@ -417,7 +425,7 @@ static void enable_lp_clock_gating(struct device *dev) u16 reg16; /* DMI */ - RCBA32_AND_OR(0x2234, ~0UL, 0xf); + RCBA32_AND_OR(0x2234, ~0, 0xf); reg16 = pci_read_config16(dev, GEN_PMCON_1); reg16 &= ~((1 << 11) | (1 << 14)); reg16 |= (1 << 5) | (1 << 6) | (1 << 7) | (1 << 12) | (1 << 13); @@ -432,7 +440,7 @@ static void enable_lp_clock_gating(struct device *dev) * RCBA + 0x2614[30:28] = 0x0 * RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b) */ - RCBA32_AND_OR(0x2614, 0x8bffffff, 0x0a206500); + RCBA32_AND_OR(0x2614, ~0x74000000, 0x0a206500); /* Check for LPT-LP B2 stepping and 0:31.0@0xFA > 4 */ struct device *const gma = pcidev_on_root(2, 0); @@ -463,8 +471,8 @@ static void enable_lp_clock_gating(struct device *dev) RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic - pch_iobp_update(0xCF000000, ~0UL, 0x00007001); - pch_iobp_update(0xCE00C000, ~1UL, 0x00000000); // bit0=0 in BWG 1.4.0 + pch_iobp_update(0xCF000000, ~0, 0x00007001); + pch_iobp_update(0xCE00C000, ~1, 0x00000000); // bit0=0 in BWG 1.4.0 } static void pch_set_acpi_mode(void) @@ -737,7 +745,6 @@ static unsigned long southbridge_write_acpi_tables(const struct device *device, struct acpi_rsdp *rsdp) { unsigned long current; - acpi_hpet_t *hpet; acpi_header_t *ssdt; current = start; @@ -748,13 +755,7 @@ static unsigned long southbridge_write_acpi_tables(const struct device *device, /* * We explicitly add these tables later on: */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - - hpet = (acpi_hpet_t *)current; - current += sizeof(acpi_hpet_t); - current = acpi_align_current(current); - acpi_create_intel_hpet(hpet); - acpi_add_table(rsdp, hpet); + current = acpi_write_hpet(device, current, rsdp); current = acpi_align_current(current); diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index adc011bb7b..1a338b14ec 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -97,31 +97,31 @@ void pch_disable_devfn(struct device *dev) break; case PCI_DEVFN(21, 0): /* DMA */ pch_enable_d3hot(dev); - pch_iobp_update(SIO_IOBP_FUNCDIS0, ~0UL, SIO_IOBP_FUNCDIS_DIS); + pch_iobp_update(SIO_IOBP_FUNCDIS0, ~0, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 1): /* I2C0 */ pch_enable_d3hot(dev); - pch_iobp_update(SIO_IOBP_FUNCDIS1, ~0UL, SIO_IOBP_FUNCDIS_DIS); + pch_iobp_update(SIO_IOBP_FUNCDIS1, ~0, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 2): /* I2C1 */ pch_enable_d3hot(dev); - pch_iobp_update(SIO_IOBP_FUNCDIS2, ~0UL, SIO_IOBP_FUNCDIS_DIS); + pch_iobp_update(SIO_IOBP_FUNCDIS2, ~0, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 3): /* SPI0 */ pch_enable_d3hot(dev); - pch_iobp_update(SIO_IOBP_FUNCDIS3, ~0UL, SIO_IOBP_FUNCDIS_DIS); + pch_iobp_update(SIO_IOBP_FUNCDIS3, ~0, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 4): /* SPI1 */ pch_enable_d3hot(dev); - pch_iobp_update(SIO_IOBP_FUNCDIS4, ~0UL, SIO_IOBP_FUNCDIS_DIS); + pch_iobp_update(SIO_IOBP_FUNCDIS4, ~0, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 5): /* UART0 */ pch_enable_d3hot(dev); - pch_iobp_update(SIO_IOBP_FUNCDIS5, ~0UL, SIO_IOBP_FUNCDIS_DIS); + pch_iobp_update(SIO_IOBP_FUNCDIS5, ~0, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 6): /* UART1 */ pch_enable_d3hot(dev); - pch_iobp_update(SIO_IOBP_FUNCDIS6, ~0UL, SIO_IOBP_FUNCDIS_DIS); + pch_iobp_update(SIO_IOBP_FUNCDIS6, ~0, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(22, 0): /* MEI #1 */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); @@ -137,7 +137,7 @@ void pch_disable_devfn(struct device *dev) break; case PCI_DEVFN(23, 0): /* SDIO */ pch_enable_d3hot(dev); - pch_iobp_update(SIO_IOBP_FUNCDIS7, ~0UL, SIO_IOBP_FUNCDIS_DIS); + pch_iobp_update(SIO_IOBP_FUNCDIS7, ~0, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ RCBA32_OR(BUC, PCH_DISABLE_GBE); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 1ecad62796..66cd05e66a 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -120,7 +120,6 @@ void disable_gpe(u32 mask); void pch_enable(struct device *dev); void pch_disable_devfn(struct device *dev); void pch_log_state(void); -void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); void enable_usb_bar(void); @@ -168,7 +167,7 @@ void mainboard_config_rcba(void); #define GEN_PMCON_2 0xa2 #define GEN_PMCON_3 0xa4 #define PMIR 0xac -#define PMIR_CF9LOCK (1UL << 31) +#define PMIR_CF9LOCK (1 << 31) #define PMIR_CF9GR (1 << 20) /* GEN_PMCON_3 bits */ @@ -316,7 +315,7 @@ void mainboard_config_rcba(void); #define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ #define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ #define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ -#define XHCI_USB3_PORTSC_WPR (1UL << 31) /* Warm Port Reset */ +#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ #define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ #define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */ #define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */ @@ -409,7 +408,7 @@ void mainboard_config_rcba(void); #define RPFN 0x0404 /* 32bit */ /* Root Port configuratinon space hide */ -#define RPFN_HIDE(port) (1UL << (((port) * 4) + 3)) +#define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) /* Get the function number assigned to a Root Port */ #define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) /* Set the function number for a Root Port */ diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 308d3c32ce..510440b76a 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -122,7 +122,7 @@ static void sata_init(struct device *dev) reg32 |= 1 << 18; /* BWG step 10 */ reg32 |= 1 << 29; /* BWG step 11 */ if (pch_is_lp()) { - reg32 &= ~((1UL << 31) | (1 << 30)); + reg32 &= ~((1 << 31) | (1 << 30)); reg32 |= 1 << 23; reg32 |= 1 << 24; /* Disable listen mode (hotplug) */ } @@ -283,7 +283,7 @@ static void sata_init(struct device *dev) reg32 = pci_read_config32(dev, 0x300); reg32 |= (1 << 17) | (1 << 16); - reg32 |= (1UL << 31) | (1 << 30) | (1 << 29); + reg32 |= (1 << 31) | (1 << 30) | (1 << 29); pci_write_config32(dev, 0x300, reg32); } diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 9a5e5c0561..9c68a54f06 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -144,12 +144,12 @@ static void southbridge_smi_sleep(void) /* Always set the flag in case CMOS was changed on runtime. For * "KEEP", switch to "OFF" - KEEP is software emulated */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); if (s5pwr == MAINBOARD_POWER_ON) reg8 &= ~1; else reg8 |= 1; - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); + pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); @@ -348,7 +348,7 @@ static void southbridge_smi_pm1(void) if (pm1_sts & PWRBTN_STS) { /* power button pressed */ elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); - disable_pm1_control(-1UL); + disable_pm1_control(-1); enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10)); } } @@ -387,7 +387,7 @@ static void southbridge_smi_tco(void) // BIOSWR if (tco_sts & (1 << 8)) { - u8 bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); + u8 bios_cntl = pci_read_config16(PCH_LPC_DEV, BIOS_CNTL); if (bios_cntl & 1) { /* @@ -401,7 +401,7 @@ static void southbridge_smi_tco(void) * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); + pci_write_config32(PCH_LPC_DEV, BIOS_CNTL, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ diff --git a/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S b/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S index 88bbf7e98a..15340d58ae 100644 --- a/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S +++ b/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S @@ -72,7 +72,7 @@ ENTRY(_psp_vs_start) // to main BL using Svc_Exit(). // ShouldNotBeReached: - mov r0, #BL_UAPP_ERR_GENERIC // Returned from Main + mov r0, #BL_ERR_GENERIC // Returned from Main svc #0x0 // SVC_EXIT ENDPROC(_psp_vs_start) @@ -95,7 +95,7 @@ ENTRY(AllocateStack) bne ret svcExit: - mov r0, #BL_UAPP_ERR_GENERIC + mov r0, #BL_ERR_GENERIC svc #0x0 // SVC_EXIT ret: diff --git a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_errorcodes_public.h b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_errorcodes_public.h index ab24750f60..1d5e86ffb1 100644 --- a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_errorcodes_public.h +++ b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_errorcodes_public.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (c) 2019, Advanced Micro Devices, Inc. + * Copyright (c) 2020, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -30,7 +30,51 @@ #ifndef BL_ERRORCODES_PUBLIC_H #define BL_ERRORCODES_PUBLIC_H -#define BL_UAPP_OK 0x00 // General - Success -#define BL_UAPP_ERR_GENERIC 0x01 // Generic Error Code +/* Bootloader Return Codes, Error only (0x00 through 0x9F) */ +#define BL_OK 0x00 // General - Success +#define BL_ERR_GENERIC 0x01 // Generic Error Code +#define BL_ERR_MEMORY 0x02 // Generic Memory Error +#define BL_ERR_BUFFER_OVERFLOW 0x03 // Buffer Overflow +#define BL_ERR_INVALID_PARAMETER 0x04 // Invalid Parameter(s) +#define BL_ERR_DATA_ALIGNMENT 0x06 // Data Alignment Error +#define BL_ERR_NULL_PTR 0x07 // Null Pointer Error +#define BL_ERR_INVALID_ADDRESS 0x0A // Invalid Address +#define BL_ERR_OUT_OF_RESOURCES 0x0B // Out of Resource Error +#define BL_ERR_DATA_ABORT 0x0D // Data Abort exception +#define BL_ERR_PREFETCH_ABORT 0x0E // Prefetch Abort exception +#define BL_ERR_GET_FW_HEADER 0x13 // Failure in retrieving firmware + // header +#define BL_ERR_KEY_SIZE 0x14 // Key size not supported +#define BL_ERR_ENTRY_NOT_FOUND 0x15 // Entry not found at requested + // location +#define BL_ERR_UNSUPPORTED_PLATFORM 0x16 // Error when feature is not enabled + // on a given platform. +#define BL_ERR_FWVALIDATION 0x18 // Generic FW Validation error +#define BL_ERR_CCP_RSA 0x19 // RSA operation fail - bootloader +#define BL_ERR_CCP_PASSTHR 0x1A // CCP Passthrough operation failed +#define BL_ERR_CCP_AES 0x1B // AES operation failed +#define BL_ERR_SHA 0x1E // SHA256/SHA384 operation failed +#define BL_ERR_ZLIB 0x1F // ZLib Decompression operation fail +#define BL_ERR_DIR_ENTRY_NOT_FOUND 0x22 // PSP directory entry not found +#define BL_ERR_SYSHUBMAP_FAILED 0x3A // Unable to map a SYSHUB address to + // AXI space +#define BL_ERR_UAPP_PSP_HEADER_NOT_MATCH 0x7A // PSP level directory from OEM user- + // app does not match expected value. +#define BL_ERR_UAPP_BIOS_HEADER_NOT_MATCH 0x7B // BIOS level directory from OEM + // user-app not match expected value. +#define BL_ERR_UAPP_PSP_DIR_OFFSET_NOT_SET 0x7C // PSP Directory offset is not set + // by OEM user-app. +#define BL_ERR_UAPP_BIOS_DIR_OFFSET_NOT_SET 0x7D // BIOS Directory offset is not set + // by OEM user-app. +#define BL_ERR_POSTCODE_MAX_VALUE 0x9F // The maximum allowable error post -#endif // BL_ERRORCODES_PUBLIC_H +/* Bootloader Return Codes, Success only (0xA0 through 0xFF) */ +#define BL_SUCCESS_USERMODE_OEM_APP 0xF7 // Updated only PSPFW Status when OEM + // PSP BL user app returns success. +#define BL_SUCCESS_PSP_BIOS_DIRECTORY_UPDATE 0xF8 // PSP and BIOS directories are loaded + // into SRAM from the offset provided + // by OEM user app. + +#define BL_SUCCESS_LAST_CODE 0xFF // Bootloader sequence finished + +#endif /* BL_ERRORCODES_PUBLIC_H */ diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index 28592cd47c..6038b13eff 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -2498,7 +2498,7 @@ typedef struct { /** Offset 0x091C - Reserved **/ - UINT8 Reserved45[12]; + UINT8 Reserved45[36]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -2517,11 +2517,11 @@ typedef struct { **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0928 +/** Offset 0x0940 **/ UINT8 UnusedUpdSpace27[6]; -/** Offset 0x092E +/** Offset 0x0946 **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/util/amdfwtool/.gitignore b/util/amdfwtool/.gitignore new file mode 100644 index 0000000000..cac1859b43 --- /dev/null +++ b/util/amdfwtool/.gitignore @@ -0,0 +1 @@ +amdfwtool diff --git a/util/amdfwtool/Makefile b/util/amdfwtool/Makefile index 8f4208c354..58606e3ed0 100644 --- a/util/amdfwtool/Makefile +++ b/util/amdfwtool/Makefile @@ -2,7 +2,7 @@ HOSTCC ?= cc -SRC = amdfwtool.c +SRC = amdfwtool.c data_parse.c OBJ = $(SRC:%.c=%.o) TARGET = amdfwtool CFLAGS=-O2 -Wall -Wextra -Wshadow diff --git a/util/amdfwtool/Makefile.inc b/util/amdfwtool/Makefile.inc index b1a21308fd..e794ed9009 100644 --- a/util/amdfwtool/Makefile.inc +++ b/util/amdfwtool/Makefile.inc @@ -1,6 +1,6 @@ # SPDX-License-Identifier: BSD-3-Clause -amdfwtoolobj = amdfwtool.o +amdfwtoolobj = amdfwtool.o data_parse.o AMDFWTOOLCFLAGS=-O2 -Wall -Wextra -Wshadow diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index f5030d381c..561b511e3d 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -56,6 +56,9 @@ #include #include #include +#include + +#include "amdfwtool.h" #define AMD_ROMSIG_OFFSET 0x20000 #define MIN_ROM_KB 256 @@ -94,13 +97,6 @@ */ #define PSP_COMBO 0 -#if defined(__GLIBC__) -typedef unsigned long long int uint64_t; -typedef unsigned int uint32_t; -typedef unsigned char uint8_t; -typedef unsigned short uint16_t; -#endif - /* * Creates the OSI Fletcher checksum. See 8473-1, Appendix C, section C.3. * The checksum field of the passed PDU does not need to be reset to zero. @@ -165,39 +161,22 @@ static void usage(void) printf("-A | --combo-capable Place PSP directory pointer at Embedded Firmware\n"); printf(" offset able to support combo directory\n"); printf("-M | --multilevel Generate primary and secondary tables\n"); - printf("-p | --pubkey Add pubkey\n"); - printf("-b | --bootloader Add bootloader\n"); - printf("-S | --subprogram Sets subprogram field for the next firmware\n"); - printf("-s | --smufirmware Add smufirmware\n"); - printf("-r | --recovery Add recovery\n"); - printf("-k | --rtmpubkey Add rtmpubkey\n"); - printf("-c | --secureos Add secureos\n"); - printf("-n | --nvram Add nvram\n"); - printf("-d | --securedebug Add securedebug\n"); - printf("-t | --trustlets Add trustlets\n"); - printf("-u | --trustletkey Add trustletkey\n"); - printf("-w | --smufirmware2 Add smufirmware2\n"); - printf("-m | --smuscs Add smuscs\n"); - printf("-T | --soft-fuse Override default soft fuse values\n"); - printf("-z | --abl-image Add AGESA Binary\n"); - printf("-J | --sec-gasket Add security gasket\n"); - printf("-B | --mp2-fw Add MP2 firmware\n"); - printf("-N | --secdebug Add secure unlock image\n"); - printf("-U | --token-unlock Reserve space for debug token\n"); - printf("-K | --drv-entry-pts Add PSP driver entry points\n"); - printf("-L | --ikek Add Wrapped iKEK\n"); - printf("-Y | --s0i3drv Add s0i3 driver\n"); + printf("-n | --nvram Add nvram binary\n"); + printf("-T | --soft-fuse Set soft fuse\n"); + printf("-U | --token-unlock Set token unlock\n"); + printf("-W | --whitelist Set if there is a whitelist\n"); + printf("-S | --use-pspsecureos Set if psp secure OS is needed\n"); + printf("-p | --load-mp2-fw Set if load MP2 firmware\n"); + printf("-L | --load-s0i3 Set if load s0i3 firmware\n"); printf("-Z | --verstage Add verstage\n"); + printf("-E | --verstage_sig Add verstage signature"); printf("\nBIOS options:\n"); printf("-I | --instance Sets instance field for the next BIOS firmware\n"); printf("-a | --apcb Add AGESA PSP customization block\n"); printf("-Q | --apob-base Destination for AGESA PSP output block\n"); printf("-F | --apob-nv-base Location of S3 resume data\n"); printf("-H | --apob-nv-size Size of S3 resume data\n"); - printf("-y | --pmu-inst Add PMU firmware instruction portion\n"); - printf("-G | --pmu-data Add PMU firmware data portion\n"); printf("-O | --ucode Add microcode patch\n"); - printf("-X | --mp2-config Add MP2 configuration\n"); printf("-V | --bios-bin Add compressed image; auto source address\n"); printf("-e | --bios-bin-src Address in flash of source if -V not used\n"); printf("-v | --bios-bin-dest Destination for uncompressed BIOS\n"); @@ -236,93 +215,11 @@ static void usage(void) printf(" 0x1 Micron parts are always used\n"); printf(" 0x2 Micron parts optional, this option is only\n"); printf(" supported with RN/LCN SOC\n"); + printf("-c | --config Config file\n"); + printf("-D | --depend List out the firmware files\n"); } -typedef enum _amd_bios_type { - AMD_BIOS_APCB = 0x60, - AMD_BIOS_APOB = 0x61, - AMD_BIOS_BIN = 0x62, - AMD_BIOS_APOB_NV = 0x63, - AMD_BIOS_PMUI = 0x64, - AMD_BIOS_PMUD = 0x65, - AMD_BIOS_UCODE = 0x66, - AMD_BIOS_APCB_BK = 0x68, - AMD_BIOS_MP2_CFG = 0x6a, - AMD_BIOS_PSP_SHARED_MEM = 0x6b, - AMD_BIOS_L2_PTR = 0x70, - AMD_BIOS_INVALID, -} amd_bios_type; - -#define BDT_LVL1 0x1 -#define BDT_LVL2 0x2 -#define BDT_BOTH (BDT_LVL1 | BDT_LVL2) -typedef struct _amd_bios_entry { - amd_bios_type type; - int region_type; - int reset; - int copy; - int ro; - int zlib; - int inst; - int subpr; - uint64_t src; - uint64_t dest; - size_t size; - char *filename; - int level; -} amd_bios_entry; - -typedef enum _amd_fw_type { - AMD_FW_PSP_PUBKEY = 0, - AMD_FW_PSP_BOOTLOADER = 1, - AMD_FW_PSP_SMU_FIRMWARE = 8, - AMD_FW_PSP_RECOVERY = 3, - AMD_FW_PSP_RTM_PUBKEY = 5, - AMD_FW_PSP_SECURED_OS = 2, - AMD_FW_PSP_NVRAM = 4, - AMD_FW_PSP_SECURED_DEBUG = 9, - AMD_FW_PSP_TRUSTLETS = 12, - AMD_FW_PSP_TRUSTLETKEY = 13, - AMD_FW_PSP_SMU_FIRMWARE2 = 18, - AMD_PSP_FUSE_CHAIN = 11, - AMD_FW_PSP_SMUSCS = 95, - AMD_DEBUG_UNLOCK = 0x13, - AMD_WRAPPED_IKEK = 0x21, - AMD_TOKEN_UNLOCK = 0x22, - AMD_SEC_GASKET = 0x24, - AMD_MP2_FW = 0x25, - AMD_DRIVER_ENTRIES = 0x28, - AMD_S0I3_DRIVER = 0x2d, - AMD_ABL0 = 0x30, - AMD_ABL1 = 0x31, - AMD_ABL2 = 0x32, - AMD_ABL3 = 0x33, - AMD_ABL4 = 0x34, - AMD_ABL5 = 0x35, - AMD_ABL6 = 0x36, - AMD_ABL7 = 0x37, - AMD_FW_PSP_WHITELIST = 0x3a, - AMD_FW_L2_PTR = 0x40, - AMD_FW_PSP_VERSTAGE = 0x52, - AMD_FW_VERSTAGE_SIG = 0x53, - AMD_FW_IMC, - AMD_FW_GEC, - AMD_FW_XHCI, - AMD_FW_INVALID, -} amd_fw_type; - -#define PSP_LVL1 0x1 -#define PSP_LVL2 0x2 -#define PSP_BOTH (PSP_LVL1 | PSP_LVL2) -typedef struct _amd_fw_entry { - amd_fw_type type; - uint8_t subprog; - char *filename; - int level; - uint64_t other; -} amd_fw_entry; - -static amd_fw_entry amd_psp_fw_table[] = { +amd_fw_entry amd_psp_fw_table[] = { { .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH }, { .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH }, { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH }, @@ -365,14 +262,14 @@ static amd_fw_entry amd_psp_fw_table[] = { { .type = AMD_FW_INVALID }, }; -static amd_fw_entry amd_fw_table[] = { +amd_fw_entry amd_fw_table[] = { { .type = AMD_FW_XHCI }, { .type = AMD_FW_IMC }, { .type = AMD_FW_GEC }, { .type = AMD_FW_INVALID }, }; -static amd_bios_entry amd_bios_table[] = { +amd_bios_entry amd_bios_table[] = { { .type = AMD_BIOS_APCB, .inst = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB, .inst = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB, .inst = 2, .level = BDT_BOTH }, @@ -699,6 +596,33 @@ static void integrate_firmwares(context *ctx, } } +static void free_psp_firmware_filenames(amd_fw_entry *fw_table) +{ + amd_fw_entry *index; + + for (index = fw_table; index->type != AMD_FW_INVALID; index++) { + if (index->filename && + index->type != AMD_FW_VERSTAGE_SIG && + index->type != AMD_FW_PSP_VERSTAGE && + index->type != AMD_FW_PSP_WHITELIST) { + free(index->filename); + } + } +} + +static void free_bdt_firmware_filenames(amd_bios_entry *fw_table) +{ + amd_bios_entry *index; + + for (index = fw_table; index->type != AMD_BIOS_INVALID; index++) { + if (index->filename && + index->type != AMD_BIOS_APCB && + index->type != AMD_BIOS_BIN && + index->type != AMD_BIOS_APCB_BK) + free(index->filename); + } +} + static void integrate_psp_firmwares(context *ctx, psp_directory_table *pspdir, psp_directory_table *pspdir2, @@ -1083,8 +1007,9 @@ enum { LONGOPT_SPI_MICRON_FLAG = 258, }; -// Unused values: D -static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:C:E:"; +/* Unused values: BGJKNXYbdkmprstuwyz*/ +static const char *optstring = "x:i:g:AMn:T:SPLUW:I:a:Q:V:e:v:j:O:F:" + "H:o:f:l:hZ:qR:C:c:E:D"; static struct option long_options[] = { {"xhci", required_argument, 0, 'x' }, @@ -1093,29 +1018,13 @@ static struct option long_options[] = { /* PSP Directory Table items */ {"combo-capable", no_argument, 0, 'A' }, {"multilevel", no_argument, 0, 'M' }, - {"subprogram", required_argument, 0, 'S' }, - {"pubkey", required_argument, 0, 'p' }, - {"bootloader", required_argument, 0, 'b' }, - {"smufirmware", required_argument, 0, 's' }, - {"recovery", required_argument, 0, 'r' }, - {"rtmpubkey", required_argument, 0, 'k' }, - {"secureos", required_argument, 0, 'c' }, {"nvram", required_argument, 0, 'n' }, - {"securedebug", required_argument, 0, 'd' }, - {"trustlets", required_argument, 0, 't' }, - {"trustletkey", required_argument, 0, 'u' }, - {"smufirmware2", required_argument, 0, 'w' }, - {"smuscs", required_argument, 0, 'm' }, {"soft-fuse", required_argument, 0, 'T' }, - {"abl-image", required_argument, 0, 'z' }, - {"sec-gasket", required_argument, 0, 'J' }, - {"mp2-fw", required_argument, 0, 'B' }, - {"drv-entry-pts", required_argument, 0, 'K' }, - {"ikek", required_argument, 0, 'L' }, - {"s0i3drv", required_argument, 0, 'Y' }, - {"secdebug", required_argument, 0, 'N' }, {"token-unlock", no_argument, 0, 'U' }, {"whitelist", required_argument, 0, 'W' }, + {"use-pspsecureos", no_argument, 0, 'S' }, + {"load-mp2-fw", no_argument, 0, 'p' }, + {"load-s0i3", no_argument, 0, 'L' }, {"verstage", required_argument, 0, 'Z' }, {"verstage_sig", required_argument, 0, 'E' }, /* BIOS Directory Table items */ @@ -1126,10 +1035,7 @@ static struct option long_options[] = { {"bios-bin-src", required_argument, 0, 'e' }, {"bios-bin-dest", required_argument, 0, 'v' }, {"bios-uncomp-size", required_argument, 0, 'j' }, - {"pmu-inst", required_argument, 0, 'y' }, - {"pmu-data", required_argument, 0, 'G' }, {"ucode", required_argument, 0, 'O' }, - {"mp2-config", required_argument, 0, 'X' }, {"apob-nv-base", required_argument, 0, 'F' }, {"apob-nv-size", required_argument, 0, 'H' }, /* Embedded Firmware Structure items*/ @@ -1144,11 +1050,14 @@ static struct option long_options[] = { {"sharedmem", required_argument, 0, 'R' }, {"sharedmem-size", required_argument, 0, 'P' }, {"soc-name", required_argument, 0, 'C' }, + + {"config", required_argument, 0, 'c' }, {"help", no_argument, 0, 'h' }, + {"depend", no_argument, 0, 'D' }, {NULL, 0, 0, 0 } }; -static void register_fw_fuse(char *str) +void register_fw_fuse(char *str) { uint32_t i; @@ -1325,11 +1234,11 @@ int main(int argc, char **argv) int comboable = 0; int fuse_defined = 0; int targetfd; - char *output = NULL; + char *output = NULL, *config = NULL; + FILE *config_handle; context ctx = { 0 }; /* Values cleared after each firmware or parameter, regardless if N/A */ uint8_t sub = 0, instance = 0; - int abl_image = 0; uint32_t dir_location = 0; bool any_location = 0; uint32_t romsig_offset; @@ -1340,6 +1249,14 @@ int main(int argc, char **argv) uint8_t efs_spi_micron_flag = 0xff; int multi = 0; + amd_cb_config cb_config; + int list_deps = 0; + + cb_config.have_whitelist = 0; + cb_config.unlock_secure = 0; + cb_config.use_secureos = 0; + cb_config.load_mp2_fw = 0; + cb_config.s0i3 = 0; while (1) { int optindex = 0; @@ -1370,69 +1287,22 @@ int main(int argc, char **argv) break; case 'U': register_fw_token_unlock(); + cb_config.unlock_secure = 1; sub = instance = 0; break; case 'S': - sub = (uint8_t)strtoul(optarg, &tmp, 16); + cb_config.use_secureos = 1; break; case 'I': instance = strtoul(optarg, &tmp, 16); break; case 'p': - register_fw_filename(AMD_FW_PSP_PUBKEY, sub, optarg); - sub = instance = 0; - break; - case 'b': - register_fw_filename(AMD_FW_PSP_BOOTLOADER, - sub, optarg); - sub = instance = 0; - break; - case 's': - register_fw_filename(AMD_FW_PSP_SMU_FIRMWARE, - sub, optarg); - sub = instance = 0; - break; - case 'r': - register_fw_filename(AMD_FW_PSP_RECOVERY, sub, optarg); - sub = instance = 0; - break; - case 'k': - register_fw_filename(AMD_FW_PSP_RTM_PUBKEY, - sub, optarg); - sub = instance = 0; - break; - case 'c': - register_fw_filename(AMD_FW_PSP_SECURED_OS, - sub, optarg); - sub = instance = 0; + cb_config.load_mp2_fw = 1; break; case 'n': register_fw_filename(AMD_FW_PSP_NVRAM, sub, optarg); sub = instance = 0; break; - case 'd': - register_fw_filename(AMD_FW_PSP_SECURED_DEBUG, - sub, optarg); - sub = instance = 0; - break; - case 't': - register_fw_filename(AMD_FW_PSP_TRUSTLETS, sub, optarg); - sub = instance = 0; - break; - case 'u': - register_fw_filename(AMD_FW_PSP_TRUSTLETKEY, - sub, optarg); - sub = instance = 0; - break; - case 'w': - register_fw_filename(AMD_FW_PSP_SMU_FIRMWARE2, - sub, optarg); - sub = instance = 0; - break; - case 'm': - register_fw_filename(AMD_FW_PSP_SMUSCS, sub, optarg); - sub = instance = 0; - break; case 'T': register_fw_fuse(optarg); fuse_defined = 1; @@ -1478,56 +1348,18 @@ int main(int argc, char **argv) register_fw_addr(AMD_BIOS_BIN, 0, 0, optarg); sub = instance = 0; break; - case 'y': - register_bdt_data(AMD_BIOS_PMUI, sub, instance, optarg); - sub = instance = 0; - break; - case 'G': - register_bdt_data(AMD_BIOS_PMUD, sub, instance, optarg); - sub = instance = 0; - break; case 'O': register_bdt_data(AMD_BIOS_UCODE, sub, instance, optarg); sub = instance = 0; break; - case 'J': - register_fw_filename(AMD_SEC_GASKET, sub, optarg); - sub = instance = 0; - break; - case 'B': - register_fw_filename(AMD_MP2_FW, sub, optarg); - sub = instance = 0; - break; - case 'z': - register_fw_filename(AMD_ABL0 + abl_image++, - sub, optarg); - sub = instance = 0; - break; - case 'X': - register_bdt_data(AMD_BIOS_MP2_CFG, sub, - instance, optarg); - sub = instance = 0; - break; - case 'K': - register_fw_filename(AMD_DRIVER_ENTRIES, sub, optarg); - sub = instance = 0; - break; case 'L': - register_fw_filename(AMD_WRAPPED_IKEK, sub, optarg); - sub = instance = 0; - break; - case 'Y': - register_fw_filename(AMD_S0I3_DRIVER, sub, optarg); - sub = instance = 0; - break; - case 'N': - register_fw_filename(AMD_DEBUG_UNLOCK, sub, optarg); - sub = instance = 0; + cb_config.s0i3 = 1; break; case 'W': register_fw_filename(AMD_FW_PSP_WHITELIST, sub, optarg); sub = instance = 0; + cb_config.have_whitelist = 1; break; case 'Z': register_fw_filename(AMD_FW_PSP_VERSTAGE, sub, optarg); @@ -1590,30 +1422,50 @@ int main(int argc, char **argv) sub = instance = 0; break; + case 'c': + config = optarg; + break; case 'h': usage(); return 0; + case 'D': + list_deps = 1; + break; default: break; } } + if (config) { + config_handle = fopen(config, "r"); + if (config_handle == NULL) { + fprintf(stderr, "Can not open file %s for reading: %s\n", + config, strerror(errno)); + exit(1); + } + if (process_config(config_handle, &cb_config, list_deps) == 0) { + fprintf(stderr, "Configuration file %s parsing error\n", config); + fclose(config_handle); + exit(1); + } + fclose(config_handle); + } if (!fuse_defined) register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN); - if (!output) { - printf("Error: Output value is not specified.\n\n"); + if (!output && !list_deps) { + fprintf(stderr, "Error: Output value is not specified.\n\n"); retval = 1; } - if (ctx.rom_size % 1024 != 0) { - printf("Error: ROM Size (%d bytes) should be a multiple of" + if ((ctx.rom_size % 1024 != 0) && !list_deps) { + fprintf(stderr, "Error: ROM Size (%d bytes) should be a multiple of" " 1024 bytes.\n\n", ctx.rom_size); retval = 1; } - if (ctx.rom_size < MIN_ROM_KB * 1024) { - printf("Error: ROM Size (%dKB) must be at least %dKB.\n\n", + if ((ctx.rom_size < MIN_ROM_KB * 1024) && !list_deps) { + fprintf(stderr, "Error: ROM Size (%dKB) must be at least %dKB.\n\n", ctx.rom_size / 1024, MIN_ROM_KB); retval = 1; } @@ -1623,6 +1475,10 @@ int main(int argc, char **argv) return retval; } + if (list_deps) { + return retval; + } + printf(" AMDFWTOOL Using ROM size of %dKB\n", ctx.rom_size / 1024); rom_base_address = 0xFFFFFFFF - ctx.rom_size + 1; @@ -1745,6 +1601,10 @@ int main(int argc, char **argv) amd_romsig->bios1_entry = BUFF_TO_RUN(ctx, biosdir); } + /* Free the filename. */ + free_psp_firmware_filenames(amd_psp_fw_table); + free_bdt_firmware_filenames(amd_bios_table); + targetfd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0666); if (targetfd >= 0) { ssize_t bytes; diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h new file mode 100644 index 0000000000..198642c077 --- /dev/null +++ b/util/amdfwtool/amdfwtool.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _AMD_FW_TOOL_H_ +#define _AMD_FW_TOOL_H_ + +#if defined(__GLIBC__) +typedef unsigned long long int uint64_t; +typedef unsigned int uint32_t; +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +#endif + + +typedef enum _amd_fw_type { + AMD_FW_PSP_PUBKEY = 0, + AMD_FW_PSP_BOOTLOADER = 1, + AMD_FW_PSP_SMU_FIRMWARE = 8, + AMD_FW_PSP_RECOVERY = 3, + AMD_FW_PSP_RTM_PUBKEY = 5, + AMD_FW_PSP_SECURED_OS = 2, + AMD_FW_PSP_NVRAM = 4, + AMD_FW_PSP_SECURED_DEBUG = 9, + AMD_FW_PSP_TRUSTLETS = 12, + AMD_FW_PSP_TRUSTLETKEY = 13, + AMD_FW_PSP_SMU_FIRMWARE2 = 18, + AMD_PSP_FUSE_CHAIN = 11, + AMD_FW_PSP_SMUSCS = 95, + AMD_DEBUG_UNLOCK = 0x13, + AMD_WRAPPED_IKEK = 0x21, + AMD_TOKEN_UNLOCK = 0x22, + AMD_SEC_GASKET = 0x24, + AMD_MP2_FW = 0x25, + AMD_DRIVER_ENTRIES = 0x28, + AMD_S0I3_DRIVER = 0x2d, + AMD_ABL0 = 0x30, + AMD_ABL1 = 0x31, + AMD_ABL2 = 0x32, + AMD_ABL3 = 0x33, + AMD_ABL4 = 0x34, + AMD_ABL5 = 0x35, + AMD_ABL6 = 0x36, + AMD_ABL7 = 0x37, + AMD_FW_PSP_WHITELIST = 0x3a, + AMD_FW_L2_PTR = 0x40, + AMD_FW_PSP_VERSTAGE = 0x52, + AMD_FW_VERSTAGE_SIG = 0x53, + AMD_FW_IMC = 0x200, /* Large enough to be larger than the top BHD entry type. */ + AMD_FW_GEC, + AMD_FW_XHCI, + AMD_FW_INVALID, /* Real last one to detect the last entry in table. */ + AMD_FW_SKIP /* This is for non-applicable options. */ +} amd_fw_type; + +typedef enum _amd_bios_type { + AMD_BIOS_APCB = 0x60, + AMD_BIOS_APOB = 0x61, + AMD_BIOS_BIN = 0x62, + AMD_BIOS_APOB_NV = 0x63, + AMD_BIOS_PMUI = 0x64, + AMD_BIOS_PMUD = 0x65, + AMD_BIOS_UCODE = 0x66, + AMD_BIOS_APCB_BK = 0x68, + AMD_BIOS_MP2_CFG = 0x6a, + AMD_BIOS_PSP_SHARED_MEM = 0x6b, + AMD_BIOS_L2_PTR = 0x70, + AMD_BIOS_INVALID, + AMD_BIOS_SKIP +} amd_bios_type; + + +#define BDT_LVL1 0x1 +#define BDT_LVL2 0x2 +#define BDT_BOTH (BDT_LVL1 | BDT_LVL2) +typedef struct _amd_bios_entry { + amd_bios_type type; + char *filename; + int subpr; + int region_type; + int reset; + int copy; + int ro; + int zlib; + int inst; + uint64_t src; + uint64_t dest; + size_t size; + int level; +} amd_bios_entry; + + +#define PSP_LVL1 0x1 +#define PSP_LVL2 0x2 +#define PSP_BOTH (PSP_LVL1 | PSP_LVL2) +typedef struct _amd_fw_entry { + amd_fw_type type; + char *filename; + uint8_t subprog; + int level; + uint64_t other; +} amd_fw_entry; + +typedef struct _amd_cb_config { + uint8_t have_whitelist; + uint8_t unlock_secure; + uint8_t use_secureos; + uint8_t load_mp2_fw; + uint8_t s0i3; +} amd_cb_config; + +void register_fw_fuse(char *str); +uint8_t process_config(FILE *config, amd_cb_config *cb_config, uint8_t print_deps); + +#define OK 0 + +#define LINE_EOF (1) +#define LINE_TOO_LONG (2) + + +#endif /* _AMD_FW_TOOL_H_ */ diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c new file mode 100644 index 0000000000..bb616d3405 --- /dev/null +++ b/util/amdfwtool/data_parse.c @@ -0,0 +1,418 @@ +#include +#include +#include +#include + +#include "amdfwtool.h" + +/* TODO: a empty line does not matched. */ +static const char blank_or_comment_regex[] = + /* a blank line */ + "(^[[:space:]]*$)" + "|" /* or ... */ + /* a line consisting of: optional whitespace followed by */ + "(^[[:space:]]*" + /* a '#' character and optionally, additional characters */ + "#.*$)"; +static regex_t blank_or_comment_expr; + +static const char entries_line_regex[] = + /* optional whitespace */ + "^[[:space:]]*" + /* followed by a chunk of nonwhitespace for macro field */ + "([^[:space:]]+)" + /* followed by one or more whitespace characters */ + "[[:space:]]+" + /* followed by a chunk of nonwhitespace for filename field */ + "([^[:space:]]+)" + /* followed by optional whitespace */ + "[[:space:]]*$"; +static regex_t entries_line_expr; + +void compile_reg_expr(int cflags, const char *expr, regex_t *reg) +{ + static const size_t ERROR_BUF_SIZE = 256; + char error_msg[ERROR_BUF_SIZE]; + int result; + + result = regcomp(reg, expr, cflags); + if (result != 0) { + regerror(result, reg, error_msg, ERROR_BUF_SIZE); + printf("%s\n", error_msg); + } +} + +extern amd_fw_entry amd_psp_fw_table[]; +extern amd_bios_entry amd_bios_table[]; + +static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename, + amd_cb_config *cb_config) +{ + amd_fw_type fw_type = AMD_FW_INVALID; + amd_fw_entry *psp_tableptr; + uint8_t subprog; + + if (strcmp(fw_name, "PSPBTLDR_WL_FILE") == 0) { + if (cb_config->have_whitelist == 1) { + fw_type = AMD_FW_PSP_BOOTLOADER; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } + } else if (strcmp(fw_name, "PSPBTLDR_FILE") == 0) { + if (cb_config->have_whitelist == 0) { + fw_type = AMD_FW_PSP_BOOTLOADER; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } + } else if (strcmp(fw_name, "AMD_PUBKEY_FILE") == 0) { + fw_type = AMD_FW_PSP_PUBKEY; + subprog = 0; + } else if (strcmp(fw_name, "PSPRCVR_FILE") == 0) { + fw_type = AMD_FW_PSP_RECOVERY; + subprog = 0; + } else if (strcmp(fw_name, "PUBSIGNEDKEY_FILE") == 0) { + fw_type = AMD_FW_PSP_RTM_PUBKEY; + subprog = 0; + } else if (strcmp(fw_name, "PSPNVRAM_FILE") == 0) { + fw_type = AMD_FW_PSP_NVRAM; + subprog = 0; + } else if (strcmp(fw_name, "SMUSCS_FILE") == 0) { + fw_type = AMD_FW_PSP_SMUSCS; + subprog = 0; + } else if (strcmp(fw_name, "PSPTRUSTLETS_FILE") == 0) { + fw_type = AMD_FW_PSP_TRUSTLETS; + subprog = 0; + } else if (strcmp(fw_name, "PSPSECUREDEBUG_FILE") == 0) { + fw_type = AMD_FW_PSP_SECURED_DEBUG; + subprog = 0; + } else if (strcmp(fw_name, "PSP_SMUFW1_SUB0_FILE") == 0) { + fw_type = AMD_FW_PSP_SMU_FIRMWARE; + subprog = 0; + } else if (strcmp(fw_name, "PSP_SMUFW1_SUB1_FILE") == 0) { + fw_type = AMD_FW_PSP_SMU_FIRMWARE; + subprog = 1; + } else if (strcmp(fw_name, "PSP_SMUFW1_SUB2_FILE") == 0) { + fw_type = AMD_FW_PSP_SMU_FIRMWARE; + subprog = 2; + } else if (strcmp(fw_name, "PSP_SMUFW2_SUB0_FILE") == 0) { + fw_type = AMD_FW_PSP_SMU_FIRMWARE2; + subprog = 0; + } else if (strcmp(fw_name, "PSP_SMUFW2_SUB1_FILE") == 0) { + fw_type = AMD_FW_PSP_SMU_FIRMWARE2; + subprog = 1; + } else if (strcmp(fw_name, "PSP_SMUFW2_SUB2_FILE") == 0) { + fw_type = AMD_FW_PSP_SMU_FIRMWARE2; + subprog = 2; + } else if (strcmp(fw_name, "PSP_SEC_DBG_KEY_FILE") == 0) { + if (cb_config->unlock_secure == 1) { + fw_type = AMD_FW_PSP_SECURED_DEBUG; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } + } else if (strcmp(fw_name, "PSP_SEC_DEBUG_FILE") == 0) { + if (cb_config->unlock_secure == 1) { + fw_type = AMD_DEBUG_UNLOCK; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } + } else if (strcmp(fw_name, "PSP_ABL0_FILE") == 0) { + fw_type = AMD_ABL0; + subprog = 0; + } else if (strcmp(fw_name, "PSP_ABL1_FILE") == 0) { + fw_type = AMD_ABL1; + subprog = 0; + } else if (strcmp(fw_name, "PSP_ABL2_FILE") == 0) { + fw_type = AMD_ABL2; + subprog = 0; + } else if (strcmp(fw_name, "PSP_ABL3_FILE") == 0) { + fw_type = AMD_ABL3; + subprog = 0; + } else if (strcmp(fw_name, "PSP_ABL4_FILE") == 0) { + fw_type = AMD_ABL4; + subprog = 0; + } else if (strcmp(fw_name, "PSP_ABL5_FILE") == 0) { + fw_type = AMD_ABL5; + subprog = 0; + } else if (strcmp(fw_name, "PSP_ABL6_FILE") == 0) { + fw_type = AMD_ABL6; + subprog = 0; + } else if (strcmp(fw_name, "PSP_ABL7_FILE") == 0) { + fw_type = AMD_ABL7; + subprog = 0; + } else if (strcmp(fw_name, "PSPSECUREOS_FILE") == 0) { + if (cb_config->use_secureos == 1) { + fw_type = AMD_FW_PSP_SECURED_OS; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } + } else if (strcmp(fw_name, "PSPTRUSTLETS_FILE") == 0) { + if (cb_config->use_secureos) { + fw_type = AMD_FW_PSP_TRUSTLETS; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } + } else if (strcmp(fw_name, "TRUSTLETKEY_FILE") == 0) { + if (cb_config->use_secureos) { + fw_type = AMD_FW_PSP_TRUSTLETKEY; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } + } else if (strcmp(fw_name, "PSP_IKEK_FILE") == 0) { + fw_type = AMD_WRAPPED_IKEK; + subprog = 0; + } else if (strcmp(fw_name, "PSP_SECG1_FILE") == 0) { + fw_type = AMD_SEC_GASKET; + subprog = 1; + } else if (strcmp(fw_name, "PSP_SECG2_FILE") == 0) { + fw_type = AMD_SEC_GASKET; + subprog = 2; + } else if (strcmp(fw_name, "PSP_MP2FW1_FILE") == 0) { + if (cb_config->load_mp2_fw == 1) { + fw_type = AMD_MP2_FW; + subprog = 1; + } else { + fw_type = AMD_FW_SKIP; + } + } else if (strcmp(fw_name, "PSP_MP2FW2_FILE") == 0) { + if (cb_config->load_mp2_fw == 1) { + fw_type = AMD_MP2_FW; + subprog = 2; + } else { + fw_type = AMD_FW_SKIP; + } + } else if (strcmp(fw_name, "PSP_MP2CFG_FILE") == 0) { + if (cb_config->load_mp2_fw == 1) { + fw_type = AMD_BIOS_MP2_CFG; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } + } else if (strcmp(fw_name, "PSP_DRIVERS_FILE") == 0) { + fw_type = AMD_DRIVER_ENTRIES; + subprog = 0; + } else if (strcmp(fw_name, "PSP_S0I3_FILE") == 0) { + if (cb_config->s0i3 == 1) { + fw_type = AMD_S0I3_DRIVER; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } + } else { + fw_type = AMD_FW_INVALID; + /* TODO: Add more */ + } + /* Search and fill the filename */ + psp_tableptr = &amd_psp_fw_table[0]; + if (fw_type != AMD_FW_SKIP && fw_type != AMD_FW_INVALID) { + while (psp_tableptr->type != AMD_FW_INVALID) { + /* instance are not used in PSP table */ + if (psp_tableptr->type == fw_type && psp_tableptr->subprog == subprog) { + psp_tableptr->filename = filename; + break; + } + psp_tableptr++; + } + } + if (fw_type == AMD_FW_INVALID) + return 0; + else + return 1; +} + +static uint8_t find_register_fw_filename_bios_dir(char *fw_name, char *filename, + amd_cb_config *cb_config) +{ + amd_bios_type fw_type = AMD_BIOS_INVALID; + amd_bios_entry *bhd_tableptr; + uint8_t subprog, instance = 0; + + (void) (cb_config); /* Remove warning and reserved for future. */ + + if (strcmp(fw_name, "PSP_PMUI_FILE1") == 0) { + fw_type = AMD_BIOS_PMUI; + subprog = 0; + instance = 1; + } else if (strcmp(fw_name, "PSP_PMUI_FILE2") == 0) { + fw_type = AMD_BIOS_PMUI; + subprog = 0; + instance = 4; + } else if (strcmp(fw_name, "PSP_PMUI_FILE3") == 0) { + fw_type = AMD_BIOS_PMUI; + subprog = 1; + instance = 1; + } else if (strcmp(fw_name, "PSP_PMUI_FILE4") == 0) { + fw_type = AMD_BIOS_PMUI; + subprog = 1; + instance = 4; + } else if (strcmp(fw_name, "PSP_PMUD_FILE1") == 0) { + fw_type = AMD_BIOS_PMUD; + subprog = 0; + instance = 1; + } else if (strcmp(fw_name, "PSP_PMUD_FILE2") == 0) { + fw_type = AMD_BIOS_PMUD; + subprog = 0; + instance = 4; + } else if (strcmp(fw_name, "PSP_PMUD_FILE3") == 0) { + fw_type = AMD_BIOS_PMUD; + subprog = 1; + instance = 1; + } else if (strcmp(fw_name, "PSP_PMUD_FILE4") == 0) { + fw_type = AMD_BIOS_PMUD; + subprog = 1; + instance = 4; + } else { + fw_type = AMD_BIOS_INVALID; + } + + bhd_tableptr = amd_bios_table; + + if (fw_type != AMD_BIOS_INVALID && fw_type != AMD_BIOS_SKIP) { + while (bhd_tableptr->type != AMD_BIOS_INVALID) { + if (bhd_tableptr->type == fw_type && + bhd_tableptr->subpr == subprog && + bhd_tableptr->inst == instance) { + bhd_tableptr->filename = filename; + break; + } + bhd_tableptr++; + } + } + if (fw_type == AMD_BIOS_INVALID) + return 0; + else + return 1; +} + +#define MAX_LINE_SIZE 1024 + +int get_input_file_line(FILE *f, char line[], int line_buf_size) +{ + if (fgets(line, line_buf_size, f) == NULL) + return LINE_EOF; + + /* If the file contains a line that is too long, then it's best + * to let the user know right away rather than passing back a + * truncated result that will lead to problems later on. + */ + line[strlen(line) - 1] = '\0'; + + if (strlen(line) == ((size_t) (line_buf_size - 1))) { + printf("The line size in config file should be lower than %d bytes.\n", + MAX_LINE_SIZE); + exit(1); + } + + return OK; +} + +static int is_valid_entry(char *oneline, regmatch_t *match) +{ + int retval; + + if (regexec(&entries_line_expr, oneline, 3, match, 0) == 0) { + oneline[match[1].rm_eo] = '\0'; + oneline[match[2].rm_eo] = '\0'; + retval = 1; + } else + retval = 0; + + return retval; +} + +static int skip_comment_blank_line(char *oneline) +{ + int retval; + + if (regexec(&blank_or_comment_expr, oneline, 0, NULL, 0) == 0) { + /* skip comment and blank */ + retval = 1; + } else { + /* no match */ + retval = 0; + } + + return retval; +} + +#define N_MATCHES 4 +/* + return value: + 0: The config file can not be parsed correctly. + 1: The config file can be parsed correctly. + */ +uint8_t process_config(FILE *config, amd_cb_config *cb_config, uint8_t print_deps) +{ + char oneline[MAX_LINE_SIZE], *path_filename; + regmatch_t match[N_MATCHES]; + char dir[MAX_LINE_SIZE] = {'\0'}; + + compile_reg_expr(REG_EXTENDED | REG_NEWLINE, + blank_or_comment_regex, &blank_or_comment_expr); + compile_reg_expr(REG_EXTENDED | REG_NEWLINE, + entries_line_regex, &entries_line_expr); + + /* Get a line */ + /* Get FIRMWARE_LOCATE in the first loop */ + while (get_input_file_line(config, oneline, MAX_LINE_SIZE) == OK) { + /* get a line */ + if (skip_comment_blank_line(oneline)) + continue; + if (is_valid_entry(oneline, match)) { + if (strcmp(&(oneline[match[1].rm_so]), "FIRMWARE_LOCATE") == 0) { + strcpy(dir, &(oneline[match[2].rm_so])); + break; + } + } + } + + if (dir[0] == '\0') { + fprintf(stderr, "No line with FIRMWARE_LOCATION\n"); + return 0; + } + + fseek(config, 0, SEEK_SET); + /* Get a line */ + while (get_input_file_line(config, oneline, MAX_LINE_SIZE) == OK) { + /* get a line */ + if (skip_comment_blank_line(oneline)) + continue; + if (is_valid_entry(oneline, match)) { + if (strcmp(&(oneline[match[1].rm_so]), "FIRMWARE_LOCATE") == 0) { + continue; + } else { + path_filename = malloc(MAX_LINE_SIZE); + strcpy(path_filename, dir); + strcat(path_filename, "/"); + strcat(path_filename, &(oneline[match[2].rm_so])); + + if (find_register_fw_filename_psp_dir( + &(oneline[match[1].rm_so]), + path_filename, cb_config) == 0) { + if (find_register_fw_filename_bios_dir( + &(oneline[match[1].rm_so]), + path_filename, cb_config) == 0) { + fprintf(stderr, "Module's name \"%s\" is not valid\n", oneline); + return 0; /* Stop parsing. */ + } else { + if (print_deps) + printf(" %s ", path_filename); + } + } else { + if (print_deps) + printf(" %s ", path_filename); + } + } + } else { + fprintf(stderr, "AMDFWTOOL config file line can't be parsed \"%s\"\n", oneline); + return 0; + } + } + return 1; +} diff --git a/util/archive/.gitignore b/util/archive/.gitignore new file mode 100644 index 0000000000..f1d43c6419 --- /dev/null +++ b/util/archive/.gitignore @@ -0,0 +1 @@ +archive diff --git a/util/autoport/.gitignore b/util/autoport/.gitignore new file mode 100644 index 0000000000..0069f999f6 --- /dev/null +++ b/util/autoport/.gitignore @@ -0,0 +1 @@ +autoport diff --git a/util/bincfg/.gitignore b/util/bincfg/.gitignore new file mode 100644 index 0000000000..20a7c5940c --- /dev/null +++ b/util/bincfg/.gitignore @@ -0,0 +1 @@ +bincfg diff --git a/util/board_status/.gitignore b/util/board_status/.gitignore new file mode 100644 index 0000000000..44847a9d5a --- /dev/null +++ b/util/board_status/.gitignore @@ -0,0 +1 @@ +board-status diff --git a/util/bucts/.gitignore b/util/bucts/.gitignore new file mode 100644 index 0000000000..f207389909 --- /dev/null +++ b/util/bucts/.gitignore @@ -0,0 +1 @@ +bucts diff --git a/util/cbfstool/.gitignore b/util/cbfstool/.gitignore new file mode 100644 index 0000000000..560d7ea827 --- /dev/null +++ b/util/cbfstool/.gitignore @@ -0,0 +1,5 @@ +cbfs-compression-tool +cbfstool +fmaptool +ifwitool +rmodtool diff --git a/util/cbmem/.gitignore b/util/cbmem/.gitignore new file mode 100644 index 0000000000..5bc3336a1f --- /dev/null +++ b/util/cbmem/.gitignore @@ -0,0 +1 @@ +cbmem diff --git a/util/crossgcc/.gitignore b/util/crossgcc/.gitignore new file mode 100644 index 0000000000..0dfddd3b66 --- /dev/null +++ b/util/crossgcc/.gitignore @@ -0,0 +1,28 @@ +acpica-unix-*/ +binutils-*/ +build-*BINUTILS/ +build-*EXPAT/ +build-*GCC/ +build-*GDB/ +build-*GMP/ +build-*LIBELF/ +build-*MPC/ +build-*MPFR/ +build-*PYTHON/ +build-*LVM/ +build-*IASL/ +expat-*/ +gcc-*/ +gdb-*/ +gmp-*/ +libelf-*/ +mingwrt-*/ +mpc-*/ +mpfr-*/ +Python-*/ +*.src/ +tarballs/ +w32api-*/ +xgcc/ +xgcc-*/ +xgcc diff --git a/util/docker/coreboot-jenkins-node/Dockerfile b/util/docker/coreboot-jenkins-node/Dockerfile index 36b77d6398..9449c05bdd 100644 --- a/util/docker/coreboot-jenkins-node/Dockerfile +++ b/util/docker/coreboot-jenkins-node/Dockerfile @@ -20,6 +20,7 @@ USER root RUN apt-get -y update && \ apt-get -y install \ meson ninja-build \ + sdcc \ lua5.3 liblua5.3-dev default-jre-headless openssh-server && \ apt-get clean diff --git a/util/ectool/.gitignore b/util/ectool/.gitignore new file mode 100644 index 0000000000..4ceecac5ab --- /dev/null +++ b/util/ectool/.gitignore @@ -0,0 +1 @@ +ectool diff --git a/util/futility/.gitignore b/util/futility/.gitignore new file mode 100644 index 0000000000..1a1d4ab072 --- /dev/null +++ b/util/futility/.gitignore @@ -0,0 +1 @@ +futility diff --git a/util/genprof/.gitignore b/util/genprof/.gitignore new file mode 100644 index 0000000000..612ef67372 --- /dev/null +++ b/util/genprof/.gitignore @@ -0,0 +1 @@ +genprof diff --git a/util/ifdtool/.gitignore b/util/ifdtool/.gitignore new file mode 100644 index 0000000000..ee8e831681 --- /dev/null +++ b/util/ifdtool/.gitignore @@ -0,0 +1 @@ +ifdtool diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 220c140417..7dbed66df6 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -1266,6 +1266,25 @@ static void lock_descriptor(const char *filename, char *image, int size) write_image(filename, image, size); } +static void enable_cpu_read_me(const char *filename, char *image, int size) +{ + int rd_shift; + fmba_t *fmba = find_fmba(image, size); + + if (!fmba) + exit(EXIT_FAILURE); + + if (ifd_version >= IFD_VERSION_2) + rd_shift = FLMSTR_RD_SHIFT_V2; + else + rd_shift = FLMSTR_RD_SHIFT_V1; + + /* CPU/BIOS can read ME. */ + fmba->flmstr1 |= (1 << REGION_ME) << rd_shift; + + write_image(filename, image, size); +} + static void unlock_descriptor(const char *filename, char *image, int size) { fmba_t *fmba = find_fmba(image, size); @@ -1626,6 +1645,7 @@ static void print_usage(const char *name) " -e | --em100 set SPI frequency to 20MHz and disable\n" " Dual Output Fast Read Support\n" " -l | --lock Lock firmware descriptor and ME region\n" + " -r | --read Enable CPU/BIOS read access for ME region\n" " -u | --unlock Unlock firmware descriptor and ME region\n" " -M | --altmedisable <0|1> Set the MeDisable and AltMeDisable (or HAP for skylake or newer platform)\n" " bits to disable ME\n" @@ -1642,7 +1662,7 @@ static void print_usage(const char *name) " -V | --newvalue The new value to write into PCH strap specified by -S\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" - " is one of Descriptor, BIOS, ME, GbE, Platform\n" + " is one of Descriptor, BIOS, ME, GbE, Platform, res1, res2, res3\n" "\n"); } @@ -1652,7 +1672,7 @@ int main(int argc, char *argv[]) int mode_dump = 0, mode_extract = 0, mode_inject = 0, mode_spifreq = 0; int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0; int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0; - int mode_altmedisable = 0, altmedisable = 0; + int mode_read = 0, mode_altmedisable = 0, altmedisable = 0; char *region_type_string = NULL, *region_fname = NULL; const char *layout_fname = NULL; char *new_filename = NULL; @@ -1675,6 +1695,7 @@ int main(int argc, char *argv[]) {"altmedisable", 1, NULL, 'M'}, {"em100", 0, NULL, 'e'}, {"lock", 0, NULL, 'l'}, + {"read", 0, NULL, 'r'}, {"unlock", 0, NULL, 'u'}, {"version", 0, NULL, 'v'}, {"help", 0, NULL, 'h'}, @@ -1685,7 +1706,7 @@ int main(int argc, char *argv[]) {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "S:V:df:D:C:M:xi:n:O:s:p:eluvth?", + while ((opt = getopt_long(argc, argv, "S:V:df:D:C:M:xi:n:O:s:p:elruvth?", long_options, &option_index)) != EOF) { switch (opt) { case 'd': @@ -1732,6 +1753,12 @@ int main(int argc, char *argv[]) region_type = 3; else if (!strcasecmp("Platform", region_type_string)) region_type = 4; + else if (!strcasecmp("res1", region_type_string)) + region_type = 5; + else if (!strcasecmp("res2", region_type_string)) + region_type = 6; + else if (!strcasecmp("res3", region_type_string)) + region_type = 7; else if (!strcasecmp("EC", region_type_string)) region_type = 8; if (region_type == -1) { @@ -1853,6 +1880,9 @@ int main(int argc, char *argv[]) exit(EXIT_FAILURE); } break; + case 'r': + mode_read = 1; + break; case 'u': mode_unlocked = 1; if (mode_locked == 1) { @@ -1994,6 +2024,9 @@ int main(int argc, char *argv[]) if (mode_locked) lock_descriptor(new_filename, image, size); + if (mode_read) + enable_cpu_read_me(new_filename, image, size); + if (mode_unlocked) unlock_descriptor(new_filename, image, size); diff --git a/util/intelmetool/.gitignore b/util/intelmetool/.gitignore new file mode 100644 index 0000000000..ea65fca311 --- /dev/null +++ b/util/intelmetool/.gitignore @@ -0,0 +1 @@ +intelmetool diff --git a/util/intelp2m/.gitignore b/util/intelp2m/.gitignore new file mode 100644 index 0000000000..c973792029 --- /dev/null +++ b/util/intelp2m/.gitignore @@ -0,0 +1,2 @@ +intelp2m +generate/gpio.h diff --git a/util/inteltool/.gitignore b/util/inteltool/.gitignore new file mode 100644 index 0000000000..f2b363a194 --- /dev/null +++ b/util/inteltool/.gitignore @@ -0,0 +1 @@ +inteltool diff --git a/util/intelvbttool/.gitignore b/util/intelvbttool/.gitignore new file mode 100644 index 0000000000..61545cde99 --- /dev/null +++ b/util/intelvbttool/.gitignore @@ -0,0 +1 @@ +intelvbttool diff --git a/util/kbc1126/.gitignore b/util/kbc1126/.gitignore new file mode 100644 index 0000000000..862c2287d6 --- /dev/null +++ b/util/kbc1126/.gitignore @@ -0,0 +1,2 @@ +kbc1126_ec_dump +kbc1126_ec_insert diff --git a/util/msrtool/.gitignore b/util/msrtool/.gitignore new file mode 100644 index 0000000000..564b06c72f --- /dev/null +++ b/util/msrtool/.gitignore @@ -0,0 +1,3 @@ +msrtool +Makefile +Makefile.deps diff --git a/util/nvramtool/.gitignore b/util/nvramtool/.gitignore new file mode 100644 index 0000000000..fc4630ee9c --- /dev/null +++ b/util/nvramtool/.gitignore @@ -0,0 +1 @@ +nvramtool diff --git a/util/pmh7tool/.gitignore b/util/pmh7tool/.gitignore new file mode 100644 index 0000000000..2f9e8249cd --- /dev/null +++ b/util/pmh7tool/.gitignore @@ -0,0 +1 @@ +pmh7tool diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 4f13293a98..a7b2ce676e 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -4,8 +4,9 @@ #include #include #include -/* stat.h needs to be included before commonlib/helpers.h to avoid errors.*/ +#include #include +/* stat.h needs to be included before commonlib/helpers.h to avoid errors.*/ #include #include #include @@ -402,8 +403,8 @@ struct fw_config_field *new_fw_config_field(const char *name, { struct fw_config_field *field = find_fw_config_field(name); - /* Check that field is within 32bits. */ - if (start_bit > end_bit || end_bit > 31) { + /* Check that field is within 64 bits. */ + if (start_bit > end_bit || end_bit > 63) { printf("ERROR: fw_config field %s has invalid range %u-%u\n", name, start_bit, end_bit); exit(1); @@ -452,15 +453,16 @@ static void append_fw_config_option_to_field(struct fw_config_field *field, } } -void add_fw_config_option(struct fw_config_field *field, const char *name, unsigned int value) +void add_fw_config_option(struct fw_config_field *field, const char *name, uint64_t value) { struct fw_config_option *option; - uint32_t field_max_value; + uint64_t field_max_value; /* Check that option value fits within field mask. */ - field_max_value = (1 << (1 + field->end_bit - field->start_bit)) - 1; + field_max_value = (1ull << (1ull + field->end_bit - field->start_bit)) - 1ull; if (value > field_max_value) { - printf("ERROR: fw_config option %s:%s value %u larger than field max %u\n", + printf("ERROR: fw_config option %s:%s value %" PRIx64 " larger than field max %" + PRIx64 "\n", field->name, name, value, field_max_value); exit(1); } @@ -475,7 +477,7 @@ void add_fw_config_option(struct fw_config_field *field, const char *name, unsig } /* Compare values. */ if (value == option->value) { - printf("ERROR: fw_config option %s:%s[%u] redefined as %s\n", + printf("ERROR: fw_config option %s:%s[%" PRIx64 "] redefined as %s\n", field->name, option->name, value, name); exit(1); } @@ -532,23 +534,24 @@ static void emit_fw_config(FILE *fil) while (field) { struct fw_config_option *option = field->options; - uint32_t mask; + uint64_t mask; fprintf(fil, "#define FW_CONFIG_FIELD_%s_NAME \"%s\"\n", field->name, field->name); /* Compute mask from start and end bit. */ - mask = ((1 << (1 + field->end_bit - field->start_bit)) - 1); + mask = ((1ull << (1ull + field->end_bit - field->start_bit)) - 1ull); mask <<= field->start_bit; - fprintf(fil, "#define FW_CONFIG_FIELD_%s_MASK 0x%08x\n", + fprintf(fil, "#define FW_CONFIG_FIELD_%s_MASK 0x%" PRIx64 "\n", field->name, mask); while (option) { fprintf(fil, "#define FW_CONFIG_FIELD_%s_OPTION_%s_NAME \"%s\"\n", field->name, option->name, option->name); - fprintf(fil, "#define FW_CONFIG_FIELD_%s_OPTION_%s_VALUE 0x%08x\n", - field->name, option->name, option->value << field->start_bit); + fprintf(fil, "#define FW_CONFIG_FIELD_%s_OPTION_%s_VALUE 0x%" + PRIx64 "\n", field->name, option->name, + option->value << field->start_bit); option = option->next; } @@ -569,7 +572,7 @@ static int emit_fw_config_probe(FILE *fil, struct device *dev) /* Find matching field. */ struct fw_config_field *field; struct fw_config_option *option; - uint32_t mask, value; + uint64_t mask, value; field = find_fw_config_field(probe->field); if (!field) { diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index e2ff4c786b..0db1ce59c9 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -1,6 +1,7 @@ /* sconfig, coreboot device tree compiler */ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -31,7 +32,7 @@ struct pci_irq_info { struct fw_config_option; struct fw_config_option { const char *name; - unsigned int value; + uint64_t value; struct fw_config_option *next; }; struct fw_config_field; @@ -213,6 +214,6 @@ struct fw_config_field *new_fw_config_field(const char *name, unsigned int start_bit, unsigned int end_bit); void add_fw_config_option(struct fw_config_field *field, const char *name, - unsigned int value); + uint64_t value); void add_fw_config_probe(struct bus *bus, const char *field, const char *option); diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index cf71b02f3e..84dfe248fd 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -2,6 +2,7 @@ /* sconfig, coreboot device tree compiler */ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include "sconfig.h" int yylex(); @@ -16,7 +17,7 @@ static struct fw_config_field *cur_field; struct device *dev; struct chip_instance *chip_instance; char *string; - int number; + uint64_t number; } %token CHIP DEVICE REGISTER ALIAS REFERENCE ASSOCIATION BOOL STATUS MANDATORY BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESC IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO LPC ESPI FW_CONFIG_TABLE FW_CONFIG_FIELD FW_CONFIG_OPTION FW_CONFIG_PROBE @@ -116,7 +117,7 @@ fw_config_field: FW_CONFIG_FIELD STRING { /* option */ fw_config_option: FW_CONFIG_OPTION STRING NUMBER /* == field value */ - { add_fw_config_option(cur_field, $2, strtoul($3, NULL, 0)); }; + { add_fw_config_option(cur_field, $2, strtoull($3, NULL, 0)); }; /* probe