From 77f4b7fe0c0f1e0f09b1a69046b958c284cedeea Mon Sep 17 00:00:00 2001 From: Josie Nordrum Date: Thu, 22 Oct 2020 17:48:55 -0600 Subject: [PATCH 001/129] soc/amd/common/acpi: Create platform.asl to define acpi transitions Define device _WAK, _PTS, and _INI acpi methods with callbacks into mainboard methods if provided. BUG=b:158087989 BRANCH=Zork TEST=tested backlight during reboot and suspend Signed-off-by: Josie Nordrum Change-Id: I8020173a15db1d310459d5c1de3600949b173b00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46669 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/amd/common/acpi/platform.asl | 33 ++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 src/soc/amd/common/acpi/platform.asl diff --git a/src/soc/amd/common/acpi/platform.asl b/src/soc/amd/common/acpi/platform.asl new file mode 100644 index 0000000000..6db12e3d47 --- /dev/null +++ b/src/soc/amd/common/acpi/platform.asl @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Callback methods to be implemented by mainboard */ +External(\_SB.MPTS, MethodObj) +External(\_SB.MWAK, MethodObj) +External(\_SB.MINI, MethodObj) + +Scope (\_SB){ + /* Platform initialization methods */ + Method (_INI, 0, NotSerialized) + { + If (CondRefOf (\_SB.MINI)) { + \_SB.MINI() + } + } +} + +/* Platform-wide wake methods */ +Method (\_WAK, 1, NotSerialized) +{ + If (CondRefOf (\_SB.MWAK)) { + \_SB.MWAK() + } + Return (Package (){ 0, 0 }) +} + +/* Platform-wide Put To Sleep (suspend) methods */ +Method (\_PTS, 1, NotSerialized) +{ + If (CondRefOf (\_SB.MPTS)) { + \_SB.MPTS() + } +} From da4d9da51a14081172762ff42e406bd5c810a7ed Mon Sep 17 00:00:00 2001 From: Josie Nordrum Date: Thu, 22 Oct 2020 17:50:20 -0600 Subject: [PATCH 002/129] soc/amd/picasso/acpi: Include platform.asl Include platform.asl to link acpi methods for _INI, _WAK, and _PTS to correctly enable backlight in OS for zork. BUG=b:158087989 BRANCH=Zork TEST=check backlight during reboot and suspend Signed-off-by: Josie Nordrum Change-Id: I702f807a5907d85d083295cf339ba9d31b246627 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46670 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/amd/picasso/acpi/sb_pci0_fch.asl | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index f627a28039..cbb1b91782 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -22,6 +22,7 @@ Method(_OSC,4) /* 0:14.3 - LPC */ #include +#include Name(CRES, ResourceTemplate() { /* Set the Bus number and Secondary Bus number for the PCI0 device From 0310fe7bdc71d6a3a96ad8438b6089b77e838c70 Mon Sep 17 00:00:00 2001 From: Josie Nordrum Date: Thu, 22 Oct 2020 17:52:37 -0600 Subject: [PATCH 003/129] mb/google/zork: Generate acpi methods in mainboard.c Generate acpi methods which enable and disable backlight during _INI, _WAK, and _PTS. BUG=b:158087989 BRANCH=Zork TEST=check backlight during reboot and suspend Signed-off-by: Josie Nordrum Change-Id: I2f3434dc92de1f697693ff69ca15bd76647b89a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46671 Reviewed-by: Martin Roth Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/zork/mainboard.c | 53 +++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index f0d9a2869d..9503d3762c 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -28,6 +29,12 @@ #include #include +#define METHOD_BACKLIGHT_ENABLE "\\_SB.BKEN" +#define METHOD_BACKLIGHT_DISABLE "\\_SB.BKDS" +#define METHOD_MAINBOARD_INI "\\_SB.MINI" +#define METHOD_MAINBOARD_WAK "\\_SB.MWAK" +#define METHOD_MAINBOARD_PTS "\\_SB.MPTS" + /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. * This table is responsible for physically routing the PIC and @@ -175,6 +182,50 @@ void mainboard_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, variant_get_dxio_ddi_descriptors(dxio_descs, dxio_num, ddi_descs, ddi_num); } +static void mainboard_write_blken(void) +{ + acpigen_write_method(METHOD_BACKLIGHT_ENABLE, 0); + acpigen_soc_clear_tx_gpio(GPIO_85); + acpigen_pop_len(); +} + +static void mainboard_write_blkdis(void) +{ + acpigen_write_method(METHOD_BACKLIGHT_DISABLE, 0); + acpigen_soc_set_tx_gpio(GPIO_85); + acpigen_pop_len(); +} + +static void mainboard_write_mini(void) +{ + acpigen_write_method(METHOD_MAINBOARD_INI, 0); + acpigen_emit_namestring(METHOD_BACKLIGHT_ENABLE); + acpigen_pop_len(); +} + +static void mainboard_write_mwak(void) +{ + acpigen_write_method(METHOD_MAINBOARD_WAK, 0); + acpigen_emit_namestring(METHOD_BACKLIGHT_ENABLE); + acpigen_pop_len(); +} + +static void mainboard_write_mpts(void) +{ + acpigen_write_method(METHOD_MAINBOARD_PTS, 0); + acpigen_emit_namestring(METHOD_BACKLIGHT_DISABLE); + acpigen_pop_len(); +} + +static void mainboard_fill_ssdt(const struct device *dev) +{ + mainboard_write_blken(); + mainboard_write_blkdis(); + mainboard_write_mini(); + mainboard_write_mpts(); + mainboard_write_mwak(); +} + /************************************************* * Dedicated mainboard function *************************************************/ @@ -186,6 +237,8 @@ static void zork_enable(struct device *dev) pirq_setup(); dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; + dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt; + } static void mainboard_final(void *chip_info) From 65d0ef7cbd42bd377079a0ec16eb0c21dbf3a0ff Mon Sep 17 00:00:00 2001 From: Josie Nordrum Date: Mon, 26 Oct 2020 11:39:23 -0600 Subject: [PATCH 004/129] mb/google/zork: Revert temp acpi backlight fix Remove code to turn on backlight during ACPI mode because backlight has been properly enabled in ACPI. BUG=b:158087989 BRANCH=Zork TEST=tested backlight during reboot and suspend Signed-off-by: Josie Nordrum Change-Id: I3bf06042aa19e4559127d611d401f0ba0516b3a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46823 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Furquan Shaikh --- src/mainboard/google/zork/smihandler.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/mainboard/google/zork/smihandler.c b/src/mainboard/google/zork/smihandler.c index 6ef2704de1..1c26d45bca 100644 --- a/src/mainboard/google/zork/smihandler.c +++ b/src/mainboard/google/zork/smihandler.c @@ -34,10 +34,5 @@ int mainboard_smi_apmc(u8 apmc) chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); - /* Temporary fix - Needs to go into ACPI instead */ - /* Turn on the backlight when we go to ACPI mode */ - if (apmc == APM_CNT_ACPI_ENABLE) - gpio_set(GPIO_85, 0); - return 0; } From e4e08f2bfe24aaf320273b71d99fb4c6d675f64b Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 26 Oct 2020 10:15:42 -0700 Subject: [PATCH 005/129] ifdtool: add "reserved" regions This will let you at least dump / add these regions. Signed-off-by: Stefan Reinauer Change-Id: I195ba5e93823603e712cd16cecbb48141302bed6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46822 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- util/ifdtool/ifdtool.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 220c140417..93f6f3feca 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -1642,7 +1642,7 @@ static void print_usage(const char *name) " -V | --newvalue The new value to write into PCH strap specified by -S\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" - " is one of Descriptor, BIOS, ME, GbE, Platform\n" + " is one of Descriptor, BIOS, ME, GbE, Platform, res1, res2, res3\n" "\n"); } @@ -1732,6 +1732,12 @@ int main(int argc, char *argv[]) region_type = 3; else if (!strcasecmp("Platform", region_type_string)) region_type = 4; + else if (!strcasecmp("res1", region_type_string)) + region_type = 5; + else if (!strcasecmp("res2", region_type_string)) + region_type = 6; + else if (!strcasecmp("res3", region_type_string)) + region_type = 7; else if (!strcasecmp("EC", region_type_string)) region_type = 8; if (region_type == -1) { From 72e49cef806467a16d4d57858ad38b092c0a61ad Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sun, 27 Sep 2020 15:38:44 +0300 Subject: [PATCH 006/129] mb/ocp/tiogapass/dsdt: Remove unnecessary comments Change-Id: I6a16e2f829219f2eba8acd3ae7f371238c0d8de1 Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/45767 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/mainboard/ocp/tiogapass/dsdt.asl | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index d5b7b42b13..ddc716093f 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -11,12 +11,8 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - // platform ACPI tables #include "acpi/platform.asl" - - // global NVS and variables #include - #include #include } From 310c7637daba6ba4e9249928e5cd0e45ef4661e1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 1 Oct 2020 22:28:03 +0200 Subject: [PATCH 007/129] soc/intel: deduplicate ACPI timer emulation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The code for enabling ACPI timer emulation is the same for the SoCs SKL, CNL, ICL, TGL, JSL and EHL. Deduplicate it by moving it to common code. APL differs in not having the delay settings. However, the bits are marked as "spare" and BWG mentions there are no "reserved bit checks done". Thus, we can write them unconditionally without any effect. Note: The ACPI timer emulation can only be used by SoCs with microcode supporting CTC (Common Timer Copy) / ACPI timer emulation. Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/45951 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/alderlake/cpu.c | 21 --------------- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/include/soc/pm.h | 2 -- src/soc/intel/apollolake/pmutil.c | 18 ------------- src/soc/intel/cannonlake/cpu.c | 25 ------------------ src/soc/intel/common/block/cpu/Makefile.inc | 1 + .../common/block/cpu/pm_timer_emulation.c | 26 +++++++++++++++++++ .../common/block/include/intelblocks/cpulib.h | 6 +++++ src/soc/intel/elkhartlake/cpu.c | 21 --------------- src/soc/intel/icelake/cpu.c | 21 --------------- src/soc/intel/jasperlake/cpu.c | 21 --------------- src/soc/intel/skylake/cpu.c | 24 ----------------- src/soc/intel/tigerlake/cpu.c | 21 --------------- 13 files changed, 34 insertions(+), 174 deletions(-) create mode 100644 src/soc/intel/common/block/cpu/pm_timer_emulation.c diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 39a42651bd..9fab277781 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -23,7 +23,6 @@ #include #include #include -#include #include static void soc_fsp_load(void) @@ -62,25 +61,6 @@ static void configure_misc(void) wrmsr(MSR_POWER_CTL, msr); } -static void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { @@ -97,7 +77,6 @@ void soc_core_init(struct device *cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); /* Enable Direct Cache Access */ diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 79fab1a9d1..64889e56f9 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -10,6 +10,7 @@ subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c +bootblock-y += ../common/block/cpu/pm_timer_emulation.c bootblock-$(CONFIG_FSP_CAR) += fspcar.c bootblock-y += car.c bootblock-y += heci.c diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index aaf62583e6..748f76adba 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -234,8 +234,6 @@ struct chipset_power_state { void pch_log_state(void); -void enable_pm_timer_emulation(void); - /* STM Support */ uint16_t get_pmbase(void); diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index e0de93eae4..6e96b57a07 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -178,24 +178,6 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps, return prev_sleep_state; } -void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + R_ACPI_PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - static int rtc_failed(uint32_t gen_pmcon1) { return !!(gen_pmcon1 & RPS); diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 20da942f84..61b19894eb 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -58,29 +57,6 @@ static void configure_misc(void) wrmsr(MSR_POWER_CTL, msr); } -/* - * The emulated ACPI timer allows replacing of the ACPI timer - * (PM1_TMR) to have no impart on the system. - */ -static void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - static void configure_c_states(void) { msr_t msr; @@ -135,7 +111,6 @@ void soc_core_init(struct device *cpu) set_aesni_lock(); - /* Enable ACPI Timer Emulation via MSR 0x121 */ enable_pm_timer_emulation(); /* Enable Direct Cache Access */ diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc index deddb67a16..7692076375 100644 --- a/src/soc/intel/common/block/cpu/Makefile.inc +++ b/src/soc/intel/common/block/cpu/Makefile.inc @@ -11,3 +11,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) += mp_init.c +ramstage-$(CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION) += pm_timer_emulation.c diff --git a/src/soc/intel/common/block/cpu/pm_timer_emulation.c b/src/soc/intel/common/block/cpu/pm_timer_emulation.c new file mode 100644 index 0000000000..8f56da54c5 --- /dev/null +++ b/src/soc/intel/common/block/cpu/pm_timer_emulation.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +void enable_pm_timer_emulation(void) +{ + msr_t msr; + + if (!CONFIG_CPU_XTAL_HZ) + return; + + /* + * The derived frequency is calculated as follows: + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. + */ + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; + /* Set PM1 timer IO port and enable */ + msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | + EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); + wrmsr(MSR_EMULATE_PM_TIMER, msr); +} diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index d2b00efb2f..4dfbef48f6 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -156,4 +156,10 @@ void cpu_lt_lock_memory(void *unused); /* Get a supported PRMRR size in bytes with respect to users choice */ int get_valid_prmrr_size(void); +/* + * Enable the emulated ACPI timer in case it's not available or to allow + * disabling the PM ACPI timer (PM1_TMR) for power saving. + */ +void enable_pm_timer_emulation(void); + #endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */ diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index 720a295e15..d0fa019ef8 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -17,7 +17,6 @@ #include #include #include -#include #include static void soc_fsp_load(void) @@ -56,25 +55,6 @@ static void configure_misc(void) wrmsr(MSR_POWER_CTL, msr); } -static void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { @@ -91,7 +71,6 @@ void soc_core_init(struct device *cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); /* Enable Direct Cache Access */ diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index ea2b3574b2..1734ba6c30 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -17,7 +17,6 @@ #include #include #include -#include #include static void soc_fsp_load(void) @@ -56,25 +55,6 @@ static void configure_misc(void) wrmsr(MSR_POWER_CTL, msr); } -static void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - static void configure_c_states(void) { msr_t msr; @@ -127,7 +107,6 @@ void soc_core_init(struct device *cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); /* Enable Direct Cache Access */ diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index 312fc7d7af..6518945d8d 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -17,7 +17,6 @@ #include #include #include -#include #include static void soc_fsp_load(void) @@ -56,25 +55,6 @@ static void configure_misc(void) wrmsr(MSR_POWER_CTL, msr); } -static void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { @@ -91,7 +71,6 @@ void soc_core_init(struct device *cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); /* Enable Direct Cache Access */ diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 1682503d4b..6872c12101 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include @@ -96,29 +95,6 @@ static void configure_c_states(void) wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } -/* - * The emulated ACPI timer allows disabling of the ACPI timer - * (PM1_TMR) to have no impart on the system. - */ -static void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index d7234e7191..36dfa1b738 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -23,7 +23,6 @@ #include #include #include -#include #include static void soc_fsp_load(void) @@ -62,25 +61,6 @@ static void configure_misc(void) wrmsr(MSR_POWER_CTL, msr); } -static void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { @@ -97,7 +77,6 @@ void soc_core_init(struct device *cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); /* Enable Direct Cache Access */ From e50f546e01994eed34e618d00ce0ab08af2d5a9e Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Tue, 27 Oct 2020 19:55:45 +0100 Subject: [PATCH 008/129] payloads/filo: Set stable tag to something that builds Also rename the prompt to "tested" to make it more obvious that there is no really stable version. Change-Id: Ib719fe5c30783a53ddad2a2dc2d9ecda37a05ac2 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/46849 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Reviewed-by: Felix Singer --- payloads/external/FILO/Kconfig | 4 ++-- payloads/external/FILO/Makefile | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/payloads/external/FILO/Kconfig b/payloads/external/FILO/Kconfig index 94d5e18df0..1cf171d2cf 100644 --- a/payloads/external/FILO/Kconfig +++ b/payloads/external/FILO/Kconfig @@ -5,9 +5,9 @@ choice default FILO_STABLE config FILO_STABLE - bool "0.6.0" + bool "tested" help - Stable FILO version + Tested FILO version config FILO_MASTER bool "HEAD" diff --git a/payloads/external/FILO/Makefile b/payloads/external/FILO/Makefile index a89ea2af59..6175cfe62c 100644 --- a/payloads/external/FILO/Makefile +++ b/payloads/external/FILO/Makefile @@ -1,6 +1,6 @@ TAG-$(CONFIG_FILO_MASTER)=origin/master NAME-$(CONFIG_FILO_MASTER)=MASTER -TAG-$(CONFIG_FILO_STABLE)=22baa6bde9339029edfafa421b3d4a7be159edad +TAG-$(CONFIG_FILO_STABLE)=c2fa1ea6125c63e84cdf7779c37d76da8c5bc412 NAME-$(CONFIG_FILO_STABLE)=STABLE project_git_repo=https://review.coreboot.org/filo.git From 025846537331783e01d8e9ea58727fd43a8f8ba6 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 4 Oct 2020 15:03:09 +0200 Subject: [PATCH 009/129] mb/asus/f2a85-m_pro: Enable GPIO0 on the super I/O It is enabled by the vendor firmware. Also drop spurious `io 0x60 = 0x00` setting. It's the default anyway and the resource is kept disabled (it's controlled by the virtual LDN 2e.008). This fixes the hang in `PCI: 00:14.3 init` when doing `outb(0, DMA1_RESET_REG)`. Fixes: 2f8192bc ("asus/f2a85m_pro: Fix superio type in devicetree") Change-Id: I351c93033bf2afd824eb6baa8d7625e7a33a295a Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/46015 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index 3f9135c76d..aa213215cc 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -61,8 +61,9 @@ chip northbridge/amd/agesa/family15tn/root_complex irq 0xf7 = 0x00 irq 0xf8 = 0x00 end - device pnp 2e.8 off # WDT1, GPIO0, GPIO1 - io 0x60 = 0x00 + device pnp 2e.008 off # WDT1 + end + device pnp 2e.108 on # GPIO0, GPIO1 irq 0xe0 = 0xff irq 0xe1 = 0xff irq 0xe2 = 0xff From 0082a3e59e30aa4a92146dad05c58553cd4ee197 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 4 Oct 2020 16:11:18 +0200 Subject: [PATCH 010/129] mb/asus/f2a85-m_pro: Comment and group super-I/O GPIO settings Change-Id: I8f5a87d006f8bf20af40f7a4f09b1e4b597ba79f Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/46019 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- .../asus/f2a85-m/devicetree_f2a85-m_pro.cb | 102 +++++++++--------- 1 file changed, 53 insertions(+), 49 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index aa213215cc..aa2d52e567 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -45,71 +45,75 @@ chip northbridge/amd/agesa/family15tn/root_complex end device pnp 2e.6 off end # CIR device pnp 2e.7 on # GPIO6, GPIO7, GPIO8 - irq 0xe0 = 0x7f - irq 0xe1 = 0x10 - irq 0xe2 = 0x00 - irq 0xe3 = 0x00 - irq 0xe4 = 0xff - irq 0xe5 = 0xff - irq 0xe6 = 0xff - irq 0xe7 = 0xff - irq 0xec = 0x00 - irq 0xed = 0xff - irq 0xf4 = 0xff - irq 0xf5 = 0xff - irq 0xf6 = 0x00 - irq 0xf7 = 0x00 - irq 0xf8 = 0x00 + irq 0xf4 = 0xff # GPIO6 i/o + irq 0xf5 = 0xff # GPIO6 data + irq 0xf6 = 0x00 # GPIO6 inversion + irq 0xf7 = 0x00 # GPIO6 status + irq 0xf8 = 0x00 # GPIO6 multiplex + + irq 0xe0 = 0x7f # GPIO7 i/o + irq 0xe1 = 0x10 # GPIO7 data + irq 0xe2 = 0x00 # GPIO7 inversion + irq 0xe3 = 0x00 # GPIO7 status + irq 0xec = 0x00 # GPIO7 multiplex + + irq 0xe4 = 0xff # GPIO8 i/o + irq 0xe5 = 0xff # GPIO8 data + irq 0xe6 = 0xff # GPIO8 inversion + irq 0xe7 = 0xff # GPIO8 status + irq 0xed = 0xff # GPIO8 multiplex end device pnp 2e.008 off # WDT1 end device pnp 2e.108 on # GPIO0, GPIO1 - irq 0xe0 = 0xff - irq 0xe1 = 0xff - irq 0xe2 = 0xff - irq 0xe3 = 0xff - irq 0xe4 = 0xff - irq 0xf0 = 0xff - irq 0xf1 = 0x28 - irq 0xf2 = 0x00 - irq 0xf3 = 0x00 - irq 0xf4 = 0x08 - irq 0xf5 = 0xff - irq 0xf6 = 0x00 - irq 0xf7 = 0xff + irq 0xe0 = 0xff # GPIO0 i/o + irq 0xe1 = 0xff # GPIO0 data + irq 0xe2 = 0xff # GPIO0 inversion + irq 0xe3 = 0xff # GPIO0 status + irq 0xe4 = 0xff # GPIO0 multiplex + + irq 0xf0 = 0xff # GPIO1 i/o + irq 0xf1 = 0x28 # GPIO1 data + irq 0xf2 = 0x00 # GPIO1 inversion + irq 0xf3 = 0x00 # GPIO1 status + irq 0xf4 = 0x08 # GPIO1 multiplex + + irq 0xf5 = 0xff # WDT1 control mode + irq 0xf6 = 0x00 # WDT1 counter + irq 0xf7 = 0xff # WDT1 control / status end device pnp 2e.009 off # GPIO8 end device pnp 2e.109 on # GPIO1 end device pnp 2e.209 on # GPIO2 - irq 0xe0 = 0xff - irq 0xe1 = 0x90 - irq 0xe2 = 0x00 - irq 0xe3 = 0x00 - irq 0xe9 = 0x00 + irq 0xe0 = 0xff # GPIO2 i/o + irq 0xe1 = 0x90 # GPIO2 data + irq 0xe2 = 0x00 # GPIO2 inversion + irq 0xe3 = 0x00 # GPIO2 status + irq 0xe9 = 0x00 # GPIO2 multiplex end device pnp 2e.309 on # GPIO3 - irq 0xe4 = 0x7f - irq 0xe5 = 0x76 - irq 0xe6 = 0x00 - irq 0xe7 = 0x00 - irq 0xea = 0x00 - irq 0xfe = 0x00 + irq 0xe4 = 0x7f # GPIO3 i/o + irq 0xe5 = 0x76 # GPIO3 data + irq 0xe6 = 0x00 # GPIO3 inversion + irq 0xe7 = 0x00 # GPIO3 status + irq 0xea = 0x00 # GPIO3 multiplex + irq 0xfe = 0x00 # GPIO3/4 debounce end device pnp 2e.409 on # GPIO4 - irq 0xe8 = 0x00 - irq 0xf0 = 0xff - irq 0xf1 = 0x7b - irq 0xf2 = 0x00 - irq 0xee = 0x00 + irq 0xf0 = 0xff # GPIO4 i/o + irq 0xf1 = 0x7b # GPIO4 data + irq 0xf2 = 0x00 # GPIO4 inversion + irq 0xe8 = 0x00 # GPIO4 status + irq 0xee = 0x00 # GPIO4 multiplex end device pnp 2e.509 on # GPIO5 - irq 0xeb = 0x00 - irq 0xf4 = 0xff - irq 0xf5 = 0xef - irq 0xf6 = 0x00 - irq 0xf7 = 0x00 + irq 0xf4 = 0xff # GPIO5 i/o + irq 0xf5 = 0xef # GPIO5 data + irq 0xf6 = 0x00 # GPIO5 inversion + irq 0xf7 = 0x00 # GPIO5 status + irq 0xeb = 0x00 # GPIO5 multiplex end device pnp 2e.609 on # GPIO6 end From 394bd94e0cc15ee238bc7e8088257904f12a06ef Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 4 Oct 2020 16:19:57 +0200 Subject: [PATCH 011/129] mb/asus/f2a85-m_pro: Clean up super-I/O GPIO settings Drop useless writes to read-only registers and don't re-write default 0x00 values. In detail: * Don't write read-only status registers. * Don't try to write input bits in data registers (iow. mask data values: `data &= ~io`). * Don't write data registers if all GPIOs are set as inputs (`io == 0xff`). * Don't write default 0x00 for inversion and multiplex registers. Note: Both GPIO0 and WDT1 values look spurious. Maybe they were dumped with the virtual devices disabled? Change-Id: I7d948d6b697285e61e4352b7354b924dbf511e9a Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/46020 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- .../asus/f2a85-m/devicetree_f2a85-m_pro.cb | 38 +------------------ 1 file changed, 2 insertions(+), 36 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index aa2d52e567..654716b2b2 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -46,36 +46,18 @@ chip northbridge/amd/agesa/family15tn/root_complex device pnp 2e.6 off end # CIR device pnp 2e.7 on # GPIO6, GPIO7, GPIO8 irq 0xf4 = 0xff # GPIO6 i/o - irq 0xf5 = 0xff # GPIO6 data - irq 0xf6 = 0x00 # GPIO6 inversion - irq 0xf7 = 0x00 # GPIO6 status - irq 0xf8 = 0x00 # GPIO6 multiplex irq 0xe0 = 0x7f # GPIO7 i/o - irq 0xe1 = 0x10 # GPIO7 data - irq 0xe2 = 0x00 # GPIO7 inversion - irq 0xe3 = 0x00 # GPIO7 status - irq 0xec = 0x00 # GPIO7 multiplex - - irq 0xe4 = 0xff # GPIO8 i/o - irq 0xe5 = 0xff # GPIO8 data - irq 0xe6 = 0xff # GPIO8 inversion - irq 0xe7 = 0xff # GPIO8 status - irq 0xed = 0xff # GPIO8 multiplex + irq 0xe1 = 0x00 # GPIO7 data end device pnp 2e.008 off # WDT1 end device pnp 2e.108 on # GPIO0, GPIO1 irq 0xe0 = 0xff # GPIO0 i/o - irq 0xe1 = 0xff # GPIO0 data irq 0xe2 = 0xff # GPIO0 inversion - irq 0xe3 = 0xff # GPIO0 status irq 0xe4 = 0xff # GPIO0 multiplex irq 0xf0 = 0xff # GPIO1 i/o - irq 0xf1 = 0x28 # GPIO1 data - irq 0xf2 = 0x00 # GPIO1 inversion - irq 0xf3 = 0x00 # GPIO1 status irq 0xf4 = 0x08 # GPIO1 multiplex irq 0xf5 = 0xff # WDT1 control mode @@ -88,32 +70,16 @@ chip northbridge/amd/agesa/family15tn/root_complex end device pnp 2e.209 on # GPIO2 irq 0xe0 = 0xff # GPIO2 i/o - irq 0xe1 = 0x90 # GPIO2 data - irq 0xe2 = 0x00 # GPIO2 inversion - irq 0xe3 = 0x00 # GPIO2 status - irq 0xe9 = 0x00 # GPIO2 multiplex end device pnp 2e.309 on # GPIO3 irq 0xe4 = 0x7f # GPIO3 i/o - irq 0xe5 = 0x76 # GPIO3 data - irq 0xe6 = 0x00 # GPIO3 inversion - irq 0xe7 = 0x00 # GPIO3 status - irq 0xea = 0x00 # GPIO3 multiplex - irq 0xfe = 0x00 # GPIO3/4 debounce + irq 0xe5 = 0x00 # GPIO3 data end device pnp 2e.409 on # GPIO4 irq 0xf0 = 0xff # GPIO4 i/o - irq 0xf1 = 0x7b # GPIO4 data - irq 0xf2 = 0x00 # GPIO4 inversion - irq 0xe8 = 0x00 # GPIO4 status - irq 0xee = 0x00 # GPIO4 multiplex end device pnp 2e.509 on # GPIO5 irq 0xf4 = 0xff # GPIO5 i/o - irq 0xf5 = 0xef # GPIO5 data - irq 0xf6 = 0x00 # GPIO5 inversion - irq 0xf7 = 0x00 # GPIO5 status - irq 0xeb = 0x00 # GPIO5 multiplex end device pnp 2e.609 on # GPIO6 end From 3ff948651a3ff848f761e55f14a3011502f63dbd Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 4 Oct 2020 16:34:10 +0200 Subject: [PATCH 012/129] mb/asus/f2a85-m_pro: Enable super-I/O LDNs 0x0f and 0x14 The LDNs don't have a 0x30 register to enable them. However, with the devices set to `off`, coreboot won't configure them. Change-Id: Iaea37c88524904a1dae8a6d3b5f07c6ea25bc3b2 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/46021 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index 654716b2b2..4e124f28e3 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -97,10 +97,10 @@ chip northbridge/amd/agesa/family15tn/root_complex end device pnp 2e.d off end # WDT1 device pnp 2e.e off end # CIR WAKE-UP - device pnp 2e.f off # GPIO Push-pull/Open-drain selection + device pnp 2e.f on # GPIO Push-pull/Open-drain selection irq 0xe6 = 7f end - device pnp 2e.14 off # PORT80 UART + device pnp 2e.14 on # PORT80 UART irq 0xe0 = 0x00 end device pnp 2e.16 off end # Deep Sleep From 68e597d81e41bb2d93558e4a4da26f0892f34d86 Mon Sep 17 00:00:00 2001 From: Huayang Duan Date: Mon, 22 Jun 2020 19:59:40 +0800 Subject: [PATCH 013/129] soc/mediatek/mt8192: Do dram full calibration If no correct params were found in flash, do dram full calibration. Full calibration will load blob, dram.elf. Blob version: v3, size: 320KB. Signed-off-by: Huayang Duan Change-Id: I2d4437a4e4c770de084927018d4dd3f2e8b87fb1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44570 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/mt8192/Makefile.inc | 10 ++++ src/soc/mediatek/mt8192/memory.c | 82 +++++++++++++++++++++++++--- 2 files changed, 84 insertions(+), 8 deletions(-) diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 8b2831cc6b..13b5b21763 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -37,6 +37,16 @@ ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c usb.c +MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192 + +DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram +$(DRAM_CBFS)-file := $(MT8192_BLOB_DIR)/dram.elf +$(DRAM_CBFS)-type := stage +$(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +ifneq ($(wildcard $($(DRAM_CBFS)-file)),) + cbfs-files-y += $(DRAM_CBFS) +endif + BL31_MAKEARGS += PLAT=mt8192 CPPFLAGS_common += -Isrc/soc/mediatek/mt8192/include diff --git a/src/soc/mediatek/mt8192/memory.c b/src/soc/mediatek/mt8192/memory.c index 5820fbf294..549dede00d 100644 --- a/src/soc/mediatek/mt8192/memory.c +++ b/src/soc/mediatek/mt8192/memory.c @@ -7,6 +7,7 @@ #include #include #include +#include static int mt_mem_test(const struct dramc_data *dparam) { @@ -41,7 +42,7 @@ static u32 compute_checksum(const struct dramc_param *dparam) static int dram_run_fast_calibration(const struct dramc_param *dparam) { if (!is_valid_dramc_param(dparam)) { - printk(BIOS_WARNING, "Invalid DRAM calibration data from flash\n"); + printk(BIOS_WARNING, "DRAM-K: Invalid DRAM calibration data from flash\n"); dump_param_header((void *)dparam); return -1; } @@ -49,7 +50,7 @@ static int dram_run_fast_calibration(const struct dramc_param *dparam) const u32 checksum = compute_checksum(dparam); if (dparam->header.checksum != checksum) { printk(BIOS_ERR, - "Invalid DRAM calibration checksum from flash " + "DRAM-K: Invalid DRAM calibration checksum from flash " "(expected: %#x, saved: %#x)\n", checksum, dparam->header.checksum); return DRAMC_ERR_INVALID_CHECKSUM; @@ -58,13 +59,13 @@ static int dram_run_fast_calibration(const struct dramc_param *dparam) const u16 config = CONFIG(MT8192_DRAM_DVFS) ? DRAMC_ENABLE_DVFS : DRAMC_DISABLE_DVFS; if (dparam->dramc_datas.ddr_info.config_dvfs != config) { printk(BIOS_WARNING, - "Incompatible config for calibration data from flash " + "DRAM-K: Incompatible config for calibration data from flash " "(expected: %#x, saved: %#x)\n", config, dparam->dramc_datas.ddr_info.config_dvfs); return -1; } - printk(BIOS_INFO, "DRAM calibration data valid pass\n"); + printk(BIOS_INFO, "DRAM-K: DRAM calibration data valid pass\n"); mt_set_emi(&dparam->dramc_datas); if (mt_mem_test(&dparam->dramc_datas) == 0) return 0; @@ -72,6 +73,43 @@ static int dram_run_fast_calibration(const struct dramc_param *dparam) return DRAMC_ERR_FAST_CALIBRATION; } +static int dram_run_full_calibration(struct dramc_param *dparam) +{ + /* Load and run the provided blob for full-calibration if available */ + struct prog dram = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/dram"); + + initialize_dramc_param(dparam); + + if (prog_locate(&dram)) { + printk(BIOS_ERR, "DRAM-K: Locate program failed\n"); + return -1; + } + + if (cbfs_prog_stage_load(&dram)) { + printk(BIOS_ERR, "DRAM-K: CBFS load program failed\n"); + return -2; + } + + dparam->do_putc = do_putchar; + + prog_set_entry(&dram, prog_entry(&dram), dparam); + prog_run(&dram); + if (dparam->header.status != DRAMC_SUCCESS) { + printk(BIOS_ERR, "DRAM-K: Full calibration failed: status = %d\n", + dparam->header.status); + return -3; + } + + if (!(dparam->header.flags & DRAMC_FLAG_HAS_SAVED_DATA)) { + printk(BIOS_ERR, + "DRAM-K: Full calibration executed without saving parameters. " + "Please ensure the blob is built properly.\n"); + return -4; + } + + return 0; +} + static void mem_init_set_default_config(struct dramc_param *dparam, u32 ddr_geometry) { @@ -93,23 +131,51 @@ static void mem_init_set_default_config(struct dramc_param *dparam, static void mt_mem_init_run(struct dramc_param_ops *dparam_ops, u32 ddr_geometry) { struct dramc_param *dparam = dparam_ops->param; + struct stopwatch sw; + int ret; /* Load calibration params from flash and run fast calibration */ mem_init_set_default_config(dparam, ddr_geometry); if (dparam_ops->read_from_flash(dparam)) { printk(BIOS_INFO, "DRAM-K: Running fast calibration\n"); - if (dram_run_fast_calibration(dparam) != 0) { - printk(BIOS_ERR, "Failed to run fast calibration\n"); + stopwatch_init(&sw); + + ret = dram_run_fast_calibration(dparam); + if (ret != 0) { + printk(BIOS_ERR, "DRAM-K: Failed to run fast calibration " + "in %ld msecs, error: %d\n", + stopwatch_duration_msecs(&sw), ret); /* Erase flash data after fast calibration failed */ memset(dparam, 0xa5, sizeof(*dparam)); dparam_ops->write_to_flash(dparam); } else { - printk(BIOS_INFO, "Fast calibration passed\n"); + printk(BIOS_INFO, "DRAM-K: Fast calibration passed in %ld msecs\n", + stopwatch_duration_msecs(&sw)); return; } } else { - printk(BIOS_WARNING, "Failed to read calibration data from flash\n"); + printk(BIOS_WARNING, "DRAM-K: Failed to read calibration data from flash\n"); + } + + /* Run full calibration */ + printk(BIOS_INFO, "DRAM-K: Running full calibration\n"); + mem_init_set_default_config(dparam, ddr_geometry); + + stopwatch_init(&sw); + int err = dram_run_full_calibration(dparam); + if (err == 0) { + printk(BIOS_INFO, "DRAM-K: Full calibration passed in %ld msecs\n", + stopwatch_duration_msecs(&sw)); + + dparam->header.checksum = compute_checksum(dparam); + dparam_ops->write_to_flash(dparam); + printk(BIOS_DEBUG, "DRAM-K: Calibration params saved to flash: " + "version=%#x, size=%#x\n", + dparam->header.version, dparam->header.size); + } else { + printk(BIOS_ERR, "DRAM-K: Full calibration failed in %ld msecs\n", + stopwatch_duration_msecs(&sw)); } } From b544fe48af76e5aae7537d95b62191e1fed2bc45 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 28 Oct 2020 13:25:06 +0530 Subject: [PATCH 014/129] mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg' List of changes: 1. Split mem_cfg for DDR4 and LPDDR4 as per board_id 2. Move dq_pins_interleaved into board-specific memory configuration information TEST=Able to build and boot DDR4 and LPDDR4 ADLRVP SKUs. Change-Id: I6ef19209767c810426bba0c8bc48178bf2e2a110 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/46873 Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- .../intel/adlrvp/romstage_fsp_params.c | 2 -- .../intel/adlrvp/variants/adlrvp_p/memory.c | 33 ++++++++++++++----- src/soc/intel/alderlake/include/soc/meminit.h | 6 ++++ src/soc/intel/alderlake/meminit.c | 1 + 4 files changed, 31 insertions(+), 11 deletions(-) diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 9d7cc9118f..209ee6a222 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -51,12 +51,10 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) switch (board_id) { case ADL_P_DDR4_1: case ADL_P_DDR4_2: - mupd->FspmConfig.DqPinsInterleaved = 1; memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_spd_info, half_populated); break; case ADL_P_LP4_1: case ADL_P_LP4_2: - mupd->FspmConfig.DqPinsInterleaved = 0; memcfg_init(&mupd->FspmConfig, mem_config, &lpddr4_spd_info, half_populated); break; default: diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c index f8b366049f..c730b995bc 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c @@ -5,7 +5,21 @@ #include #include -static const struct mb_cfg mem_config = { +static const struct mb_cfg ddr4_mem_config = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + /* Baseboard Rcomp target values */ + .rcomp_targets = {40, 30, 33, 33, 30}, + + .dq_pins_interleaved = true, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + +static const struct mb_cfg lpddr4_mem_config = { /* DQ byte map */ .dq_map = { { 0, 2, 3, 1, 6, 7, 5, 4, /* Byte 0 */ @@ -33,13 +47,7 @@ static const struct mb_cfg mem_config = { { 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 } }, - /* Baseboard uses only 100ohm Rcomp resistors */ - .rcomp_resistor = {100, 100, 100}, - - /* - * Baseboard Rcomp target values. - */ - .rcomp_targets = {40, 30, 33, 33, 30}, + .dq_pins_interleaved = false, .ect = true, /* Early Command Training */ @@ -48,5 +56,12 @@ static const struct mb_cfg mem_config = { const struct mb_cfg *variant_memory_params(void) { - return &mem_config; + int board_id = get_board_id(); + + if (board_id == ADL_P_LP4_1 || board_id == ADL_P_LP4_2) + return &lpddr4_mem_config; + else if (board_id == ADL_P_DDR4_1 || board_id == ADL_P_DDR4_2) + return &ddr4_mem_config; + + die("unsupported board id : 0x%x\n", board_id); } diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h index 76930be0e7..5fed5680c6 100644 --- a/src/soc/intel/alderlake/include/soc/meminit.h +++ b/src/soc/intel/alderlake/include/soc/meminit.h @@ -76,6 +76,12 @@ struct mb_cfg { /* Rcomp target values. */ uint16_t rcomp_targets[5]; + /* + * Dqs Pins Interleaved Setting. Enable/Disable Control + * TRUE = enable, FALSE = disable + */ + bool dq_pins_interleaved; + /* * Early Command Training Enable/Disable Control * TRUE = enable, FALSE = disable diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index e7084a5a16..f5f747d79b 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -180,4 +180,5 @@ void memcfg_init(FSP_M_CONFIG *mem_cfg, mem_cfg->ECT = board_cfg->ect; mem_cfg->UserBd = board_cfg->UserBd; + mem_cfg->DqPinsInterleaved = board_cfg->dq_pins_interleaved; } From 5b5c52e8ded9e6ef320bc01fec63ed042cac90c1 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Mon, 12 Oct 2020 11:44:46 -0600 Subject: [PATCH 015/129] include/device/device.h: Move resource debug macros Add general debug macros that print resource information. These are available to select if DEFAULT_CONSOLE_LOGLEVEL_8. The macros are helpful in debugging complex resource allocation with multiple buses. The macros are moved from soc/intel/xeon_sp, where they were originally developed. Change-Id: I2bdab7770ca5ee5901f17a8af3a9a1001b6702e4 Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/46304 Tested-by: build bot (Jenkins) Reviewed-by: Jay Talbott Reviewed-by: Stefan Reinauer --- src/Kconfig | 9 +++++++++ src/include/device/device.h | 18 ++++++++++++++++++ src/soc/intel/xeon_sp/include/soc/util.h | 11 ----------- 3 files changed, 27 insertions(+), 11 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index d265da7797..eda11c331e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -915,6 +915,15 @@ config DEBUG_MALLOC If unsure, say N. +# Only visible if DEBUG_SPEW (8) is set. +config DEBUG_RESOURCES + bool "Output verbose PCI MEM and IO resource debug messages" if DEFAULT_CONSOLE_LOGLEVEL_8 + default n + help + This option enables additional PCI memory and IO debug messages. + Note: This option will increase the size of the coreboot image. + If unsure, say N. + config DEBUG_CONSOLE_INIT bool "Debug console initialisation code" default n diff --git a/src/include/device/device.h b/src/include/device/device.h index 3a0795e526..eb9ef42eef 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -261,6 +261,24 @@ void show_one_resource(int debug_level, struct device *dev, struct resource *resource, const char *comment); void show_all_devs_resources(int debug_level, const char *msg); +/* Debug macros */ +#if CONFIG(DEBUG_RESOURCES) +#include +#define LOG_MEM_RESOURCE(type, dev, index, base_kb, size_kb) \ + printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \ + "end: 0x%llx, size_kb: 0x%llx\n", \ + __func__, __LINE__, type, dev_path(dev), index, (base_kb << 10), \ + (base_kb << 10) + (size_kb << 10) - 1, size_kb) + +#define LOG_IO_RESOURCE(type, dev, index, base, size) \ + printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \ + "end: 0x%llx, size: 0x%llx\n", \ + __func__, __LINE__, type, dev_path(dev), index, base, base + size - 1, size) +#else /* DEBUG_RESOURCES*/ +#define LOG_MEM_RESOURCE(type, dev, index, base_kb, size_kb) +#define LOG_IO_RESOURCE(type, dev, index, base, size) +#endif /* DEBUG_RESOURCES*/ + /* Rounding for boundaries. * Due to some chip bugs, go ahead and round IO to 16 */ diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index 159efeba2c..f223efafe0 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -10,17 +10,6 @@ void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus void unlock_pam_regions(void); void get_stack_busnos(uint32_t *bus); -#define LOG_MEM_RESOURCE(type, dev, index, base_kb, size_kb) \ - printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \ - "end: 0x%llx, size_kb: 0x%llx\n", \ - __func__, __LINE__, type, dev_path(dev), index, (base_kb << 10), \ - (base_kb << 10) + (size_kb << 10) - 1, size_kb) - -#define LOG_IO_RESOURCE(type, dev, index, base, size) \ - printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \ - "end: 0x%llx, size: 0x%llx\n", \ - __func__, __LINE__, type, dev_path(dev), index, base, base + size - 1, size) - #define DEV_FUNC_ENTER(dev) \ printk(BIOS_SPEW, "%s:%s:%d: ENTER (dev: %s)\n", \ __FILE__, __func__, __LINE__, dev_path(dev)) From 8b522db474f1573e7f68cdb046d5dc4d789e084b Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Mon, 12 Oct 2020 11:58:46 -0600 Subject: [PATCH 016/129] soc/intel/xeon_sp: Move function debug macros Move the macros for printing debug information to debug.h in the common console include directory and device include file. These are available if the platform selects DEFAULT_CONSOLE_LOGLEVEL_8. The macros could be used by any platform. Change-Id: Ie237bdf8cdc42c76f38a0c820fdc92e81095f47c Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/46093 Tested-by: build bot (Jenkins) Reviewed-by: Jay Talbott Reviewed-by: Stefan Reinauer --- src/Kconfig | 10 +++++++++ src/include/console/debug.h | 22 +++++++++++++++++++ src/include/device/device.h | 14 ++++++++++++ src/soc/intel/xeon_sp/cpx/chip.c | 1 + src/soc/intel/xeon_sp/cpx/cpu.c | 1 + .../intel/xeon_sp/cpx/include/soc/soc_util.h | 16 -------------- src/soc/intel/xeon_sp/include/soc/util.h | 15 ------------- src/soc/intel/xeon_sp/skx/chip.c | 2 ++ src/soc/intel/xeon_sp/skx/cpu.c | 1 + 9 files changed, 51 insertions(+), 31 deletions(-) create mode 100644 src/include/console/debug.h diff --git a/src/Kconfig b/src/Kconfig index eda11c331e..dc98ca2c05 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1123,6 +1123,16 @@ config TRACE of calling function. Please note some printk related functions are omitted from trace to have good looking console dumps. +config DEBUG_FUNC + bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8 + default n + help + This option enables additional function entry and exit debug messages + for select functions. If supported, this is less output than + the TRACE option. + Note: This option will increase the size of the coreboot image. + If unsure, say N. + config DEBUG_COVERAGE bool "Debug code coverage" default n diff --git a/src/include/console/debug.h b/src/include/console/debug.h new file mode 100644 index 0000000000..174c287c6a --- /dev/null +++ b/src/include/console/debug.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _CONSOLE_DEBUG_H_ +#define _CONSOLE_DEBUG_H_ + +#if CONFIG(DEBUG_FUNC) +#include + +#define FUNC_ENTER() \ + printk(BIOS_SPEW, "%s:%s:%d: ENTER\n", __FILE__, __func__, __LINE__) + +#define FUNC_EXIT() \ + printk(BIOS_SPEW, "%s:%s:%d: EXIT\n", __FILE__, __func__, __LINE__) + +#else /* FUNC_DEBUG */ + +#define FUNC_ENTER() +#define FUNC_EXIT() + +#endif /* FUNC_DEBUG */ + +#endif diff --git a/src/include/device/device.h b/src/include/device/device.h index eb9ef42eef..8a481b2ca2 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -279,6 +279,20 @@ void show_all_devs_resources(int debug_level, const char *msg); #define LOG_IO_RESOURCE(type, dev, index, base, size) #endif /* DEBUG_RESOURCES*/ +#if CONFIG(DEBUG_FUNC) +#include +#define DEV_FUNC_ENTER(dev) \ + printk(BIOS_SPEW, "%s:%s:%d: ENTER (dev: %s)\n", \ + __FILE__, __func__, __LINE__, dev_path(dev)) + +#define DEV_FUNC_EXIT(dev) \ + printk(BIOS_SPEW, "%s:%s:%d: EXIT (dev: %s)\n", __FILE__, \ + __func__, __LINE__, dev_path(dev)) +#else /* DEBUG_FUNC */ +#define DEV_FUNC_ENTER(dev) +#define DEV_FUNC_EXIT(dev) +#endif /* DEBUG_FUNC */ + /* Rounding for boundaries. * Due to some chip bugs, go ahead and round IO to 16 */ diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index c5a8c1cb1c..6d2dfba3c7 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 0999f6d721..4afe47cbff 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index 412730b647..3e19bac6e9 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -3,24 +3,8 @@ #ifndef _SOC_UTIL_H_ #define _SOC_UTIL_H_ -#include #include #include -#include - -#define DEV_FUNC_ENTER(dev) \ - printk(BIOS_SPEW, "%s:%s:%d: ENTER (dev: %s)\n", \ - __FILE__, __func__, __LINE__, dev_path(dev)) - -#define DEV_FUNC_EXIT(dev) \ - printk(BIOS_SPEW, "%s:%s:%d: EXIT (dev: %s)\n", __FILE__, \ - __func__, __LINE__, dev_path(dev)) - -#define FUNC_ENTER() \ - printk(BIOS_SPEW, "%s:%s:%d: ENTER\n", __FILE__, __func__, __LINE__) - -#define FUNC_EXIT() \ - printk(BIOS_SPEW, "%s:%s:%d: EXIT\n", __FILE__, __func__, __LINE__) struct iiostack_resource { uint8_t no_of_stacks; diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index f223efafe0..8c2b597247 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -3,25 +3,10 @@ #ifndef _XEON_SP_SOC_UTIL_H_ #define _XEON_SP_SOC_UTIL_H_ -#include #include void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3); void unlock_pam_regions(void); void get_stack_busnos(uint32_t *bus); -#define DEV_FUNC_ENTER(dev) \ - printk(BIOS_SPEW, "%s:%s:%d: ENTER (dev: %s)\n", \ - __FILE__, __func__, __LINE__, dev_path(dev)) - -#define DEV_FUNC_EXIT(dev) \ - printk(BIOS_SPEW, "%s:%s:%d: EXIT (dev: %s)\n", __FILE__, \ - __func__, __LINE__, dev_path(dev)) - -#define FUNC_ENTER() \ - printk(BIOS_SPEW, "%s:%s:%d: ENTER\n", __FILE__, __func__, __LINE__) - -#define FUNC_EXIT() \ - printk(BIOS_SPEW, "%s:%s:%d: EXIT\n", __FILE__, __func__, __LINE__) - #endif diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index 4324660f47..fba1e1f7d0 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -2,6 +2,8 @@ #include #include +#include +#include #include #include #include diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index bf712c3618..581378b410 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include #include #include #include From dbf74dc80ab4db252c9ef1c340cf94c017443b78 Mon Sep 17 00:00:00 2001 From: Matt Ziegelbaum Date: Mon, 26 Oct 2020 22:04:22 -0400 Subject: [PATCH 017/129] hatch: Create ambassador variant Create the ambassador variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:171561514 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_AMBASSADOR Signed-off-by: Matt Ziegelbaum Change-Id: Ib0e3a813a120a4a8e984f3a89dc3ba100d94da95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46829 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/Kconfig | 2 + src/mainboard/google/hatch/Kconfig.name | 4 + .../hatch/variants/ambassador/Makefile.inc | 4 + .../google/hatch/variants/ambassador/gpio.c | 115 +++++ .../variants/ambassador/include/variant/ec.h | 8 + .../ambassador/include/variant/gpio.h | 8 + .../hatch/variants/ambassador/overridetree.cb | 480 ++++++++++++++++++ 7 files changed, 621 insertions(+) create mode 100644 src/mainboard/google/hatch/variants/ambassador/Makefile.inc create mode 100644 src/mainboard/google/hatch/variants/ambassador/gpio.c create mode 100644 src/mainboard/google/hatch/variants/ambassador/include/variant/ec.h create mode 100644 src/mainboard/google/hatch/variants/ambassador/include/variant/gpio.h create mode 100644 src/mainboard/google/hatch/variants/ambassador/overridetree.cb diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 257ad77a42..afc9de0192 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -143,6 +143,7 @@ config MAINBOARD_PART_NUMBER default "Stryke" if BOARD_GOOGLE_STRYKE default "Wyvern" if BOARD_GOOGLE_WYVERN default "Dooly" if BOARD_GOOGLE_DOOLY + default "Ambassador" if BOARD_GOOGLE_AMBASSADOR config OVERRIDE_DEVICETREE string @@ -176,6 +177,7 @@ config VARIANT_DIR default "stryke" if BOARD_GOOGLE_STRYKE default "wyvern" if BOARD_GOOGLE_WYVERN default "dooly" if BOARD_GOOGLE_DOOLY + default "ambassador" if BOARD_GOOGLE_AMBASSADOR config VBOOT select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 69bb28ac00..71166d0bcf 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -97,3 +97,7 @@ config BOARD_GOOGLE_WYVERN config BOARD_GOOGLE_DOOLY bool "-> Dooly" select BOARD_GOOGLE_BASEBOARD_PUFF + +config BOARD_GOOGLE_AMBASSADOR + bool "-> Ambassador" + select BOARD_GOOGLE_BASEBOARD_PUFF diff --git a/src/mainboard/google/hatch/variants/ambassador/Makefile.inc b/src/mainboard/google/hatch/variants/ambassador/Makefile.inc new file mode 100644 index 0000000000..3b5b7d000d --- /dev/null +++ b/src/mainboard/google/hatch/variants/ambassador/Makefile.inc @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += gpio.c +bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/ambassador/gpio.c b/src/mainboard/google/hatch/variants/ambassador/gpio.c new file mode 100644 index 0000000000..5a911fc4f9 --- /dev/null +++ b/src/mainboard/google/hatch/variants/ambassador/gpio.c @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static const struct pad_config gpio_table[] = { + /* A16 : SD_OC_ODL */ + PAD_CFG_GPI(GPP_A16, NONE, DEEP), + /* A18 : LAN_PE_ISOLATE_ODL */ + PAD_CFG_GPO(GPP_A18, 1, DEEP), + /* A23 : M2_WLAN_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), + + /* B5 : LAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + + /* C0 : SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1 : SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C6: M2_WLAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), + /* C7 : LAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), + /* C10 : PCH_PCON_RST_ODL */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C11 : PCH_PCON_PDB_ODL */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), + /* C15 : WLAN_OFF_L */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), + + /* E2 : EN_PP_MST_OD */ + PAD_CFG_GPO(GPP_E2, 1, DEEP), + /* E9 : USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : USB_A1_OC_ODL */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + + /* F11 : EMMC_CMD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA0 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA1 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA2 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA3 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA4 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA5 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA6 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA7 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_CLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + + /* H4: PCH_I2C_PCON_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5: PCH_I2C_PCON_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H22 : PWM_PP3300_BIOZZER */ + PAD_CFG_GPO(GPP_H22, 0, DEEP), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* B14 : GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B22 : GPP_B22_STRAP */ + PAD_NC(GPP_B22, NONE), + /* E19 : GPP_E19_STRAP */ + PAD_NC(GPP_E19, NONE), + /* E21 : GPP_E21_STRAP */ + PAD_NC(GPP_E21, NONE), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/ambassador/include/variant/ec.h b/src/mainboard/google/hatch/variants/ambassador/include/variant/ec.h new file mode 100644 index 0000000000..59fb3783c5 --- /dev/null +++ b/src/mainboard/google/hatch/variants/ambassador/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/ambassador/include/variant/gpio.h b/src/mainboard/google/hatch/variants/ambassador/include/variant/gpio.h new file mode 100644 index 0000000000..79a141008f --- /dev/null +++ b/src/mainboard/google/hatch/variants/ambassador/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb new file mode 100644 index 0000000000..adb00e485f --- /dev/null +++ b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb @@ -0,0 +1,480 @@ +chip soc/intel/cannonlake + # Enable heci communication + register "HeciEnabled" = "1" + + # Auto-switch between X4 NVMe and X2 NVMe. + register "TetonGlacierMode" = "1" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # USB configuration + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 2 + register "usb2_ports[1]" = "{ + .enable = 1, + .ocpin = OC1, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 1 + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC3, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 3 + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[4]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 4 + register "usb2_ports[5]" = "{ + .enable = 1, + .ocpin = OC0, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A port 0 + register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 + + # Bitmap for Wake Enable on USB attach/detach + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(5) | \ + USB_PORT_WAKE_ENABLE(6)" + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(5) | \ + USB_PORT_WAKE_ENABLE(6)" + + # Enable eMMC HS400 + register "ScsEmmcHs400Enabled" = "1" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-14.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-14.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-14.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-14.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-14.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-14.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" + + # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. + register "PchHdaAudioLinkSsp1" = "0" + register "PchHdaAudioLinkDmic0" = "0" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | RFU | + #| I2C2 | PS175 | + #| I2C3 | MST | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + }" + + # PCIe port 7 for LAN + register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + # PCIe port 11 (x2) for NVMe hybrid storage devices + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # Uses CLK SRC 0 + register "PcieClkSrcUsage[0]" = "6" + register "PcieClkSrcClkReq[0]" = "0" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + # SATA port 1 Gen3 Strength + # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB + register "sata_port[1].TxGen3DeEmphEnable" = "1" + register "sata_port[1].TxGen3DeEmph" = "0x20" + + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(90, 85), + TEMP_PCT(85, 75), + TEMP_PCT(80, 65), + TEMP_PCT(75, 55), + TEMP_PCT(70, 45),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(50, 85), + TEMP_PCT(47, 75), + TEMP_PCT(45, 65), + TEMP_PCT(42, 55), + TEMP_PCT(39, 45),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + + ## Power Limits Control + # PL1 is fixed at 15W, avg over 28-32s interval + # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 25000, + .max_power = 64000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Left"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Right"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Right"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Middle"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Left"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 2.5 on end + end + chip drivers/usb/acpi + device usb 2.6 off end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Left"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Right"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Right"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Left"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Middle"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.5 on end + end + end + end + end # USB xHCI + device pci 15.0 off + # RFU - Reserved for Future Use. + end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 on + chip drivers/i2c/generic + register "hid" = ""1AF80175"" + register "name" = ""PS17"" + register "desc" = ""Parade PS175"" + device i2c 4a on end + end + end # I2C #2, PCON PS175. + device pci 15.3 on + chip drivers/i2c/generic + register "hid" = ""10EC2142"" + register "name" = ""RTD2"" + register "desc" = ""Realtek RTD2142"" + device i2c 4a on end + end + end # I2C #3, Realtek RTD2142. + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1a.0 on end # eMMC + device pci 1c.6 on + chip drivers/net + register "customized_leds" = "0x05af" + register "wake" = "GPE0_DW1_07" # GPP_C7 + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" + register "stop_delay_ms" = "12" # NIC needs time to quiesce + register "stop_off_delay_ms" = "1" + register "has_power_resource" = "1" + register "device_index" = "0" + device pci 00.0 on end + end + end # RTL8111H Ethernet NIC + device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1e.3 off end # GSPI #1 + end + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | + #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | + #+----------------+-------+-------+-------+-------+ + #Note: IccMax settings are moved to SoC code + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 1004, + .dc_loadline = 1004, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 181, + .dc_loadline = 181, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 319, + .dc_loadline = 319, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 319, + .dc_loadline = 319, + }" + +end From c1f58e68fb93bf3da9c220b48b45519fb8fb0bf9 Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Mon, 26 Oct 2020 01:34:16 +0800 Subject: [PATCH 018/129] mb/google/volteer: correct memory id for elemi BUG=b:170604353 BRANCH=volteer TEST=emerge-volteer coreboot, and boot into kernel. Change-Id: If354aa158f3ad60193268f38278a44f9c99bf3db Signed-off-by: Wisley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/46770 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/variants/elemi/memory.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/volteer/variants/elemi/memory.c b/src/mainboard/google/volteer/variants/elemi/memory.c index d3de4be711..32b7abca17 100644 --- a/src/mainboard/google/volteer/variants/elemi/memory.c +++ b/src/mainboard/google/volteer/variants/elemi/memory.c @@ -21,10 +21,10 @@ const struct ddr_memory_cfg *variant_memory_params(void) int variant_memory_sku(void) { gpio_t spd_gpios[] = { - GPIO_MEM_CONFIG_3, - GPIO_MEM_CONFIG_2, - GPIO_MEM_CONFIG_1, GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, }; return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); From f2a295a5b6201b8346aa2474dc0e0a01d8806909 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 20:40:20 +0200 Subject: [PATCH 019/129] mb/google/jecht: Prepare devicetree for PCH split MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tested with BUILD_TIMELESS=1, all variants remain identical. Change-Id: I0fa486b8a0fc8be974f37d0bb4eb77a254e8cd86 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46703 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/google/jecht/devicetree.cb | 185 ++++++++++++----------- 1 file changed, 94 insertions(+), 91 deletions(-) diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index c4707e0c00..e5508228c9 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -9,27 +9,6 @@ chip soc/intel/broadwell # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # SuperIO range is 0x700-0x73f - register "gen2_dec" = "0x003c0701" - - register "alt_gp_smi_en" = "0x0000" - register "gpe0_en_1" = "0x00000000" - register "gpe0_en_2" = "0x00000000" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - register "sata_devslp_disable" = "0x1" - - # Force enable ASPM for PCIe Port 4 - register "pcie_port_force_aspm" = "0x10" - - # Enable port coalescing - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP - register "icc_clock_disable" = "0x01220000" - device cpu_cluster 0 on device lapic 0 on end end @@ -38,78 +17,102 @@ chip soc/intel/broadwell device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 off end # Serial I/O DMA - device pci 15.1 off end # I2C0 - device pci 15.2 off end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip superio/ite/it8772f - # Skip keyboard init - register "skip_keyboard" = "1" - # Enable PECI on TMPIN3 - register "peci_tmpin" = "3" - # Disable use of TMPIN1 - register "tmpin1_mode" = "0" - # Enable Thermal Diode on TMPIN2 - register "tmpin2_mode" = "1" - # Enable FAN2 - register "fan2_enable" = "1" - # Default FAN2 speed - register "fan2_speed" = "0x4d" - device pnp 2e.0 off end # FDC - device pnp 2e.1 on # Serial Port 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 +# chip soc/intel/broadwell/pch + # SuperIO range is 0x700-0x73f + register "gen2_dec" = "0x003c0701" + + register "alt_gp_smi_en" = "0x0000" + register "gpe0_en_1" = "0x00000000" + register "gpe0_en_2" = "0x00000000" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "sata_port_map" = "0x1" + register "sata_devslp_disable" = "0x1" + + # Force enable ASPM for PCIe Port 4 + register "pcie_port_force_aspm" = "0x10" + + # Enable port coalescing + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP + register "icc_clock_disable" = "0x01220000" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end end - device pnp 2e.4 on # Environment Controller - io 0x60 = 0x700 - io 0x62 = 0x710 - irq 0x70 = 0x09 - irq 0xf2 = 0x20 - irq 0xf4 = 0x0 - irq 0xfa = 0x12 + chip superio/ite/it8772f + # Skip keyboard init + register "skip_keyboard" = "1" + # Enable PECI on TMPIN3 + register "peci_tmpin" = "3" + # Disable use of TMPIN1 + register "tmpin1_mode" = "0" + # Enable Thermal Diode on TMPIN2 + register "tmpin2_mode" = "1" + # Enable FAN2 + register "fan2_enable" = "1" + # Default FAN2 speed + register "fan2_speed" = "0x4d" + + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x700 + io 0x62 = 0x710 + irq 0x70 = 0x09 + irq 0xf2 = 0x20 + irq 0xf4 = 0x0 + irq 0xfa = 0x12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x720 + io 0x62 = 0x730 + end + device pnp 2e.5 off + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end # Keyboard + device pnp 2e.6 off + irq 0x70 = 12 + end # Mouse + device pnp 2e.a off end # IR end - device pnp 2e.7 on # GPIO - io 0x60 = 0x720 - io 0x62 = 0x730 - end - device pnp 2e.5 off - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end # Keyboard - device pnp 2e.6 off - irq 0x70 = 12 - end # Mouse - device pnp 2e.a off end # IR - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal + end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal +# end end end From 5e60637ef6ca64bedacbdd5aad1d1a7a85d67c05 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 20:40:46 +0200 Subject: [PATCH 020/129] mb/intel/wtm2: Prepare devicetree for PCH split MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tested with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I75d6594f9576c96a585526c652a070cb9616dbe9 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46704 Reviewed-by: Arthur Heymans Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/intel/wtm2/devicetree.cb | 77 +++++++++++++------------- 1 file changed, 40 insertions(+), 37 deletions(-) diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index bff39b72eb..927a60344c 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -9,15 +9,6 @@ chip soc/intel/broadwell # Enable DVI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - register "alt_gp_smi_en" = "0x0000" - register "gpe0_en_1" = "0x00000400" - register "gpe0_en_2" = "0x00000000" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x2" - register "sio_acpi_mode" = "1" - device cpu_cluster 0 on device lapic 0 on end end @@ -25,33 +16,45 @@ chip soc/intel/broadwell device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 - device pci 1d.0 off end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal + +# chip soc/intel/broadwell/pch + register "alt_gp_smi_en" = "0x0000" + register "gpe0_en_1" = "0x00000400" + register "gpe0_en_2" = "0x00000000" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "sata_port_map" = "0x2" + register "sio_acpi_mode" = "1" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1d.0 off end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal +# end end end From 34672f2bc4e8378d3c24bc026022c36cef261ab1 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 20:41:09 +0200 Subject: [PATCH 021/129] mb/purism/librem_bdw: Prepare devicetree for PCH split MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tested with BUILD_TIMELESS=1, all variants remain identical. Change-Id: I0fe6de35f7471ce173df40db1444153623544f00 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46705 Reviewed-by: Arthur Heymans Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/purism/librem_bdw/devicetree.cb | 67 ++++++++++--------- .../variants/librem13v1/overridetree.cb | 20 +++--- .../variants/librem15v2/overridetree.cb | 20 +++--- 3 files changed, 57 insertions(+), 50 deletions(-) diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index b7c6fe58ae..4f34f7d6d4 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -16,10 +16,6 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms - # EC host command ranges are in 0x380-0x383 & 0x80-0x8f - register "gen1_dec" = "0x00000381" - register "gen2_dec" = "0x000c0081" - device cpu_cluster 0 on device lapic 0 on end end @@ -27,33 +23,40 @@ chip soc/intel/broadwell device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 off end # Serial I/O DMA - device pci 15.1 off end # I2C0 - device pci 15.2 off end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - LAN - device pci 1c.3 on end # PCIe Port #4 - WiFi - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe - device pci 1d.0 off end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 off end # Thermal + +# chip soc/intel/broadwell/pch + # EC host command ranges are in 0x380-0x383 & 0x80-0x8f + register "gen1_dec" = "0x00000381" + register "gen2_dec" = "0x000c0081" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 - LAN + device pci 1c.3 on end # PCIe Port #4 - WiFi + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe + device pci 1d.0 off end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 off end # Thermal +# end end end diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb index d3d0ae72d0..237e6979ec 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb @@ -1,14 +1,16 @@ chip soc/intel/broadwell - # Port 0 is HDD - # Port 3 is M.2 NGFF - register "sata_port_map" = "0x9" - - # Port tuning for link stability - register "sata_port0_gen3_dtle" = "9" - register "sata_port3_gen3_dtle" = "9" - device domain 0 on - device pci 1c.2 on end # PCIe Port #3 - LAN +# chip soc/intel/broadwell/pch + # Port 0 is HDD + # Port 3 is M.2 NGFF + register "sata_port_map" = "0x9" + + # Port tuning for link stability + register "sata_port0_gen3_dtle" = "9" + register "sata_port3_gen3_dtle" = "9" + + device pci 1c.2 on end # PCIe Port #3 - LAN +# end end end diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb index c0c8d0360f..b9b29cd6ff 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb @@ -1,14 +1,16 @@ chip soc/intel/broadwell - # Port 0 is HDD - # Port 1 is M.2 NGFF - register "sata_port_map" = "0x3" - - # Port tuning for link stability - register "sata_port0_gen3_dtle" = "7" - register "sata_port1_gen3_dtle" = "9" - device domain 0 on - device pci 1d.0 on end # USB2 EHCI +# chip soc/intel/broadwell/pch + # Port 0 is HDD + # Port 1 is M.2 NGFF + register "sata_port_map" = "0x3" + + # Port tuning for link stability + register "sata_port0_gen3_dtle" = "7" + register "sata_port1_gen3_dtle" = "9" + + device pci 1d.0 on end # USB2 EHCI +# end end end From d79b87a1d6fcd6228edbd894e7e7ebc9b85d2813 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 16:44:22 +0100 Subject: [PATCH 022/129] mb/google/auron: Add SATA PCI device to overridetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit `chip` entries are only hooked up via device nodes to the tree. A `chip` without a `device` below it does nothing. To allow variants to override SATA tuning parameters, ensure a device exists under the PCH chip scope. Without this change, some variants would not properly override the SATA tuning parameters after extracting the PCH parts into a different chip. TEST=Sanity-check static.c and verify overridetrees override properly. Change-Id: I013dbe1403567b93c8ee0e66f76481f2a3f42796 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46769 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/google/auron/variants/auron_paine/overridetree.cb | 2 ++ src/mainboard/google/auron/variants/auron_yuna/overridetree.cb | 2 ++ src/mainboard/google/auron/variants/buddy/overridetree.cb | 1 + src/mainboard/google/auron/variants/gandof/overridetree.cb | 2 ++ src/mainboard/google/auron/variants/lulu/overridetree.cb | 2 ++ src/mainboard/google/auron/variants/samus/overridetree.cb | 1 + 6 files changed, 10 insertions(+) diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb index dc70085dd0..f5f3eeacdf 100644 --- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb @@ -12,6 +12,8 @@ chip soc/intel/broadwell # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5" + + device pci 1f.2 on end # SATA Controller # end end end diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb index b46e34cf83..5a64648cd1 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb @@ -12,6 +12,8 @@ chip soc/intel/broadwell # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x7" register "sata_port1_gen3_dtle" = "0x5" + + device pci 1f.2 on end # SATA Controller # end end end diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index 45229bad6d..5b6ab9f858 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -34,6 +34,7 @@ chip soc/intel/broadwell device pci 1c.0 off end # PCIe Port #1 device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1) device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) + device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus # end end diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb index eae7999ea2..924e7d3c90 100644 --- a/src/mainboard/google/auron/variants/gandof/overridetree.cb +++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb @@ -12,6 +12,8 @@ chip soc/intel/broadwell # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5" + + device pci 1f.2 on end # SATA Controller # end end end diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb index dc70085dd0..f5f3eeacdf 100644 --- a/src/mainboard/google/auron/variants/lulu/overridetree.cb +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -12,6 +12,8 @@ chip soc/intel/broadwell # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5" + + device pci 1f.2 on end # SATA Controller # end end end diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index 710fa95cac..93445756e2 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -36,6 +36,7 @@ chip soc/intel/broadwell device pci 1c.0 off end # PCIe Port #1 device pci 1c.2 on end # PCIe Port #3 device pci 1d.0 off end # USB2 EHCI + device pci 1f.2 on end # SATA Controller # end end end From a6f02a8c494a6a8584caf0453a028d76bdd2d972 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 02:14:51 +0200 Subject: [PATCH 023/129] soc/intel/broadwell/cpu.c: Re-add `configure_thermal_target` MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 360684b (soc/intel/common: add TCC activation functionality) made Broadwell use common SoC code. However, this makes Broadwell depend on SoC code, which prevents splitting Broadwell into CPU, northbridge and southbridge, a stepping stone before merging with Haswell and Lynxpoint. Tested on out-of-tree Acer E5-573, still boots. Change-Id: Ib7ab4e75bd4416dde4612e67405a871da569008a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46731 Reviewed-by: Arthur Heymans Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/cpu.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 00460c6282..694c7277a4 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -290,6 +290,28 @@ static void configure_c_states(void) wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } +static void configure_thermal_target(void) +{ + config_t *conf; + struct device *lapic; + msr_t msr; + + /* Find pointer to CPU configuration */ + lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + if (!lapic || !lapic->chip_info) + return; + conf = lapic->chip_info; + + /* Set TCC activation offset if supported */ + msr = rdmsr(MSR_PLATFORM_INFO); + if ((msr.lo & (1 << 30)) && conf->tcc_offset) { + msr = rdmsr(MSR_TEMPERATURE_TARGET); + msr.lo &= ~(0xf << 24); /* Bits 27:24 */ + msr.lo |= (conf->tcc_offset & 0xf) << 24; + wrmsr(MSR_TEMPERATURE_TARGET, msr); + } +} + static void configure_misc(void) { msr_t msr; @@ -372,7 +394,7 @@ static void cpu_core_init(struct device *cpu) configure_misc(); /* Thermal throttle activation offset */ - configure_tcc_thermal_target(); + configure_thermal_target(); /* Enable Direct Cache Access */ configure_dca_cap(); From 9f6cdbaaf5d1a799e314e0baf9f4fda218abdf75 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 00:02:29 +0000 Subject: [PATCH 024/129] Revert "broadwell: update processor power limits configuration" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit fa42d568a00e5daadd35722790c529539227130e. Reason for revert: Passes in an incompatible structure and only happens to boot by chance. Moreover, Broadwell will soon be merged with Haswell and this requires Broadwell to not depend on any Intel common SoC code. Tested on out-of-tree Acer Aspire E5-573, PL values are correct again. Change-Id: I6e8e000dba8ff09fab4e6f174ab703348dcd6a96 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45011 Reviewed-by: Michael Niewöhner Reviewed-by: Tim Wawrzynczak Reviewed-by: Sumeet R Pawnikar Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/Kconfig | 3 - src/soc/intel/broadwell/acpi.c | 1 - src/soc/intel/broadwell/chip.h | 1 - src/soc/intel/broadwell/cpu.c | 143 +++++++++++++++++- src/soc/intel/broadwell/include/soc/cpu.h | 4 + src/soc/intel/broadwell/include/soc/msr.h | 10 +- .../intel/broadwell/include/soc/soc_chip.h | 8 - src/soc/intel/broadwell/systemagent.c | 5 +- 8 files changed, 155 insertions(+), 20 deletions(-) delete mode 100644 src/soc/intel/broadwell/include/soc/soc_chip.h diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 35129af8b7..2430be61f5 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -33,9 +33,6 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select TSC_MONOTONIC_TIMER select SOC_INTEL_COMMON - select SOC_INTEL_COMMON_BLOCK - select SOC_INTEL_COMMON_BLOCK_CPU - select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 760842b2ab..1b4db1dae6 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -24,7 +24,6 @@ #include #include #include -#include /* * List of supported C-states in this processor. Only the ULT parts support C8, diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index ae433536cd..45d512ac02 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -4,7 +4,6 @@ #define _SOC_INTEL_BROADWELL_CHIP_H_ #include -#include #include struct soc_intel_broadwell_config { diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 694c7277a4..72efa3dc81 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -25,6 +24,64 @@ #include #include +/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ +static const u8 power_limit_time_sec_to_msr[] = { + [0] = 0x00, + [1] = 0x0a, + [2] = 0x0b, + [3] = 0x4b, + [4] = 0x0c, + [5] = 0x2c, + [6] = 0x4c, + [7] = 0x6c, + [8] = 0x0d, + [10] = 0x2d, + [12] = 0x4d, + [14] = 0x6d, + [16] = 0x0e, + [20] = 0x2e, + [24] = 0x4e, + [28] = 0x6e, + [32] = 0x0f, + [40] = 0x2f, + [48] = 0x4f, + [56] = 0x6f, + [64] = 0x10, + [80] = 0x30, + [96] = 0x50, + [112] = 0x70, + [128] = 0x11, +}; + +/* Convert POWER_LIMIT_1_TIME MSR value to seconds */ +static const u8 power_limit_time_msr_to_sec[] = { + [0x00] = 0, + [0x0a] = 1, + [0x0b] = 2, + [0x4b] = 3, + [0x0c] = 4, + [0x2c] = 5, + [0x4c] = 6, + [0x6c] = 7, + [0x0d] = 8, + [0x2d] = 10, + [0x4d] = 12, + [0x6d] = 14, + [0x0e] = 16, + [0x2e] = 20, + [0x4e] = 24, + [0x6e] = 28, + [0x0f] = 32, + [0x2f] = 40, + [0x4f] = 48, + [0x6f] = 56, + [0x10] = 64, + [0x30] = 80, + [0x50] = 96, + [0x70] = 112, + [0x11] = 128, +}; + /* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate * the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly * when a core is woken up. */ @@ -230,6 +287,90 @@ static void configure_pch_power_sharing(void) RCBA32(PMSYNC_CONFIG2) = pmsync2; } +int cpu_config_tdp_levels(void) +{ + msr_t platform_info; + + /* Bits 34:33 indicate how many levels supported */ + platform_info = rdmsr(MSR_PLATFORM_INFO); + return (platform_info.hi >> 1) & 3; +} + +/* + * Configure processor power limits if possible + * This must be done AFTER set of BIOS_RESET_CPL + */ +void set_power_limits(u8 power_limit_1_time) +{ + msr_t msr = rdmsr(MSR_PLATFORM_INFO); + msr_t limit; + unsigned int power_unit; + unsigned int tdp, min_power, max_power, max_time; + u8 power_limit_1_val; + + if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) + power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; + + if (!(msr.lo & PLATFORM_INFO_SET_TDP)) + return; + + /* Get units */ + msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = 2 << ((msr.lo & 0xf) - 1); + + /* Get power defaults for this SKU */ + msr = rdmsr(MSR_PKG_POWER_SKU); + tdp = msr.lo & 0x7fff; + min_power = (msr.lo >> 16) & 0x7fff; + max_power = msr.hi & 0x7fff; + max_time = (msr.hi >> 16) & 0x7f; + + printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); + + if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) + power_limit_1_time = power_limit_time_msr_to_sec[max_time]; + + if (min_power > 0 && tdp < min_power) + tdp = min_power; + + if (max_power > 0 && tdp > max_power) + tdp = max_power; + + power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; + + /* Set long term power limit to TDP */ + limit.lo = 0; + limit.lo |= tdp & PKG_POWER_LIMIT_MASK; + limit.lo |= PKG_POWER_LIMIT_EN; + limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << + PKG_POWER_LIMIT_TIME_SHIFT; + + /* Set short term power limit to 1.25 * TDP */ + limit.hi = 0; + limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; + limit.hi |= PKG_POWER_LIMIT_EN; + /* Power limit 2 time is only programmable on server SKU */ + + wrmsr(MSR_PKG_POWER_LIMIT, limit); + + /* Set power limit values in MCHBAR as well */ + MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo; + MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi; + + /* Set DDR RAPL power limit by copying from MMIO to MSR */ + msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO); + msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI); + wrmsr(MSR_DDR_RAPL_LIMIT, msr); + + /* Use nominal TDP values for CPUs with configurable TDP */ + if (cpu_config_tdp_levels()) { + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + limit.hi = 0; + limit.lo = msr.lo & 0xff; + wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); + } +} + static void configure_c_states(void) { msr_t msr; diff --git a/src/soc/intel/broadwell/include/soc/cpu.h b/src/soc/intel/broadwell/include/soc/cpu.h index 9167736c00..02605851ce 100644 --- a/src/soc/intel/broadwell/include/soc/cpu.h +++ b/src/soc/intel/broadwell/include/soc/cpu.h @@ -37,6 +37,10 @@ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ (IRTL_1024_NS >> 10)) +/* Configure power limits for turbo mode */ +void set_power_limits(u8 power_limit_1_time); +int cpu_config_tdp_levels(void); + /* CPU identification */ u32 cpu_family_model(void); u32 cpu_stepping(void); diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index b8ed3328cc..6a5f4dc5f1 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -3,8 +3,6 @@ #ifndef _BROADWELL_MSR_H_ #define _BROADWELL_MSR_H_ -#include - #define MSR_CORE_THREAD_COUNT 0x35 #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) @@ -46,6 +44,14 @@ #define IRTL_RESPONSE_MASK (0x3ff) #define MSR_COUNTER_24_MHZ 0x637 +/* Long duration in low dword, short duration in high dword */ +#define MSR_PKG_POWER_LIMIT 0x610 +#define PKG_POWER_LIMIT_MASK 0x7fff +#define PKG_POWER_LIMIT_EN (1 << 15) +#define PKG_POWER_LIMIT_CLAMP (1 << 16) +#define PKG_POWER_LIMIT_TIME_SHIFT 17 +#define PKG_POWER_LIMIT_TIME_MASK 0x7f + #define MSR_VR_CURRENT_CONFIG 0x601 #define MSR_VR_MISC_CONFIG 0x603 #define MSR_PKG_POWER_SKU_UNIT 0x606 diff --git a/src/soc/intel/broadwell/include/soc/soc_chip.h b/src/soc/intel/broadwell/include/soc/soc_chip.h deleted file mode 100644 index bbd556e55d..0000000000 --- a/src/soc/intel/broadwell/include/soc/soc_chip.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_BROADWELL_SOC_CHIP_H_ -#define _SOC_BROADWELL_SOC_CHIP_H_ - -#include "../../chip.h" - -#endif /* _SOC_BROADWELL_SOC_CHIP_H_ */ diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 4b4848b4ef..dc6f546780 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -406,7 +405,6 @@ static void systemagent_read_resources(struct device *dev) static void systemagent_init(struct device *dev) { - struct soc_power_limits_config *config; u8 bios_reset_cpl, pair; /* Enable Power Aware Interrupt Routing */ @@ -426,8 +424,7 @@ static void systemagent_init(struct device *dev) /* Configure turbo power limits 1ms after reset complete bit */ mdelay(1); - config = config_of_soc(); - set_power_limits(MOBILE_SKU_PL1_TIME_SEC, config); + set_power_limits(28); } static struct device_operations systemagent_ops = { From 3cc2c38d50741fffb9193851a4a3b7c636f7cd4d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 20:38:23 +0200 Subject: [PATCH 025/129] soc/intel/broadwell: Separate PCH in devicetree Flesh out the PCH configuration into a separate chip. Keep it within the Broadwell SoC directory for now, to ease moving files around. The boards were prepared beforehand and the devicetrees require next to no changes. Tested on out-of-tree Acer Aspire E5-573, still boots. Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46700 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/mainboard/google/auron/devicetree.cb | 4 +- .../variants/auron_paine/overridetree.cb | 4 +- .../auron/variants/auron_yuna/overridetree.cb | 4 +- .../auron/variants/buddy/overridetree.cb | 4 +- .../auron/variants/gandof/overridetree.cb | 4 +- .../auron/variants/lulu/overridetree.cb | 4 +- .../auron/variants/samus/overridetree.cb | 4 +- src/mainboard/google/jecht/devicetree.cb | 4 +- src/mainboard/intel/wtm2/devicetree.cb | 4 +- src/mainboard/purism/librem_bdw/devicetree.cb | 4 +- .../variants/librem13v1/overridetree.cb | 4 +- .../variants/librem15v2/overridetree.cb | 4 +- src/soc/intel/broadwell/adsp.c | 4 +- src/soc/intel/broadwell/chip.h | 72 +---------------- .../intel/broadwell/include/soc/ramstage.h | 1 - src/soc/intel/broadwell/lpc.c | 8 +- src/soc/intel/broadwell/me.c | 4 +- src/soc/intel/broadwell/pch.c | 13 +++- src/soc/intel/broadwell/pch/chip.h | 78 +++++++++++++++++++ src/soc/intel/broadwell/pcie.c | 6 +- src/soc/intel/broadwell/romstage/pch.c | 6 +- src/soc/intel/broadwell/sata.c | 6 +- src/soc/intel/broadwell/serialio.c | 4 +- src/soc/intel/broadwell/systemagent.c | 6 -- 24 files changed, 135 insertions(+), 121 deletions(-) create mode 100644 src/soc/intel/broadwell/pch/chip.h diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index 09593b7b53..26a53366b4 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -26,7 +26,7 @@ chip soc/intel/broadwell device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # EC range is 0x800-0x9ff register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x00fc0901" @@ -83,6 +83,6 @@ chip soc/intel/broadwell device pci 1f.2 on end # SATA Controller device pci 1f.3 off end # SMBus device pci 1f.6 on end # Thermal -# end + end end end diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb index f5f3eeacdf..81110408c1 100644 --- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb @@ -8,12 +8,12 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5" device pci 1f.2 on end # SATA Controller -# end + end end end diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb index 5a64648cd1..eb33d433e8 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb @@ -8,12 +8,12 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x7" register "sata_port1_gen3_dtle" = "0x5" device pci 1f.2 on end # SATA Controller -# end + end end end diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index 5b6ab9f858..60fb08cbf7 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -10,7 +10,7 @@ chip soc/intel/broadwell register "s0ix_enable" = "0" device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch register "sata_devslp_disable" = "0x1" register "sio_i2c0_voltage" = "1" # 1.8V @@ -36,6 +36,6 @@ chip soc/intel/broadwell device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus -# end + end end end diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb index 924e7d3c90..c7e2421ee8 100644 --- a/src/mainboard/google/auron/variants/gandof/overridetree.cb +++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb @@ -8,12 +8,12 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5" device pci 1f.2 on end # SATA Controller -# end + end end end diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb index f5f3eeacdf..81110408c1 100644 --- a/src/mainboard/google/auron/variants/lulu/overridetree.cb +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -8,12 +8,12 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5" device pci 1f.2 on end # SATA Controller -# end + end end end diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index 93445756e2..d8aec0ae04 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -17,7 +17,7 @@ chip soc/intel/broadwell register "s0ix_enable" = "0" device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch register "sata_port0_gen3_tx" = "0x72" # Set I2C0 to 1.8V @@ -37,6 +37,6 @@ chip soc/intel/broadwell device pci 1c.2 on end # PCIe Port #3 device pci 1d.0 off end # USB2 EHCI device pci 1f.2 on end # SATA Controller -# end + end end end diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index e5508228c9..94fd8044c1 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -18,7 +18,7 @@ chip soc/intel/broadwell device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701" @@ -113,6 +113,6 @@ chip soc/intel/broadwell device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus device pci 1f.6 on end # Thermal -# end + end end end diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index 927a60344c..29041aaeca 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -17,7 +17,7 @@ chip soc/intel/broadwell device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch register "alt_gp_smi_en" = "0x0000" register "gpe0_en_1" = "0x00000400" register "gpe0_en_2" = "0x00000000" @@ -55,6 +55,6 @@ chip soc/intel/broadwell device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus device pci 1f.6 on end # Thermal -# end + end end end diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index 4f34f7d6d4..0d0fc720f7 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -24,7 +24,7 @@ chip soc/intel/broadwell device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # EC host command ranges are in 0x380-0x383 & 0x80-0x8f register "gen1_dec" = "0x00000381" register "gen2_dec" = "0x000c0081" @@ -57,6 +57,6 @@ chip soc/intel/broadwell device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus device pci 1f.6 off end # Thermal -# end + end end end diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb index 237e6979ec..256077cbd9 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/broadwell device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # Port 0 is HDD # Port 3 is M.2 NGFF register "sata_port_map" = "0x9" @@ -11,6 +11,6 @@ chip soc/intel/broadwell register "sata_port3_gen3_dtle" = "9" device pci 1c.2 on end # PCIe Port #3 - LAN -# end + end end end diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb index b9b29cd6ff..d88c19c26a 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/broadwell device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # Port 0 is HDD # Port 1 is M.2 NGFF register "sata_port_map" = "0x3" @@ -11,6 +11,6 @@ chip soc/intel/broadwell register "sata_port1_gen3_dtle" = "9" device pci 1d.0 on end # USB2 EHCI -# end + end end end diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index 220ad6f269..06dd38bd8a 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -14,11 +14,11 @@ #include #include #include -#include +#include static void adsp_init(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); struct resource *bar0, *bar1; u32 tmp32; diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 45d512ac02..81c9780776 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -7,70 +7,6 @@ #include struct soc_intel_broadwell_config { - /* GPE configuration */ - uint32_t gpe0_en_1; - uint32_t gpe0_en_2; - uint32_t gpe0_en_3; - uint32_t gpe0_en_4; - - /* GPIO SMI configuration */ - uint32_t alt_gp_smi_en; - - /* IDE configuration */ - uint8_t sata_port_map; - uint32_t sata_port0_gen3_tx; - uint32_t sata_port1_gen3_tx; - uint32_t sata_port2_gen3_tx; - uint32_t sata_port3_gen3_tx; - uint32_t sata_port0_gen3_dtle; - uint32_t sata_port1_gen3_dtle; - uint32_t sata_port2_gen3_dtle; - uint32_t sata_port3_gen3_dtle; - - /* - * SATA DEVSLP Mux - * 0 = port 0 DEVSLP on DEVSLP0/GPIO33 - * 1 = port 3 DEVSLP on DEVSLP0/GPIO33 - */ - uint8_t sata_devslp_mux; - - /* - * DEVSLP Disable - * 0: DEVSLP is enabled - * 1: DEVSLP is disabled - */ - uint8_t sata_devslp_disable; - - /* Generic IO decode ranges */ - uint32_t gen1_dec; - uint32_t gen2_dec; - uint32_t gen3_dec; - uint32_t gen4_dec; - - /* Enable linear PCIe Root Port function numbers starting at zero */ - uint8_t pcie_port_coalesce; - - /* Force root port ASPM configuration with port bitmap */ - uint8_t pcie_port_force_aspm; - - /* Put SerialIO devices into ACPI mode instead of a PCI device */ - uint8_t sio_acpi_mode; - - /* I2C voltage select: 0=3.3V 1=1.8V */ - uint8_t sio_i2c0_voltage; - uint8_t sio_i2c1_voltage; - - /* Enable ADSP power gating features */ - uint8_t adsp_d3_pg_enable; - uint8_t adsp_sram_pg_enable; - - /* - * Clock Disable Map: - * [21:16] = CLKOUT_PCIE# 5-0 - * [24] = CLKOUT_ITPXDP - */ - uint32_t icc_clock_disable; - /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -107,9 +43,6 @@ struct soc_intel_broadwell_config { struct i915_gpu_controller_info gfx; - /* Enable S0iX support */ - int s0ix_enable; - /* * Minimum voltage for C6/C7 state: * 0x67 = 1.6V (full swing) @@ -132,9 +65,8 @@ struct soc_intel_broadwell_config { /* Enable slow VR ramp rate */ int vr_slow_ramp_rate_enable; - /* Deep SX enable */ - int deep_sx_enable_ac; - int deep_sx_enable_dc; + /* Enable S0iX support */ + int s0ix_enable; /* TCC activation offset */ uint32_t tcc_offset; diff --git a/src/soc/intel/broadwell/include/soc/ramstage.h b/src/soc/intel/broadwell/include/soc/ramstage.h index 0b6ef0d61b..5d7eceb4a5 100644 --- a/src/soc/intel/broadwell/include/soc/ramstage.h +++ b/src/soc/intel/broadwell/include/soc/ramstage.h @@ -8,7 +8,6 @@ void broadwell_init_pre_device(void *chip_info); void broadwell_init_cpus(struct device *dev); -void broadwell_pch_enable_dev(struct device *dev); #if CONFIG(HAVE_REFCODE_BLOB) void broadwell_run_reference_code(void); diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 8b85a0420d..2111913a0e 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include @@ -130,7 +130,7 @@ static void pch_power_options(struct device *dev) u16 reg16; const char *state; /* Get the chip configuration */ - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; /* Which state do we want to goto after g3 (power restored)? @@ -336,7 +336,7 @@ static void pch_enable_mphy(void) static void pch_init_deep_sx(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); if (config->deep_sx_enable_ac) { RCBA32_OR(DEEP_S3_POL, DEEP_S3_EN_AC); @@ -567,7 +567,7 @@ static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, static void pch_lpc_add_io_resources(struct device *dev) { struct resource *res; - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); /* Add the default claimed IO range for the LPC device. */ res = new_resource(dev, 0); diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 80ffe2b9ac..40a81d8810 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #if CONFIG(CHROMEOS) #include @@ -950,7 +950,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) /* Check whether ME is present and do basic init */ static void intel_me_init(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); me_bios_path path = intel_me_path(dev); me_bios_payload mbp_data; int mbp_ret; diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index 2a27d92152..e0c5bb0c4d 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -166,10 +166,16 @@ void pch_disable_devfn(struct device *dev) } } -void broadwell_pch_enable_dev(struct device *dev) +static void broadwell_pch_enable_dev(struct device *dev) { u16 reg16; + if (dev->path.type != DEVICE_PATH_PCI) + return; + + if (dev->ops && dev->ops->enable) + return; + /* These devices need special enable/disable handling */ switch (PCI_SLOT(dev->path.pci.devfn)) { case PCH_DEV_SLOT_PCIE: @@ -195,4 +201,9 @@ void broadwell_pch_enable_dev(struct device *dev) } } +struct chip_operations soc_intel_broadwell_pch_ops = { + CHIP_NAME("Intel Broadwell PCH") + .enable_dev = &broadwell_pch_enable_dev, +}; + #endif diff --git a/src/soc/intel/broadwell/pch/chip.h b/src/soc/intel/broadwell/pch/chip.h new file mode 100644 index 0000000000..2164a31050 --- /dev/null +++ b/src/soc/intel/broadwell/pch/chip.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_BROADWELL_PCH_CHIP_H_ +#define _SOC_INTEL_BROADWELL_PCH_CHIP_H_ + +#include + +struct soc_intel_broadwell_pch_config { + /* GPE configuration */ + uint32_t gpe0_en_1; + uint32_t gpe0_en_2; + uint32_t gpe0_en_3; + uint32_t gpe0_en_4; + + /* GPIO SMI configuration */ + uint32_t alt_gp_smi_en; + + /* IDE configuration */ + uint8_t sata_port_map; + uint32_t sata_port0_gen3_tx; + uint32_t sata_port1_gen3_tx; + uint32_t sata_port2_gen3_tx; + uint32_t sata_port3_gen3_tx; + uint32_t sata_port0_gen3_dtle; + uint32_t sata_port1_gen3_dtle; + uint32_t sata_port2_gen3_dtle; + uint32_t sata_port3_gen3_dtle; + + /* + * SATA DEVSLP Mux + * 0 = port 0 DEVSLP on DEVSLP0/GPIO33 + * 1 = port 3 DEVSLP on DEVSLP0/GPIO33 + */ + uint8_t sata_devslp_mux; + + /* + * DEVSLP Disable + * 0: DEVSLP is enabled + * 1: DEVSLP is disabled + */ + uint8_t sata_devslp_disable; + + /* Generic IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; + + /* Enable linear PCIe Root Port function numbers starting at zero */ + uint8_t pcie_port_coalesce; + + /* Force root port ASPM configuration with port bitmap */ + uint8_t pcie_port_force_aspm; + + /* Put SerialIO devices into ACPI mode instead of a PCI device */ + uint8_t sio_acpi_mode; + + /* I2C voltage select: 0=3.3V 1=1.8V */ + uint8_t sio_i2c0_voltage; + uint8_t sio_i2c1_voltage; + + /* Enable ADSP power gating features */ + uint8_t adsp_d3_pg_enable; + uint8_t adsp_sram_pg_enable; + + /* + * Clock Disable Map: + * [21:16] = CLKOUT_PCIE# 5-0 + * [24] = CLKOUT_ITPXDP + */ + uint32_t icc_clock_disable; + + /* Deep SX enable */ + int deep_sx_enable_ac; + int deep_sx_enable_dc; +}; + +#endif diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 0d41d42525..c98201e5ab 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include @@ -121,7 +121,7 @@ static void root_port_init_config(struct device *dev) root_port_config_update_gbe_port(); pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4)); - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); rpc.coalesce = config->pcie_port_coalesce; } @@ -436,7 +436,7 @@ static void pcie_add_0x0202000_iobp(u32 reg) static void pch_pcie_early(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); int do_aspm = 0; int rp = root_port_number(dev); diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index d68e17eee2..149dda1ca0 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include static void pch_route_interrupts(void) { @@ -52,9 +52,9 @@ static void pch_route_interrupts(void) static void pch_enable_lpc(void) { /* Lookup device tree in romstage */ - const config_t *config; + const struct device *const dev = pcidev_on_root(0x1f, 0); - config = config_of_soc(); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec); pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec); diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index c9168325e2..b496e53e3d 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include static inline u32 sir_read(struct device *dev, int idx) { @@ -27,7 +27,7 @@ static inline void sir_write(struct device *dev, int idx, u32 value) static void sata_init(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); u32 reg32; u8 *abar; u16 reg16; @@ -256,7 +256,7 @@ static void sata_init(struct device *dev) static void sata_enable(struct device *dev) { /* Get the chip configuration */ - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); u16 map = 0x0060; map |= (config->sata_port_map ^ 0xf) << 8; diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index 766f5dd048..d32a27ddca 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include /* Set D3Hot Power State in ACPI mode */ static void serialio_enable_d3hot(struct resource *res) @@ -156,7 +156,7 @@ static void serialio_init_once(int acpi_mode) static void serialio_init(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); struct resource *bar0, *bar1; int sio_index = -1; diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index dc6f546780..b9aeb388a1 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -472,12 +472,6 @@ static void broadwell_enable(struct device *dev) dev->ops = &pci_domain_ops; } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; - } else if (dev->path.type == DEVICE_PATH_PCI) { - /* Handle PCH device enable */ - if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_MINIHD && - (dev->ops == NULL || dev->ops->enable == NULL)) { - broadwell_pch_enable_dev(dev); - } } } From c200e8c7cdebed98860a771888efbf998c5912b3 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 21:37:21 +0200 Subject: [PATCH 026/129] soc/intel/broadwell: Move PCH code into pch subdir Change-Id: Icb57eb89b4f225298e43ae27970dc1e27fb6e222 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46706 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/Makefile.inc | 36 +----------------- src/soc/intel/broadwell/pch/Makefile.inc | 38 +++++++++++++++++++ src/soc/intel/broadwell/{ => pch}/adsp.c | 0 .../{bootblock/pch.c => pch/bootblock.c} | 0 .../{romstage/pch.c => pch/early_pch.c} | 0 src/soc/intel/broadwell/{ => pch}/ehci.c | 0 src/soc/intel/broadwell/{ => pch}/elog.c | 0 src/soc/intel/broadwell/{ => pch}/fadt.c | 0 src/soc/intel/broadwell/{ => pch}/gpio.c | 0 src/soc/intel/broadwell/{ => pch}/hda.c | 0 src/soc/intel/broadwell/{ => pch}/iobp.c | 0 src/soc/intel/broadwell/{ => pch}/lpc.c | 0 src/soc/intel/broadwell/{ => pch}/me.c | 0 src/soc/intel/broadwell/{ => pch}/me_status.c | 0 src/soc/intel/broadwell/{ => pch}/pch.c | 0 src/soc/intel/broadwell/{ => pch}/pcie.c | 0 src/soc/intel/broadwell/{ => pch}/pmutil.c | 0 .../broadwell/{romstage => pch}/power_state.c | 0 src/soc/intel/broadwell/{ => pch}/sata.c | 0 src/soc/intel/broadwell/{ => pch}/serialio.c | 0 src/soc/intel/broadwell/{ => pch}/smbus.c | 0 src/soc/intel/broadwell/{ => pch}/smi.c | 0 .../intel/broadwell/{ => pch}/smihandler.c | 0 .../intel/broadwell/{romstage => pch}/uart.c | 0 src/soc/intel/broadwell/{ => pch}/usb_debug.c | 0 src/soc/intel/broadwell/{ => pch}/xhci.c | 0 src/soc/intel/broadwell/romstage/Makefile.inc | 3 -- 27 files changed, 40 insertions(+), 37 deletions(-) create mode 100644 src/soc/intel/broadwell/pch/Makefile.inc rename src/soc/intel/broadwell/{ => pch}/adsp.c (100%) rename src/soc/intel/broadwell/{bootblock/pch.c => pch/bootblock.c} (100%) rename src/soc/intel/broadwell/{romstage/pch.c => pch/early_pch.c} (100%) rename src/soc/intel/broadwell/{ => pch}/ehci.c (100%) rename src/soc/intel/broadwell/{ => pch}/elog.c (100%) rename src/soc/intel/broadwell/{ => pch}/fadt.c (100%) rename src/soc/intel/broadwell/{ => pch}/gpio.c (100%) rename src/soc/intel/broadwell/{ => pch}/hda.c (100%) rename src/soc/intel/broadwell/{ => pch}/iobp.c (100%) rename src/soc/intel/broadwell/{ => pch}/lpc.c (100%) rename src/soc/intel/broadwell/{ => pch}/me.c (100%) rename src/soc/intel/broadwell/{ => pch}/me_status.c (100%) rename src/soc/intel/broadwell/{ => pch}/pch.c (100%) rename src/soc/intel/broadwell/{ => pch}/pcie.c (100%) rename src/soc/intel/broadwell/{ => pch}/pmutil.c (100%) rename src/soc/intel/broadwell/{romstage => pch}/power_state.c (100%) rename src/soc/intel/broadwell/{ => pch}/sata.c (100%) rename src/soc/intel/broadwell/{ => pch}/serialio.c (100%) rename src/soc/intel/broadwell/{ => pch}/smbus.c (100%) rename src/soc/intel/broadwell/{ => pch}/smi.c (100%) rename src/soc/intel/broadwell/{ => pch}/smihandler.c (100%) rename src/soc/intel/broadwell/{romstage => pch}/uart.c (100%) rename src/soc/intel/broadwell/{ => pch}/usb_debug.c (100%) rename src/soc/intel/broadwell/{ => pch}/xhci.c (100%) diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index e24b949fb5..75ef33fa02 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -9,52 +9,28 @@ subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common +subdirs-y += pch + bootblock-y += bootblock/cpu.c -bootblock-y += bootblock/pch.c bootblock-y += bootblock/systemagent.c bootblock-y += ../../../cpu/intel/car/bootblock.c bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S bootblock-y += ../../../cpu/x86/early_reset.S ramstage-y += acpi.c -ramstage-y += adsp.c ramstage-y += cpu.c ramstage-y += cpu_info.c smm-y += cpu_info.c -ramstage-$(CONFIG_ELOG) += elog.c ramstage-y += finalize.c -ramstage-y += gpio.c -romstage-y += gpio.c -smm-y += gpio.c -ramstage-y += hda.c ramstage-y += gma.c -ramstage-y += iobp.c -romstage-y += iobp.c -ramstage-y += fadt.c -ramstage-y += lpc.c -ramstage-y += me.c -ramstage-y += me_status.c -romstage-y += me_status.c ramstage-y += memmap.c romstage-y += memmap.c postcar-y += memmap.c ramstage-y += minihd.c -ramstage-y += pch.c -romstage-y += pch.c -ramstage-y += pcie.c ramstage-y += pei_data.c romstage-y += pei_data.c -ramstage-y += pmutil.c -romstage-y += pmutil.c -smm-y += pmutil.c -verstage-y += pmutil.c ramstage-y += ramstage.c ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c -ramstage-y += sata.c -ramstage-y += serialio.c -ramstage-y += smbus.c -ramstage-y += smi.c -smm-y += smihandler.c ramstage-y += smmrelocate.c ramstage-y += systemagent.c bootblock-y += tsc_freq.c @@ -63,17 +39,9 @@ romstage-y += tsc_freq.c smm-y += tsc_freq.c postcar-y += tsc_freq.c verstage-y += tsc_freq.c -bootblock-y += usb_debug.c -romstage-y += usb_debug.c -ramstage-y += usb_debug.c -ramstage-y += ehci.c -ramstage-y += xhci.c -smm-y += xhci.c postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c - cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin CPPFLAGS_common += -Isrc/soc/intel/broadwell/include diff --git a/src/soc/intel/broadwell/pch/Makefile.inc b/src/soc/intel/broadwell/pch/Makefile.inc new file mode 100644 index 0000000000..7e5c65aa76 --- /dev/null +++ b/src/soc/intel/broadwell/pch/Makefile.inc @@ -0,0 +1,38 @@ +bootblock-y += bootblock.c + +ramstage-y += adsp.c +romstage-y += early_pch.c +ramstage-$(CONFIG_ELOG) += elog.c +ramstage-y += gpio.c +romstage-y += gpio.c +smm-y += gpio.c +ramstage-y += hda.c +ramstage-y += iobp.c +romstage-y += iobp.c +ramstage-y += fadt.c +ramstage-y += lpc.c +ramstage-y += me.c +ramstage-y += me_status.c +romstage-y += me_status.c +ramstage-y += pch.c +romstage-y += pch.c +ramstage-y += pcie.c +ramstage-y += pmutil.c +romstage-y += pmutil.c +smm-y += pmutil.c +verstage-y += pmutil.c +romstage-y += power_state.c +ramstage-y += sata.c +ramstage-y += serialio.c +ramstage-y += smbus.c +ramstage-y += smi.c +smm-y += smihandler.c +romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c +bootblock-y += usb_debug.c +romstage-y += usb_debug.c +ramstage-y += usb_debug.c +ramstage-y += ehci.c +ramstage-y += xhci.c +smm-y += xhci.c + +ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/pch/adsp.c similarity index 100% rename from src/soc/intel/broadwell/adsp.c rename to src/soc/intel/broadwell/pch/adsp.c diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/pch/bootblock.c similarity index 100% rename from src/soc/intel/broadwell/bootblock/pch.c rename to src/soc/intel/broadwell/pch/bootblock.c diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/pch/early_pch.c similarity index 100% rename from src/soc/intel/broadwell/romstage/pch.c rename to src/soc/intel/broadwell/pch/early_pch.c diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/pch/ehci.c similarity index 100% rename from src/soc/intel/broadwell/ehci.c rename to src/soc/intel/broadwell/pch/ehci.c diff --git a/src/soc/intel/broadwell/elog.c b/src/soc/intel/broadwell/pch/elog.c similarity index 100% rename from src/soc/intel/broadwell/elog.c rename to src/soc/intel/broadwell/pch/elog.c diff --git a/src/soc/intel/broadwell/fadt.c b/src/soc/intel/broadwell/pch/fadt.c similarity index 100% rename from src/soc/intel/broadwell/fadt.c rename to src/soc/intel/broadwell/pch/fadt.c diff --git a/src/soc/intel/broadwell/gpio.c b/src/soc/intel/broadwell/pch/gpio.c similarity index 100% rename from src/soc/intel/broadwell/gpio.c rename to src/soc/intel/broadwell/pch/gpio.c diff --git a/src/soc/intel/broadwell/hda.c b/src/soc/intel/broadwell/pch/hda.c similarity index 100% rename from src/soc/intel/broadwell/hda.c rename to src/soc/intel/broadwell/pch/hda.c diff --git a/src/soc/intel/broadwell/iobp.c b/src/soc/intel/broadwell/pch/iobp.c similarity index 100% rename from src/soc/intel/broadwell/iobp.c rename to src/soc/intel/broadwell/pch/iobp.c diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/pch/lpc.c similarity index 100% rename from src/soc/intel/broadwell/lpc.c rename to src/soc/intel/broadwell/pch/lpc.c diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/pch/me.c similarity index 100% rename from src/soc/intel/broadwell/me.c rename to src/soc/intel/broadwell/pch/me.c diff --git a/src/soc/intel/broadwell/me_status.c b/src/soc/intel/broadwell/pch/me_status.c similarity index 100% rename from src/soc/intel/broadwell/me_status.c rename to src/soc/intel/broadwell/pch/me_status.c diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch/pch.c similarity index 100% rename from src/soc/intel/broadwell/pch.c rename to src/soc/intel/broadwell/pch/pch.c diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pch/pcie.c similarity index 100% rename from src/soc/intel/broadwell/pcie.c rename to src/soc/intel/broadwell/pch/pcie.c diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pch/pmutil.c similarity index 100% rename from src/soc/intel/broadwell/pmutil.c rename to src/soc/intel/broadwell/pch/pmutil.c diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/pch/power_state.c similarity index 100% rename from src/soc/intel/broadwell/romstage/power_state.c rename to src/soc/intel/broadwell/pch/power_state.c diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/pch/sata.c similarity index 100% rename from src/soc/intel/broadwell/sata.c rename to src/soc/intel/broadwell/pch/sata.c diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/pch/serialio.c similarity index 100% rename from src/soc/intel/broadwell/serialio.c rename to src/soc/intel/broadwell/pch/serialio.c diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/pch/smbus.c similarity index 100% rename from src/soc/intel/broadwell/smbus.c rename to src/soc/intel/broadwell/pch/smbus.c diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/pch/smi.c similarity index 100% rename from src/soc/intel/broadwell/smi.c rename to src/soc/intel/broadwell/pch/smi.c diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/pch/smihandler.c similarity index 100% rename from src/soc/intel/broadwell/smihandler.c rename to src/soc/intel/broadwell/pch/smihandler.c diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/pch/uart.c similarity index 100% rename from src/soc/intel/broadwell/romstage/uart.c rename to src/soc/intel/broadwell/pch/uart.c diff --git a/src/soc/intel/broadwell/usb_debug.c b/src/soc/intel/broadwell/pch/usb_debug.c similarity index 100% rename from src/soc/intel/broadwell/usb_debug.c rename to src/soc/intel/broadwell/pch/usb_debug.c diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/pch/xhci.c similarity index 100% rename from src/soc/intel/broadwell/xhci.c rename to src/soc/intel/broadwell/pch/xhci.c diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc index edfec30fdc..b77e7a579d 100644 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ b/src/soc/intel/broadwell/romstage/Makefile.inc @@ -1,9 +1,6 @@ romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += cpu.c -romstage-y += pch.c -romstage-y += power_state.c romstage-y += raminit.c romstage-y += report_platform.c romstage-y += romstage.c romstage-y += systemagent.c -romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c From 37164ff60927ad965915af28f593c491a7623908 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 21:56:17 +0200 Subject: [PATCH 027/129] soc/intel/broadwell: Inline CPUID helpers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These functions are small and used in various stages. Inline them. Change-Id: I0d15012f264dbb0ae2eff8210f79176b350b6e7f Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46707 Reviewed-by: Arthur Heymans Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/cpu_info.c | 10 ---------- src/soc/intel/broadwell/include/soc/cpu.h | 14 ++++++++++++-- src/soc/intel/broadwell/romstage/cpu.c | 5 ----- 3 files changed, 12 insertions(+), 17 deletions(-) diff --git a/src/soc/intel/broadwell/cpu_info.c b/src/soc/intel/broadwell/cpu_info.c index 506b1a7985..8814a480e5 100644 --- a/src/soc/intel/broadwell/cpu_info.c +++ b/src/soc/intel/broadwell/cpu_info.c @@ -5,16 +5,6 @@ #include #include -u32 cpu_family_model(void) -{ - return cpuid_eax(1) & 0x0fff0ff0; -} - -u32 cpu_stepping(void) -{ - return cpuid_eax(1) & 0xf; -} - /* Dynamically determine if the part is ULT. */ int cpu_is_ult(void) { diff --git a/src/soc/intel/broadwell/include/soc/cpu.h b/src/soc/intel/broadwell/include/soc/cpu.h index 02605851ce..b8ef761e38 100644 --- a/src/soc/intel/broadwell/include/soc/cpu.h +++ b/src/soc/intel/broadwell/include/soc/cpu.h @@ -3,7 +3,9 @@ #ifndef _BROADWELL_CPU_H_ #define _BROADWELL_CPU_H_ +#include #include +#include /* CPU types */ #define HASWELL_FAMILY_ULT 0x40650 @@ -42,8 +44,16 @@ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); /* CPU identification */ -u32 cpu_family_model(void); -u32 cpu_stepping(void); +static inline u32 cpu_family_model(void) +{ + return cpuid_eax(1) & 0x0fff0ff0; +} + +static inline u32 cpu_stepping(void) +{ + return cpuid_eax(1) & 0xf; +} + int cpu_is_ult(void); #endif diff --git a/src/soc/intel/broadwell/romstage/cpu.c b/src/soc/intel/broadwell/romstage/cpu.c index 736487697d..c9f70a85d1 100644 --- a/src/soc/intel/broadwell/romstage/cpu.c +++ b/src/soc/intel/broadwell/romstage/cpu.c @@ -7,11 +7,6 @@ #include #include -u32 cpu_family_model(void) -{ - return cpuid_eax(1) & 0x0fff0ff0; -} - void set_max_freq(void) { msr_t msr, perf_ctl, platform_info; From 9eaca7dcf42c173645627e5523e5d8d6b7b74b76 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 22:01:44 +0200 Subject: [PATCH 028/129] soc/intel/broadwell: Get rid of `cpu_is_ult` It is only used in a single file, on two functions that already check whether coreboot is running on a Haswell or a Broadwell processor. Change-Id: I86e1061f722e6d6855190c2fd863d85fc24a1ee0 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46708 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/Makefile.inc | 2 -- src/soc/intel/broadwell/cpu_info.c | 22 ---------------------- src/soc/intel/broadwell/gma.c | 6 ++++-- src/soc/intel/broadwell/include/soc/cpu.h | 2 -- 4 files changed, 4 insertions(+), 28 deletions(-) delete mode 100644 src/soc/intel/broadwell/cpu_info.c diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 75ef33fa02..ce1dd9cbf6 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -19,8 +19,6 @@ bootblock-y += ../../../cpu/x86/early_reset.S ramstage-y += acpi.c ramstage-y += cpu.c -ramstage-y += cpu_info.c -smm-y += cpu_info.c ramstage-y += finalize.c ramstage-y += gma.c ramstage-y += memmap.c diff --git a/src/soc/intel/broadwell/cpu_info.c b/src/soc/intel/broadwell/cpu_info.c deleted file mode 100644 index 8814a480e5..0000000000 --- a/src/soc/intel/broadwell/cpu_info.c +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include - -/* Dynamically determine if the part is ULT. */ -int cpu_is_ult(void) -{ - static int ult = -1; - - if (ult < 0) { - u32 fm = cpu_family_model(); - if (fm == BROADWELL_FAMILY_ULT || fm == HASWELL_FAMILY_ULT) - ult = 1; - else - ult = 0; - } - - return ult; -} diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index c77f5c4476..3889be3513 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -364,6 +364,7 @@ static int igd_get_cdclk_haswell(u32 *const cdsel, int *const inform_pc, /* Check for ULX GT1 or GT2 */ const int devid = pci_read_config16(dev, PCI_DEVICE_ID); + const int cpu_is_ult = cpu_family_model() == HASWELL_FAMILY_ULT; const int gpu_is_ulx = devid == IGD_HASWELL_ULX_GT1 || devid == IGD_HASWELL_ULX_GT2; @@ -378,7 +379,7 @@ static int igd_get_cdclk_haswell(u32 *const cdsel, int *const inform_pc, */ if (gpu_is_ulx && cdclk <= GT_CDCLK_337) cdclk = GT_CDCLK_337; - else if (gpu_is_ulx || cpu_is_ult() || + else if (gpu_is_ulx || cpu_is_ult || cdclk == GT_CDCLK_337 || cdclk == GT_CDCLK_450) cdclk = GT_CDCLK_450; else @@ -398,6 +399,7 @@ static int igd_get_cdclk_broadwell(u32 *const cdsel, int *const inform_pc, /* Check for ULX */ const int devid = pci_read_config16(dev, PCI_DEVICE_ID); + const int cpu_is_ult = cpu_family_model() == BROADWELL_FAMILY_ULT; const int gpu_is_ulx = devid == IGD_BROADWELL_Y_GT2; /* Inform power controller of upcoming frequency change */ @@ -428,7 +430,7 @@ static int igd_get_cdclk_broadwell(u32 *const cdsel, int *const inform_pc, (gpu_is_ulx && cdclk == GT_CDCLK_DEFAULT)) cdclk = GT_CDCLK_450; else if (cdclk == GT_CDCLK_540 || gpu_is_ulx || - (cpu_is_ult() && cdclk == GT_CDCLK_DEFAULT)) + (cpu_is_ult && cdclk == GT_CDCLK_DEFAULT)) cdclk = GT_CDCLK_540; else cdclk = GT_CDCLK_675; diff --git a/src/soc/intel/broadwell/include/soc/cpu.h b/src/soc/intel/broadwell/include/soc/cpu.h index b8ef761e38..bc5d2d76bd 100644 --- a/src/soc/intel/broadwell/include/soc/cpu.h +++ b/src/soc/intel/broadwell/include/soc/cpu.h @@ -54,6 +54,4 @@ static inline u32 cpu_stepping(void) return cpuid_eax(1) & 0xf; } -int cpu_is_ult(void); - #endif From 071754c9dc8b68ef63481688a787be3d8bc17bf2 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 22:35:41 +0200 Subject: [PATCH 029/129] soc/intel/broadwell: Relocate PCH finalisation code Change-Id: I94a4194e935fddb99645ed2929bdd70583c2fd5b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46709 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/finalize.c | 45 +------------------- src/soc/intel/broadwell/include/soc/pch.h | 2 + src/soc/intel/broadwell/pch/Makefile.inc | 1 + src/soc/intel/broadwell/pch/finalize.c | 51 +++++++++++++++++++++++ 4 files changed, 56 insertions(+), 43 deletions(-) create mode 100644 src/soc/intel/broadwell/pch/finalize.c diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 4196144369..3dafc9defd 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -4,15 +4,9 @@ #include #include #include -#include -#include #include -#include -#include -#include -#include +#include #include -#include /* * 16.6 System Agent Configuration Locking @@ -55,48 +49,13 @@ static void broadwell_systemagent_finalize(void) MCHBAR32(0x6008) = MCHBAR32(0x6008); } -const struct reg_script pch_finalize_script[] = { -#if !CONFIG(EM100PRO_SPI_CONSOLE) - /* Lock SPIBAR */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS, - SPIBAR_HSFS_FLOCKDN), -#endif - - /* TC Lockdown */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0050, (1 << 31)), - - /* BIOS Interface Lockdown */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 0)), - - /* Function Disable SUS Well Lockdown */ - REG_MMIO_OR8(RCBA_BASE_ADDRESS + FDSW, (1 << 7)), - - /* Global SMI Lock */ - REG_PCI_OR16(GEN_PMCON_1, SMI_LOCK), - - /* GEN_PMCON Lock */ - REG_PCI_OR8(GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK), - - /* PMSYNC */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + PMSYNC_CONFIG, (1 << 31)), - - REG_SCRIPT_END -}; - static void broadwell_finalize(void *unused) { printk(BIOS_DEBUG, "Finalizing chipset.\n"); broadwell_systemagent_finalize(); - spi_finalize_ops(); - reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script); - - /* Lock */ - RCBA32_OR(0x3a6c, 0x00000001); - - /* Read+Write this R/WO register */ - RCBA32(LCAP) = RCBA32(LCAP); + broadwell_pch_finalize(); /* Indicate finalize step with post code */ post_code(POST_OS_BOOT); diff --git a/src/soc/intel/broadwell/include/soc/pch.h b/src/soc/intel/broadwell/include/soc/pch.h index 59b5b18f17..cf27499fe5 100644 --- a/src/soc/intel/broadwell/include/soc/pch.h +++ b/src/soc/intel/broadwell/include/soc/pch.h @@ -30,4 +30,6 @@ int pch_is_wpt_ulx(void); u32 pch_read_soft_strap(int id); void pch_disable_devfn(struct device *dev); +void broadwell_pch_finalize(void); + #endif diff --git a/src/soc/intel/broadwell/pch/Makefile.inc b/src/soc/intel/broadwell/pch/Makefile.inc index 7e5c65aa76..1c196136c4 100644 --- a/src/soc/intel/broadwell/pch/Makefile.inc +++ b/src/soc/intel/broadwell/pch/Makefile.inc @@ -3,6 +3,7 @@ bootblock-y += bootblock.c ramstage-y += adsp.c romstage-y += early_pch.c ramstage-$(CONFIG_ELOG) += elog.c +ramstage-y += finalize.c ramstage-y += gpio.c romstage-y += gpio.c smm-y += gpio.c diff --git a/src/soc/intel/broadwell/pch/finalize.c b/src/soc/intel/broadwell/pch/finalize.c new file mode 100644 index 0000000000..37afded317 --- /dev/null +++ b/src/soc/intel/broadwell/pch/finalize.c @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +const struct reg_script pch_finalize_script[] = { +#if !CONFIG(EM100PRO_SPI_CONSOLE) + /* Lock SPIBAR */ + REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS, + SPIBAR_HSFS_FLOCKDN), +#endif + + /* TC Lockdown */ + REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0050, (1 << 31)), + + /* BIOS Interface Lockdown */ + REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 0)), + + /* Function Disable SUS Well Lockdown */ + REG_MMIO_OR8(RCBA_BASE_ADDRESS + FDSW, (1 << 7)), + + /* Global SMI Lock */ + REG_PCI_OR16(GEN_PMCON_1, SMI_LOCK), + + /* GEN_PMCON Lock */ + REG_PCI_OR8(GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK), + + /* PMSYNC */ + REG_MMIO_OR32(RCBA_BASE_ADDRESS + PMSYNC_CONFIG, (1 << 31)), + + REG_SCRIPT_END +}; + +void broadwell_pch_finalize(void) +{ + spi_finalize_ops(); + reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script); + + /* Lock */ + RCBA32_OR(0x3a6c, 0x00000001); + + /* Read+Write this R/WO register */ + RCBA32(LCAP) = RCBA32(LCAP); +} From c3a6d4b2c70472a952db1187e5555ea6a8558ad6 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 22:40:33 +0200 Subject: [PATCH 030/129] soc/intel/broadwell: Drop reg-script to finalize PCH Tested on out-of-tree Acer Aspire E5-573, still boots. Change-Id: I3b9ae75842e3ec1ecd02323d104a9f1d45564172 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46710 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/pch/finalize.c | 52 +++++++++++--------------- 1 file changed, 22 insertions(+), 30 deletions(-) diff --git a/src/soc/intel/broadwell/pch/finalize.c b/src/soc/intel/broadwell/pch/finalize.c index 37afded317..71f06390e0 100644 --- a/src/soc/intel/broadwell/pch/finalize.c +++ b/src/soc/intel/broadwell/pch/finalize.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include @@ -10,38 +9,31 @@ #include #include -const struct reg_script pch_finalize_script[] = { -#if !CONFIG(EM100PRO_SPI_CONSOLE) - /* Lock SPIBAR */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS, - SPIBAR_HSFS_FLOCKDN), -#endif - - /* TC Lockdown */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0050, (1 << 31)), - - /* BIOS Interface Lockdown */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 0)), - - /* Function Disable SUS Well Lockdown */ - REG_MMIO_OR8(RCBA_BASE_ADDRESS + FDSW, (1 << 7)), - - /* Global SMI Lock */ - REG_PCI_OR16(GEN_PMCON_1, SMI_LOCK), - - /* GEN_PMCON Lock */ - REG_PCI_OR8(GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK), - - /* PMSYNC */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + PMSYNC_CONFIG, (1 << 31)), - - REG_SCRIPT_END -}; - void broadwell_pch_finalize(void) { spi_finalize_ops(); - reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script); + + /* Lock SPIBAR */ + if (!CONFIG(EM100PRO_SPI_CONSOLE)) + RCBA32_OR(SPIBAR_OFFSET + SPIBAR_HSFS, SPIBAR_HSFS_FLOCKDN); + + /* TC Lockdown */ + RCBA32_OR(0x0050, 1 << 31); + + /* BIOS Interface Lockdown */ + RCBA32_OR(GCS, 1 << 0); + + /* Function Disable SUS Well Lockdown */ + RCBA8(FDSW) |= 1 << 7; + + /* Global SMI Lock */ + pci_or_config16(PCH_DEV_LPC, GEN_PMCON_1, SMI_LOCK); + + /* GEN_PMCON Lock */ + pci_or_config8(PCH_DEV_LPC, GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK); + + /* PMSYNC */ + RCBA32_OR(PMSYNC_CONFIG, 1 << 31); /* Lock */ RCBA32_OR(0x3a6c, 0x00000001); From 33b0f15434a40527e1e5278a63e91465ef4c7617 Mon Sep 17 00:00:00 2001 From: Anil Kumar Date: Mon, 12 Oct 2020 11:39:15 -0700 Subject: [PATCH 031/129] drivers/soundwire/alc711: Add Realtek ALC711 soundwire device Bug=None Test=Enabled the device on TGLY RVP and tested that the codec is reflected in SSDT. Checked sound card binding works and soundwire drivers are enabled in kernel. Signed-off-by: Anil Kumar Change-Id: Ia7358927fe8531e609ebe070bef259a2bbc09093 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46303 Tested-by: build bot (Jenkins) Reviewed-by: Sathyanarayana Nujella Reviewed-by: Duncan Laurie --- src/drivers/soundwire/alc711/Kconfig | 2 + src/drivers/soundwire/alc711/Makefile.inc | 1 + src/drivers/soundwire/alc711/alc711.c | 156 ++++++++++++++++++++++ src/drivers/soundwire/alc711/chip.h | 11 ++ src/include/device/mipi_ids.h | 1 + 5 files changed, 171 insertions(+) create mode 100644 src/drivers/soundwire/alc711/Kconfig create mode 100644 src/drivers/soundwire/alc711/Makefile.inc create mode 100644 src/drivers/soundwire/alc711/alc711.c create mode 100644 src/drivers/soundwire/alc711/chip.h diff --git a/src/drivers/soundwire/alc711/Kconfig b/src/drivers/soundwire/alc711/Kconfig new file mode 100644 index 0000000000..bdc02a9324 --- /dev/null +++ b/src/drivers/soundwire/alc711/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_SOUNDWIRE_ALC711 + bool diff --git a/src/drivers/soundwire/alc711/Makefile.inc b/src/drivers/soundwire/alc711/Makefile.inc new file mode 100644 index 0000000000..78e4d1b7fe --- /dev/null +++ b/src/drivers/soundwire/alc711/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_SOUNDWIRE_ALC711) += alc711.c diff --git a/src/drivers/soundwire/alc711/alc711.c b/src/drivers/soundwire/alc711/alc711.c new file mode 100644 index 0000000000..8382fc94fb --- /dev/null +++ b/src/drivers/soundwire/alc711/alc711.c @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" + +static struct soundwire_address alc711_address = { + .version = SOUNDWIRE_VERSION_1_1, + .manufacturer_id = MIPI_MFG_ID_REALTEK, + .part_id = MIPI_DEV_ID_REALTEK_ALC711, + .class = MIPI_CLASS_NONE +}; + +static struct soundwire_slave alc711_slave = { + .wake_up_unavailable = false, + .test_mode_supported = false, + .clock_stop_mode1_supported = true, + .simplified_clockstopprepare_sm_supported = true, + .clockstopprepare_hard_reset_behavior = false, + .highPHY_capable = false, + .paging_supported = false, + .bank_delay_supported = false, + .port15_read_behavior = false, + .source_port_list = SOUNDWIRE_PORT(2), + .sink_port_list = SOUNDWIRE_PORT(1), +}; + +static struct soundwire_audio_mode alc711_audio_mode = { + /* Bus frequency must be 1/2/4/8 divider of supported input frequencies. */ + .bus_frequency_configs_count = 12, + .bus_frequency_configs = { + 9600 * KHz, + 4800 * KHz, + 2400 * KHz, + 1200 * KHz, + 12000 * KHz, + 6000 * KHz, + 3000 * KHz, + 1500 * KHz, + 12288 * KHz, + 6144 * KHz, + 3072 * KHz, + 1536 * KHz + }, + /* Support 16 KHz to 192 KHz sampling frequency */ + .sampling_frequency_configs_count = 9, + .sampling_frequency_configs = { + 16 * KHz, + 22.05 * KHz, + 24 * KHz, + 32 * KHz, + 44.1 * KHz, + 48 * KHz, + 88.2 * KHz, + 96 * KHz, + 192 * KHz + }, + .prepare_channel_behavior = CHANNEL_PREPARE_ANY_FREQUENCY +}; + +static struct soundwire_dpn alc711_dp = { + .port_wordlength_configs_count = 1, + .port_wordlength_configs = { 32 }, + .data_port_type = FULL_DATA_PORT, + .max_grouping_supported = BLOCK_GROUP_COUNT_1, + .simplified_channelprepare_sm = false, + .imp_def_dpn_interrupts_supported = 0, + .min_channel_number = 1, + .max_channel_number = 2, + .modes_supported = MODE_ISOCHRONOUS | MODE_TX_CONTROLLED | + MODE_RX_CONTROLLED | MODE_FULL_ASYNCHRONOUS, + .block_packing_mode = true, + .port_audio_mode_count = 1, + .port_audio_mode_list = { 0 } +}; + +static const struct soundwire_codec alc711_codec = { + .slave = &alc711_slave, + .audio_mode = { &alc711_audio_mode }, + .dpn = { + { + /* Data Input for Speaker Path */ + .port = 1, + .sink = &alc711_dp + }, + { + /* Data Output for DSP Path */ + .port = 2, + .source = &alc711_dp + } + } + +}; + +static void soundwire_alc711_fill_ssdt(const struct device *dev) +{ + struct drivers_soundwire_alc711_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_dp *dsd; + + if (!dev->enabled || !scope) + return; + + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + + /* Set codec address IDs. */ + alc711_address.link_id = dev->path.generic.id; + alc711_address.unique_id = dev->path.generic.subid; + + acpigen_write_ADR_soundwire_device(&alc711_address); + acpigen_write_name_string("_DDN", config->desc ? : dev->chip_ops->name); + acpigen_write_STA(acpi_device_status(dev)); + + dsd = acpi_dp_new_table("_DSD"); + soundwire_gen_codec(dsd, &alc711_codec, NULL); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static const char *soundwire_alc711_acpi_name(const struct device *dev) +{ + struct drivers_soundwire_alc711_config *config = dev->chip_info; + static char name[5]; + + if (config->name) + return config->name; + snprintf(name, sizeof(name), "SW%1X%1X", dev->path.generic.id, dev->path.generic.subid); + return name; +} + +static struct device_operations soundwire_alc711_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = soundwire_alc711_acpi_name, + .acpi_fill_ssdt = soundwire_alc711_fill_ssdt, +}; + +static void soundwire_alc711_enable(struct device *dev) +{ + dev->ops = &soundwire_alc711_ops; +} + +struct chip_operations drivers_soundwire_alc711_ops = { + CHIP_NAME("Realtek ALC711 SoundWire Codec") + .enable_dev = soundwire_alc711_enable +}; diff --git a/src/drivers/soundwire/alc711/chip.h b/src/drivers/soundwire/alc711/chip.h new file mode 100644 index 0000000000..6d317fddfe --- /dev/null +++ b/src/drivers/soundwire/alc711/chip.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_SOUNDWIRE_ALC711_CHIP_H__ +#define __DRIVERS_SOUNDWIRE_ALC711_CHIP_H__ + +struct drivers_soundwire_alc711_config { + const char *name; + const char *desc; +}; + +#endif /* __DRIVERS_SOUNDWIRE_ALC711_CHIP_H__ */ diff --git a/src/include/device/mipi_ids.h b/src/include/device/mipi_ids.h index 86b5116005..951caaacaa 100644 --- a/src/include/device/mipi_ids.h +++ b/src/include/device/mipi_ids.h @@ -20,6 +20,7 @@ /* Contributing Members */ #define MIPI_MFG_ID_REALTEK 0x025d #define MIPI_DEV_ID_REALTEK_ALC5682 0x5682 +#define MIPI_DEV_ID_REALTEK_ALC711 0x0711 #define MIPI_MFG_ID_MAXIM 0x019f #define MIPI_DEV_ID_MAXIM_MAX98373 0x8373 From 6065f616ebf4c11ed2c5ad01f8f41d5ba49c272d Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 28 Oct 2020 11:30:54 +0100 Subject: [PATCH 032/129] .gitignore: Split into subdirectory files There's no need for the global list of files to ignore, so use git's ability to work with more local configuration. Change-Id: I50882e6756cbc0fdfd899353cc23962544690fb3 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/46879 Reviewed-by: Angel Pons Reviewed-by: Felix Held Reviewed-by: Stefan Reinauer Reviewed-by: Christian Walter Tested-by: build bot (Jenkins) --- .gitignore | 99 ++-------------------------------- Documentation/.gitignore | 7 +++ payloads/coreinfo/.gitignore | 2 + payloads/external/.gitignore | 10 ++++ payloads/libpayload/.gitignore | 1 + payloads/nvramcui/.gitignore | 2 + util/amdfwtool/.gitignore | 3 ++ util/archive/.gitignore | 3 ++ util/autoport/.gitignore | 3 ++ util/bincfg/.gitignore | 3 ++ util/board_status/.gitignore | 1 + util/bucts/.gitignore | 3 ++ util/cbfstool/.gitignore | 7 +++ util/cbmem/.gitignore | 3 ++ util/crossgcc/.gitignore | 28 ++++++++++ util/ectool/.gitignore | 3 ++ util/futility/.gitignore | 3 ++ util/genprof/.gitignore | 3 ++ util/ifdtool/.gitignore | 3 ++ util/intelmetool/.gitignore | 3 ++ util/intelp2m/.gitignore | 4 ++ util/inteltool/.gitignore | 3 ++ util/intelvbttool/.gitignore | 3 ++ util/kbc1126/.gitignore | 4 ++ util/msrtool/.gitignore | 5 ++ util/nvramtool/.gitignore | 3 ++ util/pmh7tool/.gitignore | 3 ++ util/spd_tools/.gitignore | 4 ++ util/superiotool/.gitignore | 3 ++ util/vgabios/.gitignore | 3 ++ 30 files changed, 129 insertions(+), 96 deletions(-) create mode 100644 Documentation/.gitignore create mode 100644 payloads/coreinfo/.gitignore create mode 100644 payloads/external/.gitignore create mode 100644 payloads/libpayload/.gitignore create mode 100644 payloads/nvramcui/.gitignore create mode 100644 util/amdfwtool/.gitignore create mode 100644 util/archive/.gitignore create mode 100644 util/autoport/.gitignore create mode 100644 util/bincfg/.gitignore create mode 100644 util/board_status/.gitignore create mode 100644 util/bucts/.gitignore create mode 100644 util/cbfstool/.gitignore create mode 100644 util/cbmem/.gitignore create mode 100644 util/crossgcc/.gitignore create mode 100644 util/ectool/.gitignore create mode 100644 util/futility/.gitignore create mode 100644 util/genprof/.gitignore create mode 100644 util/ifdtool/.gitignore create mode 100644 util/intelmetool/.gitignore create mode 100644 util/intelp2m/.gitignore create mode 100644 util/inteltool/.gitignore create mode 100644 util/intelvbttool/.gitignore create mode 100644 util/kbc1126/.gitignore create mode 100644 util/msrtool/.gitignore create mode 100644 util/nvramtool/.gitignore create mode 100644 util/pmh7tool/.gitignore create mode 100644 util/spd_tools/.gitignore create mode 100644 util/superiotool/.gitignore create mode 100644 util/vgabios/.gitignore diff --git a/.gitignore b/.gitignore index 97cc9ce95d..a60777212d 100644 --- a/.gitignore +++ b/.gitignore @@ -1,6 +1,3 @@ -payloads/libpayload/install/ -payloads/nvramcui/build -payloads/nvramcui/libpayload junit.xml abuild*.xml .config @@ -11,46 +8,8 @@ defconfig .ccwrap build/ coreboot-builds/ -payloads/coreinfo/lpbuild/ -payloads/coreinfo/lp.config* -payloads/external/depthcharge/depthcharge/ -payloads/external/FILO/filo/ -payloads/external/GRUB2/grub2/ -payloads/external/LinuxBoot/linuxboot/ -payloads/external/SeaBIOS/seabios/ -payloads/external/tianocore/tianocore/ -payloads/external/tint/tint/ -payloads/external/U-Boot/u-boot/ -payloads/external/Memtest86Plus/memtest86plus/ -payloads/external/iPXE/ipxe/ -util/crossgcc/acpica-unix-*/ -util/crossgcc/binutils-*/ -util/crossgcc/build-*BINUTILS/ -util/crossgcc/build-*EXPAT/ -util/crossgcc/build-*GCC/ -util/crossgcc/build-*GDB/ -util/crossgcc/build-*GMP/ -util/crossgcc/build-*LIBELF/ -util/crossgcc/build-*MPC/ -util/crossgcc/build-*MPFR/ -util/crossgcc/build-*PYTHON/ -util/crossgcc/build-*LVM/ -util/crossgcc/build-*IASL/ -util/crossgcc/expat-*/ -util/crossgcc/gcc-*/ -util/crossgcc/gdb-*/ -util/crossgcc/gmp-*/ -util/crossgcc/libelf-*/ -util/crossgcc/mingwrt-*/ -util/crossgcc/mpc-*/ -util/crossgcc/mpfr-*/ -util/crossgcc/Python-*/ -util/crossgcc/*.src/ -util/crossgcc/tarballs/ -util/crossgcc/w32api-*/ -util/crossgcc/xgcc/ -util/crossgcc/xgcc-*/ -util/crossgcc/xgcc +coreboot-builds*/ + site-local *.\# @@ -66,7 +25,6 @@ site-local *.pyc *.sw[po] /*.rom -coreboot-builds*/ # Development friendly files tags @@ -76,60 +34,9 @@ tags xgcc/ tarballs/ -# -# KDE editors create lots of backup files whenever -# a file is edited, so just ignore them +# editor backup files, temporary files, IDE project files *~ *.kate-swp -# Ignore Kdevelop project file *.kdev4 -util/*/.dependencies -util/*/.test -util/amdfwtool/amdfwtool -util/archive/archive -util/bincfg/bincfg -util/board_status/board-status -util/bucts/bucts -util/cbfstool/cbfs-compression-tool -util/cbfstool/cbfstool -util/cbfstool/fmaptool -util/cbfstool/ifwitool -util/cbfstool/rmodtool -util/cbmem/.dependencies -util/cbmem/cbmem -util/ectool/ectool -util/futility/futility -util/genprof/genprof -util/getpir/getpir -util/ifdtool/ifdtool -util/intelmetool/intelmetool -util/inteltool/.dependencies -util/inteltool/inteltool -util/intelp2m/intelp2m -util/intelp2m/generate/gpio.h -util/intelvbttool/intelvbttool -util/msrtool/Makefile -util/msrtool/Makefile.deps -util/msrtool/msrtool -util/nvramtool/.dependencies -util/nvramtool/nvramtool -util/pmh7tool/pmh7tool -util/runfw/googlesnow -util/superiotool/superiotool -util/vgabios/testbios -util/autoport/autoport -util/kbc1126/kbc1126_ec_dump -util/kbc1126/kbc1126_ec_insert -util/spd_tools/*/gen_spd -util/spd_tools/*/gen_part_id - -Documentation/*.aux -Documentation/*.idx -Documentation/*.log -Documentation/*.toc -Documentation/*.out -Documentation/*.pdf -Documentation/_build - doxygen/* diff --git a/Documentation/.gitignore b/Documentation/.gitignore new file mode 100644 index 0000000000..a8f5d5f6fa --- /dev/null +++ b/Documentation/.gitignore @@ -0,0 +1,7 @@ +*.aux +*.idx +*.log +*.toc +*.out +*.pdf +_build diff --git a/payloads/coreinfo/.gitignore b/payloads/coreinfo/.gitignore new file mode 100644 index 0000000000..101045e012 --- /dev/null +++ b/payloads/coreinfo/.gitignore @@ -0,0 +1,2 @@ +lpbuild/ +lp.config* diff --git a/payloads/external/.gitignore b/payloads/external/.gitignore new file mode 100644 index 0000000000..ebca42908b --- /dev/null +++ b/payloads/external/.gitignore @@ -0,0 +1,10 @@ +depthcharge/depthcharge/ +FILO/filo/ +GRUB2/grub2/ +LinuxBoot/linuxboot/ +SeaBIOS/seabios/ +tianocore/tianocore/ +tint/tint/ +U-Boot/u-boot/ +Memtest86Plus/memtest86plus/ +iPXE/ipxe/ diff --git a/payloads/libpayload/.gitignore b/payloads/libpayload/.gitignore new file mode 100644 index 0000000000..c7b20fc357 --- /dev/null +++ b/payloads/libpayload/.gitignore @@ -0,0 +1 @@ +install/ diff --git a/payloads/nvramcui/.gitignore b/payloads/nvramcui/.gitignore new file mode 100644 index 0000000000..4885853d42 --- /dev/null +++ b/payloads/nvramcui/.gitignore @@ -0,0 +1,2 @@ +build +libpayload diff --git a/util/amdfwtool/.gitignore b/util/amdfwtool/.gitignore new file mode 100644 index 0000000000..221a616c28 --- /dev/null +++ b/util/amdfwtool/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +amdfwtool diff --git a/util/archive/.gitignore b/util/archive/.gitignore new file mode 100644 index 0000000000..ea0035fa2a --- /dev/null +++ b/util/archive/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +archive diff --git a/util/autoport/.gitignore b/util/autoport/.gitignore new file mode 100644 index 0000000000..dc8599efdc --- /dev/null +++ b/util/autoport/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +autoport diff --git a/util/bincfg/.gitignore b/util/bincfg/.gitignore new file mode 100644 index 0000000000..ee1b39446e --- /dev/null +++ b/util/bincfg/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +bincfg diff --git a/util/board_status/.gitignore b/util/board_status/.gitignore new file mode 100644 index 0000000000..44847a9d5a --- /dev/null +++ b/util/board_status/.gitignore @@ -0,0 +1 @@ +board-status diff --git a/util/bucts/.gitignore b/util/bucts/.gitignore new file mode 100644 index 0000000000..c5a4708e0f --- /dev/null +++ b/util/bucts/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +bucts diff --git a/util/cbfstool/.gitignore b/util/cbfstool/.gitignore new file mode 100644 index 0000000000..28fb4b2d54 --- /dev/null +++ b/util/cbfstool/.gitignore @@ -0,0 +1,7 @@ +.dependencies +.test +cbfs-compression-tool +cbfstool +fmaptool +ifwitool +rmodtool diff --git a/util/cbmem/.gitignore b/util/cbmem/.gitignore new file mode 100644 index 0000000000..4905bd3757 --- /dev/null +++ b/util/cbmem/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +cbmem diff --git a/util/crossgcc/.gitignore b/util/crossgcc/.gitignore new file mode 100644 index 0000000000..0dfddd3b66 --- /dev/null +++ b/util/crossgcc/.gitignore @@ -0,0 +1,28 @@ +acpica-unix-*/ +binutils-*/ +build-*BINUTILS/ +build-*EXPAT/ +build-*GCC/ +build-*GDB/ +build-*GMP/ +build-*LIBELF/ +build-*MPC/ +build-*MPFR/ +build-*PYTHON/ +build-*LVM/ +build-*IASL/ +expat-*/ +gcc-*/ +gdb-*/ +gmp-*/ +libelf-*/ +mingwrt-*/ +mpc-*/ +mpfr-*/ +Python-*/ +*.src/ +tarballs/ +w32api-*/ +xgcc/ +xgcc-*/ +xgcc diff --git a/util/ectool/.gitignore b/util/ectool/.gitignore new file mode 100644 index 0000000000..67d81e4d6e --- /dev/null +++ b/util/ectool/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +ectool diff --git a/util/futility/.gitignore b/util/futility/.gitignore new file mode 100644 index 0000000000..aa3b0c76a9 --- /dev/null +++ b/util/futility/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +futility diff --git a/util/genprof/.gitignore b/util/genprof/.gitignore new file mode 100644 index 0000000000..14ffbb6b15 --- /dev/null +++ b/util/genprof/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +genprof diff --git a/util/ifdtool/.gitignore b/util/ifdtool/.gitignore new file mode 100644 index 0000000000..6cdb4236c9 --- /dev/null +++ b/util/ifdtool/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +ifdtool diff --git a/util/intelmetool/.gitignore b/util/intelmetool/.gitignore new file mode 100644 index 0000000000..5de15c02cd --- /dev/null +++ b/util/intelmetool/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +intelmetool diff --git a/util/intelp2m/.gitignore b/util/intelp2m/.gitignore new file mode 100644 index 0000000000..0696ea0e1c --- /dev/null +++ b/util/intelp2m/.gitignore @@ -0,0 +1,4 @@ +.dependencies +.test +intelp2m +generate/gpio.h diff --git a/util/inteltool/.gitignore b/util/inteltool/.gitignore new file mode 100644 index 0000000000..767fbcc0b8 --- /dev/null +++ b/util/inteltool/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +inteltool diff --git a/util/intelvbttool/.gitignore b/util/intelvbttool/.gitignore new file mode 100644 index 0000000000..d4d9279835 --- /dev/null +++ b/util/intelvbttool/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +intelvbttool diff --git a/util/kbc1126/.gitignore b/util/kbc1126/.gitignore new file mode 100644 index 0000000000..9ded0a5149 --- /dev/null +++ b/util/kbc1126/.gitignore @@ -0,0 +1,4 @@ +.dependencies +.test +kbc1126_ec_dump +kbc1126_ec_insert diff --git a/util/msrtool/.gitignore b/util/msrtool/.gitignore new file mode 100644 index 0000000000..13137c663c --- /dev/null +++ b/util/msrtool/.gitignore @@ -0,0 +1,5 @@ +.dependencies +.test +msrtool +Makefile +Makefile.deps diff --git a/util/nvramtool/.gitignore b/util/nvramtool/.gitignore new file mode 100644 index 0000000000..ab073417d7 --- /dev/null +++ b/util/nvramtool/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +nvramtool diff --git a/util/pmh7tool/.gitignore b/util/pmh7tool/.gitignore new file mode 100644 index 0000000000..4b8dbc51c0 --- /dev/null +++ b/util/pmh7tool/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +pmh7tool diff --git a/util/spd_tools/.gitignore b/util/spd_tools/.gitignore new file mode 100644 index 0000000000..5cd54134ed --- /dev/null +++ b/util/spd_tools/.gitignore @@ -0,0 +1,4 @@ +.dependencies +.test +*/gen_spd +*/gen_part_id diff --git a/util/superiotool/.gitignore b/util/superiotool/.gitignore new file mode 100644 index 0000000000..566cd8452d --- /dev/null +++ b/util/superiotool/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +superiotool diff --git a/util/vgabios/.gitignore b/util/vgabios/.gitignore new file mode 100644 index 0000000000..e19a8a51b6 --- /dev/null +++ b/util/vgabios/.gitignore @@ -0,0 +1,3 @@ +.dependencies +.test +testbios From 0a9eea0f5bb192a7e92115c87480836fb3395471 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 29 Oct 2020 10:21:45 +0100 Subject: [PATCH 033/129] util/docker: Add sdcc to our build nodes core-ec will need it. Change-Id: Id7d677a6f92ce266f893372a2540d77abb613707 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/46940 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- util/docker/coreboot-jenkins-node/Dockerfile | 1 + 1 file changed, 1 insertion(+) diff --git a/util/docker/coreboot-jenkins-node/Dockerfile b/util/docker/coreboot-jenkins-node/Dockerfile index 36b77d6398..9449c05bdd 100644 --- a/util/docker/coreboot-jenkins-node/Dockerfile +++ b/util/docker/coreboot-jenkins-node/Dockerfile @@ -20,6 +20,7 @@ USER root RUN apt-get -y update && \ apt-get -y install \ meson ninja-build \ + sdcc \ lua5.3 liblua5.3-dev default-jre-headless openssh-server && \ apt-get clean From 0655f78041ef617844f436306fa5431e211f4431 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 11 Dec 2019 16:19:48 -0800 Subject: [PATCH 034/129] commonlib/bsd: Add new CBFS core implementation This patch adds a new CBFS implementation that is intended to replace the existing commonlib/cbfs.c. The new implementation is designed to meet a bunch of current and future goals that in aggregate make it easier to start from scratch than to adapt the exisiting implementation: 1. Be BSD-licensed so it can evetually be shared with libpayload. 2. Allow generating/verifying a metadata hash for future CBFS per-file verification (see [1][2]). 3. Be very careful about reading (not mmaping) all data only once, to be suitable for eventual TOCTOU-safe verification. 4. Make it possible to efficiently implement all current and future firmware use cases (both with and without verification). The main primitive is the cbfs_walk() function which will traverse a CBFS and call a callback for every file. cbfs_lookup() uses this to implement the most common use case of finding a file so that it can be read. A host application using this code (e.g. coreboot, libpayload, cbfstool) will need to provide a header to provide the glue to access the respective CBFS storage backend implementation. This patch merely adds the code, the next patch will integrate it into coreboot. [1]: https://www.youtube.com/watch?v=Hs_EhewBgtM [2]: https://osfc.io/uploads/talk/paper/47/The_future_of_firmware_verification_in_coreboot.pdf (Note: In early discussions the metadata hash was called "master hash".) Change-Id: Ica64c1751fa37686814c0247460c399261d5814c Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/38421 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- MAINTAINERS | 9 +- src/commonlib/bsd/cbfs_private.c | 161 ++++++++++++++++++ .../bsd/include/commonlib/bsd/cb_err.h | 5 + .../bsd/include/commonlib/bsd/cbfs_private.h | 116 +++++++++++++ .../include/commonlib/bsd/cbfs_serialized.h | 6 +- 5 files changed, 292 insertions(+), 5 deletions(-) create mode 100644 src/commonlib/bsd/cbfs_private.c create mode 100644 src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h diff --git a/MAINTAINERS b/MAINTAINERS index d867c78465..ba88813509 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -694,8 +694,13 @@ OPTION ROM EXECUTION & X86EMU F: src/device/oprom/ CBFS -F: src/include/cbfs.h -F: src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h +M: Julius Werner +F: src/include/cbfs* +F: src/commonlib/bsd/include/commonlib/bsd/cbfs* +F: src/commonlib/bsd/cbfs* +F: src/lib/cbfs.c + +CBFSTOOL F: util/cbfstool/ CBMEM diff --git a/src/commonlib/bsd/cbfs_private.c b/src/commonlib/bsd/cbfs_private.c new file mode 100644 index 0000000000..035684b91e --- /dev/null +++ b/src/commonlib/bsd/cbfs_private.c @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */ + +#include +#include + +static cb_err_t read_next_header(cbfs_dev_t dev, size_t *offset, struct cbfs_file *buffer) +{ + const size_t devsize = cbfs_dev_size(dev); + DEBUG("Looking for next file @%#zx...\n", *offset); + *offset = ALIGN_UP(*offset, CBFS_ALIGNMENT); + while (*offset + sizeof(*buffer) < devsize) { + if (cbfs_dev_read(dev, buffer, *offset, sizeof(*buffer)) != sizeof(*buffer)) + return CB_CBFS_IO; + + if (memcmp(buffer->magic, CBFS_FILE_MAGIC, sizeof(buffer->magic)) == 0) + return CB_SUCCESS; + + *offset += CBFS_ALIGNMENT; + } + + DEBUG("End of CBFS reached\n"); + return CB_CBFS_NOT_FOUND; +} + +cb_err_t cbfs_walk(cbfs_dev_t dev, cb_err_t (*walker)(cbfs_dev_t dev, size_t offset, + const union cbfs_mdata *mdata, + size_t already_read, void *arg), + void *arg, struct vb2_hash *metadata_hash, enum cbfs_walk_flags flags) +{ + const bool do_hash = CBFS_ENABLE_HASHING && metadata_hash; + struct vb2_digest_context dc; + vb2_error_t vbrv; + + assert(CBFS_ENABLE_HASHING || (!metadata_hash && !(flags & CBFS_WALK_WRITEBACK_HASH))); + if (do_hash && (vbrv = vb2_digest_init(&dc, metadata_hash->algo))) { + ERROR("Metadata hash digest (%d) init error: %#x\n", metadata_hash->algo, vbrv); + return CB_ERR_ARG; + } + + size_t offset = 0; + cb_err_t ret_header; + cb_err_t ret_walker = CB_CBFS_NOT_FOUND; + union cbfs_mdata mdata; + while ((ret_header = read_next_header(dev, &offset, &mdata.h)) == CB_SUCCESS) { + const uint32_t attr_offset = be32toh(mdata.h.attributes_offset); + const uint32_t data_offset = be32toh(mdata.h.offset); + const uint32_t data_length = be32toh(mdata.h.len); + const uint32_t type = be32toh(mdata.h.type); + const bool empty = (type == CBFS_TYPE_DELETED || type == CBFS_TYPE_DELETED2); + + DEBUG("Found CBFS header @%#zx (type %d, attr +%#x, data +%#x, length %#x)\n", + offset, type, attr_offset, data_offset, data_length); + if (data_offset > sizeof(mdata)) { + ERROR("File metadata @%#zx too large\n", offset); + goto next_file; + } + + if (empty && !(flags & CBFS_WALK_INCLUDE_EMPTY)) + goto next_file; + + /* When hashing we need to read everything. Otherwise skip the attributes. + attr_offset may be 0, which means there are no attributes. */ + ssize_t todo; + if (do_hash || attr_offset == 0) + todo = data_offset - sizeof(mdata.h); + else + todo = attr_offset - sizeof(mdata.h); + if (todo <= 0 || data_offset < attr_offset) { + ERROR("Corrupt file header @%#zx\n", offset); + goto next_file; + } + + /* Read the rest of the metadata (filename, and possibly attributes). */ + assert(todo > 0 && todo <= sizeof(mdata) - sizeof(mdata.h)); + if (cbfs_dev_read(dev, mdata.raw + sizeof(mdata.h), + offset + sizeof(mdata.h), todo) != todo) + return CB_CBFS_IO; + DEBUG("File name: '%s'\n", mdata.filename); + + if (do_hash && !empty && vb2_digest_extend(&dc, mdata.raw, data_offset)) + return CB_ERR; + + if (walker && ret_walker == CB_CBFS_NOT_FOUND) + ret_walker = walker(dev, offset, &mdata, sizeof(mdata.h) + todo, arg); + + /* Return IO errors immediately. For others, finish the hash first if needed. */ + if (ret_walker == CB_CBFS_IO || (ret_walker != CB_CBFS_NOT_FOUND && !do_hash)) + return ret_walker; + +next_file: + offset += data_offset + data_length; + } + + if (ret_header != CB_CBFS_NOT_FOUND) + return ret_header; + + if (do_hash) { + uint8_t real_hash[VB2_MAX_DIGEST_SIZE]; + size_t hash_size = vb2_digest_size(metadata_hash->algo); + if (vb2_digest_finalize(&dc, real_hash, hash_size)) + return CB_ERR; + if (flags & CBFS_WALK_WRITEBACK_HASH) + memcpy(metadata_hash->raw, real_hash, hash_size); + else if (memcmp(metadata_hash->raw, real_hash, hash_size) != 0) + return CB_CBFS_HASH_MISMATCH; + } + + return ret_walker; +} + +cb_err_t cbfs_copy_fill_metadata(union cbfs_mdata *dst, const union cbfs_mdata *src, + size_t already_read, cbfs_dev_t dev, size_t offset) +{ + /* First, copy the stuff that cbfs_walk() already read for us. */ + memcpy(dst, src, already_read); + + /* Then read in whatever metadata may be left (will only happen in non-hashing case). */ + const size_t todo = be32toh(src->h.offset) - already_read; + assert(todo <= sizeof(*dst) - already_read); + if (todo && cbfs_dev_read(dev, dst->raw + already_read, offset + already_read, + todo) != todo) + return CB_CBFS_IO; + return CB_SUCCESS; +} + +struct cbfs_lookup_args { + union cbfs_mdata *mdata_out; + const char *name; + size_t namesize; + size_t *data_offset_out; +}; + +static cb_err_t lookup_walker(cbfs_dev_t dev, size_t offset, const union cbfs_mdata *mdata, + size_t already_read, void *arg) +{ + struct cbfs_lookup_args *args = arg; + + /* Check if the name we're looking for could fit, then we can safely memcmp() it. */ + if (args->namesize > already_read - offsetof(union cbfs_mdata, filename) || + memcmp(args->name, mdata->filename, args->namesize) != 0) + return CB_CBFS_NOT_FOUND; + + LOG("Found '%s' @%#zx size %#x\n", args->name, offset, be32toh(mdata->h.len)); + if (cbfs_copy_fill_metadata(args->mdata_out, mdata, already_read, dev, offset)) + return CB_CBFS_IO; + + *args->data_offset_out = offset + be32toh(mdata->h.offset); + return CB_SUCCESS; +} + +cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out, + size_t *data_offset_out, struct vb2_hash *metadata_hash) +{ + struct cbfs_lookup_args args = { + .mdata_out = mdata_out, + .name = name, + .namesize = strlen(name) + 1, /* Count trailing \0 so we can memcmp() it. */ + .data_offset_out = data_offset_out, + }; + return cbfs_walk(dev, lookup_walker, &args, metadata_hash, 0); +} diff --git a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h index ab419a7709..e5aa852617 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h @@ -34,6 +34,11 @@ enum cb_err { CB_I2C_PROTOCOL_ERROR = -302, /**< Data lost or spurious slave device response, try again? */ CB_I2C_TIMEOUT = -303, /**< Transmission timed out */ + + /* CBFS errors */ + CB_CBFS_IO = -400, /**< Underlying I/O error */ + CB_CBFS_NOT_FOUND = -401, /**< File not found in directory */ + CB_CBFS_HASH_MISMATCH = -402, /**< Master hash validation failed */ }; /* Don't typedef the enum directly, so the size is unambiguous for serialization. */ diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h new file mode 100644 index 0000000000..aaee62f4c3 --- /dev/null +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */ + +#ifndef _COMMONLIB_BSD_CBFS_PRIVATE_H_ +#define _COMMONLIB_BSD_CBFS_PRIVATE_H_ + + +#include +#include +#include +#include +#include +#include + +/* + * This header implements low-level CBFS access APIs that can be shared across different + * host applications (e.g. coreboot, libpayload, cbfstool). For verification purposes it + * implements the metadata hashing part but not the file hashing part, so the host application + * will need to verify file hashes itself after loading each file. Host applications that use + * verification should implement wrapper APIs that combine the lookup, loading and hashing steps + * into a single, safe function call and outside of the code implementing those APIs should not + * be accessing the low-level APIs in this file directly (e.g. coreboot SoC/driver code should + * never directly #include this file, and always use the higher level APIs in src/lib/cbfs.c). + * + * needs to be provided by the host application using this CBFS library. It must + * define the following type, macros and functions: + * + * cbfs_dev_t An opaque type representing a CBFS storage backend. + * CBFS_ENABLE_HASHING Should be 0 to avoid linking hashing features, 1 otherwise. (Only for + * metadata hashing. Host application needs to check file hashes itself.) + * ERROR(...) printf-style macro to print errors. + * LOG(...) printf-style macro to print normal-operation log messages. + * DEBUG(...) printf-style macro to print detailed debug output. + * + * ssize_t cbfs_dev_read(cbfs_dev_t dev, void *buffer, size_t offset, size_t size); + * Read |size| bytes starting at |offset| from |dev| into |buffer|. + * Returns amount of bytes read on success and < 0 on error. + * This function *MUST* sanity-check offset/size on its own. + * + * size_t cbfs_dev_size(cbfs_dev_t dev); + * Return the total size in bytes of the CBFS storage (actual CBFS area). + */ +#include + +/* + * Helper structure to allocate space for a blob of metadata on the stack. + * NOTE: The fields in any union cbfs_mdata or any of its substructures from cbfs_serialized.h + * should always remain in the same byte order as they are stored on flash (= big endian). To + * avoid byte-order confusion, fields should always and only be converted to host byte order at + * exactly the time they are read from one of these structures into their own separate variable. + */ +#define CBFS_METADATA_MAX_SIZE 256 +union cbfs_mdata { + struct { + struct cbfs_file h; + char filename[]; + }; + uint8_t raw[CBFS_METADATA_MAX_SIZE]; +}; + +/* Flags that modify behavior of cbfs_walk(). */ +enum cbfs_walk_flags { + /* Write the calculated hash back out to |metadata_hash->hash| rather than comparing it. + |metadata_hash->algo| must still have been initialized by the caller. */ + CBFS_WALK_WRITEBACK_HASH = (1 << 0), + /* Call |walker| for empty file entries (i.e. entries with one of the CBFS_TYPE_DELETED + types that mark free space in the CBFS). Otherwise, those entries will be skipped. + Either way, these entries are never included in the metadata_hash calculation. */ + CBFS_WALK_INCLUDE_EMPTY = (1 << 1), +}; + +/* + * Traverse a CBFS and call a |walker| callback function for every file. Can additionally + * calculate a hash over the metadata of all files in the CBFS. If |metadata_hash| is NULL, + * hashing is disabled. If |walker| is NULL, will just traverse and hash the CBFS without + * invoking any callbacks (and always return CB_CBFS_NOT_FOUND unless there was another error). + * + * |arg| and |dev| will be passed through to |walker| unmodified. |offset| is the absolute + * offset in |dev| at which the current file metadata starts. |mdata| is a temporary buffer + * (only valid for the duration of this call to |walker|) containing already read metadata from + * the current file, up to |already_read| bytes. This will always at least contain the header + * fields and filename, but may contain more (i.e. attributes), depending on whether hashing is + * enabled. |walker| should call into cbfs_copy_fill_medadata() to copy the metadata of a file + * to a persistent buffer and automatically load remaining metadata from |dev| as needed based + * on the value of |already_read|. + * + * |walker| should return CB_CBFS_NOT_FOUND if it wants to continue being called for further + * files. Any other return code will be used as the final return code for cbfs_walk(). It will + * return immediately unless it needs to calculate a hash in which case it will still traverse + * the remaining CBFS (but not call |walker| anymore). + * + * Returns, from highest to lowest priority: + * CB_CBFS_IO - There was an IO error with the CBFS device (always considered fatal) + * CB_CBFS_HASH_MISMATCH - |metadata_hash| was provided and did not match the CBFS + * CB_SUCCESS/ - First non-CB_CBFS_NOT_FOUND code returned by walker() + * CB_CBFS_NOT_FOUND - walker() returned CB_CBFS_NOT_FOUND for every file in the CBFS + */ +cb_err_t cbfs_walk(cbfs_dev_t dev, cb_err_t (*walker)(cbfs_dev_t dev, size_t offset, + const union cbfs_mdata *mdata, + size_t already_read, void *arg), + void *arg, struct vb2_hash *metadata_hash, enum cbfs_walk_flags); + +/* + * Helper function that can be used by a |walker| callback to cbfs_walk() to copy the metadata + * of a file into a permanent buffer. Will copy the |already_read| metadata from |src| into + * |dst| and load remaining metadata from |dev| as required. + */ +cb_err_t cbfs_copy_fill_metadata(union cbfs_mdata *dst, const union cbfs_mdata *src, + size_t already_read, cbfs_dev_t dev, size_t offset); + +/* Find a file named |name| in the CBFS on |dev|. Copy its metadata (including attributes) + * into |mdata_out| and pass out the offset to the file data on the CBFS device. + * Verify the metadata with |metadata_hash| if provided. */ +cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out, + size_t *data_offset_out, struct vb2_hash *metadata_hash); + +#endif /* _COMMONLIB_BSD_CBFS_PRIVATE_H_ */ diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h index 3c76a49f55..7171634c8e 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h @@ -4,6 +4,7 @@ #define _CBFS_SERIALIZED_H_ #include +#include /** These are standard values for the known compression algorithms that coreboot knows about for stages and @@ -124,12 +125,11 @@ struct cbfs_file_attr_compression { uint32_t decompressed_size; } __packed; +/* Actual size in CBFS may be larger/smaller than struct size! */ struct cbfs_file_attr_hash { uint32_t tag; uint32_t len; - uint32_t hash_type; - /* hash_data is len - sizeof(struct) bytes */ - uint8_t hash_data[]; + struct vb2_hash hash; } __packed; struct cbfs_file_attr_position { From 1cd013bec5967ca1d0203de0f506a8af984f814e Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 11 Dec 2019 16:50:02 -0800 Subject: [PATCH 035/129] cbfs: Hook up to new CBFS implementation This patch hooks coreboot up to the new commonlib/bsd CBFS implementation. This is intended as the "minimum viable patch" that makes the new implementation useable with the smallest amount of changes -- that is why some of this may look a bit roundabout (returning the whole metadata for a file but then just using that to fill out the rdevs of the existing struct cbfsf). Future changes will migrate the higher level CBFS APIs one-by-one to use the new implementation directly (rather than translated into the results of the old one), at which point this will become more efficient. Change-Id: I4d112d1239475920de2d872dac179c245275038d Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/38422 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/commonlib/Makefile.inc | 7 ++++ src/commonlib/cbfs.c | 15 -------- src/commonlib/include/commonlib/cbfs.h | 3 +- src/include/cbfs_glue.h | 30 +++++++++++++++ src/lib/cbfs.c | 53 ++++++++++++-------------- 5 files changed, 64 insertions(+), 44 deletions(-) create mode 100644 src/include/cbfs_glue.h diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index 5bd6cf9e65..b2225cb114 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -30,6 +30,13 @@ ramstage-y += cbfs.c smm-y += cbfs.c postcar-y += cbfs.c +bootblock-y += bsd/cbfs_private.c +verstage-y += bsd/cbfs_private.c +romstage-y += bsd/cbfs_private.c +postcar-y += bsd/cbfs_private.c +ramstage-y += bsd/cbfs_private.c +smm-y += bsd/cbfs_private.c + decompressor-y += bsd/lz4_wrapper.c bootblock-y += bsd/lz4_wrapper.c verstage-y += bsd/lz4_wrapper.c diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c index 115f99a68e..999c35e52a 100644 --- a/src/commonlib/cbfs.c +++ b/src/commonlib/cbfs.c @@ -7,21 +7,6 @@ #include #include -#if !defined(LOG) -#define LOG(x...) printk(BIOS_INFO, "CBFS: " x) -#endif -#if defined(CONFIG) - -#if CONFIG(DEBUG_CBFS) -#define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x) -#else -#define DEBUG(x...) -#endif - -#elif !defined(DEBUG) -#define DEBUG(x...) -#endif - static size_t cbfs_next_offset(const struct region_device *cbfs, const struct cbfsf *f) { diff --git a/src/commonlib/include/commonlib/cbfs.h b/src/commonlib/include/commonlib/cbfs.h index 90aa0b2571..6565c1dcd3 100644 --- a/src/commonlib/include/commonlib/cbfs.h +++ b/src/commonlib/include/commonlib/cbfs.h @@ -3,7 +3,7 @@ #ifndef _COMMONLIB_CBFS_H_ #define _COMMONLIB_CBFS_H_ -#include +#include #include #include @@ -11,6 +11,7 @@ struct cbfsf { struct region_device metadata; struct region_device data; + union cbfs_mdata mdata; }; /* Locate file by name and optional type. Returns 0 on success else < 0 on diff --git a/src/include/cbfs_glue.h b/src/include/cbfs_glue.h new file mode 100644 index 0000000000..ebfbc2e7ae --- /dev/null +++ b/src/include/cbfs_glue.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _CBFS_GLUE_H_ +#define _CBFS_GLUE_H_ + +#include +#include + +#define CBFS_ENABLE_HASHING 0 + +#define ERROR(...) printk(BIOS_ERR, "CBFS ERROR: " __VA_ARGS__) +#define LOG(...) printk(BIOS_ERR, "CBFS: " __VA_ARGS__) +#define DEBUG(...) do { \ + if (CONFIG(DEBUG_CBFS)) \ + printk(BIOS_SPEW, "CBFS DEBUG: " __VA_ARGS__); \ +} while (0) + +typedef const struct region_device *cbfs_dev_t; + +static inline ssize_t cbfs_dev_read(cbfs_dev_t dev, void *buffer, size_t offset, size_t size) +{ + return rdev_readat(dev, buffer, offset, size); +} + +static inline size_t cbfs_dev_size(cbfs_dev_t dev) +{ + return region_device_sz(dev); +} + +#endif /* _CBFS_GLUE_H_ */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 35193d0ecf..447d91f1be 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -15,14 +16,6 @@ #include #include -#define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) -#define LOG(x...) printk(BIOS_INFO, "CBFS: " x) -#if CONFIG(DEBUG_CBFS) -#define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x) -#else -#define DEBUG(x...) -#endif - int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) { struct region_device rdev; @@ -30,31 +23,35 @@ int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) if (cbfs_boot_region_device(&rdev)) return -1; - int ret = cbfs_locate(fh, &rdev, name, type); + size_t data_offset; + cb_err_t err = cbfs_lookup(&rdev, name, &fh->mdata, &data_offset, NULL); - if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && ret) { - - /* - * When VBOOT_ENABLE_CBFS_FALLBACK is enabled and a file is not available in the - * active RW region, the RO (COREBOOT) region will be used to locate the file. - * - * This functionality makes it possible to avoid duplicate files in the RO - * and RW partitions while maintaining updateability. - * - * Files can be added to the RO_REGION_ONLY config option to use this feature. - */ - printk(BIOS_DEBUG, "Fall back to RO region for %s\n", name); + if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && err == CB_CBFS_NOT_FOUND) { + printk(BIOS_INFO, "CBFS: Fall back to RO region for %s\n", + name); if (fmap_locate_area_as_rdev("COREBOOT", &rdev)) - ERROR("RO region not found\n"); - else - ret = cbfs_locate(fh, &rdev, name, type); + return -1; + err = cbfs_lookup(&rdev, name, &fh->mdata, &data_offset, NULL); + } + if (err) + return -1; + + size_t msize = be32toh(fh->mdata.h.offset); + if (rdev_chain(&fh->metadata, &addrspace_32bit.rdev, + (uintptr_t)&fh->mdata, msize) || + rdev_chain(&fh->data, &rdev, data_offset, be32toh(fh->mdata.h.len))) + return -1; + if (type) { + if (!*type) + *type = be32toh(fh->mdata.h.type); + else if (*type != be32toh(fh->mdata.h.type)) + return -1; } - if (!ret) - if (tspi_measure_cbfs_hook(fh, name)) - return -1; + if (tspi_measure_cbfs_hook(fh, name)) + return -1; - return ret; + return 0; } void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size) From c5e28abaf803465ae4bfec1904618497e077ca50 Mon Sep 17 00:00:00 2001 From: Zheng Bao Date: Wed, 28 Oct 2020 11:38:09 +0800 Subject: [PATCH 036/129] amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) Reviewed-by: Nikolai Vyssotski Reviewed-by: Felix Held --- src/soc/amd/picasso/Kconfig | 14 +- src/soc/amd/picasso/Makefile.inc | 178 +-------- src/soc/amd/picasso/fw.cfg | 39 ++ src/soc/amd/stoneyridge/Kconfig | 11 +- src/soc/amd/stoneyridge/Makefile.inc | 129 ++----- src/soc/amd/stoneyridge/fw_cz.cfg | 18 + src/soc/amd/stoneyridge/fw_st.cfg | 20 + src/southbridge/amd/pi/hudson/Kconfig | 4 + src/southbridge/amd/pi/hudson/Makefile.inc | 39 +- src/southbridge/amd/pi/hudson/fw_avl.cfg | 8 + util/amdfwtool/Makefile | 2 +- util/amdfwtool/Makefile.inc | 2 +- util/amdfwtool/amdfwtool.c | 344 +++++------------ util/amdfwtool/amdfwtool.h | 119 ++++++ util/amdfwtool/data_parse.c | 418 +++++++++++++++++++++ 15 files changed, 786 insertions(+), 559 deletions(-) create mode 100644 src/soc/amd/picasso/fw.cfg create mode 100644 src/soc/amd/stoneyridge/fw_cz.cfg create mode 100644 src/soc/amd/stoneyridge/fw_st.cfg create mode 100644 src/southbridge/amd/pi/hudson/fw_avl.cfg create mode 100644 util/amdfwtool/amdfwtool.h create mode 100644 util/amdfwtool/data_parse.c diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 6a5b93244d..7e03a41613 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -446,9 +446,9 @@ comment "AMD Firmware Directory Table set to location for 8MB ROM" comment "AMD Firmware Directory Table set to location for 16MB ROM" depends on AMD_FWM_POSITION_INDEX = 5 -config AMD_PUBKEY_FILE +config AMDFW_CONFIG_FILE string - default "3rdparty/amd_blobs/picasso/PSP/AmdPubKeyRV.bin" + default "src/soc/amd/picasso/fw.cfg" config USE_PSPSECUREOS bool @@ -487,16 +487,6 @@ config PSP_WHITELIST_FILE depends on HAVE_PSP_WHITELIST_FILE default "3rdparty/amd_blobs/picasso/PSP/wtl-rvn.sbin" -config PSP_BOOTLOADER_FILE - string "Specify the PSP Bootloader file path" - default "3rdparty/amd_blobs/picasso/PSP/PspBootLoader_WL_RV.sbin" if HAVE_PSP_WHITELIST_FILE - default "3rdparty/amd_blobs/picasso/PSP/PspBootLoader_prod_RV.sbin" - help - Supply the name of the PSP bootloader file. - - Note that this option may conflict with the whitelist file if a - different PSP bootloader binary is specified. - config PSP_SHAREDMEM_SIZE hex "Maximum size of shared memory area" default 0x3000 if VBOOT diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 514b313a6d..7ec695aed9 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -125,77 +125,35 @@ PICASSO_FWM_POSITION=$(call int-add, \ # Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). # -# type = 0x0 -FIRMWARE_LOCATE=$(realpath $(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)))) - -# type = 0x1 -ifeq ($(CONFIG_PSP_BOOTLOADER_FILE),) -$(error CONFIG_PSP_BOOTLOADER_FILE was not defined) -endif -PSPBTLDR_FILE=$(realpath $(call strip_quotes, $(CONFIG_PSP_BOOTLOADER_FILE))) -$(info Adding PSP $(shell dd if=$(PSPBTLDR_FILE) | md5sum)) - -# types = 0x8 and 0x12 -PSP_SMUFW1_SUB1_FILE=$(FIRMWARE_LOCATE)/SmuFirmwareRV2.csbin -PSP_SMUFW1_SUB2_FILE=$(FIRMWARE_LOCATE)/SmuFirmwarePCO.csbin -PSP_SMUFW2_SUB1_FILE=$(FIRMWARE_LOCATE)/SmuFirmware2RV2.csbin -PSP_SMUFW2_SUB2_FILE=$(FIRMWARE_LOCATE)/SmuFirmware2PCO.csbin +FIRMWARE_LOCATE=$(shell grep -e FIRMWARE_LOCATE $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) -# type = 0x9 -PSP_SEC_DBG_KEY_FILE=$(FIRMWARE_LOCATE)/RavenSecureDebug_PublicKey.bin -# type = 0x13 -PSP_SEC_DEBUG_FILE=$(FIRMWARE_LOCATE)/secure_unlock_prod_RV.sbin # Enable secure debug unlock PSP_SOFTFUSE_BITS += 0 -PSP_TOKEN_UNLOCK="--token-unlock" +OPT_TOKEN_UNLOCK="--token-unlock" endif ifeq ($(CONFIG_USE_PSPSECUREOS),y) # types = 0x2 -PSPSECUREOS_FILE=$(FIRMWARE_LOCATE)/psp_os_combined_prod_RV.sbin +OPT_PSP_USE_PSPSECUREOS="--use-pspsecureos" endif -# type = 0x21 -PSP_IKEK_FILE=$(FIRMWARE_LOCATE)/PspIkekRV.bin - -# type = 0x24 -PSP_SECG1_FILE=$(FIRMWARE_LOCATE)/security_policy_RV2_FP5_AM4.sbin -PSP_SECG2_FILE=$(FIRMWARE_LOCATE)/security_policy_PCO_FP5_AM4.sbin ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) -# type = 0x25 -PSP_MP2FW1_FILE=$(FIRMWARE_LOCATE)/MP2I2CFWRV2.sbin -PSP_MP2FW2_FILE=$(FIRMWARE_LOCATE)/MP2I2CFWPCO.sbin -# BIOS type = 0x6a -PSP_MP2CFG_FILE=$(FIRMWARE_LOCATE)/MP2FWConfig.sbin +OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" else # Disable MP2 firmware loading PSP_SOFTFUSE_BITS += 29 endif -# type = 0x28 -PSP_DRIVERS_FILE=$(FIRMWARE_LOCATE)/drv_sys_prod_RV.sbin - ifeq ($(CONFIG_PSP_LOAD_S0I3_FW),y) -PSP_S0I3_FILE=$(FIRMWARE_LOCATE)/dr_agesa_prod_RV.sbin +OPT_PSP_LOAD_S0I3_FW="--load-s0i3" endif -# types = 0x30 - 0x37 -PSP_ABL0_FILE=$(FIRMWARE_LOCATE)/AgesaBootloader0_prod_RV.csbin -PSP_ABL1_FILE=$(FIRMWARE_LOCATE)/AgesaBootloader1_prod_RV.csbin -PSP_ABL2_FILE=$(FIRMWARE_LOCATE)/AgesaBootloader2_prod_RV.csbin -PSP_ABL3_FILE=$(FIRMWARE_LOCATE)/AgesaBootloader3_prod_RV.csbin -PSP_ABL4_FILE=$(FIRMWARE_LOCATE)/AgesaBootloader4_prod_RV.csbin -PSP_ABL5_FILE=$(FIRMWARE_LOCATE)/AgesaBootloader5_prod_RV.csbin -PSP_ABL6_FILE=$(FIRMWARE_LOCATE)/AgesaBootloader6_prod_RV.csbin -PSP_ABL7_FILE=$(FIRMWARE_LOCATE)/AgesaBootloader7_prod_RV.csbin - # type = 0x3a ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) endif - # # BIOS Directory Table items - proper ordering is managed by amdfwtool # @@ -216,16 +174,6 @@ PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | a APOB_NV_SIZE=$(shell grep "FMAP_SECTION_RW_MRC_CACHE_SIZE" $(obj)/fmap_config.h | awk '{print $$(NF)}') APOB_NV_BASE=$(shell grep "FMAP_SECTION_RW_MRC_CACHE_START" $(obj)/fmap_config.h | awk '{print $$(NF)}') -# type2 = 0x64, 0x65 -PSP_PMUI_FILE1=$(FIRMWARE_LOCATE)/Appb_Rv_1D_Ddr4_Udimm_Imem.csbin -PSP_PMUI_FILE2=$(FIRMWARE_LOCATE)/Appb_Rv_2D_Ddr4_Imem.csbin -PSP_PMUI_FILE3=$(FIRMWARE_LOCATE)/Appb_Rv2_1D_ddr4_Udimm_Imem.csbin -PSP_PMUI_FILE4=$(FIRMWARE_LOCATE)/Appb_Rv2_2D_ddr4_Udimm_Imem.csbin -PSP_PMUD_FILE1=$(FIRMWARE_LOCATE)/Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin -PSP_PMUD_FILE2=$(FIRMWARE_LOCATE)/Appb_Rv_2D_Ddr4_Dmem.csbin -PSP_PMUD_FILE3=$(FIRMWARE_LOCATE)/Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin -PSP_PMUD_FILE4=$(FIRMWARE_LOCATE)/Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin - # type = 0x66 PSP_UCODE_FILE1=$(FIRMWARE_LOCATE)/UcodePatch_PCO_B1.bin PSP_UCODE_FILE2=$(FIRMWARE_LOCATE)/UcodePatch_PCO_B0.bin @@ -259,33 +207,6 @@ PSP_SOFTFUSE=$(shell A=$(call int-add, \ add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) -OPT_AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey) -OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(PSPBTLDR_FILE), --bootloader) -OPT_SMUFW1_SUB1_FILE=$(call add_opt_prefix, $(PSP_SMUFW1_SUB1_FILE), --subprogram 1 --smufirmware) -OPT_SMUFW1_SUB2_FILE=$(call add_opt_prefix, $(PSP_SMUFW1_SUB2_FILE), --subprogram 2 --smufirmware) -OPT_SMUFW2_SUB1_FILE=$(call add_opt_prefix, $(PSP_SMUFW2_SUB1_FILE), --subprogram 1 --smufirmware2) -OPT_SMUFW2_SUB2_FILE=$(call add_opt_prefix, $(PSP_SMUFW2_SUB2_FILE), --subprogram 2 --smufirmware2) -OPT_PSP_SEC_DBG_KEY_FILE=$(call add_opt_prefix, $(PSP_SEC_DBG_KEY_FILE), --securedebug) -OPT_TOKEN_UNLOCK=$(call add_opt_prefix, $(PSP_TOKEN_UNLOCK), "") -OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) -OPT_PSPSECUREOS_FILE=$(call add_opt_prefix, $(PSPSECUREOS_FILE), --secureos) -OPT_SEC_DEBUG_FILE=$(call add_opt_prefix, $(PSP_SEC_DEBUG_FILE), --secdebug) -OPT_IKEK_FILE=$(call add_opt_prefix, $(PSP_IKEK_FILE), --ikek) -OPT_SECG1_FILE=$(call add_opt_prefix, $(PSP_SECG1_FILE), --subprog 1 --sec-gasket) -OPT_SECG2_FILE=$(call add_opt_prefix, $(PSP_SECG2_FILE), --subprog 2 --sec-gasket) -OPT_MP2FW1_FILE=$(call add_opt_prefix, $(PSP_MP2FW1_FILE), --subprog 1 --mp2-fw) -OPT_MP2FW2_FILE=$(call add_opt_prefix, $(PSP_MP2FW2_FILE), --subprog 2 --mp2-fw) -OPT_DRIVERS_FILE=$(call add_opt_prefix, $(PSP_DRIVERS_FILE), --drv-entry-pts) -OPT_PSP_S0I3_FILE=$(call add_opt_prefix, $(PSP_S0I3_FILE), --s0i3drv) -OPT_ABL0_FILE=$(call add_opt_prefix, $(PSP_ABL0_FILE), --abl-image) -OPT_ABL1_FILE=$(call add_opt_prefix, $(PSP_ABL1_FILE), --abl-image) -OPT_ABL2_FILE=$(call add_opt_prefix, $(PSP_ABL2_FILE), --abl-image) -OPT_ABL3_FILE=$(call add_opt_prefix, $(PSP_ABL3_FILE), --abl-image) -OPT_ABL4_FILE=$(call add_opt_prefix, $(PSP_ABL4_FILE), --abl-image) -OPT_ABL5_FILE=$(call add_opt_prefix, $(PSP_ABL5_FILE), --abl-image) -OPT_ABL6_FILE=$(call add_opt_prefix, $(PSP_ABL6_FILE), --abl-image) -OPT_ABL7_FILE=$(call add_opt_prefix, $(PSP_ABL7_FILE), --abl-image) -OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) @@ -297,15 +218,7 @@ OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) -OPT_PSP_PMUI_FILE1=$(call add_opt_prefix, $(PSP_PMUI_FILE1), --subprogram 0 --instance 1 --pmu-inst) -OPT_PSP_PMUI_FILE2=$(call add_opt_prefix, $(PSP_PMUI_FILE2), --subprogram 0 --instance 4 --pmu-inst) -OPT_PSP_PMUI_FILE3=$(call add_opt_prefix, $(PSP_PMUI_FILE3), --subprogram 1 --instance 1 --pmu-inst) -OPT_PSP_PMUI_FILE4=$(call add_opt_prefix, $(PSP_PMUI_FILE4), --subprogram 1 --instance 4 --pmu-inst) -OPT_PSP_PMUD_FILE1=$(call add_opt_prefix, $(PSP_PMUD_FILE1), --subprogram 0 --instance 1 --pmu-data) -OPT_PSP_PMUD_FILE2=$(call add_opt_prefix, $(PSP_PMUD_FILE2), --subprogram 0 --instance 4 --pmu-data) -OPT_PSP_PMUD_FILE3=$(call add_opt_prefix, $(PSP_PMUD_FILE3), --subprogram 1 --instance 1 --pmu-data) -OPT_PSP_PMUD_FILE4=$(call add_opt_prefix, $(PSP_PMUD_FILE4), --subprogram 1 --instance 4 --pmu-data) -OPT_MP2CFG_FILE=$(call add_opt_prefix, $(PSP_MP2CFG_FILE), --mp2-config) + OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) @@ -314,49 +227,28 @@ OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi- OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) +OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) + ifeq ($(CONFIG_VBOOT),) OPT_APOB0_NV_SIZE=$(OPT_APOB_NV_SIZE) OPT_APOB0_NV_BASE=$(OPT_APOB_NV_BASE) endif -AMDFW_COMMON_ARGS=$(OPT_AMD_PUBKEY_FILE) \ - $(OPT_PSPSECUREOS_FILE) \ - $(OPT_PSP_SEC_DBG_KEY_FILE) \ - $(OPT_SMUFW1_SUB2_FILE) \ - $(OPT_SMUFW2_SUB2_FILE) \ - $(OPT_SMUFW1_SUB1_FILE) \ - $(OPT_SMUFW2_SUB1_FILE) \ - $(OPT_PSP_APCB_FILES) \ +OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) + +# Add all the files listed in the config file +DEP_FILES=$(shell $(AMDFWTOOL) --config $(CONFIG_AMDFW_CONFIG_FILE) --depend) + +AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_APOB_ADDR) \ $(OPT_PSP_BIOSBIN_FILE) \ $(OPT_PSP_BIOSBIN_DEST) \ $(OPT_PSP_BIOSBIN_SIZE) \ $(OPT_PSP_SOFTFUSE) \ - $(OPT_PSP_PMUI_FILE1) \ - $(OPT_PSP_PMUI_FILE2) \ - $(OPT_PSP_PMUI_FILE3) \ - $(OPT_PSP_PMUI_FILE4) \ - $(OPT_PSP_PMUD_FILE1) \ - $(OPT_PSP_PMUD_FILE2) \ - $(OPT_PSP_PMUD_FILE3) \ - $(OPT_PSP_PMUD_FILE4) \ - $(OPT_MP2CFG_FILE) \ - $(OPT_ABL0_FILE) \ - $(OPT_ABL1_FILE) \ - $(OPT_ABL2_FILE) \ - $(OPT_ABL3_FILE) \ - $(OPT_ABL4_FILE) \ - $(OPT_ABL5_FILE) \ - $(OPT_ABL6_FILE) \ - $(OPT_ABL7_FILE) \ + $(OPT_PSP_USE_PSPSECUREOS) \ + $(OPT_PSP_LOAD_MP2_FW) \ + $(OPT_PSP_LOAD_S0I3_FW) \ $(OPT_WHITELIST_FILE) \ - $(OPT_SECG1_FILE) \ - $(OPT_SECG2_FILE) \ - $(OPT_MP2FW1_FILE) \ - $(OPT_MP2FW2_FILE) \ - $(OPT_DRIVERS_FILE) \ - $(OPT_PSP_S0I3_FILE) \ - $(OPT_IKEK_FILE) \ $(OPT_SEC_DEBUG_FILE) \ $(OPT_PSP_SHAREDMEM_BASE) \ $(OPT_PSP_SHAREDMEM_SIZE) \ @@ -365,45 +257,15 @@ AMDFW_COMMON_ARGS=$(OPT_AMD_PUBKEY_FILE) \ $(OPT_EFS_SPI_READ_MODE) \ $(OPT_EFS_SPI_SPEED) \ $(OPT_EFS_SPI_MICRON_FLAG) \ + --config $(CONFIG_AMDFW_CONFIG_FILE) \ --soc-name "Picasso" \ --flashsize $(CONFIG_ROM_SIZE) -$(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ - $(call strip_quotes, $(PSPBTLDR_FILE)) \ - $(call strip_quotes, $(PSPSECUREOS_FILE)) \ - $(call strip_quotes, $(PSP_SEC_DBG_KEY_FILE)) \ - $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ - $(call strip_quotes, $(PSP_PMUI_FILE1)) \ - $(call strip_quotes, $(PSP_PMUI_FILE2)) \ - $(call strip_quotes, $(PSP_PMUI_FILE3)) \ - $(call strip_quotes, $(PSP_PMUI_FILE4)) \ - $(call strip_quotes, $(PSP_PMUD_FILE1)) \ - $(call strip_quotes, $(PSP_PMUD_FILE2)) \ - $(call strip_quotes, $(PSP_PMUD_FILE3)) \ - $(call strip_quotes, $(PSP_PMUD_FILE4)) \ - $(call strip_quotes, $(PSP_MP2CFG_FILE)) \ - $(call strip_quotes, $(PSP_SMUFW1_SUB1_FILE)) \ - $(call strip_quotes, $(PSP_SMUFW1_SUB2_FILE)) \ - $(call strip_quotes, $(PSP_SMUFW2_SUB1_FILE)) \ - $(call strip_quotes, $(PSP_SMUFW2_SUB2_FILE)) \ - $(call strip_quotes, $(PSP_ABL0_FILE)) \ - $(call strip_quotes, $(PSP_ABL1_FILE)) \ - $(call strip_quotes, $(PSP_ABL2_FILE)) \ - $(call strip_quotes, $(PSP_ABL3_FILE)) \ - $(call strip_quotes, $(PSP_ABL4_FILE)) \ - $(call strip_quotes, $(PSP_ABL5_FILE)) \ - $(call strip_quotes, $(PSP_ABL6_FILE)) \ - $(call strip_quotes, $(PSP_ABL7_FILE)) \ - $(call strip_quotes, $(PSP_WHITELIST_FILE)) \ - $(call strip_quotes, $(PSP_SECG1_FILE)) \ - $(call strip_quotes, $(PSP_SECG2_FILE)) \ - $(call_strip_quotes, $(PSP_DRIVERS_FILE)) \ - $(call_strip_quotes, $(PSP_S0I3_FILE)) \ - $(call_strip_quotes, $(PSP_IKEK_FILE)) \ - $(call_strip_quotes, $(PSP_SEC_DEBUG_FILE)) \ +$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ $(PSP_VERSTAGE_FILE) \ $(PSP_VERSTAGE_SIG_FILE) \ $$(PSP_APCB_FILES) \ + $(DEP_FILES) \ $(AMDFWTOOL) \ $(obj)/fmap_config.h $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) diff --git a/src/soc/amd/picasso/fw.cfg b/src/soc/amd/picasso/fw.cfg new file mode 100644 index 0000000000..e746d1e299 --- /dev/null +++ b/src/soc/amd/picasso/fw.cfg @@ -0,0 +1,39 @@ +# PSP fw config file + +FIRMWARE_LOCATE 3rdparty/amd_blobs/picasso/PSP + +# type file +AMD_PUBKEY_FILE AmdPubKeyRV.bin +PSPBTLDR_FILE PspBootLoader_prod_RV.sbin +PSPBTLDR_WL_FILE PspBootLoader_WL_RV.sbin +PSP_SMUFW1_SUB1_FILE SmuFirmwareRV2.csbin +PSP_SMUFW1_SUB2_FILE SmuFirmwarePCO.csbin +PSP_SMUFW2_SUB1_FILE SmuFirmware2RV2.csbin +PSP_SMUFW2_SUB2_FILE SmuFirmware2PCO.csbin +PSPSECUREOS_FILE psp_os_combined_prod_RV.sbin +PSP_SEC_DBG_KEY_FILE RavenSecureDebug_PublicKey.bin +PSP_SEC_DEBUG_FILE secure_unlock_prod_RV.sbin +PSP_ABL0_FILE AgesaBootloader0_prod_RV.csbin +PSP_ABL1_FILE AgesaBootloader1_prod_RV.csbin +PSP_ABL2_FILE AgesaBootloader2_prod_RV.csbin +PSP_ABL3_FILE AgesaBootloader3_prod_RV.csbin +PSP_ABL4_FILE AgesaBootloader4_prod_RV.csbin +PSP_ABL5_FILE AgesaBootloader5_prod_RV.csbin +PSP_ABL6_FILE AgesaBootloader6_prod_RV.csbin +PSP_ABL7_FILE AgesaBootloader7_prod_RV.csbin +PSP_IKEK_FILE PspIkekRV.bin +PSP_SECG1_FILE security_policy_RV2_FP5_AM4.sbin +PSP_SECG2_FILE security_policy_PCO_FP5_AM4.sbin +PSP_MP2FW1_FILE MP2I2CFWRV2.sbin +PSP_MP2FW2_FILE MP2I2CFWPCO.sbin +PSP_MP2CFG_FILE MP2FWConfig.sbin +PSP_DRIVERS_FILE drv_sys_prod_RV.sbin +# BDT +PSP_PMUI_FILE1 Appb_Rv_1D_Ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE2 Appb_Rv_2D_Ddr4_Imem.csbin +PSP_PMUI_FILE3 Appb_Rv2_1D_ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE4 Appb_Rv2_2D_ddr4_Udimm_Imem.csbin +PSP_PMUD_FILE1 Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE2 Appb_Rv_2D_Ddr4_Dmem.csbin +PSP_PMUD_FILE3 Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE4 Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 2ef90eb5f4..0e32005fb0 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -190,12 +190,13 @@ config STONEYRIDGE_GEC_FWM_FILE string "GEC firmware path and filename" depends on STONEYRIDGE_GEC_FWM -config AMD_PUBKEY_FILE - string "AMD public Key" +config AMDFW_CONFIG_FILE + string + string "AMD PSP Firmware config file" default "" if !USE_AMD_BLOBS - default "3rdparty/amd_blobs/stoneyridge/PSP/CZ/AmdPubKeyCZ.bin" if AMD_APU_MERLINFALCON - default "3rdparty/amd_blobs/stoneyridge/PSP/ST/AmdPubKeyST.bin" if AMD_APU_PRAIRIEFALCON - default "3rdparty/amd_blobs/stoneyridge/PSP/ST/AmdPubKeyST.bin" if AMD_APU_STONEYRIDGE + default "src/soc/amd/stoneyridge/fw_cz.cfg" if AMD_APU_MERLINFALCON + default "src/soc/amd/stoneyridge/fw_st.cfg" if AMD_APU_PRAIRIEFALCON + default "src/soc/amd/stoneyridge/fw_st.cfg" if AMD_APU_STONEYRIDGE config STONEYRIDGE_SATA_MODE int "SATA Mode" diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 16597e1eda..9211e81476 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -101,7 +101,9 @@ STONEYRIDGE_FWM_POSITION=$(call int-add, \ 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) ### 0 -FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) + +FIRMWARE_LOCATE=$(shell grep -e FIRMWARE_LOCATE $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') + ifneq ($(FIRMWARE_LOCATE),) ifeq ($(CONFIG_AMD_APU_STONEYRIDGE),y) @@ -119,134 +121,47 @@ endif # CONFIG_AMD_APU_PRAIRIEFALCON endif # CONFIG_AMD_APU_MERLINFALCON endif # CONFIG_AMD_APU_STONEYRIDGE -###5 -PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key +add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) -###1 -PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_$(FIRMWARE_TYPE).sbin +OPT_STONEYRIDGE_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE), --xhci) +OPT_STONEYRIDGE_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE), --gec) -###3 -PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_$(FIRMWARE_TYPE).sbin +SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/$(shell awk '($$1=="PSP_SMUFW1_SUB0_FILE") {print $$2}' $(CONFIG_AMDFW_CONFIG_FILE)) +SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/$(shell awk '($$1=="PSP_SMUFW1_SUB1_FILE") {print $$2}' $(CONFIG_AMDFW_CONFIG_FILE)) -###4 -PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin - -###8 - Check for SMU firmware named either *.sbin or *.csbin. Both "signed" and -### "compressed signed" are used by generations supported by this file. -SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware_$(FIRMWARE_TYPE).csbin -SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware_$(FIRMWARE_TYPE)_FN.csbin -ifeq ("$(wildcard $(SMUFWM_FILE))","") -SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin -SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE)_FN.sbin -endif - -###95 -SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin - -###9 -PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key - -ifeq ($(CONFIG_USE_PSPSECUREOS),y) -###2 -PSPSECUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_$(FIRMWARE_TYPE).csbin - -###12 -PSPTRUSTLETS_FILE=$(wildcard $(top)/$(FIRMWARE_LOCATE)/PspTrustlets*_prod_$(FIRMWARE_TYPE).cbin) - -###13 -TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_$(FIRMWARE_TYPE).sbin -endif - -###18- Check for SMU firmware2 named either *.sbin or *.csbin -### TODO: Remove *.sbin section after the blobs repo is updated. -SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).csbin -SMUFIRMWARE2_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE)_FN.csbin -ifeq ("$(wildcard $(SMUFIRMWARE2_FILE))","") -SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).sbin -SMUFIRMWARE2_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE)_FN.sbin -endif +SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/$(shell awk '($$1=="PSP_SMUFW2_SUB0_FILE") {print $$2}' $(CONFIG_AMDFW_CONFIG_FILE)) +SMUFIRMWARE2_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/$(shell awk '($$1=="PSP_SMUFW2_SUB1_FILE") {print $$2}' $(CONFIG_AMDFW_CONFIG_FILE)) ifeq ("$(wildcard $(SMUFWM_FN_FILE))","") SMUFWM_FN_FILE= SMUFIRMWARE2_FN_FILE= endif -add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) - -OPT_STONEYRIDGE_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE), --xhci) -OPT_STONEYRIDGE_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_GEC_FWM_FILEddd), --gec) - -OPT_AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey) -OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(PSPBTLDR_FILE), --bootloader) -OPT_SMUFWM_FILE=$(call add_opt_prefix, $(SMUFWM_FILE), --smufirmware) -OPT_PSPRCVR_FILE=$(call add_opt_prefix, $(PSPRCVR_FILE), --recovery) -OPT_PUBSIGNEDKEY_FILE=$(call add_opt_prefix, $(PUBSIGNEDKEY_FILE), --rtmpubkey) -OPT_PSPNVRAM_FILE=$(call add_opt_prefix, $(PSPNVRAM_FILE), --nvram) -OPT_PSPSECUREDEBUG_FILE=$(call add_opt_prefix, $(PSPSECUREDEBUG_FILE), --securedebug) -ifeq ($(CONFIG_USE_PSPSECUREOS),y) -OPT_PSPSECUREOS_FILE=$(call add_opt_prefix, $(PSPSECUREOS_FILE), --secureos) -OPT_PSPTRUSTLETS_FILE=$(call add_opt_prefix, $(PSPTRUSTLETS_FILE), --trustlets) -OPT_TRUSTLETKEY_FILE=$(call add_opt_prefix, $(TRUSTLETKEY_FILE), --trustletkey) -endif -OPT_SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FILE), --smufirmware2) -OPT_SMUSCS_FILE=$(call add_opt_prefix, $(SMUSCS_FILE), --smuscs) -SUBPROG_FN_SMU_FW=1 -OPT_SMUFWM_FN_FILE=$(call add_opt_prefix, $(SMUFWM_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware) -OPT_SMUFIRMWARE2_FN_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware2) - ifeq ($(FIRMWARE_TYPE),ST) OPT_COMBOCAPABLE=--combo-capable endif +ifeq ($(CONFIG_USE_PSPSECUREOS),y) +PSP_USE_PSPSECUREOS="--use-pspsecureos" +endif + +OPT_PSP_USE_PSPSECUREOS=$(call strip_quotes, $(PSP_USE_PSPSECUREOS)) + +# Add all the files listed in the config file +DEP_FILES=$(shell $(AMDFWTOOL) --config $(CONFIG_AMDFW_CONFIG_FILE) --depend) + $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ - $(call strip_quotes, $(PUBSIGNEDKEY_FILE)) \ - $(call strip_quotes, $(PSPBTLDR_FILE)) \ - $(call strip_quotes, $(PSPRCVR_FILE)) \ - $(call strip_quotes, $(PSPSECUREOS_FILE)) \ - $(call strip_quotes, $(PSPNVRAM_FILE)) \ - $(call strip_quotes, $(SMUFWM_FILE)) \ - $(call strip_quotes, $(SMUFWM_FN_FILE)) \ - $(call strip_quotes, $(SMUSCS_FILE)) \ - $(call strip_quotes, $(PSPSECUREDEBUG_FILE)) \ - $(call strip_quotes, $(PSPTRUSTLETS_FILE)) \ - $(call strip_quotes, $(TRUSTLETKEY_FILE)) \ - $(call strip_quotes, $(SMUFIRMWARE2_FILE)) \ - $(call strip_quotes, $(SMUFIRMWARE2_FN_FILE)) \ + $(DEP_FILES) \ $(AMDFWTOOL) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ $(OPT_STONEYRIDGE_XHCI_FWM_FILE) \ $(OPT_STONEYRIDGE_GEC_FWM_FILE) \ - $(OPT_AMD_PUBKEY_FILE) \ - $(OPT_PSPBTLDR_FILE) \ - $(OPT_SMUFWM_FILE) \ - $(OPT_PSPRCVR_FILE) \ - $(OPT_PUBSIGNEDKEY_FILE) \ - $(OPT_PSPSECUREOS_FILE) \ - $(OPT_PSPNVRAM_FILE) \ - $(OPT_PSPSECUREDEBUG_FILE) \ - $(OPT_PSPTRUSTLETS_FILE) \ - $(OPT_TRUSTLETKEY_FILE) \ - $(OPT_SMUFIRMWARE2_FILE) \ - $(OPT_SMUSCS_FILE) \ - $(OPT_AMD_PUBKEY_FILE) \ - $(OPT_PSPBTLDR_FILE) \ - $(OPT_SMUFWM_FILE) \ - $(OPT_SMUFWM_FN_FILE) \ - $(OPT_PSPRCVR_FILE) \ - $(OPT_PUBSIGNEDKEY_FILE) \ - $(OPT_PSPSECUREOS_FILE) \ - $(OPT_PSPNVRAM_FILE) \ - $(OPT_PSPSECUREDEBUG_FILE) \ - $(OPT_PSPTRUSTLETS_FILE) \ - $(OPT_TRUSTLETKEY_FILE) \ - $(OPT_SMUFIRMWARE2_FILE) \ - $(OPT_SMUFIRMWARE2_FN_FILE) \ - $(OPT_SMUSCS_FILE) \ $(OPT_COMBOCAPABLE)\ + $(OPT_PSP_USE_PSPSECUREOS) \ + --config $(CONFIG_AMDFW_CONFIG_FILE) \ --flashsize $(CONFIG_ROM_SIZE) \ --location $(shell printf "0x%x" $(STONEYRIDGE_FWM_POSITION)) \ --output $@ diff --git a/src/soc/amd/stoneyridge/fw_cz.cfg b/src/soc/amd/stoneyridge/fw_cz.cfg new file mode 100644 index 0000000000..acbf13616b --- /dev/null +++ b/src/soc/amd/stoneyridge/fw_cz.cfg @@ -0,0 +1,18 @@ +# PSP fw config file + +FIRMWARE_LOCATE 3rdparty/amd_blobs/stoneyridge/PSP/CZ +#PSP +AMD_PUBKEY_FILE AmdPubKeyCZ.bin +PSPBTLDR_FILE PspBootLoader_prod_CZ.sbin +PSP_SMUFW1_SUB0_FILE SmuFirmwareCZ.sbin +#PSP_SMUFW1_SUB1_FILE SmuFirmware_CZ_FN.csbin +PSP_SMUFW2_SUB0_FILE SmuFirmware2_prod_CZ.sbin +#PSP_SMUFW2_SUB1_FILE SmuFirmware2_prod_CZ_FN.sbin +PSPRCVR_FILE PspRecoveryBootLoader_prod_CZ.sbin +PUBSIGNEDKEY_FILE RtmPubSignedCZ.key +PSPNVRAM_FILE PspNvramCZ.bin +PSPSECUREOS_FILE PspSecureOs_prod_CZ.csbin +SMUSCS_FILE SmuScsCZ.bin +PSPTRUSTLETS_FILE PspTrustlets_prod_CZ.cbin +TRUSTLETKEY_FILE TrustletKey_prod_CZ.sbin +PSPSECUREDEBUG_FILE PspSecureDebugCZ.Key diff --git a/src/soc/amd/stoneyridge/fw_st.cfg b/src/soc/amd/stoneyridge/fw_st.cfg new file mode 100644 index 0000000000..aa026683c0 --- /dev/null +++ b/src/soc/amd/stoneyridge/fw_st.cfg @@ -0,0 +1,20 @@ +# PSP fw config file + +FIRMWARE_LOCATE 3rdparty/amd_blobs/stoneyridge/PSP/ST + +#XHCI_FWM_FILE xhci.bin +#PSP +AMD_PUBKEY_FILE AmdPubKeyST.bin +PSPBTLDR_FILE PspBootLoader_prod_ST.sbin +PSP_SMUFW1_SUB0_FILE SmuFirmware_ST.csbin +PSP_SMUFW1_SUB1_FILE SmuFirmware_ST_FN.csbin +PSP_SMUFW2_SUB0_FILE SmuFirmware2_prod_ST.csbin +PSP_SMUFW2_SUB1_FILE SmuFirmware2_prod_ST_FN.sbin +PSPRCVR_FILE PspRecoveryBootLoader_prod_ST.sbin +PUBSIGNEDKEY_FILE RtmPubSignedST.key +PSPNVRAM_FILE PspNvramST.bin +PSPSECUREOS_FILE PspSecureOs_prod_ST.csbin +SMUSCS_FILE SmuScsST.bin +PSPTRUSTLETS_FILE PspTrustlets_prod_ST.cbin +TRUSTLETKEY_FILE TrustletKey_prod_ST.sbin +PSPSECUREDEBUG_FILE PspSecureDebugST.Key diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index b56969008b..cfe85a1952 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -63,6 +63,10 @@ config HUDSON_PSP bool default y if CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 +config AMDFW_CONFIG_FILE + string "AMD PSP Firmware config file" + default "src/southbridge/amd/pi/hudson/fw_avl.cfg" if CPU_AMD_PI_00730F01 + config HUDSON_XHCI_FWM_FILE string "XHCI firmware path and filename" default "3rdparty/blobs/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 09bf1d6682..c845f846c7 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -78,14 +78,9 @@ endif ifeq ($(CONFIG_HUDSON_PSP), y) ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) +FIRMWARE_LOCATE=$(shell grep -e FIRMWARE_LOCATE $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') FIRMWARE_TYPE= -PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader.Bypass.sbin -#PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery.sbin -#PSPSECUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs.sbin -#PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin -#TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert endif ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) @@ -102,9 +97,6 @@ endif #PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key #PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin -SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin -SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE)_FN.sbin -SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin #PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key endif @@ -128,21 +120,12 @@ OPT_TRUSTLETKEY_FILE=$(call add_opt_prefix, $(TRUSTLETKEY_FILE), --trustletkey) OPT_SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FILE), --smufirmware2) OPT_SMUSCS_FILE=$(call add_opt_prefix, $(SMUSCS_FILE), --smuscs) +# Add all the files listed in the config file +DEP_FILES=$(shell $(AMDFWTOOL) --config $(CONFIG_AMDFW_CONFIG_FILE) --depend) + $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ - $(call strip_quotes, $(PUBSIGNEDKEY_FILE)) \ - $(call strip_quotes, $(PSPBTLDR_FILE)) \ - $(call strip_quotes, $(PSPRCVR_FILE)) \ - $(call strip_quotes, $(PSPSECUREOS_FILE)) \ - $(call strip_quotes, $(PSPNVRAM_FILE)) \ - $(call strip_quotes, $(SMUFWM_FILE)) \ - $(call strip_quotes, $(SMUSCS_FILE)) \ - $(call strip_quotes, $(PSPSECUREDEBUG_FILE)) \ - $(call strip_quotes, $(PSPTRUSTLETS_FILE)) \ - $(call strip_quotes, $(TRUSTLETKEY_FILE)) \ - $(call strip_quotes, $(SMUFIRMWARE2_FILE)) \ $(call strip_quotes, $(AMD_PUBKEY2_FILE)) \ $(call strip_quotes, $(PUBSIGNEDKEY2_FILE)) \ $(call strip_quotes, $(PSPBTLDR2_FILE)) \ @@ -157,6 +140,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(call strip_quotes, $(TRUSTLETKEY2_FILE)) \ $(call strip_quotes, $(SMUFIRMWARE2_2_FILE)) \ $(call strip_quotes, $(SMUFIRMWARE2_2_FN_FILE)) \ + $(DEP_FILES) \ $(AMDFWTOOL) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" @@ -164,18 +148,6 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(OPT_HUDSON_XHCI_FWM_FILE) \ $(OPT_HUDSON_IMC_FWM_FILE) \ $(OPT_HUDSON_GEC_FWM_FILE) \ - $(OPT_AMD_PUBKEY_FILE) \ - $(OPT_PSPBTLDR_FILE) \ - $(OPT_SMUFWM_FILE) \ - $(OPT_PSPRCVR_FILE) \ - $(OPT_PUBSIGNEDKEY_FILE) \ - $(OPT_PSPSECUREOS_FILE) \ - $(OPT_PSPNVRAM_FILE) \ - $(OPT_PSPSECUREDEBUG_FILE) \ - $(OPT_PSPTRUSTLETS_FILE) \ - $(OPT_TRUSTLETKEY_FILE) \ - $(OPT_SMUFIRMWARE2_FILE) \ - $(OPT_SMUSCS_FILE) \ $(OPT_2AMD_PUBKEY_FILE) \ $(OPT_2PSPBTLDR_FILE) \ $(OPT_2SMUFWM_FILE) \ @@ -192,6 +164,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(OPT_2SMUSCS_FILE) \ --flashsize $(CONFIG_ROM_SIZE) \ --location $(HUDSON_FWM_POSITION) \ + --config $(CONFIG_AMDFW_CONFIG_FILE) \ --output $@ ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) diff --git a/src/southbridge/amd/pi/hudson/fw_avl.cfg b/src/southbridge/amd/pi/hudson/fw_avl.cfg new file mode 100644 index 0000000000..f65d6b822f --- /dev/null +++ b/src/southbridge/amd/pi/hudson/fw_avl.cfg @@ -0,0 +1,8 @@ +# PSP fw config file + +FIRMWARE_LOCATE 3rdparty/blobs/southbridge/amd/avalon/PSP +#PSP +AMD_PUBKEY_FILE AmdPubKey.bin +PSPBTLDR_FILE PspBootLoader.Bypass.sbin +PSP_SMUFW1_SUB0_FILE SmuFirmware.sbin +SMUSCS_FILE SmuScs.bin diff --git a/util/amdfwtool/Makefile b/util/amdfwtool/Makefile index 8f4208c354..58606e3ed0 100644 --- a/util/amdfwtool/Makefile +++ b/util/amdfwtool/Makefile @@ -2,7 +2,7 @@ HOSTCC ?= cc -SRC = amdfwtool.c +SRC = amdfwtool.c data_parse.c OBJ = $(SRC:%.c=%.o) TARGET = amdfwtool CFLAGS=-O2 -Wall -Wextra -Wshadow diff --git a/util/amdfwtool/Makefile.inc b/util/amdfwtool/Makefile.inc index b1a21308fd..e794ed9009 100644 --- a/util/amdfwtool/Makefile.inc +++ b/util/amdfwtool/Makefile.inc @@ -1,6 +1,6 @@ # SPDX-License-Identifier: BSD-3-Clause -amdfwtoolobj = amdfwtool.o +amdfwtoolobj = amdfwtool.o data_parse.o AMDFWTOOLCFLAGS=-O2 -Wall -Wextra -Wshadow diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index f5030d381c..561b511e3d 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -56,6 +56,9 @@ #include #include #include +#include + +#include "amdfwtool.h" #define AMD_ROMSIG_OFFSET 0x20000 #define MIN_ROM_KB 256 @@ -94,13 +97,6 @@ */ #define PSP_COMBO 0 -#if defined(__GLIBC__) -typedef unsigned long long int uint64_t; -typedef unsigned int uint32_t; -typedef unsigned char uint8_t; -typedef unsigned short uint16_t; -#endif - /* * Creates the OSI Fletcher checksum. See 8473-1, Appendix C, section C.3. * The checksum field of the passed PDU does not need to be reset to zero. @@ -165,39 +161,22 @@ static void usage(void) printf("-A | --combo-capable Place PSP directory pointer at Embedded Firmware\n"); printf(" offset able to support combo directory\n"); printf("-M | --multilevel Generate primary and secondary tables\n"); - printf("-p | --pubkey Add pubkey\n"); - printf("-b | --bootloader Add bootloader\n"); - printf("-S | --subprogram Sets subprogram field for the next firmware\n"); - printf("-s | --smufirmware Add smufirmware\n"); - printf("-r | --recovery Add recovery\n"); - printf("-k | --rtmpubkey Add rtmpubkey\n"); - printf("-c | --secureos Add secureos\n"); - printf("-n | --nvram Add nvram\n"); - printf("-d | --securedebug Add securedebug\n"); - printf("-t | --trustlets Add trustlets\n"); - printf("-u | --trustletkey Add trustletkey\n"); - printf("-w | --smufirmware2 Add smufirmware2\n"); - printf("-m | --smuscs Add smuscs\n"); - printf("-T | --soft-fuse Override default soft fuse values\n"); - printf("-z | --abl-image Add AGESA Binary\n"); - printf("-J | --sec-gasket Add security gasket\n"); - printf("-B | --mp2-fw Add MP2 firmware\n"); - printf("-N | --secdebug Add secure unlock image\n"); - printf("-U | --token-unlock Reserve space for debug token\n"); - printf("-K | --drv-entry-pts Add PSP driver entry points\n"); - printf("-L | --ikek Add Wrapped iKEK\n"); - printf("-Y | --s0i3drv Add s0i3 driver\n"); + printf("-n | --nvram Add nvram binary\n"); + printf("-T | --soft-fuse Set soft fuse\n"); + printf("-U | --token-unlock Set token unlock\n"); + printf("-W | --whitelist Set if there is a whitelist\n"); + printf("-S | --use-pspsecureos Set if psp secure OS is needed\n"); + printf("-p | --load-mp2-fw Set if load MP2 firmware\n"); + printf("-L | --load-s0i3 Set if load s0i3 firmware\n"); printf("-Z | --verstage Add verstage\n"); + printf("-E | --verstage_sig Add verstage signature"); printf("\nBIOS options:\n"); printf("-I | --instance Sets instance field for the next BIOS firmware\n"); printf("-a | --apcb Add AGESA PSP customization block\n"); printf("-Q | --apob-base Destination for AGESA PSP output block\n"); printf("-F | --apob-nv-base Location of S3 resume data\n"); printf("-H | --apob-nv-size Size of S3 resume data\n"); - printf("-y | --pmu-inst Add PMU firmware instruction portion\n"); - printf("-G | --pmu-data Add PMU firmware data portion\n"); printf("-O | --ucode Add microcode patch\n"); - printf("-X | --mp2-config Add MP2 configuration\n"); printf("-V | --bios-bin Add compressed image; auto source address\n"); printf("-e | --bios-bin-src Address in flash of source if -V not used\n"); printf("-v | --bios-bin-dest Destination for uncompressed BIOS\n"); @@ -236,93 +215,11 @@ static void usage(void) printf(" 0x1 Micron parts are always used\n"); printf(" 0x2 Micron parts optional, this option is only\n"); printf(" supported with RN/LCN SOC\n"); + printf("-c | --config Config file\n"); + printf("-D | --depend List out the firmware files\n"); } -typedef enum _amd_bios_type { - AMD_BIOS_APCB = 0x60, - AMD_BIOS_APOB = 0x61, - AMD_BIOS_BIN = 0x62, - AMD_BIOS_APOB_NV = 0x63, - AMD_BIOS_PMUI = 0x64, - AMD_BIOS_PMUD = 0x65, - AMD_BIOS_UCODE = 0x66, - AMD_BIOS_APCB_BK = 0x68, - AMD_BIOS_MP2_CFG = 0x6a, - AMD_BIOS_PSP_SHARED_MEM = 0x6b, - AMD_BIOS_L2_PTR = 0x70, - AMD_BIOS_INVALID, -} amd_bios_type; - -#define BDT_LVL1 0x1 -#define BDT_LVL2 0x2 -#define BDT_BOTH (BDT_LVL1 | BDT_LVL2) -typedef struct _amd_bios_entry { - amd_bios_type type; - int region_type; - int reset; - int copy; - int ro; - int zlib; - int inst; - int subpr; - uint64_t src; - uint64_t dest; - size_t size; - char *filename; - int level; -} amd_bios_entry; - -typedef enum _amd_fw_type { - AMD_FW_PSP_PUBKEY = 0, - AMD_FW_PSP_BOOTLOADER = 1, - AMD_FW_PSP_SMU_FIRMWARE = 8, - AMD_FW_PSP_RECOVERY = 3, - AMD_FW_PSP_RTM_PUBKEY = 5, - AMD_FW_PSP_SECURED_OS = 2, - AMD_FW_PSP_NVRAM = 4, - AMD_FW_PSP_SECURED_DEBUG = 9, - AMD_FW_PSP_TRUSTLETS = 12, - AMD_FW_PSP_TRUSTLETKEY = 13, - AMD_FW_PSP_SMU_FIRMWARE2 = 18, - AMD_PSP_FUSE_CHAIN = 11, - AMD_FW_PSP_SMUSCS = 95, - AMD_DEBUG_UNLOCK = 0x13, - AMD_WRAPPED_IKEK = 0x21, - AMD_TOKEN_UNLOCK = 0x22, - AMD_SEC_GASKET = 0x24, - AMD_MP2_FW = 0x25, - AMD_DRIVER_ENTRIES = 0x28, - AMD_S0I3_DRIVER = 0x2d, - AMD_ABL0 = 0x30, - AMD_ABL1 = 0x31, - AMD_ABL2 = 0x32, - AMD_ABL3 = 0x33, - AMD_ABL4 = 0x34, - AMD_ABL5 = 0x35, - AMD_ABL6 = 0x36, - AMD_ABL7 = 0x37, - AMD_FW_PSP_WHITELIST = 0x3a, - AMD_FW_L2_PTR = 0x40, - AMD_FW_PSP_VERSTAGE = 0x52, - AMD_FW_VERSTAGE_SIG = 0x53, - AMD_FW_IMC, - AMD_FW_GEC, - AMD_FW_XHCI, - AMD_FW_INVALID, -} amd_fw_type; - -#define PSP_LVL1 0x1 -#define PSP_LVL2 0x2 -#define PSP_BOTH (PSP_LVL1 | PSP_LVL2) -typedef struct _amd_fw_entry { - amd_fw_type type; - uint8_t subprog; - char *filename; - int level; - uint64_t other; -} amd_fw_entry; - -static amd_fw_entry amd_psp_fw_table[] = { +amd_fw_entry amd_psp_fw_table[] = { { .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH }, { .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH }, { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH }, @@ -365,14 +262,14 @@ static amd_fw_entry amd_psp_fw_table[] = { { .type = AMD_FW_INVALID }, }; -static amd_fw_entry amd_fw_table[] = { +amd_fw_entry amd_fw_table[] = { { .type = AMD_FW_XHCI }, { .type = AMD_FW_IMC }, { .type = AMD_FW_GEC }, { .type = AMD_FW_INVALID }, }; -static amd_bios_entry amd_bios_table[] = { +amd_bios_entry amd_bios_table[] = { { .type = AMD_BIOS_APCB, .inst = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB, .inst = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB, .inst = 2, .level = BDT_BOTH }, @@ -699,6 +596,33 @@ static void integrate_firmwares(context *ctx, } } +static void free_psp_firmware_filenames(amd_fw_entry *fw_table) +{ + amd_fw_entry *index; + + for (index = fw_table; index->type != AMD_FW_INVALID; index++) { + if (index->filename && + index->type != AMD_FW_VERSTAGE_SIG && + index->type != AMD_FW_PSP_VERSTAGE && + index->type != AMD_FW_PSP_WHITELIST) { + free(index->filename); + } + } +} + +static void free_bdt_firmware_filenames(amd_bios_entry *fw_table) +{ + amd_bios_entry *index; + + for (index = fw_table; index->type != AMD_BIOS_INVALID; index++) { + if (index->filename && + index->type != AMD_BIOS_APCB && + index->type != AMD_BIOS_BIN && + index->type != AMD_BIOS_APCB_BK) + free(index->filename); + } +} + static void integrate_psp_firmwares(context *ctx, psp_directory_table *pspdir, psp_directory_table *pspdir2, @@ -1083,8 +1007,9 @@ enum { LONGOPT_SPI_MICRON_FLAG = 258, }; -// Unused values: D -static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:C:E:"; +/* Unused values: BGJKNXYbdkmprstuwyz*/ +static const char *optstring = "x:i:g:AMn:T:SPLUW:I:a:Q:V:e:v:j:O:F:" + "H:o:f:l:hZ:qR:C:c:E:D"; static struct option long_options[] = { {"xhci", required_argument, 0, 'x' }, @@ -1093,29 +1018,13 @@ static struct option long_options[] = { /* PSP Directory Table items */ {"combo-capable", no_argument, 0, 'A' }, {"multilevel", no_argument, 0, 'M' }, - {"subprogram", required_argument, 0, 'S' }, - {"pubkey", required_argument, 0, 'p' }, - {"bootloader", required_argument, 0, 'b' }, - {"smufirmware", required_argument, 0, 's' }, - {"recovery", required_argument, 0, 'r' }, - {"rtmpubkey", required_argument, 0, 'k' }, - {"secureos", required_argument, 0, 'c' }, {"nvram", required_argument, 0, 'n' }, - {"securedebug", required_argument, 0, 'd' }, - {"trustlets", required_argument, 0, 't' }, - {"trustletkey", required_argument, 0, 'u' }, - {"smufirmware2", required_argument, 0, 'w' }, - {"smuscs", required_argument, 0, 'm' }, {"soft-fuse", required_argument, 0, 'T' }, - {"abl-image", required_argument, 0, 'z' }, - {"sec-gasket", required_argument, 0, 'J' }, - {"mp2-fw", required_argument, 0, 'B' }, - {"drv-entry-pts", required_argument, 0, 'K' }, - {"ikek", required_argument, 0, 'L' }, - {"s0i3drv", required_argument, 0, 'Y' }, - {"secdebug", required_argument, 0, 'N' }, {"token-unlock", no_argument, 0, 'U' }, {"whitelist", required_argument, 0, 'W' }, + {"use-pspsecureos", no_argument, 0, 'S' }, + {"load-mp2-fw", no_argument, 0, 'p' }, + {"load-s0i3", no_argument, 0, 'L' }, {"verstage", required_argument, 0, 'Z' }, {"verstage_sig", required_argument, 0, 'E' }, /* BIOS Directory Table items */ @@ -1126,10 +1035,7 @@ static struct option long_options[] = { {"bios-bin-src", required_argument, 0, 'e' }, {"bios-bin-dest", required_argument, 0, 'v' }, {"bios-uncomp-size", required_argument, 0, 'j' }, - {"pmu-inst", required_argument, 0, 'y' }, - {"pmu-data", required_argument, 0, 'G' }, {"ucode", required_argument, 0, 'O' }, - {"mp2-config", required_argument, 0, 'X' }, {"apob-nv-base", required_argument, 0, 'F' }, {"apob-nv-size", required_argument, 0, 'H' }, /* Embedded Firmware Structure items*/ @@ -1144,11 +1050,14 @@ static struct option long_options[] = { {"sharedmem", required_argument, 0, 'R' }, {"sharedmem-size", required_argument, 0, 'P' }, {"soc-name", required_argument, 0, 'C' }, + + {"config", required_argument, 0, 'c' }, {"help", no_argument, 0, 'h' }, + {"depend", no_argument, 0, 'D' }, {NULL, 0, 0, 0 } }; -static void register_fw_fuse(char *str) +void register_fw_fuse(char *str) { uint32_t i; @@ -1325,11 +1234,11 @@ int main(int argc, char **argv) int comboable = 0; int fuse_defined = 0; int targetfd; - char *output = NULL; + char *output = NULL, *config = NULL; + FILE *config_handle; context ctx = { 0 }; /* Values cleared after each firmware or parameter, regardless if N/A */ uint8_t sub = 0, instance = 0; - int abl_image = 0; uint32_t dir_location = 0; bool any_location = 0; uint32_t romsig_offset; @@ -1340,6 +1249,14 @@ int main(int argc, char **argv) uint8_t efs_spi_micron_flag = 0xff; int multi = 0; + amd_cb_config cb_config; + int list_deps = 0; + + cb_config.have_whitelist = 0; + cb_config.unlock_secure = 0; + cb_config.use_secureos = 0; + cb_config.load_mp2_fw = 0; + cb_config.s0i3 = 0; while (1) { int optindex = 0; @@ -1370,69 +1287,22 @@ int main(int argc, char **argv) break; case 'U': register_fw_token_unlock(); + cb_config.unlock_secure = 1; sub = instance = 0; break; case 'S': - sub = (uint8_t)strtoul(optarg, &tmp, 16); + cb_config.use_secureos = 1; break; case 'I': instance = strtoul(optarg, &tmp, 16); break; case 'p': - register_fw_filename(AMD_FW_PSP_PUBKEY, sub, optarg); - sub = instance = 0; - break; - case 'b': - register_fw_filename(AMD_FW_PSP_BOOTLOADER, - sub, optarg); - sub = instance = 0; - break; - case 's': - register_fw_filename(AMD_FW_PSP_SMU_FIRMWARE, - sub, optarg); - sub = instance = 0; - break; - case 'r': - register_fw_filename(AMD_FW_PSP_RECOVERY, sub, optarg); - sub = instance = 0; - break; - case 'k': - register_fw_filename(AMD_FW_PSP_RTM_PUBKEY, - sub, optarg); - sub = instance = 0; - break; - case 'c': - register_fw_filename(AMD_FW_PSP_SECURED_OS, - sub, optarg); - sub = instance = 0; + cb_config.load_mp2_fw = 1; break; case 'n': register_fw_filename(AMD_FW_PSP_NVRAM, sub, optarg); sub = instance = 0; break; - case 'd': - register_fw_filename(AMD_FW_PSP_SECURED_DEBUG, - sub, optarg); - sub = instance = 0; - break; - case 't': - register_fw_filename(AMD_FW_PSP_TRUSTLETS, sub, optarg); - sub = instance = 0; - break; - case 'u': - register_fw_filename(AMD_FW_PSP_TRUSTLETKEY, - sub, optarg); - sub = instance = 0; - break; - case 'w': - register_fw_filename(AMD_FW_PSP_SMU_FIRMWARE2, - sub, optarg); - sub = instance = 0; - break; - case 'm': - register_fw_filename(AMD_FW_PSP_SMUSCS, sub, optarg); - sub = instance = 0; - break; case 'T': register_fw_fuse(optarg); fuse_defined = 1; @@ -1478,56 +1348,18 @@ int main(int argc, char **argv) register_fw_addr(AMD_BIOS_BIN, 0, 0, optarg); sub = instance = 0; break; - case 'y': - register_bdt_data(AMD_BIOS_PMUI, sub, instance, optarg); - sub = instance = 0; - break; - case 'G': - register_bdt_data(AMD_BIOS_PMUD, sub, instance, optarg); - sub = instance = 0; - break; case 'O': register_bdt_data(AMD_BIOS_UCODE, sub, instance, optarg); sub = instance = 0; break; - case 'J': - register_fw_filename(AMD_SEC_GASKET, sub, optarg); - sub = instance = 0; - break; - case 'B': - register_fw_filename(AMD_MP2_FW, sub, optarg); - sub = instance = 0; - break; - case 'z': - register_fw_filename(AMD_ABL0 + abl_image++, - sub, optarg); - sub = instance = 0; - break; - case 'X': - register_bdt_data(AMD_BIOS_MP2_CFG, sub, - instance, optarg); - sub = instance = 0; - break; - case 'K': - register_fw_filename(AMD_DRIVER_ENTRIES, sub, optarg); - sub = instance = 0; - break; case 'L': - register_fw_filename(AMD_WRAPPED_IKEK, sub, optarg); - sub = instance = 0; - break; - case 'Y': - register_fw_filename(AMD_S0I3_DRIVER, sub, optarg); - sub = instance = 0; - break; - case 'N': - register_fw_filename(AMD_DEBUG_UNLOCK, sub, optarg); - sub = instance = 0; + cb_config.s0i3 = 1; break; case 'W': register_fw_filename(AMD_FW_PSP_WHITELIST, sub, optarg); sub = instance = 0; + cb_config.have_whitelist = 1; break; case 'Z': register_fw_filename(AMD_FW_PSP_VERSTAGE, sub, optarg); @@ -1590,30 +1422,50 @@ int main(int argc, char **argv) sub = instance = 0; break; + case 'c': + config = optarg; + break; case 'h': usage(); return 0; + case 'D': + list_deps = 1; + break; default: break; } } + if (config) { + config_handle = fopen(config, "r"); + if (config_handle == NULL) { + fprintf(stderr, "Can not open file %s for reading: %s\n", + config, strerror(errno)); + exit(1); + } + if (process_config(config_handle, &cb_config, list_deps) == 0) { + fprintf(stderr, "Configuration file %s parsing error\n", config); + fclose(config_handle); + exit(1); + } + fclose(config_handle); + } if (!fuse_defined) register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN); - if (!output) { - printf("Error: Output value is not specified.\n\n"); + if (!output && !list_deps) { + fprintf(stderr, "Error: Output value is not specified.\n\n"); retval = 1; } - if (ctx.rom_size % 1024 != 0) { - printf("Error: ROM Size (%d bytes) should be a multiple of" + if ((ctx.rom_size % 1024 != 0) && !list_deps) { + fprintf(stderr, "Error: ROM Size (%d bytes) should be a multiple of" " 1024 bytes.\n\n", ctx.rom_size); retval = 1; } - if (ctx.rom_size < MIN_ROM_KB * 1024) { - printf("Error: ROM Size (%dKB) must be at least %dKB.\n\n", + if ((ctx.rom_size < MIN_ROM_KB * 1024) && !list_deps) { + fprintf(stderr, "Error: ROM Size (%dKB) must be at least %dKB.\n\n", ctx.rom_size / 1024, MIN_ROM_KB); retval = 1; } @@ -1623,6 +1475,10 @@ int main(int argc, char **argv) return retval; } + if (list_deps) { + return retval; + } + printf(" AMDFWTOOL Using ROM size of %dKB\n", ctx.rom_size / 1024); rom_base_address = 0xFFFFFFFF - ctx.rom_size + 1; @@ -1745,6 +1601,10 @@ int main(int argc, char **argv) amd_romsig->bios1_entry = BUFF_TO_RUN(ctx, biosdir); } + /* Free the filename. */ + free_psp_firmware_filenames(amd_psp_fw_table); + free_bdt_firmware_filenames(amd_bios_table); + targetfd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0666); if (targetfd >= 0) { ssize_t bytes; diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h new file mode 100644 index 0000000000..198642c077 --- /dev/null +++ b/util/amdfwtool/amdfwtool.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _AMD_FW_TOOL_H_ +#define _AMD_FW_TOOL_H_ + +#if defined(__GLIBC__) +typedef unsigned long long int uint64_t; +typedef unsigned int uint32_t; +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +#endif + + +typedef enum _amd_fw_type { + AMD_FW_PSP_PUBKEY = 0, + AMD_FW_PSP_BOOTLOADER = 1, + AMD_FW_PSP_SMU_FIRMWARE = 8, + AMD_FW_PSP_RECOVERY = 3, + AMD_FW_PSP_RTM_PUBKEY = 5, + AMD_FW_PSP_SECURED_OS = 2, + AMD_FW_PSP_NVRAM = 4, + AMD_FW_PSP_SECURED_DEBUG = 9, + AMD_FW_PSP_TRUSTLETS = 12, + AMD_FW_PSP_TRUSTLETKEY = 13, + AMD_FW_PSP_SMU_FIRMWARE2 = 18, + AMD_PSP_FUSE_CHAIN = 11, + AMD_FW_PSP_SMUSCS = 95, + AMD_DEBUG_UNLOCK = 0x13, + AMD_WRAPPED_IKEK = 0x21, + AMD_TOKEN_UNLOCK = 0x22, + AMD_SEC_GASKET = 0x24, + AMD_MP2_FW = 0x25, + AMD_DRIVER_ENTRIES = 0x28, + AMD_S0I3_DRIVER = 0x2d, + AMD_ABL0 = 0x30, + AMD_ABL1 = 0x31, + AMD_ABL2 = 0x32, + AMD_ABL3 = 0x33, + AMD_ABL4 = 0x34, + AMD_ABL5 = 0x35, + AMD_ABL6 = 0x36, + AMD_ABL7 = 0x37, + AMD_FW_PSP_WHITELIST = 0x3a, + AMD_FW_L2_PTR = 0x40, + AMD_FW_PSP_VERSTAGE = 0x52, + AMD_FW_VERSTAGE_SIG = 0x53, + AMD_FW_IMC = 0x200, /* Large enough to be larger than the top BHD entry type. */ + AMD_FW_GEC, + AMD_FW_XHCI, + AMD_FW_INVALID, /* Real last one to detect the last entry in table. */ + AMD_FW_SKIP /* This is for non-applicable options. */ +} amd_fw_type; + +typedef enum _amd_bios_type { + AMD_BIOS_APCB = 0x60, + AMD_BIOS_APOB = 0x61, + AMD_BIOS_BIN = 0x62, + AMD_BIOS_APOB_NV = 0x63, + AMD_BIOS_PMUI = 0x64, + AMD_BIOS_PMUD = 0x65, + AMD_BIOS_UCODE = 0x66, + AMD_BIOS_APCB_BK = 0x68, + AMD_BIOS_MP2_CFG = 0x6a, + AMD_BIOS_PSP_SHARED_MEM = 0x6b, + AMD_BIOS_L2_PTR = 0x70, + AMD_BIOS_INVALID, + AMD_BIOS_SKIP +} amd_bios_type; + + +#define BDT_LVL1 0x1 +#define BDT_LVL2 0x2 +#define BDT_BOTH (BDT_LVL1 | BDT_LVL2) +typedef struct _amd_bios_entry { + amd_bios_type type; + char *filename; + int subpr; + int region_type; + int reset; + int copy; + int ro; + int zlib; + int inst; + uint64_t src; + uint64_t dest; + size_t size; + int level; +} amd_bios_entry; + + +#define PSP_LVL1 0x1 +#define PSP_LVL2 0x2 +#define PSP_BOTH (PSP_LVL1 | PSP_LVL2) +typedef struct _amd_fw_entry { + amd_fw_type type; + char *filename; + uint8_t subprog; + int level; + uint64_t other; +} amd_fw_entry; + +typedef struct _amd_cb_config { + uint8_t have_whitelist; + uint8_t unlock_secure; + uint8_t use_secureos; + uint8_t load_mp2_fw; + uint8_t s0i3; +} amd_cb_config; + +void register_fw_fuse(char *str); +uint8_t process_config(FILE *config, amd_cb_config *cb_config, uint8_t print_deps); + +#define OK 0 + +#define LINE_EOF (1) +#define LINE_TOO_LONG (2) + + +#endif /* _AMD_FW_TOOL_H_ */ diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c new file mode 100644 index 0000000000..bb616d3405 --- /dev/null +++ b/util/amdfwtool/data_parse.c @@ -0,0 +1,418 @@ +#include +#include +#include +#include + +#include "amdfwtool.h" + +/* TODO: a empty line does not matched. */ +static const char blank_or_comment_regex[] = + /* a blank line */ + "(^[[:space:]]*$)" + "|" /* or ... */ + /* a line consisting of: optional whitespace followed by */ + "(^[[:space:]]*" + /* a '#' character and optionally, additional characters */ + "#.*$)"; +static regex_t blank_or_comment_expr; + +static const char entries_line_regex[] = + /* optional whitespace */ + "^[[:space:]]*" + /* followed by a chunk of nonwhitespace for macro field */ + "([^[:space:]]+)" + /* followed by one or more whitespace characters */ + "[[:space:]]+" + /* followed by a chunk of nonwhitespace for filename field */ + "([^[:space:]]+)" + /* followed by optional whitespace */ + "[[:space:]]*$"; +static regex_t entries_line_expr; + +void compile_reg_expr(int cflags, const char *expr, regex_t *reg) +{ + static const size_t ERROR_BUF_SIZE = 256; + char error_msg[ERROR_BUF_SIZE]; + int result; + + result = regcomp(reg, expr, cflags); + if (result != 0) { + regerror(result, reg, error_msg, ERROR_BUF_SIZE); + printf("%s\n", error_msg); + } +} + +extern amd_fw_entry amd_psp_fw_table[]; +extern amd_bios_entry amd_bios_table[]; + +static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename, + amd_cb_config *cb_config) +{ + amd_fw_type fw_type = AMD_FW_INVALID; + amd_fw_entry *psp_tableptr; + uint8_t subprog; + + if (strcmp(fw_name, "PSPBTLDR_WL_FILE") == 0) { + if (cb_config->have_whitelist == 1) { + fw_type = AMD_FW_PSP_BOOTLOADER; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } + } else if (strcmp(fw_name, "PSPBTLDR_FILE") == 0) { + if (cb_config->have_whitelist == 0) { + fw_type = AMD_FW_PSP_BOOTLOADER; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } + } else if (strcmp(fw_name, "AMD_PUBKEY_FILE") == 0) { + fw_type = AMD_FW_PSP_PUBKEY; + subprog = 0; + } else if (strcmp(fw_name, "PSPRCVR_FILE") == 0) { + fw_type = AMD_FW_PSP_RECOVERY; + subprog = 0; + } else if (strcmp(fw_name, "PUBSIGNEDKEY_FILE") == 0) { + fw_type = AMD_FW_PSP_RTM_PUBKEY; + subprog = 0; + } else if (strcmp(fw_name, "PSPNVRAM_FILE") == 0) { + fw_type = AMD_FW_PSP_NVRAM; + subprog = 0; + } else if (strcmp(fw_name, "SMUSCS_FILE") == 0) { + fw_type = AMD_FW_PSP_SMUSCS; + subprog = 0; + } else if (strcmp(fw_name, "PSPTRUSTLETS_FILE") == 0) { + fw_type = AMD_FW_PSP_TRUSTLETS; + subprog = 0; + } else if (strcmp(fw_name, "PSPSECUREDEBUG_FILE") == 0) { + fw_type = AMD_FW_PSP_SECURED_DEBUG; + subprog = 0; + } else if (strcmp(fw_name, "PSP_SMUFW1_SUB0_FILE") == 0) { + fw_type = AMD_FW_PSP_SMU_FIRMWARE; + subprog = 0; + } else if (strcmp(fw_name, "PSP_SMUFW1_SUB1_FILE") == 0) { + fw_type = AMD_FW_PSP_SMU_FIRMWARE; + subprog = 1; + } else if (strcmp(fw_name, "PSP_SMUFW1_SUB2_FILE") == 0) { + fw_type = AMD_FW_PSP_SMU_FIRMWARE; + subprog = 2; + } else if (strcmp(fw_name, "PSP_SMUFW2_SUB0_FILE") == 0) { + fw_type = AMD_FW_PSP_SMU_FIRMWARE2; + subprog = 0; + } else if (strcmp(fw_name, "PSP_SMUFW2_SUB1_FILE") == 0) { + fw_type = AMD_FW_PSP_SMU_FIRMWARE2; + subprog = 1; + } else if (strcmp(fw_name, "PSP_SMUFW2_SUB2_FILE") == 0) { + fw_type = AMD_FW_PSP_SMU_FIRMWARE2; + subprog = 2; + } else if (strcmp(fw_name, "PSP_SEC_DBG_KEY_FILE") == 0) { + if (cb_config->unlock_secure == 1) { + fw_type = AMD_FW_PSP_SECURED_DEBUG; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } + } else if (strcmp(fw_name, "PSP_SEC_DEBUG_FILE") == 0) { + if (cb_config->unlock_secure == 1) { + fw_type = AMD_DEBUG_UNLOCK; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } + } else if (strcmp(fw_name, "PSP_ABL0_FILE") == 0) { + fw_type = AMD_ABL0; + subprog = 0; + } else if (strcmp(fw_name, "PSP_ABL1_FILE") == 0) { + fw_type = AMD_ABL1; + subprog = 0; + } else if (strcmp(fw_name, "PSP_ABL2_FILE") == 0) { + fw_type = AMD_ABL2; + subprog = 0; + } else if (strcmp(fw_name, "PSP_ABL3_FILE") == 0) { + fw_type = AMD_ABL3; + subprog = 0; + } else if (strcmp(fw_name, "PSP_ABL4_FILE") == 0) { + fw_type = AMD_ABL4; + subprog = 0; + } else if (strcmp(fw_name, "PSP_ABL5_FILE") == 0) { + fw_type = AMD_ABL5; + subprog = 0; + } else if (strcmp(fw_name, "PSP_ABL6_FILE") == 0) { + fw_type = AMD_ABL6; + subprog = 0; + } else if (strcmp(fw_name, "PSP_ABL7_FILE") == 0) { + fw_type = AMD_ABL7; + subprog = 0; + } else if (strcmp(fw_name, "PSPSECUREOS_FILE") == 0) { + if (cb_config->use_secureos == 1) { + fw_type = AMD_FW_PSP_SECURED_OS; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } + } else if (strcmp(fw_name, "PSPTRUSTLETS_FILE") == 0) { + if (cb_config->use_secureos) { + fw_type = AMD_FW_PSP_TRUSTLETS; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } + } else if (strcmp(fw_name, "TRUSTLETKEY_FILE") == 0) { + if (cb_config->use_secureos) { + fw_type = AMD_FW_PSP_TRUSTLETKEY; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } + } else if (strcmp(fw_name, "PSP_IKEK_FILE") == 0) { + fw_type = AMD_WRAPPED_IKEK; + subprog = 0; + } else if (strcmp(fw_name, "PSP_SECG1_FILE") == 0) { + fw_type = AMD_SEC_GASKET; + subprog = 1; + } else if (strcmp(fw_name, "PSP_SECG2_FILE") == 0) { + fw_type = AMD_SEC_GASKET; + subprog = 2; + } else if (strcmp(fw_name, "PSP_MP2FW1_FILE") == 0) { + if (cb_config->load_mp2_fw == 1) { + fw_type = AMD_MP2_FW; + subprog = 1; + } else { + fw_type = AMD_FW_SKIP; + } + } else if (strcmp(fw_name, "PSP_MP2FW2_FILE") == 0) { + if (cb_config->load_mp2_fw == 1) { + fw_type = AMD_MP2_FW; + subprog = 2; + } else { + fw_type = AMD_FW_SKIP; + } + } else if (strcmp(fw_name, "PSP_MP2CFG_FILE") == 0) { + if (cb_config->load_mp2_fw == 1) { + fw_type = AMD_BIOS_MP2_CFG; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } + } else if (strcmp(fw_name, "PSP_DRIVERS_FILE") == 0) { + fw_type = AMD_DRIVER_ENTRIES; + subprog = 0; + } else if (strcmp(fw_name, "PSP_S0I3_FILE") == 0) { + if (cb_config->s0i3 == 1) { + fw_type = AMD_S0I3_DRIVER; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } + } else { + fw_type = AMD_FW_INVALID; + /* TODO: Add more */ + } + /* Search and fill the filename */ + psp_tableptr = &amd_psp_fw_table[0]; + if (fw_type != AMD_FW_SKIP && fw_type != AMD_FW_INVALID) { + while (psp_tableptr->type != AMD_FW_INVALID) { + /* instance are not used in PSP table */ + if (psp_tableptr->type == fw_type && psp_tableptr->subprog == subprog) { + psp_tableptr->filename = filename; + break; + } + psp_tableptr++; + } + } + if (fw_type == AMD_FW_INVALID) + return 0; + else + return 1; +} + +static uint8_t find_register_fw_filename_bios_dir(char *fw_name, char *filename, + amd_cb_config *cb_config) +{ + amd_bios_type fw_type = AMD_BIOS_INVALID; + amd_bios_entry *bhd_tableptr; + uint8_t subprog, instance = 0; + + (void) (cb_config); /* Remove warning and reserved for future. */ + + if (strcmp(fw_name, "PSP_PMUI_FILE1") == 0) { + fw_type = AMD_BIOS_PMUI; + subprog = 0; + instance = 1; + } else if (strcmp(fw_name, "PSP_PMUI_FILE2") == 0) { + fw_type = AMD_BIOS_PMUI; + subprog = 0; + instance = 4; + } else if (strcmp(fw_name, "PSP_PMUI_FILE3") == 0) { + fw_type = AMD_BIOS_PMUI; + subprog = 1; + instance = 1; + } else if (strcmp(fw_name, "PSP_PMUI_FILE4") == 0) { + fw_type = AMD_BIOS_PMUI; + subprog = 1; + instance = 4; + } else if (strcmp(fw_name, "PSP_PMUD_FILE1") == 0) { + fw_type = AMD_BIOS_PMUD; + subprog = 0; + instance = 1; + } else if (strcmp(fw_name, "PSP_PMUD_FILE2") == 0) { + fw_type = AMD_BIOS_PMUD; + subprog = 0; + instance = 4; + } else if (strcmp(fw_name, "PSP_PMUD_FILE3") == 0) { + fw_type = AMD_BIOS_PMUD; + subprog = 1; + instance = 1; + } else if (strcmp(fw_name, "PSP_PMUD_FILE4") == 0) { + fw_type = AMD_BIOS_PMUD; + subprog = 1; + instance = 4; + } else { + fw_type = AMD_BIOS_INVALID; + } + + bhd_tableptr = amd_bios_table; + + if (fw_type != AMD_BIOS_INVALID && fw_type != AMD_BIOS_SKIP) { + while (bhd_tableptr->type != AMD_BIOS_INVALID) { + if (bhd_tableptr->type == fw_type && + bhd_tableptr->subpr == subprog && + bhd_tableptr->inst == instance) { + bhd_tableptr->filename = filename; + break; + } + bhd_tableptr++; + } + } + if (fw_type == AMD_BIOS_INVALID) + return 0; + else + return 1; +} + +#define MAX_LINE_SIZE 1024 + +int get_input_file_line(FILE *f, char line[], int line_buf_size) +{ + if (fgets(line, line_buf_size, f) == NULL) + return LINE_EOF; + + /* If the file contains a line that is too long, then it's best + * to let the user know right away rather than passing back a + * truncated result that will lead to problems later on. + */ + line[strlen(line) - 1] = '\0'; + + if (strlen(line) == ((size_t) (line_buf_size - 1))) { + printf("The line size in config file should be lower than %d bytes.\n", + MAX_LINE_SIZE); + exit(1); + } + + return OK; +} + +static int is_valid_entry(char *oneline, regmatch_t *match) +{ + int retval; + + if (regexec(&entries_line_expr, oneline, 3, match, 0) == 0) { + oneline[match[1].rm_eo] = '\0'; + oneline[match[2].rm_eo] = '\0'; + retval = 1; + } else + retval = 0; + + return retval; +} + +static int skip_comment_blank_line(char *oneline) +{ + int retval; + + if (regexec(&blank_or_comment_expr, oneline, 0, NULL, 0) == 0) { + /* skip comment and blank */ + retval = 1; + } else { + /* no match */ + retval = 0; + } + + return retval; +} + +#define N_MATCHES 4 +/* + return value: + 0: The config file can not be parsed correctly. + 1: The config file can be parsed correctly. + */ +uint8_t process_config(FILE *config, amd_cb_config *cb_config, uint8_t print_deps) +{ + char oneline[MAX_LINE_SIZE], *path_filename; + regmatch_t match[N_MATCHES]; + char dir[MAX_LINE_SIZE] = {'\0'}; + + compile_reg_expr(REG_EXTENDED | REG_NEWLINE, + blank_or_comment_regex, &blank_or_comment_expr); + compile_reg_expr(REG_EXTENDED | REG_NEWLINE, + entries_line_regex, &entries_line_expr); + + /* Get a line */ + /* Get FIRMWARE_LOCATE in the first loop */ + while (get_input_file_line(config, oneline, MAX_LINE_SIZE) == OK) { + /* get a line */ + if (skip_comment_blank_line(oneline)) + continue; + if (is_valid_entry(oneline, match)) { + if (strcmp(&(oneline[match[1].rm_so]), "FIRMWARE_LOCATE") == 0) { + strcpy(dir, &(oneline[match[2].rm_so])); + break; + } + } + } + + if (dir[0] == '\0') { + fprintf(stderr, "No line with FIRMWARE_LOCATION\n"); + return 0; + } + + fseek(config, 0, SEEK_SET); + /* Get a line */ + while (get_input_file_line(config, oneline, MAX_LINE_SIZE) == OK) { + /* get a line */ + if (skip_comment_blank_line(oneline)) + continue; + if (is_valid_entry(oneline, match)) { + if (strcmp(&(oneline[match[1].rm_so]), "FIRMWARE_LOCATE") == 0) { + continue; + } else { + path_filename = malloc(MAX_LINE_SIZE); + strcpy(path_filename, dir); + strcat(path_filename, "/"); + strcat(path_filename, &(oneline[match[2].rm_so])); + + if (find_register_fw_filename_psp_dir( + &(oneline[match[1].rm_so]), + path_filename, cb_config) == 0) { + if (find_register_fw_filename_bios_dir( + &(oneline[match[1].rm_so]), + path_filename, cb_config) == 0) { + fprintf(stderr, "Module's name \"%s\" is not valid\n", oneline); + return 0; /* Stop parsing. */ + } else { + if (print_deps) + printf(" %s ", path_filename); + } + } else { + if (print_deps) + printf(" %s ", path_filename); + } + } + } else { + fprintf(stderr, "AMDFWTOOL config file line can't be parsed \"%s\"\n", oneline); + return 0; + } + } + return 1; +} From 902518e983d5aa3c1fdb5dfd91ca1fb468117191 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Tue, 27 Oct 2020 16:32:11 -0600 Subject: [PATCH 037/129] soc/amd/picasso: Fix the PSP SMI trigger info Align coreboot's PSP MboxBiosCmdSmmInfo setup to how AGESA's PSP library was implemented. The trigger address must be an SMI trigger register. Assign one of the reserved triggers to the PSP. The #define of SMITYPE_PSP 33 is still correct and is intentionally unmodified. This patch should be innocuous as the system doesn't currently support SMI-based features of the PSP. The call only exists so the PSP will honor a mailbox command during S3 suspend. BUG=b:171815390 TEST=Run SST on Morphius BRANCH=Zork Signed-off-by: Marshall Dawson Change-Id: I74029271a522a4f23e54fd76f99a8e3eb0dd4d55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46854 Reviewed-by: Felix Held Reviewed-by: Jason Glenesk Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/include/soc/smi.h | 1 + src/soc/amd/picasso/psp.c | 6 +++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index a629fc5541..0529ef6877 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -160,6 +160,7 @@ #define SMI_TIMER_EN (1 << 15) #define SMI_REG_SMITRIG0 0x98 +# define SMITRIG0_PSP (1 << 25) # define SMITRG0_EOS (1 << 28) # define SMI_TIMER_SEL (1 << 29) # define SMITRG0_SMIENB (1 << 31) diff --git a/src/soc/amd/picasso/psp.c b/src/soc/amd/picasso/psp.c index e40d395637..702b0d9d96 100644 --- a/src/soc/amd/picasso/psp.c +++ b/src/soc/amd/picasso/psp.c @@ -27,11 +27,11 @@ void soc_fill_smm_trig_info(struct smm_trigger_info *trig) if (!trig) return; - trig->address = (uintptr_t)acpimmio_smi + SMI_REG_CONTROL2; + trig->address = (uintptr_t)acpimmio_smi + SMI_REG_SMITRIG0; trig->address_type = SMM_TRIGGER_MEM; trig->value_width = SMM_TRIGGER_DWORD; - trig->value_and_mask = 0xfdffffff; - trig->value_or_mask = 0x02000000; + trig->value_and_mask = ~SMITRIG0_PSP; + trig->value_or_mask = SMITRIG0_PSP; } void soc_fill_smm_reg_info(struct smm_register_info *reg) From fdcbae0a9bec7adb4f0db3d5479813be42b4f323 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Thu, 1 Oct 2020 15:39:42 -0600 Subject: [PATCH 038/129] vc/amd/fsp: Update bl_errorcodes_public.h Replace the initial bl_errorcodes_public.h (a temporary, minimal version) with the full version released by AMD. BUG=None TEST=Build BRANCH=Zork Signed-off-by: Martin Roth Change-Id: I82585c74d74139a96419b9bffe1df3b8c344eb5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45943 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson Reviewed-by: Felix Held --- src/soc/amd/picasso/psp_verstage/fch.c | 4 +- .../amd/fsp/picasso/bl_uapp/bl_uapp_startup.S | 4 +- .../include/bl_uapp/bl_errorcodes_public.h | 52 +++++++++++++++++-- 3 files changed, 52 insertions(+), 8 deletions(-) diff --git a/src/soc/amd/picasso/psp_verstage/fch.c b/src/soc/amd/picasso/psp_verstage/fch.c index 7d0b856545..b813770b4a 100644 --- a/src/soc/amd/picasso/psp_verstage/fch.c +++ b/src/soc/amd/picasso/psp_verstage/fch.c @@ -124,13 +124,13 @@ static uint32_t map_fch_devices(void) bar_map[i].set_bar(bar); } - return BL_UAPP_OK; + return BL_OK; } uint32_t unmap_fch_devices(void) { void *bar; - uint32_t err, rtn = BL_UAPP_OK; + uint32_t err, rtn = BL_OK; unsigned int i; for (i = 0; i < ARRAY_SIZE(bar_map); ++i) { diff --git a/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S b/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S index 88bbf7e98a..15340d58ae 100644 --- a/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S +++ b/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S @@ -72,7 +72,7 @@ ENTRY(_psp_vs_start) // to main BL using Svc_Exit(). // ShouldNotBeReached: - mov r0, #BL_UAPP_ERR_GENERIC // Returned from Main + mov r0, #BL_ERR_GENERIC // Returned from Main svc #0x0 // SVC_EXIT ENDPROC(_psp_vs_start) @@ -95,7 +95,7 @@ ENTRY(AllocateStack) bne ret svcExit: - mov r0, #BL_UAPP_ERR_GENERIC + mov r0, #BL_ERR_GENERIC svc #0x0 // SVC_EXIT ret: diff --git a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_errorcodes_public.h b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_errorcodes_public.h index ab24750f60..1d5e86ffb1 100644 --- a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_errorcodes_public.h +++ b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_errorcodes_public.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (c) 2019, Advanced Micro Devices, Inc. + * Copyright (c) 2020, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -30,7 +30,51 @@ #ifndef BL_ERRORCODES_PUBLIC_H #define BL_ERRORCODES_PUBLIC_H -#define BL_UAPP_OK 0x00 // General - Success -#define BL_UAPP_ERR_GENERIC 0x01 // Generic Error Code +/* Bootloader Return Codes, Error only (0x00 through 0x9F) */ +#define BL_OK 0x00 // General - Success +#define BL_ERR_GENERIC 0x01 // Generic Error Code +#define BL_ERR_MEMORY 0x02 // Generic Memory Error +#define BL_ERR_BUFFER_OVERFLOW 0x03 // Buffer Overflow +#define BL_ERR_INVALID_PARAMETER 0x04 // Invalid Parameter(s) +#define BL_ERR_DATA_ALIGNMENT 0x06 // Data Alignment Error +#define BL_ERR_NULL_PTR 0x07 // Null Pointer Error +#define BL_ERR_INVALID_ADDRESS 0x0A // Invalid Address +#define BL_ERR_OUT_OF_RESOURCES 0x0B // Out of Resource Error +#define BL_ERR_DATA_ABORT 0x0D // Data Abort exception +#define BL_ERR_PREFETCH_ABORT 0x0E // Prefetch Abort exception +#define BL_ERR_GET_FW_HEADER 0x13 // Failure in retrieving firmware + // header +#define BL_ERR_KEY_SIZE 0x14 // Key size not supported +#define BL_ERR_ENTRY_NOT_FOUND 0x15 // Entry not found at requested + // location +#define BL_ERR_UNSUPPORTED_PLATFORM 0x16 // Error when feature is not enabled + // on a given platform. +#define BL_ERR_FWVALIDATION 0x18 // Generic FW Validation error +#define BL_ERR_CCP_RSA 0x19 // RSA operation fail - bootloader +#define BL_ERR_CCP_PASSTHR 0x1A // CCP Passthrough operation failed +#define BL_ERR_CCP_AES 0x1B // AES operation failed +#define BL_ERR_SHA 0x1E // SHA256/SHA384 operation failed +#define BL_ERR_ZLIB 0x1F // ZLib Decompression operation fail +#define BL_ERR_DIR_ENTRY_NOT_FOUND 0x22 // PSP directory entry not found +#define BL_ERR_SYSHUBMAP_FAILED 0x3A // Unable to map a SYSHUB address to + // AXI space +#define BL_ERR_UAPP_PSP_HEADER_NOT_MATCH 0x7A // PSP level directory from OEM user- + // app does not match expected value. +#define BL_ERR_UAPP_BIOS_HEADER_NOT_MATCH 0x7B // BIOS level directory from OEM + // user-app not match expected value. +#define BL_ERR_UAPP_PSP_DIR_OFFSET_NOT_SET 0x7C // PSP Directory offset is not set + // by OEM user-app. +#define BL_ERR_UAPP_BIOS_DIR_OFFSET_NOT_SET 0x7D // BIOS Directory offset is not set + // by OEM user-app. +#define BL_ERR_POSTCODE_MAX_VALUE 0x9F // The maximum allowable error post -#endif // BL_ERRORCODES_PUBLIC_H +/* Bootloader Return Codes, Success only (0xA0 through 0xFF) */ +#define BL_SUCCESS_USERMODE_OEM_APP 0xF7 // Updated only PSPFW Status when OEM + // PSP BL user app returns success. +#define BL_SUCCESS_PSP_BIOS_DIRECTORY_UPDATE 0xF8 // PSP and BIOS directories are loaded + // into SRAM from the offset provided + // by OEM user app. + +#define BL_SUCCESS_LAST_CODE 0xFF // Bootloader sequence finished + +#endif /* BL_ERRORCODES_PUBLIC_H */ From 69c0b19ae1d17f52907d1d31ac45a48b6fe426a7 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 8 Oct 2019 10:04:51 +0200 Subject: [PATCH 039/129] {soc/amd,sb/amd/hudson}: Fix generating the ACPI mcfg MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The last argument for acpi_fill_mcfg() is the last PCI bus, which is an uint8_t, not the total number of busses, which overflows the argument if CONFIG_MMCONF_BUS_NUMBER is 256. Change-Id: I8887e14128dbe54688eb6e803d6694b7c29956c1 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/35872 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Marshall Dawson Reviewed-by: Michał Żygowski --- src/soc/amd/stoneyridge/northbridge.c | 2 +- src/southbridge/amd/pi/hudson/lpc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 63ab6b4e81..0f66927e45 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -170,7 +170,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - CONFIG_MMCONF_BUS_NUMBER); + CONFIG_MMCONF_BUS_NUMBER - 1); return current; } diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index c884f209d3..b77548ecbb 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -324,7 +324,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - CONFIG_MMCONF_BUS_NUMBER); + CONFIG_MMCONF_BUS_NUMBER - 1); return current; } From 8269692517808d44d0b9c8deecd9e9182892726f Mon Sep 17 00:00:00 2001 From: Johnny Li Date: Thu, 8 Oct 2020 09:11:21 +0800 Subject: [PATCH 040/129] mb/google/volteer/variants/volteer2: I2C5 trackpad bus freq 400 kHz The current I2C5 bus frequency is 367 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:153588771 TEST=Verified that I2C5 frequency is between 389-396kHz. Signed-off-by: Johnny Li Change-Id: If0803a74ba9071acf15486ce4038261c1681a92f Reviewed-on: https://review.coreboot.org/c/coreboot/+/46142 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../volteer/variants/volteer2/overridetree.cb | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 2db1f087ef..3f666ac148 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -4,6 +4,44 @@ chip soc/intel/tigerlake register "IomTypeCPortPadCfg[1]" = "0x090E000D" register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + }" register "HybridStorageMode" = "1" From dd0066a91957cb3ec036a2466a66d86069edc5d2 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 29 Oct 2020 10:50:17 +0100 Subject: [PATCH 041/129] cpu/intel/Makefile.inc: Use correct Kconfig symbols MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Guard CPU code using CPU Kconfig symbols instead of northbridge symbols. Change-Id: I0e5d7fc2e042381b96d2fbdfa34a3d4bf58201f9 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46943 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/cpu/intel/Makefile.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 1849f19a3e..01913de312 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -10,9 +10,9 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559 subdirs-$(CONFIG_CPU_INTEL_SOCKET_M) += socket_m subdirs-$(CONFIG_CPU_INTEL_SOCKET_P) += socket_p subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604 -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IRONLAKE) += model_2065x -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell +subdirs-$(CONFIG_CPU_INTEL_MODEL_2065X) += model_2065x +subdirs-$(CONFIG_CPU_INTEL_MODEL_206AX) += model_206ax +subdirs-$(CONFIG_CPU_INTEL_HASWELL) += haswell subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775 From e7881ed447c9a6ce5aea99f53c12f5c43fbd81dd Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Wed, 30 Sep 2020 13:12:26 -0600 Subject: [PATCH 042/129] soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers Now that device aliases can be used in the devicetree, the hacky function 'soc_get_pmc_mux_device' can be removed and replaced with pointers to the devices the function was supposed to return (1 for each port). Signed-off-by: Tim Wawrzynczak Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45747 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/ec/google/chromeec/chip.h | 7 +++ src/ec/google/chromeec/ec_acpi.c | 50 ++++--------------- .../common/block/include/intelblocks/pmc.h | 9 ---- src/soc/intel/tigerlake/pmc.c | 22 -------- 4 files changed, 17 insertions(+), 71 deletions(-) diff --git a/src/ec/google/chromeec/chip.h b/src/ec/google/chromeec/chip.h index 9bfb1c4fd1..3915cf92e7 100644 --- a/src/ec/google/chromeec/chip.h +++ b/src/ec/google/chromeec/chip.h @@ -3,7 +3,14 @@ #ifndef EC_GOOGLE_CHROMEEC_CHIP_H #define EC_GOOGLE_CHROMEEC_CHIP_H +#include +#include + +#define MAX_TYPEC_PORTS 4 + struct ec_google_chromeec_config { + /* Pointer to PMC Mux connector for each Type-C port */ + DEVTREE_CONST struct device *mux_conn[MAX_TYPEC_PORTS]; }; #endif /* EC_GOOGLE_CHROMEEC_CHIP_H */ diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index b7683167af..344f5f42e5 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -16,14 +16,6 @@ #define GOOGLE_CHROMEEC_USBC_DEVICE_HID "GOOG0014" #define GOOGLE_CHROMEEC_USBC_DEVICE_NAME "USBC" -/* Avoid adding a false dependency on an SoC or intel/common */ -extern const struct device *soc_get_pmc_mux_device(int port_number); - -__weak const struct device *soc_get_pmc_mux_device(int port_number) -{ - return NULL; -} - const char *google_chromeec_acpi_name(const struct device *dev) { /* @@ -121,36 +113,18 @@ static const char *port_location_to_str(enum ec_pd_port_location port_location) static struct usb_pd_port_caps port_caps; static void add_port_location(struct acpi_dp *dsd, int port_number) { - acpi_dp_add_string(dsd, "port-location", - port_location_to_str(port_caps.port_location)); -} - -static int conn_id_to_match; - -/* A callback to match a port's connector for dev_find_matching_device_on_bus */ -static bool match_connector(DEVTREE_CONST struct device *dev) -{ - if (CONFIG(DRIVERS_INTEL_PMC)) { - extern struct chip_operations drivers_intel_pmc_mux_conn_ops; - - return (dev->chip_ops == &drivers_intel_pmc_mux_conn_ops && - dev->path.type == DEVICE_PATH_GENERIC && - dev->path.generic.id == conn_id_to_match); - } - - return false; + acpi_dp_add_string(dsd, "port-location", port_location_to_str(port_caps.port_location)); } static void fill_ssdt_typec_device(const struct device *dev) { + struct ec_google_chromeec_config *config = dev->chip_info; int rv; int i; unsigned int num_ports; struct device *usb2_port; struct device *usb3_port; struct device *usb4_port; - const struct device *mux; - const struct device *conn; if (google_chromeec_get_num_pd_ports(&num_ports)) return; @@ -166,32 +140,28 @@ static void fill_ssdt_typec_device(const struct device *dev) if (rv) continue; - /* Get the MUX device, and find the matching connector on its bus */ - conn = NULL; - mux = soc_get_pmc_mux_device(i); - if (mux) { - conn_id_to_match = i; - conn = dev_find_matching_device_on_bus(mux->link_list, match_connector); - } + if (!config->mux_conn[i]) + printk(BIOS_ERR, "ERROR: Mux connector info missing for Type-C port " + "#%d\n", i); usb2_port = NULL; usb3_port = NULL; usb4_port = NULL; get_usb_port_references(i, &usb2_port, &usb3_port, &usb4_port); - struct typec_connector_class_config config = { + struct typec_connector_class_config typec_config = { .power_role = port_caps.power_role_cap, .try_power_role = port_caps.try_power_role_cap, .data_role = port_caps.data_role_cap, .usb2_port = usb2_port, .usb3_port = usb3_port, .usb4_port = usb4_port, - .orientation_switch = conn, - .usb_role_switch = conn, - .mode_switch = conn, + .orientation_switch = config->mux_conn[i], + .usb_role_switch = config->mux_conn[i], + .mode_switch = config->mux_conn[i], }; - acpigen_write_typec_connector(&config, i, add_port_location); + acpigen_write_typec_connector(&typec_config, i, add_port_location); } acpigen_pop_len(); /* Device GOOGLE_CHROMEEC_USBC_DEVICE_NAME */ diff --git a/src/soc/intel/common/block/include/intelblocks/pmc.h b/src/soc/intel/common/block/include/intelblocks/pmc.h index 75e212740d..329bbe9bd7 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmc.h +++ b/src/soc/intel/common/block/include/intelblocks/pmc.h @@ -51,13 +51,4 @@ int pmc_soc_get_resources(struct pmc_resource_config *cfg); /* API to set ACPI mode */ void pmc_set_acpi_mode(void); -/* - * Returns a reference to the PMC MUX device for the given port number. - * Returns NULL if not found or SoC does not support PMC MUX. - * - * Input: Port number (0-based) - * Output: Const pointer to PMC MUX device - */ -const struct device *soc_get_pmc_mux_device(int port_number); - #endif /* SOC_INTEL_COMMON_BLOCK_PMC_H */ diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index f2f8a06260..dbf3671af7 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -126,28 +126,6 @@ static void soc_pmc_fill_ssdt(const struct device *dev) dev_path(dev)); } -/* FIXME: Rewrite loop below without this. */ -extern struct chip_operations drivers_intel_pmc_mux_ops; - -/* By default, TGL uses the PMC MUX for all ports, so port_number is unused */ -const struct device *soc_get_pmc_mux_device(int port_number) -{ - const struct device *pmc; - struct device *child; - - child = NULL; - pmc = pcidev_path_on_root(PCH_DEVFN_PMC); - if (!pmc || !pmc->link_list) - return NULL; - - while ((child = dev_bus_each_child(pmc->link_list, child)) != NULL) - if (child->chip_ops == &drivers_intel_pmc_mux_ops) - break; - - /* child will either be the correct device or NULL if not found */ - return child; -} - static void soc_acpi_mode_init(struct device *dev) { /* From eafe7989ace4e5d0b4214b6b30467438da3965ff Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Wed, 30 Sep 2020 13:59:21 -0600 Subject: [PATCH 043/129] tigerlake mainboards: switch to devtree aliases for PMC MUX connectors Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices can be hooked up together via devicetree aliases. Signed-off-by: Tim Wawrzynczak Change-Id: Ib51764da5b3c029f9ac7ac60199a0aedfc7f29b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45878 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/mainboard.c | 51 +++++++++++++++++++ .../volteer/variants/delbin/overridetree.cb | 11 +++- .../volteer/variants/terrador/overridetree.cb | 11 +++- .../volteer/variants/todor/overridetree.cb | 11 +++- .../volteer/variants/volteer/overridetree.cb | 26 ++++------ .../volteer/variants/volteer2/overridetree.cb | 28 ++++------ .../volteer/variants/voxel/overridetree.cb | 11 +++- .../tglrvp/variants/tglrvp_up3/devicetree.cb | 6 ++- .../tglrvp/variants/tglrvp_up4/devicetree.cb | 6 ++- 9 files changed, 114 insertions(+), 47 deletions(-) diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 03a78fd777..016572a39f 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -9,14 +9,65 @@ #include #include #include +#include #include #include #include #include +#include "drivers/intel/pmc_mux/conn/chip.h" + +extern struct chip_operations drivers_intel_pmc_mux_conn_ops; + +static bool is_port1(struct device *dev) +{ + return dev->path.type == DEVICE_PATH_GENERIC && dev->path.generic.id == 1 && + dev->chip_ops == &drivers_intel_pmc_mux_conn_ops; +} + +static void typec_orientation_fixup(void) +{ + /* + * TODO: This is an ugly hack, see if there's a better way to accomplish this same thing + * via fw_config + devicetree, i.e., change a register's value depending on fw_config + * probing. + */ + const struct device *pmc; + const struct device *mux; + const struct device *conn; + + pmc = pcidev_path_on_root(PCH_DEVFN_PMC); + if (!pmc || !pmc->link_list->children) { + printk(BIOS_ERR, "%s: unable to find PMC device or its mux\n", __func__); + return; + } + + /* + * Find port 1 underneath PMC.MUX; some variants may not have this defined, so it's okay + * to just silently return here. + */ + mux = pmc->link_list->children; + conn = dev_find_matching_device_on_bus(mux->link_list, is_port1); + if (!conn) + return; + + if (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) || + fw_config_probe(FW_CONFIG(DB_USB, USB3_ACTIVE)) || + fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3)) || + fw_config_probe(FW_CONFIG(DB_USB, USB3_NO_A))) { + struct drivers_intel_pmc_mux_conn_config *config = conn->chip_info; + + if (config) { + printk(BIOS_INFO, "Configure Right Type-C port orientation for retimer\n"); + config->sbu_orientation = TYPEC_ORIENTATION_NORMAL; + } + } +} + static void mainboard_init(struct device *dev) { mainboard_ec_init(); + typec_orientation_fixup(); } static void add_fw_config_oem_string(const struct fw_config *config, void *arg) diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index 5ecfccfba0..ba02d8c55a 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -70,6 +70,13 @@ chip soc/intel/tigerlake device i2c 15 on end end end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -80,14 +87,14 @@ chip soc/intel/tigerlake register "usb3_port_number" = "1" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "4" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index ae26e79558..d62a30374b 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -172,6 +172,13 @@ chip soc/intel/tigerlake device i2c 15 on end end end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -182,14 +189,14 @@ chip soc/intel/tigerlake register "usb3_port_number" = "1" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "3" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end diff --git a/src/mainboard/google/volteer/variants/todor/overridetree.cb b/src/mainboard/google/volteer/variants/todor/overridetree.cb index ae26e79558..d62a30374b 100644 --- a/src/mainboard/google/volteer/variants/todor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/todor/overridetree.cb @@ -172,6 +172,13 @@ chip soc/intel/tigerlake device i2c 15 on end end end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -182,14 +189,14 @@ chip soc/intel/tigerlake register "usb3_port_number" = "1" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "3" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index c5b4c72927..a047e875c3 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -221,6 +221,13 @@ chip soc/intel/tigerlake end end end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -230,27 +237,12 @@ chip soc/intel/tigerlake register "usb2_port_number" = "9" register "usb3_port_number" = "1" # SBU & HSL follow CC - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "4" register "usb3_port_number" = "2" - # SBU is fixed, HSL follows CC - register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on - probe DB_USB USB4_GEN2 - probe DB_USB USB3_ACTIVE - probe DB_USB USB4_GEN3 - probe DB_USB USB3_NO_A - end - end - chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" - # SBU & HSL follow CC - device generic 1 on - probe DB_USB USB3_PASSIVE - end + device generic 1 alias conn1 on end end end end diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 3f666ac148..a36a8441b4 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -93,7 +93,7 @@ chip soc/intel/tigerlake TEMP_PCT(42, 36),}}}" device generic 0 on end end - end # DPTF 0x9A03 + end device ref ipu on end # IPU 0x9A19 device ref i2c0 on chip drivers/i2c/generic @@ -254,6 +254,13 @@ chip soc/intel/tigerlake end end end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -263,27 +270,12 @@ chip soc/intel/tigerlake register "usb2_port_number" = "9" register "usb3_port_number" = "1" # SBU & HSL follow CC - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "4" register "usb3_port_number" = "2" - # SBU is fixed, HSL follows CC - register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on - probe DB_USB USB4_GEN2 - probe DB_USB USB3_ACTIVE - probe DB_USB USB4_GEN3 - probe DB_USB USB3_NO_A - end - end - chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" - # SBU & HSL follow CC - device generic 1 on - probe DB_USB USB3_PASSIVE - end + device generic 1 alias conn1 on end end end end diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index e8be8e3eb3..184007e0fc 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -187,6 +187,13 @@ chip soc/intel/tigerlake device i2c 15 on end end end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -197,14 +204,14 @@ chip soc/intel/tigerlake register "usb3_port_number" = "1" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "4" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index de93c99aa2..e16bd1f174 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -306,6 +306,8 @@ chip soc/intel/tigerlake end # GSPI1 0xA0AB device pci 1f.0 on chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] device pnp 0c09.0 on end end end # eSPI 0xA080 - A09F @@ -320,14 +322,14 @@ chip soc/intel/tigerlake register "usb3_port_number" = "3" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "7" register "usb3_port_number" = "4" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 4078894bfd..e6c0585787 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -310,6 +310,8 @@ chip soc/intel/tigerlake end # GSPI1 0xA0AB device pci 1f.0 on chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] device pnp 0c09.0 on end end end # eSPI 0xA080 - A09F @@ -324,14 +326,14 @@ chip soc/intel/tigerlake register "usb3_port_number" = "3" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "5" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end From 24b4af668b3f3995a5844560ce1885d30d8d8bfd Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Thu, 1 Oct 2020 15:41:31 -0600 Subject: [PATCH 044/129] fw_config: Convert fw_config to a 64-bit field We all knew this was coming, 32 bits is never enough. Doing this early so that it doesn't affect too much code yet. Take care of every usage of fw_config throughout the codebase so the conversion is all done at once. BUG=b:169668368 TEST=Hacked up this code to OR 0x1_000_0000 with CBI-sourced FW_CONFIG and verify the console print contained that bit. Signed-off-by: Tim Wawrzynczak Change-Id: I6f2065d347eafa0ef7b346caeabdc3b626402092 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45939 Reviewed-by: Furquan Shaikh Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- Documentation/lib/fw_config.md | 10 +++--- src/ec/google/chromeec/ec.c | 11 +++++-- src/ec/google/chromeec/ec.h | 2 +- src/include/fw_config.h | 6 ++-- src/lib/fw_config.c | 24 +++++++------- src/mainboard/google/dedede/board_info.c | 2 +- .../baseboard/include/baseboard/variants.h | 2 +- .../google/zork/variants/baseboard/helpers.c | 8 ++--- util/sconfig/main.c | 31 ++++++++++--------- util/sconfig/sconfig.h | 5 +-- util/sconfig/sconfig.y | 5 +-- 11 files changed, 60 insertions(+), 46 deletions(-) diff --git a/Documentation/lib/fw_config.md b/Documentation/lib/fw_config.md index 63a56dcd7b..dcf1bb4e95 100644 --- a/Documentation/lib/fw_config.md +++ b/Documentation/lib/fw_config.md @@ -73,18 +73,18 @@ return true. ## Firmware Configuration Value -The 32bit value used as the firmware configuration bitmask is meant to be determined at runtime +The 64-bit value used as the firmware configuration bitmask is meant to be determined at runtime but could also be defined at compile time if needed. There are two supported sources for providing this information to coreboot. ### CBFS -The value can be provided with a 32bit raw value in CBFS that is read by coreboot. The value +The value can be provided with a 64-bit raw value in CBFS that is read by coreboot. The value can be set at build time but also adjusted in an existing image with `cbfstool`. To enable this select the `CONFIG_FW_CONFIG_CBFS` option in the build configuration and add a -raw 32bit value to CBFS with the name of the current prefix at `CONFIG_FW_PREFIX/fw_config`. +raw 64-bit value to CBFS with the name of the current prefix at `CONFIG_FW_PREFIX/fw_config`. When `fw_config_probe_device()` or `fw_config_probe()` is called it will look for the specified file in CBFS use the value it contains when matching fields and options. @@ -291,8 +291,8 @@ field and option to check. struct fw_config { const char *field_name; const char *option_name; - uint32_t mask; - uint32_t value; + uint64_t mask; + uint64_t value; }; ``` diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 39cf89512f..2ffccbc77c 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -841,9 +841,16 @@ int google_chromeec_cbi_get_sku_id(uint32_t *id) return cbi_get_uint32(id, CBI_TAG_SKU_ID); } -int google_chromeec_cbi_get_fw_config(uint32_t *fw_config) +int google_chromeec_cbi_get_fw_config(uint64_t *fw_config) { - return cbi_get_uint32(fw_config, CBI_TAG_FW_CONFIG); + uint32_t config; + + if (cbi_get_uint32(&config, CBI_TAG_FW_CONFIG)) + return -1; + + /* FIXME: Yet to determine source of other 32 bits... */ + *fw_config = (uint64_t)config; + return 0; } int google_chromeec_cbi_get_oem_id(uint32_t *id) diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index c2ceff831f..bed8594a8b 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -83,7 +83,7 @@ int google_chromeec_reboot(int dev_idx, enum ec_reboot_cmd type, uint8_t flags); */ int google_chromeec_cbi_get_oem_id(uint32_t *id); int google_chromeec_cbi_get_sku_id(uint32_t *id); -int google_chromeec_cbi_get_fw_config(uint32_t *fw_config); +int google_chromeec_cbi_get_fw_config(uint64_t *fw_config); int google_chromeec_cbi_get_dram_part_num(char *buf, size_t bufsize); int google_chromeec_cbi_get_oem_name(char *buf, size_t bufsize); /* version may be stored in CBI as a smaller integer width, but the EC code diff --git a/src/include/fw_config.h b/src/include/fw_config.h index 81980b93ae..494ce7f389 100644 --- a/src/include/fw_config.h +++ b/src/include/fw_config.h @@ -18,8 +18,8 @@ struct fw_config { const char *field_name; const char *option_name; - uint32_t mask; - uint32_t value; + uint64_t mask; + uint64_t value; }; /* Generate a pointer to a compound literal of the fw_config structure. */ @@ -53,7 +53,7 @@ void fw_config_for_each_found(void (*cb)(const struct fw_config *config, void *a * * Return pointer to cached `struct fw_config` if successfully probed, otherwise NULL. */ -const struct fw_config *fw_config_get_found(uint32_t field_mask); +const struct fw_config *fw_config_get_found(uint64_t field_mask); #else diff --git a/src/lib/fw_config.c b/src/lib/fw_config.c index ec3205958d..0973cbeeff 100644 --- a/src/lib/fw_config.c +++ b/src/lib/fw_config.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -14,11 +15,11 @@ /** * fw_config_get() - Provide firmware configuration value. * - * Return 32bit firmware configuration value determined for the system. + * Return 64bit firmware configuration value determined for the system. */ -static uint32_t fw_config_get(void) +static uint64_t fw_config_get(void) { - static uint32_t fw_config_value; + static uint64_t fw_config_value; static bool fw_config_value_initialized; /* Nothing to prepare if setup is already done. */ @@ -35,7 +36,7 @@ static uint32_t fw_config_get(void) __func__); fw_config_value = 0; } else { - printk(BIOS_INFO, "FW_CONFIG value from CBFS is 0x%08x\n", + printk(BIOS_INFO, "FW_CONFIG value from CBFS is 0x%" PRIx64 "\n", fw_config_value); return fw_config_value; } @@ -47,7 +48,7 @@ static uint32_t fw_config_get(void) printk(BIOS_WARNING, "%s: Could not get fw_config from EC\n", __func__); } - printk(BIOS_INFO, "FW_CONFIG value is 0x%08x\n", fw_config_value); + printk(BIOS_INFO, "FW_CONFIG value is 0x%" PRIx64 "\n", fw_config_value); return fw_config_value; } @@ -59,7 +60,8 @@ bool fw_config_probe(const struct fw_config *match) printk(BIOS_INFO, "fw_config match found: %s=%s\n", match->field_name, match->option_name); else - printk(BIOS_INFO, "fw_config match found: mask=0x%08x value=0x%08x\n", + printk(BIOS_INFO, "fw_config match found: mask=0x%" PRIx64 " value=0x%" + PRIx64 "\n", match->mask, match->value); return true; } @@ -70,20 +72,20 @@ bool fw_config_probe(const struct fw_config *match) #if ENV_RAMSTAGE /* - * The maximum number of fw_config fields is limited by the 32-bit mask that is used to + * The maximum number of fw_config fields is limited by the 64-bit mask that is used to * represent them. */ -#define MAX_CACHE_ELEMENTS (8 * sizeof(uint32_t)) +#define MAX_CACHE_ELEMENTS (8 * sizeof(uint64_t)) static const struct fw_config *cached_configs[MAX_CACHE_ELEMENTS]; -static size_t probe_index(uint32_t mask) +static size_t probe_index(uint64_t mask) { assert(mask); - return __ffs(mask); + return __ffs64(mask); } -const struct fw_config *fw_config_get_found(uint32_t field_mask) +const struct fw_config *fw_config_get_found(uint64_t field_mask) { const struct fw_config *config; config = cached_configs[probe_index(field_mask)]; diff --git a/src/mainboard/google/dedede/board_info.c b/src/mainboard/google/dedede/board_info.c index fdb4b5ff64..22d35d7475 100644 --- a/src/mainboard/google/dedede/board_info.c +++ b/src/mainboard/google/dedede/board_info.c @@ -3,7 +3,7 @@ #include #include -int board_info_get_fw_config(uint32_t *fw_config) +int board_info_get_fw_config(uint64_t *fw_config) { return google_chromeec_cbi_get_fw_config(fw_config); } diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index dc855c63cd..bb41e45931 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -21,7 +21,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num); * @param fw_config Address where the fw_config is stored. * @return 0 on success or negative integer for errors. */ -int board_info_get_fw_config(uint32_t *fw_config); +int board_info_get_fw_config(uint64_t *fw_config); /* Return memory configuration structure. */ const struct mb_cfg *variant_memcfg_config(void); diff --git a/src/mainboard/google/zork/variants/baseboard/helpers.c b/src/mainboard/google/zork/variants/baseboard/helpers.c index cc07fe18d6..70710351d2 100644 --- a/src/mainboard/google/zork/variants/baseboard/helpers.c +++ b/src/mainboard/google/zork/variants/baseboard/helpers.c @@ -48,9 +48,9 @@ enum { FW_CONFIG_SHIFT_FAN = 27, }; -static int get_fw_config(uint32_t *val) +static int get_fw_config(uint64_t *val) { - static uint32_t known_value; + static uint64_t known_value; if (known_value) { *val = known_value; @@ -67,9 +67,9 @@ static int get_fw_config(uint32_t *val) return 0; } -static unsigned int extract_field(uint32_t mask, int shift) +static unsigned int extract_field(uint64_t mask, int shift) { - uint32_t fw_config; + uint64_t fw_config; /* On errors nothing is assumed to be set. */ if (get_fw_config(&fw_config)) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 4f13293a98..a7b2ce676e 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -4,8 +4,9 @@ #include #include #include -/* stat.h needs to be included before commonlib/helpers.h to avoid errors.*/ +#include #include +/* stat.h needs to be included before commonlib/helpers.h to avoid errors.*/ #include #include #include @@ -402,8 +403,8 @@ struct fw_config_field *new_fw_config_field(const char *name, { struct fw_config_field *field = find_fw_config_field(name); - /* Check that field is within 32bits. */ - if (start_bit > end_bit || end_bit > 31) { + /* Check that field is within 64 bits. */ + if (start_bit > end_bit || end_bit > 63) { printf("ERROR: fw_config field %s has invalid range %u-%u\n", name, start_bit, end_bit); exit(1); @@ -452,15 +453,16 @@ static void append_fw_config_option_to_field(struct fw_config_field *field, } } -void add_fw_config_option(struct fw_config_field *field, const char *name, unsigned int value) +void add_fw_config_option(struct fw_config_field *field, const char *name, uint64_t value) { struct fw_config_option *option; - uint32_t field_max_value; + uint64_t field_max_value; /* Check that option value fits within field mask. */ - field_max_value = (1 << (1 + field->end_bit - field->start_bit)) - 1; + field_max_value = (1ull << (1ull + field->end_bit - field->start_bit)) - 1ull; if (value > field_max_value) { - printf("ERROR: fw_config option %s:%s value %u larger than field max %u\n", + printf("ERROR: fw_config option %s:%s value %" PRIx64 " larger than field max %" + PRIx64 "\n", field->name, name, value, field_max_value); exit(1); } @@ -475,7 +477,7 @@ void add_fw_config_option(struct fw_config_field *field, const char *name, unsig } /* Compare values. */ if (value == option->value) { - printf("ERROR: fw_config option %s:%s[%u] redefined as %s\n", + printf("ERROR: fw_config option %s:%s[%" PRIx64 "] redefined as %s\n", field->name, option->name, value, name); exit(1); } @@ -532,23 +534,24 @@ static void emit_fw_config(FILE *fil) while (field) { struct fw_config_option *option = field->options; - uint32_t mask; + uint64_t mask; fprintf(fil, "#define FW_CONFIG_FIELD_%s_NAME \"%s\"\n", field->name, field->name); /* Compute mask from start and end bit. */ - mask = ((1 << (1 + field->end_bit - field->start_bit)) - 1); + mask = ((1ull << (1ull + field->end_bit - field->start_bit)) - 1ull); mask <<= field->start_bit; - fprintf(fil, "#define FW_CONFIG_FIELD_%s_MASK 0x%08x\n", + fprintf(fil, "#define FW_CONFIG_FIELD_%s_MASK 0x%" PRIx64 "\n", field->name, mask); while (option) { fprintf(fil, "#define FW_CONFIG_FIELD_%s_OPTION_%s_NAME \"%s\"\n", field->name, option->name, option->name); - fprintf(fil, "#define FW_CONFIG_FIELD_%s_OPTION_%s_VALUE 0x%08x\n", - field->name, option->name, option->value << field->start_bit); + fprintf(fil, "#define FW_CONFIG_FIELD_%s_OPTION_%s_VALUE 0x%" + PRIx64 "\n", field->name, option->name, + option->value << field->start_bit); option = option->next; } @@ -569,7 +572,7 @@ static int emit_fw_config_probe(FILE *fil, struct device *dev) /* Find matching field. */ struct fw_config_field *field; struct fw_config_option *option; - uint32_t mask, value; + uint64_t mask, value; field = find_fw_config_field(probe->field); if (!field) { diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index e2ff4c786b..0db1ce59c9 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -1,6 +1,7 @@ /* sconfig, coreboot device tree compiler */ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -31,7 +32,7 @@ struct pci_irq_info { struct fw_config_option; struct fw_config_option { const char *name; - unsigned int value; + uint64_t value; struct fw_config_option *next; }; struct fw_config_field; @@ -213,6 +214,6 @@ struct fw_config_field *new_fw_config_field(const char *name, unsigned int start_bit, unsigned int end_bit); void add_fw_config_option(struct fw_config_field *field, const char *name, - unsigned int value); + uint64_t value); void add_fw_config_probe(struct bus *bus, const char *field, const char *option); diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index cf71b02f3e..84dfe248fd 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -2,6 +2,7 @@ /* sconfig, coreboot device tree compiler */ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include "sconfig.h" int yylex(); @@ -16,7 +17,7 @@ static struct fw_config_field *cur_field; struct device *dev; struct chip_instance *chip_instance; char *string; - int number; + uint64_t number; } %token CHIP DEVICE REGISTER ALIAS REFERENCE ASSOCIATION BOOL STATUS MANDATORY BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESC IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO LPC ESPI FW_CONFIG_TABLE FW_CONFIG_FIELD FW_CONFIG_OPTION FW_CONFIG_PROBE @@ -116,7 +117,7 @@ fw_config_field: FW_CONFIG_FIELD STRING { /* option */ fw_config_option: FW_CONFIG_OPTION STRING NUMBER /* == field value */ - { add_fw_config_option(cur_field, $2, strtoul($3, NULL, 0)); }; + { add_fw_config_option(cur_field, $2, strtoull($3, NULL, 0)); }; /* probe