arch/io.h: Drop unnecessary include

Change-Id: I91158452680586ac676ea11c8589062880a31f91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31692
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/southbridge/amd/agesa/hudson/bootblock.c

@@ -14,7 +14,6 @@
  */
 
 #include <stdint.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 
 /*

src/southbridge/amd/agesa/hudson/hda.c

@@ -17,7 +17,6 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include <arch/io.h>
 #include <delay.h>
 #include "hudson.h"
 

src/southbridge/amd/agesa/hudson/lpc.c

@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <pc80/mc146818rtc.h>
 #include <pc80/isa-dma.h>
-#include <arch/io.h>
 #include <arch/ioapic.h>
 #include <arch/acpi.h>
 #include <pc80/i8254.h>

src/southbridge/amd/agesa/hudson/reset.c

@@ -16,7 +16,6 @@
 // Use simple device model for this file even in ramstage
 #define __SIMPLE_DEVICE__
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <cf9_reset.h>
 #include <reset.h>

src/southbridge/amd/agesa/hudson/sata.c

@@ -18,7 +18,6 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include <arch/io.h>
 #include "hudson.h"
 
 

src/southbridge/amd/agesa/hudson/sd.c

@@ -18,7 +18,6 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include <arch/io.h>
 #include "hudson.h"
 
 static void sd_init(struct device *dev)

src/southbridge/amd/agesa/hudson/sm.c

@@ -18,7 +18,6 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <device/smbus.h>
-#include <arch/io.h>
 #include <cpu/x86/lapic.h>
 #include <arch/ioapic.h>
 #include <stdlib.h>

src/southbridge/amd/agesa/hudson/usb.c

@@ -18,7 +18,6 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <device/pci_ehci.h>
-#include <arch/io.h>
 #include "hudson.h"
 
 static struct pci_operations lops_pci = {

src/southbridge/amd/amd8111/bootblock.c

@@ -15,7 +15,6 @@
  */
 
 #include <stdint.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <device/pci_type.h>

src/southbridge/amd/amd8111/reset.c

@@ -14,7 +14,6 @@
 
 #define __SIMPLE_DEVICE__
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <reset.h>
 #include <device/pci.h>

src/southbridge/amd/amd8111/smbus.c

@@ -18,7 +18,6 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <device/smbus.h>
-#include <arch/io.h>
 #include "amd8111.h"
 
 

src/southbridge/amd/amd8111/usb.c

@@ -17,7 +17,6 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include <arch/io.h>
 #include "amd8111.h"
 
 

src/southbridge/amd/cimx/sb800/cfg.c

@@ -17,7 +17,6 @@
 #include "cfg.h"
 #include <OEM.h>
 
-#include <arch/io.h>
 #include <arch/acpi.h>
 
 /**

src/southbridge/amd/cimx/sb800/early.c

@@ -15,7 +15,6 @@
 
 #include <stdint.h>
 #include <device/pci_ids.h>
-#include <arch/io.h>		/* inl, outl */
 #include "SBPLATFORM.h"
 #include "sb_cimx.h"
 #include "cfg.h"		/*sb800_cimx_config*/

src/southbridge/amd/cimx/sb800/lpc.c

@@ -19,7 +19,6 @@
 #include <device/pci_def.h>
 #include <arch/ioapic.h>
 #include "lpc.h"
-#include <arch/io.h>
 #include <device/pci_ops.h>
 
 void lpc_read_resources(struct device *dev)

src/southbridge/amd/cimx/sb800/reset.c

@@ -16,7 +16,6 @@
 // Use simple device model for this file even in ramstage
 #define __SIMPLE_DEVICE__
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <cf9_reset.h>
 #include <reset.h>

src/southbridge/amd/cimx/sb900/bootblock.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 
 static void sb900_enable_rom(void)

src/southbridge/amd/cimx/sb900/reset.c

@@ -16,7 +16,6 @@
 // Use simple device model for this file even in ramstage
 #define __SIMPLE_DEVICE__
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <cf9_reset.h>
 #include <reset.h>

src/southbridge/amd/pi/hudson/bootblock.c

@@ -14,7 +14,6 @@
  */
 
 #include <stdint.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
 

src/southbridge/amd/pi/hudson/hda.c

@@ -17,7 +17,6 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include <arch/io.h>
 #include <delay.h>
 #include "hudson.h"
 

src/southbridge/amd/pi/hudson/lpc.c

@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <pc80/mc146818rtc.h>
 #include <pc80/isa-dma.h>
-#include <arch/io.h>
 #include <arch/ioapic.h>
 #include <arch/acpi.h>
 #include <pc80/i8254.h>

src/southbridge/amd/pi/hudson/reset.c

@@ -16,7 +16,6 @@
 // Use simple device model for this file even in ramstage
 #define __SIMPLE_DEVICE__
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <cf9_reset.h>
 #include <reset.h>

src/southbridge/amd/pi/hudson/sata.c

@@ -18,7 +18,6 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include <arch/io.h>
 #include "hudson.h"
 
 

src/southbridge/amd/pi/hudson/sd.c

@@ -18,7 +18,6 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include <arch/io.h>
 #include "hudson.h"
 
 static void sd_init(struct device *dev)

src/southbridge/amd/pi/hudson/sm.c

@@ -18,7 +18,6 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <device/smbus.h>
-#include <arch/io.h>
 #include <cpu/x86/lapic.h>
 #include <arch/ioapic.h>
 #include <stdlib.h>

src/southbridge/amd/pi/hudson/usb.c

@@ -18,7 +18,6 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <device/pci_ehci.h>
-#include <arch/io.h>
 #include "hudson.h"
 
 static struct pci_operations lops_pci = {

src/southbridge/amd/rs780/cmn.c

@@ -14,7 +14,6 @@
  */
 
 #include <console/console.h>
-#include <arch/io.h>
 #include <arch/cpu.h>
 #include <device/device.h>
 #include <device/pci.h>

src/southbridge/amd/rs780/early_setup.c

@@ -14,7 +14,6 @@
  */
 
 #include <types.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <northbridge/amd/amdmct/mct/mct_d.h>
 #include <console/console.h>

src/southbridge/amd/rs780/rs780.c

@@ -14,7 +14,6 @@
  */
 
 #include <console/console.h>
-#include <arch/io.h>
 #include <arch/acpi.h>
 #include <device/device.h>
 #include <device/pci.h>

src/southbridge/amd/sb700/bootblock.c

@@ -15,7 +15,6 @@
  */
 
 #include <stdint.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 
 #define IO_MEM_PORT_DECODE_ENABLE_5	0x48

src/southbridge/amd/sb700/fadt.c

@@ -21,7 +21,6 @@
 #include <string.h>
 #include <console/console.h>
 #include <arch/acpi.h>
-#include <arch/io.h>
 #include <device/device.h>
 #include <cpu/amd/powernow.h>
 #include <version.h>

src/southbridge/amd/sb700/lpc.c

@@ -26,7 +26,6 @@
 #include <arch/acpi.h>
 #include <arch/acpigen.h>
 #include <pc80/isa-dma.h>
-#include <arch/io.h>
 #include <arch/ioapic.h>
 #include <cpu/amd/powernow.h>
 #include "sb700.h"

src/southbridge/amd/sb700/smbus.h

@@ -19,7 +19,6 @@
 
 #include <stdint.h>
 #include "stddef.h"
-#include <arch/io.h>
 
 #define SMBUS_IO_BASE 0xb00
 #define SMBUS_AUX_IO_BASE 0xb20

src/southbridge/amd/sb800/bootblock.c

@@ -14,7 +14,6 @@
  */
 
 #include <stdint.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 
 /*

src/southbridge/amd/sb800/fadt.c

@@ -21,7 +21,6 @@
 #include <string.h>
 #include <console/console.h>
 #include <arch/acpi.h>
-#include <arch/io.h>
 #include <device/device.h>
 #include <cpu/amd/powernow.h>
 #include <version.h>

src/southbridge/amd/sb800/lpc.c

@@ -24,7 +24,6 @@
 #include <pc80/i8254.h>
 #include <pc80/i8259.h>
 #include <pc80/isa-dma.h>
-#include <arch/io.h>
 #include <arch/acpi.h>
 #include "sb800.h"
 

src/southbridge/amd/sr5650/cmn.h

@@ -17,7 +17,6 @@
 #ifndef __SR5650_CMN_H__
 #define __SR5650_CMN_H__
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 
 #define NBMISC_INDEX	0x60

src/southbridge/broadcom/bcm5785/bootblock.c

@@ -15,7 +15,6 @@
  */
 
 #include <stdint.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <device/pci_type.h>

src/southbridge/broadcom/bcm5785/lpc.c

@@ -22,7 +22,6 @@
 #include <device/pci_ops.h>
 #include <pc80/mc146818rtc.h>
 #include <pc80/isa-dma.h>
-#include <arch/io.h>
 #include <arch/ioapic.h>
 #include "bcm5785.h"
 

src/southbridge/intel/bd82x6x/bootblock.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include "pch.h"
 

src/southbridge/intel/bd82x6x/early_spi.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <delay.h>

src/southbridge/intel/bd82x6x/early_usb_mrc.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include "pch.h"

src/southbridge/intel/bd82x6x/pch.c

@@ -18,7 +18,6 @@
 #include <console/console.h>
 #include <delay.h>
 #ifdef __SMM__
-#include <arch/io.h>
 #include <device/pci_def.h>
 #else /* !__SMM__ */
 #include <device/device.h>

src/southbridge/intel/bd82x6x/usb_xhci.c

@@ -20,7 +20,6 @@
 #include <device/pci_ids.h>
 #include "pch.h"
 #include <device/pci_ehci.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 
 static void usb_xhci_init(struct device *dev)

src/southbridge/intel/bd82x6x/watchdog.c

@@ -16,7 +16,6 @@
  */
 
 #include <console/console.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/device.h>
 #include <device/pci.h>

src/southbridge/intel/common/acpi_pirq_gen.c

@@ -14,7 +14,6 @@
  */
 
 #include <arch/acpigen.h>
-#include <arch/io.h>
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>

src/southbridge/intel/common/pmutil.c

@@ -15,7 +15,6 @@
  */
 
 #include <types.h>
-#include <arch/io.h>
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <device/pci_def.h>

src/southbridge/intel/common/usb_debug.c

@@ -17,7 +17,6 @@
 #define __SIMPLE_DEVICE__
 
 #include <stdint.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/pci_ehci.h>
 #include <device/pci_def.h>

src/southbridge/intel/fsp_rangeley/early_spi.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <delay.h>

src/southbridge/intel/fsp_rangeley/early_usb.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include "soc.h"

src/southbridge/intel/fsp_rangeley/smbus.c

@@ -20,7 +20,6 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include <arch/io.h>
 #include <southbridge/intel/common/smbus.h>
 #include "soc.h"
 

src/southbridge/intel/i82371eb/bootblock.c

@@ -15,7 +15,6 @@
  */
 
 #include <stdint.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <device/pci_type.h>

src/southbridge/intel/i82371eb/early_pm.c

@@ -15,7 +15,6 @@
  */
 
 #include <stdint.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/pci.h>
 #include <device/pci_def.h>

src/southbridge/intel/i82371eb/i82371eb.h

@@ -19,7 +19,6 @@
 
 #if !defined(__ASSEMBLER__) && !defined(__ACPI__)
 #if !defined(__PRE_RAM__)
-#include <arch/io.h>
 #include <device/device.h>
 #include "chip.h"
 

src/southbridge/intel/i82801dx/bootblock.c

@@ -12,7 +12,6 @@
  */
 
 #include <cpu/intel/car/bootblock.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 
 void bootblock_early_southbridge_init(void)

src/southbridge/intel/i82801gx/bootblock.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include "i82801gx.h"
 

src/southbridge/intel/i82801gx/smbus.c

@@ -20,7 +20,6 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include <arch/io.h>
 #include <southbridge/intel/common/smbus.h>
 #include "i82801gx.h"
 

src/southbridge/intel/i82801gx/smihandler.c

@@ -15,7 +15,6 @@
  */
 
 #include <types.h>
-#include <arch/io.h>
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>

src/southbridge/intel/i82801ix/bootblock.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 
 static void enable_spi_prefetch(void)

src/southbridge/intel/i82801ix/dmi_setup.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/pci_def.h>
 #include <console/console.h>
 #include <northbridge/intel/gm45/gm45.h>

src/southbridge/intel/i82801ix/smbus.c

@@ -20,7 +20,6 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include <arch/io.h>
 #include <southbridge/intel/common/smbus.h>
 #include "i82801ix.h"
 

src/southbridge/intel/i82801ix/smihandler.c

@@ -16,7 +16,6 @@
  */
 
 #include <types.h>
-#include <arch/io.h>
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>

src/southbridge/intel/i82801jx/bootblock.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include "i82801jx.h"
 

src/southbridge/intel/i82801jx/smbus.c

@@ -20,7 +20,6 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include <arch/io.h>
 #include <southbridge/intel/common/smbus.h>
 #include "i82801jx.h"
 

src/southbridge/intel/i82801jx/smihandler.c

@@ -16,7 +16,6 @@
  */
 
 #include <types.h>
-#include <arch/io.h>
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>

src/southbridge/intel/i82870/pci_parity.c

@@ -12,7 +12,6 @@
  */
 
 #include <pci.h>
-#include <arch/io.h>
 #include <printk.h>
 #
 

src/southbridge/intel/ibexpeak/madt.c

@@ -16,7 +16,6 @@
  */
 
 #include <string.h>
-#include <arch/io.h>
 #include <arch/ioapic.h>
 #include <arch/acpi.h>
 #include <arch/acpigen.h>

src/southbridge/intel/lynxpoint/bootblock.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include "pch.h"
 

src/southbridge/intel/lynxpoint/early_spi.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <delay.h>

src/southbridge/intel/lynxpoint/early_usb.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include "pch.h"

src/southbridge/intel/lynxpoint/pch.c

@@ -17,7 +17,6 @@
 
 #include <console/console.h>
 #include <delay.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/device.h>
 #include <device/pci.h>

src/southbridge/intel/lynxpoint/rcba.c

@@ -14,7 +14,6 @@
  */
 
 #include <device/pci_def.h>
-#include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include "pch.h"

src/southbridge/nvidia/ck804/bootblock.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include "ck804.h"
 

src/southbridge/nvidia/ck804/ck804.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>

src/southbridge/nvidia/ck804/enable_usbdebug.c

@@ -21,7 +21,6 @@
 #define __SIMPLE_DEVICE__
 
 #include <stdint.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/pci_ehci.h>
 #include <device/pci_def.h>

src/southbridge/nvidia/ck804/smbus.c

@@ -19,7 +19,6 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <device/smbus.h>
-#include <arch/io.h>
 #include "chip.h"
 #include "smbus.h"
 

src/southbridge/nvidia/mcp55/bootblock.c

@@ -18,7 +18,6 @@
  */
 
 #include <stdint.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include "mcp55.h"
 

src/southbridge/nvidia/mcp55/enable_usbdebug.c

@@ -21,7 +21,6 @@
 #define __SIMPLE_DEVICE__
 
 #include <stdint.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/pci_ehci.h>
 #include <device/pci_def.h>

src/southbridge/nvidia/mcp55/fadt.c

@@ -19,7 +19,6 @@
 #include <console/console.h>
 #include <string.h>
 #include <arch/acpi.h>
-#include <arch/io.h>
 #include <device/device.h>
 #include <device/pci_ids.h>
 #include <version.h>

src/southbridge/nvidia/mcp55/mcp55.c

@@ -17,7 +17,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>

src/southbridge/nvidia/mcp55/smbus.c

@@ -22,7 +22,6 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <device/smbus.h>
-#include <arch/io.h>
 #include "mcp55.h"
 #include "smbus.h"
 

src/southbridge/ricoh/rl5c476/rl5c476.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>

src/southbridge/ti/pci1x2x/pci1x2x.c

@@ -20,7 +20,6 @@
 #include <device/pci_ops.h>
 #include <device/cardbus.h>
 #include <console/console.h>
-#include <arch/io.h>
 #include "chip.h"
 
 static void ti_pci1x2y_init(struct device *dev)

src/southbridge/ti/pci7420/cardbus.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>

src/southbridge/ti/pci7420/firewire.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>

src/southbridge/ti/pcixx12/pcixx12.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>