amd/olivehillplus/romstage.c: remove not useful variable 'halt'
The variable 'halt' is not useful and results in a compile error because of: 1b2f2a07 Introduce halt() build error: src/mainboard/amd/olivehillplus/romstage.c: In function 'cache_as_ram_main': src/mainboard/amd/olivehillplus/romstage.c:43:15: error: declaration of 'halt' shadows a global declaration [-Werror=shadow] In file included from src/include/cpu/x86/lapic.h:6:0, from src/mainboard/amd/olivehillplus/romstage.c:29: src/include/halt.h:31:32: error: shadowed declaration is here [-Werror=shadow] cc1: all warnings being treated as errors make: *** [build/mainboard/amd/olivehillplus/romstage.pre.inc] Error 1 Change-Id: Id67a0dcb192fb6478115e489f46bfb07021afd90 Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/7847 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
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@ -40,7 +40,6 @@
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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{
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u32 val;
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u32 val;
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volatile int halt = 0;
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/*
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/*
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* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
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* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
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@ -64,9 +63,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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console_init();
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console_init();
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}
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}
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if(boot_cpu()) {
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while(halt);
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}
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/* Halt if there was a built in self test failure */
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/* Halt if there was a built in self test failure */
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post_code(0x34);
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post_code(0x34);
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report_bist_failure(bist);
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report_bist_failure(bist);
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