CK804/MCP55 devicetree.cb cosmetic and indentation fixes.
Add a few more comments for the entries, and also change the devicetree.cb files to the more compact and better readable variant with indentation level of 2 spaces (instead of random mix of tabs and spaces). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6071 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
@@ -1,152 +1,150 @@
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chip northbridge/amd/amdk8/root_complex
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device lapic_cluster 0 on
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chip cpu/amd/socket_940
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device lapic 0 on end
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end
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chip northbridge/amd/amdk8/root_complex # Root complex
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device lapic_cluster 0 on # (L)APIC cluster
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chip cpu/amd/socket_940 # CPU socket
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device lapic 0 on end # Local APIC of the CPU
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end
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end
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device pci_domain 0 on # PCI domain
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chip northbridge/amd/amdk8 # Northbridge / RAM controller
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device pci 18.0 on end
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device pci 18.0 on # Link 0 == LDT 0
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chip southbridge/nvidia/ck804 # Southbridge
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device pci 0.0 on end # HT
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device pci 1.0 on # LPC
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chip superio/smsc/lpc47m10x # Super I/O
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.3 off # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.4 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.5 off # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.7 off # PS/2 keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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end
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end
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device pci 1.1 on # SM 0
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chip drivers/generic/generic # DIMM 0-0-0
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device i2c 50 on end
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end
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chip drivers/generic/generic # DIMM 0-0-1
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device i2c 51 on end
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end
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chip drivers/generic/generic # DIMM 0-1-0
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device i2c 52 on end
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end
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chip drivers/generic/generic # DIMM 0-1-1
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device i2c 53 on end
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end
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chip drivers/generic/generic # DIMM 1-0-0
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device i2c 54 on end
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end
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chip drivers/generic/generic # DIMM 1-0-1
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device i2c 55 on end
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end
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chip drivers/generic/generic # DIMM 1-1-0
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device i2c 56 on end
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end
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chip drivers/generic/generic # DIMM 1-1-1
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device i2c 57 on end
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end
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end
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device pci 1.1 on # SM 1
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# PCI device SMBus address will
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# depend on addon PCI device, do
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# we need to scan_smbus_bus?
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# chip drivers/generic/generic # PCIXA slot 1
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# device i2c 50 on end
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# end
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# chip drivers/generic/generic # PCIXB slot 1
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# device i2c 51 on end
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# end
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# chip drivers/generic/generic # PCIXB slot 2
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# device i2c 52 on end
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# end
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# chip drivers/generic/generic # PCI slot 1
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# device i2c 53 on end
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# end
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# chip drivers/generic/generic # Master CK804 PCI-E
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# device i2c 54 on end
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# end
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# chip drivers/generic/generic # Slave CK804 PCI-E
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# device i2c 55 on end
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# end
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chip drivers/generic/generic # MAC EEPROM
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device i2c 51 on end
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end
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end
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device pci 2.0 on end # USB 1.1
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device pci 2.1 on end # USB 2
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device pci 4.0 on end # ACI
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device pci 4.1 off end # MCI
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device pci 6.0 on end # IDE
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device pci 7.0 on end # SATA 1
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device pci 8.0 on end # SATA 0
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device pci 9.0 on end # PCI
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device pci a.0 on end # NIC
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device pci b.0 off end # PCI E 3
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device pci c.0 off end # PCI E 2
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device pci d.0 off end # PCI E 1
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device pci e.0 on end # PCI E 0
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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register "sata0_enable" = "1"
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register "sata1_enable" = "1"
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# 1: SMBus under 2e.8, 2: SM0 3: SM1
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register "mac_eeprom_smbus" = "3"
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register "mac_eeprom_addr" = "0x51"
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end
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device pci_domain 0 on
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chip northbridge/amd/amdk8 #mc0
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device pci 18.0 on end # link 0
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device pci 18.0 on # link1
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# devices on link 0, link 0 == LDT 0
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chip southbridge/nvidia/ck804
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device pci 0.0 on end # HT
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device pci 1.0 on # LPC
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chip superio/smsc/lpc47m10x
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.3 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.4 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.5 off # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.7 off # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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end
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end
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device pci 1.1 on # SM 0
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chip drivers/generic/generic #dimm 0-0-0
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device i2c 50 on end
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end
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chip drivers/generic/generic #dimm 0-0-1
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device i2c 51 on end
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end
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chip drivers/generic/generic #dimm 0-1-0
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device i2c 52 on end
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end
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chip drivers/generic/generic #dimm 0-1-1
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device i2c 53 on end
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end
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chip drivers/generic/generic #dimm 1-0-0
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device i2c 54 on end
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end
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chip drivers/generic/generic #dimm 1-0-1
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device i2c 55 on end
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end
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chip drivers/generic/generic #dimm 1-1-0
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device i2c 56 on end
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end
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chip drivers/generic/generic #dimm 1-1-1
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device i2c 57 on end
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end
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end # SM
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device pci 1.1 on # SM 1
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#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
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# chip drivers/generic/generic #PCIXA Slot1
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# device i2c 50 on end
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# end
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# chip drivers/generic/generic #PCIXB Slot1
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# device i2c 51 on end
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# end
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# chip drivers/generic/generic #PCIXB Slot2
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# device i2c 52 on end
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# end
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# chip drivers/generic/generic #PCI Slot1
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# device i2c 53 on end
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# end
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# chip drivers/generic/generic #Master CK804 PCI-E
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# device i2c 54 on end
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# end
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# chip drivers/generic/generic #Slave CK804 PCI-E
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# device i2c 55 on end
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# end
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chip drivers/generic/generic #MAC EEPROM
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device i2c 51 on end
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end
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end # SM
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device pci 2.0 on end # USB 1.1
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device pci 2.1 on end # USB 2
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device pci 4.0 on end # ACI
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device pci 4.1 off end # MCI
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device pci 6.0 on end # IDE
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device pci 7.0 on end # SATA 1
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device pci 8.0 on end # SATA 0
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device pci 9.0 on end # PCI
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device pci a.0 on end # NIC
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device pci b.0 off end # PCI E 3
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device pci c.0 off end # PCI E 2
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device pci d.0 off end # PCI E 1
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device pci e.0 on end # PCI E 0
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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register "sata0_enable" = "1"
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register "sata1_enable" = "1"
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register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
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register "mac_eeprom_addr" = "0x51"
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end
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end # device pci 18.0
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device pci 18.0 on end # link 2
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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end # mc0
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chip northbridge/amd/amdk8
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device pci 19.0 on end # link 0
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device pci 19.0 on
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# devices on link 1, link 1 == LDT 1
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chip southbridge/nvidia/ck804
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device pci 0.0 on end # HT
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device pci 1.0 on end # LPC
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device pci 1.1 off end # SM
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device pci 2.0 off end # USB 1.1
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device pci 2.1 off end # USB 2
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device pci 4.0 off end # ACI
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device pci 4.1 off end # MCI
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device pci 6.0 off end # IDE
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device pci 7.0 off end # SATA 1
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device pci 8.0 off end # SATA 0
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device pci 9.0 off end # PCI
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device pci a.0 on end # NIC
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device pci b.0 off end # PCI E 3
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device pci c.0 off end # PCI E 2
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device pci d.0 off end # PCI E 1
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device pci e.0 on end # PCI E 0
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register "mac_eeprom_smbus" = "3"
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register "mac_eeprom_addr" = "0x51"
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end
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end # device pci 19.0
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device pci 19.0 on end
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device pci 19.1 on end
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device pci 19.2 on end
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device pci 19.3 on end
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end
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end # PCI domain
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end #root_complex
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end
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device pci 18.0 on end # Link 2
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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end
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chip northbridge/amd/amdk8 # Northbridge / RAM controller
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device pci 19.0 on end # Link 0
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device pci 19.0 on # Link 1 == LDT 1
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chip southbridge/nvidia/ck804 # Southbridge
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device pci 0.0 on end # HT
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device pci 1.0 on end # LPC
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device pci 1.1 off end # SM
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device pci 2.0 off end # USB 1.1
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device pci 2.1 off end # USB 2
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device pci 4.0 off end # ACI
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device pci 4.1 off end # MCI
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device pci 6.0 off end # IDE
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device pci 7.0 off end # SATA 1
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device pci 8.0 off end # SATA 0
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device pci 9.0 off end # PCI
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device pci a.0 on end # NIC
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device pci b.0 off end # PCI E 3
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device pci c.0 off end # PCI E 2
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device pci d.0 off end # PCI E 1
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device pci e.0 on end # PCI E 0
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# 1: SMBus under 2e.8, 2: SM0 3: SM1
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register "mac_eeprom_smbus" = "3"
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register "mac_eeprom_addr" = "0x51"
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end
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end
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device pci 19.0 on end
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device pci 19.1 on end
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device pci 19.2 on end
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device pci 19.3 on end
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end
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end
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end
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