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mainboard: Drop print_ implementation from non-romcc boards

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Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the mainboard code to use printk() on all non-ROMCC
boards.

Change-Id: I2383f24343fc2041fef4af65d717d754ad58425e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8111
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Stefan Reinauer
2015-01-05 13:02:32 -08:00
committed by Stefan Reinauer
parent 5491ca23fc
commit 069f4766a0
83 changed files with 229 additions and 388 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/msi/ms7135/romstage.c
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@@ -146,7 +146,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x();
if (needs_reset) {
print_info("ht reset -\n");
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}

16
src/mainboard/msi/ms7260/romstage.c
View File

@@ -131,9 +131,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
report_bist_failure(bist); /* Halt upon BIST failure. */
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
print_debug("bsp_apicid=");
print_debug_hex8(bsp_apicid);
print_debug("\n");
printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
/* In BSP so could hold all AP until sysinfo is in RAM. */
set_sysinfo_in_ram(0);
@@ -158,20 +156,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
{
msr_t msr = rdmsr(0xc0010042);
print_debug("begin msr fid, vid ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\n");
printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
{
msr_t msr = rdmsr(0xc0010042);
print_debug("end msr fid, vid ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\n");
printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
#endif
@@ -183,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* fidvid change will issue one LDTSTOP and the HT change will be effective too. */
if (needs_reset) {
print_info("ht reset -\n");
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);

8
src/mainboard/msi/ms9185/romstage.c
View File

@@ -123,7 +123,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
setup_coherent_ht_domain();
@@ -153,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -162,7 +162,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
#endif
@@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
print_info("ht reset -\n");
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
#endif

2
src/mainboard/msi/ms9282/romstage.c
View File

@@ -155,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset |= mcp55_early_setup_x();
if (needs_reset) {
print_info("ht reset -\n");
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}

2
src/mainboard/msi/ms9652_fam10/romstage.c
View File

@@ -209,7 +209,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
print_info("...WARM RESET...\n\n\n");
printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}