google/poppy: Add new board
Add poppy board files using kabylake and FSP 2.0. BUG=chrome-os-partner:60713 BRANCH=None TEST=Compiles successfully Change-Id: Ic9aa5093b319690ae893a21cab98d9b843000e6c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17866 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Furquan Shaikh
committed by
Martin Roth
Martin Roth
parent
2911b5e509
commit
06cd903566
245
src/mainboard/google/poppy/gpio.h
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245
src/mainboard/google/poppy/gpio.h
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#ifndef __MAINBOARD_GPIO_H__
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#define __MAINBOARD_GPIO_H__
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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/* EC in RW */
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#define GPIO_EC_IN_RW GPP_C6
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/* BIOS Flash Write Protect */
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#define GPIO_PCH_WP GPP_C23
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/* Memory configuration board straps */
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#define GPIO_MEM_CONFIG_0 GPP_C12
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#define GPIO_MEM_CONFIG_1 GPP_C13
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#define GPIO_MEM_CONFIG_2 GPP_C14
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#define GPIO_MEM_CONFIG_3 GPP_C15
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/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
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#define GPE_EC_WAKE GPE0_LAN_WAK
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/* eSPI virtual wire reporting */
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#define EC_SCI_GPI GPE0_ESPI
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#ifndef __ACPI__
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/* Pad configuration in ramstage */
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/* Leave eSPI pins untouched from default settings */
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static const struct pad_config gpio_table[] = {
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/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP41 */
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/* ESPI_IO0 */
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/* ESPI_IO1 */
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/* ESPI_IO2 */
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/* ESPI_IO3 */
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/* ESPI_CS# */
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/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP44 */
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/* PIRQA# */ PAD_CFG_NC(GPP_A7),
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/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP45 */
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/* ESPI_CLK */
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/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10),
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/* PME# */ PAD_CFG_NC(GPP_A11), /* TP67 */
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/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),
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/* SUSWARN# */ PAD_CFG_NC(GPP_A13),
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/* ESPI_RESET# */
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/* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
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/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16),
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/* SD_PWR_EN# */ PAD_CFG_NC(GPP_A17),
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/* ISH_GP0 */ PAD_CFG_NC(GPP_A18),
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/* ISH_GP1 */ PAD_CFG_NC(GPP_A19),
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/* ISH_GP2 */ PAD_CFG_GPI_APIC(GPP_A20, NONE,
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PLTRST), /* ACCEL_GYRO_INT_L */
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/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),
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/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),
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/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
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/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP42 */
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/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), /* TP43 */
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/* VRALERT# */ PAD_CFG_NC(GPP_B2),
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/* CPU_GP2 */ PAD_CFG_NC(GPP_B3),
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/* CPU_GP3 */ PAD_CFG_NC(GPP_B4),
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/* SRCCLKREQ0# */ PAD_CFG_NC(GPP_B5),
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/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CLKREQ */
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/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* WWAN CLKREQ */
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/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8),
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/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* NVME CLKREQ */
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/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10),
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/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11),
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/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* SPKR */ PAD_CFG_NC(GPP_B14),
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/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* TPM */
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/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* TPM */
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/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* TPM */
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/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* TPM */
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/* GSPI1_CS# */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), /* FP */
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/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), /* FP */
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/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* FP */
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/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), /* FP */
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/* SM1ALERT# */ PAD_CFG_NC(GPP_B23),
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/* SMBCLK */ PAD_CFG_NC(GPP_C0),
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/* SMBDATA */ PAD_CFG_NC(GPP_C1),
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/* SMBALERT# */ PAD_CFG_NC(GPP_C2),
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/* SML0CLK */ PAD_CFG_NC(GPP_C3),
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/* SML0DATA */ PAD_CFG_NC(GPP_C4),
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/* SML0ALERT# */ PAD_CFG_NC(GPP_C5),
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/* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
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/* SM1DATA */ PAD_CFG_NC(GPP_C7),
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/* UART0_RXD */ PAD_CFG_NC(GPP_C8),
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/* UART0_TXD */ PAD_CFG_NC(GPP_C9),
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/* UART0_RTS# */ PAD_CFG_NC(GPP_C10),
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/* UART0_CTS# */ PAD_CFG_NC(GPP_C11),
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/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
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/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
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/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */
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/* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */
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/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */
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/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */
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/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* NFC */
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/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* NFC */
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/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
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/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
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/* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1,
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DEEP), /* EN_PP3300_DX_TOUCHSCREEN */
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/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
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/* SPI1_CS# */ PAD_CFG_NC(GPP_D0),
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/* SPI1_CLK */ PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST), /* PEN_IRQ_L */
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/* SPI1_MISO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), /* PEN_PDCT_L */
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/* SPI1_MOSI */ PAD_CFG_GPO(GPP_D3, 0, DEEP), /* PEN_RESET */
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/* FASHTRIG */ PAD_CFG_NC(GPP_D4),
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/* ISH_I2C0_SDA */ PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP,
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NF1), /* ISH_SENSOR */
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/* ISH_I2C0_SCL */ PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP,
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NF1), /* ISH_SENSOR */
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/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
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/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
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/* ISH_SPI_CS# */ PAD_CFG_GPI_APIC(GPP_D9, NONE,
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PLTRST), /* HP_IRQ_GPIO */
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/* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* SPKR_RST_L */
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/* ISH_SPI_MISO */ PAD_CFG_GPI_APIC(GPP_D11, NONE,
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PLTRST), /* SPKR_INT_L */
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/* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12),
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/* ISH_UART0_RXD */ PAD_CFG_GPI_APIC(GPP_D13, NONE, PLTRST), /* FP_INT */
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/* ISH_UART0_TXD */ PAD_CFG_GPO(GPP_D14, 0, DEEP), /* FP_RST_ODL */
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/* ISH_UART0_RTS# */ PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST), /* MIC_IRQ_L */
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/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16),
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/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* DMIC_CLK1 */
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/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* DMIC_DATA1 */
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/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_CLK0 */
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/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* DMIC_DATA0 */
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/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21),
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/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */
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/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* MCLK */
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/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE,
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PLTRST), /* TPM_INT_L */
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/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),
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/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2),
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/* CPU_GP0 */ PAD_CFG_NC(GPP_E3),
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/* SATA_DEVSLP0 */ PAD_CFG_GPO(GPP_E4, 0, DEEP), /* NFC_RESET_ODL */
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/* SATA_DEVSLP1 */ PAD_CFG_GPI_APIC(GPP_E5, NONE, PLTRST), /* NFC_INT_L */
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/* SATA_DEVSLP2 */ PAD_CFG_GPO(GPP_E6, 0, DEEP), /* NFC_FW_DL */
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/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE,
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PLTRST), /* TOUCHSCREEN_INT_L */
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/* SATALED# */ PAD_CFG_NC(GPP_E8),
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/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_C0_OC_ODL */
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/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP,
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NF1), /* USB_C1_OC_ODL */
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/* USB2_OC2# */ PAD_CFG_GPO(GPP_E11, 0, DEEP), /* TOUCHSCREEN_RESET_L */
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/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* USB2_OC3_L */
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/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP,
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NF1), /* USB_C0_DP_HPD */
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/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP,
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NF1), /* USB_C1_DP_HPD */
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/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP48 */
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/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP244 */
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/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
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/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18),
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/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19),
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/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20),
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/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21),
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/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22),
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/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23),
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/* The next 4 pads are for bit banging the amplifiers, default to I2S */
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/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP),
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/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP),
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/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP),
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/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP),
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/* I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* CAM_PMIC */
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/* I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), /* CAM_PMIC */
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/* I2C3_SDA */ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), /* PEN */
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/* I2C3_SCL */ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), /* PEN */
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/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* UFCAM */
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/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* UFCAM*/
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/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1), /* AUDIO */
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/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1), /* AUDIO */
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/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
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/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
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/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
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/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
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/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
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/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
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/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
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/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
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/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
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/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
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/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
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/* RSVD */ PAD_CFG_NC(GPP_F23),
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/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
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/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
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/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
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/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
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/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
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/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
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/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
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/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1),
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/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
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/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
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/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */
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/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
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/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
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/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
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/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP26 */
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/* RSVD */ PAD_CFG_NC(GPD7),
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/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
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/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP25 */
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/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP15 */
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/* LANPHYC */ PAD_CFG_NC(GPD11),
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};
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* TPM */
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/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* TPM */
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/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* TPM */
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/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* TPM */
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/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
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/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE,
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PLTRST), /* TPM_INT_L */
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/* Ensure UART pins are in native mode for H1. */
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/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
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/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
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};
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#endif
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#endif
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