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cpu/intel/smm/gen1: Use correct MSR for model_6fx and model_1067x

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According to the "Intel® 64 and IA-32 Architectures Software Developer’s Manual"
the SMRR MSR are at a different offset for model_6fx and model_1067x.

This still need SMRR enabled and lock bit set in MSR_FEATURE_CONTROL.

Change-Id: I8ee8292ab038e58deb8c24745ec1a9b5da8c31a9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Arthur Heymans
2018-07-20 23:41:54 +02:00
committed by Patrick Georgi
parent e8d0c0092a
commit 06f818c932
2 changed files with 40 additions and 4 deletions
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4
src/include/cpu/x86/mtrr.h
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@@ -31,6 +31,10 @@
#define IA32_SMRR_PHYS_BASE 0x1f2
#define IA32_SMRR_PHYS_MASK 0x1f3
/* Specific to model_6fx and model_1067x */
#define MSR_SMRR_PHYS_BASE 0xa0
#define MSR_SMRR_PHYS_MASK 0xa1
#define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg))
#define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1)
#define MTRR_PHYS_MASK_VALID (1 << 11)