sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mods for early printing on OLPC

Browse Source 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
2006-05-04 23:05:49 +00:00
parent ab4f5d0c10
commit 070a10f759
3 changed files with 74 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/include/cpu/amd/gx2def.h
View File

@@ -89,7 +89,8 @@
#define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1)
#define MSR_AES ((GL1_AES << 26) + MSR_GLIU1)
/* South Bridge*/
#define MSR_SB (SB_PORT << 23) + MSR_PCI /* address to the SouthBridge*/
#define SB_PORT 2 /* port of the SouthBridge */
#define MSR_SB ((SB_PORT << 23) + MSR_PCI) /* address to the SouthBridge*/
#define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift.*/
@@ -502,7 +503,7 @@
#define CS5535_IDSEL 0x02000000 // IDSEL = AD25, device #15
#define CHIPSET_DEV_NUM 15
#define IDSEL_BASE 11 // bit 11 = device 1
#define SB_PORT 2 // port of the SouthBridge
/* standard AMD post definitions -- might as well use them. */
#define POST_Output_Port (0x080) /* port to write post codes to*/