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mb/google/nissa/var/anraggar: Config DP AUX BIAS according to fw_config

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EVT mini-build changes redriver IC from PS8745 to ANX7493, the ANX7493 not support DP AUX BIAS, so connects DP AUX BIAS of DB to SOC directly. Add DB_AUX_BIAS bit field to fw_config for compatibility.

BUG=b:320235566
TEST=DP function of MB and DB workable

Change-Id: I53974ec7444912a63d0fe0a9303c9e5d6941f68d
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80259
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Weimin Wu
2024-01-31 20:43:42 +08:00
committed by Felix Held
parent 8a505902c0
commit 0740d96e7e
2 changed files with 34 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
src/mainboard/google/brya/variants/anraggar/overridetree.cb
View File

@ -10,6 +10,10 @@ fw_config
option UF_720P 2 option UF_720P 2
option UF_1080P_WF 3 option UF_1080P_WF 3
end end
field DB_AUX_BIAS 3 4
option REDRIVER 0
option SOC 1
end
end end
chip soc/intel/alderlake chip soc/intel/alderlake
@ -60,21 +64,6 @@ chip soc/intel/alderlake
# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515" register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"
# SOC Aux orientation override:
# This is a bitfield that corresponds to up to 4 TCSS ports.
# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
# TcssAuxOri = 0100b
# Bit0 set to "0" indicates has retimer on USBC Port0, on the DB.
# Bit2 set to "1" indicates no retimer on USBC Port1, on the MB.
# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
# motherboard to USBC connector
register "tcss_aux_ori" = "4"
register "typec_aux_bias_pads[0]" = "{
.pad_auxp_dc = GPP_E22,
.pad_auxn_dc = GPP_E23
}"
# FIVR configurations for anraggar are disabled since the board doesn't have V1p05 and Vnn # FIVR configurations for anraggar are disabled since the board doesn't have V1p05 and Vnn
# bypass rails implemented. # bypass rails implemented.
register "ext_fivr_settings" = "{ register "ext_fivr_settings" = "{

30
src/mainboard/google/brya/variants/anraggar/variant.c
View File

@ -1,9 +1,39 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/variants.h>
#include <chip.h>
#include <fw_config.h> #include <fw_config.h>
#include <sar.h> #include <sar.h>
#include <soc/gpio_soc_defs.h>
const char *get_wifi_sar_cbfs_filename(void) const char *get_wifi_sar_cbfs_filename(void)
{ {
return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI)); return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
} }
void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
{
/*
* SOC Aux orientation override:
* This is a bitfield that corresponds to up to 4 TCSS ports.
* Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
* Bit0, Bit2 set to "0" indicates has retimer on TCSS Port.
* Bit0, Bit2 set to "1" indicates no retimer on TCSS Port.
* Bit1, Bit3 set to "0" indicates Aux lines are not swapped on TCSS Port.
* Bit1, Bit3 set to "1" indicates Aux lines are swapped on TCSS Port.
*/
if (fw_config_probe(FW_CONFIG(DB_AUX_BIAS, SOC))) {
printk(BIOS_INFO, "DB DP AUX BIAS connect to SOC.\n");
config->tcss_aux_ori = 5;
config->typec_aux_bias_pads[0].pad_auxp_dc = GPP_A19;
config->typec_aux_bias_pads[0].pad_auxn_dc = GPP_A20;
config->typec_aux_bias_pads[1].pad_auxp_dc = GPP_E22;
config->typec_aux_bias_pads[1].pad_auxn_dc = GPP_E23;
} else {
printk(BIOS_INFO, "DB DP AUX BIAS connect to redriver IC.\n");
config->tcss_aux_ori = 4;
config->typec_aux_bias_pads[1].pad_auxp_dc = GPP_E22;
config->typec_aux_bias_pads[1].pad_auxn_dc = GPP_E23;
}
}