intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOP

Change-Id: I02881ce465cb3835a6fa7c06b718aa42d0d327ec
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15227
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

src/cpu/intel/car/cache_as_ram.inc

@@ -318,7 +318,12 @@ lout:
 	/* We need to set EBP? No need. */
 	movl	%esp, %ebp
 	pushl	%eax  /* BIST */
-	call	main
+	call	romstage_main
+
+	/* Save return value from romstage_main. It contains the stack to use
+	 * after cache-as-ram is torn down. It also contains the information
+	 * for setting up MTRRs. */
+	movl	%eax, %ebx
 
 	/* We don't need CAR from now on. */
 
@@ -356,7 +361,8 @@ __main:
 	post_code(POST_PREPARE_RAMSTAGE)
 	cld			/* Clear direction flag. */
 
-	movl	$CONFIG_RAMTOP, %esp
+	/* Setup stack as indicated by return value from romstage_main(). */
+	movl	%ebx, %esp
 	movl	%esp, %ebp
 	call	copy_and_run
 

src/cpu/intel/slot_1/Makefile.inc

@@ -29,3 +29,4 @@ subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
+romstage-y += ../car/romstage.c

src/cpu/intel/socket_FC_PGA370/Makefile.inc

@@ -23,3 +23,4 @@ subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
+romstage-y += ../car/romstage.c

src/cpu/intel/socket_PGA370/Makefile.inc

@@ -23,3 +23,4 @@ subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
+romstage-y += ../car/romstage.c

src/cpu/intel/socket_mFCBGA479/Makefile.inc

@@ -7,3 +7,4 @@ subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
+romstage-y += ../car/romstage.c

src/cpu/intel/socket_mPGA479M/Makefile.inc

@@ -10,3 +10,4 @@ subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
+romstage-y += ../car/romstage.c