intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOP

Change-Id: I02881ce465cb3835a6fa7c06b718aa42d0d327ec
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15227
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

src/mainboard/biostar/m6tba/romstage.c

@@ -24,6 +24,7 @@
 #include <northbridge/intel/i440bx/raminit.h>
 #include <delay.h>
 #include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
 #include <superio/smsc/smscsuperio/smscsuperio.h>
 #include <lib.h>
 
@@ -34,8 +35,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
+void mainboard_romstage_entry(unsigned long bist)
 {
 	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();