AGESA vendorcode: Build a common amdlib

Having CFLAGS with -Os disables -falign-function, for
unlucky builds this may delay entry to ramstage by 600ms.
Build the low-level IO functions aligned with -O2 instead.

Change-Id: Ice6781666a0834f1e8e60a0c93048ac8472f27d9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14414
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/southbridge/amd/agesa/hudson/imc.c

@@ -18,7 +18,7 @@
 #include <delay.h>
 #include "Porting.h"
 #include "AGESA.h"
-#include <Lib/amdlib.h>
+#include <amdlib.h>
 #include <Proc/Fch/Fch.h>
 #include <Proc/Fch/Common/FchCommonCfg.h>
 #include <Proc/Fch/FchPlatform.h>