sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

This patch unifies the use of config options in v2 to all start with CONFIG_

Browse Source 
It's basically done with the following script and some manual fixup:

VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
	find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2009-06-30 15:17:49 +00:00
committed by Stefan Reinauer
parent 9702b6bf7e
commit 0867062412
863 changed files with 14632 additions and 14632 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
src/cpu/amd/car/cache_as_ram.inc
View File

@@ -18,13 +18,13 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define CacheSize DCACHE_RAM_SIZE
#define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase (0xd0000 - CacheSize)
/* leave some space for global variable to pass to RAM stage */
#define GlobalVarSize DCACHE_RAM_GLOBAL_VAR_SIZE
#define GlobalVarSize CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
/* for CAR_FAM10 */
/* for CONFIG_CAR_FAM10 */
#define CacheSizeAPStack 0x400 /* 1K */
#define MSR_FAM10 0xC001102A
@@ -72,7 +72,7 @@ cache_as_ram_setup:
cvtsd2si %xmm3, %ebx
/* hope we can skip the double set for normal part */
#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))
#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
/* check if cpu_init_detected */
movl $MTRRdefType_MSR, %ecx
@@ -248,10 +248,10 @@ clear_fixed_var_mtrr_out:
xorl %edx, %edx
movl $(((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
wrmsr
#endif /* USE_FAILOVER_IMAGE == 1*/
#endif /* CONFIG_USE_FAILOVER_IMAGE == 1*/
#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 0)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 0))
#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 0)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 0))
/* disable cache */
movl %cr0, %eax
orl $(1 << 30),%eax
@@ -259,25 +259,25 @@ clear_fixed_var_mtrr_out:
#endif
#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
/* enable write base caching so we can do execute in place
* on the flash rom.
*/
movl $0x202, %ecx
xorl %edx, %edx
movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
wrmsr
movl $0x203, %ecx
movl $0xff, %edx /* (1 << (CPU_ADDR_BITS - 32)) - 1 for K8 (CPU_ADDR_BITS = 40) */
movl $0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */
jmp_if_k8(wbcache_post_fam10_setup)
movl $0xffff, %edx /* (1 << (CPU_ADDR_BITS - 32)) - 1 for FAM10 (CPU_ADDR_BITS = 48) */
movl $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */
wbcache_post_fam10_setup:
movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr
#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))
#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
/* Set the default memory type and enable fixed and variable MTRRs */
movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx
@@ -313,7 +313,7 @@ fam10_end_part1:
movb $0xA2, %al
outb %al, $0x80
#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))
#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
/* Read the range with lodsl*/
cld
movl $CacheBase, %esi
@@ -325,7 +325,7 @@ fam10_end_part1:
xorl %eax, %eax
rep stosl
#endif /*USE_FAILOVER_IMAGE == 1*/
#endif /*CONFIG_USE_FAILOVER_IMAGE == 1*/
/* set up the stack pointer */
movl $(CacheBase + CacheSize - GlobalVarSize), %eax

6
src/cpu/amd/car/clear_init_ram.c
View File

@@ -7,11 +7,11 @@ static void __attribute__((noinline)) clear_init_ram(void)
// will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already
// so noline clear_init_ram
#if HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME == 1
/* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
clear_memory( _RAMBASE, (CONFIG_LB_MEM_TOPK << 10) - _RAMBASE - DCACHE_RAM_SIZE);
clear_memory( CONFIG_RAMBASE, (CONFIG_LB_MEM_TOPK << 10) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE);
#else
clear_memory(0, ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE));
clear_memory(0, ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_SIZE));
#endif
}

4
src/cpu/amd/car/copy_and_run.c
View File

@@ -8,7 +8,7 @@ void cbfs_and_run_core(char*, unsigned ebp);
static void copy_and_run(void)
{
# if USE_FALLBACK_IMAGE == 1
# if CONFIG_USE_FALLBACK_IMAGE == 1
cbfs_and_run_core("fallback/coreboot_ram", 0);
# else
cbfs_and_run_core("normal/coreboot_ram", 0);
@@ -19,7 +19,7 @@ static void copy_and_run(void)
static void copy_and_run_ap_code_in_car(unsigned ret_addr)
{
# if USE_FALLBACK_IMAGE == 1
# if CONFIG_USE_FALLBACK_IMAGE == 1
cbfs_and_run_core("fallback/coreboot_apc", ret_addr);
# else
cbfs_and_run_core("normal/coreboot_apc", ret_addr);

2
src/cpu/amd/car/disable_cache_as_ram.c
View File

@@ -16,7 +16,7 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
"xorl %edx, %edx\n\t"
"xorl %eax, %eax\n\t"
"wrmsr\n\t"
#if DCACHE_RAM_SIZE > 0x8000
#if CONFIG_DCACHE_RAM_SIZE > 0x8000
"movl $0x268, %ecx\n\t" /* fix4k_c0000*/
"wrmsr\n\t"
#endif

18
src/cpu/amd/car/post_cache_as_ram.c
View File

@@ -64,7 +64,7 @@ static void post_cache_as_ram(void)
set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_LB_MEM_TOPK) */
// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x8000, DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x7c00);
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x8000, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x7c00);
print_debug("Copying data from cache to RAM -- switching to use RAM as stack... ");
/* from here don't store more data in CAR */
@@ -76,14 +76,14 @@ static void post_cache_as_ram(void)
);
#endif
memcopy((void *)((CONFIG_LB_MEM_TOPK<<10)-DCACHE_RAM_SIZE), (void *)DCACHE_RAM_BASE, DCACHE_RAM_SIZE); //inline
memcopy((void *)((CONFIG_LB_MEM_TOPK<<10)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
// dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00);
__asm__ volatile (
/* set new esp */ /* before _RAMBASE */
/* set new esp */ /* before CONFIG_RAMBASE */
"subl %0, %%ebp\n\t"
"subl %0, %%esp\n\t"
::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) )
::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) )
); // We need to push %eax to the stack (CAR) before copy stack and pop it later after copy stack and change esp
#if 0
__asm__ volatile (
@@ -102,18 +102,18 @@ static void post_cache_as_ram(void)
disable_cache_as_ram_bsp();
print_debug("Clearing initial memory region: ");
clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10))
clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10))
print_debug("Done\r\n");
// dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00);
#ifndef MEM_TRAIN_SEQ
#define MEM_TRAIN_SEQ 0
#ifndef CONFIG_MEM_TRAIN_SEQ
#define CONFIG_MEM_TRAIN_SEQ 0
#endif
set_sysinfo_in_ram(1); // So other core0 could start to train mem
#if MEM_TRAIN_SEQ == 1
// struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE);
#if CONFIG_MEM_TRAIN_SEQ == 1
// struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
// wait for ap memory to trained
// wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c

2
src/cpu/amd/dualcore/amd_sibling.c
View File

@@ -110,7 +110,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
if((apicid_base+ioapic_num-1)>0xf) {
// We need to enable APIC EXT ID
printk_info("if the IO APIC device doesn't support 256 apic id, \r\n you need to set ENABLE_APIC_EXT_ID in auto.c so you can spare 16 id for ioapic\r\n");
printk_info("if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in auto.c so you can spare 16 id for ioapic\r\n");
enable_apic_ext_id(nodes);
}

16
src/cpu/amd/dualcore/dualcore.c
View File

@@ -19,7 +19,7 @@ static inline unsigned get_core_num_in_bsp(unsigned nodeid)
#if SET_NB_CFG_54 == 1
static inline uint8_t set_apicid_cpuid_lo(void)
{
#if K8_REV_F_SUPPORT == 0
#if CONFIG_K8_REV_F_SUPPORT == 0
if(is_cpu_pre_e0()) return 0; // pre_e0 can not be set
#endif
@@ -56,7 +56,7 @@ static inline void start_other_cores(void)
unsigned nodes;
unsigned nodeid;
if (HAVE_OPTION_TABLE &&
if (CONFIG_HAVE_OPTION_TABLE &&
read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) {
return; // disable dual_core
}
@@ -70,7 +70,7 @@ static inline void start_other_cores(void)
}
}
#if USE_DCACHE_RAM == 0
#if CONFIG_USE_DCACHE_RAM == 0
static void do_k8_init_and_stop_secondaries(void)
{
struct node_core_id id;
@@ -106,22 +106,22 @@ static void do_k8_init_and_stop_secondaries(void)
pci_write_config32(dev_f0, 0x68, val);
/* Set the lapicid */
#if (ENABLE_APIC_EXT_ID == 1)
#if (CONFIG_ENABLE_APIC_EXT_ID == 1)
unsigned initial_apicid = get_initial_apicid();
#if LIFT_BSP_APIC_ID == 0
#if CONFIG_LIFT_BSP_APIC_ID == 0
if( initial_apicid != 0 ) // other than bsp
#endif
{
/* use initial apic id to lift it */
uint32_t dword = lapic_read(LAPIC_ID);
dword &= ~(0xff<<24);
dword |= (((initial_apicid + APIC_ID_OFFSET) & 0xff)<<24);
dword |= (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff)<<24);
lapic_write(LAPIC_ID, dword);
}
#if LIFT_BSP_APIC_ID == 1
bsp_apicid += APIC_ID_OFFSET;
#if CONFIG_LIFT_BSP_APIC_ID == 1
bsp_apicid += CONFIG_APIC_ID_OFFSET;
#endif
#endif

12
src/cpu/amd/model_10xxx/Config.lb
View File

@@ -17,13 +17,13 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
uses HAVE_INIT_TIMER
uses HAVE_MOVNTI
uses CPU_ADDR_BITS
uses CONFIG_HAVE_INIT_TIMER
uses CONFIG_HAVE_MOVNTI
uses CONFIG_CPU_ADDR_BITS
default HAVE_INIT_TIMER=1
default HAVE_MOVNTI=1
default CPU_ADDR_BITS=48
default CONFIG_HAVE_INIT_TIMER=1
default CONFIG_HAVE_MOVNTI=1
default CONFIG_CPU_ADDR_BITS=48
dir /cpu/x86/tsc
dir /cpu/x86/fpu
dir /cpu/x86/mmx

36
src/cpu/amd/model_10xxx/init_cpus.c
View File

@@ -19,7 +19,7 @@
#include "defaults.h"
//it takes the ENABLE_APIC_EXT_ID and APIC_ID_OFFSET and LIFT_BSP_APIC_ID
//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID
#ifndef FAM10_SET_FIDVID
#define FAM10_SET_FIDVID 1
#endif
@@ -58,13 +58,13 @@ static void prep_fid_change(void);
static void init_fidvid_stage2(u32 apicid, u32 nodeid);
void cpuSetAMDMSR(void);
#if PCI_IO_CFG_EXT == 1
#if CONFIG_PCI_IO_CFG_EXT == 1
static void set_EnableCf8ExtCfg(void)
{
// set the NB_CFG[46]=1;
msr_t msr;
msr = rdmsr(NB_CFG_MSR);
// EnableCf8ExtCfg: We need that to access PCI_IO_CFG_EXT 4K range
// EnableCf8ExtCfg: We need that to access CONFIG_PCI_IO_CFG_EXT 4K range
msr.hi |= (1<<(46-32));
wrmsr(NB_CFG_MSR, msr);
}
@@ -80,12 +80,12 @@ static void set_EnableCf8ExtCfg(void) { }
static void set_pci_mmio_conf_reg(void)
{
#if MMCONF_SUPPORT
#if CONFIG_MMCONF_SUPPORT
msr_t msr;
msr = rdmsr(0xc0010058);
msr.lo &= ~(0xfff00000 | (0xf << 2));
// 256 bus per segment, MMIO reg will be 4G , enable MMIO Config space
msr.lo |= ((8+PCI_BUS_SEGN_BITS) << 2) | (1 << 0);
msr.lo |= ((8+CONFIG_PCI_BUS_SEGN_BITS) << 2) | (1 << 0);
msr.hi &= ~(0x0000ffff);
msr.hi |= (PCI_MMIO_BASE >> (32-8));
wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg
@@ -168,11 +168,11 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range,
for (j = jstart; j <= jend; j++) {
ap_apicid = i * (nb_cfg_54 ? (siblings + 1):1) + j * (nb_cfg_54 ? 1:64);
#if (ENABLE_APIC_EXT_ID == 1) && (APIC_ID_OFFSET > 0)
#if LIFT_BSP_APIC_ID == 0
#if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0)
#if CONFIG_LIFT_BSP_APIC_ID == 0
if( (i != 0) || (j != 0)) /* except bsp */
#endif
ap_apicid += APIC_ID_OFFSET;
ap_apicid += CONFIG_APIC_ID_OFFSET;
#endif
if(ap_apicid == bsp_apicid) continue;
@@ -307,8 +307,8 @@ static void STOP_CAR_AND_CPU()
}
#ifndef MEM_TRAIN_SEQ
#define MEM_TRAIN_SEQ 0
#ifndef CONFIG_MEM_TRAIN_SEQ
#define CONFIG_MEM_TRAIN_SEQ 0
#endif
#if RAMINIT_SYSINFO == 1
@@ -337,7 +337,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
if(id.coreid == 0) {
set_apicid_cpuid_lo(); /* only set it on core0 */
set_EnableCf8ExtCfg(); /* only set it on core0 */
#if (ENABLE_APIC_EXT_ID == 1)
#if (CONFIG_ENABLE_APIC_EXT_ID == 1)
enable_apic_ext_id(id.nodeid);
#endif
}
@@ -345,23 +345,23 @@ static u32 init_cpus(u32 cpu_init_detectedx)
enable_lapic();
#if (ENABLE_APIC_EXT_ID == 1) && (APIC_ID_OFFSET > 0)
#if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0)
u32 initial_apicid = get_initial_apicid();
#if LIFT_BSP_APIC_ID == 0
#if CONFIG_LIFT_BSP_APIC_ID == 0
if( initial_apicid != 0 ) // other than bsp
#endif
{
/* use initial apic id to lift it */
u32 dword = lapic_read(LAPIC_ID);
dword &= ~(0xff << 24);
dword |= (((initial_apicid + APIC_ID_OFFSET) & 0xff) << 24);
dword |= (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff) << 24);
lapic_write(LAPIC_ID, dword);
}
#if LIFT_BSP_APIC_ID == 1
bsp_apicid += APIC_ID_OFFSET;
#if CONFIG_LIFT_BSP_APIC_ID == 1
bsp_apicid += CONFIG_APIC_ID_OFFSET;
#endif
#endif
@@ -478,8 +478,8 @@ static void start_node(u8 node)
/* Enable routing table */
printk_debug("Start node %02x", node);
#if CAR_FAM10 == 1
/* For CAR_FAM10 support, we need to set Dram base/limit for the new node */
#if CONFIG_CAR_FAM10 == 1
/* For CONFIG_CAR_FAM10 support, we need to set Dram base/limit for the new node */
pci_write_config32(NODE_MP(node), 0x44, 0);
pci_write_config32(NODE_MP(node), 0x40, 3);
#endif

2
src/cpu/amd/model_10xxx/update_microcode.c
View File

@@ -47,7 +47,7 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = {
* 00100F62h (DA-C2) 1062h 0100009Fh
*/
#include AMD_UCODE_PATCH_FILE
#include CONFIG_AMD_UCODE_PATCH_FILE
#endif
/* Dummy terminator */

12
src/cpu/amd/model_fxx/Config.lb
View File

@@ -1,10 +1,10 @@
uses HAVE_INIT_TIMER
uses HAVE_MOVNTI
uses CPU_ADDR_BITS
uses CONFIG_HAVE_INIT_TIMER
uses CONFIG_HAVE_MOVNTI
uses CONFIG_CPU_ADDR_BITS
default HAVE_INIT_TIMER=1
default HAVE_MOVNTI=1
default CPU_ADDR_BITS=40
default CONFIG_HAVE_INIT_TIMER=1
default CONFIG_HAVE_MOVNTI=1
default CONFIG_CPU_ADDR_BITS=40
dir /cpu/x86/tsc
dir /cpu/x86/fpu
dir /cpu/x86/mmx

2
src/cpu/amd/model_fxx/fidvid.c
View File

@@ -73,7 +73,7 @@ static void enable_fid_change(void)
// dword = 0x00070000; /* enable FID/VID change */
pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0x80, dword);
#if HAVE_ACPI_RESUME
#if CONFIG_HAVE_ACPI_RESUME
dword = 0x21132113;
#else
dword = 0x00132113;

34
src/cpu/amd/model_fxx/init_cpus.c
View File

@@ -1,6 +1,6 @@
//it takes the ENABLE_APIC_EXT_ID and APIC_ID_OFFSET and LIFT_BSP_APIC_ID
//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID
#ifndef K8_SET_FIDVID
#if K8_REV_F_SUPPORT == 0
#if CONFIG_K8_REV_F_SUPPORT == 0
#define K8_SET_FIDVID 0
#else
// for rev F, need to set FID to max
@@ -72,7 +72,7 @@ static void for_each_ap(unsigned bsp_apicid, unsigned core_range, process_ap_t p
nodes = get_nodes();
disable_siblings = !CONFIG_LOGICAL_CPUS;
#if CONFIG_LOGICAL_CPUS == 1 && HAVE_OPTION_TABLE == 1
#if CONFIG_LOGICAL_CPUS == 1 && CONFIG_HAVE_OPTION_TABLE == 1
if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { // 0 mean dual core
disable_siblings = 1;
}
@@ -87,7 +87,7 @@ static void for_each_ap(unsigned bsp_apicid, unsigned core_range, process_ap_t p
j = ((pci_read_config32(PCI_DEV(0, 0x18+i, 3), 0xe8) >> 12) & 3);
if(nb_cfg_54) {
if(j == 0 ){ // if it is single core, we need to increase siblings for apic calculation
#if K8_REV_F_SUPPORT == 0
#if CONFIG_K8_REV_F_SUPPORT == 0
e0_later_single_core = is_e0_later_in_bsp(i); // single core
#else
e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3
@@ -119,11 +119,11 @@ static void for_each_ap(unsigned bsp_apicid, unsigned core_range, process_ap_t p
ap_apicid = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
#if (ENABLE_APIC_EXT_ID == 1)
#if LIFT_BSP_APIC_ID == 0
#if (CONFIG_ENABLE_APIC_EXT_ID == 1)
#if CONFIG_LIFT_BSP_APIC_ID == 0
if( (i!=0) || (j!=0)) /* except bsp */
#endif
ap_apicid += APIC_ID_OFFSET;
ap_apicid += CONFIG_APIC_ID_OFFSET;
#endif
if(ap_apicid == bsp_apicid) continue;
@@ -238,12 +238,12 @@ static void STOP_CAR_AND_CPU(void)
stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp ....
}
#ifndef MEM_TRAIN_SEQ
#define MEM_TRAIN_SEQ 0
#ifndef CONFIG_MEM_TRAIN_SEQ
#define CONFIG_MEM_TRAIN_SEQ 0
#endif
#if MEM_TRAIN_SEQ == 1
#if CONFIG_MEM_TRAIN_SEQ == 1
static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall);
#endif
@@ -268,7 +268,7 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
/* NB_CFG MSR is shared between cores, so we need make sure core0 is done at first --- use wait_all_core0_started */
if(id.coreid == 0) {
set_apicid_cpuid_lo(); /* only set it on core0 */
#if ENABLE_APIC_EXT_ID == 1
#if CONFIG_ENABLE_APIC_EXT_ID == 1
enable_apic_ext_id(id.nodeid);
#endif
}
@@ -276,22 +276,22 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
enable_lapic();
// init_timer(); // We need TMICT to pass msg for FID/VID change
#if (ENABLE_APIC_EXT_ID == 1)
#if (CONFIG_ENABLE_APIC_EXT_ID == 1)
unsigned initial_apicid = get_initial_apicid();
#if LIFT_BSP_APIC_ID == 0
#if CONFIG_LIFT_BSP_APIC_ID == 0
if( initial_apicid != 0 ) // other than bsp
#endif
{
/* use initial apic id to lift it */
uint32_t dword = lapic_read(LAPIC_ID);
dword &= ~(0xff<<24);
dword |= (((initial_apicid + APIC_ID_OFFSET) & 0xff)<<24);
dword |= (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff)<<24);
lapic_write(LAPIC_ID, dword);
}
#if LIFT_BSP_APIC_ID == 1
bsp_apicid += APIC_ID_OFFSET;
#if CONFIG_LIFT_BSP_APIC_ID == 1
bsp_apicid += CONFIG_APIC_ID_OFFSET;
#endif
#endif
@@ -346,7 +346,7 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
}
lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu
set_init_ram_access();
#if MEM_TRAIN_SEQ == 1
#if CONFIG_MEM_TRAIN_SEQ == 1
train_ram_on_node(id.nodeid, id.coreid, sysinfo, STOP_CAR_AND_CPU);
#endif

28
src/cpu/amd/model_fxx/model_fxx_init.c
View File

@@ -32,15 +32,15 @@
void cpus_ready_for_init(void)
{
#if MEM_TRAIN_SEQ == 1
struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE);
#if CONFIG_MEM_TRAIN_SEQ == 1
struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
// wait for ap memory to trained
wait_all_core0_mem_trained(sysinfox);
#endif
}
#if K8_REV_F_SUPPORT == 0
#if CONFIG_K8_REV_F_SUPPORT == 0
int is_e0_later_in_bsp(int nodeid)
{
uint32_t val;
@@ -67,7 +67,7 @@ int is_e0_later_in_bsp(int nodeid)
}
#endif
#if K8_REV_F_SUPPORT == 1
#if CONFIG_K8_REV_F_SUPPORT == 1
int is_cpu_f0_in_bsp(int nodeid)
{
uint32_t dword;
@@ -289,8 +289,8 @@ static void init_ecc_memory(unsigned node_id)
startk = (pci_read_config32(f1_dev, 0x40 + (node_id*8)) & 0xffff0000) >> 2;
endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000;
#if HW_MEM_HOLE_SIZEK != 0
#if K8_REV_F_SUPPORT == 0
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
#if CONFIG_K8_REV_F_SUPPORT == 0
if (!is_cpu_pre_e0())
{
#endif
@@ -300,7 +300,7 @@ static void init_ecc_memory(unsigned node_id)
if(val & 1) {
hole_startk = ((val & (0xff<<24)) >> 10);
}
#if K8_REV_F_SUPPORT == 0
#if CONFIG_K8_REV_F_SUPPORT == 0
}
#endif
#endif
@@ -322,7 +322,7 @@ static void init_ecc_memory(unsigned node_id)
disable_lapic();
/* Walk through 2M chunks and zero them */
#if HW_MEM_HOLE_SIZEK != 0
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
/* here hole_startk can not be equal to begink, never. Also hole_startk is in 2M boundary, 64M? */
if ( (hole_startk != 0) && ((begink < hole_startk) && (endk>(4*1024*1024)))) {
for(basek = begink; basek < hole_startk;
@@ -368,7 +368,7 @@ static void init_ecc_memory(unsigned node_id)
static inline void k8_errata(void)
{
msr_t msr;
#if K8_REV_F_SUPPORT == 0
#if CONFIG_K8_REV_F_SUPPORT == 0
if (is_cpu_pre_c0()) {
/* Erratum 63... */
msr = rdmsr(HWCR_MSR);
@@ -438,7 +438,7 @@ static inline void k8_errata(void)
}
#endif
#if K8_REV_F_SUPPORT == 0
#if CONFIG_K8_REV_F_SUPPORT == 0
if (!is_cpu_pre_e0())
#endif
{
@@ -453,7 +453,7 @@ static inline void k8_errata(void)
msr.lo |= 1 << 6;
wrmsr(HWCR_MSR, msr);
#if K8_REV_F_SUPPORT == 1
#if CONFIG_K8_REV_F_SUPPORT == 1
/* Erratum 131... */
msr = rdmsr(NB_CFG_MSR);
msr.lo |= 1 << 20;
@@ -478,7 +478,7 @@ void model_fxx_init(device_t dev)
unsigned siblings;
#endif
#if K8_REV_F_SUPPORT == 1
#if CONFIG_K8_REV_F_SUPPORT == 1
struct cpuinfo_x86 c;
get_fms(&c, dev->device);
@@ -564,7 +564,7 @@ static struct device_operations cpu_dev_ops = {
};
static struct cpu_device_id cpu_table[] = {
#if K8_REV_F_SUPPORT == 0
#if CONFIG_K8_REV_F_SUPPORT == 0
{ X86_VENDOR_AMD, 0xf40 }, /* SH-B0 (socket 754) */
{ X86_VENDOR_AMD, 0xf50 }, /* SH-B0 (socket 940) */
{ X86_VENDOR_AMD, 0xf51 }, /* SH-B3 (socket 940) */
@@ -606,7 +606,7 @@ static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x30ff2 }, /* E4 ? */
#endif
#if K8_REV_F_SUPPORT == 1
#if CONFIG_K8_REV_F_SUPPORT == 1
/*
* AMD F0 support.
*

8
src/cpu/amd/model_fxx/model_fxx_update_microcode.c
View File

@@ -52,13 +52,13 @@ $1.0$
static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = {
#if K8_REV_F_SUPPORT == 0
#if CONFIG_K8_REV_F_SUPPORT == 0
#include "microcode_rev_c.h"
#include "microcode_rev_d.h"
#include "microcode_rev_e.h"
#endif
#if K8_REV_F_SUPPORT == 1
#if CONFIG_K8_REV_F_SUPPORT == 1
// #include "microcode_rev_f.h"
#endif
/* Dummy terminator */
@@ -70,7 +70,7 @@ static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = {
static unsigned get_equivalent_processor_rev_id(unsigned orig_id) {
static unsigned id_mapping_table[] = {
#if K8_REV_F_SUPPORT == 0
#if CONFIG_K8_REV_F_SUPPORT == 0
0x0f48, 0x0048,
0x0f58, 0x0048,
@@ -93,7 +93,7 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) {
0x20fb1, 0x0210,
#endif
#if K8_REV_F_SUPPORT == 1
#if CONFIG_K8_REV_F_SUPPORT == 1
#endif

2
src/cpu/amd/model_fxx/powernow_acpi.c
View File

@@ -169,7 +169,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
cpuid1 = cpuid(0x80000001);
pwr_lmt = ((cpuid1.ebx & 0x1C0) >> 5) | ((cpuid1.ebx & 0x4000) >> 14);
for (index = 0; index <= sizeof(TDP) / sizeof(TDP[0]); index++)
if (TDP[index].socket_type == CPU_SOCKET_TYPE &&
if (TDP[index].socket_type == CONFIG_CPU_SOCKET_TYPE &&
TDP[index].cmp_cap == cmp_cap &&
TDP[index].pwr_lmt == pwr_lmt) {
power_limit = TDP[index].power_limit;

10
src/cpu/amd/model_fxx/processor_name.c
View File

@@ -41,7 +41,7 @@
* your mainboard will not be posted on the AMD Recommended Motherboard Website
*/
#if K8_REV_F_SUPPORT == 0
#if CONFIG_K8_REV_F_SUPPORT == 0
static char *processor_names[]={
/* 0x00 */ "AMD Engineering Sample",
/* 0x01-0x03 */ NULL, NULL, NULL,
@@ -163,7 +163,7 @@ int init_processor_name(void)
char program_string[48];
unsigned int *program_values = (unsigned int *)program_string;
#if K8_REV_F_SUPPORT == 0
#if CONFIG_K8_REV_F_SUPPORT == 0
/* Find out which CPU brand it is */
EightBitBrandId = cpuid_ebx(0x00000001) & 0xff;
BrandId = cpuid_ebx(0x80000001) & 0xffff;
@@ -187,7 +187,7 @@ int init_processor_name(void)
processor_name_string = "AMD Processor model unknown";
#endif
#if K8_REV_F_SUPPORT == 1
#if CONFIG_K8_REV_F_SUPPORT == 1
u32 Socket;
u32 CmpCap;
u32 PwrLmt;
@@ -343,7 +343,7 @@ int init_processor_name(void)
for (i=0; i<47; i++) { // 48 -1
if(program_string[i] == program_string[i+1]) {
switch (program_string[i]) {
#if K8_REV_F_SUPPORT == 0
#if CONFIG_K8_REV_F_SUPPORT == 0
case 'X': ModelNumber = 22+ NN; break;
case 'Y': ModelNumber = 38 + (2*NN); break;
case 'Z':
@@ -352,7 +352,7 @@ int init_processor_name(void)
case 'V': ModelNumber = 9 + NN; break;
#endif
#if K8_REV_F_SUPPORT == 1
#if CONFIG_K8_REV_F_SUPPORT == 1
case 'R': ModelNumber = NN - 1; break;
case 'P': ModelNumber = 26 + NN; break;
case 'T': ModelNumber = 15 + (CmpCap * 10) + NN; break;

2
src/cpu/amd/model_gx2/vsmsetup.c
View File

@@ -271,7 +271,7 @@ void do_vsmbios(void)
//rom = 0xfff80000;
//rom = 0xfffc0000;
/* the VSA starts at the base of rom - 64 */
rom = ((unsigned long) 0) - (ROM_SIZE + 64*1024);
rom = ((unsigned long) 0) - (CONFIG_ROM_SIZE + 64*1024);
buf = (unsigned char *) 0x60000;
olen = unrv2b((uint8_t *)rom, buf, &ilen);

28
src/cpu/amd/model_lx/cache_as_ram.inc
View File

@@ -17,8 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define LX_STACK_BASE DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */
#define LX_STACK_END LX_STACK_BASE+(DCACHE_RAM_SIZE-1)
#define LX_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */
#define LX_STACK_END LX_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1)
#define LX_NUM_CACHELINES 0x080 /* there are 128lines per way */
#define LX_CACHELINE_SIZE 0x020 /* there are 32bytes per line */
@@ -82,7 +82,7 @@ DCacheSetup:
xorl %esi, %esi
xorl %ebp, %ebp
/* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + DCACHE_RAM_SIZE for holding stack */
/* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + CONFIG_DCACHE_RAM_SIZE for holding stack */
/* remember, there is NO stack yet... */
/* Tell cache we want to fill WAY 0 starting at the top */
@@ -192,7 +192,7 @@ done_cache_as_ram_main:
mov string, %ebx ; \
CALLSP(crt_console_tx_string)
# if defined(TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
# if defined(CONFIG_TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
# define CONSOLE_DEBUG_TX_STRING(string) __CRT_CONSOLE_TX_STRING(string)
# else
# define CONSOLE_DEBUG_TX_STRING(string)
@@ -333,26 +333,26 @@ crt_console_tx_string:
RETSP
9:
/* Base Address */
#ifndef TTYS0_BASE
#define TTYS0_BASE 0x3f8
#ifndef CONFIG_TTYS0_BASE
#define CONFIG_TTYS0_BASE 0x3f8
#endif
/* Data */
#define TTYS0_RBR (TTYS0_BASE+0x00)
#define TTYS0_RBR (CONFIG_TTYS0_BASE+0x00)
/* Control */
#define TTYS0_TBR TTYS0_RBR
#define TTYS0_IER (TTYS0_BASE+0x01)
#define TTYS0_IIR (TTYS0_BASE+0x02)
#define TTYS0_IER (CONFIG_TTYS0_BASE+0x01)
#define TTYS0_IIR (CONFIG_TTYS0_BASE+0x02)
#define TTYS0_FCR TTYS0_IIR
#define TTYS0_LCR (TTYS0_BASE+0x03)
#define TTYS0_MCR (TTYS0_BASE+0x04)
#define TTYS0_LCR (CONFIG_TTYS0_BASE+0x03)
#define TTYS0_MCR (CONFIG_TTYS0_BASE+0x04)
#define TTYS0_DLL TTYS0_RBR
#define TTYS0_DLM TTYS0_IER
/* Status */
#define TTYS0_LSR (TTYS0_BASE+0x05)
#define TTYS0_MSR (TTYS0_BASE+0x06)
#define TTYS0_SCR (TTYS0_BASE+0x07)
#define TTYS0_LSR (CONFIG_TTYS0_BASE+0x05)
#define TTYS0_MSR (CONFIG_TTYS0_BASE+0x06)
#define TTYS0_SCR (CONFIG_TTYS0_BASE+0x07)
mov %al, %ah
10: mov $TTYS0_LSR, %dx

2
src/cpu/amd/model_lx/syspreinit.c
View File

@@ -39,7 +39,7 @@ void SystemPreInit(void)
{
/* they want a jump ... */
#ifndef USE_DCACHE_RAM
#ifndef CONFIG_USE_DCACHE_RAM
__asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n");
#endif
StartTimer1();

2
src/cpu/amd/model_lx/vsmsetup.c
View File

@@ -292,7 +292,7 @@ void do_vsmbios(void)
*/
//VSA is cat onto the end after LB builds
rom = ((unsigned long)0) - (ROM_SIZE + 36 * 1024);
rom = ((unsigned long)0) - (CONFIG_ROM_SIZE + 36 * 1024);
buf = (unsigned char *)VSA2_BUFFER;
olen = unrv2b((uint8_t *) rom, buf, &ilen);
printk_debug("buf ilen %d olen%d\n", ilen, olen);

4
src/cpu/amd/mtrr/amd_earlymtrr.c
View File

@@ -41,11 +41,11 @@ static void do_amd_early_mtrr_init(const unsigned long *mtrr_msrs)
msr.lo = (((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK);
wrmsr(TOP_MEM, msr);
#if defined(XIP_ROM_SIZE)
#if defined(CONFIG_XIP_ROM_SIZE)
/* enable write through caching so we can do execute in place
* on the flash rom.
*/
set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
set_var_mtrr(1, CONFIG_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
#endif
/* Set the default memory type and enable fixed and variable MTRRs

2
src/cpu/amd/mtrr/amd_mtrr.c
View File

@@ -180,7 +180,7 @@ void amd_setup_mtrrs(void)
/* FIXME we should probably query the cpu for this
* but so far this is all any recent AMD cpu has supported.
*/
address_bits = CPU_ADDR_BITS; //K8 could be 40, and GH could be 48
address_bits = CONFIG_CPU_ADDR_BITS; //K8 could be 40, and GH could be 48
/* Now that I have mapped what is memory and what is not
* Setup the mtrrs so we can cache the memory.

2
src/cpu/amd/quadcore/amd_sibling.c
View File

@@ -114,7 +114,7 @@ u32 get_apicid_base(u32 ioapic_num)
if((apicid_base+ioapic_num-1)>0xf) {
// We need to enable APIC EXT ID
printk_spew("if the IO APIC device doesn't support 256 apic id, \r\n you need to set ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\r\n");
printk_spew("if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\r\n");
enable_apic_ext_id(sysconf.nodes);
}

16
src/cpu/amd/socket_AM2/Config.lb
View File

@@ -1,15 +1,15 @@
uses K8_REV_F_SUPPORT
uses K8_HT_FREQ_1G_SUPPORT
uses DIMM_SUPPORT
uses CPU_SOCKET_TYPE
uses CONFIG_K8_REV_F_SUPPORT
uses CONFIG_K8_HT_FREQ_1G_SUPPORT
uses CONFIG_DIMM_SUPPORT
uses CONFIG_CPU_SOCKET_TYPE
config chip.h
default K8_REV_F_SUPPORT=1
default CONFIG_K8_REV_F_SUPPORT=1
#Opteron K8 1G HT Support
default K8_HT_FREQ_1G_SUPPORT=1
default DIMM_SUPPORT=0x0004 #DDR2 unbuffered
default CPU_SOCKET_TYPE=0x11
default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
default CONFIG_DIMM_SUPPORT=0x0004 #DDR2 unbuffered
default CONFIG_CPU_SOCKET_TYPE=0x11
object socket_AM2.o

16
src/cpu/amd/socket_F/Config.lb
View File

@@ -1,15 +1,15 @@
uses K8_REV_F_SUPPORT
uses K8_HT_FREQ_1G_SUPPORT
uses DIMM_SUPPORT
uses CPU_SOCKET_TYPE
uses CONFIG_K8_REV_F_SUPPORT
uses CONFIG_K8_HT_FREQ_1G_SUPPORT
uses CONFIG_DIMM_SUPPORT
uses CONFIG_CPU_SOCKET_TYPE
config chip.h
default K8_REV_F_SUPPORT=1
default CONFIG_K8_REV_F_SUPPORT=1
#Opteron K8 1G HT Support
default K8_HT_FREQ_1G_SUPPORT=1
default DIMM_SUPPORT=0x0104 #DDR2 and REG
default CPU_SOCKET_TYPE=0x10
default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
default CONFIG_DIMM_SUPPORT=0x0104 #DDR2 and REG
default CONFIG_CPU_SOCKET_TYPE=0x10
object socket_F.o

46
src/cpu/amd/socket_F_1207/Config.lb
View File

@@ -17,37 +17,37 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
uses PCI_IO_CFG_EXT
uses MMCONF_SUPPORT
uses HT3_SUPPORT
uses EXT_RT_TBL_SUPPORT
uses EXT_CONF_SUPPORT
uses DIMM_SUPPORT
uses CPU_SOCKET_TYPE
uses CBB
uses CDB
uses PCI_BUS_SEGN_BITS
uses CAR_FAM10
uses CONFIG_PCI_IO_CFG_EXT
uses CONFIG_MMCONF_SUPPORT
uses CONFIG_HT3_SUPPORT
uses CONFIG_EXT_RT_TBL_SUPPORT
uses CONFIG_EXT_CONF_SUPPORT
uses CONFIG_DIMM_SUPPORT
uses CONFIG_CPU_SOCKET_TYPE
uses CONFIG_CBB
uses CONFIG_CDB
uses CONFIG_PCI_BUS_SEGN_BITS
uses CONFIG_CAR_FAM10
config chip.h
default PCI_IO_CFG_EXT=1
default CONFIG_PCI_IO_CFG_EXT=1
default HT3_SUPPORT=1
default EXT_RT_TBL_SUPPORT=0
default EXT_CONF_SUPPORT=0
default DIMM_SUPPORT=0x0104 #DDR2 and REG
default CPU_SOCKET_TYPE=0x10
default CONFIG_HT3_SUPPORT=1
default CONFIG_EXT_RT_TBL_SUPPORT=0
default CONFIG_EXT_CONF_SUPPORT=0
default CONFIG_DIMM_SUPPORT=0x0104 #DDR2 and REG
default CONFIG_CPU_SOCKET_TYPE=0x10
default CAR_FAM10=1
default CONFIG_CAR_FAM10=1
if EXT_RT_TBL_SUPPORT
default CBB=0xff
default CDB=0
if CONFIG_EXT_RT_TBL_SUPPORT
default CONFIG_CBB=0xff
default CONFIG_CDB=0
end
#default MMCONF_SUPPORT=1
#default MMCONF_SUPPORT_DEFAULT=1
#default CONFIG_MMCONF_SUPPORT=1
#default CONFIG_MMCONF_SUPPORT_DEFAULT=1
object socket_F_1207.o

16
src/cpu/amd/socket_S1G1/Config.lb
View File

@@ -1,15 +1,15 @@
uses K8_REV_F_SUPPORT
uses K8_HT_FREQ_1G_SUPPORT
uses DIMM_SUPPORT
uses CPU_SOCKET_TYPE
uses CONFIG_K8_REV_F_SUPPORT
uses CONFIG_K8_HT_FREQ_1G_SUPPORT
uses CONFIG_DIMM_SUPPORT
uses CONFIG_CPU_SOCKET_TYPE
config chip.h
default K8_REV_F_SUPPORT=1
default CONFIG_K8_REV_F_SUPPORT=1
#Opteron K8 1G HT Support
default K8_HT_FREQ_1G_SUPPORT=1
default DIMM_SUPPORT=0x0204 #DDR2 and REG, S1G1
default CPU_SOCKET_TYPE=0x12
default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
default CONFIG_DIMM_SUPPORT=0x0204 #DDR2 and REG, S1G1
default CONFIG_CPU_SOCKET_TYPE=0x12
object socket_S1G1.o

4
src/cpu/emulation/qemu-x86/northbridge.c
View File

@@ -65,7 +65,7 @@ static uint32_t find_pci_tolm(struct bus *bus)
return tolm;
}
#if HAVE_HIGH_TABLES==1
#if CONFIG_HAVE_HIGH_TABLES==1
#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
extern uint64_t high_tables_base, high_tables_size;
#endif
@@ -118,7 +118,7 @@ static void pci_domain_set_resources(device_t dev)
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tolmk - 768);
#if HAVE_HIGH_TABLES==1
#if CONFIG_HAVE_HIGH_TABLES==1
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
high_tables_size = HIGH_TABLES_SIZE * 1024;

4
src/cpu/intel/model_6ex/Config.lb
View File

@@ -1,5 +1,5 @@
uses HAVE_MOVNTI
default HAVE_MOVNTI=1
uses CONFIG_HAVE_MOVNTI
default CONFIG_HAVE_MOVNTI=1
dir /cpu/x86/tsc
dir /cpu/x86/mtrr

14
src/cpu/intel/model_6ex/cache_as_ram.inc
View File

@@ -18,8 +18,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define CACHE_AS_RAM_SIZE DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE DCACHE_RAM_BASE
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
#define post_code(x) intel_chip_post_macro(x)
#include <cpu/x86/mtrr.h>
@@ -29,7 +29,7 @@
movl %eax, %ebp
cache_as_ram:
#if USE_FALLBACK_IMAGE == 1
#if CONFIG_USE_FALLBACK_IMAGE == 1
post_code(0x20)
@@ -101,18 +101,18 @@ clear_mtrrs:
orl $(1 << 30), %eax
movl %eax, %cr0
#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
movl $0x0000000f, %edx
movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr
#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
/* enable cache */
movl %cr0, %eax

6
src/cpu/intel/model_6ex/cache_as_ram_disable.c
View File

@@ -27,7 +27,7 @@ void stage1_main(unsigned long bist)
{
unsigned int cpu_reset = 0;
#if USE_FALLBACK_IMAGE == 1
#if CONFIG_USE_FALLBACK_IMAGE == 1
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
@@ -87,10 +87,10 @@ cpu_reset_x:
}
__asm__ volatile (
/* set new esp */ /* before _RAMBASE */
/* set new esp */ /* before CONFIG_RAMBASE */
"subl %0, %%ebp\n\t"
"subl %0, %%esp\n\t"
::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- CONFIG_RAMBASE )
);
{

4
src/cpu/intel/model_6fx/Config.lb
View File

@@ -1,5 +1,5 @@
uses HAVE_MOVNTI
default HAVE_MOVNTI=1
uses CONFIG_HAVE_MOVNTI
default CONFIG_HAVE_MOVNTI=1
dir /cpu/x86/tsc
dir /cpu/x86/mtrr

14
src/cpu/intel/model_6fx/cache_as_ram.inc
View File

@@ -18,8 +18,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define CACHE_AS_RAM_SIZE DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE DCACHE_RAM_BASE
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
#define post_code(x) intel_chip_post_macro(x)
#include <cpu/x86/mtrr.h>
@@ -29,7 +29,7 @@
movl %eax, %ebp
cache_as_ram:
#if USE_FALLBACK_IMAGE == 1
#if CONFIG_USE_FALLBACK_IMAGE == 1
post_code(0x20)
@@ -108,18 +108,18 @@ clear_mtrrs:
orl $(1 << 30), %eax
movl %eax, %cr0
#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
movl $0x0000000f, %edx
movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr
#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
/* enable cache */
movl %cr0, %eax

6
src/cpu/intel/model_6fx/cache_as_ram_disable.c
View File

@@ -27,7 +27,7 @@ void stage1_main(unsigned long bist)
{
unsigned int cpu_reset = 0;
#if USE_FALLBACK_IMAGE == 1
#if CONFIG_USE_FALLBACK_IMAGE == 1
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
@@ -87,10 +87,10 @@ cpu_reset_x:
}
__asm__ volatile (
/* set new esp */ /* before _RAMBASE */
/* set new esp */ /* before CONFIG_RAMBASE */
"subl %0, %%ebp\n\t"
"subl %0, %%esp\n\t"
::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- CONFIG_RAMBASE )
);
{

4
src/cpu/intel/model_f0x/Config.lb
View File

@@ -1,5 +1,5 @@
uses HAVE_MOVNTI
default HAVE_MOVNTI=1
uses CONFIG_HAVE_MOVNTI
default CONFIG_HAVE_MOVNTI=1
dir /cpu/x86/tsc
dir /cpu/x86/mtrr
dir /cpu/x86/fpu

4
src/cpu/intel/model_f1x/Config.lb
View File

@@ -1,5 +1,5 @@
uses HAVE_MOVNTI
default HAVE_MOVNTI=1
uses CONFIG_HAVE_MOVNTI
default CONFIG_HAVE_MOVNTI=1
dir /cpu/x86/tsc
dir /cpu/x86/mtrr
dir /cpu/x86/fpu

4
src/cpu/intel/model_f2x/Config.lb
View File

@@ -1,5 +1,5 @@
uses HAVE_MOVNTI
default HAVE_MOVNTI=1
uses CONFIG_HAVE_MOVNTI
default CONFIG_HAVE_MOVNTI=1
dir /cpu/x86/tsc
dir /cpu/x86/mtrr
dir /cpu/x86/fpu

4
src/cpu/intel/model_f3x/Config.lb
View File

@@ -1,5 +1,5 @@
uses HAVE_MOVNTI
default HAVE_MOVNTI=1
uses CONFIG_HAVE_MOVNTI
default CONFIG_HAVE_MOVNTI=1
dir /cpu/x86/tsc
dir /cpu/x86/mtrr
dir /cpu/x86/fpu

4
src/cpu/intel/model_f4x/Config.lb
View File

@@ -1,5 +1,5 @@
uses HAVE_MOVNTI
default HAVE_MOVNTI=1
uses CONFIG_HAVE_MOVNTI
default CONFIG_HAVE_MOVNTI=1
dir /cpu/x86/tsc
dir /cpu/x86/mtrr
dir /cpu/x86/fpu

14
src/cpu/ppc/mpc74xx/Config.lb
View File

@@ -1,19 +1,19 @@
##
## CPU initialization
##
uses _RAMBASE
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses CONFIG_RAMBASE
uses CONFIG_USE_DCACHE_RAM
uses CONFIG_DCACHE_RAM_BASE
uses CONFIG_DCACHE_RAM_SIZE
##
## Use cache ram for initial setup
##
default USE_DCACHE_RAM=1
default CONFIG_USE_DCACHE_RAM=1
## Set dcache ram above coreboot image
default DCACHE_RAM_BASE=_RAMBASE+0x100000
default CONFIG_DCACHE_RAM_BASE=CONFIG_RAMBASE+0x100000
## Dcache size is 32Kb
default DCACHE_RAM_SIZE=0x8000
default CONFIG_DCACHE_RAM_SIZE=0x8000
initinclude "FAMILY_INIT" cpu/ppc/mpc74xx/mpc74xx.inc
object cache.S

8
src/cpu/ppc/mpc74xx/mpc74xx.inc
View File

@@ -30,7 +30,7 @@
* - enable L1 I/D caches, otherwise performance will be slow
* - set up DBATs for the following regions:
* - RAM (generally 0x00000000 -> 0x7fffffff)
* - ROM (_ROMBASE -> _ROMBASE + ROM_SIZE)
* - ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE + CONFIG_ROM_SIZE)
* - I/O (generally 0xfc000000 -> 0xfdffffff)
* - the main purpose for setting up the DBATs is so the I/O region
* can be marked cache inhibited/write through
@@ -147,7 +147,7 @@
* IBATS
*
* IBAT0 covers RAM (0 -> 256Mb)
* IBAT1 covers ROM (_ROMBASE -> _ROMBASE+ROM_SIZE)
* IBAT1 covers ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE+CONFIG_ROM_SIZE)
*/
lis r2, 0@h
ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
@@ -156,8 +156,8 @@
mtibatl 0, r2
isync
lis r2, _ROMBASE@h
#if ROM_SIZE > 1048576
lis r2, CONFIG_ROMBASE@h
#if CONFIG_ROM_SIZE > 1048576
ori r3, r2, BAT_BL_16M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
#else
ori r3, r2, BAT_BL_1M | BAT_VALID_SUPERVISOR | BAT_VALID_USER

14
src/cpu/ppc/ppc4xx/Config.lb
View File

@@ -1,19 +1,19 @@
##
## CPU initialization
##
uses _RAMBASE
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses CONFIG_RAMBASE
uses CONFIG_USE_DCACHE_RAM
uses CONFIG_DCACHE_RAM_BASE
uses CONFIG_DCACHE_RAM_SIZE
##
## PPC4XX always uses cache ram for initial setup
##
default USE_DCACHE_RAM=1
default CONFIG_USE_DCACHE_RAM=1
## Set dcache ram above coreboot image
default DCACHE_RAM_BASE=_RAMBASE+0x100000
default CONFIG_DCACHE_RAM_BASE=CONFIG_RAMBASE+0x100000
## Dcache size is 16Kb
default DCACHE_RAM_SIZE=16384
default CONFIG_DCACHE_RAM_SIZE=16384
initinclude "FAMILY_INIT" cpu/ppc/ppc4xx/ppc4xx.inc
initobject cache.S

6
src/cpu/ppc/ppc4xx/cache.S
View File

@@ -57,7 +57,7 @@ invalidate_icache:
invalidate_dcache:
li r6,0x0000 /* clear GPR 6 */
/* Do loop for # of dcache congruence classes. */
li r7,(DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
li r7,(CONFIG_DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
/* NOTE: dccci invalidates both */
mtctr r7 /* ways in the D cache */
1:
@@ -79,8 +79,8 @@ flush_dcache:
mtdccr r10
/* do loop for # of congruence classes. */
li r10,(DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
li r11,(DCACHE_RAM_SIZE / 2) /* D cache set size - 2 way sets */
li r10,(CONFIG_DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
li r11,(CONFIG_DCACHE_RAM_SIZE / 2) /* D cache set size - 2 way sets */
mtctr r10
li r10,(0xE000-0x10000) /* start at 0xFFFFE000 */
add r11,r10,r11 /* add to get to other side of cache line */

2
src/cpu/ppc/ppc4xx/pci_domain.c
View File

@@ -47,7 +47,7 @@ static void pci_domain_set_resources(device_t dev)
{
int idx = 3; /* who knows? */
ram_resource(dev, idx, 0, EMBEDDED_RAM_SIZE>>10);
ram_resource(dev, idx, 0, CONFIG_EMBEDDED_RAM_SIZE>>10);
assign_resources(&dev->link[0]);
}

8
src/cpu/ppc/ppc4xx/ppc4xx.inc
View File

@@ -94,15 +94,15 @@
isync
/*
* Enable dcache region containing DCACHE_RAM_BASE
* Enable dcache region containing CONFIG_DCACHE_RAM_BASE
* On reset all regions are set to write-back, so we
* just leave them alone.
*
* dccr = (1 << (0x1F - (DCACHE_RAM_BASE >> 27))
* dccr = (1 << (0x1F - (CONFIG_DCACHE_RAM_BASE >> 27))
*/
lis r4, DCACHE_RAM_BASE@ha
ori r4, r4, DCACHE_RAM_BASE@l
lis r4, CONFIG_DCACHE_RAM_BASE@ha
ori r4, r4, CONFIG_DCACHE_RAM_BASE@l
srwi r4, r4, 27
subfic r4, r4, 31
li r0, 1

8
src/cpu/ppc/ppc4xx/sdram.c
View File

@@ -98,17 +98,17 @@ void memory_init(void)
/* TODO: work out why this trashes cache ram */
//mtsdram0(mem_mcopt1, 0x00000000);
#if EMBEDDED_RAM_SIZE==128*1024*1024
#if CONFIG_EMBEDDED_RAM_SIZE==128*1024*1024
/* TODO */
#elif EMBEDDED_RAM_SIZE==64*1024*1024
#elif CONFIG_EMBEDDED_RAM_SIZE==64*1024*1024
set_sdram0(mem_sdtr1, TR);
set_sdram0(mem_mb0cf, B0CR);
set_sdram0(mem_rtr, RTR);
set_sdram0(mem_ecccf, ECCCF);
set_sdram0(mem_pmit, PMIT);
#elif EMBEDDED_RAM_SIZE==32*1024*1024
#elif CONFIG_EMBEDDED_RAM_SIZE==32*1024*1024
/* TODO */
#elif EMBEDDED_RAM_SIZE==16*1024*1024
#elif CONFIG_EMBEDDED_RAM_SIZE==16*1024*1024
/* TODO */
#endif

14
src/cpu/ppc/ppc7xx/Config.lb
View File

@@ -1,19 +1,19 @@
##
## CPU initialization
##
uses _RAMBASE
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses CONFIG_RAMBASE
uses CONFIG_USE_DCACHE_RAM
uses CONFIG_DCACHE_RAM_BASE
uses CONFIG_DCACHE_RAM_SIZE
##
## PPC7XX always uses cache ram for initial setup
##
default USE_DCACHE_RAM=1
default CONFIG_USE_DCACHE_RAM=1
## Set dcache ram above coreboot image
default DCACHE_RAM_BASE=_RAMBASE+0x100000
default CONFIG_DCACHE_RAM_BASE=CONFIG_RAMBASE+0x100000
## Dcache size is 16Kb
default DCACHE_RAM_SIZE=16384
default CONFIG_DCACHE_RAM_SIZE=16384
initinclude "FAMILY_INIT" cpu/ppc/ppc7xx/ppc7xx.inc

14
src/cpu/ppc/ppc7xx/ppc7xx.inc
View File

@@ -30,7 +30,7 @@
* - enable L1 I/D caches, otherwise performance will be slow
* - set up DBATs for the following regions:
* - RAM (generally 0x00000000 -> 0x7fffffff)
* - ROM (_ROMBASE -> _ROMBASE + ROM_SIZE)
* - ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE + CONFIG_ROM_SIZE)
* - I/O (generally 0xfc000000 -> 0xfdffffff)
* - the main purpose for setting up the DBATs is so the I/O region
* can be marked cache inhibited/write through
@@ -113,7 +113,7 @@
* IBATS
*
* IBAT0 covers RAM (0 -> 256Mb)
* IBAT1 covers ROM (_ROMBASE -> _ROMBASE+ROM_SIZE)
* IBAT1 covers ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE+CONFIG_ROM_SIZE)
*/
lis r2, 0@h
ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
@@ -122,8 +122,8 @@
mtibatl 0, r2
isync
lis r2, _ROMBASE@h
#if ROM_SIZE > 1048576
lis r2, CONFIG_ROMBASE@h
#if CONFIG_ROM_SIZE > 1048576
ori r3, r2, BAT_BL_16M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
#else
ori r3, r2, BAT_BL_1M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
@@ -161,9 +161,9 @@
* Initialize data cache blocks
* (assumes cache block size of 32 bytes)
*/
lis r1, DCACHE_RAM_BASE@h
ori r1, r1, DCACHE_RAM_BASE@l
li r3, (DCACHE_RAM_SIZE / 32)
lis r1, CONFIG_DCACHE_RAM_BASE@h
ori r1, r1, CONFIG_DCACHE_RAM_BASE@l
li r3, (CONFIG_DCACHE_RAM_SIZE / 32)
mtctr r3
0: dcbz r0, r1
addi r1, r1, 32

6
src/cpu/ppc/ppc970/Config.lb
View File

@@ -1,15 +1,15 @@
##
## CPU initialization
##
uses _RAMBASE
uses USE_DCACHE_RAM
uses CONFIG_RAMBASE
uses CONFIG_USE_DCACHE_RAM
##
## Assumes RAM already initialiazed
## This is true for the Apache board, but may
## not be for other 970 systems.
##
default USE_DCACHE_RAM=0
default CONFIG_USE_DCACHE_RAM=0
initinclude "FAMILY_INIT" cpu/ppc/ppc970/ppc970.inc

12
src/cpu/via/car/cache_as_ram.inc
View File

@@ -25,8 +25,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define CacheSize DCACHE_RAM_SIZE
#define CacheBase DCACHE_RAM_BASE
#define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase CONFIG_DCACHE_RAM_BASE
#include <cpu/x86/mtrr.h>
@@ -82,13 +82,13 @@ clear_fixed_var_mtrr_out:
/* MTRRPhysBase */
movl $0x202, %ecx
xorl %edx, %edx
movl $(XIP_ROM_BASE|MTRR_TYPE_WRBACK),%eax
movl $(CONFIG_XIP_ROM_BASE|MTRR_TYPE_WRBACK),%eax
wrmsr
/* MTRRPhysMask */
movl $0x203, %ecx
movl $0x0000000f,%edx
movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr
@@ -119,9 +119,9 @@ clear_fixed_var_mtrr_out:
xorl $0x5c5c5c5c,%eax
rep stosl
movl XIP_ROM_BASE, %esi
movl CONFIG_XIP_ROM_BASE, %esi
movl %esi, %edi
movl $(XIP_ROM_SIZE>>2), %ecx
movl $(CONFIG_XIP_ROM_SIZE>>2), %ecx
rep lodsl
/* The key point of this CAR code is C7 cache does not turn into

6
src/cpu/via/car/cache_as_ram_post.c
View File

@@ -78,16 +78,16 @@ and in x86_setup_fixed_mtrrs()(mtrr.c), 0-256M is set cacheable.*/
"movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax\n\t"
"wrmsr\n\t"
/*jasonzhao@viatech.com.cn add this 2008-11-27, cache XIP_ROM_BASE-SIZE to speedup the coreboot code*/
/*jasonzhao@viatech.com.cn add this 2008-11-27, cache CONFIG_XIP_ROM_BASE-SIZE to speedup the coreboot code*/
"movl $0x206, %ecx\n\t"
"xorl %edx, %edx\n\t"
"movl $XIP_ROM_BASE,%eax\n\t"
"movl $CONFIG_XIP_ROM_BASE,%eax\n\t"
"orl $(0 | 6), %eax\n\t"
"wrmsr\n\t"
"movl $0x207, %ecx\n\t"
"xorl %edx, %edx\n\t"
"movl $XIP_ROM_SIZE,%eax\n\t"
"movl $CONFIG_XIP_ROM_SIZE,%eax\n\t"
"decl %eax\n\t"
"notl %eax\n\t"
"orl $(0 | 0x800), %eax\n\t"

2
src/cpu/x86/16bit/reset16.lds
View File

@@ -5,7 +5,7 @@
SECTIONS {
/* Trigger an error if I have an unuseable start address */
_bogus = ASSERT(_start >= 0xffff0000, "_start too low. Please decrease ROM_IMAGE_SIZE");
_bogus = ASSERT(_start >= 0xffff0000, "_start too low. Please decrease CONFIG_ROM_IMAGE_SIZE");
_ROMTOP = 0xfffffff0;
. = _ROMTOP;
.reset . : {

2
src/cpu/x86/32bit/reset32.lds
View File

@@ -4,7 +4,7 @@
*/
SECTIONS {
_ROMTOP = _ROMBASE + ROM_IMAGE_SIZE - 0x10;
_ROMTOP = CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10;
. = _ROMTOP;
.reset (.): {
*(.reset)

22
src/cpu/x86/car/cache_as_ram.inc
View File

@@ -27,7 +27,7 @@
/* disable HyperThreading is done by eswar*/
/* other's is the same as AMD except remove amd specific msr */
#define CacheSize DCACHE_RAM_SIZE
#define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase (0xd0000 - CacheSize)
#include <cpu/x86/mtrr.h>
@@ -37,7 +37,7 @@
CacheAsRam:
/* hope we can skip the double set for normal part */
#if USE_FALLBACK_IMAGE == 1
#if CONFIG_USE_FALLBACK_IMAGE == 1
// Check whether the processor has HT capability
movl $01, %eax
@@ -197,29 +197,29 @@ clear_fixed_var_mtrr_out:
orl $(0x1<<30),%eax
movl %eax, %cr0
#endif /* USE_FALLBACK_IMAGE == 1*/
#endif /* CONFIG_USE_FALLBACK_IMAGE == 1*/
#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
/* enable write base caching so we can do execute in place
* on the flash rom.
*/
movl $0x202, %ecx
xorl %edx, %edx
movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
wrmsr
movl $0x203, %ecx
movl $0x0000000f, %edx
movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr
#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
/* enable cache */
movl %cr0, %eax
andl $0x9fffffff,%eax
movl %eax, %cr0
#if USE_FALLBACK_IMAGE == 1
#if CONFIG_USE_FALLBACK_IMAGE == 1
/* Read the range with lodsl*/
movl $CacheBase, %esi
@@ -277,7 +277,7 @@ clear_fixed_var_mtrr_out:
.xout1x:
#endif
#endif /*USE_FALLBACK_IMAGE == 1*/
#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/
movl $(CacheBase+CacheSize-4), %eax
@@ -314,7 +314,7 @@ var_mtrr_msr:
.long 0x20C, 0x20D, 0x20E, 0x20F
.long 0x000 /* NULL, end of table */
#if USE_FALLBACK_IMAGE == 1
#if CONFIG_USE_FALLBACK_IMAGE == 1
.align 0x1000
.code16
.global LogicalAP_SIPI
@@ -344,5 +344,5 @@ Halt_LogicalAP:
hlt
jmp Halt_LogicalAP
.code32
#endif /*USE_FALLBACK_IMAGE == 1*/
#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/
.CacheAsRam_out:

2
src/cpu/x86/car/cache_as_ram_post.c
View File

@@ -16,7 +16,7 @@
"xorl %edx, %edx\n\t"
"xorl %eax, %eax\n\t"
"wrmsr\n\t"
#if DCACHE_RAM_SIZE > 0x8000
#if CONFIG_DCACHE_RAM_SIZE > 0x8000
"movl $0x268, %ecx\n\t" /* fix4k_c0000*/
"wrmsr\n\t"
#endif

2
src/cpu/x86/car/copy_and_run.c
View File

@@ -10,7 +10,7 @@ static void copy_and_run(unsigned cpu_reset)
if (cpu_reset == 1) cpu_reset = -1;
else cpu_reset = 0;
# if USE_FALLBACK_IMAGE == 1
# if CONFIG_USE_FALLBACK_IMAGE == 1
cbfs_and_run_core("fallback/coreboot_ram", cpu_reset);
# else
cbfs_and_run_core("normal/coreboot_ram", cpu_reset);

42
src/cpu/x86/lapic/lapic_cpu_init.c
View File

@@ -1,6 +1,6 @@
/*
2005.12 yhlu add coreboot_ram cross the vga font buffer handling
2005.12 yhlu add _RAMBASE above 1M support for SMP
2005.12 yhlu add CONFIG_RAMBASE above 1M support for SMP
2008.05 stepan add support for going back to sipi wait state
*/
@@ -17,7 +17,7 @@
#if CONFIG_SMP == 1
#if _RAMBASE >= 0x100000
#if CONFIG_RAMBASE >= 0x100000
/* This is a lot more paranoid now, since Linux can NOT handle
* being told there is a CPU when none exists. So any errors
* will return 0, meaning no CPU.
@@ -31,7 +31,7 @@ static unsigned long get_valid_start_eip(unsigned long orig_start_eip)
}
#endif
#if HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME == 1
char *lowmem_backup;
char *lowmem_backup_ptr;
int lowmem_backup_size;
@@ -39,7 +39,7 @@ int lowmem_backup_size;
static void copy_secondary_start_to_1m_below(void)
{
#if _RAMBASE >= 0x100000
#if CONFIG_RAMBASE >= 0x100000
extern char _secondary_start[];
extern char _secondary_start_end[];
unsigned long code_size;
@@ -51,7 +51,7 @@ static void copy_secondary_start_to_1m_below(void)
start_eip = get_valid_start_eip((unsigned long)_secondary_start);
code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start;
#if HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME == 1
/* need to save it for RAM resume */
lowmem_backup_size = code_size;
lowmem_backup = malloc(code_size);
@@ -137,7 +137,7 @@ static int lapic_start_cpu(unsigned long apicid)
return 0;
}
#if _RAMBASE >= 0x100000
#if CONFIG_RAMBASE >= 0x100000
start_eip = get_valid_start_eip((unsigned long)_secondary_start);
#else
start_eip = (unsigned long)_secondary_start;
@@ -246,14 +246,14 @@ int start_cpu(device_t cpu)
index = ++last_cpu_index;
/* Find end of the new processors stack */
#if (CONFIG_LB_MEM_TOPK>1024) && (_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
#if (CONFIG_LB_MEM_TOPK>1024) && (CONFIG_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
if(index<1) { // only keep bsp on low
stack_end = ((unsigned long)_estack) - (STACK_SIZE*index) - sizeof(struct cpu_info);
stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info);
} else {
// for all APs, let use stack after pgtbl, 20480 is the pgtbl size for every cpu
stack_end = 0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPUS - (STACK_SIZE*index);
#if (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPUS) > (CONFIG_LB_MEM_TOPK<<10)
#warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPUS)\n"
stack_end = 0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS - (CONFIG_STACK_SIZE*index);
#if (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS) > (CONFIG_LB_MEM_TOPK<<10)
#warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS)\n"
#endif
if(stack_end > (CONFIG_LB_MEM_TOPK<<10)) {
printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %luK\n", stack_end>>10);
@@ -262,7 +262,7 @@ int start_cpu(device_t cpu)
stack_end -= sizeof(struct cpu_info);
}
#else
stack_end = ((unsigned long)_estack) - (STACK_SIZE*index) - sizeof(struct cpu_info);
stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info);
#endif
@@ -363,13 +363,13 @@ void stop_this_cpu(void)
void secondary_cpu_init(void)
{
atomic_inc(&active_cpus);
#if SERIAL_CPU_INIT == 1
#if CONFIG_SERIAL_CPU_INIT == 1
#if CONFIG_MAX_CPUS>2
spin_lock(&start_cpu_lock);
#endif
#endif
cpu_initialize();
#if SERIAL_CPU_INIT == 1
#if CONFIG_SERIAL_CPU_INIT == 1
#if CONFIG_MAX_CPUS>2
spin_unlock(&start_cpu_lock);
#endif
@@ -389,7 +389,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
if (cpu->path.type != DEVICE_PATH_APIC) {
continue;
}
#if SERIAL_CPU_INIT == 0
#if CONFIG_SERIAL_CPU_INIT == 0
if(cpu==bsp_cpu) {
continue;
}
@@ -408,7 +408,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
printk_err("CPU 0x%02x would not start!\n",
cpu->path.apic.apic_id);
}
#if SERIAL_CPU_INIT == 1
#if CONFIG_SERIAL_CPU_INIT == 1
#if CONFIG_MAX_CPUS>2
udelay(10);
#endif
@@ -448,13 +448,13 @@ static void wait_other_cpus_stop(struct bus *cpu_bus)
#define initialize_other_cpus(root) do {} while(0)
#endif /* CONFIG_SMP */
#if WAIT_BEFORE_CPUS_INIT==0
#if CONFIG_WAIT_BEFORE_CPUS_INIT==0
#define cpus_ready_for_init() do {} while(0)
#else
void cpus_ready_for_init(void);
#endif
#if HAVE_SMI_HANDLER
#if CONFIG_HAVE_SMI_HANDLER
void smm_init(void);
#endif
@@ -486,14 +486,14 @@ void initialize_cpus(struct bus *cpu_bus)
copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init
#endif
#if HAVE_SMI_HANDLER
#if CONFIG_HAVE_SMI_HANDLER
smm_init();
#endif
cpus_ready_for_init();
#if CONFIG_SMP == 1
#if SERIAL_CPU_INIT == 0
#if CONFIG_SERIAL_CPU_INIT == 0
/* start all aps at first, so we can init ECC all together */
start_other_cpus(cpu_bus, info->cpu);
#endif
@@ -503,7 +503,7 @@ void initialize_cpus(struct bus *cpu_bus)
cpu_initialize();
#if CONFIG_SMP == 1
#if SERIAL_CPU_INIT == 1
#if CONFIG_SERIAL_CPU_INIT == 1
start_other_cpus(cpu_bus, info->cpu);
#endif

28
src/cpu/x86/mtrr/earlymtrr.c
View File

@@ -4,22 +4,22 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
/* Validate XIP_ROM_SIZE and XIP_ROM_BASE */
#if defined(XIP_ROM_SIZE) && !defined(XIP_ROM_BASE)
# error "XIP_ROM_SIZE without XIP_ROM_BASE"
/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */
#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE)
# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE"
#endif
#if defined(XIP_ROM_BASE) && !defined(XIP_ROM_SIZE)
# error "XIP_ROM_BASE without XIP_ROM_SIZE"
#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE)
# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE"
#endif
#if !defined(CONFIG_LB_MEM_TOPK)
# error "CONFIG_LB_MEM_TOPK not defined"
#endif
#if defined(XIP_ROM_SIZE) && ((XIP_ROM_SIZE & (XIP_ROM_SIZE -1)) != 0)
# error "XIP_ROM_SIZE is not a power of 2"
#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
#endif
#if defined(XIP_ROM_SIZE) && ((XIP_ROM_BASE % XIP_ROM_SIZE) != 0)
# error "XIP_ROM_BASE is not a multiple of XIP_ROM_SIZE"
#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0)
# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE"
#endif
#if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0
@@ -48,7 +48,7 @@ static void set_var_mtrr(
basem.hi = 0;
wrmsr(MTRRphysBase_MSR(reg), basem);
maskm.lo = ~(size - 1) | 0x800;
maskm.hi = (1<<(CPU_ADDR_BITS-32))-1;
maskm.hi = (1<<(CONFIG_CPU_ADDR_BITS-32))-1;
wrmsr(MTRRphysMask_MSR(reg), maskm);
}
@@ -59,9 +59,9 @@ static void set_var_mtrr_x(
/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
msr_t basem, maskm;
basem.lo = (base_lo & 0xfffff000) | type;
basem.hi = base_hi & ((1<<(CPU_ADDR_BITS-32))-1);
basem.hi = base_hi & ((1<<(CONFIG_CPU_ADDR_BITS-32))-1);
wrmsr(MTRRphysBase_MSR(reg), basem);
maskm.hi = (1<<(CPU_ADDR_BITS-32))-1;
maskm.hi = (1<<(CONFIG_CPU_ADDR_BITS-32))-1;
if(size_lo) {
maskm.lo = ~(size_lo - 1) | 0x800;
} else {
@@ -99,11 +99,11 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
wrmsr(msr_nr, msr);
}
#if defined(XIP_ROM_SIZE)
#if defined(CONFIG_XIP_ROM_SIZE)
/* enable write through caching so we can do execute in place
* on the flash rom.
*/
set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
set_var_mtrr(1, CONFIG_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
#endif
/* Set the default memory type and enable fixed and variable MTRRs

2
src/cpu/x86/pae/pgtbl.c
View File

@@ -54,7 +54,7 @@ void *map_2M_page(unsigned long page)
struct pde pdp[512];
} __attribute__ ((packed));
#if (CONFIG_LB_MEM_TOPK>1024) && (_RAMBASE<0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
#if (CONFIG_LB_MEM_TOPK>1024) && (CONFIG_RAMBASE<0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
/*
pgtbl is too big, so use last one 1M before CONFIG_LB_MEM_TOP, otherwise for 8 way dual core with vga support will push stack and heap cross 0xa0000,
and that region need to be used as vga font buffer. Please make sure set CONFIG_LB_MEM_TOPK=2048 in MB Config

8
src/cpu/x86/smm/Config.lb
View File

@@ -18,9 +18,9 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
uses HAVE_SMI_HANDLER
uses CONFIG_HAVE_SMI_HANDLER
if HAVE_SMI_HANDLER
if CONFIG_HAVE_SMI_HANDLER
object smmrelocate.S
smmobject smmhandler.S
@@ -34,8 +34,8 @@ if HAVE_SMI_HANDLER
makerule smm
depends "smm.o $(TOP)/src/cpu/x86/smm/smm.ld ldoptions"
action "$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o smm.elf -T $(TOP)/src/cpu/x86/smm/smm.ld smm.o"
action "$(CROSS_COMPILE)nm -n smm.elf | sort > smm.map"
action "$(OBJCOPY) -O binary smm.elf smm"
action "$(CONFIG_CROSS_COMPILE)nm -n smm.elf | sort > smm.map"
action "$(CONFIG_OBJCOPY) -O binary smm.elf smm"
end
makerule smm_bin.c

8
src/cpu/x86/smm/smihandler.c
View File

@@ -89,7 +89,7 @@ static inline __attribute__((always_inline)) unsigned long nodeid(void)
static int uart_can_tx_byte(void)
{
return inb(TTYS0_BASE + UART_LSR) & 0x20;
return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
}
static void uart_wait_to_tx_byte(void)
@@ -100,14 +100,14 @@ static void uart_wait_to_tx_byte(void)
static void uart_wait_until_sent(void)
{
while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
static void uart_tx_byte(unsigned char data)
{
uart_wait_to_tx_byte();
outb(data, TTYS0_BASE + UART_TBR);
outb(data, CONFIG_TTYS0_BASE + UART_TBR);
/* Make certain the data clears the fifos */
uart_wait_until_sent();
}
@@ -169,7 +169,7 @@ void smi_handler(u32 smm_revision)
node=nodeid();
#ifdef DEBUG_SMI
console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
#else
console_loglevel = 1;
#endif

2
src/cpu/x86/smm/smmrelocate.S
View File

@@ -140,7 +140,7 @@ smm_relocate:
/* End of hardware specific section. */
#ifdef DEBUG_SMM_RELOCATION
/* print [SMM-x] so we can determine if CPUx went to SMM */
movw $TTYS0_BASE, %dx
movw $CONFIG_TTYS0_BASE, %dx
mov $'[', %al
outb %al, %dx
mov $'S', %al

4
src/cpu/x86/tsc/Config.lb
View File

@@ -1,9 +1,9 @@
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses HAVE_INIT_TIMER
uses CONFIG_HAVE_INIT_TIMER
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0
if CONFIG_UDELAY_TSC
default HAVE_INIT_TIMER=1
default CONFIG_HAVE_INIT_TIMER=1
object delay_tsc.o
end