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This patch unifies the use of config options in v2 to all start with CONFIG_

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It's basically done with the following script and some manual fixup:

VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
	find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2009-06-30 15:17:49 +00:00
committed by Stefan Reinauer
parent 9702b6bf7e
commit 0867062412
863 changed files with 14632 additions and 14632 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/x86/16bit/reset16.lds
View File

@@ -5,7 +5,7 @@
SECTIONS {
/* Trigger an error if I have an unuseable start address */
_bogus = ASSERT(_start >= 0xffff0000, "_start too low. Please decrease ROM_IMAGE_SIZE");
_bogus = ASSERT(_start >= 0xffff0000, "_start too low. Please decrease CONFIG_ROM_IMAGE_SIZE");
_ROMTOP = 0xfffffff0;
. = _ROMTOP;
.reset . : {

2
src/cpu/x86/32bit/reset32.lds
View File

@@ -4,7 +4,7 @@
*/
SECTIONS {
_ROMTOP = _ROMBASE + ROM_IMAGE_SIZE - 0x10;
_ROMTOP = CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10;
. = _ROMTOP;
.reset (.): {
*(.reset)

22
src/cpu/x86/car/cache_as_ram.inc
View File

@@ -27,7 +27,7 @@
/* disable HyperThreading is done by eswar*/
/* other's is the same as AMD except remove amd specific msr */
#define CacheSize DCACHE_RAM_SIZE
#define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase (0xd0000 - CacheSize)
#include <cpu/x86/mtrr.h>
@@ -37,7 +37,7 @@
CacheAsRam:
/* hope we can skip the double set for normal part */
#if USE_FALLBACK_IMAGE == 1
#if CONFIG_USE_FALLBACK_IMAGE == 1
// Check whether the processor has HT capability
movl $01, %eax
@@ -197,29 +197,29 @@ clear_fixed_var_mtrr_out:
orl $(0x1<<30),%eax
movl %eax, %cr0
#endif /* USE_FALLBACK_IMAGE == 1*/
#endif /* CONFIG_USE_FALLBACK_IMAGE == 1*/
#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
/* enable write base caching so we can do execute in place
* on the flash rom.
*/
movl $0x202, %ecx
xorl %edx, %edx
movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
wrmsr
movl $0x203, %ecx
movl $0x0000000f, %edx
movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr
#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
/* enable cache */
movl %cr0, %eax
andl $0x9fffffff,%eax
movl %eax, %cr0
#if USE_FALLBACK_IMAGE == 1
#if CONFIG_USE_FALLBACK_IMAGE == 1
/* Read the range with lodsl*/
movl $CacheBase, %esi
@@ -277,7 +277,7 @@ clear_fixed_var_mtrr_out:
.xout1x:
#endif
#endif /*USE_FALLBACK_IMAGE == 1*/
#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/
movl $(CacheBase+CacheSize-4), %eax
@@ -314,7 +314,7 @@ var_mtrr_msr:
.long 0x20C, 0x20D, 0x20E, 0x20F
.long 0x000 /* NULL, end of table */
#if USE_FALLBACK_IMAGE == 1
#if CONFIG_USE_FALLBACK_IMAGE == 1
.align 0x1000
.code16
.global LogicalAP_SIPI
@@ -344,5 +344,5 @@ Halt_LogicalAP:
hlt
jmp Halt_LogicalAP
.code32
#endif /*USE_FALLBACK_IMAGE == 1*/
#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/
.CacheAsRam_out:

2
src/cpu/x86/car/cache_as_ram_post.c
View File

@@ -16,7 +16,7 @@
"xorl %edx, %edx\n\t"
"xorl %eax, %eax\n\t"
"wrmsr\n\t"
#if DCACHE_RAM_SIZE > 0x8000
#if CONFIG_DCACHE_RAM_SIZE > 0x8000
"movl $0x268, %ecx\n\t" /* fix4k_c0000*/
"wrmsr\n\t"
#endif

2
src/cpu/x86/car/copy_and_run.c
View File

@@ -10,7 +10,7 @@ static void copy_and_run(unsigned cpu_reset)
if (cpu_reset == 1) cpu_reset = -1;
else cpu_reset = 0;
# if USE_FALLBACK_IMAGE == 1
# if CONFIG_USE_FALLBACK_IMAGE == 1
cbfs_and_run_core("fallback/coreboot_ram", cpu_reset);
# else
cbfs_and_run_core("normal/coreboot_ram", cpu_reset);

42
src/cpu/x86/lapic/lapic_cpu_init.c
View File

@@ -1,6 +1,6 @@
/*
2005.12 yhlu add coreboot_ram cross the vga font buffer handling
2005.12 yhlu add _RAMBASE above 1M support for SMP
2005.12 yhlu add CONFIG_RAMBASE above 1M support for SMP
2008.05 stepan add support for going back to sipi wait state
*/
@@ -17,7 +17,7 @@
#if CONFIG_SMP == 1
#if _RAMBASE >= 0x100000
#if CONFIG_RAMBASE >= 0x100000
/* This is a lot more paranoid now, since Linux can NOT handle
* being told there is a CPU when none exists. So any errors
* will return 0, meaning no CPU.
@@ -31,7 +31,7 @@ static unsigned long get_valid_start_eip(unsigned long orig_start_eip)
}
#endif
#if HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME == 1
char *lowmem_backup;
char *lowmem_backup_ptr;
int lowmem_backup_size;
@@ -39,7 +39,7 @@ int lowmem_backup_size;
static void copy_secondary_start_to_1m_below(void)
{
#if _RAMBASE >= 0x100000
#if CONFIG_RAMBASE >= 0x100000
extern char _secondary_start[];
extern char _secondary_start_end[];
unsigned long code_size;
@@ -51,7 +51,7 @@ static void copy_secondary_start_to_1m_below(void)
start_eip = get_valid_start_eip((unsigned long)_secondary_start);
code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start;
#if HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME == 1
/* need to save it for RAM resume */
lowmem_backup_size = code_size;
lowmem_backup = malloc(code_size);
@@ -137,7 +137,7 @@ static int lapic_start_cpu(unsigned long apicid)
return 0;
}
#if _RAMBASE >= 0x100000
#if CONFIG_RAMBASE >= 0x100000
start_eip = get_valid_start_eip((unsigned long)_secondary_start);
#else
start_eip = (unsigned long)_secondary_start;
@@ -246,14 +246,14 @@ int start_cpu(device_t cpu)
index = ++last_cpu_index;
/* Find end of the new processors stack */
#if (CONFIG_LB_MEM_TOPK>1024) && (_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
#if (CONFIG_LB_MEM_TOPK>1024) && (CONFIG_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
if(index<1) { // only keep bsp on low
stack_end = ((unsigned long)_estack) - (STACK_SIZE*index) - sizeof(struct cpu_info);
stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info);
} else {
// for all APs, let use stack after pgtbl, 20480 is the pgtbl size for every cpu
stack_end = 0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPUS - (STACK_SIZE*index);
#if (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPUS) > (CONFIG_LB_MEM_TOPK<<10)
#warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPUS)\n"
stack_end = 0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS - (CONFIG_STACK_SIZE*index);
#if (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS) > (CONFIG_LB_MEM_TOPK<<10)
#warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS)\n"
#endif
if(stack_end > (CONFIG_LB_MEM_TOPK<<10)) {
printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %luK\n", stack_end>>10);
@@ -262,7 +262,7 @@ int start_cpu(device_t cpu)
stack_end -= sizeof(struct cpu_info);
}
#else
stack_end = ((unsigned long)_estack) - (STACK_SIZE*index) - sizeof(struct cpu_info);
stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info);
#endif
@@ -363,13 +363,13 @@ void stop_this_cpu(void)
void secondary_cpu_init(void)
{
atomic_inc(&active_cpus);
#if SERIAL_CPU_INIT == 1
#if CONFIG_SERIAL_CPU_INIT == 1
#if CONFIG_MAX_CPUS>2
spin_lock(&start_cpu_lock);
#endif
#endif
cpu_initialize();
#if SERIAL_CPU_INIT == 1
#if CONFIG_SERIAL_CPU_INIT == 1
#if CONFIG_MAX_CPUS>2
spin_unlock(&start_cpu_lock);
#endif
@@ -389,7 +389,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
if (cpu->path.type != DEVICE_PATH_APIC) {
continue;
}
#if SERIAL_CPU_INIT == 0
#if CONFIG_SERIAL_CPU_INIT == 0
if(cpu==bsp_cpu) {
continue;
}
@@ -408,7 +408,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
printk_err("CPU 0x%02x would not start!\n",
cpu->path.apic.apic_id);
}
#if SERIAL_CPU_INIT == 1
#if CONFIG_SERIAL_CPU_INIT == 1
#if CONFIG_MAX_CPUS>2
udelay(10);
#endif
@@ -448,13 +448,13 @@ static void wait_other_cpus_stop(struct bus *cpu_bus)
#define initialize_other_cpus(root) do {} while(0)
#endif /* CONFIG_SMP */
#if WAIT_BEFORE_CPUS_INIT==0
#if CONFIG_WAIT_BEFORE_CPUS_INIT==0
#define cpus_ready_for_init() do {} while(0)
#else
void cpus_ready_for_init(void);
#endif
#if HAVE_SMI_HANDLER
#if CONFIG_HAVE_SMI_HANDLER
void smm_init(void);
#endif
@@ -486,14 +486,14 @@ void initialize_cpus(struct bus *cpu_bus)
copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init
#endif
#if HAVE_SMI_HANDLER
#if CONFIG_HAVE_SMI_HANDLER
smm_init();
#endif
cpus_ready_for_init();
#if CONFIG_SMP == 1
#if SERIAL_CPU_INIT == 0
#if CONFIG_SERIAL_CPU_INIT == 0
/* start all aps at first, so we can init ECC all together */
start_other_cpus(cpu_bus, info->cpu);
#endif
@@ -503,7 +503,7 @@ void initialize_cpus(struct bus *cpu_bus)
cpu_initialize();
#if CONFIG_SMP == 1
#if SERIAL_CPU_INIT == 1
#if CONFIG_SERIAL_CPU_INIT == 1
start_other_cpus(cpu_bus, info->cpu);
#endif

28
src/cpu/x86/mtrr/earlymtrr.c
View File

@@ -4,22 +4,22 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
/* Validate XIP_ROM_SIZE and XIP_ROM_BASE */
#if defined(XIP_ROM_SIZE) && !defined(XIP_ROM_BASE)
# error "XIP_ROM_SIZE without XIP_ROM_BASE"
/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */
#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE)
# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE"
#endif
#if defined(XIP_ROM_BASE) && !defined(XIP_ROM_SIZE)
# error "XIP_ROM_BASE without XIP_ROM_SIZE"
#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE)
# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE"
#endif
#if !defined(CONFIG_LB_MEM_TOPK)
# error "CONFIG_LB_MEM_TOPK not defined"
#endif
#if defined(XIP_ROM_SIZE) && ((XIP_ROM_SIZE & (XIP_ROM_SIZE -1)) != 0)
# error "XIP_ROM_SIZE is not a power of 2"
#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
#endif
#if defined(XIP_ROM_SIZE) && ((XIP_ROM_BASE % XIP_ROM_SIZE) != 0)
# error "XIP_ROM_BASE is not a multiple of XIP_ROM_SIZE"
#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0)
# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE"
#endif
#if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0
@@ -48,7 +48,7 @@ static void set_var_mtrr(
basem.hi = 0;
wrmsr(MTRRphysBase_MSR(reg), basem);
maskm.lo = ~(size - 1) | 0x800;
maskm.hi = (1<<(CPU_ADDR_BITS-32))-1;
maskm.hi = (1<<(CONFIG_CPU_ADDR_BITS-32))-1;
wrmsr(MTRRphysMask_MSR(reg), maskm);
}
@@ -59,9 +59,9 @@ static void set_var_mtrr_x(
/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
msr_t basem, maskm;
basem.lo = (base_lo & 0xfffff000) | type;
basem.hi = base_hi & ((1<<(CPU_ADDR_BITS-32))-1);
basem.hi = base_hi & ((1<<(CONFIG_CPU_ADDR_BITS-32))-1);
wrmsr(MTRRphysBase_MSR(reg), basem);
maskm.hi = (1<<(CPU_ADDR_BITS-32))-1;
maskm.hi = (1<<(CONFIG_CPU_ADDR_BITS-32))-1;
if(size_lo) {
maskm.lo = ~(size_lo - 1) | 0x800;
} else {
@@ -99,11 +99,11 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
wrmsr(msr_nr, msr);
}
#if defined(XIP_ROM_SIZE)
#if defined(CONFIG_XIP_ROM_SIZE)
/* enable write through caching so we can do execute in place
* on the flash rom.
*/
set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
set_var_mtrr(1, CONFIG_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
#endif
/* Set the default memory type and enable fixed and variable MTRRs

2
src/cpu/x86/pae/pgtbl.c
View File

@@ -54,7 +54,7 @@ void *map_2M_page(unsigned long page)
struct pde pdp[512];
} __attribute__ ((packed));
#if (CONFIG_LB_MEM_TOPK>1024) && (_RAMBASE<0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
#if (CONFIG_LB_MEM_TOPK>1024) && (CONFIG_RAMBASE<0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
/*
pgtbl is too big, so use last one 1M before CONFIG_LB_MEM_TOP, otherwise for 8 way dual core with vga support will push stack and heap cross 0xa0000,
and that region need to be used as vga font buffer. Please make sure set CONFIG_LB_MEM_TOPK=2048 in MB Config

8
src/cpu/x86/smm/Config.lb
View File

@@ -18,9 +18,9 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
uses HAVE_SMI_HANDLER
uses CONFIG_HAVE_SMI_HANDLER
if HAVE_SMI_HANDLER
if CONFIG_HAVE_SMI_HANDLER
object smmrelocate.S
smmobject smmhandler.S
@@ -34,8 +34,8 @@ if HAVE_SMI_HANDLER
makerule smm
depends "smm.o $(TOP)/src/cpu/x86/smm/smm.ld ldoptions"
action "$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o smm.elf -T $(TOP)/src/cpu/x86/smm/smm.ld smm.o"
action "$(CROSS_COMPILE)nm -n smm.elf | sort > smm.map"
action "$(OBJCOPY) -O binary smm.elf smm"
action "$(CONFIG_CROSS_COMPILE)nm -n smm.elf | sort > smm.map"
action "$(CONFIG_OBJCOPY) -O binary smm.elf smm"
end
makerule smm_bin.c

8
src/cpu/x86/smm/smihandler.c
View File

@@ -89,7 +89,7 @@ static inline __attribute__((always_inline)) unsigned long nodeid(void)
static int uart_can_tx_byte(void)
{
return inb(TTYS0_BASE + UART_LSR) & 0x20;
return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
}
static void uart_wait_to_tx_byte(void)
@@ -100,14 +100,14 @@ static void uart_wait_to_tx_byte(void)
static void uart_wait_until_sent(void)
{
while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
static void uart_tx_byte(unsigned char data)
{
uart_wait_to_tx_byte();
outb(data, TTYS0_BASE + UART_TBR);
outb(data, CONFIG_TTYS0_BASE + UART_TBR);
/* Make certain the data clears the fifos */
uart_wait_until_sent();
}
@@ -169,7 +169,7 @@ void smi_handler(u32 smm_revision)
node=nodeid();
#ifdef DEBUG_SMI
console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
#else
console_loglevel = 1;
#endif

2
src/cpu/x86/smm/smmrelocate.S
View File

@@ -140,7 +140,7 @@ smm_relocate:
/* End of hardware specific section. */
#ifdef DEBUG_SMM_RELOCATION
/* print [SMM-x] so we can determine if CPUx went to SMM */
movw $TTYS0_BASE, %dx
movw $CONFIG_TTYS0_BASE, %dx
mov $'[', %al
outb %al, %dx
mov $'S', %al

4
src/cpu/x86/tsc/Config.lb
View File

@@ -1,9 +1,9 @@
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses HAVE_INIT_TIMER
uses CONFIG_HAVE_INIT_TIMER
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0
if CONFIG_UDELAY_TSC
default HAVE_INIT_TIMER=1
default CONFIG_HAVE_INIT_TIMER=1
object delay_tsc.o
end