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This patch unifies the use of config options in v2 to all start with CONFIG_

Browse Source 
It's basically done with the following script and some manual fixup:

VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
	find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2009-06-30 15:17:49 +00:00
committed by Stefan Reinauer
parent 9702b6bf7e
commit 0867062412
863 changed files with 14632 additions and 14632 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
src/mainboard/a-trend/atc-6220/Config.lb
View File

@@ -18,38 +18,38 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
if CONFIG_HAVE_PIRQ_TABLE
object irq_tables.o
end
makerule ./failover.E
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./auto.E
# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(MAINBOARD)/auto.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(MAINBOARD)/auto.c ../romcc"
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -59,7 +59,7 @@ end
mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end

120
src/mainboard/a-trend/atc-6220/Options.lb
View File

@@ -18,82 +18,82 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
uses HAVE_MP_TABLE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_ROM_PAYLOAD
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ARCH
uses CONFIG_FALLBACK_SIZE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses PAYLOAD_SIZE
uses _ROMBASE
uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
uses CROSS_COMPILE
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_RAMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
default ROM_SIZE = 256 * 1024
default HAVE_FALLBACK_BOOT = 1
default HAVE_MP_TABLE = 0
default HAVE_HARD_RESET = 0
default CONFIG_ROM_SIZE = 256 * 1024
default CONFIG_HAVE_FALLBACK_BOOT = 1
default CONFIG_HAVE_MP_TABLE = 0
default CONFIG_HAVE_HARD_RESET = 0
default CONFIG_UDELAY_TSC = 1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
default HAVE_PIRQ_TABLE = 1
default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
default ROM_IMAGE_SIZE = 64 * 1024
default FALLBACK_SIZE = 128 * 1024
default STACK_SIZE = 8 * 1024
default HEAP_SIZE = 16 * 1024
default HAVE_OPTION_TABLE = 0
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0
default _RAMBASE = 0x00004000
default CONFIG_HAVE_PIRQ_TABLE = 1
default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
default CONFIG_FALLBACK_SIZE = 128 * 1024
default CONFIG_STACK_SIZE = 8 * 1024
default CONFIG_HEAP_SIZE = 16 * 1024
default CONFIG_HAVE_OPTION_TABLE = 0
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
default CONFIG_USE_OPTION_TABLE = 0
default CONFIG_RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
default CROSS_COMPILE = ""
default CC = "$(CROSS_COMPILE)gcc -m32"
default HOSTCC = "gcc"
default CONFIG_CROSS_COMPILE = ""
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
default CONFIG_HOSTCC = "gcc"
default CONFIG_CONSOLE_SERIAL8250 = 1
default TTYS0_BAUD = 115200
default TTYS0_BASE = 0x3f8
default TTYS0_LCS = 0x3 # 8n1
default DEFAULT_CONSOLE_LOGLEVEL = 9
default MAXIMUM_CONSOLE_LOGLEVEL = 9
default CONFIG_TTYS0_BAUD = 115200
default CONFIG_TTYS0_BASE = 0x3f8
default CONFIG_TTYS0_LCS = 0x3 # 8n1
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
default CONFIG_CONSOLE_VGA = 1
default CONFIG_PCI_ROM_RUN = 1

2
src/mainboard/a-trend/atc-6220/auto.c
View File

@@ -54,7 +54,7 @@ static void main(unsigned long bist)
if (bist == 0)
early_mtrr_init();
w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE);
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
report_bist_failure(bist);

2
src/mainboard/a-trend/atc-6220/irq_tables.c
View File

@@ -23,7 +23,7 @@
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE,
PIRQ_VERSION,
32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
(0x07 << 3) | 0x0, /* Interrupt router device */
0x600, /* IRQs devoted exclusively to PCI usage */

30
src/mainboard/a-trend/atc-6240/Config.lb
View File

@@ -18,38 +18,38 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
if CONFIG_HAVE_PIRQ_TABLE
object irq_tables.o
end
makerule ./failover.E
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./auto.E
# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(MAINBOARD)/auto.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(MAINBOARD)/auto.c ../romcc"
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -59,7 +59,7 @@ end
mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end

120
src/mainboard/a-trend/atc-6240/Options.lb
View File

@@ -18,82 +18,82 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
uses HAVE_MP_TABLE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_ROM_PAYLOAD
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ARCH
uses CONFIG_FALLBACK_SIZE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses PAYLOAD_SIZE
uses _ROMBASE
uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
uses CROSS_COMPILE
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_RAMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
default ROM_SIZE = 256 * 1024
default HAVE_FALLBACK_BOOT = 1
default HAVE_MP_TABLE = 0
default HAVE_HARD_RESET = 0
default CONFIG_ROM_SIZE = 256 * 1024
default CONFIG_HAVE_FALLBACK_BOOT = 1
default CONFIG_HAVE_MP_TABLE = 0
default CONFIG_HAVE_HARD_RESET = 0
default CONFIG_UDELAY_TSC = 1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
default HAVE_PIRQ_TABLE = 1
default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
default ROM_IMAGE_SIZE = 64 * 1024
default FALLBACK_SIZE = 128 * 1024
default STACK_SIZE = 8 * 1024
default HEAP_SIZE = 16 * 1024
default HAVE_OPTION_TABLE = 0
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0
default _RAMBASE = 0x00004000
default CONFIG_HAVE_PIRQ_TABLE = 1
default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
default CONFIG_FALLBACK_SIZE = 128 * 1024
default CONFIG_STACK_SIZE = 8 * 1024
default CONFIG_HEAP_SIZE = 16 * 1024
default CONFIG_HAVE_OPTION_TABLE = 0
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
default CONFIG_USE_OPTION_TABLE = 0
default CONFIG_RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
default CROSS_COMPILE = ""
default CC = "$(CROSS_COMPILE)gcc -m32"
default HOSTCC = "gcc"
default CONFIG_CROSS_COMPILE = ""
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
default CONFIG_HOSTCC = "gcc"
default CONFIG_CONSOLE_SERIAL8250 = 1
default TTYS0_BAUD = 115200
default TTYS0_BASE = 0x3f8
default TTYS0_LCS = 0x3 # 8n1
default DEFAULT_CONSOLE_LOGLEVEL = 9
default MAXIMUM_CONSOLE_LOGLEVEL = 9
default CONFIG_TTYS0_BAUD = 115200
default CONFIG_TTYS0_BASE = 0x3f8
default CONFIG_TTYS0_LCS = 0x3 # 8n1
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
default CONFIG_CONSOLE_VGA = 1
default CONFIG_PCI_ROM_RUN = 1

2
src/mainboard/a-trend/atc-6240/auto.c
View File

@@ -54,7 +54,7 @@ static void main(unsigned long bist)
if (bist == 0)
early_mtrr_init();
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
report_bist_failure(bist);

2
src/mainboard/a-trend/atc-6240/irq_tables.c
View File

@@ -23,7 +23,7 @@
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE,
PIRQ_VERSION,
32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
(0x07 << 3) | 0x0, /* Interrupt router device */
0xc20, /* IRQs devoted exclusively to PCI usage */

30
src/mainboard/abit/be6-ii_v2_0/Config.lb
View File

@@ -18,38 +18,38 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
if CONFIG_HAVE_PIRQ_TABLE
object irq_tables.o
end
makerule ./failover.E
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./auto.E
# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(MAINBOARD)/auto.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(MAINBOARD)/auto.c ../romcc"
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -59,7 +59,7 @@ end
mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end

120
src/mainboard/abit/be6-ii_v2_0/Options.lb
View File

@@ -18,83 +18,83 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
uses HAVE_MP_TABLE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_ROM_PAYLOAD
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ARCH
uses CONFIG_FALLBACK_SIZE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses PAYLOAD_SIZE
uses _ROMBASE
uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
uses CROSS_COMPILE
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_RAMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
default ROM_SIZE = 256 * 1024 # Override this in targets/*/Config.lb.
default HAVE_FALLBACK_BOOT = 1
default HAVE_MP_TABLE = 0
default HAVE_HARD_RESET = 0
default CONFIG_ROM_SIZE = 256 * 1024 # Override this in targets/*/Config.lb.
default CONFIG_HAVE_FALLBACK_BOOT = 1
default CONFIG_HAVE_MP_TABLE = 0
default CONFIG_HAVE_HARD_RESET = 0
default CONFIG_UDELAY_TSC = 1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
default HAVE_PIRQ_TABLE = 1
default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
default ROM_IMAGE_SIZE = 64 * 1024
default FALLBACK_SIZE = 128 * 1024
default STACK_SIZE = 8 * 1024
default HEAP_SIZE = 16 * 1024
default HAVE_OPTION_TABLE = 0
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0
default _RAMBASE = 0x00004000
default CONFIG_HAVE_PIRQ_TABLE = 1
default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
default CONFIG_FALLBACK_SIZE = 128 * 1024
default CONFIG_STACK_SIZE = 8 * 1024
default CONFIG_HEAP_SIZE = 16 * 1024
default CONFIG_HAVE_OPTION_TABLE = 0
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
default CONFIG_USE_OPTION_TABLE = 0
default CONFIG_RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
default CROSS_COMPILE = ""
default CC = "$(CROSS_COMPILE)gcc -m32"
default HOSTCC = "gcc"
default CONFIG_CROSS_COMPILE = ""
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
default CONFIG_HOSTCC = "gcc"
default CONFIG_CONSOLE_SERIAL8250 = 1
default TTYS0_BAUD = 115200
default TTYS0_BASE = 0x3f8
default TTYS0_LCS = 0x3 # 8n1
default DEFAULT_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb.
default MAXIMUM_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb.
default CONFIG_TTYS0_BAUD = 115200
default CONFIG_TTYS0_BASE = 0x3f8
default CONFIG_TTYS0_LCS = 0x3 # 8n1
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb.
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb.
default CONFIG_CONSOLE_VGA = 1 # Override this in targets/*/Config.lb.
default CONFIG_PCI_ROM_RUN = 1 # Override this in targets/*/Config.lb.

2
src/mainboard/abit/be6-ii_v2_0/auto.c
View File

@@ -57,7 +57,7 @@ static void main(unsigned long bist)
early_mtrr_init();
/* FIXME: It's a Winbond W83977EF, actually. */
w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE);
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
report_bist_failure(bist);

2
src/mainboard/abit/be6-ii_v2_0/irq_tables.c
View File

@@ -23,7 +23,7 @@
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE,
PIRQ_VERSION,
32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
(0x07 << 3) | 0x0, /* Interrupt router device */
0x1c20, /* IRQs devoted exclusively to PCI usage */

30
src/mainboard/advantech/pcm-5820/Config.lb
View File

@@ -18,38 +18,38 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
if CONFIG_HAVE_PIRQ_TABLE
object irq_tables.o
end
makerule ./failover.E
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./auto.E
# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(MAINBOARD)/auto.c ../romcc"
action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(MAINBOARD)/auto.c ../romcc"
action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -59,7 +59,7 @@ end
mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end

116
src/mainboard/advantech/pcm-5820/Options.lb
View File

@@ -18,45 +18,45 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
uses HAVE_MP_TABLE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_ROM_PAYLOAD
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ARCH
uses CONFIG_FALLBACK_SIZE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD_START
uses PAYLOAD_SIZE
uses _ROMBASE
uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses CROSS_COMPILE
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_RAMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
@@ -64,7 +64,7 @@ uses CONFIG_VIDEO_MB
uses CONFIG_SPLASH_GRAPHIC
uses CONFIG_GX1_VIDEO
uses CONFIG_GX1_VIDEOMODE
uses PIRQ_ROUTE
uses CONFIG_PIRQ_ROUTE
## Enable VGA with a splash screen (only 640x480 to run on most monitors).
## We want to support up to 1024x768@16 so we need 2MiB video memory.
@@ -74,34 +74,34 @@ default CONFIG_GX1_VIDEOMODE = 0
default CONFIG_SPLASH_GRAPHIC = 1
default CONFIG_VIDEO_MB = 2
default ROM_SIZE = 256 * 1024
default HAVE_PIRQ_TABLE = 1
default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
default PIRQ_ROUTE = 1
default HAVE_FALLBACK_BOOT = 1
default HAVE_MP_TABLE = 0
default HAVE_HARD_RESET = 0
default CONFIG_ROM_SIZE = 256 * 1024
default CONFIG_HAVE_PIRQ_TABLE = 1
default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
default CONFIG_PIRQ_ROUTE = 1
default CONFIG_HAVE_FALLBACK_BOOT = 1
default CONFIG_HAVE_MP_TABLE = 0
default CONFIG_HAVE_HARD_RESET = 0
default CONFIG_UDELAY_TSC = 1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
default HAVE_OPTION_TABLE = 0
default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
default ROM_IMAGE_SIZE = 64 * 1024
default FALLBACK_SIZE = 128 * 1024
default STACK_SIZE = 8 * 1024
default HEAP_SIZE = 16 * 1024
default USE_OPTION_TABLE = 0
default _RAMBASE = 0x00004000
default CONFIG_HAVE_OPTION_TABLE = 0
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
default CONFIG_FALLBACK_SIZE = 128 * 1024
default CONFIG_STACK_SIZE = 8 * 1024
default CONFIG_HEAP_SIZE = 16 * 1024
default CONFIG_USE_OPTION_TABLE = 0
default CONFIG_RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
default CROSS_COMPILE = ""
default CC = "$(CROSS_COMPILE)gcc "
default HOSTCC = "gcc"
default CONFIG_CROSS_COMPILE = ""
default CC = "$(CONFIG_CROSS_COMPILE)gcc "
default CONFIG_HOSTCC = "gcc"
default CONFIG_CONSOLE_SERIAL8250 = 1
default TTYS0_BAUD = 115200
default TTYS0_BASE = 0x3f8
default TTYS0_LCS = 0x3 # 8n1
default DEFAULT_CONSOLE_LOGLEVEL = 9
default MAXIMUM_CONSOLE_LOGLEVEL = 9
default CONFIG_TTYS0_BAUD = 115200
default CONFIG_TTYS0_BASE = 0x3f8
default CONFIG_TTYS0_LCS = 0x3 # 8n1
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
#
# CBFS

2
src/mainboard/advantech/pcm-5820/auto.c
View File

@@ -36,7 +36,7 @@
static void main(unsigned long bist)
{
w83977f_enable_serial(SERIAL_DEV, TTYS0_BASE);
w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
report_bist_failure(bist);

2
src/mainboard/advantech/pcm-5820/irq_tables.c
View File

@@ -23,7 +23,7 @@
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE,
PIRQ_VERSION,
32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
(0x12 << 3) | 0x0, /* Interrupt router device */
0xc00, /* IRQs devoted exclusively to PCI usage */

14
src/mainboard/amd/db800/Config.lb
View File

@@ -1,5 +1,5 @@
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
##
@@ -14,14 +14,14 @@ arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
if CONFIG_HAVE_PIRQ_TABLE
object irq_tables.o
end
#compile cache_as_ram.c to auto.inc
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
@@ -37,7 +37,7 @@ ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -59,7 +59,7 @@ ldscript /arch/i386/lib/id.lds
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
# mainboardinit ./failover.inc
end

148
src/mainboard/amd/db800/Options.lb
View File

@@ -1,59 +1,59 @@
uses HAVE_MP_TABLE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_ROM_PAYLOAD
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ARCH
uses CONFIG_FALLBACK_SIZE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses PAYLOAD_SIZE
uses _ROMBASE
uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
uses CROSS_COMPILE
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_RAMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses CONFIG_VIDEO_MB
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses CONFIG_USE_DCACHE_RAM
uses CONFIG_DCACHE_RAM_BASE
uses CONFIG_DCACHE_RAM_SIZE
uses CONFIG_USE_PRINTK_IN_CAR
uses PIRQ_ROUTE
uses CONFIG_PIRQ_ROUTE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
default CONFIG_ROM_SIZE = 256*1024
###
### Build options
@@ -65,17 +65,17 @@ default CONFIG_PCI_ROM_RUN=0
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
default CONFIG_HAVE_FALLBACK_BOOT=1
##
## no MP table
##
default HAVE_MP_TABLE=0
default CONFIG_HAVE_MP_TABLE=0
##
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
default CONFIG_HAVE_HARD_RESET=0
## Delay timer options
##
@@ -85,58 +85,58 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=4
default PIRQ_ROUTE=1
default CONFIG_HAVE_PIRQ_TABLE=1
default CONFIG_IRQ_SLOT_COUNT=4
default CONFIG_PIRQ_ROUTE=1
#object irq_tables.o
##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE=0
default CONFIG_HAVE_OPTION_TABLE=0
###
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default CONFIG_ROM_IMAGE_SIZE = 65536
default CONFIG_FALLBACK_SIZE = 131072
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xc8000
default DCACHE_RAM_SIZE=0x08000
default CONFIG_USE_DCACHE_RAM=1
default CONFIG_DCACHE_RAM_BASE=0xc8000
default CONFIG_DCACHE_RAM_SIZE=0x08000
default CONFIG_USE_PRINTK_IN_CAR=1
##
## Use a small 8K stack
##
default STACK_SIZE=0x2000
default CONFIG_STACK_SIZE=0x2000
##
## Use a small 16K heap
##
default HEAP_SIZE=0x4000
default CONFIG_HEAP_SIZE=0x4000
##
## Only use the option table in a normal image
##
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
default CONFIG_USE_OPTION_TABLE = 0
default _RAMBASE = 0x00004000
default CONFIG_RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
##
## The default compiler
##
default CROSS_COMPILE=""
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
default CONFIG_CROSS_COMPILE=""
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
default CONFIG_HOSTCC="gcc"
##
## The Serial Console
@@ -146,21 +146,21 @@ default HOSTCC="gcc"
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
default TTYS0_BAUD=115200
#default TTYS0_BAUD=57600
#default TTYS0_BAUD=38400
#default TTYS0_BAUD=19200
#default TTYS0_BAUD=9600
#default TTYS0_BAUD=4800
#default TTYS0_BAUD=2400
#default TTYS0_BAUD=1200
default CONFIG_TTYS0_BAUD=115200
#default CONFIG_TTYS0_BAUD=57600
#default CONFIG_TTYS0_BAUD=38400
#default CONFIG_TTYS0_BAUD=19200
#default CONFIG_TTYS0_BAUD=9600
#default CONFIG_TTYS0_BAUD=4800
#default CONFIG_TTYS0_BAUD=2400
#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
default TTYS0_BASE=0x3f8
default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default TTYS0_LCS=0x3
default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
@@ -172,13 +172,13 @@ default TTYS0_LCS=0x3
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
## DEBUG 8 debug-level messages
## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
default DEFAULT_CONSOLE_LOGLEVEL=8
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
default MAXIMUM_CONSOLE_LOGLEVEL=8
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
#

2
src/mainboard/amd/db800/cache_as_ram_auto.c
View File

@@ -113,7 +113,7 @@ void cache_as_ram_main(void)
/* Note: must do this AFTER the early_setup! It is counting on some
* early MSR setup for CS5536.
*/
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
mb_gpio_init();
uart_init();
console_init();

4
src/mainboard/amd/db800/irq_tables.c
View File

@@ -44,7 +44,7 @@
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
0x00, /* IRQs devoted exclusively to PCI usage */
@@ -54,7 +54,7 @@ const struct irq_routing_table intel_irq_routing_table = {
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
/* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */

26
src/mainboard/amd/dbm690t/Config.lb
View File

@@ -19,8 +19,8 @@
##
##
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
arch i386 end
@@ -33,18 +33,18 @@ driver mainboard.o
#dir /drivers/si/3114
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE
if CONFIG_HAVE_MP_TABLE object mptable.o end
if CONFIG_HAVE_PIRQ_TABLE
object get_bus_conf.o
object irq_tables.o
end
if HAVE_ACPI_TABLES
if CONFIG_HAVE_ACPI_TABLES
object acpi_tables.o
object fadt.o
makerule dsdt.c
depends "$(MAINBOARD)/acpi/*.asl"
action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/acpi/dsdt.asl"
depends "$(CONFIG_MAINBOARD)/acpi/*.asl"
action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl"
action "mv dsdt.hex dsdt.c"
end
object ./dsdt.o
@@ -55,15 +55,15 @@ end
if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
end
else
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
@@ -87,7 +87,7 @@ ldscript /cpu/x86/16bit/entry16.lds
##
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -111,7 +111,7 @@ ldscript /arch/i386/lib/id.lds
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
end

206
src/mainboard/amd/dbm690t/Options.lb
View File

@@ -19,133 +19,133 @@
##
##
uses HAVE_MP_TABLE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses HAVE_ACPI_TABLES
uses HAVE_ACPI_RESUME
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_HAVE_ACPI_TABLES
uses CONFIG_HAVE_ACPI_RESUME
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_LOGICAL_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_FALLBACK_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses PAYLOAD_SIZE
uses _ROMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses STACK_SIZE
uses HEAP_SIZE
uses USE_OPTION_TABLE
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_LB_CKS_RANGE_START
uses CONFIG_LB_CKS_RANGE_END
uses CONFIG_LB_CKS_LOC
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_RAMBASE
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
uses HT_CHAIN_UNITID_BASE
uses HT_CHAIN_END_UNITID_BASE
uses SB_HT_CHAIN_ON_BUS0
uses CONFIG_HW_MEM_HOLE_SIZEK
uses CONFIG_HT_CHAIN_UNITID_BASE
uses CONFIG_HT_CHAIN_END_UNITID_BASE
uses CONFIG_SB_HT_CHAIN_ON_BUS0
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses DCACHE_RAM_GLOBAL_VAR_SIZE
uses CONFIG_USE_DCACHE_RAM
uses CONFIG_DCACHE_RAM_BASE
uses CONFIG_DCACHE_RAM_SIZE
uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
uses CONFIG_USE_INIT
uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses CONFIG_USE_PRINTK_IN_CAR
uses CONFIG_VIDEO_MB
uses CONFIG_GFXUMA
uses HAVE_MAINBOARD_RESOURCES
uses CONFIG_HAVE_MAINBOARD_RESOURCES
###
### Build options
###
##
## ROM_SIZE is the size of boot ROM that this board will use.
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
##
default ROM_SIZE=524288
default CONFIG_ROM_SIZE=524288
##
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
#default FALLBACK_SIZE=131072
#default CONFIG_FALLBACK_SIZE=131072
#256K
default FALLBACK_SIZE=0x40000
default CONFIG_FALLBACK_SIZE=0x40000
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
default CONFIG_HAVE_FALLBACK_BOOT=1
##
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default CONFIG_HAVE_HARD_RESET=1
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=11
default CONFIG_HAVE_PIRQ_TABLE=1
default CONFIG_IRQ_SLOT_COUNT=11
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
default HAVE_MP_TABLE=1
default CONFIG_HAVE_MP_TABLE=1
## ACPI tables will be included
default HAVE_ACPI_TABLES=1
default CONFIG_HAVE_ACPI_TABLES=1
##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE=0
default CONFIG_HAVE_OPTION_TABLE=0
##
## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default LB_CKS_LOC=123
default CONFIG_LB_CKS_RANGE_START=49
default CONFIG_LB_CKS_RANGE_END=122
default CONFIG_LB_CKS_LOC=123
##
## Build code for SMP support
@@ -158,7 +158,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=1
default CONFIG_LOGICAL_CPUS=1
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
#VGA Console
default CONFIG_CONSOLE_VGA=1
@@ -166,23 +166,23 @@ default CONFIG_PCI_ROM_RUN=1
# BTDC: Only one HT device on Herring.
#HT Unit ID offset
#default HT_CHAIN_UNITID_BASE=0x6
default HT_CHAIN_UNITID_BASE=0x0
#default CONFIG_HT_CHAIN_UNITID_BASE=0x6
default CONFIG_HT_CHAIN_UNITID_BASE=0x0
#real SB Unit ID
default HT_CHAIN_END_UNITID_BASE=0x1
default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
#make the SB HT chain on bus 0
default SB_HT_CHAIN_ON_BUS0=1
default CONFIG_SB_HT_CHAIN_ON_BUS0=1
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xc8000
default DCACHE_RAM_SIZE=0x8000
default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
default CONFIG_USE_DCACHE_RAM=1
default CONFIG_DCACHE_RAM_BASE=0xc8000
default CONFIG_DCACHE_RAM_SIZE=0x8000
default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
default CONFIG_USE_INIT=0
##
@@ -193,39 +193,39 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="dbm690t"
default MAINBOARD_VENDOR="amd"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
default CONFIG_MAINBOARD_PART_NUMBER="dbm690t"
default CONFIG_MAINBOARD_VENDOR="amd"
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
###
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default CONFIG_ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
default STACK_SIZE=0x2000
default CONFIG_STACK_SIZE=0x2000
##
## Use a small 16K heap
##
default HEAP_SIZE=0x4000
default CONFIG_HEAP_SIZE=0x4000
##
## Only use the option table in a normal image
##
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
default CONFIG_USE_OPTION_TABLE = 0
##
## coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default CONFIG_RAMBASE=0x00004000
##
## Load the payload from the ROM
@@ -239,8 +239,8 @@ default CONFIG_ROM_PAYLOAD = 1
##
## The default compiler
##
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
default CONFIG_HOSTCC="gcc"
##
## Disable the gdb stub by default
@@ -258,21 +258,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
default TTYS0_BAUD=115200
#default TTYS0_BAUD=57600
#default TTYS0_BAUD=38400
#default TTYS0_BAUD=19200
#default TTYS0_BAUD=9600
#default TTYS0_BAUD=4800
#default TTYS0_BAUD=2400
#default TTYS0_BAUD=1200
default CONFIG_TTYS0_BAUD=115200
#default CONFIG_TTYS0_BAUD=57600
#default CONFIG_TTYS0_BAUD=38400
#default CONFIG_TTYS0_BAUD=19200
#default CONFIG_TTYS0_BAUD=9600
#default CONFIG_TTYS0_BAUD=4800
#default CONFIG_TTYS0_BAUD=2400
#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
default TTYS0_BASE=0x3f8
default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default TTYS0_LCS=0x3
default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
@@ -284,21 +284,21 @@ default TTYS0_LCS=0x3
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
## DEBUG 8 debug-level messages
## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
default DEFAULT_CONSOLE_LOGLEVEL=8
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
default MAXIMUM_CONSOLE_LOGLEVEL=8
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
##
## Select power on after power fail setting
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
default CONFIG_VIDEO_MB=1
default CONFIG_GFXUMA=1
default HAVE_MAINBOARD_RESOURCES=1
default CONFIG_HAVE_MAINBOARD_RESOURCES=1
### End Options.lb
#

4
src/mainboard/amd/dbm690t/acpi_tables.c
View File

@@ -59,7 +59,7 @@ static void dump_mem(u32 start, u32 end)
extern u8 AmlCode[];
#if ACPI_SSDTX_NUM >= 1
#if CONFIG_ACPI_SSDTX_NUM >= 1
extern u8 AmlCode_ssdt2[];
extern u8 AmlCode_ssdt3[];
extern u8 AmlCode_ssdt4[];
@@ -201,7 +201,7 @@ unsigned long write_acpi_tables(unsigned long start)
current += ssdt->length;
acpi_add_table(rsdt, ssdt);
#if ACPI_SSDTX_NUM >= 1
#if CONFIG_ACPI_SSDTX_NUM >= 1
/* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */

10
src/mainboard/amd/dbm690t/cache_as_ram_auto.c
View File

@@ -100,7 +100,7 @@ static inline int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_fxx/fidvid.c"
#if USE_FALLBACK_IMAGE == 1
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "northbridge/amd/amdk8/early_ht.c"
@@ -139,14 +139,14 @@ normal_image:
fallback_image:
post_code(0x25);
}
#endif /* USE_FALLBACK_IMAGE == 1 */
#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if USE_FALLBACK_IMAGE == 1
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
@@ -159,7 +159,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0;
msr_t msr;
struct cpuid_result cpuid1;
struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
if (bist == 0) {
@@ -170,7 +170,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb600_lpc_init();
/* it8712f_enable_serial does not use its 1st parameter. */
it8712f_enable_serial(0, TTYS0_BASE);
it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
uart_init();
console_init();

2
src/mainboard/amd/dbm690t/mptable.c
View File

@@ -142,7 +142,7 @@ void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if HAVE_ACPI_TABLES == 0
#if CONFIG_HAVE_ACPI_TABLES == 0
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
#else

14
src/mainboard/amd/norwich/Config.lb
View File

@@ -1,5 +1,5 @@
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
##
@@ -14,7 +14,7 @@ arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
if CONFIG_HAVE_PIRQ_TABLE
object irq_tables.o
end
@@ -22,8 +22,8 @@ end
#compile cache_as_ram.c to auto.inc
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
@@ -39,7 +39,7 @@ ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -61,7 +61,7 @@ ldscript /arch/i386/lib/id.lds
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
# mainboardinit ./failover.inc
end

148
src/mainboard/amd/norwich/Options.lb
View File

@@ -1,59 +1,59 @@
uses HAVE_MP_TABLE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_ROM_PAYLOAD
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ARCH
uses CONFIG_FALLBACK_SIZE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses PAYLOAD_SIZE
uses _ROMBASE
uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
uses CROSS_COMPILE
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_RAMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses CONFIG_VIDEO_MB
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses CONFIG_USE_DCACHE_RAM
uses CONFIG_DCACHE_RAM_BASE
uses CONFIG_DCACHE_RAM_SIZE
uses CONFIG_USE_PRINTK_IN_CAR
uses PIRQ_ROUTE
uses CONFIG_PIRQ_ROUTE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
default CONFIG_ROM_SIZE = 256*1024
###
### Build options
@@ -65,17 +65,17 @@ default CONFIG_PCI_ROM_RUN=0
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
default CONFIG_HAVE_FALLBACK_BOOT=1
##
## no MP table
##
default HAVE_MP_TABLE=0
default CONFIG_HAVE_MP_TABLE=0
##
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
default CONFIG_HAVE_HARD_RESET=0
## Delay timer options
##
@@ -85,58 +85,58 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=6
default PIRQ_ROUTE=1
default CONFIG_HAVE_PIRQ_TABLE=1
default CONFIG_IRQ_SLOT_COUNT=6
default CONFIG_PIRQ_ROUTE=1
#object irq_tables.o
##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE=0
default CONFIG_HAVE_OPTION_TABLE=0
###
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default CONFIG_ROM_IMAGE_SIZE = 65536
default CONFIG_FALLBACK_SIZE = 131072
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xc8000
default DCACHE_RAM_SIZE=0x08000
default CONFIG_USE_DCACHE_RAM=1
default CONFIG_DCACHE_RAM_BASE=0xc8000
default CONFIG_DCACHE_RAM_SIZE=0x08000
default CONFIG_USE_PRINTK_IN_CAR=1
##
## Use a small 8K stack
##
default STACK_SIZE=0x2000
default CONFIG_STACK_SIZE=0x2000
##
## Use a small 16K heap
##
default HEAP_SIZE=0x4000
default CONFIG_HEAP_SIZE=0x4000
##
## Only use the option table in a normal image
##
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
default CONFIG_USE_OPTION_TABLE = 0
default _RAMBASE = 0x00004000
default CONFIG_RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
##
## The default compiler
##
default CROSS_COMPILE=""
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
default CONFIG_CROSS_COMPILE=""
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
default CONFIG_HOSTCC="gcc"
##
## The Serial Console
@@ -146,21 +146,21 @@ default HOSTCC="gcc"
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
default TTYS0_BAUD=115200
#default TTYS0_BAUD=57600
#default TTYS0_BAUD=38400
#default TTYS0_BAUD=19200
#default TTYS0_BAUD=9600
#default TTYS0_BAUD=4800
#default TTYS0_BAUD=2400
#default TTYS0_BAUD=1200
default CONFIG_TTYS0_BAUD=115200
#default CONFIG_TTYS0_BAUD=57600
#default CONFIG_TTYS0_BAUD=38400
#default CONFIG_TTYS0_BAUD=19200
#default CONFIG_TTYS0_BAUD=9600
#default CONFIG_TTYS0_BAUD=4800
#default CONFIG_TTYS0_BAUD=2400
#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
default TTYS0_BASE=0x3f8
default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default TTYS0_LCS=0x3
default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
@@ -172,13 +172,13 @@ default TTYS0_LCS=0x3
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
## DEBUG 8 debug-level messages
## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
default DEFAULT_CONSOLE_LOGLEVEL=8
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
default MAXIMUM_CONSOLE_LOGLEVEL=8
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
#

4
src/mainboard/amd/norwich/irq_tables.c
View File

@@ -44,7 +44,7 @@
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
0x00, /* IRQs devoted exclusively to PCI usage */
@@ -54,7 +54,7 @@ const struct irq_routing_table intel_irq_routing_table = {
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
/* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */

26
src/mainboard/amd/pistachio/Config.lb
View File

@@ -19,8 +19,8 @@
##
##
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
arch i386 end
@@ -33,18 +33,18 @@ driver mainboard.o
#dir /drivers/si/3114
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE
if CONFIG_HAVE_MP_TABLE object mptable.o end
if CONFIG_HAVE_PIRQ_TABLE
object get_bus_conf.o
object irq_tables.o
end
if HAVE_ACPI_TABLES
if CONFIG_HAVE_ACPI_TABLES
object acpi_tables.o
object fadt.o
makerule dsdt.c
depends "$(MAINBOARD)/acpi/*.asl"
action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/acpi/dsdt.asl"
depends "$(CONFIG_MAINBOARD)/acpi/*.asl"
action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl"
action "mv dsdt.hex dsdt.c"
end
object ./dsdt.o
@@ -55,15 +55,15 @@ end
if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
end
else
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
@@ -87,7 +87,7 @@ ldscript /cpu/x86/16bit/entry16.lds
##
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -111,7 +111,7 @@ ldscript /arch/i386/lib/id.lds
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
end

206
src/mainboard/amd/pistachio/Options.lb
View File

@@ -19,133 +19,133 @@
##
##
uses HAVE_MP_TABLE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses HAVE_ACPI_TABLES
uses HAVE_ACPI_RESUME
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_HAVE_ACPI_TABLES
uses CONFIG_HAVE_ACPI_RESUME
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_LOGICAL_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_FALLBACK_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses PAYLOAD_SIZE
uses _ROMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses STACK_SIZE
uses HEAP_SIZE
uses USE_OPTION_TABLE
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_LB_CKS_RANGE_START
uses CONFIG_LB_CKS_RANGE_END
uses CONFIG_LB_CKS_LOC
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_RAMBASE
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
uses HT_CHAIN_UNITID_BASE
uses HT_CHAIN_END_UNITID_BASE
uses SB_HT_CHAIN_ON_BUS0
uses CONFIG_HW_MEM_HOLE_SIZEK
uses CONFIG_HT_CHAIN_UNITID_BASE
uses CONFIG_HT_CHAIN_END_UNITID_BASE
uses CONFIG_SB_HT_CHAIN_ON_BUS0
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses DCACHE_RAM_GLOBAL_VAR_SIZE
uses CONFIG_USE_DCACHE_RAM
uses CONFIG_DCACHE_RAM_BASE
uses CONFIG_DCACHE_RAM_SIZE
uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
uses CONFIG_USE_INIT
uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses CONFIG_USE_PRINTK_IN_CAR
uses CONFIG_VIDEO_MB
uses CONFIG_GFXUMA
uses HAVE_MAINBOARD_RESOURCES
uses CONFIG_HAVE_MAINBOARD_RESOURCES
###
### Build options
###
##
## ROM_SIZE is the size of boot ROM that this board will use.
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
##
default ROM_SIZE=524288
default CONFIG_ROM_SIZE=524288
##
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
#default FALLBACK_SIZE=131072
#default CONFIG_FALLBACK_SIZE=131072
#256K
default FALLBACK_SIZE=0x40000
default CONFIG_FALLBACK_SIZE=0x40000
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
default CONFIG_HAVE_FALLBACK_BOOT=1
##
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default CONFIG_HAVE_HARD_RESET=1
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=11
default CONFIG_HAVE_PIRQ_TABLE=1
default CONFIG_IRQ_SLOT_COUNT=11
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
default HAVE_MP_TABLE=1
default CONFIG_HAVE_MP_TABLE=1
## ACPI tables will be included
default HAVE_ACPI_TABLES=1
default CONFIG_HAVE_ACPI_TABLES=1
##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE=0
default CONFIG_HAVE_OPTION_TABLE=0
##
## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default LB_CKS_LOC=123
default CONFIG_LB_CKS_RANGE_START=49
default CONFIG_LB_CKS_RANGE_END=122
default CONFIG_LB_CKS_LOC=123
##
## Build code for SMP support
@@ -158,7 +158,7 @@ default CONFIG_MAX_PHYSICAL_CPUS=1
default CONFIG_LOGICAL_CPUS=1
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
#VGA Console
default CONFIG_CONSOLE_VGA=1
@@ -166,23 +166,23 @@ default CONFIG_PCI_ROM_RUN=1
# BTDC: Only one HT device on Herring.
#HT Unit ID offset
#default HT_CHAIN_UNITID_BASE=0x6
default HT_CHAIN_UNITID_BASE=0x0
#default CONFIG_HT_CHAIN_UNITID_BASE=0x6
default CONFIG_HT_CHAIN_UNITID_BASE=0x0
#real SB Unit ID
default HT_CHAIN_END_UNITID_BASE=0x1
default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
#make the SB HT chain on bus 0
default SB_HT_CHAIN_ON_BUS0=1
default CONFIG_SB_HT_CHAIN_ON_BUS0=1
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xc8000
default DCACHE_RAM_SIZE=0x8000
default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
default CONFIG_USE_DCACHE_RAM=1
default CONFIG_DCACHE_RAM_BASE=0xc8000
default CONFIG_DCACHE_RAM_SIZE=0x8000
default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
default CONFIG_USE_INIT=0
##
@@ -193,39 +193,39 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="pistachio"
default MAINBOARD_VENDOR="amd"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
default CONFIG_MAINBOARD_PART_NUMBER="pistachio"
default CONFIG_MAINBOARD_VENDOR="amd"
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
###
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default CONFIG_ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
default STACK_SIZE=0x2000
default CONFIG_STACK_SIZE=0x2000
##
## Use a small 16K heap
##
default HEAP_SIZE=0x4000
default CONFIG_HEAP_SIZE=0x4000
##
## Only use the option table in a normal image
##
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
default CONFIG_USE_OPTION_TABLE = 0
##
## coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default CONFIG_RAMBASE=0x00004000
##
## Load the payload from the ROM
@@ -239,8 +239,8 @@ default CONFIG_ROM_PAYLOAD = 1
##
## The default compiler
##
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
default CONFIG_HOSTCC="gcc"
##
## Disable the gdb stub by default
@@ -258,21 +258,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
default TTYS0_BAUD=115200
#default TTYS0_BAUD=57600
#default TTYS0_BAUD=38400
#default TTYS0_BAUD=19200
#default TTYS0_BAUD=9600
#default TTYS0_BAUD=4800
#default TTYS0_BAUD=2400
#default TTYS0_BAUD=1200
default CONFIG_TTYS0_BAUD=115200
#default CONFIG_TTYS0_BAUD=57600
#default CONFIG_TTYS0_BAUD=38400
#default CONFIG_TTYS0_BAUD=19200
#default CONFIG_TTYS0_BAUD=9600
#default CONFIG_TTYS0_BAUD=4800
#default CONFIG_TTYS0_BAUD=2400
#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
default TTYS0_BASE=0x3f8
default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default TTYS0_LCS=0x3
default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
@@ -284,21 +284,21 @@ default TTYS0_LCS=0x3
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
## DEBUG 8 debug-level messages
## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
default DEFAULT_CONSOLE_LOGLEVEL=8
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
default MAXIMUM_CONSOLE_LOGLEVEL=8
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
##
## Select power on after power fail setting
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
default CONFIG_VIDEO_MB=1
default CONFIG_GFXUMA=1
default HAVE_MAINBOARD_RESOURCES=1
default CONFIG_HAVE_MAINBOARD_RESOURCES=1
### End Options.lb
#

4
src/mainboard/amd/pistachio/acpi_tables.c
View File

@@ -59,7 +59,7 @@ static void dump_mem(u32 start, u32 end)
extern u8 AmlCode[];
#if ACPI_SSDTX_NUM >= 1
#if CONFIG_ACPI_SSDTX_NUM >= 1
extern u8 AmlCode_ssdt2[];
extern u8 AmlCode_ssdt3[];
extern u8 AmlCode_ssdt4[];
@@ -201,7 +201,7 @@ unsigned long write_acpi_tables(unsigned long start)
current += ssdt->length;
acpi_add_table(rsdt, ssdt);
#if ACPI_SSDTX_NUM >= 1
#if CONFIG_ACPI_SSDTX_NUM >= 1
/* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */

10
src/mainboard/amd/pistachio/cache_as_ram_auto.c
View File

@@ -94,7 +94,7 @@ static inline int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_fxx/fidvid.c"
#if USE_FALLBACK_IMAGE == 1
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "northbridge/amd/amdk8/early_ht.c"
@@ -133,14 +133,14 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
fallback_image:
post_code(0x02);
}
#endif /* USE_FALLBACK_IMAGE == 1 */
#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if USE_FALLBACK_IMAGE == 1
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
@@ -154,8 +154,8 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
msr_t msr;
struct cpuid_result cpuid1;
struct sys_info *sysinfo =
(struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE -
DCACHE_RAM_GLOBAL_VAR_SIZE);
(struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE -
CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);

2
src/mainboard/amd/pistachio/mptable.c
View File

@@ -142,7 +142,7 @@ void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if HAVE_ACPI_TABLES == 0
#if CONFIG_HAVE_ACPI_TABLES == 0
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
#else

26
src/mainboard/amd/rumba/Config.lb
View File

@@ -1,5 +1,5 @@
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
##
@@ -14,29 +14,29 @@ arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE object irq_tables.o end
if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
##
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
##
@@ -50,7 +50,7 @@ ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -72,7 +72,7 @@ ldscript /arch/i386/lib/id.lds
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end

132
src/mainboard/amd/rumba/Options.lb
View File

@@ -1,50 +1,50 @@
uses HAVE_MP_TABLE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_ROM_PAYLOAD
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ARCH
uses CONFIG_FALLBACK_SIZE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses PAYLOAD_SIZE
uses _ROMBASE
uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
uses CROSS_COMPILE
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_RAMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
default CONFIG_ROM_SIZE = 256*1024
###
### Build options
@@ -53,17 +53,17 @@ default ROM_SIZE = 256*1024
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
default CONFIG_HAVE_FALLBACK_BOOT=1
##
## no MP table
##
default HAVE_MP_TABLE=0
default CONFIG_HAVE_MP_TABLE=0
##
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
default CONFIG_HAVE_HARD_RESET=0
## Delay timer options
##
@@ -73,49 +73,49 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=2
default CONFIG_HAVE_PIRQ_TABLE=1
default CONFIG_IRQ_SLOT_COUNT=2
#object irq_tables.o
##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE=0
default CONFIG_HAVE_OPTION_TABLE=0
###
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default CONFIG_ROM_IMAGE_SIZE = 65536
default CONFIG_FALLBACK_SIZE = 131072
##
## Use a small 8K stack
##
default STACK_SIZE=0x2000
default CONFIG_STACK_SIZE=0x2000
##
## Use a small 16K heap
##
default HEAP_SIZE=0x4000
default CONFIG_HEAP_SIZE=0x4000
##
## Only use the option table in a normal image
##
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
default CONFIG_USE_OPTION_TABLE = 0
default _RAMBASE = 0x00004000
default CONFIG_RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
##
## The default compiler
##
default CROSS_COMPILE=""
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
default CONFIG_CROSS_COMPILE=""
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
default CONFIG_HOSTCC="gcc"
##
## The Serial Console
@@ -125,21 +125,21 @@ default HOSTCC="gcc"
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
default TTYS0_BAUD=115200
#default TTYS0_BAUD=57600
#default TTYS0_BAUD=38400
#default TTYS0_BAUD=19200
#default TTYS0_BAUD=9600
#default TTYS0_BAUD=4800
#default TTYS0_BAUD=2400
#default TTYS0_BAUD=1200
default CONFIG_TTYS0_BAUD=115200
#default CONFIG_TTYS0_BAUD=57600
#default CONFIG_TTYS0_BAUD=38400
#default CONFIG_TTYS0_BAUD=19200
#default CONFIG_TTYS0_BAUD=9600
#default CONFIG_TTYS0_BAUD=4800
#default CONFIG_TTYS0_BAUD=2400
#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
default TTYS0_BASE=0x3f8
default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default TTYS0_LCS=0x3
default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
@@ -151,13 +151,13 @@ default TTYS0_LCS=0x3
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
## DEBUG 8 debug-level messages
## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
default DEFAULT_CONSOLE_LOGLEVEL=8
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
default MAXIMUM_CONSOLE_LOGLEVEL=8
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
#

2
src/mainboard/amd/rumba/auto.c
View File

@@ -127,7 +127,7 @@ static void main(unsigned long bist)
SystemPreInit();
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();

68
src/mainboard/amd/serengeti_cheetah/Config.lb
View File

@@ -1,5 +1,5 @@
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/failovercalculation.lb
arch i386 end
@@ -15,25 +15,25 @@ driver mainboard.o
#needed by irq_tables and mptable and acpi_tables
object get_bus_conf.o
if HAVE_MP_TABLE
if CONFIG_HAVE_MP_TABLE
object mptable.o
end
if HAVE_PIRQ_TABLE
if CONFIG_HAVE_PIRQ_TABLE
object irq_tables.o
end
#if HAVE_ACPI_TABLES
#if CONFIG_HAVE_ACPI_TABLES
# object acpi_tables.o
# object fadt.o
# if SB_HT_CHAIN_ON_BUS0
# if CONFIG_SB_HT_CHAIN_ON_BUS0
# object dsdt_bus0.o
# else
# object dsdt.o
# end
# object ssdt.o
# if ACPI_SSDTX_NUM
# if SB_HT_CHAIN_ON_BUS0
# if CONFIG_ACPI_SSDTX_NUM
# if CONFIG_SB_HT_CHAIN_ON_BUS0
# object ssdt2_bus0.o
# else
# object ssdt2.o
@@ -41,36 +41,36 @@ end
# end
#end
if HAVE_ACPI_TABLES
if CONFIG_HAVE_ACPI_TABLES
object acpi_tables.o
object fadt.o
makerule dsdt.c
depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
action "iasl -p $(CURDIR)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
action "iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
action "mv dsdt_lb.hex dsdt.c"
end
object ./dsdt.o
#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
if ACPI_SSDTX_NUM
if CONFIG_ACPI_SSDTX_NUM
makerule ssdt2.c
depends "$(MAINBOARD)/dx/pci2.asl"
action "iasl -p $(CURDIR)/pci2 -tc $(MAINBOARD)/dx/pci2.asl"
depends "$(CONFIG_MAINBOARD)/dx/pci2.asl"
action "iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl"
action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
action "mv pci2.hex ssdt2.c"
end
object ./ssdt2.o
makerule ssdt3.c
depends "$(MAINBOARD)/dx/pci3.asl"
action "iasl -p $(CURDIR)/pci3 -tc $(MAINBOARD)/dx/pci3.asl"
depends "$(CONFIG_MAINBOARD)/dx/pci3.asl"
action "iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl"
action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
action "mv pci3.hex ssdt3.c"
end
object ./ssdt3.o
makerule ssdt4.c
depends "$(MAINBOARD)/dx/pci4.asl"
action "iasl -p $(CURDIR)/pci4 -tc $(MAINBOARD)/dx/pci4.asl"
depends "$(CONFIG_MAINBOARD)/dx/pci4.asl"
action "iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl"
action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
action "mv pci4.hex ssdt4.c"
end
@@ -81,26 +81,26 @@ end
if CONFIG_USE_INIT
# compile cache_as_ram.c to auto.o
makerule ./cache_as_ram_auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
end
else
#compile cache_as_ram.c to auto.inc
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
if USE_FAILOVER_IMAGE
if CONFIG_USE_FAILOVER_IMAGE
else
if CONFIG_AP_CODE_IN_CAR
makerule ./apc_auto.o
depends "$(MAINBOARD)/apc_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
end
ldscript /arch/i386/init/ldscript_apc.lb
end
@@ -110,13 +110,13 @@ end
## Build our 16 bit and 32 bit coreboot entry code
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
if CONFIG_HAVE_FAILOVER_BOOT
if CONFIG_USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
else
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
@@ -134,8 +134,8 @@ mainboardinit cpu/x86/32bit/entry32.inc
##
## Build our reset vector (This is where coreboot is entered)
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
if CONFIG_HAVE_FAILOVER_BOOT
if CONFIG_USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -143,7 +143,7 @@ if HAVE_FAILOVER_BOOT
ldscript /cpu/x86/32bit/reset32.lds
end
else
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -168,12 +168,12 @@ ldscript /arch/i386/lib/id.lds
### Things are delicate and we test to see if we should
### failover to another image.
###
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
if CONFIG_HAVE_FAILOVER_BOOT
if CONFIG_USE_FAILOVER_IMAGE
ldscript /arch/i386/lib/failover_failover.lds
end
else
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
end
end

252
src/mainboard/amd/serengeti_cheetah/Options.lb
View File

@@ -1,85 +1,85 @@
uses HAVE_MP_TABLE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses HAVE_ACPI_TABLES
uses HAVE_ACPI_RESUME
uses ACPI_SSDTX_NUM
uses USE_FALLBACK_IMAGE
uses USE_FAILOVER_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_FAILOVER_BOOT
uses HAVE_HARD_RESET
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_HAVE_ACPI_TABLES
uses CONFIG_HAVE_ACPI_RESUME
uses CONFIG_ACPI_SSDTX_NUM
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_USE_FAILOVER_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_FAILOVER_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_LOGICAL_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
uses FAILOVER_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_FALLBACK_SIZE
uses CONFIG_FAILOVER_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses PAYLOAD_SIZE
uses _ROMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses STACK_SIZE
uses HEAP_SIZE
uses USE_OPTION_TABLE
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_LB_CKS_RANGE_START
uses CONFIG_LB_CKS_RANGE_END
uses CONFIG_LB_CKS_LOC
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_RAMBASE
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZE_AUTO_INC
uses K8_HT_FREQ_1G_SUPPORT
uses CONFIG_HW_MEM_HOLE_SIZEK
uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
uses CONFIG_K8_HT_FREQ_1G_SUPPORT
uses HT_CHAIN_UNITID_BASE
uses HT_CHAIN_END_UNITID_BASE
uses SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses CONFIG_HT_CHAIN_UNITID_BASE
uses CONFIG_HT_CHAIN_END_UNITID_BASE
uses CONFIG_SB_HT_CHAIN_ON_BUS0
uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses DCACHE_RAM_GLOBAL_VAR_SIZE
uses CONFIG_USE_DCACHE_RAM
uses CONFIG_DCACHE_RAM_BASE
uses CONFIG_DCACHE_RAM_SIZE
uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
uses CONFIG_USE_INIT
uses SERIAL_CPU_INIT
uses CONFIG_SERIAL_CPU_INIT
uses ENABLE_APIC_EXT_ID
uses APIC_ID_OFFSET
uses LIFT_BSP_APIC_ID
uses CONFIG_ENABLE_APIC_EXT_ID
uses CONFIG_APIC_ID_OFFSET
uses CONFIG_LIFT_BSP_APIC_ID
uses CONFIG_PCI_64BIT_PREF_MEM
@@ -87,9 +87,9 @@ uses CONFIG_LB_MEM_TOPK
uses CONFIG_AP_CODE_IN_CAR
uses MEM_TRAIN_SEQ
uses CONFIG_MEM_TRAIN_SEQ
uses WAIT_BEFORE_CPUS_INIT
uses CONFIG_WAIT_BEFORE_CPUS_INIT
uses CONFIG_USE_PRINTK_IN_CAR
@@ -98,20 +98,20 @@ uses CONFIG_USE_PRINTK_IN_CAR
###
##
## ROM_SIZE is the size of boot ROM that this board will use.
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
##
default ROM_SIZE=524288
default CONFIG_ROM_SIZE=524288
##
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
#default FALLBACK_SIZE=131072
#default FALLBACK_SIZE=0x40000
#default CONFIG_FALLBACK_SIZE=131072
#default CONFIG_FALLBACK_SIZE=0x40000
#FALLBACK: 256K-4K
default FALLBACK_SIZE=0x3f000
default CONFIG_FALLBACK_SIZE=0x3f000
#FAILOVER: 4K
default FAILOVER_SIZE=0x01000
default CONFIG_FAILOVER_SIZE=0x01000
#more 1M for pgtbl
default CONFIG_LB_MEM_TOPK=2048
@@ -119,42 +119,42 @@ default CONFIG_LB_MEM_TOPK=2048
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
default HAVE_FAILOVER_BOOT=1
default CONFIG_HAVE_FALLBACK_BOOT=1
default CONFIG_HAVE_FAILOVER_BOOT=1
##
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default CONFIG_HAVE_HARD_RESET=1
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=11
default CONFIG_HAVE_PIRQ_TABLE=1
default CONFIG_IRQ_SLOT_COUNT=11
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
default HAVE_MP_TABLE=1
default CONFIG_HAVE_MP_TABLE=1
## ACPI tables will be included
default HAVE_ACPI_TABLES=1
default CONFIG_HAVE_ACPI_TABLES=1
## extra SSDT num
default ACPI_SSDTX_NUM=1
default CONFIG_ACPI_SSDTX_NUM=1
##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE=1
default CONFIG_HAVE_OPTION_TABLE=1
##
## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default LB_CKS_LOC=123
default CONFIG_LB_CKS_RANGE_START=49
default CONFIG_LB_CKS_RANGE_END=122
default CONFIG_LB_CKS_LOC=123
##
## Build code for SMP support
@@ -165,41 +165,41 @@ default CONFIG_MAX_CPUS=8
default CONFIG_MAX_PHYSICAL_CPUS=4
default CONFIG_LOGICAL_CPUS=1
default SERIAL_CPU_INIT=0
default CONFIG_SERIAL_CPU_INIT=0
default ENABLE_APIC_EXT_ID=0
default APIC_ID_OFFSET=0x8
default LIFT_BSP_APIC_ID=1
default CONFIG_ENABLE_APIC_EXT_ID=0
default CONFIG_APIC_ID_OFFSET=0x8
default CONFIG_LIFT_BSP_APIC_ID=1
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000
#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
#1G
default HW_MEM_HOLE_SIZEK=0x100000
default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
#512M
#default HW_MEM_HOLE_SIZEK=0x80000
#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
#default HW_MEM_HOLE_SIZE_AUTO_INC=1
#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
#Opteron K8 1G HT Support
default K8_HT_FREQ_1G_SUPPORT=1
default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
#VGA Console
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
#HT Unit ID offset, default is 1, the typical one
default HT_CHAIN_UNITID_BASE=0xa
default CONFIG_HT_CHAIN_UNITID_BASE=0xa
#real SB Unit ID, default is 0x20, mean dont touch it at last
default HT_CHAIN_END_UNITID_BASE=0x6
default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
#make the SB HT chain on bus 0, default is not (0)
default SB_HT_CHAIN_ON_BUS0=2
default CONFIG_SB_HT_CHAIN_ON_BUS0=2
#only offset for SB chain?, default is yes(1)
#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
#allow capable device use that above 4G
#default CONFIG_PCI_64BIT_PREF_MEM=1
@@ -207,10 +207,10 @@ default SB_HT_CHAIN_ON_BUS0=2
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xc8000
default DCACHE_RAM_SIZE=0x08000
default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
default CONFIG_USE_DCACHE_RAM=1
default CONFIG_DCACHE_RAM_BASE=0xc8000
default CONFIG_DCACHE_RAM_SIZE=0x08000
default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
default CONFIG_USE_INIT=0
@@ -218,8 +218,8 @@ default CONFIG_USE_INIT=0
## for rev F training on AP purpose
##
default CONFIG_AP_CODE_IN_CAR=1
default MEM_TRAIN_SEQ=1
default WAIT_BEFORE_CPUS_INIT=1
default CONFIG_MEM_TRAIN_SEQ=1
default CONFIG_WAIT_BEFORE_CPUS_INIT=1
##
## Build code to setup a generic IOAPIC
@@ -229,37 +229,37 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="serengeti_cheetah"
default MAINBOARD_VENDOR="AMD"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
default CONFIG_MAINBOARD_PART_NUMBER="serengeti_cheetah"
default CONFIG_MAINBOARD_VENDOR="AMD"
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
###
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default CONFIG_ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
default STACK_SIZE=0x2000
default CONFIG_STACK_SIZE=0x2000
##
## Use a small 32K heap
##
default HEAP_SIZE=0x8000
default CONFIG_HEAP_SIZE=0x8000
##
## Only use the option table in a normal image
##
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
##
## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00100000
default CONFIG_RAMBASE=0x00100000
##
## Load the payload from the ROM
@@ -273,8 +273,8 @@ default CONFIG_ROM_PAYLOAD = 1
##
## The default compiler
##
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
default CONFIG_HOSTCC="gcc"
##
## Disable the gdb stub by default
@@ -290,21 +290,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
default TTYS0_BAUD=115200
#default TTYS0_BAUD=57600
#default TTYS0_BAUD=38400
#default TTYS0_BAUD=19200
#default TTYS0_BAUD=9600
#default TTYS0_BAUD=4800
#default TTYS0_BAUD=2400
#default TTYS0_BAUD=1200
default CONFIG_TTYS0_BAUD=115200
#default CONFIG_TTYS0_BAUD=57600
#default CONFIG_TTYS0_BAUD=38400
#default CONFIG_TTYS0_BAUD=19200
#default CONFIG_TTYS0_BAUD=9600
#default CONFIG_TTYS0_BAUD=4800
#default CONFIG_TTYS0_BAUD=2400
#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
default TTYS0_BASE=0x3f8
default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default TTYS0_LCS=0x3
default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
@@ -316,17 +316,17 @@ default TTYS0_LCS=0x3
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
## DEBUG 8 debug-level messages
## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
default DEFAULT_CONSOLE_LOGLEVEL=8
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
default MAXIMUM_CONSOLE_LOGLEVEL=8
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
##
## Select power on after power fail setting
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
### End Options.lb
#

4
src/mainboard/amd/serengeti_cheetah/acpi_tables.c
View File

@@ -39,7 +39,7 @@ static void dump_mem(unsigned start, unsigned end)
#endif
extern unsigned char AmlCode[];
#if ACPI_SSDTX_NUM >= 1
#if CONFIG_ACPI_SSDTX_NUM >= 1
extern unsigned char AmlCode_ssdt2[];
extern unsigned char AmlCode_ssdt3[];
extern unsigned char AmlCode_ssdt4[];
@@ -263,7 +263,7 @@ unsigned long write_acpi_tables(unsigned long start)
current += ssdt->length;
acpi_add_table(rsdt, ssdt);
#if ACPI_SSDTX_NUM >= 1
#if CONFIG_ACPI_SSDTX_NUM >= 1
//same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table

4
src/mainboard/amd/serengeti_cheetah/apc_auto.c
View File

@@ -74,8 +74,8 @@ static inline unsigned get_nodes(void)
void hardwaremain(int ret_addr)
{
struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
struct node_core_id id;

26
src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
View File

@@ -19,7 +19,7 @@
//if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1
#if K8_REV_F_SUPPORT == 1
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -45,7 +45,7 @@ static void post_code(uint8_t value) {
#endif
}
#endif
#if USE_FAILOVER_IMAGE==0
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include <cpu/amd/model_fxx_rev.h>
@@ -59,7 +59,7 @@ static void post_code(uint8_t value) {
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#if USE_FAILOVER_IMAGE==0
#if CONFIG_USE_FAILOVER_IMAGE==0
#include "cpu/x86/bist.h"
#include "lib/delay.c"
@@ -156,7 +156,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/fidvid.c"
#endif
#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -201,7 +201,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
);
fallback_image:
#if HAVE_FAILOVER_BOOT==1
#if CONFIG_HAVE_FAILOVER_BOOT==1
__asm__ volatile ("jmp __fallback_image"
: /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
@@ -215,21 +215,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if HAVE_FAILOVER_BOOT==1
#if USE_FAILOVER_IMAGE==1
#if CONFIG_HAVE_FAILOVER_BOOT==1
#if CONFIG_USE_FAILOVER_IMAGE==1
failover_process(bist, cpu_init_detectedx);
#else
real_main(bist, cpu_init_detectedx);
#endif
#else
#if USE_FALLBACK_IMAGE == 1
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
#endif
}
#if USE_FAILOVER_IMAGE==0
#if CONFIG_USE_FAILOVER_IMAGE==0
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
@@ -253,7 +253,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset; int i;
unsigned bsp_apicid = 0;
@@ -265,11 +265,11 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
@@ -284,7 +284,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
#if MEM_TRAIN_SEQ == 1
#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#endif
setup_coherent_ht_domain(); // routing table and start other core0

4
src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
View File

@@ -109,7 +109,7 @@ void get_bus_conf(void)
dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
if (dev) {
m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE
#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE
m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
m->bus_isa++;
// printk_debug("bus_isa=%d\n",bus_isa);
@@ -132,7 +132,7 @@ void get_bus_conf(void)
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1,0));
if (dev) {
m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
m->bus_isa++;
// printk_debug("bus_isa=%d\n",bus_isa);

64
src/mainboard/amd/serengeti_cheetah_fam10/Config.lb
View File

@@ -17,8 +17,8 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/failovercalculation.lb
arch i386 end
@@ -33,51 +33,51 @@ driver mainboard.o
#needed by irq_tables and mptable and acpi_tables
object get_bus_conf.o
if HAVE_MP_TABLE
if CONFIG_HAVE_MP_TABLE
object mptable.o
end
if HAVE_PIRQ_TABLE
if CONFIG_HAVE_PIRQ_TABLE
object irq_tables.o
end
if HAVE_ACPI_TABLES
if CONFIG_HAVE_ACPI_TABLES
object acpi_tables.o
object fadt.o
makerule dsdt.c
depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
action "iasl -p $(CURDIR)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
action "iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
action "mv dsdt_lb.hex dsdt.c"
end
object ./dsdt.o
#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
if ACPI_SSDTX_NUM
if CONFIG_ACPI_SSDTX_NUM
makerule ssdt2.c
depends "$(MAINBOARD)/dx/pci2.asl"
action "iasl -p $(CURDIR)/pci2 -tc $(MAINBOARD)/dx/pci2.asl"
depends "$(CONFIG_MAINBOARD)/dx/pci2.asl"
action "iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl"
action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
action "mv pci2.hex ssdt2.c"
end
object ./ssdt2.o
makerule ssdt3.c
depends "$(MAINBOARD)/dx/pci3.asl"
action "iasl -p $(CURDIR)/pci3 -tc $(MAINBOARD)/dx/pci3.asl"
depends "$(CONFIG_MAINBOARD)/dx/pci3.asl"
action "iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl"
action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
action "mv pci3.hex ssdt3.c"
end
object ./ssdt3.o
makerule ssdt4.c
depends "$(MAINBOARD)/dx/pci4.asl"
action "iasl -p $(CURDIR)/pci4 -tc $(MAINBOARD)/dx/pci4.asl"
depends "$(CONFIG_MAINBOARD)/dx/pci4.asl"
action "iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl"
action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
action "mv pci4.hex ssdt4.c"
end
object ./ssdt4.o
makerule ssdt5.c
depends "$(MAINBOARD)/dx/pci5.asl"
action "iasl -p $(CURDIR)/pci5 -tc $(MAINBOARD)/dx/pci5.asl"
depends "$(CONFIG_MAINBOARD)/dx/pci5.asl"
action "iasl -p $(CURDIR)/pci5 -tc $(CONFIG_MAINBOARD)/dx/pci5.asl"
action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
action "mv pci5.hex ssdt5.c"
end
@@ -88,27 +88,27 @@ end
if CONFIG_USE_INIT
# compile cache_as_ram.c to auto.o
makerule ./cache_as_ram_auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
end
else
#compile cache_as_ram.c to auto.inc
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
if USE_FAILOVER_IMAGE
if CONFIG_USE_FAILOVER_IMAGE
else
if CONFIG_AP_CODE_IN_CAR
makerule ./apc_auto.o
depends "$(MAINBOARD)/apc_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
end
ldscript /arch/i386/init/ldscript_apc.lb
end
@@ -118,13 +118,13 @@ end
## Build our 16 bit and 32 bit coreboot entry code
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
if CONFIG_HAVE_FAILOVER_BOOT
if CONFIG_USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
else
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
@@ -142,8 +142,8 @@ mainboardinit cpu/x86/32bit/entry32.inc
##
## Build our reset vector (This is where coreboot is entered)
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
if CONFIG_HAVE_FAILOVER_BOOT
if CONFIG_USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -151,7 +151,7 @@ if HAVE_FAILOVER_BOOT
ldscript /cpu/x86/32bit/reset32.lds
end
else
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -177,12 +177,12 @@ ldscript /arch/i386/lib/id.lds
### Things are delicate and we test to see if we should
### failover to another image.
###
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
if CONFIG_HAVE_FAILOVER_BOOT
if CONFIG_USE_FAILOVER_IMAGE
ldscript /arch/i386/lib/failover_failover.lds
end
else
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
end
end

258
src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
View File

@@ -17,126 +17,126 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
uses HAVE_MP_TABLE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses HAVE_ACPI_TABLES
uses HAVE_ACPI_RESUME
uses ACPI_SSDTX_NUM
uses USE_FALLBACK_IMAGE
uses USE_FAILOVER_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_FAILOVER_BOOT
uses HAVE_HARD_RESET
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_HAVE_ACPI_TABLES
uses CONFIG_HAVE_ACPI_RESUME
uses CONFIG_ACPI_SSDTX_NUM
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_USE_FAILOVER_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_FAILOVER_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_LOGICAL_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
uses FAILOVER_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_FALLBACK_SIZE
uses CONFIG_FAILOVER_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses PAYLOAD_SIZE
uses _ROMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses STACK_SIZE
uses HEAP_SIZE
uses USE_OPTION_TABLE
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_LB_CKS_RANGE_START
uses CONFIG_LB_CKS_RANGE_END
uses CONFIG_LB_CKS_LOC
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_RAMBASE
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZE_AUTO_INC
uses CONFIG_HW_MEM_HOLE_SIZEK
uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
uses HT_CHAIN_UNITID_BASE
uses HT_CHAIN_END_UNITID_BASE
uses SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses CONFIG_HT_CHAIN_UNITID_BASE
uses CONFIG_HT_CHAIN_END_UNITID_BASE
uses CONFIG_SB_HT_CHAIN_ON_BUS0
uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses DCACHE_RAM_GLOBAL_VAR_SIZE
uses CONFIG_USE_DCACHE_RAM
uses CONFIG_DCACHE_RAM_BASE
uses CONFIG_DCACHE_RAM_SIZE
uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
uses CONFIG_USE_INIT
uses SERIAL_CPU_INIT
uses CONFIG_SERIAL_CPU_INIT
uses ENABLE_APIC_EXT_ID
uses APIC_ID_OFFSET
uses LIFT_BSP_APIC_ID
uses CONFIG_ENABLE_APIC_EXT_ID
uses CONFIG_APIC_ID_OFFSET
uses CONFIG_LIFT_BSP_APIC_ID
uses CONFIG_PCI_64BIT_PREF_MEM
uses CONFIG_LB_MEM_TOPK
uses PCI_BUS_SEGN_BITS
uses CONFIG_PCI_BUS_SEGN_BITS
uses CONFIG_AP_CODE_IN_CAR
uses MEM_TRAIN_SEQ
uses CONFIG_MEM_TRAIN_SEQ
uses WAIT_BEFORE_CPUS_INIT
uses CONFIG_WAIT_BEFORE_CPUS_INIT
uses CONFIG_AMDMCT
uses CONFIG_USE_PRINTK_IN_CAR
uses CAR_FAM10
uses AMD_UCODE_PATCH_FILE
uses CONFIG_CAR_FAM10
uses CONFIG_AMD_UCODE_PATCH_FILE
###
### Build options
###
##
## ROM_SIZE is the size of boot ROM that this board will use.
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
##
default ROM_SIZE=1024*1024
default CONFIG_ROM_SIZE=1024*1024
##
##
#FALLBACK_SIZE_SIZE is the amount of the ROM the complete fallback image will use
##
#default FALLBACK_SIZE=131072
#default FALLBACK_SIZE=0x40000
#default CONFIG_FALLBACK_SIZE=131072
#default CONFIG_FALLBACK_SIZE=0x40000
#FALLBACK: 1024K - 8K
default FALLBACK_SIZE=0xFE000
default CONFIG_FALLBACK_SIZE=0xFE000
#FAILOVER: 8k
default FAILOVER_SIZE=0x02000
default CONFIG_FAILOVER_SIZE=0x02000
#more 1M for pgtbl
#if there is RAM on node0, we need to set it to 32M, otherwise can not access CAR on node0, and RAM on node1 at same time.
@@ -145,42 +145,42 @@ default CONFIG_LB_MEM_TOPK=16384
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
default HAVE_FAILOVER_BOOT=1
default CONFIG_HAVE_FALLBACK_BOOT=1
default CONFIG_HAVE_FAILOVER_BOOT=1
##
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default CONFIG_HAVE_HARD_RESET=1
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=11
default CONFIG_HAVE_PIRQ_TABLE=1
default CONFIG_IRQ_SLOT_COUNT=11
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
default HAVE_MP_TABLE=1
default CONFIG_HAVE_MP_TABLE=1
## ACPI tables will be included
default HAVE_ACPI_TABLES=1
default CONFIG_HAVE_ACPI_TABLES=1
## extra SSDT num
default ACPI_SSDTX_NUM=31
default CONFIG_ACPI_SSDTX_NUM=31
##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE=1
default CONFIG_HAVE_OPTION_TABLE=1
##
## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default LB_CKS_LOC=123
default CONFIG_LB_CKS_RANGE_START=49
default CONFIG_LB_CKS_RANGE_END=122
default CONFIG_LB_CKS_LOC=123
##
## Build code for SMP support
@@ -190,58 +190,58 @@ default CONFIG_MAX_PHYSICAL_CPUS=8
default CONFIG_MAX_CPUS=6 * CONFIG_MAX_PHYSICAL_CPUS
default CONFIG_LOGICAL_CPUS=1
#default SERIAL_CPU_INIT=0
#default CONFIG_SERIAL_CPU_INIT=0
default ENABLE_APIC_EXT_ID=1
default APIC_ID_OFFSET=0x00
default LIFT_BSP_APIC_ID=1
default CONFIG_ENABLE_APIC_EXT_ID=1
default CONFIG_APIC_ID_OFFSET=0x00
default CONFIG_LIFT_BSP_APIC_ID=1
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000
#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
#1G
default HW_MEM_HOLE_SIZEK=0x100000
default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
#512M
#default HW_MEM_HOLE_SIZEK=0x80000
#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
#default HW_MEM_HOLE_SIZE_AUTO_INC=1
#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
#VGA Console
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
#HT Unit ID offset, default is 1, the typical one
default HT_CHAIN_UNITID_BASE=0xa
default CONFIG_HT_CHAIN_UNITID_BASE=0xa
#real SB Unit ID, default is 0x20, mean dont touch it at last
default HT_CHAIN_END_UNITID_BASE=0x6
default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
#make the SB HT chain on bus 0, default is not (0)
default SB_HT_CHAIN_ON_BUS0=2
default CONFIG_SB_HT_CHAIN_ON_BUS0=2
#only offset for SB chain?, default is yes(1)
#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
#allow capable device use that above 4G
#default CONFIG_PCI_64BIT_PREF_MEM=1
#it only be 0, 1, 2, 3, 4 and default is 0
#default PCI_BUS_SEGN_BITS=3
#default CONFIG_PCI_BUS_SEGN_BITS=3
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xc4000
default DCACHE_RAM_SIZE=0x0c000
#default DCACHE_RAM_GLOBAL_VAR_SIZE=0x08000
default DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000
default CONFIG_USE_DCACHE_RAM=1
default CONFIG_DCACHE_RAM_BASE=0xc4000
default CONFIG_DCACHE_RAM_SIZE=0x0c000
#default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x08000
default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000
default CONFIG_USE_INIT=0
#default CONFIG_AP_CODE_IN_CAR=1
default MEM_TRAIN_SEQ=2
default WAIT_BEFORE_CPUS_INIT=0
default CONFIG_MEM_TRAIN_SEQ=2
default CONFIG_WAIT_BEFORE_CPUS_INIT=0
default CONFIG_AMDMCT = 1
@@ -253,10 +253,10 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="Cheetah Fam10"
default MAINBOARD_VENDOR="AMD"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
default CONFIG_MAINBOARD_PART_NUMBER="Cheetah Fam10"
default CONFIG_MAINBOARD_VENDOR="AMD"
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
##
## Set microcode patch file name
@@ -266,34 +266,34 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
## Barcelona rev DR-B2, B3: "mc_patch_01000095.h"
## Shanghai rev DA-C2: "mc_patch_0100009f.h"
##
default AMD_UCODE_PATCH_FILE="mc_patch_01000095.h"
default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_01000095.h"
###
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default CONFIG_ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
default STACK_SIZE=0x2000
default CONFIG_STACK_SIZE=0x2000
##
## Use a small 768k heap
##
default HEAP_SIZE=0xc0000
default CONFIG_HEAP_SIZE=0xc0000
##
## Only use the option table in a normal image
##
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
##
## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00200000
default CONFIG_RAMBASE=0x00200000
##
## Load the payload from the ROM
@@ -307,8 +307,8 @@ default CONFIG_ROM_PAYLOAD = 1
##
## The default compiler
##
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
default CONFIG_HOSTCC="gcc"
##
## Disable the gdb stub by default
@@ -325,21 +325,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
default TTYS0_BAUD=115200
#default TTYS0_BAUD=57600
#default TTYS0_BAUD=38400
#default TTYS0_BAUD=19200
#default TTYS0_BAUD=9600
#default TTYS0_BAUD=4800
#default TTYS0_BAUD=2400
#default TTYS0_BAUD=1200
default CONFIG_TTYS0_BAUD=115200
#default CONFIG_TTYS0_BAUD=57600
#default CONFIG_TTYS0_BAUD=38400
#default CONFIG_TTYS0_BAUD=19200
#default CONFIG_TTYS0_BAUD=9600
#default CONFIG_TTYS0_BAUD=4800
#default CONFIG_TTYS0_BAUD=2400
#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
default TTYS0_BASE=0x3f8
default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default TTYS0_LCS=0x3
default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
@@ -351,17 +351,17 @@ default TTYS0_LCS=0x3
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
## DEBUG 8 debug-level messages
## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
default DEFAULT_CONSOLE_LOGLEVEL=8
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
default MAXIMUM_CONSOLE_LOGLEVEL=8
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
##
## Select power on after power fail setting
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
### End Options.lb
#

4
src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
View File

@@ -49,7 +49,7 @@ static void dump_mem(u32 start, u32 end)
extern u8 AmlCode[];
extern u8 AmlCode_ssdt[];
#if ACPI_SSDTX_NUM >= 1
#if CONFIG_ACPI_SSDTX_NUM >= 1
extern u8 AmlCode_ssdt2[];
extern u8 AmlCode_ssdt3[];
extern u8 AmlCode_ssdt4[];
@@ -276,7 +276,7 @@ unsigned long write_acpi_tables(unsigned long start)
printk_debug("ACPI: * SSDT for PState at %lx\n", current);
current = acpi_add_ssdt_pstates(rsdt, current);
#if ACPI_SSDTX_NUM >= 1
#if CONFIG_ACPI_SSDTX_NUM >= 1
/* same htio, but different possition? We may have to copy,
change HCIN, and recalculate the checknum and add_table */

8
src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c
View File

@@ -50,9 +50,9 @@
#include "lib/delay.c"
#if NODE_NUMS == 64
#define NODE_PCI(x,fn) ((x<32)?PCI_DEV(CBB,CDB+x,fn):PCI_DEV(CBB-1, CDB+x-32, fn))
#define NODE_PCI(x,fn) ((x<32)?PCI_DEV(CONFIG_CBB,CONFIG_CDB+x,fn):PCI_DEV(CONFIG_CBB-1, CONFIG_CDB+x-32, fn))
#else
#define NODE_PCI(x, fn) PCI_DEV(CBB,CDB+x,fn)
#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,CONFIG_CDB+x,fn)
#endif
//#include "cpu/x86/lapic/boot_cpu.c"
@@ -73,8 +73,8 @@
void hardwaremain(int ret_addr)
{
struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
struct node_core_id id;

30
src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c
View File

@@ -60,7 +60,7 @@ static void post_code(u8 value) {
outb(value, 0x80);
}
#if (USE_FAILOVER_IMAGE == 0)
#if (CONFIG_USE_FAILOVER_IMAGE == 0)
#include "arch/i386/lib/console.c"
#include "pc80/serial.c"
#include "ram/ramtest.c"
@@ -80,7 +80,7 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf,
#include "cpu/x86/bist.h"
#if (USE_FAILOVER_IMAGE == 0)
#if (CONFIG_USE_FAILOVER_IMAGE == 0)
#include "northbridge/amd/amdfam10/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
@@ -142,10 +142,10 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "cpu/amd/model_10xxx/fidvid.c"
#endif /* (USE_FAILOVER_IMAGE == 0) */
#endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */
#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
@@ -190,7 +190,7 @@ normal_image:
);
fallback_image:
#if HAVE_FAILOVER_BOOT==1
#if CONFIG_HAVE_FAILOVER_BOOT==1
__asm__ volatile ("jmp __fallback_image"
: /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
@@ -198,22 +198,22 @@ fallback_image:
#endif
;
}
#endif /* ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) */
#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) */
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
//FIXME: I think that there is a hole here with the real_main() logic realmain is inside a USE_FAILOVER_IMAGE=0.
#if HAVE_FAILOVER_BOOT==1
#if USE_FAILOVER_IMAGE==1
//FIXME: I think that there is a hole here with the real_main() logic realmain is inside a CONFIG_USE_FAILOVER_IMAGE=0.
#if CONFIG_HAVE_FAILOVER_BOOT==1
#if CONFIG_USE_FAILOVER_IMAGE==1
failover_process(bist, cpu_init_detectedx);
#else
real_main(bist, cpu_init_detectedx);
#endif
#else
#if USE_FALLBACK_IMAGE == 1
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
@@ -221,7 +221,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
#if (USE_FAILOVER_IMAGE==0)
#if (CONFIG_USE_FAILOVER_IMAGE==0)
#include "spd_addr.h"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
@@ -229,7 +229,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
u32 bsp_apicid = 0;
u32 val;
msr_t msr;
@@ -243,12 +243,12 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
printk_debug("\n");
// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
@@ -380,4 +380,4 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
#endif /* USE_FAILOVER_IMAGE==0 */
#endif /* CONFIG_USE_FAILOVER_IMAGE==0 */

6
src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c
View File

@@ -116,11 +116,11 @@ unsigned long write_pirq_routing_table(unsigned long addr)
}
#if CBB
write_pirq_info(pirq_info, CBB, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
#if CONFIG_CBB
write_pirq_info(pirq_info, CONFIG_CBB, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
if(sysconf.nodes>32) {
write_pirq_info(pirq_info, CBB-1, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
write_pirq_info(pirq_info, CONFIG_CBB-1, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
}
#endif

88
src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c
View File

@@ -49,14 +49,14 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40 bit address
* that define the end of the DRAM region.
*/
// PCI_ADDR(CBB, CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR_FAM10
PCI_ADDR(CBB, CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
PCI_ADDR(CBB, CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
PCI_ADDR(CBB, CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
PCI_ADDR(CBB, CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
PCI_ADDR(CBB, CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
PCI_ADDR(CBB, CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
PCI_ADDR(CBB, CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
/* DRAM Base i Registers
* F1:0x40 i = 0
* F1:0x48 i = 1
@@ -87,14 +87,14 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40-bit address
* that define the start of the DRAM region.
*/
// PCI_ADDR(CBB, CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CAR_FAM10
PCI_ADDR(CBB, CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
PCI_ADDR(CBB, CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
PCI_ADDR(CBB, CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
PCI_ADDR(CBB, CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
PCI_ADDR(CBB, CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
PCI_ADDR(CBB, CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
PCI_ADDR(CBB, CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers
* F1:0x84 i = 0
@@ -128,14 +128,14 @@ static void setup_mb_resource_map(void)
* This field defines the upp adddress bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CBB, CDB, 1, 0x84), 0x00000048, 0x00000000,
PCI_ADDR(CBB, CDB, 1, 0x8C), 0x00000048, 0x00000000,
PCI_ADDR(CBB, CDB, 1, 0x94), 0x00000048, 0x00000000,
PCI_ADDR(CBB, CDB, 1, 0x9C), 0x00000048, 0x00000000,
PCI_ADDR(CBB, CDB, 1, 0xA4), 0x00000048, 0x00000000,
PCI_ADDR(CBB, CDB, 1, 0xAC), 0x00000048, 0x00000000,
PCI_ADDR(CBB, CDB, 1, 0xB4), 0x00000048, 0x00000000,
// PCI_ADDR(CBB, CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
@@ -163,14 +163,14 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40bit address
* that defines the start of memory-mapped I/O region i
*/
PCI_ADDR(CBB, CDB, 1, 0x80), 0x000000f0, 0x00000000,
PCI_ADDR(CBB, CDB, 1, 0x88), 0x000000f0, 0x00000000,
PCI_ADDR(CBB, CDB, 1, 0x90), 0x000000f0, 0x00000000,
PCI_ADDR(CBB, CDB, 1, 0x98), 0x000000f0, 0x00000000,
PCI_ADDR(CBB, CDB, 1, 0xA0), 0x000000f0, 0x00000000,
PCI_ADDR(CBB, CDB, 1, 0xA8), 0x000000f0, 0x00000000,
PCI_ADDR(CBB, CDB, 1, 0xB0), 0x000000f0, 0x00000000,
// PCI_ADDR(CBB, CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers
* F1:0xC4 i = 0
@@ -197,10 +197,10 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
// PCI_ADDR(CBB, CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
PCI_ADDR(CBB, CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(CBB, CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(CBB, CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers
* F1:0xC0 i = 0
@@ -227,10 +227,10 @@ static void setup_mb_resource_map(void)
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
// PCI_ADDR(CBB, CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
PCI_ADDR(CBB, CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(CBB, CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(CBB, CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers
* F1:0xE0 i = 0
@@ -268,10 +268,10 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration regin i
*/
// PCI_ADDR(CBB, CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
PCI_ADDR(CBB, CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CBB, CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CBB, CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
};
int max;

22
src/mainboard/arima/hdama/Config.lb
View File

@@ -1,5 +1,5 @@
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 128 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 128 * 1024
include /config/nofailovercalculation.lb
##
@@ -13,21 +13,21 @@ arch i386 end
##
driver mainboard.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
if CONFIG_HAVE_MP_TABLE object mptable.o end
if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
if CONFIG_USE_INIT
makerule ./auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
end
else
makerule ./auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
@@ -37,7 +37,7 @@ end
##
## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
@@ -55,7 +55,7 @@ mainboardinit cpu/x86/32bit/entry32.inc
##
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -79,7 +79,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
end

168
src/mainboard/arima/hdama/Options.lb
View File

@@ -1,61 +1,61 @@
uses HAVE_MP_TABLE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_FALLBACK_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses PAYLOAD_SIZE
uses _ROMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses STACK_SIZE
uses HEAP_SIZE
uses USE_OPTION_TABLE
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_LB_CKS_RANGE_START
uses CONFIG_LB_CKS_RANGE_END
uses CONFIG_LB_CKS_LOC
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_RAMBASE
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses CONFIG_LOGICAL_CPUS
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses CONFIG_USE_DCACHE_RAM
uses CONFIG_DCACHE_RAM_BASE
uses CONFIG_DCACHE_RAM_SIZE
uses CONFIG_USE_INIT
uses CONFIG_USE_PRINTK_IN_CAR
@@ -69,48 +69,48 @@ uses CONFIG_USE_PRINTK_IN_CAR
default CONFIG_LOGICAL_CPUS=1
##
## ROM_SIZE is the size of boot ROM that this board will use.
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
##
default ROM_SIZE=524288
default CONFIG_ROM_SIZE=524288
##
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
default FALLBACK_SIZE=0x40000
default CONFIG_FALLBACK_SIZE=0x40000
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
default CONFIG_HAVE_FALLBACK_BOOT=1
##
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default CONFIG_HAVE_HARD_RESET=1
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=9
default CONFIG_HAVE_PIRQ_TABLE=1
default CONFIG_IRQ_SLOT_COUNT=9
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
default HAVE_MP_TABLE=1
default CONFIG_HAVE_MP_TABLE=1
##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE=1
default CONFIG_HAVE_OPTION_TABLE=1
##
## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default LB_CKS_LOC=123
default CONFIG_LB_CKS_RANGE_START=49
default CONFIG_LB_CKS_RANGE_END=122
default CONFIG_LB_CKS_LOC=123
##
## Build code for SMP support
@@ -128,9 +128,9 @@ default CONFIG_IOAPIC=1
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_DCACHE_RAM=1
default CONFIG_DCACHE_RAM_BASE=0xcf000
default CONFIG_DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=0
#VGA
@@ -140,38 +140,38 @@ default CONFIG_PCI_ROM_RUN=1
##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="HDAMA"
default MAINBOARD_VENDOR="ARIMA"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
default CONFIG_MAINBOARD_PART_NUMBER="HDAMA"
default CONFIG_MAINBOARD_VENDOR="ARIMA"
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
###
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default CONFIG_ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
default STACK_SIZE=0x2000
default CONFIG_STACK_SIZE=0x2000
##
## Use a small 16K heap
##
default HEAP_SIZE=0x4000
default CONFIG_HEAP_SIZE=0x4000
##
## Only use the option table in a normal image
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
##
## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default CONFIG_RAMBASE=0x00004000
##
## Load the payload from the ROM
@@ -185,8 +185,8 @@ default CONFIG_ROM_PAYLOAD = 1
##
## The default compiler
##
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
default CONFIG_HOSTCC="gcc"
##
## Disable the gdb stub by default
@@ -203,21 +203,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
default TTYS0_BAUD=115200
#default TTYS0_BAUD=57600
#default TTYS0_BAUD=38400
#default TTYS0_BAUD=19200
#default TTYS0_BAUD=9600
#default TTYS0_BAUD=4800
#default TTYS0_BAUD=2400
#default TTYS0_BAUD=1200
default CONFIG_TTYS0_BAUD=115200
#default CONFIG_TTYS0_BAUD=57600
#default CONFIG_TTYS0_BAUD=38400
#default CONFIG_TTYS0_BAUD=19200
#default CONFIG_TTYS0_BAUD=9600
#default CONFIG_TTYS0_BAUD=4800
#default CONFIG_TTYS0_BAUD=2400
#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
default TTYS0_BASE=0x3f8
default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default TTYS0_LCS=0x3
default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
@@ -229,17 +229,17 @@ default TTYS0_LCS=0x3
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
## DEBUG 8 debug-level messages
## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
default DEFAULT_CONSOLE_LOGLEVEL=8
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
default MAXIMUM_CONSOLE_LOGLEVEL=8
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
##
## Select power on after power fail setting
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
### End Options.lb
#

6
src/mainboard/arima/hdama/cache_as_ram_auto.c
View File

@@ -96,7 +96,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#if USE_FALLBACK_IMAGE == 1
#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -148,7 +148,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if USE_FALLBACK_IMAGE == 1
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
@@ -186,7 +186,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
init_cpus(cpu_init_detectedx);
}
pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();

2
src/mainboard/arima/hdama/irq_tables.c
View File

@@ -18,7 +18,7 @@
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT table entries */
32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT table entries */
IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */
IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */
0x00, /* IRQs devoted exclusively to PCI usage */

14
src/mainboard/artecgroup/dbe61/Config.lb
View File

@@ -1,5 +1,5 @@
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
##
@@ -14,13 +14,13 @@ arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE object irq_tables.o end
if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
#compile cache_as_ram.c to auto.inc
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
@@ -36,7 +36,7 @@ ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -58,7 +58,7 @@ ldscript /arch/i386/lib/id.lds
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
# mainboardinit ./failover.inc
end

148
src/mainboard/artecgroup/dbe61/Options.lb
View File

@@ -1,59 +1,59 @@
uses HAVE_MP_TABLE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_ROM_PAYLOAD
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ARCH
uses CONFIG_FALLBACK_SIZE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses PAYLOAD_SIZE
uses _ROMBASE
uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
uses CROSS_COMPILE
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_RAMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses CONFIG_VIDEO_MB
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses CONFIG_USE_DCACHE_RAM
uses CONFIG_DCACHE_RAM_BASE
uses CONFIG_DCACHE_RAM_SIZE
uses CONFIG_USE_PRINTK_IN_CAR
uses PIRQ_ROUTE
uses CONFIG_PIRQ_ROUTE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
default CONFIG_ROM_SIZE = 256*1024
###
### Build options
@@ -65,17 +65,17 @@ default CONFIG_VIDEO_MB=8
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
default CONFIG_HAVE_FALLBACK_BOOT=1
##
## no MP table
##
default HAVE_MP_TABLE=0
default CONFIG_HAVE_MP_TABLE=0
##
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
default CONFIG_HAVE_HARD_RESET=0
## Delay timer options
##
@@ -85,58 +85,58 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=3
default PIRQ_ROUTE=1
default CONFIG_HAVE_PIRQ_TABLE=1
default CONFIG_IRQ_SLOT_COUNT=3
default CONFIG_PIRQ_ROUTE=1
#object irq_tables.o
##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE=0
default CONFIG_HAVE_OPTION_TABLE=0
###
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default CONFIG_ROM_IMAGE_SIZE = 65536
default CONFIG_FALLBACK_SIZE = 131072
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xc8000
default DCACHE_RAM_SIZE=0x08000
default CONFIG_USE_DCACHE_RAM=1
default CONFIG_DCACHE_RAM_BASE=0xc8000
default CONFIG_DCACHE_RAM_SIZE=0x08000
default CONFIG_USE_PRINTK_IN_CAR=1
##
## Use a small 8K stack
##
default STACK_SIZE=0x2000
default CONFIG_STACK_SIZE=0x2000
##
## Use a small 16K heap
##
default HEAP_SIZE=0x4000
default CONFIG_HEAP_SIZE=0x4000
##
## Only use the option table in a normal image
##
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
default CONFIG_USE_OPTION_TABLE = 0
default _RAMBASE = 0x00004000
default CONFIG_RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
##
## The default compiler
##
default CROSS_COMPILE=""
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
default CONFIG_CROSS_COMPILE=""
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
default CONFIG_HOSTCC="gcc"
##
## The Serial Console
@@ -146,21 +146,21 @@ default HOSTCC="gcc"
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
default TTYS0_BAUD=115200
#default TTYS0_BAUD=57600
#default TTYS0_BAUD=38400
#default TTYS0_BAUD=19200
#default TTYS0_BAUD=9600
#default TTYS0_BAUD=4800
#default TTYS0_BAUD=2400
#default TTYS0_BAUD=1200
default CONFIG_TTYS0_BAUD=115200
#default CONFIG_TTYS0_BAUD=57600
#default CONFIG_TTYS0_BAUD=38400
#default CONFIG_TTYS0_BAUD=19200
#default CONFIG_TTYS0_BAUD=9600
#default CONFIG_TTYS0_BAUD=4800
#default CONFIG_TTYS0_BAUD=2400
#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
default TTYS0_BASE=0x3f8
default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default TTYS0_LCS=0x3
default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
@@ -172,13 +172,13 @@ default TTYS0_LCS=0x3
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
## DEBUG 8 debug-level messages
## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
default DEFAULT_CONSOLE_LOGLEVEL=8
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
default MAXIMUM_CONSOLE_LOGLEVEL=8
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
#

4
src/mainboard/artecgroup/dbe61/irq_tables.c
View File

@@ -44,7 +44,7 @@
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
0x00, /* IRQs devoted exclusively to PCI usage */
@@ -54,7 +54,7 @@ const struct irq_routing_table intel_irq_routing_table = {
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
/* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */

30
src/mainboard/asi/mb_5blgp/Config.lb
View File

@@ -18,38 +18,38 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
if CONFIG_HAVE_PIRQ_TABLE
object irq_tables.o
end
makerule ./failover.E
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./auto.E
# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(MAINBOARD)/auto.c ../romcc"
action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(MAINBOARD)/auto.c ../romcc"
action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -59,7 +59,7 @@ end
mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end

116
src/mainboard/asi/mb_5blgp/Options.lb
View File

@@ -18,45 +18,45 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
uses HAVE_MP_TABLE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_ROM_PAYLOAD
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ARCH
uses CONFIG_FALLBACK_SIZE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD_START
uses PAYLOAD_SIZE
uses _ROMBASE
uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses CROSS_COMPILE
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_RAMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
@@ -64,7 +64,7 @@ uses CONFIG_VIDEO_MB
uses CONFIG_SPLASH_GRAPHIC
uses CONFIG_GX1_VIDEO
uses CONFIG_GX1_VIDEOMODE
uses PIRQ_ROUTE
uses CONFIG_PIRQ_ROUTE
## Enable VGA with a splash screen (only 640x480 to run on most monitors).
## We want to support up to 1024x768@16 so we need 2MiB video memory.
@@ -74,34 +74,34 @@ default CONFIG_GX1_VIDEOMODE = 0
default CONFIG_SPLASH_GRAPHIC = 1
default CONFIG_VIDEO_MB = 2
default ROM_SIZE = 256 * 1024
default HAVE_PIRQ_TABLE = 1
default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
default PIRQ_ROUTE = 1
default HAVE_FALLBACK_BOOT = 1
default HAVE_MP_TABLE = 0
default HAVE_HARD_RESET = 0
default CONFIG_ROM_SIZE = 256 * 1024
default CONFIG_HAVE_PIRQ_TABLE = 1
default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
default CONFIG_PIRQ_ROUTE = 1
default CONFIG_HAVE_FALLBACK_BOOT = 1
default CONFIG_HAVE_MP_TABLE = 0
default CONFIG_HAVE_HARD_RESET = 0
default CONFIG_UDELAY_TSC = 1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
default HAVE_OPTION_TABLE = 0
default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
default ROM_IMAGE_SIZE = 64 * 1024
default FALLBACK_SIZE = 128 * 1024
default STACK_SIZE = 8 * 1024
default HEAP_SIZE = 16 * 1024
default USE_OPTION_TABLE = 0
default _RAMBASE = 0x00004000
default CONFIG_HAVE_OPTION_TABLE = 0
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
default CONFIG_FALLBACK_SIZE = 128 * 1024
default CONFIG_STACK_SIZE = 8 * 1024
default CONFIG_HEAP_SIZE = 16 * 1024
default CONFIG_USE_OPTION_TABLE = 0
default CONFIG_RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
default CROSS_COMPILE = ""
default CC = "$(CROSS_COMPILE)gcc "
default HOSTCC = "gcc"
default CONFIG_CROSS_COMPILE = ""
default CC = "$(CONFIG_CROSS_COMPILE)gcc "
default CONFIG_HOSTCC = "gcc"
default CONFIG_CONSOLE_SERIAL8250 = 1
default TTYS0_BAUD = 115200
default TTYS0_BASE = 0x3f8
default TTYS0_LCS = 0x3 # 8n1
default DEFAULT_CONSOLE_LOGLEVEL = 9
default MAXIMUM_CONSOLE_LOGLEVEL = 9
default CONFIG_TTYS0_BAUD = 115200
default CONFIG_TTYS0_BASE = 0x3f8
default CONFIG_TTYS0_LCS = 0x3 # 8n1
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
#
# CBFS

2
src/mainboard/asi/mb_5blgp/auto.c
View File

@@ -36,7 +36,7 @@
static void main(unsigned long bist)
{
pc87351_enable_serial(SERIAL_DEV, TTYS0_BASE);
pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
report_bist_failure(bist);

2
src/mainboard/asi/mb_5blgp/irq_tables.c
View File

@@ -23,7 +23,7 @@
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE,
PIRQ_VERSION,
32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
(0x12 << 3) | 0x0, /* Interrupt router device */
0x8800, /* IRQs devoted exclusively to PCI usage */

26
src/mainboard/asi/mb_5blmp/Config.lb
View File

@@ -1,5 +1,5 @@
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
##
@@ -14,7 +14,7 @@ arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
if CONFIG_HAVE_PIRQ_TABLE
object irq_tables.o
end
@@ -22,22 +22,22 @@ end
## Romcc output
##
# makerule ./failover.E
# depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
# action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
# depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
# action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
# end
#
# makerule ./failover.inc
# depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
# action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
# depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
# action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
# end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c ../romcc"
action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "$(MAINBOARD)/auto.c ../romcc"
action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
##
@@ -51,7 +51,7 @@ ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -73,7 +73,7 @@ ldscript /arch/i386/lib/id.lds
### Things are delicate and we test to see if we should
### failover to another image.
###
# if USE_FALLBACK_IMAGE
# if CONFIG_USE_FALLBACK_IMAGE
# ldscript /arch/i386/lib/failover.lds
# mainboardinit ./failover.inc
# end

126
src/mainboard/asi/mb_5blmp/Options.lb
View File

@@ -1,52 +1,52 @@
uses HAVE_PIRQ_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_CBFS
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_ROM_PAYLOAD
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ARCH
uses CONFIG_FALLBACK_SIZE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESS
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses PAYLOAD_SIZE
uses _ROMBASE
uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses CROSS_COMPILE
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_RAMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
# uses CONFIG_CONSOLE_VGA
# uses CONFIG_PCI_ROM_RUN
uses CONFIG_VIDEO_MB
uses PIRQ_ROUTE
uses CONFIG_PIRQ_ROUTE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256 * 1024
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
default CONFIG_ROM_SIZE = 256 * 1024
###
### Build options
@@ -55,12 +55,12 @@ default ROM_SIZE = 256 * 1024
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
default CONFIG_HAVE_FALLBACK_BOOT=1
##
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
default CONFIG_HAVE_HARD_RESET=0
## Delay timer options
##
@@ -70,49 +70,49 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=5 # TODO?
default PIRQ_ROUTE=1
default CONFIG_HAVE_PIRQ_TABLE=1
default CONFIG_IRQ_SLOT_COUNT=5 # TODO?
default CONFIG_PIRQ_ROUTE=1
##
## Build code to export a CMOS option table
##
# default HAVE_OPTION_TABLE=0
# default CONFIG_HAVE_OPTION_TABLE=0
###
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 64 * 1024
default FALLBACK_SIZE = 128 * 1024
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
default CONFIG_FALLBACK_SIZE = 128 * 1024
##
## Use a small 8K stack
##
default STACK_SIZE=0x2000
default CONFIG_STACK_SIZE=0x2000
##
## Use a small 16K heap
##
default HEAP_SIZE=0x4000
default CONFIG_HEAP_SIZE=0x4000
##
## Only use the option table in a normal image
##
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
# default USE_OPTION_TABLE = 0
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
# default CONFIG_USE_OPTION_TABLE = 0
default _RAMBASE = 0x00004000
default CONFIG_RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
##
## The default compiler
##
default CROSS_COMPILE=""
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
default CONFIG_CROSS_COMPILE=""
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
default CONFIG_HOSTCC="gcc"
##
## The Serial Console
@@ -122,21 +122,21 @@ default HOSTCC="gcc"
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
default TTYS0_BAUD=115200
#default TTYS0_BAUD=57600
#default TTYS0_BAUD=38400
#default TTYS0_BAUD=19200
#default TTYS0_BAUD=9600
#default TTYS0_BAUD=4800
#default TTYS0_BAUD=2400
#default TTYS0_BAUD=1200
default CONFIG_TTYS0_BAUD=115200
#default CONFIG_TTYS0_BAUD=57600
#default CONFIG_TTYS0_BAUD=38400
#default CONFIG_TTYS0_BAUD=19200
#default CONFIG_TTYS0_BAUD=9600
#default CONFIG_TTYS0_BAUD=4800
#default CONFIG_TTYS0_BAUD=2400
#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
default TTYS0_BASE=0x3f8
default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default TTYS0_LCS=0x3
default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
@@ -148,13 +148,13 @@ default TTYS0_LCS=0x3
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
## DEBUG 8 debug-level messages
## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
default DEFAULT_CONSOLE_LOGLEVEL=9
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
## At a maximum only compile in this level of debugging
default MAXIMUM_CONSOLE_LOGLEVEL=9
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
# VGA Console
# default CONFIG_CONSOLE_VGA=1

2
src/mainboard/asi/mb_5blmp/auto.c
View File

@@ -38,7 +38,7 @@
static void main(unsigned long bist)
{
/* Initialize the serial console. */
pc87351_enable_serial(SERIAL_DEV, TTYS0_BASE);
pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();

40
src/mainboard/asus/a8n_e/Config.lb
View File

@@ -21,36 +21,36 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/failovercalculation.lb
arch i386 end
driver mainboard.o
# Needed by irq_tables and mptable and acpi_tables.
object get_bus_conf.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
if CONFIG_HAVE_MP_TABLE object mptable.o end
if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
if CONFIG_USE_INIT
makerule ./auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
end
else
makerule ./auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
if CONFIG_HAVE_FAILOVER_BOOT
if CONFIG_USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
else
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
@@ -60,8 +60,8 @@ mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/32bit/entry32.lds
ldscript /cpu/amd/car/cache_as_ram.lds
end
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
if CONFIG_HAVE_FAILOVER_BOOT
if CONFIG_USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -69,7 +69,7 @@ if HAVE_FAILOVER_BOOT
ldscript /cpu/x86/32bit/reset32.lds
end
else
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -81,24 +81,24 @@ end
mainboardinit southbridge/nvidia/ck804/id.inc
ldscript /southbridge/nvidia/ck804/id.lds
# ROMSTRAP table for CK804.
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
if CONFIG_HAVE_FAILOVER_BOOT
if CONFIG_USE_FAILOVER_IMAGE
mainboardinit southbridge/nvidia/ck804/romstrap.inc
ldscript /southbridge/nvidia/ck804/romstrap.lds
end
else
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit southbridge/nvidia/ck804/romstrap.inc
ldscript /southbridge/nvidia/ck804/romstrap.lds
end
end
mainboardinit cpu/amd/car/cache_as_ram.inc
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
if CONFIG_HAVE_FAILOVER_BOOT
if CONFIG_USE_FAILOVER_IMAGE
ldscript /arch/i386/lib/failover_failover.lds
end
else
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
end
end

200
src/mainboard/asus/a8n_e/Options.lb
View File

@@ -19,153 +19,153 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
uses HAVE_MP_TABLE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses USE_FAILOVER_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_FAILOVER_BOOT
uses HAVE_HARD_RESET
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_USE_FAILOVER_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_FAILOVER_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_LOGICAL_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
uses FAILOVER_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_FALLBACK_SIZE
uses CONFIG_FAILOVER_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses PAYLOAD_SIZE
uses _ROMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses STACK_SIZE
uses HEAP_SIZE
uses USE_OPTION_TABLE
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_LB_CKS_RANGE_START
uses CONFIG_LB_CKS_RANGE_END
uses CONFIG_LB_CKS_LOC
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses CONFIG_RAMBASE
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses CONFIG_CONSOLE_BTEXT
uses HAVE_INIT_TIMER
uses CONFIG_HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses CONFIG_HW_MEM_HOLE_SIZEK
uses CONFIG_USE_DCACHE_RAM
uses CONFIG_DCACHE_RAM_BASE
uses CONFIG_DCACHE_RAM_SIZE
uses CONFIG_USE_INIT
uses DCACHE_RAM_GLOBAL_VAR_SIZE
uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
uses CONFIG_AP_CODE_IN_CAR
uses MEM_TRAIN_SEQ
uses WAIT_BEFORE_CPUS_INIT
uses ENABLE_APIC_EXT_ID
uses APIC_ID_OFFSET
uses LIFT_BSP_APIC_ID
uses CONFIG_MEM_TRAIN_SEQ
uses CONFIG_WAIT_BEFORE_CPUS_INIT
uses CONFIG_ENABLE_APIC_EXT_ID
uses CONFIG_APIC_ID_OFFSET
uses CONFIG_LIFT_BSP_APIC_ID
uses CONFIG_PCI_64BIT_PREF_MEM
uses HT_CHAIN_UNITID_BASE
uses HT_CHAIN_END_UNITID_BASE
uses SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses CONFIG_HT_CHAIN_UNITID_BASE
uses CONFIG_HT_CHAIN_END_UNITID_BASE
uses CONFIG_SB_HT_CHAIN_ON_BUS0
uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses CONFIG_LB_MEM_TOPK
uses CONFIG_USE_PRINTK_IN_CAR
default ROM_SIZE = 512 * 1024
default ROM_IMAGE_SIZE = 64 * 1024
default FALLBACK_SIZE = 252 * 1024
default FAILOVER_SIZE = 4 * 1024
default HAVE_FALLBACK_BOOT = 1
default HAVE_FAILOVER_BOOT = 1
default HAVE_HARD_RESET = 1
default HAVE_PIRQ_TABLE = 1
default IRQ_SLOT_COUNT = 13
default HAVE_MP_TABLE = 1
default HAVE_OPTION_TABLE = 1
default CONFIG_ROM_SIZE = 512 * 1024
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
default CONFIG_FALLBACK_SIZE = 252 * 1024
default CONFIG_FAILOVER_SIZE = 4 * 1024
default CONFIG_HAVE_FALLBACK_BOOT = 1
default CONFIG_HAVE_FAILOVER_BOOT = 1
default CONFIG_HAVE_HARD_RESET = 1
default CONFIG_HAVE_PIRQ_TABLE = 1
default CONFIG_IRQ_SLOT_COUNT = 13
default CONFIG_HAVE_MP_TABLE = 1
default CONFIG_HAVE_OPTION_TABLE = 1
# Move the default coreboot CMOS range off of AMD RTC registers.
default LB_CKS_RANGE_START = 49
default LB_CKS_RANGE_END = 122
default LB_CKS_LOC = 123
default CONFIG_LB_CKS_RANGE_START = 49
default CONFIG_LB_CKS_RANGE_END = 122
default CONFIG_LB_CKS_LOC = 123
# SMP support (only worry about 2 micro processors).
default CONFIG_SMP = 1
default CONFIG_MAX_CPUS = 2
default CONFIG_MAX_PHYSICAL_CPUS = 1
default CONFIG_LOGICAL_CPUS = 1
# 1G memory hole.
default HW_MEM_HOLE_SIZEK = 0x100000
default CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
# HT Unit ID offset, default is 1, the typical one.
default HT_CHAIN_UNITID_BASE = 0
default CONFIG_HT_CHAIN_UNITID_BASE = 0
# Real SB Unit ID, default is 0x20, mean don't touch it at last.
# default HT_CHAIN_END_UNITID_BASE = 0x10
# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x10
# Make the SB HT chain on bus 0, default is not (0).
default SB_HT_CHAIN_ON_BUS0 = 2
default CONFIG_SB_HT_CHAIN_ON_BUS0 = 2
# Only offset for SB chain?, default is yes(1).
default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
# default CONFIG_CONSOLE_BTEXT = 1 # BTEXT console
default CONFIG_CONSOLE_VGA = 1 # For VGA console
default CONFIG_PCI_ROM_RUN = 1 # For VGA console
default USE_DCACHE_RAM = 1
default DCACHE_RAM_BASE = 0xc8000
default DCACHE_RAM_SIZE = 32 * 1024
default DCACHE_RAM_GLOBAL_VAR_SIZE = 4 * 1024
default CONFIG_USE_DCACHE_RAM = 1
default CONFIG_DCACHE_RAM_BASE = 0xc8000
default CONFIG_DCACHE_RAM_SIZE = 32 * 1024
default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 4 * 1024
default CONFIG_USE_INIT = 0
default CONFIG_AP_CODE_IN_CAR = 0
default MEM_TRAIN_SEQ = 2
default WAIT_BEFORE_CPUS_INIT = 0
# default ENABLE_APIC_EXT_ID = 0
# default APIC_ID_OFFSET = 0x10
# default LIFT_BSP_APIC_ID = 0
default CONFIG_MEM_TRAIN_SEQ = 2
default CONFIG_WAIT_BEFORE_CPUS_INIT = 0
# default CONFIG_ENABLE_APIC_EXT_ID = 0
# default CONFIG_APIC_ID_OFFSET = 0x10
# default CONFIG_LIFT_BSP_APIC_ID = 0
# default CONFIG_PCI_64BIT_PREF_MEM = 1
default CONFIG_IOAPIC = 1
default MAINBOARD_PART_NUMBER = "A8N-E"
default MAINBOARD_VENDOR = "ASUS"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a
default STACK_SIZE = 8 * 1024
default HEAP_SIZE = 16 * 1024
default CONFIG_MAINBOARD_PART_NUMBER = "A8N-E"
default CONFIG_MAINBOARD_VENDOR = "ASUS"
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a
default CONFIG_STACK_SIZE = 8 * 1024
default CONFIG_HEAP_SIZE = 16 * 1024
# Only use the option table in a normal image.
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE)
default _RAMBASE = 0x00004000
default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE)
default CONFIG_RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
default CC = "$(CROSS_COMPILE)gcc -m32"
default HOSTCC = "gcc"
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
default CONFIG_HOSTCC = "gcc"
default CONFIG_GDB_STUB = 0
default CONFIG_USE_PRINTK_IN_CAR=1
default CONFIG_CONSOLE_SERIAL8250 = 1
default TTYS0_BAUD = 115200
default TTYS0_BASE = 0x3f8
default TTYS0_LCS = 0x3
default DEFAULT_CONSOLE_LOGLEVEL = 8
default MAXIMUM_CONSOLE_LOGLEVEL = 8
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
default CONFIG_TTYS0_BAUD = 115200
default CONFIG_TTYS0_BASE = 0x3f8
default CONFIG_TTYS0_LCS = 0x3
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
#
# CBFS

24
src/mainboard/asus/a8n_e/cache_as_ram_auto.c
View File

@@ -50,7 +50,7 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
#if USE_FAILOVER_IMAGE == 0
#if CONFIG_USE_FAILOVER_IMAGE == 0
/* Used by ck894_early_setup(). */
#define CK804_NUM 1
@@ -99,10 +99,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#endif /* USE_FAILOVER_IMAGE */
#endif /* CONFIG_USE_FAILOVER_IMAGE */
#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) \
|| ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) \
|| ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -166,7 +166,7 @@ normal_image:
fallback_image:
#if HAVE_FAILOVER_BOOT == 1
#if CONFIG_HAVE_FAILOVER_BOOT == 1
__asm__ volatile ("jmp __fallback_image"
: /* outputs */
:"a" (bist), "b"(cpu_init_detectedx) /* inputs */
@@ -175,27 +175,27 @@ fallback_image:
;
}
#endif /* ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) ... */
#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) ... */
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if HAVE_FAILOVER_BOOT == 1
#if USE_FAILOVER_IMAGE == 1
#if CONFIG_HAVE_FAILOVER_BOOT == 1
#if CONFIG_USE_FAILOVER_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#else
real_main(bist, cpu_init_detectedx);
#endif
#else
#if USE_FALLBACK_IMAGE == 1
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
#endif
}
#if USE_FAILOVER_IMAGE == 0
#if CONFIG_USE_FAILOVER_IMAGE == 0
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
@@ -215,7 +215,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
bsp_apicid = init_cpus(cpu_init_detectedx);
it8712f_24mhz_clkin();
it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE);
it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
@@ -266,4 +266,4 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}
#endif /* USE_FAILOVER_IMAGE */
#endif /* CONFIG_USE_FAILOVER_IMAGE */

28
src/mainboard/asus/a8v-e_se/Config.lb
View File

@@ -20,42 +20,42 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
default CONFIG_ROM_PAYLOAD = 1
arch i386 end
driver mainboard.o
if HAVE_ACPI_TABLES
if CONFIG_HAVE_ACPI_TABLES
object acpi_tables.o
makerule dsdt.c
depends "$(MAINBOARD)/dsdt.asl"
action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/dsdt.asl"
depends "$(CONFIG_MAINBOARD)/dsdt.asl"
action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl"
action "mv dsdt.hex dsdt.c"
end
object ./dsdt.o
end
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
if CONFIG_HAVE_MP_TABLE object mptable.o end
if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
# object reset.o
if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
end
else
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
mainboardinit southbridge/via/k8t890/romstrap.inc
@@ -71,7 +71,7 @@ mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/amd/car/cache_as_ram.lds
end
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -81,7 +81,7 @@ end
mainboardinit cpu/amd/car/cache_as_ram.inc
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
end

188
src/mainboard/asus/a8v-e_se/Options.lb
View File

@@ -17,156 +17,156 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
uses HAVE_MP_TABLE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_LOGICAL_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_FALLBACK_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
uses PAYLOAD_SIZE
uses _ROMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses STACK_SIZE
uses HEAP_SIZE
# uses USE_OPTION_TABLE
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
# uses CONFIG_USE_OPTION_TABLE
# uses CONFIG_LB_MEM_TOPK
uses HAVE_ACPI_TABLES
uses HAVE_ACPI_RESUME
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses CONFIG_HAVE_ACPI_TABLES
uses CONFIG_HAVE_ACPI_RESUME
uses CONFIG_LB_CKS_RANGE_START
uses CONFIG_LB_CKS_RANGE_END
uses CONFIG_LB_CKS_LOC
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses CONFIG_RAMBASE
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
# bx_b001- uses K8_HW_MEM_HOLE_SIZEK
uses K8_HT_FREQ_1G_SUPPORT
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses DCACHE_RAM_GLOBAL_VAR_SIZE
uses CONFIG_K8_HT_FREQ_1G_SUPPORT
uses CONFIG_USE_DCACHE_RAM
uses CONFIG_DCACHE_RAM_BASE
uses CONFIG_DCACHE_RAM_SIZE
uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
uses CONFIG_USE_INIT
uses ENABLE_APIC_EXT_ID
uses APIC_ID_OFFSET
uses LIFT_BSP_APIC_ID
uses HT_CHAIN_UNITID_BASE
uses HT_CHAIN_END_UNITID_BASE
uses CONFIG_ENABLE_APIC_EXT_ID
uses CONFIG_APIC_ID_OFFSET
uses CONFIG_LIFT_BSP_APIC_ID
uses CONFIG_HT_CHAIN_UNITID_BASE
uses CONFIG_HT_CHAIN_END_UNITID_BASE
# bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
# bx_b005+
uses SB_HT_CHAIN_ON_BUS0
uses CONFIG_SB_HT_CHAIN_ON_BUS0
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_USE_PRINTK_IN_CAR
default ROM_SIZE = 512 * 1024
default FALLBACK_SIZE = 256 * 1024
default HAVE_FALLBACK_BOOT = 1
default HAVE_HARD_RESET = 0
default HAVE_PIRQ_TABLE = 0
default IRQ_SLOT_COUNT = 11 # FIXME?
default HAVE_MP_TABLE = 1
default HAVE_OPTION_TABLE = 0 # FIXME
default CONFIG_ROM_SIZE = 512 * 1024
default CONFIG_FALLBACK_SIZE = 256 * 1024
default CONFIG_HAVE_FALLBACK_BOOT = 1
default CONFIG_HAVE_HARD_RESET = 0
default CONFIG_HAVE_PIRQ_TABLE = 0
default CONFIG_IRQ_SLOT_COUNT = 11 # FIXME?
default CONFIG_HAVE_MP_TABLE = 1
default CONFIG_HAVE_OPTION_TABLE = 0 # FIXME
# Move the default coreboot CMOS range off of AMD RTC registers.
default LB_CKS_RANGE_START = 49
default LB_CKS_RANGE_END = 122
default LB_CKS_LOC = 123
default CONFIG_LB_CKS_RANGE_START = 49
default CONFIG_LB_CKS_RANGE_END = 122
default CONFIG_LB_CKS_LOC = 123
default CONFIG_SMP = 1
default CONFIG_MAX_CPUS = 2
default CONFIG_MAX_PHYSICAL_CPUS = 1
default CONFIG_LOGICAL_CPUS = 1
default HAVE_ACPI_TABLES = 1
default CONFIG_HAVE_ACPI_TABLES = 1
# 1G memory hole
# bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000
# Opteron K8 1G HT support
default K8_HT_FREQ_1G_SUPPORT = 1
default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1
# HT Unit ID offset, default is 1, the typical one.
default HT_CHAIN_UNITID_BASE = 0x0
default CONFIG_HT_CHAIN_UNITID_BASE = 0x0
# Real SB Unit ID, default is 0x20, mean don't touch it at last.
# default HT_CHAIN_END_UNITID_BASE = 0x0
# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
# Make the SB HT chain on bus 0, default is not (0).
# bx_b001- default K8_SB_HT_CHAIN_ON_BUS0 = 2
# bx_b005+ make the SB HT chain on bus 0.
default SB_HT_CHAIN_ON_BUS0 = 1
default CONFIG_SB_HT_CHAIN_ON_BUS0 = 1
# Only offset for SB chain?, default is yes(1).
default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
default CONFIG_CONSOLE_VGA = 1 # Needed for VGA.
default CONFIG_PCI_ROM_RUN = 1 # Needed for VGA.
default USE_DCACHE_RAM = 1
default DCACHE_RAM_BASE = 0xcc000
default DCACHE_RAM_SIZE = 0x4000
default DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000
default CONFIG_USE_DCACHE_RAM = 1
default CONFIG_DCACHE_RAM_BASE = 0xcc000
default CONFIG_DCACHE_RAM_SIZE = 0x4000
default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000
default CONFIG_USE_INIT = 0
default ENABLE_APIC_EXT_ID = 0
default APIC_ID_OFFSET = 0x10
default LIFT_BSP_APIC_ID = 0
default CONFIG_ENABLE_APIC_EXT_ID = 0
default CONFIG_APIC_ID_OFFSET = 0x10
default CONFIG_LIFT_BSP_APIC_ID = 0
default CONFIG_IOAPIC = 1
default MAINBOARD_VENDOR = "ASUS"
default MAINBOARD_PART_NUMBER = "A8V-E SE"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
# default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME
default ROM_IMAGE_SIZE = 64 * 1024
default STACK_SIZE = 8 * 1024
default HEAP_SIZE = 256 * 1024
default CONFIG_MAINBOARD_VENDOR = "ASUS"
default CONFIG_MAINBOARD_PART_NUMBER = "A8V-E SE"
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
# default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
default CONFIG_STACK_SIZE = 8 * 1024
default CONFIG_HEAP_SIZE = 256 * 1024
# More 1M for pgtbl.
# default CONFIG_LB_MEM_TOPK = 2048
default _RAMBASE = 0x00004000
# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default CONFIG_RAMBASE = 0x00004000
# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
default CONFIG_ROM_PAYLOAD = 1
default CC = "$(CROSS_COMPILE)gcc -m32"
default HOSTCC = "gcc"
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
default CONFIG_HOSTCC = "gcc"
default CONFIG_GDB_STUB = 0
default CONFIG_USE_PRINTK_IN_CAR = 1
default CONFIG_CONSOLE_SERIAL8250 = 1
default TTYS0_BAUD = 115200
default TTYS0_BASE = 0x3f8
default TTYS0_LCS = 0x3 # 8n1
default DEFAULT_CONSOLE_LOGLEVEL = 8
default MAXIMUM_CONSOLE_LOGLEVEL = 8
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
default CONFIG_TTYS0_BAUD = 115200
default CONFIG_TTYS0_BASE = 0x3f8
default CONFIG_TTYS0_LCS = 0x3 # 8n1
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
#
# CBFS
#

10
src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
View File

@@ -178,7 +178,7 @@ void sio_init(void)
pnp_exit_ext_func_mode(GPIO_DEV);
}
#if USE_FALLBACK_IMAGE == 1
#if CONFIG_USE_FALLBACK_IMAGE == 1
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
@@ -187,7 +187,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
unsigned last_boot_normal_x = 1;
sio_init();
w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE);
w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
enable_rom_decode();
@@ -232,7 +232,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if USE_FALLBACK_IMAGE == 1
#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
@@ -251,11 +251,11 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
unsigned bsp_apicid = 0;
int needs_reset = 0;
struct sys_info *sysinfo =
(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
char *p;
sio_init();
w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE);
w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
enable_rom_decode();

24
src/mainboard/asus/m2v-mx_se/Config.lb
View File

@@ -20,18 +20,18 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 128 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 128 * 1024
include /config/nofailovercalculation.lb
arch i386 end
driver mainboard.o
if HAVE_ACPI_TABLES
if CONFIG_HAVE_ACPI_TABLES
object acpi_tables.o
makerule dsdt.c
depends "$(MAINBOARD)/dsdt.asl"
action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/dsdt.asl"
depends "$(CONFIG_MAINBOARD)/dsdt.asl"
action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl"
action "mv dsdt.hex dsdt.c"
end
object ./dsdt.o
@@ -39,19 +39,19 @@ end
if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
end
else
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
mainboardinit southbridge/via/k8t890/romstrap.inc
@@ -67,7 +67,7 @@ mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/amd/car/cache_as_ram.lds
end
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -77,7 +77,7 @@ end
mainboardinit cpu/amd/car/cache_as_ram.inc
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
end

192
src/mainboard/asus/m2v-mx_se/Options.lb
View File

@@ -17,159 +17,159 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
uses HAVE_MP_TABLE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_LOGICAL_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_FALLBACK_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
uses PAYLOAD_SIZE
uses _ROMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses STACK_SIZE
uses HEAP_SIZE
# uses USE_OPTION_TABLE
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
# uses CONFIG_USE_OPTION_TABLE
uses CONFIG_LB_MEM_TOPK
uses HAVE_ACPI_TABLES
uses HAVE_MAINBOARD_RESOURCES
uses HAVE_ACPI_RESUME
uses HAVE_LOW_TABLES
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses CONFIG_HAVE_ACPI_TABLES
uses CONFIG_HAVE_MAINBOARD_RESOURCES
uses CONFIG_HAVE_ACPI_RESUME
uses CONFIG_HAVE_LOW_TABLES
uses CONFIG_LB_CKS_RANGE_START
uses CONFIG_LB_CKS_RANGE_END
uses CONFIG_LB_CKS_LOC
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses CONFIG_RAMBASE
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
# bx_b001- uses K8_HW_MEM_HOLE_SIZEK
uses K8_HT_FREQ_1G_SUPPORT
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses DCACHE_RAM_GLOBAL_VAR_SIZE
uses CONFIG_K8_HT_FREQ_1G_SUPPORT
uses CONFIG_USE_DCACHE_RAM
uses CONFIG_DCACHE_RAM_BASE
uses CONFIG_DCACHE_RAM_SIZE
uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
uses CONFIG_USE_INIT
uses ENABLE_APIC_EXT_ID
uses APIC_ID_OFFSET
uses LIFT_BSP_APIC_ID
uses HT_CHAIN_UNITID_BASE
uses HT_CHAIN_END_UNITID_BASE
uses CONFIG_ENABLE_APIC_EXT_ID
uses CONFIG_APIC_ID_OFFSET
uses CONFIG_LIFT_BSP_APIC_ID
uses CONFIG_HT_CHAIN_UNITID_BASE
uses CONFIG_HT_CHAIN_END_UNITID_BASE
# bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
# bx_b005+
uses SB_HT_CHAIN_ON_BUS0
uses CONFIG_SB_HT_CHAIN_ON_BUS0
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_USE_PRINTK_IN_CAR
default HAVE_FALLBACK_BOOT = 1
default HAVE_HARD_RESET = 1
default HAVE_PIRQ_TABLE = 0
default IRQ_SLOT_COUNT = 11 # FIXME?
default HAVE_MP_TABLE = 0
default HAVE_OPTION_TABLE = 0 # FIXME
default CONFIG_HAVE_FALLBACK_BOOT = 1
default CONFIG_HAVE_HARD_RESET = 1
default CONFIG_HAVE_PIRQ_TABLE = 0
default CONFIG_IRQ_SLOT_COUNT = 11 # FIXME?
default CONFIG_HAVE_MP_TABLE = 0
default CONFIG_HAVE_OPTION_TABLE = 0 # FIXME
# Move the default coreboot CMOS range off of AMD RTC registers.
default LB_CKS_RANGE_START = 49
default LB_CKS_RANGE_END = 122
default LB_CKS_LOC = 123
default CONFIG_LB_CKS_RANGE_START = 49
default CONFIG_LB_CKS_RANGE_END = 122
default CONFIG_LB_CKS_LOC = 123
default CONFIG_SMP = 1
default CONFIG_MAX_CPUS = 2
default CONFIG_MAX_PHYSICAL_CPUS = 1
default CONFIG_LOGICAL_CPUS = 1
default HAVE_ACPI_TABLES = 1
default HAVE_MAINBOARD_RESOURCES = 1
default HAVE_LOW_TABLES = 0
default HAVE_ACPI_RESUME = 1
default CONFIG_HAVE_ACPI_TABLES = 1
default CONFIG_HAVE_MAINBOARD_RESOURCES = 1
default CONFIG_HAVE_LOW_TABLES = 0
default CONFIG_HAVE_ACPI_RESUME = 1
# 1G memory hole
# bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000
# Opteron K8 1G HT support
default K8_HT_FREQ_1G_SUPPORT = 1
default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1
# HT Unit ID offset, default is 1, the typical one.
default HT_CHAIN_UNITID_BASE = 0x0
default CONFIG_HT_CHAIN_UNITID_BASE = 0x0
# Real SB Unit ID, default is 0x20, mean don't touch it at last.
# default HT_CHAIN_END_UNITID_BASE = 0x0
# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
# Make the SB HT chain on bus 0, default is not (0).
# bx_b001- default K8_SB_HT_CHAIN_ON_BUS0 = 2
# bx_b005+ make the SB HT chain on bus 0.
default SB_HT_CHAIN_ON_BUS0 = 1
default CONFIG_SB_HT_CHAIN_ON_BUS0 = 1
# Only offset for SB chain?, default is yes(1).
default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
default CONFIG_CONSOLE_VGA = 1 # Needed for VGA.
default CONFIG_PCI_ROM_RUN = 0 # Needed for VGA.
default USE_DCACHE_RAM = 1
default DCACHE_RAM_BASE = 0xcc000
default DCACHE_RAM_SIZE = 0x4000
default DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000
default CONFIG_USE_DCACHE_RAM = 1
default CONFIG_DCACHE_RAM_BASE = 0xcc000
default CONFIG_DCACHE_RAM_SIZE = 0x4000
default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000
default CONFIG_USE_INIT = 0
default ENABLE_APIC_EXT_ID = 0
default APIC_ID_OFFSET = 0x10
default LIFT_BSP_APIC_ID = 0
default CONFIG_ENABLE_APIC_EXT_ID = 0
default CONFIG_APIC_ID_OFFSET = 0x10
default CONFIG_LIFT_BSP_APIC_ID = 0
default CONFIG_IOAPIC = 1
default MAINBOARD_VENDOR = "ASUS"
default MAINBOARD_PART_NUMBER = "M2V-MX SE"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
# default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME
default STACK_SIZE = 8 * 1024
default HEAP_SIZE = 256 * 1024
default CONFIG_MAINBOARD_VENDOR = "ASUS"
default CONFIG_MAINBOARD_PART_NUMBER = "M2V-MX SE"
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
# default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME
default CONFIG_STACK_SIZE = 8 * 1024
default CONFIG_HEAP_SIZE = 256 * 1024
# More 1M for pgtbl.
default CONFIG_LB_MEM_TOPK = 32768
# to 1MB
default _RAMBASE = 0x1F00000
# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default CONFIG_RAMBASE = 0x1F00000
# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
default CONFIG_ROM_PAYLOAD = 1
default CC = "$(CROSS_COMPILE)gcc -m32"
default HOSTCC = "gcc"
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
default CONFIG_HOSTCC = "gcc"
default CONFIG_GDB_STUB = 0
default CONFIG_USE_PRINTK_IN_CAR=1
default CONFIG_CONSOLE_SERIAL8250 = 1
default TTYS0_BAUD = 115200
default TTYS0_BASE = 0x3f8
default TTYS0_LCS = 0x3 # 8n1
default DEFAULT_CONSOLE_LOGLEVEL = 9
default MAXIMUM_CONSOLE_LOGLEVEL = 9
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
default CONFIG_TTYS0_BAUD = 115200
default CONFIG_TTYS0_BASE = 0x3f8
default CONFIG_TTYS0_LCS = 0x3 # 8n1
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
#
# CBFS
#

6
src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c
View File

@@ -40,7 +40,7 @@ unsigned int get_sbdn(unsigned bus);
/* If we want to wait for core1 done before DQS training, set it to 0. */
#define K8_SET_FIDVID_CORE0_ONLY 1
#if K8_REV_F_SUPPORT == 1
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -183,12 +183,12 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
unsigned bsp_apicid = 0;
int needs_reset = 0;
struct sys_info *sysinfo =
(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
char *p;
u8 reg;
sio_init();
it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE);
it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog();
it8712f_enable_3vsbsw();
uart_init();

6
src/mainboard/asus/m2v-mx_se/mainboard.c
View File

@@ -25,11 +25,11 @@
int add_mainboard_resources(struct lb_memory *mem)
{
#if HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME == 1
lb_add_memory_range(mem, LB_MEM_RESERVED,
_RAMBASE, ((CONFIG_LB_MEM_TOPK<<10) - _RAMBASE));
CONFIG_RAMBASE, ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_RAMBASE));
lb_add_memory_range(mem, LB_MEM_RESERVED,
DCACHE_RAM_BASE, DCACHE_RAM_SIZE);
CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE);
#endif
return 0;
}

30
src/mainboard/asus/mew-am/Config.lb
View File

@@ -18,40 +18,40 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
if CONFIG_HAVE_PIRQ_TABLE
object irq_tables.o
end
makerule ./failover.E
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./auto.E
# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(MAINBOARD)/auto.c ../romcc"
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
# Note: The -mcpu=p2 is important, or else... 'too few registers'.
action "../romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
action "../romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(MAINBOARD)/auto.c ../romcc"
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
# Note: The -mcpu=p2 is important, or else... 'too few registers'.
action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -61,7 +61,7 @@ end
mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end

120
src/mainboard/asus/mew-am/Options.lb
View File

@@ -18,82 +18,82 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
uses HAVE_MP_TABLE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_ROM_PAYLOAD
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ARCH
uses CONFIG_FALLBACK_SIZE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses PAYLOAD_SIZE
uses _ROMBASE
uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
uses CROSS_COMPILE
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_RAMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
default ROM_SIZE = 512 * 1024 # Override this in targets/*/Config.lb.
default HAVE_FALLBACK_BOOT = 1
default HAVE_MP_TABLE = 0
default HAVE_HARD_RESET = 0
default CONFIG_ROM_SIZE = 512 * 1024 # Override this in targets/*/Config.lb.
default CONFIG_HAVE_FALLBACK_BOOT = 1
default CONFIG_HAVE_MP_TABLE = 0
default CONFIG_HAVE_HARD_RESET = 0
default CONFIG_UDELAY_TSC = 1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
default HAVE_PIRQ_TABLE = 1
default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
default ROM_IMAGE_SIZE = 64 * 1024
default FALLBACK_SIZE = 128 * 1024
default STACK_SIZE = 8 * 1024
default HEAP_SIZE = 16 * 1024
default HAVE_OPTION_TABLE = 0
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0
default _RAMBASE = 0x00004000
default CONFIG_HAVE_PIRQ_TABLE = 1
default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
default CONFIG_FALLBACK_SIZE = 128 * 1024
default CONFIG_STACK_SIZE = 8 * 1024
default CONFIG_HEAP_SIZE = 16 * 1024
default CONFIG_HAVE_OPTION_TABLE = 0
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
default CONFIG_USE_OPTION_TABLE = 0
default CONFIG_RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
default CROSS_COMPILE = ""
default CC = "$(CROSS_COMPILE)gcc -m32"
default HOSTCC = "gcc"
default CONFIG_CROSS_COMPILE = ""
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
default CONFIG_HOSTCC = "gcc"
default CONFIG_CONSOLE_SERIAL8250 = 1
default TTYS0_BAUD = 115200
default TTYS0_BASE = 0x3f8
default TTYS0_LCS = 0x3 # 8n1
default DEFAULT_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb.
default MAXIMUM_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb.
default CONFIG_TTYS0_BAUD = 115200
default CONFIG_TTYS0_BASE = 0x3f8
default CONFIG_TTYS0_LCS = 0x3 # 8n1
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb.
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb.
default CONFIG_CONSOLE_VGA = 1 # Override this in targets/*/Config.lb.
default CONFIG_PCI_ROM_RUN = 1 # Override this in targets/*/Config.lb.

2
src/mainboard/asus/mew-am/auto.c
View File

@@ -54,7 +54,7 @@ static void main(unsigned long bist)
if (bist == 0)
early_mtrr_init();
smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE);
smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
report_bist_failure(bist);

2
src/mainboard/asus/mew-am/irq_tables.c
View File

@@ -23,7 +23,7 @@
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE,
PIRQ_VERSION,
32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
(0x1f << 3) | 0x0, /* Interrupt router device */
0, /* IRQs devoted exclusively to PCI usage */

26
src/mainboard/asus/mew-vm/Config.lb
View File

@@ -1,5 +1,5 @@
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
##
@@ -14,29 +14,29 @@ arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE object irq_tables.o end
if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
##
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
##
@@ -50,7 +50,7 @@ ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -72,7 +72,7 @@ ldscript /arch/i386/lib/id.lds
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end

132
src/mainboard/asus/mew-vm/Options.lb
View File

@@ -1,50 +1,50 @@
uses HAVE_MP_TABLE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_ROM_PAYLOAD
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ARCH
uses CONFIG_FALLBACK_SIZE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses PAYLOAD_SIZE
uses _ROMBASE
uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
uses CROSS_COMPILE
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_RAMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_UDELAY_TSC
uses CONFIG_IDE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 512*1024
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
default CONFIG_ROM_SIZE = 512*1024
###
### Build options
@@ -53,28 +53,28 @@ default ROM_SIZE = 512*1024
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT = 1
default CONFIG_HAVE_FALLBACK_BOOT = 1
##
## no MP table
##
default HAVE_MP_TABLE = 0
default CONFIG_HAVE_MP_TABLE = 0
##
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET = 0
default CONFIG_HAVE_HARD_RESET = 0
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE = 1
default IRQ_SLOT_COUNT = 11
default CONFIG_HAVE_PIRQ_TABLE = 1
default CONFIG_IRQ_SLOT_COUNT = 11
##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE = 0
default CONFIG_HAVE_OPTION_TABLE = 0
## IDE Support
default CONFIG_IDE = 1
@@ -83,36 +83,36 @@ default CONFIG_IDE = 1
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default CONFIG_ROM_IMAGE_SIZE = 65536
default CONFIG_FALLBACK_SIZE = 131072
##
## Use a small 8K stack
##
default STACK_SIZE=0x2000
default CONFIG_STACK_SIZE=0x2000
##
## Use a small 16K heap
##
default HEAP_SIZE=0x4000
default CONFIG_HEAP_SIZE=0x4000
##
## Only use the option table in a normal image
##
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
default CONFIG_USE_OPTION_TABLE = 0
default _RAMBASE = 0x00004000
default CONFIG_RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
##
## The default compiler
##
default CROSS_COMPILE=""
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
default CONFIG_CROSS_COMPILE=""
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
default CONFIG_HOSTCC="gcc"
##
## The Serial Console
@@ -122,21 +122,21 @@ default HOSTCC="gcc"
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
default TTYS0_BAUD=115200
#default TTYS0_BAUD=57600
#default TTYS0_BAUD=38400
#default TTYS0_BAUD=19200
#default TTYS0_BAUD=9600
#default TTYS0_BAUD=4800
#default TTYS0_BAUD=2400
#default TTYS0_BAUD=1200
default CONFIG_TTYS0_BAUD=115200
#default CONFIG_TTYS0_BAUD=57600
#default CONFIG_TTYS0_BAUD=38400
#default CONFIG_TTYS0_BAUD=19200
#default CONFIG_TTYS0_BAUD=9600
#default CONFIG_TTYS0_BAUD=4800
#default CONFIG_TTYS0_BAUD=2400
#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
default TTYS0_BASE=0x3f8
default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default TTYS0_LCS=0x3
default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
@@ -148,13 +148,13 @@ default TTYS0_LCS=0x3
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
## DEBUG 8 debug-level messages
## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
default DEFAULT_CONSOLE_LOGLEVEL=9
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
## At a maximum only compile in this level of debugging
default MAXIMUM_CONSOLE_LOGLEVEL=9
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
default CONFIG_UDELAY_TSC=1

2
src/mainboard/asus/mew-vm/auto.c
View File

@@ -58,7 +58,7 @@ static void main(unsigned long bist)
if (bist == 0)
early_mtrr_init();
lpc47b272_enable_serial(SERIAL_DEV, TTYS0_BASE);
lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();

32
src/mainboard/asus/p2b-d/Config.lb
View File

@@ -18,37 +18,37 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
arch i386 end
driver mainboard.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
if CONFIG_HAVE_MP_TABLE object mptable.o end
if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
makerule ./failover.E
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./auto.E
# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(MAINBOARD)/auto.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(MAINBOARD)/auto.c ../romcc"
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -58,7 +58,7 @@ end
mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end

120
src/mainboard/asus/p2b-d/Options.lb
View File

@@ -18,89 +18,89 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
uses HAVE_MP_TABLE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_ROM_PAYLOAD
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ARCH
uses CONFIG_FALLBACK_SIZE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses PAYLOAD_SIZE
uses _ROMBASE
uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
uses CROSS_COMPILE
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_RAMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses CONFIG_SMP
uses CONFIG_MAX_CPUS
uses CONFIG_IOAPIC
default ROM_SIZE = 256 * 1024
default HAVE_FALLBACK_BOOT = 1
default HAVE_MP_TABLE = 1
default HAVE_HARD_RESET = 0
default CONFIG_ROM_SIZE = 256 * 1024
default CONFIG_HAVE_FALLBACK_BOOT = 1
default CONFIG_HAVE_MP_TABLE = 1
default CONFIG_HAVE_HARD_RESET = 0
default CONFIG_UDELAY_TSC = 1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
default HAVE_PIRQ_TABLE = 1
default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
default ROM_IMAGE_SIZE = 64 * 1024
default FALLBACK_SIZE = 128 * 1024
default STACK_SIZE = 8 * 1024
default HEAP_SIZE = 16 * 1024
default HAVE_OPTION_TABLE = 0
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0
default _RAMBASE = 0x00004000
default CONFIG_HAVE_PIRQ_TABLE = 1
default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
default CONFIG_FALLBACK_SIZE = 128 * 1024
default CONFIG_STACK_SIZE = 8 * 1024
default CONFIG_HEAP_SIZE = 16 * 1024
default CONFIG_HAVE_OPTION_TABLE = 0
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
default CONFIG_USE_OPTION_TABLE = 0
default CONFIG_RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
default CONFIG_SMP = 1
default CONFIG_MAX_CPUS = 2
default CONFIG_IOAPIC = 1
default CROSS_COMPILE = ""
default CC = "$(CROSS_COMPILE)gcc -m32"
default HOSTCC = "gcc"
default CONFIG_CROSS_COMPILE = ""
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
default CONFIG_HOSTCC = "gcc"
default CONFIG_CONSOLE_SERIAL8250 = 1
default TTYS0_BAUD = 115200
default TTYS0_BASE = 0x3f8
default TTYS0_LCS = 0x3 # 8n1
default DEFAULT_CONSOLE_LOGLEVEL = 9
default MAXIMUM_CONSOLE_LOGLEVEL = 9
default CONFIG_TTYS0_BAUD = 115200
default CONFIG_TTYS0_BASE = 0x3f8
default CONFIG_TTYS0_LCS = 0x3 # 8n1
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
default CONFIG_CONSOLE_VGA = 1
default CONFIG_PCI_ROM_RUN = 1
default CONFIG_CBFS = 0

2
src/mainboard/asus/p2b-d/auto.c
View File

@@ -57,7 +57,7 @@ static void main(unsigned long bist)
enable_lapic(); /* FIXME? */
}
w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE);
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
report_bist_failure(bist);

2
src/mainboard/asus/p2b-d/irq_tables.c
View File

@@ -23,7 +23,7 @@
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE,
PIRQ_VERSION,
32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
(0x04 << 3) | 0x0, /* Interrupt router device */
0, /* IRQs devoted exclusively to PCI usage */

32
src/mainboard/asus/p2b-ds/Config.lb
View File

@@ -18,37 +18,37 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
arch i386 end
driver mainboard.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
if CONFIG_HAVE_MP_TABLE object mptable.o end
if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
makerule ./failover.E
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./auto.E
# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(MAINBOARD)/auto.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(MAINBOARD)/auto.c ../romcc"
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -58,7 +58,7 @@ end
mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end

120
src/mainboard/asus/p2b-ds/Options.lb
View File

@@ -18,89 +18,89 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
uses HAVE_MP_TABLE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_ROM_PAYLOAD
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ARCH
uses CONFIG_FALLBACK_SIZE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses PAYLOAD_SIZE
uses _ROMBASE
uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
uses CROSS_COMPILE
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_RAMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses CONFIG_SMP
uses CONFIG_MAX_CPUS
uses CONFIG_IOAPIC
default ROM_SIZE = 256 * 1024
default HAVE_FALLBACK_BOOT = 1
default HAVE_MP_TABLE = 1
default HAVE_HARD_RESET = 0
default CONFIG_ROM_SIZE = 256 * 1024
default CONFIG_HAVE_FALLBACK_BOOT = 1
default CONFIG_HAVE_MP_TABLE = 1
default CONFIG_HAVE_HARD_RESET = 0
default CONFIG_UDELAY_TSC = 1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
default HAVE_PIRQ_TABLE = 1
default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
default ROM_IMAGE_SIZE = 64 * 1024
default FALLBACK_SIZE = 128 * 1024
default STACK_SIZE = 8 * 1024
default HEAP_SIZE = 16 * 1024
default HAVE_OPTION_TABLE = 0
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0
default _RAMBASE = 0x00004000
default CONFIG_HAVE_PIRQ_TABLE = 1
default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
default CONFIG_FALLBACK_SIZE = 128 * 1024
default CONFIG_STACK_SIZE = 8 * 1024
default CONFIG_HEAP_SIZE = 16 * 1024
default CONFIG_HAVE_OPTION_TABLE = 0
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
default CONFIG_USE_OPTION_TABLE = 0
default CONFIG_RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
default CONFIG_SMP = 1
default CONFIG_MAX_CPUS = 2
default CONFIG_IOAPIC = 1
default CROSS_COMPILE = ""
default CC = "$(CROSS_COMPILE)gcc -m32"
default HOSTCC = "gcc"
default CONFIG_CROSS_COMPILE = ""
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
default CONFIG_HOSTCC = "gcc"
default CONFIG_CONSOLE_SERIAL8250 = 1
default TTYS0_BAUD = 115200
default TTYS0_BASE = 0x3f8
default TTYS0_LCS = 0x3 # 8n1
default DEFAULT_CONSOLE_LOGLEVEL = 9
default MAXIMUM_CONSOLE_LOGLEVEL = 9
default CONFIG_TTYS0_BAUD = 115200
default CONFIG_TTYS0_BASE = 0x3f8
default CONFIG_TTYS0_LCS = 0x3 # 8n1
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
default CONFIG_CONSOLE_VGA = 1
default CONFIG_PCI_ROM_RUN = 1

2
src/mainboard/asus/p2b-ds/auto.c
View File

@@ -57,7 +57,7 @@ static void main(unsigned long bist)
enable_lapic(); /* FIXME? */
}
w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE);
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
report_bist_failure(bist);

2
src/mainboard/asus/p2b-ds/irq_tables.c
View File

@@ -23,7 +23,7 @@
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE,
PIRQ_VERSION,
32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
(0x04 << 3) | 0x0, /* Interrupt router device */
0, /* IRQs devoted exclusively to PCI usage */

30
src/mainboard/asus/p2b-f/Config.lb
View File

@@ -18,38 +18,38 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
if CONFIG_HAVE_PIRQ_TABLE
object irq_tables.o
end
makerule ./failover.E
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./auto.E
# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(MAINBOARD)/auto.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(MAINBOARD)/auto.c ../romcc"
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -59,7 +59,7 @@ end
mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end

120
src/mainboard/asus/p2b-f/Options.lb
View File

@@ -18,82 +18,82 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
uses HAVE_MP_TABLE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_ROM_PAYLOAD
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ARCH
uses CONFIG_FALLBACK_SIZE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses PAYLOAD_SIZE
uses _ROMBASE
uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
uses CROSS_COMPILE
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_RAMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
default ROM_SIZE = 256 * 1024
default HAVE_FALLBACK_BOOT = 1
default HAVE_MP_TABLE = 0
default HAVE_HARD_RESET = 0
default CONFIG_ROM_SIZE = 256 * 1024
default CONFIG_HAVE_FALLBACK_BOOT = 1
default CONFIG_HAVE_MP_TABLE = 0
default CONFIG_HAVE_HARD_RESET = 0
default CONFIG_UDELAY_TSC = 1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
default HAVE_PIRQ_TABLE = 1
default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
default ROM_IMAGE_SIZE = 64 * 1024
default FALLBACK_SIZE = 128 * 1024
default STACK_SIZE = 8 * 1024
default HEAP_SIZE = 16 * 1024
default HAVE_OPTION_TABLE = 0
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0
default _RAMBASE = 0x00004000
default CONFIG_HAVE_PIRQ_TABLE = 1
default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
default CONFIG_FALLBACK_SIZE = 128 * 1024
default CONFIG_STACK_SIZE = 8 * 1024
default CONFIG_HEAP_SIZE = 16 * 1024
default CONFIG_HAVE_OPTION_TABLE = 0
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
default CONFIG_USE_OPTION_TABLE = 0
default CONFIG_RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
default CROSS_COMPILE = ""
default CC = "$(CROSS_COMPILE)gcc -m32"
default HOSTCC = "gcc"
default CONFIG_CROSS_COMPILE = ""
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
default CONFIG_HOSTCC = "gcc"
default CONFIG_CONSOLE_SERIAL8250 = 1
default TTYS0_BAUD = 115200
default TTYS0_BASE = 0x3f8
default TTYS0_LCS = 0x3 # 8n1
default DEFAULT_CONSOLE_LOGLEVEL = 9
default MAXIMUM_CONSOLE_LOGLEVEL = 9
default CONFIG_TTYS0_BAUD = 115200
default CONFIG_TTYS0_BASE = 0x3f8
default CONFIG_TTYS0_LCS = 0x3 # 8n1
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
default CONFIG_CONSOLE_VGA = 1
default CONFIG_PCI_ROM_RUN = 1

2
src/mainboard/asus/p2b-f/auto.c
View File

@@ -57,7 +57,7 @@ static void main(unsigned long bist)
early_mtrr_init();
/* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */
w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE);
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
report_bist_failure(bist);

2
src/mainboard/asus/p2b-f/irq_tables.c
View File

@@ -23,7 +23,7 @@
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE,
PIRQ_VERSION,
32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
(0x04 << 3) | 0x0, /* Interrupt router device */
0, /* IRQs devoted exclusively to PCI usage */

30
src/mainboard/asus/p2b/Config.lb
View File

@@ -18,38 +18,38 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
if CONFIG_HAVE_PIRQ_TABLE
object irq_tables.o
end
makerule ./failover.E
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./auto.E
# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(MAINBOARD)/auto.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(MAINBOARD)/auto.c ../romcc"
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -59,7 +59,7 @@ end
mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end

120
src/mainboard/asus/p2b/Options.lb
View File

@@ -18,83 +18,83 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
uses HAVE_MP_TABLE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_ROM_PAYLOAD
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ARCH
uses CONFIG_FALLBACK_SIZE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses PAYLOAD_SIZE
uses _ROMBASE
uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
uses CROSS_COMPILE
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_RAMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
default ROM_SIZE = 256 * 1024
default HAVE_FALLBACK_BOOT = 1
default HAVE_MP_TABLE = 0
default HAVE_HARD_RESET = 0
default CONFIG_ROM_SIZE = 256 * 1024
default CONFIG_HAVE_FALLBACK_BOOT = 1
default CONFIG_HAVE_MP_TABLE = 0
default CONFIG_HAVE_HARD_RESET = 0
default CONFIG_UDELAY_TSC = 1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
default HAVE_PIRQ_TABLE = 1
default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
default ROM_IMAGE_SIZE = 64 * 1024
default FALLBACK_SIZE = 128 * 1024
default STACK_SIZE = 8 * 1024
default HEAP_SIZE = 16 * 1024
default HAVE_OPTION_TABLE = 0
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0
default _RAMBASE = 0x00004000
default CONFIG_HAVE_PIRQ_TABLE = 1
default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
default CONFIG_FALLBACK_SIZE = 128 * 1024
default CONFIG_STACK_SIZE = 8 * 1024
default CONFIG_HEAP_SIZE = 16 * 1024
default CONFIG_HAVE_OPTION_TABLE = 0
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
default CONFIG_USE_OPTION_TABLE = 0
default CONFIG_RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
default CROSS_COMPILE = ""
default CC = "$(CROSS_COMPILE)gcc -m32"
default HOSTCC = "gcc"
default CONFIG_CROSS_COMPILE = ""
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
default CONFIG_HOSTCC = "gcc"
default CONFIG_CONSOLE_SERIAL8250 = 1
default TTYS0_BAUD = 115200
default TTYS0_BASE = 0x3f8
default TTYS0_LCS = 0x3 # 8n1
default DEFAULT_CONSOLE_LOGLEVEL = 9
default MAXIMUM_CONSOLE_LOGLEVEL = 9
default CONFIG_TTYS0_BAUD = 115200
default CONFIG_TTYS0_BASE = 0x3f8
default CONFIG_TTYS0_LCS = 0x3 # 8n1
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
default CONFIG_CONSOLE_VGA = 1
default CONFIG_PCI_ROM_RUN = 1

2
src/mainboard/asus/p2b/auto.c
View File

@@ -54,7 +54,7 @@ static void main(unsigned long bist)
if (bist == 0)
early_mtrr_init();
w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE);
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
report_bist_failure(bist);

2
src/mainboard/asus/p2b/irq_tables.c
View File

@@ -23,7 +23,7 @@
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE,
PIRQ_VERSION,
32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
(0x04 << 3) | 0x0, /* Interrupt router device */
0, /* IRQs devoted exclusively to PCI usage */

30
src/mainboard/asus/p3b-f/Config.lb
View File

@@ -18,38 +18,38 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
if CONFIG_HAVE_PIRQ_TABLE
object irq_tables.o
end
makerule ./failover.E
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./auto.E
# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(MAINBOARD)/auto.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(MAINBOARD)/auto.c ../romcc"
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -59,7 +59,7 @@ end
mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end

120
src/mainboard/asus/p3b-f/Options.lb
View File

@@ -18,82 +18,82 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
uses HAVE_MP_TABLE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_ROM_PAYLOAD
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ARCH
uses CONFIG_FALLBACK_SIZE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses PAYLOAD_SIZE
uses _ROMBASE
uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
uses CROSS_COMPILE
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_ROMBASE
uses CONFIG_RAMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
default ROM_SIZE = 256 * 1024
default HAVE_FALLBACK_BOOT = 1
default HAVE_MP_TABLE = 0
default HAVE_HARD_RESET = 0
default CONFIG_ROM_SIZE = 256 * 1024
default CONFIG_HAVE_FALLBACK_BOOT = 1
default CONFIG_HAVE_MP_TABLE = 0
default CONFIG_HAVE_HARD_RESET = 0
default CONFIG_UDELAY_TSC = 1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
default HAVE_PIRQ_TABLE = 1
default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
default ROM_IMAGE_SIZE = 64 * 1024
default FALLBACK_SIZE = 128 * 1024
default STACK_SIZE = 8 * 1024
default HEAP_SIZE = 16 * 1024
default HAVE_OPTION_TABLE = 0
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0
default _RAMBASE = 0x00004000
default CONFIG_HAVE_PIRQ_TABLE = 1
default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
default CONFIG_FALLBACK_SIZE = 128 * 1024
default CONFIG_STACK_SIZE = 8 * 1024
default CONFIG_HEAP_SIZE = 16 * 1024
default CONFIG_HAVE_OPTION_TABLE = 0
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
default CONFIG_USE_OPTION_TABLE = 0
default CONFIG_RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
default CROSS_COMPILE = ""
default CC = "$(CROSS_COMPILE)gcc -m32"
default HOSTCC = "gcc"
default CONFIG_CROSS_COMPILE = ""
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
default CONFIG_HOSTCC = "gcc"
default CONFIG_CONSOLE_SERIAL8250 = 1
default TTYS0_BAUD = 115200
default TTYS0_BASE = 0x3f8
default TTYS0_LCS = 0x3 # 8n1
default DEFAULT_CONSOLE_LOGLEVEL = 9
default MAXIMUM_CONSOLE_LOGLEVEL = 9
default CONFIG_TTYS0_BAUD = 115200
default CONFIG_TTYS0_BASE = 0x3f8
default CONFIG_TTYS0_LCS = 0x3 # 8n1
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
default CONFIG_CONSOLE_VGA = 1
default CONFIG_PCI_ROM_RUN = 1

2
src/mainboard/asus/p3b-f/auto.c
View File

@@ -57,7 +57,7 @@ static void main(unsigned long bist)
early_mtrr_init();
/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE);
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
report_bist_failure(bist);

2
src/mainboard/asus/p3b-f/irq_tables.c
View File

@@ -23,7 +23,7 @@
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE,
PIRQ_VERSION,
32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
(0x04 << 3) | 0x0, /* Interrupt router device */
0, /* IRQs devoted exclusively to PCI usage */

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