sravan/system76-coreboot
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This patch unifies the use of config options in v2 to all start with CONFIG_

Browse Source 
It's basically done with the following script and some manual fixup:

VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
	find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2009-06-30 15:17:49 +00:00
committed by Stefan Reinauer
parent 9702b6bf7e
commit 0867062412
863 changed files with 14632 additions and 14632 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
targets/a-trend/atc-6220/Config.lb
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@@ -21,29 +21,29 @@
target atc-6220
mainboard a-trend/atc-6220
option ROM_SIZE = 256 * 1024
option CONFIG_ROM_SIZE = 256 * 1024
option MAINBOARD_VENDOR = "A-Trend"
option MAINBOARD_PART_NUMBER = "ATC-6220"
option CONFIG_MAINBOARD_VENDOR = "A-Trend"
option CONFIG_MAINBOARD_PART_NUMBER = "ATC-6220"
option IRQ_SLOT_COUNT = 7
option CONFIG_IRQ_SLOT_COUNT = 7
option DEFAULT_CONSOLE_LOGLEVEL = 9
option MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_CONSOLE_VGA = 1
option CONFIG_PCI_ROM_RUN = 1
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 0
option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option CONFIG_USE_FALLBACK_IMAGE = 1
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

18
targets/a-trend/atc-6240/Config.lb
View File

@@ -21,29 +21,29 @@
target atc-6240
mainboard a-trend/atc-6240
option ROM_SIZE = 256 * 1024
option CONFIG_ROM_SIZE = 256 * 1024
option MAINBOARD_VENDOR = "A-Trend"
option MAINBOARD_PART_NUMBER = "ATC-6240"
option CONFIG_MAINBOARD_VENDOR = "A-Trend"
option CONFIG_MAINBOARD_PART_NUMBER = "ATC-6240"
option IRQ_SLOT_COUNT = 7
option CONFIG_IRQ_SLOT_COUNT = 7
option DEFAULT_CONSOLE_LOGLEVEL = 9
option MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_CONSOLE_VGA = 1
option CONFIG_PCI_ROM_RUN = 1
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 0
option COREBOOT_EXTRA_VERSION = ".0Normal"
payload ../payload.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option CONFIG_USE_FALLBACK_IMAGE = 1
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload ../payload.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

18
targets/abit/be6-ii_v2_0/Config.lb
View File

@@ -21,29 +21,29 @@
target be6-ii_v2_0
mainboard abit/be6-ii_v2_0
option ROM_SIZE = 256 * 1024
option CONFIG_ROM_SIZE = 256 * 1024
option MAINBOARD_VENDOR = "Abit"
option MAINBOARD_PART_NUMBER = "BE6-II V2.0"
option CONFIG_MAINBOARD_VENDOR = "Abit"
option CONFIG_MAINBOARD_PART_NUMBER = "BE6-II V2.0"
option IRQ_SLOT_COUNT = 9
option CONFIG_IRQ_SLOT_COUNT = 9
option DEFAULT_CONSOLE_LOGLEVEL = 9
option MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_CONSOLE_VGA = 1
option CONFIG_PCI_ROM_RUN = 1
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 0
option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option CONFIG_USE_FALLBACK_IMAGE = 1
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

18
targets/advantech/pcm-5820/Config.lb
View File

@@ -21,12 +21,12 @@
target pcm-5820
mainboard advantech/pcm-5820
option ROM_SIZE = 256 * 1024
option CONFIG_ROM_SIZE = 256 * 1024
option MAINBOARD_VENDOR = "Advantech"
option MAINBOARD_PART_NUMBER = "PCM-5820"
option CONFIG_MAINBOARD_VENDOR = "Advantech"
option CONFIG_MAINBOARD_PART_NUMBER = "PCM-5820"
option IRQ_SLOT_COUNT = 2
option CONFIG_IRQ_SLOT_COUNT = 2
## Enable VGA with a splash screen (only 640x480 to run on most monitors).
## We want to support up to 1024x768@16 so we need 2MiB video memory.
@@ -36,19 +36,19 @@ option CONFIG_GX1_VIDEOMODE = 0
option CONFIG_SPLASH_GRAPHIC = 1
option CONFIG_VIDEO_MB = 2
option DEFAULT_CONSOLE_LOGLEVEL = 9
option MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 0
option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option CONFIG_USE_FALLBACK_IMAGE = 1
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

20
targets/amd/db800/Config.lb
View File

@@ -30,20 +30,20 @@ option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
option CONFIG_COMPRESSED_PAYLOAD_LZMA=0
# Leave 36k for VSA.
option ROM_SIZE=512*1024-36*1024
# option ROM_SIZE=256*1024-36*1024
option FALLBACK_SIZE=ROM_SIZE
option CONFIG_ROM_SIZE=512*1024-36*1024
# option CONFIG_ROM_SIZE=256*1024-36*1024
option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE
option DEFAULT_CONSOLE_LOGLEVEL = 9
option MAXIMUM_CONSOLE_LOGLEVEL = 9
# option DEFAULT_CONSOLE_LOGLEVEL = 4
# option MAXIMUM_CONSOLE_LOGLEVEL = 4
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
# option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 4
# option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 4
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=64*1024
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=64*1024
option COREBOOT_EXTRA_VERSION=".0Fallback"
payload ../payload.elf
end
buildrom ./coreboot.rom ROM_SIZE "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"

20
targets/amd/dbm690t/Config-abuild.lb
View File

@@ -4,27 +4,27 @@ target VENDOR_MAINBOARD
mainboard VENDOR/MAINBOARD
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
option CONFIG_HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
__LOGLEVEL__
option ROM_SIZE=1024*1024
option CONFIG_ROM_SIZE=1024*1024
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x20000
option CONFIG_XIP_ROM_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-normal"
payload __PAYLOAD__
end
romimage "failover"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x20000
option CONFIG_XIP_ROM_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-failover"
payload __PAYLOAD__
end
buildrom ./coreboot.rom ROM_SIZE "normal" "failover"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "failover"

16
targets/amd/dbm690t/Config.lb
View File

@@ -4,18 +4,18 @@ target dbm690t
mainboard amd/dbm690t
romimage "normal"
option ROM_SIZE = 1024*1024 - 55808
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
option CONFIG_ROM_SIZE = 1024*1024 - 55808
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x20000
option CONFIG_XIP_ROM_SIZE=0x20000
payload ../payload.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x20000
option CONFIG_XIP_ROM_SIZE=0x20000
payload ../payload.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

20
targets/amd/norwich/Config.lb
View File

@@ -30,20 +30,20 @@ option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
option CONFIG_COMPRESSED_PAYLOAD_LZMA=0
option ROM_SIZE=512*1024-36*1024
#option ROM_SIZE=256*1024-36*1024
option FALLBACK_SIZE=ROM_SIZE
option CONFIG_ROM_SIZE=512*1024-36*1024
#option CONFIG_ROM_SIZE=256*1024-36*1024
option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE
option DEFAULT_CONSOLE_LOGLEVEL = 9
option MAXIMUM_CONSOLE_LOGLEVEL = 9
#option DEFAULT_CONSOLE_LOGLEVEL = 4
#option MAXIMUM_CONSOLE_LOGLEVEL = 4
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
#option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 4
#option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 4
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=64*1024
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=64*1024
option COREBOOT_EXTRA_VERSION=".0Fallback"
payload ../payload.elf
end
buildrom ./coreboot.rom ROM_SIZE "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"

20
targets/amd/pistachio/Config-abuild.lb
View File

@@ -4,27 +4,27 @@ target VENDOR_MAINBOARD
mainboard VENDOR/MAINBOARD
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
option CONFIG_HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
__LOGLEVEL__
option ROM_SIZE=1024*1024
option CONFIG_ROM_SIZE=1024*1024
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x20000
option CONFIG_XIP_ROM_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-normal"
payload __PAYLOAD__
end
romimage "failover"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x20000
option CONFIG_XIP_ROM_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-failover"
payload __PAYLOAD__
end
buildrom ./coreboot.rom ROM_SIZE "normal" "failover"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "failover"

16
targets/amd/pistachio/Config.lb
View File

@@ -4,18 +4,18 @@ target pistachio
mainboard amd/pistachio
romimage "normal"
option ROM_SIZE = 1024*1024 - 55808
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
option CONFIG_ROM_SIZE = 1024*1024 - 55808
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x20000
option CONFIG_XIP_ROM_SIZE=0x20000
payload ../payload.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x20000
option CONFIG_XIP_ROM_SIZE=0x20000
payload ../payload.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

12
targets/amd/rumba/Config.lb
View File

@@ -4,11 +4,11 @@
target rumba
mainboard amd/rumba
option ROM_SIZE=256*1024
option CONFIG_ROM_SIZE=256*1024
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x10000
option COREBOOT_EXTRA_VERSION=".0Normal"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
@@ -19,8 +19,8 @@ romimage "normal"
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x10000
option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
@@ -30,4 +30,4 @@ romimage "fallback"
payload /tmp/filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

18
targets/amd/rumba/Config.nofallback.lb
View File

@@ -4,13 +4,13 @@
target rumba
mainboard amd/rumba
option ROM_SIZE=128*1024
option FALLBACK_SIZE=ROM_SIZE
#option FALLBACK_SIZE=65535
option CONFIG_ROM_SIZE=128*1024
option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE
#option CONFIG_FALLBACK_SIZE=65535
#romimage "normal"
# option USE_FALLBACK_IMAGE=0
# option ROM_IMAGE_SIZE=0x10000
# option CONFIG_USE_FALLBACK_IMAGE=0
# option CONFIG_ROM_IMAGE_SIZE=0x10000
# option COREBOOT_EXTRA_VERSION=".0Normal"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
@@ -21,8 +21,8 @@ option FALLBACK_SIZE=ROM_SIZE
#end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x10000
option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
@@ -33,6 +33,6 @@ romimage "fallback"
# payload /home/ollie/work/filo-0.4.1/filo.elf
end
#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom ROM_SIZE "fallback"
#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"

26
targets/amd/serengeti_cheetah/Config-abuild.lb
View File

@@ -4,33 +4,33 @@ target VENDOR_MAINBOARD
mainboard VENDOR/MAINBOARD
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
option CONFIG_HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
__LOGLEVEL__
romimage "normal"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
romimage "failover"
option USE_FAILOVER_IMAGE=1
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
option CONFIG_USE_FAILOVER_IMAGE=1
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"

18
targets/amd/serengeti_cheetah/Config-lab.lb
View File

@@ -5,20 +5,20 @@
target serengeti_cheetah
mainboard amd/serengeti_cheetah
option ROM_SIZE = 0x100000
option USE_FAILOVER_IMAGE=0
option HAVE_FAILOVER_BOOT=0
option FAILOVER_SIZE=0
option CONFIG_ROM_SIZE = 0x100000
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_HAVE_FAILOVER_BOOT=0
option CONFIG_FAILOVER_SIZE=0
romimage "fallback"
option CONFIG_PRECOMPRESSED_PAYLOAD=1
option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
option FALLBACK_SIZE=ROM_SIZE
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x1a000
option XIP_ROM_SIZE=0x40000
option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x1a000
option CONFIG_XIP_ROM_SIZE=0x40000
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
payload ../payload.elf.lzma
end
buildrom ./coreboot.rom ROM_SIZE "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"

46
targets/amd/serengeti_cheetah/Config.lb
View File

@@ -8,18 +8,18 @@ mainboard amd/serengeti_cheetah
# serengeti_leopard
romimage "normal"
# 48K for SCSI FW
# option ROM_SIZE = 475136
# option CONFIG_ROM_SIZE = 475136
# 48K for SCSI FW and 48K for ATI ROM
# option ROM_SIZE = 425984
# option CONFIG_ROM_SIZE = 425984
# 64K for Etherboot
# option ROM_SIZE = 458752
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=0
# option ROM_IMAGE_SIZE=0x13800
# option ROM_IMAGE_SIZE=0x18800
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
# option CONFIG_ROM_SIZE = 458752
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=0
# option CONFIG_ROM_IMAGE_SIZE=0x13800
# option CONFIG_ROM_IMAGE_SIZE=0x18800
option CONFIG_ROM_IMAGE_SIZE=0x20000
# option CONFIG_ROM_IMAGE_SIZE=0x15800
option CONFIG_XIP_ROM_SIZE=0x40000
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
@@ -42,13 +42,13 @@ romimage "normal"
end
romimage "fallback"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=1
# option ROM_IMAGE_SIZE=0x13800
# option ROM_IMAGE_SIZE=0x19800
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=1
# option CONFIG_ROM_IMAGE_SIZE=0x13800
# option CONFIG_ROM_IMAGE_SIZE=0x19800
option CONFIG_ROM_IMAGE_SIZE=0x20000
# option CONFIG_ROM_IMAGE_SIZE=0x15800
option CONFIG_XIP_ROM_SIZE=0x40000
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
@@ -75,13 +75,13 @@ romimage "fallback"
end
romimage "failover"
option USE_FAILOVER_IMAGE=1
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
option CONFIG_USE_FAILOVER_IMAGE=1
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

20
targets/amd/serengeti_cheetah_fam10/Config-abuild.lb
View File

@@ -4,27 +4,27 @@ target VENDOR_MAINBOARD
mainboard VENDOR/MAINBOARD
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
option CONFIG_HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
__LOGLEVEL__
option ROM_SIZE=1024*1024
option CONFIG_ROM_SIZE=1024*1024
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x3f000
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x3f000
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
romimage "failover"
option USE_FAILOVER_IMAGE=1
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
option CONFIG_USE_FAILOVER_IMAGE=1
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
option COREBOOT_EXTRA_VERSION=".0-failover"
end
buildrom ./coreboot.rom ROM_SIZE "fallback" "failover"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover"

26
targets/amd/serengeti_cheetah_fam10/Config-lab.lb
View File

@@ -25,30 +25,30 @@
target serengeti_cheetah_fam10
mainboard amd/serengeti_cheetah_fam10
# Request this level of debugging output
option DEFAULT_CONSOLE_LOGLEVEL=9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
# At a maximum only compile in this level of debugging
option MAXIMUM_CONSOLE_LOGLEVEL=9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
# 1024KB ROM
option ROM_SIZE=1024*1024
option FALLBACK_SIZE=ROM_SIZE-FAILOVER_SIZE
option CONFIG_ROM_SIZE=1024*1024
option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE-CONFIG_FAILOVER_SIZE
romimage "fallback"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x30000
option XIP_ROM_SIZE=0x40000
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x30000
option CONFIG_XIP_ROM_SIZE=0x40000
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
payload ../payload.elf.lzma
end
romimage "failover"
option USE_FAILOVER_IMAGE=1
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
option CONFIG_USE_FAILOVER_IMAGE=1
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
end
buildrom ./coreboot.rom ROM_SIZE "fallback" "failover"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover"

44
targets/amd/serengeti_cheetah_fam10/Config.lb
View File

@@ -25,46 +25,46 @@
target serengeti_cheetah_fam10
mainboard amd/serengeti_cheetah_fam10
# Request this level of debugging output
option DEFAULT_CONSOLE_LOGLEVEL=9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
# At a maximum only compile in this level of debugging
option MAXIMUM_CONSOLE_LOGLEVEL=9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
# 512KB ROM
option ROM_SIZE=1024*1024
option CONFIG_ROM_SIZE=1024*1024
# Cheetah Family 10
#romimage "normal"
# 1MB ROM
# option ROM_SIZE = 0x100000
# option USE_FAILOVER_IMAGE=0
# option USE_FALLBACK_IMAGE=0
# option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x30000
# option XIP_ROM_SIZE=0x40000
# option CONFIG_ROM_SIZE = 0x100000
# option CONFIG_USE_FAILOVER_IMAGE=0
# option CONFIG_USE_FALLBACK_IMAGE=0
# option CONFIG_ROM_IMAGE_SIZE=0x20000
# option CONFIG_ROM_IMAGE_SIZE=0x30000
# option CONFIG_XIP_ROM_SIZE=0x40000
# option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../payload.elf
#end
romimage "fallback"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=1
# option ROM_IMAGE_SIZE=0x13800
# option ROM_IMAGE_SIZE=0x19800
option ROM_IMAGE_SIZE=0x7f000
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x80000
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=1
# option CONFIG_ROM_IMAGE_SIZE=0x13800
# option CONFIG_ROM_IMAGE_SIZE=0x19800
option CONFIG_ROM_IMAGE_SIZE=0x7f000
# option CONFIG_ROM_IMAGE_SIZE=0x15800
option CONFIG_XIP_ROM_SIZE=0x80000
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
payload ../payload.elf
end
romimage "failover"
option USE_FAILOVER_IMAGE=1
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
option CONFIG_USE_FAILOVER_IMAGE=1
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
end
#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
buildrom ./coreboot.rom ROM_SIZE "fallback" "failover"
#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover"

16
targets/arima/hdama/Config-abuild.lb
View File

@@ -4,25 +4,25 @@ target VENDOR_MAINBOARD
mainboard VENDOR/MAINBOARD
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
option CONFIG_HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
__LOGLEVEL__
option ROM_SIZE=512*1024
option CONFIG_ROM_SIZE=512*1024
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

80
targets/arima/hdama/Config.kernelimage.lb
View File

@@ -6,79 +6,79 @@ loadoptions
target hdama
uses ARCH
uses CONFIG_ARCH
uses CONFIG_COMPRESS
uses CONFIG_IOAPIC
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_UDELAY_TSC
uses CPU_FIXUP
uses FALLBACK_SIZE
uses HAVE_FALLBACK_BOOT
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses HAVE_HARD_RESET
uses CONFIG_FALLBACK_SIZE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_HAVE_HARD_RESET
uses i586
uses i686
uses INTEL_PPRO_MTRR
uses HEAP_SIZE
uses IRQ_SLOT_COUNT
uses CONFIG_INTEL_PPRO_MTRR
uses CONFIG_HEAP_SIZE
uses CONFIG_IRQ_SLOT_COUNT
uses k7
uses k8
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_SMP
uses CONFIG_MAX_CPUS
uses MEMORY_HOLE
uses PAYLOAD_SIZE
uses _RAMBASE
uses _ROMBASE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_OFFSET
uses ROM_SECTION_SIZE
uses ROM_SIZE
uses STACK_SIZE
uses USE_FALLBACK_IMAGE
uses USE_OPTION_TABLE
uses HAVE_OPTION_TABLE
uses MAXIMUM_CONSOLE_LOGLEVEL
uses DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MEMORY_HOLE
uses CONFIG_PAYLOAD_SIZE
uses CONFIG_RAMBASE
uses CONFIG_ROMBASE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_STACK_SIZE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses MAINBOARD
uses CONFIG_MAINBOARD
uses CONFIG_CHIP_CONFIGURE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses COREBOOT_EXTRA_VERSION
option CONFIG_CHIP_CONFIGURE=1
option MAXIMUM_CONSOLE_LOGLEVEL=8
option DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_CONSOLE_SERIAL8250=1
option CPU_FIXUP=1
option CONFIG_UDELAY_TSC=0
option i686=1
option i586=1
option INTEL_PPRO_MTRR=1
option CONFIG_INTEL_PPRO_MTRR=1
option k7=1
option k8=1
option ROM_SIZE=1024*1024
option CONFIG_ROM_SIZE=1024*1024
option HAVE_OPTION_TABLE=1
option CONFIG_HAVE_OPTION_TABLE=1
option CONFIG_ROM_PAYLOAD=1
option HAVE_FALLBACK_BOOT=1
option CONFIG_HAVE_FALLBACK_BOOT=1
###
### Compute the location and size of where this firmware image
### (coreboot plus bootloader) will live in the boot rom chip.
###
option FALLBACK_SIZE=ROM_SIZE
option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE
## Coreboot C code runs at this location in RAM
option _RAMBASE=0x00004000
option CONFIG_RAMBASE=0x00004000
#
###
@@ -89,9 +89,9 @@ option _RAMBASE=0x00004000
#
# Arima hdama
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
# option ROM_SECTION_SIZE=0x100000
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x10000
# option CONFIG_ROM_SECTION_SIZE=0x100000
option COREBOOT_EXTRA_VERSION=".0Fallback"
mainboard arima/hdama
# payload ../../../../tg3--ide_disk.zelf
@@ -100,4 +100,4 @@ romimage "fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
end
buildrom ./coreboot.rom ROM_SIZE "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"

12
targets/arima/hdama/Config.lb
View File

@@ -6,23 +6,23 @@
target hdama
mainboard arima/hdama
option ROM_SIZE=512*1024-36*1024
option CONFIG_ROM_SIZE=512*1024-36*1024
# Arima hdama
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0Normal"
payload ../../../payloads/filo.elf
# payload /etc/hosts
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0Fallback"
payload ../../../payloads/filo.elf
# payload /etc/hosts
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

20
targets/artecgroup/dbe61/Config.lb
View File

@@ -9,26 +9,26 @@ option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
option CONFIG_COMPRESSED_PAYLOAD_LZMA=0
## ROM_SIZE is the total number of bytes allocated for coreboot use
## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
## (normal AND fallback images and payloads).
## leave 36k for vsa and 32K for video ROM
#option ROM_SIZE = 1024*256 - 36*1024 - 32 * 1024
#option CONFIG_ROM_SIZE = 1024*256 - 36*1024 - 32 * 1024
#No VGA for now
option ROM_SIZE = 1024*512 - 36*1024
option CONFIG_ROM_SIZE = 1024*512 - 36*1024
# ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
# CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
## not including any payload.
option ROM_IMAGE_SIZE=64*1024
option CONFIG_ROM_IMAGE_SIZE=64*1024
option FALLBACK_SIZE = ROM_SIZE
option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
option DEFAULT_CONSOLE_LOGLEVEL = 9
option MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option CONFIG_USE_FALLBACK_IMAGE=1
option COREBOOT_EXTRA_VERSION=".0Fallback"
payload ../payload.elf
end
buildrom ./coreboot.rom ROM_SIZE "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"

18
targets/asi/mb_5blgp/Config.lb
View File

@@ -21,12 +21,12 @@
target mb_5blgp
mainboard asi/mb_5blgp
option ROM_SIZE = 256 * 1024
option CONFIG_ROM_SIZE = 256 * 1024
option MAINBOARD_VENDOR = "ASI"
option MAINBOARD_PART_NUMBER = "MB-5BLGP"
option CONFIG_MAINBOARD_VENDOR = "ASI"
option CONFIG_MAINBOARD_PART_NUMBER = "MB-5BLGP"
option IRQ_SLOT_COUNT = 3
option CONFIG_IRQ_SLOT_COUNT = 3
## Enable VGA with a splash screen (only 640x480 to run on most monitors).
## We want to support up to 1024x768@16 so we need 2MiB video memory.
@@ -36,19 +36,19 @@ option CONFIG_GX1_VIDEOMODE = 0
option CONFIG_SPLASH_GRAPHIC = 1
option CONFIG_VIDEO_MB = 2
option DEFAULT_CONSOLE_LOGLEVEL = 9
option MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 0
option COREBOOT_EXTRA_VERSION = ".0Normal"
payload ../payload.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option CONFIG_USE_FALLBACK_IMAGE = 1
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload ../payload.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

18
targets/asi/mb_5blmp/Config.lb
View File

@@ -21,23 +21,23 @@
target mb_5blmp
mainboard asi/mb_5blmp
option ROM_SIZE = (256 * 1024)
# option ROM_SIZE = (256 * 1024) - (32 * 1024)
# option FALLBACK_SIZE = (256 * 1024) - (32 * 1024)
option CONFIG_ROM_SIZE = (256 * 1024)
# option CONFIG_ROM_SIZE = (256 * 1024) - (32 * 1024)
# option CONFIG_FALLBACK_SIZE = (256 * 1024) - (32 * 1024)
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option ROM_IMAGE_SIZE = 64 * 1024
option CONFIG_USE_FALLBACK_IMAGE = 0
option CONFIG_ROM_IMAGE_SIZE = 64 * 1024
option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option ROM_IMAGE_SIZE = 64 * 1024
option CONFIG_USE_FALLBACK_IMAGE = 1
option CONFIG_ROM_IMAGE_SIZE = 64 * 1024
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
# buildrom ./coreboot.rom ROM_SIZE "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
# buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"

26
targets/asus/a8n_e/Config-abuild.lb
View File

@@ -4,33 +4,33 @@ target VENDOR_MAINBOARD
mainboard VENDOR/MAINBOARD
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
option CONFIG_HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
__LOGLEVEL__
romimage "normal"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
romimage "failover"
option USE_FAILOVER_IMAGE=1
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
option CONFIG_USE_FAILOVER_IMAGE=1
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"

28
targets/asus/a8n_e/Config.lb
View File

@@ -23,30 +23,30 @@ target asus_a8n_e
mainboard asus/a8n_e
romimage "normal"
option USE_FAILOVER_IMAGE = 0
option USE_FALLBACK_IMAGE = 0
option ROM_IMAGE_SIZE = 128 * 1024
option XIP_ROM_SIZE = 128 * 1024
option CONFIG_USE_FAILOVER_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 0
option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
option CONFIG_XIP_ROM_SIZE = 128 * 1024
option COREBOOT_EXTRA_VERSION = "_Normal"
payload ../payload.elf
end
romimage "fallback"
option USE_FAILOVER_IMAGE = 0
option USE_FALLBACK_IMAGE = 1
option ROM_IMAGE_SIZE = 128 * 1024
option XIP_ROM_SIZE = 128 * 1024
option CONFIG_USE_FAILOVER_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 1
option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
option CONFIG_XIP_ROM_SIZE = 128 * 1024
option COREBOOT_EXTRA_VERSION = "_Fallback"
payload ../payload.elf
end
romimage "failover"
option USE_FAILOVER_IMAGE = 1
option USE_FALLBACK_IMAGE = 0
option ROM_IMAGE_SIZE = FAILOVER_SIZE
option XIP_ROM_SIZE = FAILOVER_SIZE
option CONFIG_USE_FAILOVER_IMAGE = 1
option CONFIG_USE_FALLBACK_IMAGE = 0
option CONFIG_ROM_IMAGE_SIZE = CONFIG_FAILOVER_SIZE
option CONFIG_XIP_ROM_SIZE = CONFIG_FAILOVER_SIZE
option COREBOOT_EXTRA_VERSION = "_Failover"
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
# buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
# buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

12
targets/asus/a8v-e_se/Config.lb
View File

@@ -21,18 +21,18 @@ target asus_a8v-e_se
mainboard asus/a8v-e_se
romimage "normal"
option ROM_SIZE = 512 * 1024
option USE_FALLBACK_IMAGE = 0
option ROM_IMAGE_SIZE = 128 * 1024
option CONFIG_ROM_SIZE = 512 * 1024
option CONFIG_USE_FALLBACK_IMAGE = 0
option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
option COREBOOT_EXTRA_VERSION=".0Normal"
payload ../payload.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option ROM_IMAGE_SIZE = 128 * 1024
option CONFIG_USE_FALLBACK_IMAGE = 1
option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
option COREBOOT_EXTRA_VERSION=".0Fallback"
payload ../payload.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

20
targets/asus/m2v-mx_se/Config-abuild.lb
View File

@@ -21,32 +21,32 @@ target asus_m2v-mx_se
mainboard asus/m2v-mx_se
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
option CONFIG_HOSTCC="CROSS_HOSTCC"
## ROM_SIZE is the total number of bytes allocated for coreboot use
## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
## (normal AND fallback images and payloads).
# The board comes with 512KB SPI flash (DIP8), 128KB is for coreboot binary
# 384KB of flash is for payload/roms.
option ROM_SIZE = 512 * 1024
option CONFIG_ROM_SIZE = 512 * 1024
## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
## not including any payload.
# Please note that 128KB is cached for (XIP) too
option ROM_IMAGE_SIZE = 128 * 1024
option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
## FALLBACK_SIZE is the amount of the ROM the complete fallback image
## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image
## (including payload) will use.
option FALLBACK_SIZE = ROM_SIZE
option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option CONFIG_USE_FALLBACK_IMAGE=1
payload __PAYLOAD__
end
buildrom ./coreboot.rom ROM_SIZE "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"

18
targets/asus/m2v-mx_se/Config.lb
View File

@@ -20,35 +20,35 @@
target asus_m2v-mx_se
mainboard asus/m2v-mx_se
## ROM_SIZE is the total number of bytes allocated for coreboot use
## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
## (normal AND fallback images and payloads).
# The board comes with 512KB SPI flash (DIP8), 128KB is for coreboot binary
# 384KB of flash is for payload/roms.
option ROM_SIZE = 512 * 1024
option CONFIG_ROM_SIZE = 512 * 1024
# Use following line instead if you want to use onboard VGA -
# padd the rom size to 64KB or XIP won't work, complaining about
# not good base.
#option ROM_SIZE = (512 * 1024) - (64 * 1024)
#option CONFIG_ROM_SIZE = (512 * 1024) - (64 * 1024)
## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
## not including any payload.
# Please note that 128KB is cached for (XIP) too
option ROM_IMAGE_SIZE = 128 * 1024
option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
## FALLBACK_SIZE is the amount of the ROM the complete fallback image
## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image
## (including payload) will use.
option FALLBACK_SIZE = ROM_SIZE
option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option CONFIG_USE_FALLBACK_IMAGE=1
payload ../payload.elf
end
buildrom ./coreboot.rom ROM_SIZE "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"

18
targets/asus/mew-am/Config.lb
View File

@@ -21,29 +21,29 @@
target mew-am
mainboard asus/mew-am
option ROM_SIZE = 512 * 1024
option CONFIG_ROM_SIZE = 512 * 1024
option MAINBOARD_VENDOR = "ASUS"
option MAINBOARD_PART_NUMBER = "MEW-AM"
option CONFIG_MAINBOARD_VENDOR = "ASUS"
option CONFIG_MAINBOARD_PART_NUMBER = "MEW-AM"
option IRQ_SLOT_COUNT = 8
option CONFIG_IRQ_SLOT_COUNT = 8
option DEFAULT_CONSOLE_LOGLEVEL = 9
option MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_CONSOLE_VGA = 1
option CONFIG_PCI_ROM_RUN = 1
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 0
option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option CONFIG_USE_FALLBACK_IMAGE = 1
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

14
targets/asus/mew-vm/Config.lb
View File

@@ -2,24 +2,24 @@ target mew-vm
mainboard asus/mew-vm
## Without VGA BIOS
option ROM_SIZE = 512 * 1024
option CONFIG_ROM_SIZE = 512 * 1024
## With VGA BIOS (32k)
#option ROM_SIZE = (512 * 1024) - (32 * 1024)
#option CONFIG_ROM_SIZE = (512 * 1024) - (32 * 1024)
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x10000
option COREBOOT_EXTRA_VERSION=".0Normal"
# payload /etc/hosts
payload /home/amp/filo-0.5/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x10000
option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload /etc/hosts
payload /home/amp/filo-0.5/filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

18
targets/asus/p2b-d/Config.lb
View File

@@ -21,29 +21,29 @@
target p2b-d
mainboard asus/p2b-d
option ROM_SIZE = 256 * 1024
option CONFIG_ROM_SIZE = 256 * 1024
option MAINBOARD_VENDOR = "ASUS"
option MAINBOARD_PART_NUMBER = "P2B-D"
option CONFIG_MAINBOARD_VENDOR = "ASUS"
option CONFIG_MAINBOARD_PART_NUMBER = "P2B-D"
option IRQ_SLOT_COUNT = 6
option CONFIG_IRQ_SLOT_COUNT = 6
option DEFAULT_CONSOLE_LOGLEVEL = 9
option MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_CONSOLE_VGA = 1
option CONFIG_PCI_ROM_RUN = 1
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 0
option COREBOOT_EXTRA_VERSION = ".0Normal"
payload ../payload.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option CONFIG_USE_FALLBACK_IMAGE = 1
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload ../payload.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

18
targets/asus/p2b-ds/Config.lb
View File

@@ -21,29 +21,29 @@
target p2b-ds
mainboard asus/p2b-ds
option ROM_SIZE = 256 * 1024
option CONFIG_ROM_SIZE = 256 * 1024
option MAINBOARD_VENDOR = "ASUS"
option MAINBOARD_PART_NUMBER = "P2B-DS"
option CONFIG_MAINBOARD_VENDOR = "ASUS"
option CONFIG_MAINBOARD_PART_NUMBER = "P2B-DS"
option IRQ_SLOT_COUNT = 7
option CONFIG_IRQ_SLOT_COUNT = 7
option DEFAULT_CONSOLE_LOGLEVEL = 9
option MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_CONSOLE_VGA = 1
option CONFIG_PCI_ROM_RUN = 1
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 0
option COREBOOT_EXTRA_VERSION = ".0Normal"
payload ../payload.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option CONFIG_USE_FALLBACK_IMAGE = 1
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload ../payload.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

18
targets/asus/p2b-f/Config.lb
View File

@@ -21,29 +21,29 @@
target p2b-f
mainboard asus/p2b-f
option ROM_SIZE = 256 * 1024
option CONFIG_ROM_SIZE = 256 * 1024
option MAINBOARD_VENDOR = "ASUS"
option MAINBOARD_PART_NUMBER = "P2B-F"
option CONFIG_MAINBOARD_VENDOR = "ASUS"
option CONFIG_MAINBOARD_PART_NUMBER = "P2B-F"
option IRQ_SLOT_COUNT = 7
option CONFIG_IRQ_SLOT_COUNT = 7
option DEFAULT_CONSOLE_LOGLEVEL = 9
option MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_CONSOLE_VGA = 1
option CONFIG_PCI_ROM_RUN = 1
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 0
option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option CONFIG_USE_FALLBACK_IMAGE = 1
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

18
targets/asus/p2b/Config.lb
View File

@@ -21,29 +21,29 @@
target p2b
mainboard asus/p2b
option ROM_SIZE = 256 * 1024
option CONFIG_ROM_SIZE = 256 * 1024
option MAINBOARD_VENDOR = "ASUS"
option MAINBOARD_PART_NUMBER = "P2B"
option CONFIG_MAINBOARD_VENDOR = "ASUS"
option CONFIG_MAINBOARD_PART_NUMBER = "P2B"
option IRQ_SLOT_COUNT = 6
option CONFIG_IRQ_SLOT_COUNT = 6
option DEFAULT_CONSOLE_LOGLEVEL = 9
option MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_CONSOLE_VGA = 1
option CONFIG_PCI_ROM_RUN = 1
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 0
option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option CONFIG_USE_FALLBACK_IMAGE = 1
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

18
targets/asus/p3b-f/Config.lb
View File

@@ -21,29 +21,29 @@
target p3b-f
mainboard asus/p3b-f
option ROM_SIZE = 256 * 1024
option CONFIG_ROM_SIZE = 256 * 1024
option MAINBOARD_VENDOR = "ASUS"
option MAINBOARD_PART_NUMBER = "P3B-F"
option CONFIG_MAINBOARD_VENDOR = "ASUS"
option CONFIG_MAINBOARD_PART_NUMBER = "P3B-F"
option IRQ_SLOT_COUNT = 8
option CONFIG_IRQ_SLOT_COUNT = 8
option DEFAULT_CONSOLE_LOGLEVEL = 9
option MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_CONSOLE_VGA = 1
option CONFIG_PCI_ROM_RUN = 1
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 0
option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option CONFIG_USE_FALLBACK_IMAGE = 1
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

12
targets/axus/tc320/Config.lb
View File

@@ -23,7 +23,7 @@
target tc320
mainboard axus/tc320
option ROM_SIZE = 256 * 1024
option CONFIG_ROM_SIZE = 256 * 1024
## Enable VGA with a splash screen (only 640x480 to run on most monitors).
## We want to support up to 1024x768@16 so we need 2MiB video memory.
@@ -33,19 +33,19 @@ option CONFIG_GX1_VIDEOMODE = 0
option CONFIG_SPLASH_GRAPHIC = 1
option CONFIG_VIDEO_MB = 2
option DEFAULT_CONSOLE_LOGLEVEL = 6
option MAXIMUM_CONSOLE_LOGLEVEL = 6
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 0
option COREBOOT_EXTRA_VERSION = ".0Normal"
payload ../../../../../../../images/etherboot.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option CONFIG_USE_FALLBACK_IMAGE = 1
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload ../../../../../../../images/etherboot.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

18
targets/azza/pt-6ibd/Config.lb
View File

@@ -21,29 +21,29 @@
target pt-6ibd
mainboard azza/pt-6ibd
option ROM_SIZE = 256 * 1024
option CONFIG_ROM_SIZE = 256 * 1024
option MAINBOARD_VENDOR = "AZZA"
option MAINBOARD_PART_NUMBER = "PT-6IBD"
option CONFIG_MAINBOARD_VENDOR = "AZZA"
option CONFIG_MAINBOARD_PART_NUMBER = "PT-6IBD"
option IRQ_SLOT_COUNT = 7
option CONFIG_IRQ_SLOT_COUNT = 7
option DEFAULT_CONSOLE_LOGLEVEL = 9
option MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_CONSOLE_VGA = 1
option CONFIG_PCI_ROM_RUN = 1
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 0
option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option CONFIG_USE_FALLBACK_IMAGE = 1
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

16
targets/bcom/winnet100/Config.lb
View File

@@ -23,7 +23,7 @@
target winnet100
mainboard bcom/winnet100
option ROM_SIZE = 256 * 1024
option CONFIG_ROM_SIZE = 256 * 1024
## Enable VGA with a splash screen (only 640x480 to run on most monitors).
## We want to support up to 1024x768@16 so we need 2MiB video memory.
@@ -33,21 +33,21 @@ option CONFIG_GX1_VIDEOMODE = 0
option CONFIG_SPLASH_GRAPHIC = 1
option CONFIG_VIDEO_MB = 2
option DEFAULT_CONSOLE_LOGLEVEL = 6
option MAXIMUM_CONSOLE_LOGLEVEL = 6
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option ROM_IMAGE_SIZE = 64 * 1024
option CONFIG_USE_FALLBACK_IMAGE = 0
option CONFIG_ROM_IMAGE_SIZE = 64 * 1024
option COREBOOT_EXTRA_VERSION = ".0Normal"
payload ../../../../../../../images/etherboot.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option ROM_IMAGE_SIZE = 64 * 1024
option CONFIG_USE_FALLBACK_IMAGE = 1
option CONFIG_ROM_IMAGE_SIZE = 64 * 1024
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload ../../../../../../../images/etherboot.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

12
targets/bcom/winnetp680/Config-abuild.lb
View File

@@ -4,18 +4,18 @@ target VENDOR_MAINBOARD
mainboard VENDOR/MAINBOARD
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
option CONFIG_HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
__LOGLEVEL__
option ROM_SIZE=512*1024
option CONFIG_ROM_SIZE=512*1024
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
buildrom ./coreboot.rom ROM_SIZE "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"

12
targets/bcom/winnetp680/Config.lb
View File

@@ -22,24 +22,24 @@
target bcom-winnet-p680
mainboard bcom/winnetp680
option MAXIMUM_CONSOLE_LOGLEVEL=8
option DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_CONSOLE_SERIAL8250=1
# coreboot C code runs at this location in RAM
option _RAMBASE=0x00004000
option CONFIG_RAMBASE=0x00004000
#
# If space is allotted for a VGA BIOS,
# generate the final ROM like this:
# cat vgabios bochsbios coreboot.rom > coreboot.rom.final
#
#option ROM_SIZE = (512 * 1024) - (63 * 1024) - (64 * 1024)
option ROM_SIZE = (512 * 1024)
#option CONFIG_ROM_SIZE = (512 * 1024) - (63 * 1024) - (64 * 1024)
option CONFIG_ROM_SIZE = (512 * 1024)
romimage "image"
option COREBOOT_EXTRA_VERSION = "-winnetp680"
payload ../payload.elf
end
buildrom ./coreboot.rom ROM_SIZE "image"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "image"

18
targets/biostar/m6tba/Config.lb
View File

@@ -22,29 +22,29 @@ target m6tba
mainboard biostar/m6tba
# Note: The original flash ROM chip is 128 KB.
option ROM_SIZE = 256 * 1024
option CONFIG_ROM_SIZE = 256 * 1024
option MAINBOARD_VENDOR = "Biostar"
option MAINBOARD_PART_NUMBER = "M6TBA"
option CONFIG_MAINBOARD_VENDOR = "Biostar"
option CONFIG_MAINBOARD_PART_NUMBER = "M6TBA"
option IRQ_SLOT_COUNT = 7
option CONFIG_IRQ_SLOT_COUNT = 7
option DEFAULT_CONSOLE_LOGLEVEL = 9
option MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_CONSOLE_VGA = 1
option CONFIG_PCI_ROM_RUN = 1
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 0
option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option CONFIG_USE_FALLBACK_IMAGE = 1
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

32
targets/broadcom/blast/Config.lb
View File

@@ -7,17 +7,17 @@ mainboard broadcom/blast
romimage "normal"
# 48K for ATI rom
option ROM_SIZE = 512*1024-48*1024
option CONFIG_ROM_SIZE = 512*1024-48*1024
# 48K for SCSI FW and 48K for ATI ROM
# option ROM_SIZE = 512*1024-48*1024-48*1024
# option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024
# 64K for Etherboot
# option ROM_SIZE = 512*1024-64*1024
option USE_FALLBACK_IMAGE=0
# option ROM_IMAGE_SIZE=0x13800
# option ROM_IMAGE_SIZE=0x17800
# option ROM_IMAGE_SIZE=0x15000
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
# option CONFIG_ROM_SIZE = 512*1024-64*1024
option CONFIG_USE_FALLBACK_IMAGE=0
# option CONFIG_ROM_IMAGE_SIZE=0x13800
# option CONFIG_ROM_IMAGE_SIZE=0x17800
# option CONFIG_ROM_IMAGE_SIZE=0x15000
option CONFIG_ROM_IMAGE_SIZE=0x20000
option CONFIG_XIP_ROM_SIZE=0x20000
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
@@ -37,12 +37,12 @@ romimage "normal"
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
# option ROM_IMAGE_SIZE=0x13800
# option ROM_IMAGE_SIZE=0x17800
# option ROM_IMAGE_SIZE=0x15000
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
option CONFIG_USE_FALLBACK_IMAGE=1
# option CONFIG_ROM_IMAGE_SIZE=0x13800
# option CONFIG_ROM_IMAGE_SIZE=0x17800
# option CONFIG_ROM_IMAGE_SIZE=0x15000
option CONFIG_ROM_IMAGE_SIZE=0x20000
option CONFIG_XIP_ROM_SIZE=0x20000
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
@@ -62,4 +62,4 @@ romimage "fallback"
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

18
targets/compaq/deskpro_en_sff_p600/Config.lb
View File

@@ -21,29 +21,29 @@
target deskpro_en_sff_p600
mainboard compaq/deskpro_en_sff_p600
option ROM_SIZE = 256 * 1024
option CONFIG_ROM_SIZE = 256 * 1024
option MAINBOARD_VENDOR = "Compaq"
option MAINBOARD_PART_NUMBER = "Deskpro EN SFF P600"
option CONFIG_MAINBOARD_VENDOR = "Compaq"
option CONFIG_MAINBOARD_PART_NUMBER = "Deskpro EN SFF P600"
option IRQ_SLOT_COUNT = 5
option CONFIG_IRQ_SLOT_COUNT = 5
option DEFAULT_CONSOLE_LOGLEVEL = 9
option MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_CONSOLE_VGA = 1
option CONFIG_PCI_ROM_RUN = 1
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 0
option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option CONFIG_USE_FALLBACK_IMAGE = 1
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

16
targets/dell/s1850/Config.lb
View File

@@ -1,24 +1,24 @@
target s1850
mainboard dell/s1850
option ROM_SIZE=1024*1024
option MAXIMUM_CONSOLE_LOGLEVEL=9
option DEFAULT_CONSOLE_LOGLEVEL=9
option CONFIG_ROM_SIZE=1024*1024
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x16000
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x16000
option COREBOOT_EXTRA_VERSION=".0Normal"
# payload ../../../payloads/filo.elf
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x16000
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x16000
option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload ../../../payloads/filo.elf
payload /tmp/filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

14
targets/digitallogic/adl855pc/Config.lb
View File

@@ -4,20 +4,20 @@
target adl855pc
mainboard digitallogic/adl855pc
option DEFAULT_CONSOLE_LOGLEVEL=9
option MAXIMUM_CONSOLE_LOGLEVEL=9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x10000
option COREBOOT_EXTRA_VERSION=".0Normal"
payload /etc/hosts
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x10000
option COREBOOT_EXTRA_VERSION=".0Fallback"
payload /etc/hosts
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

12
targets/digitallogic/msm586seg/Config-abuild.lb
View File

@@ -2,18 +2,18 @@ target VENDOR_MAINBOARD
mainboard VENDOR/MAINBOARD
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
option CONFIG_HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
__LOGLEVEL__
romimage "fallback"
option FALLBACK_SIZE = 256 * 1024
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE= 128 * 1024
option CONFIG_FALLBACK_SIZE = 256 * 1024
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE= 128 * 1024
option COREBOOT_EXTRA_VERSION=".0Fallback"
payload __PAYLOAD__
end
buildrom ./coreboot.rom ROM_SIZE "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"

24
targets/digitallogic/msm586seg/Config.lb
View File

@@ -3,30 +3,30 @@ mainboard digitallogic/msm586seg
option DEFAULT_CONSOLE_LOGLEVEL=3
option MAXIMUM_CONSOLE_LOGLEVEL=3
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=3
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=3
option CONFIG_COMPRESS=0
option CONFIG_CONSOLE_VGA=0
#romimage "normal"
# option USE_FALLBACK_IMAGE=0
# option ROM_IMAGE_SIZE=0x10000
# option CONFIG_USE_FALLBACK_IMAGE=0
# option CONFIG_ROM_IMAGE_SIZE=0x10000
# option COREBOOT_EXTRA_VERSION=".0Normal"
# payload /etc/hosts
#end
romimage "fallback"
option FALLBACK_SIZE = 256 * 1024
# option ROM_SIZE=512*1024
# option ROM_SECTION_SIZE=512*1024
option USE_FALLBACK_IMAGE=1
# option ROM_IMAGE_SIZE=32 * 1024 # 0x8000
option ROM_IMAGE_SIZE=128 * 1024 # 0x10000
# option ROM_IMAGE_SIZE=512 * 1024 # 0x10000
option CONFIG_FALLBACK_SIZE = 256 * 1024
# option CONFIG_ROM_SIZE=512*1024
# option CONFIG_ROM_SECTION_SIZE=512*1024
option CONFIG_USE_FALLBACK_IMAGE=1
# option CONFIG_ROM_IMAGE_SIZE=32 * 1024 # 0x8000
option CONFIG_ROM_IMAGE_SIZE=128 * 1024 # 0x10000
# option CONFIG_ROM_IMAGE_SIZE=512 * 1024 # 0x10000
option COREBOOT_EXTRA_VERSION=".0Fallback"
payload ../../filo.elf
# payload ../../eepro100--ide_disk.zelf
end
buildrom ./coreboot.rom ROM_SIZE "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"

18
targets/digitallogic/msm800sev/Config.lb
View File

@@ -5,24 +5,24 @@ mainboard digitallogic/msm800sev
option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
## ROM_SIZE is the total number of bytes allocated for coreboot use
## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
## (normal AND fallback images and payloads).
## leave 36k for vsa
##
option ROM_SIZE = 1024*1024 - 36 * 1024
option CONFIG_ROM_SIZE = 1024*1024 - 36 * 1024
## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
## not including any payload.
option ROM_IMAGE_SIZE=64*1024
option CONFIG_ROM_IMAGE_SIZE=64*1024
option FALLBACK_SIZE = ROM_SIZE
option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
option DEFAULT_CONSOLE_LOGLEVEL = 9
option MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option CONFIG_USE_FALLBACK_IMAGE=1
option COREBOOT_EXTRA_VERSION=".0Fallback"
payload ../payload.elf
end
buildrom ./coreboot.rom ROM_SIZE "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"

12
targets/eaglelion/5bcm/Config.lb
View File

@@ -4,11 +4,11 @@
target 5bcm
mainboard eaglelion/5bcm
option ROM_SIZE=256*1024
option CONFIG_ROM_SIZE=256*1024
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x10000
option COREBOOT_EXTRA_VERSION=".0Normal"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
@@ -18,8 +18,8 @@ romimage "normal"
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x10000
option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
@@ -28,4 +28,4 @@ romimage "fallback"
payload /home/hamish/work/etherboot/eb-5.2.6-lne100.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

36
targets/embeddedplanet/ep405pc/Config.lb
View File

@@ -6,10 +6,10 @@ mainboard embeddedplanet/ep405pc
romimage "normal"
## Enable PPC405 instructions
option CPU_OPT="-mcpu=405"
option CONFIG_CPU_OPT="-mcpu=405"
## use a cross compiler
#option CROSS_COMPILE="powerpc-ibm-eabi-"
#option CONFIG_CROSS_COMPILE="powerpc-ibm-eabi-"
## Use stage 1 initialization code
option CONFIG_USE_INIT=1
@@ -21,14 +21,14 @@ romimage "normal"
option CONFIG_COMPRESS=0
## Turn off POST codes
option NO_POST=1
option CONFIG_NO_POST=1
## Enable serial console
option DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_CONSOLE_SERIAL8250=1
# Divisor of 69 == 9600 baud due to weird clocking
option TTYS0_DIV=69
option TTYS0_BAUD=9600
option CONFIG_TTYS0_DIV=69
option CONFIG_TTYS0_BAUD=9600
## Boot linux from IDE
option CONFIG_IDE=1
@@ -36,25 +36,25 @@ romimage "normal"
option CONFIG_FS_EXT2=1
option CONFIG_FS_ISO9660=1
option CONFIG_FS_FAT=1
option AUTOBOOT_CMDLINE="hda1:/vmlinuz"
option CONFIG_AUTOBOOT_CMDLINE="hda1:/vmlinuz"
option ROM_SIZE=1024*1024
option CONFIG_ROM_SIZE=1024*1024
## Board has fixed size RAM
option EMBEDDED_RAM_SIZE=64*1024*1024
option CONFIG_EMBEDDED_RAM_SIZE=64*1024*1024
## Coreboot C code runs at this location in RAM
option _RAMBASE=0x00100000
option CONFIG_RAMBASE=0x00100000
##
## Use a 64K stack
##
option STACK_SIZE=0x10000
option CONFIG_STACK_SIZE=0x10000
##
## Use a 64K heap
##
option HEAP_SIZE=0x10000
option CONFIG_HEAP_SIZE=0x10000
##
## System clock
@@ -62,20 +62,20 @@ romimage "normal"
option CONFIG_SYS_CLK_FREQ=33
##
option _ROMBASE=0xfff00000
option CONFIG_ROMBASE=0xfff00000
## Reset vector address
option _RESET=0xfffffffc
option CONFIG_RESET=0xfffffffc
## Exception vectors
option _EXCEPTION_VECTORS=_ROMBASE+0x100
option CONFIG_EXCEPTION_VECTORS=CONFIG_ROMBASE+0x100
## coreboot ROM start address
option _ROMSTART=0xfff03000
option CONFIG_ROMSTART=0xfff03000
## coreboot C code runs at this location in RAM
option _RAMBASE=0x00100000
option CONFIG_RAMBASE=0x00100000
end
buildrom ./coreboot.rom ROM_SIZE "normal"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal"

8
targets/emulation/qemu-x86/Config-abuild.lb
View File

@@ -2,17 +2,17 @@ target VENDOR_MAINBOARD
mainboard VENDOR/MAINBOARD
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
option CONFIG_HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
__LOGLEVEL__
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option CONFIG_USE_FALLBACK_IMAGE=1
option COREBOOT_EXTRA_VERSION=".0"
payload __PAYLOAD__
end
buildrom ./coreboot.rom ROM_SIZE "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"

14
targets/emulation/qemu-x86/Config-car.lb
View File

@@ -3,24 +3,24 @@
target qemu-x86-car
mainboard emulation/qemu-x86
option USE_DCACHE_RAM=1
option CONFIG_USE_DCACHE_RAM=1
option CONFIG_USE_INIT=1
option ROM_SIZE=512*1024
option CONFIG_ROM_SIZE=512*1024
option CONFIG_USE_INIT=1
option CONFIG_USE_PRINTK_IN_CAR=1
option CC="gcc -m32"
option HAVE_PIRQ_TABLE=1
option IRQ_SLOT_COUNT=6
option CONFIG_HAVE_PIRQ_TABLE=1
option CONFIG_IRQ_SLOT_COUNT=6
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x10000
option COREBOOT_EXTRA_VERSION="-GRUB2"
# payload /home/stepan/core.img
payload ../payload.elf
end
buildrom ./coreboot.rom ROM_SIZE "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"

8
targets/emulation/qemu-x86/Config-lab.lb
View File

@@ -3,19 +3,19 @@
target qemu-x86
mainboard emulation/qemu-x86
option ROM_SIZE=2048*1024
option CONFIG_ROM_SIZE=2048*1024
option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
option CONFIG_PRECOMPRESSED_PAYLOAD=1
option CC="gcc -m32"
option HAVE_PIRQ_TABLE=1
option IRQ_SLOT_COUNT=6
option CONFIG_HAVE_PIRQ_TABLE=1
option CONFIG_IRQ_SLOT_COUNT=6
romimage "image"
option COREBOOT_EXTRA_VERSION="-LAB"
payload ../payload.elf.lzma
end
buildrom ./coreboot.rom ROM_SIZE "image"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "image"

8
targets/emulation/qemu-x86/Config.OLPC.lb
View File

@@ -3,19 +3,19 @@
target qemu-x86-OLPC
mainboard emulation/qemu-x86
option ROM_SIZE=1024*1024 - (128 * 1024)
option CONFIG_ROM_SIZE=1024*1024 - (128 * 1024)
option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
option CONFIG_PRECOMPRESSED_PAYLOAD=0
option CC="gcc -m32"
option HAVE_PIRQ_TABLE=1
option IRQ_SLOT_COUNT=6
option CONFIG_HAVE_PIRQ_TABLE=1
option CONFIG_IRQ_SLOT_COUNT=6
romimage "image"
option COREBOOT_EXTRA_VERSION="-OpenBIOS"
payload /tmp/olpcpayload.elf
end
buildrom ./coreboot.rom ROM_SIZE "image"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "image"

12
targets/emulation/qemu-x86/Config.lb
View File

@@ -3,14 +3,14 @@
target qemu-x86
mainboard emulation/qemu-x86
option ROM_SIZE=512*1024
option CONFIG_ROM_SIZE=512*1024
option CC="gcc -m32"
option HAVE_PIRQ_TABLE=1
option IRQ_SLOT_COUNT=6
option DEFAULT_CONSOLE_LOGLEVEL=9
option MAXIMUM_CONSOLE_LOGLEVEL=9
option CONFIG_HAVE_PIRQ_TABLE=1
option CONFIG_IRQ_SLOT_COUNT=6
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
romimage "normal"
option COREBOOT_EXTRA_VERSION="-GRUB2"
@@ -18,5 +18,5 @@ romimage "normal"
payload ../payload.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal"

18
targets/gigabyte/ga-6bxc/Config.lb
View File

@@ -21,29 +21,29 @@
target ga-6bxc
mainboard gigabyte/ga-6bxc
option ROM_SIZE = 256 * 1024
option CONFIG_ROM_SIZE = 256 * 1024
option MAINBOARD_VENDOR = "GIGABYTE"
option MAINBOARD_PART_NUMBER = "GA-6BXC"
option CONFIG_MAINBOARD_VENDOR = "GIGABYTE"
option CONFIG_MAINBOARD_PART_NUMBER = "GA-6BXC"
option IRQ_SLOT_COUNT = 6
option CONFIG_IRQ_SLOT_COUNT = 6
option DEFAULT_CONSOLE_LOGLEVEL = 9
option MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_CONSOLE_VGA = 1
option CONFIG_PCI_ROM_RUN = 1
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 0
option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option CONFIG_USE_FALLBACK_IMAGE = 1
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

32
targets/gigabyte/ga_2761gxdk/Config-abuild.lb
View File

@@ -23,39 +23,39 @@ target VENDOR_MAINBOARD
mainboard VENDOR/MAINBOARD
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
option CONFIG_HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
__LOGLEVEL__
option ROM_SIZE = 512*1024
option CONFIG_ROM_SIZE = 512*1024
romimage "normal"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x28000
option XIP_ROM_SIZE=0x40000
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x28000
option CONFIG_XIP_ROM_SIZE=0x40000
option COREBOOT_EXTRA_VERSION=".0-Normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x40000
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x20000
option CONFIG_XIP_ROM_SIZE=0x40000
option COREBOOT_EXTRA_VERSION=".0-Fallback"
payload __PAYLOAD__
end
romimage "failover"
option USE_FAILOVER_IMAGE=1
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
option CONFIG_USE_FAILOVER_IMAGE=1
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
option COREBOOT_EXTRA_VERSION=".0-Failover"
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"

28
targets/gigabyte/ga_2761gxdk/Config.lb
View File

@@ -26,33 +26,33 @@ mainboard gigabyte/ga_2761gxdk
romimage "normal"
# 32K for VGA BIOS
option ROM_SIZE = (512*1024 - 32*1024)
option CONFIG_ROM_SIZE = (512*1024 - 32*1024)
option USE_FAILOVER_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x40000
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x20000
option CONFIG_XIP_ROM_SIZE=0x40000
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../../payloads/filo_uda1.elf
payload ../payload.elf
end
romimage "fallback"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x40000
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x20000
option CONFIG_XIP_ROM_SIZE=0x40000
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../../payloads/filo_uda1.elf
payload ../payload.elf
end
romimage "failover"
option USE_FAILOVER_IMAGE=1
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
option CONFIG_USE_FAILOVER_IMAGE=1
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
end
# buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
# buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"

26
targets/gigabyte/m57sli/Config-abuild.lb
View File

@@ -4,33 +4,33 @@ target VENDOR_MAINBOARD
mainboard VENDOR/MAINBOARD
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
option CONFIG_HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
__LOGLEVEL__
romimage "normal"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
romimage "failover"
option USE_FAILOVER_IMAGE=1
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
option CONFIG_USE_FAILOVER_IMAGE=1
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"

22
targets/gigabyte/m57sli/Config-lab.lb
View File

@@ -24,26 +24,26 @@
target m57sli
mainboard gigabyte/m57sli
option ROM_SIZE=0x100000
option FALLBACK_SIZE=(ROM_SIZE-0x1000)
option CONFIG_ROM_SIZE=0x100000
option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0x1000)
romimage "fallback"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=1
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
option CONFIG_PRECOMPRESSED_PAYLOAD=1
option ROM_IMAGE_SIZE=0x17000
option XIP_ROM_SIZE=0x40000
option CONFIG_ROM_IMAGE_SIZE=0x17000
option CONFIG_XIP_ROM_SIZE=0x40000
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
payload ../payload.elf.lzma
end
romimage "failover"
option USE_FAILOVER_IMAGE=1
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
option CONFIG_USE_FAILOVER_IMAGE=1
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
end
buildrom ./coreboot.rom ROM_SIZE "fallback" "failover"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover"

48
targets/gigabyte/m57sli/Config.lb
View File

@@ -25,20 +25,20 @@ mainboard gigabyte/m57sli
# serengeti_leopard
romimage "normal"
# 48K for SCSI FW
# option ROM_SIZE = 475136
# option CONFIG_ROM_SIZE = 475136
# 48K for SCSI FW and 48K for ATI ROM
# option ROM_SIZE = 425984
# option CONFIG_ROM_SIZE = 425984
# 64K for Etherboot
# option ROM_SIZE = 458752
# option CONFIG_ROM_SIZE = 458752
# 44k for atixx.rom
# option ROM_SIZE = 479232
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=0
# option ROM_IMAGE_SIZE=0x13800
# option ROM_IMAGE_SIZE=0x18800
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
# option CONFIG_ROM_SIZE = 479232
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=0
# option CONFIG_ROM_IMAGE_SIZE=0x13800
# option CONFIG_ROM_IMAGE_SIZE=0x18800
option CONFIG_ROM_IMAGE_SIZE=0x20000
# option CONFIG_ROM_IMAGE_SIZE=0x15800
option CONFIG_XIP_ROM_SIZE=0x40000
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
@@ -61,13 +61,13 @@ romimage "normal"
end
romimage "fallback"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=1
# option ROM_IMAGE_SIZE=0x13800
# option ROM_IMAGE_SIZE=0x19800
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=1
# option CONFIG_ROM_IMAGE_SIZE=0x13800
# option CONFIG_ROM_IMAGE_SIZE=0x19800
option CONFIG_ROM_IMAGE_SIZE=0x20000
# option CONFIG_ROM_IMAGE_SIZE=0x15800
option CONFIG_XIP_ROM_SIZE=0x40000
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
@@ -95,12 +95,12 @@ romimage "fallback"
end
romimage "failover"
option USE_FAILOVER_IMAGE=1
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
option CONFIG_USE_FAILOVER_IMAGE=1
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
end
#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"

30
targets/gigabyte/m57sli/Config.lb.kernel
View File

@@ -24,19 +24,19 @@
target m57sli
mainboard gigabyte/m57sli
option ROM_SIZE=0x200000
option FALLBACK_SIZE=(ROM_SIZE-0x1000)
option CONFIG_ROM_SIZE=0x200000
option CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE-0x1000)
romimage "fallback"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=1
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
option CONFIG_PRECOMPRESSED_PAYLOAD=1
# option ROM_IMAGE_SIZE=0x19800
option ROM_IMAGE_SIZE=0x17000
# option ROM_IMAGE_SIZE=0x15800
# option ROM_IMAGE_SIZE=0x13800
option XIP_ROM_SIZE=0x40000
# option CONFIG_ROM_IMAGE_SIZE=0x19800
option CONFIG_ROM_IMAGE_SIZE=0x17000
# option CONFIG_ROM_IMAGE_SIZE=0x15800
# option CONFIG_ROM_IMAGE_SIZE=0x13800
option CONFIG_XIP_ROM_SIZE=0x40000
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
@@ -65,13 +65,13 @@ romimage "fallback"
end
romimage "failover"
option USE_FAILOVER_IMAGE=1
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
option CONFIG_USE_FAILOVER_IMAGE=1
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
end
buildrom ./coreboot.rom ROM_SIZE "fallback" "failover"
#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover"
#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

8
targets/hp/dl145_g3/Config.lb
View File

@@ -24,16 +24,16 @@
target dl145_g3
mainboard hp/dl145_g3
option ROM_SIZE= 1024*1024
option CONFIG_ROM_SIZE= 1024*1024
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option XIP_ROM_SIZE=0x20000
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_XIP_ROM_SIZE=0x20000
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
payload ./bios.bin.elf
end
buildrom ./coreboot.rom ROM_SIZE "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
pci_rom ./matrox.rom vendor_id=0x102b device_id=0x0522

10
targets/ibm/e325/Config.lb
View File

@@ -14,16 +14,16 @@ mainboard ibm/e325
#
# Arima hdama
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0Normal"
# payload ../../filo.elf
payload ../../../payloads/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload ../../filo.elf
payload ../../../payloads/filo.elf
@@ -31,4 +31,4 @@ romimage "fallback"
# payload /etc/hosts
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

16
targets/ibm/e326/Config-abuild.lb
View File

@@ -4,25 +4,25 @@ target VENDOR_MAINBOARD
mainboard VENDOR/MAINBOARD
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
option CONFIG_HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
__LOGLEVEL__
option ROM_SIZE=512*1024
option CONFIG_ROM_SIZE=512*1024
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

10
targets/ibm/e326/Config.lb
View File

@@ -10,16 +10,16 @@ mainboard ibm/e326
###
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0Normal"
# payload ../../filo.elf
payload ../../../payloads/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload ../../filo.elf
payload ../../../payloads/filo.elf
@@ -27,4 +27,4 @@ romimage "fallback"
# payload /etc/hosts
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

18
targets/iei/juki-511p/Config-abuild.lb
View File

@@ -2,31 +2,31 @@ target VENDOR_MAINBOARD
mainboard VENDOR/MAINBOARD
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
option CONFIG_HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
__LOGLEVEL__
option ROM_SIZE=256*1024
option CONFIG_ROM_SIZE=256*1024
###
### Compute the location and size of where this firmware image
### (coreboot plus bootloader) will live in the boot rom chip.
###
option FALLBACK_SIZE=128*1024
option CONFIG_FALLBACK_SIZE=128*1024
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=64*1024
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=64*1024
option COREBOOT_EXTRA_VERSION=".0-Normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=64*1024
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=64*1024
option COREBOOT_EXTRA_VERSION=".0-Fallback"
payload __PAYLOAD__
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

8
targets/iei/juki-511p/Config.lb
View File

@@ -21,17 +21,17 @@
target juki-511p
mainboard iei/juki-511p
option ROM_SIZE=256*1024
option CONFIG_ROM_SIZE=256*1024
option HAVE_PIRQ_TABLE=1
option CONFIG_HAVE_PIRQ_TABLE=1
option CONFIG_COMPRESS=0
option CONFIG_PRECOMPRESSED_PAYLOAD=0
romimage "image"
option ROM_IMAGE_SIZE=64*1024
option CONFIG_ROM_IMAGE_SIZE=64*1024
option COREBOOT_EXTRA_VERSION="-filo"
payload ../../filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "image"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "image"

16
targets/iei/nova4899r/Config.lb
View File

@@ -24,24 +24,24 @@
target nova4899r
mainboard iei/nova4899r
#option ROM_SIZE=256*1024
#option CONFIG_ROM_SIZE=256*1024
#from OLPC definitions
option CONFIG_COMPRESSED_PAYLOAD_NRV2B=1
#option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
#option CONFIG_PRECOMPRESSED_PAYLOAD=0
# leave 128k for vsa and 32k for VGA code
option ROM_SIZE=(256*1024)-(128*1024)-(32*1024)
option FALLBACK_SIZE=ROM_SIZE
option CONFIG_ROM_SIZE=(256*1024)-(128*1024)-(32*1024)
option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE
option DEFAULT_CONSOLE_LOGLEVEL = 8
option MAXIMUM_CONSOLE_LOGLEVEL = 8
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=64*1024
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=64*1024
option COREBOOT_EXTRA_VERSION=".0Fallback"
payload /opt/coreboot-SVN/filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
#"normal"

18
targets/iei/pcisa-lx-800-r10/Config.lb
View File

@@ -27,20 +27,20 @@ option CONFIG_COMPRESSED_PAYLOAD_NRV2B = 0
option CONFIG_COMPRESSED_PAYLOAD_LZMA = 0
# Leave 36k for VSA.
option ROM_SIZE = (512 * 1024) - (36 * 1024)
# option ROM_SIZE = (2048 * 1024) - (36 * 1024)
option CONFIG_ROM_SIZE = (512 * 1024) - (36 * 1024)
# option CONFIG_ROM_SIZE = (2048 * 1024) - (36 * 1024)
# Leave 36k for VSA, 1152k for bzImage and 750k for initrd.
# option ROM_SIZE = (2048 * 1024) - (36 * 1024) - (1152 * 1024) - (750 * 1024)
option FALLBACK_SIZE = ROM_SIZE
# option CONFIG_ROM_SIZE = (2048 * 1024) - (36 * 1024) - (1152 * 1024) - (750 * 1024)
option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
option DEFAULT_CONSOLE_LOGLEVEL = 0
option MAXIMUM_CONSOLE_LOGLEVEL = 0
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option ROM_IMAGE_SIZE = 80 * 1024
option CONFIG_USE_FALLBACK_IMAGE = 1
option CONFIG_ROM_IMAGE_SIZE = 80 * 1024
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload ../payload.elf
end
buildrom ./coreboot.rom ROM_SIZE "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"

16
targets/intel/mtarvon/Config.lb
View File

@@ -20,21 +20,21 @@
target mtarvon
mainboard intel/mtarvon
## ROM_SIZE is the total number of bytes allocated for coreboot use
## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
## (normal AND fallback images and payloads).
option ROM_SIZE = 2 * 1024 * 1024
option CONFIG_ROM_SIZE = 2 * 1024 * 1024
## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
## not including any payload.
option ROM_IMAGE_SIZE = 128 * 1024
option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
## FALLBACK_SIZE is the amount of the ROM the complete fallback image
## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image
## (including payload) will use
option FALLBACK_SIZE = ROM_SIZE
option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option CONFIG_USE_FALLBACK_IMAGE=1
payload /tmp/filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"

16
targets/intel/truxton/Config.lb
View File

@@ -20,21 +20,21 @@
target truxton
mainboard intel/truxton
## ROM_SIZE is the total number of bytes allocated for coreboot use
## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
## (normal AND fallback images and payloads).
option ROM_SIZE = 2 * 1024 * 1024
option CONFIG_ROM_SIZE = 2 * 1024 * 1024
## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
## not including any payload.
option ROM_IMAGE_SIZE = 128 * 1024
option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
## FALLBACK_SIZE is the amount of the ROM the complete fallback image
## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image
## (including payload) will use
option FALLBACK_SIZE = ROM_SIZE
option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option CONFIG_USE_FALLBACK_IMAGE=1
payload /tmp/filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"

18
targets/intel/xe7501devkit/Config.lb
View File

@@ -1,22 +1,22 @@
target xe7501devkit
mainboard intel/xe7501devkit
## ROM_SIZE is the total number of bytes allocated for coreboot use
## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
## (normal AND fallback images and payloads).
option ROM_SIZE = 192*1024
option CONFIG_ROM_SIZE = 192*1024
## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
## not including any payload.
option ROM_IMAGE_SIZE = 0x1B000
option CONFIG_ROM_IMAGE_SIZE = 0x1B000
## FALLBACK_SIZE is the amount of the ROM the complete fallback image
## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image
## (including payload) will use
option FALLBACK_SIZE = 0
option CONFIG_FALLBACK_SIZE = 0
romimage "normal"
option USE_FALLBACK_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=0
# option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../../../../../memtest86/memtest
# payload ../../../../../../../etherboot/src/bin/e1000.zelf
@@ -27,11 +27,11 @@ end
#NOTE: CMOS currently not supported due to conflicts with factory BIOS
# Thus no support for fallback boot.
#romimage "fallback"
# option USE_FALLBACK_IMAGE=1
# option CONFIG_USE_FALLBACK_IMAGE=1
# option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../../../../../memtest86/memtest
# payload ../../../../../../../etherboot/src/bin/e1000.zelf
# payload ../../../../../../../etherboot/src/bin/e1000--filo.zelf
#end
buildrom ./coreboot.rom ROM_SIZE "normal"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal"

26
targets/iwill/dk8_htx/Config-abuild.lb
View File

@@ -4,33 +4,33 @@ target VENDOR_MAINBOARD
mainboard VENDOR/MAINBOARD
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
option CONFIG_HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
__LOGLEVEL__
romimage "normal"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
romimage "failover"
option USE_FAILOVER_IMAGE=1
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
option CONFIG_USE_FAILOVER_IMAGE=1
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"

46
targets/iwill/dk8_htx/Config.lb
View File

@@ -5,18 +5,18 @@ mainboard iwill/dk8_htx
# serengeti_leopard
romimage "normal"
# 48K for SCSI FW
# option ROM_SIZE = 475136
# option CONFIG_ROM_SIZE = 475136
# 48K for SCSI FW and 48K for ATI ROM
# option ROM_SIZE = 425984
# option CONFIG_ROM_SIZE = 425984
# 64K for Etherboot
# option ROM_SIZE = 458752
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=0
# option ROM_IMAGE_SIZE=0x13800
# option ROM_IMAGE_SIZE=0x17800
# option ROM_IMAGE_SIZE=0x15800
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
# option CONFIG_ROM_SIZE = 458752
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=0
# option CONFIG_ROM_IMAGE_SIZE=0x13800
# option CONFIG_ROM_IMAGE_SIZE=0x17800
# option CONFIG_ROM_IMAGE_SIZE=0x15800
option CONFIG_ROM_IMAGE_SIZE=0x20000
option CONFIG_XIP_ROM_SIZE=0x20000
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
@@ -36,13 +36,13 @@ romimage "normal"
end
romimage "fallback"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=1
# option ROM_IMAGE_SIZE=0x13800
# option ROM_IMAGE_SIZE=0x17800
# option ROM_IMAGE_SIZE=0x15800
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=1
# option CONFIG_ROM_IMAGE_SIZE=0x13800
# option CONFIG_ROM_IMAGE_SIZE=0x17800
# option CONFIG_ROM_IMAGE_SIZE=0x15800
option CONFIG_ROM_IMAGE_SIZE=0x20000
option CONFIG_XIP_ROM_SIZE=0x20000
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
@@ -63,12 +63,12 @@ romimage "fallback"
end
romimage "failover"
option USE_FAILOVER_IMAGE=1
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
option CONFIG_USE_FAILOVER_IMAGE=1
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

90
targets/iwill/dk8s2/Config.lb
View File

@@ -6,13 +6,13 @@ target dk8s2
mainboard iwill/dk8s2
option HAVE_HARD_RESET=1
option CONFIG_HAVE_HARD_RESET=1
option HAVE_OPTION_TABLE=1
option HAVE_MP_TABLE=1
option ROM_SIZE=1024*1024
option CONFIG_HAVE_OPTION_TABLE=1
option CONFIG_HAVE_MP_TABLE=1
option CONFIG_ROM_SIZE=1024*1024
option HAVE_FALLBACK_BOOT=1
option CONFIG_HAVE_FALLBACK_BOOT=1
#option CONFIG_LSI_SCSI_FW_FIXUP=1
@@ -21,8 +21,8 @@ option HAVE_FALLBACK_BOOT=1
###
### Build code to export a programmable irq routing table
###
option HAVE_PIRQ_TABLE=1
option IRQ_SLOT_COUNT=12
option CONFIG_HAVE_PIRQ_TABLE=1
option CONFIG_IRQ_SLOT_COUNT=12
#
###
### Build code for SMP support
@@ -39,7 +39,7 @@ option CONFIG_MAX_PHYSICAL_CPUS=2
option CONFIG_IOAPIC=1
#
###
### MEMORY_HOLE instructs earlymtrr.inc to
### CONFIG_MEMORY_HOLE instructs earlymtrr.inc to
### enable caching from 0-640KB and to disable
### caching from 640KB-1MB using fixed MTRRs
###
@@ -47,24 +47,24 @@ option CONFIG_IOAPIC=1
### CPU identification depends on only variable MTRRs
### being enabled.
###
#option MEMORY_HOLE=0
#option CONFIG_MEMORY_HOLE=0
#
###
### Clean up the motherboard id strings
###
option MAINBOARD_PART_NUMBER="DK8S2"
option MAINBOARD_VENDOR="IWILL"
option CONFIG_MAINBOARD_PART_NUMBER="DK8S2"
option CONFIG_MAINBOARD_VENDOR="IWILL"
#
###
### Compute the location and size of where this firmware image
### (coreboot plus bootloader) will live in the boot rom chip.
###
#option FALLBACK_SIZE=524288
#option FALLBACK_SIZE=98304
option FALLBACK_SIZE=131072
#option CONFIG_FALLBACK_SIZE=524288
#option CONFIG_FALLBACK_SIZE=98304
option CONFIG_FALLBACK_SIZE=131072
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
option ROM_IMAGE_SIZE=65536
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
option CONFIG_ROM_IMAGE_SIZE=65536
###
@@ -77,7 +77,7 @@ option ROM_IMAGE_SIZE=65536
#option CONFIG_COMPRESS=1
option CONFIG_CONSOLE_SERIAL8250=1
option TTYS0_BAUD=115200
option CONFIG_TTYS0_BAUD=115200
##
### Select the coreboot loglevel
@@ -89,30 +89,30 @@ option TTYS0_BAUD=115200
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
## DEBUG 8 debug-level messages
## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
option DEFAULT_CONSOLE_LOGLEVEL=7
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
## At a maximum only compile in this level of debugging
option MAXIMUM_CONSOLE_LOGLEVEL=7
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=7
#option DEBUG=1
#option CONFIG_DEBUG=1
#
## Coreboot C code runs at this location in RAM
option _RAMBASE=0x004000
option CONFIG_RAMBASE=0x004000
##
## Use a 32K stack
##
option STACK_SIZE=0x8000
option CONFIG_STACK_SIZE=0x8000
##
## Use a 56K heap
##
option HEAP_SIZE=0xe000
option CONFIG_HEAP_SIZE=0xe000
#
###
@@ -125,22 +125,22 @@ option CONFIG_ROM_PAYLOAD = 1
#
romimage "normal"
# 48K for SCSI FW
# option ROM_SIZE = 512*1024-48*1024
# option CONFIG_ROM_SIZE = 512*1024-48*1024
# 48K for SCSI FW and 48K for ATI ROM
# option ROM_SIZE = 512*1024-48*1024-48*1024
# option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
option USE_FALLBACK_IMAGE=0
option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
option ROM_SECTION_OFFSET= 0
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_SECTION_SIZE = (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE)
option CONFIG_ROM_SECTION_OFFSET= 0
option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
option CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
option _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
option CONFIG_PAYLOAD_SIZE = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE)
option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
option CONFIG_ROMBASE = (CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE)
# option XIP_ROM_SIZE = FALLBACK_SIZE
option XIP_ROM_SIZE = 65536
# option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE
option CONFIG_XIP_ROM_SIZE = 65536
option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE)
payload /usr/src/filo-0.4.1_btext/filo.elf
# payload /usr/src/filo-0.4.2/filo.elf
@@ -148,20 +148,20 @@ end
romimage "fallback"
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
option USE_FALLBACK_IMAGE=1
option ROM_SECTION_SIZE = FALLBACK_SIZE
option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_SECTION_SIZE = CONFIG_FALLBACK_SIZE
option CONFIG_ROM_SECTION_OFFSET= (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE)
option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
option CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
option _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
option CONFIG_PAYLOAD_SIZE = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE)
option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
option CONFIG_ROMBASE = (CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE)
# option XIP_ROM_SIZE = FALLBACK_SIZE
option XIP_ROM_SIZE = 65536
option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
# option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE
option CONFIG_XIP_ROM_SIZE = 65536
option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE)
payload ../../../payloads/filo.elf
# payload /usr/src/filo-0.4.2/filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

90
targets/iwill/dk8x/Config.lb
View File

@@ -6,13 +6,13 @@ target dk8x
mainboard iwill/dk8x
option HAVE_HARD_RESET=1
option CONFIG_HAVE_HARD_RESET=1
option HAVE_OPTION_TABLE=1
option HAVE_MP_TABLE=1
option ROM_SIZE=1024*1024
option CONFIG_HAVE_OPTION_TABLE=1
option CONFIG_HAVE_MP_TABLE=1
option CONFIG_ROM_SIZE=1024*1024
option HAVE_FALLBACK_BOOT=1
option CONFIG_HAVE_FALLBACK_BOOT=1
#option CONFIG_LSI_SCSI_FW_FIXUP=1
@@ -21,8 +21,8 @@ option HAVE_FALLBACK_BOOT=1
###
### Build code to export a programmable irq routing table
###
option HAVE_PIRQ_TABLE=1
option IRQ_SLOT_COUNT=12
option CONFIG_HAVE_PIRQ_TABLE=1
option CONFIG_IRQ_SLOT_COUNT=12
#
###
### Build code for SMP support
@@ -39,7 +39,7 @@ option CONFIG_MAX_PHYSICAL_CPUS=2
option CONFIG_IOAPIC=1
#
###
### MEMORY_HOLE instructs earlymtrr.inc to
### CONFIG_MEMORY_HOLE instructs earlymtrr.inc to
### enable caching from 0-640KB and to disable
### caching from 640KB-1MB using fixed MTRRs
###
@@ -47,24 +47,24 @@ option CONFIG_IOAPIC=1
### CPU identification depends on only variable MTRRs
### being enabled.
###
#option MEMORY_HOLE=0
#option CONFIG_MEMORY_HOLE=0
#
###
### Clean up the motherboard id strings
###
option MAINBOARD_PART_NUMBER="DK8X"
option MAINBOARD_VENDOR="IWILL"
option CONFIG_MAINBOARD_PART_NUMBER="DK8X"
option CONFIG_MAINBOARD_VENDOR="IWILL"
#
###
### Compute the location and size of where this firmware image
### (coreboot plus bootloader) will live in the boot rom chip.
###
#option FALLBACK_SIZE=524288
#option FALLBACK_SIZE=98304
option FALLBACK_SIZE=131072
#option CONFIG_FALLBACK_SIZE=524288
#option CONFIG_FALLBACK_SIZE=98304
option CONFIG_FALLBACK_SIZE=131072
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
option ROM_IMAGE_SIZE=65536
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
option CONFIG_ROM_IMAGE_SIZE=65536
###
@@ -77,7 +77,7 @@ option ROM_IMAGE_SIZE=65536
#option CONFIG_COMPRESS=1
option CONFIG_CONSOLE_SERIAL8250=1
option TTYS0_BAUD=115200
option CONFIG_TTYS0_BAUD=115200
##
### Select the coreboot loglevel
@@ -89,30 +89,30 @@ option TTYS0_BAUD=115200
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
## DEBUG 8 debug-level messages
## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
option DEFAULT_CONSOLE_LOGLEVEL=7
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
## At a maximum only compile in this level of debugging
option MAXIMUM_CONSOLE_LOGLEVEL=7
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=7
#option DEBUG=1
#option CONFIG_DEBUG=1
#
## Coreboot C code runs at this location in RAM
option _RAMBASE=0x004000
option CONFIG_RAMBASE=0x004000
##
## Use a 32K stack
##
option STACK_SIZE=0x8000
option CONFIG_STACK_SIZE=0x8000
##
## Use a 56K heap
##
option HEAP_SIZE=0xe000
option CONFIG_HEAP_SIZE=0xe000
#
###
@@ -125,22 +125,22 @@ option CONFIG_ROM_PAYLOAD = 1
#
romimage "normal"
# 48K for SCSI FW
# option ROM_SIZE = 512*1024-48*1024
# option CONFIG_ROM_SIZE = 512*1024-48*1024
# 48K for SCSI FW and 48K for ATI ROM
# option ROM_SIZE = 512*1024-48*1024-48*1024
# option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
option USE_FALLBACK_IMAGE=0
option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
option ROM_SECTION_OFFSET= 0
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_SECTION_SIZE = (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE)
option CONFIG_ROM_SECTION_OFFSET= 0
option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
option CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
option _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
option CONFIG_PAYLOAD_SIZE = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE)
option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
option CONFIG_ROMBASE = (CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE)
# option XIP_ROM_SIZE = FALLBACK_SIZE
option XIP_ROM_SIZE = 65536
# option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE
option CONFIG_XIP_ROM_SIZE = 65536
option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE)
payload /usr/src/filo-0.4.1_btext/filo.elf
# payload /usr/src/filo-0.4.2/filo.elf
@@ -148,20 +148,20 @@ end
romimage "fallback"
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
option USE_FALLBACK_IMAGE=1
option ROM_SECTION_SIZE = FALLBACK_SIZE
option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_SECTION_SIZE = CONFIG_FALLBACK_SIZE
option CONFIG_ROM_SECTION_OFFSET= (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE)
option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
option CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
option _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
option CONFIG_PAYLOAD_SIZE = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE)
option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
option CONFIG_ROMBASE = (CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE)
# option XIP_ROM_SIZE = FALLBACK_SIZE
option XIP_ROM_SIZE = 65536
option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
# option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE
option CONFIG_XIP_ROM_SIZE = 65536
option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE)
payload ../../../payloads/filo.elf
# payload /usr/src/filo-0.4.2/filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

12
targets/jetway/j7f24/Config-abuild.lb
View File

@@ -4,18 +4,18 @@ target VENDOR_MAINBOARD
mainboard VENDOR/MAINBOARD
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
option CONFIG_HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
__LOGLEVEL__
option ROM_SIZE=512*1024
option CONFIG_ROM_SIZE=512*1024
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
buildrom ./coreboot.rom ROM_SIZE "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"

12
targets/jetway/j7f24/Config.lb
View File

@@ -22,24 +22,24 @@
target jetway-j7f24
mainboard jetway/j7f24
option MAXIMUM_CONSOLE_LOGLEVEL=8
option DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_CONSOLE_SERIAL8250=1
# coreboot C code runs at this location in RAM
option _RAMBASE=0x00004000
option CONFIG_RAMBASE=0x00004000
#
# If space is allotted for a VGA BIOS,
# generate the final ROM like this:
# cat vgabios bochsbios coreboot.rom > coreboot.rom.final
#
#option ROM_SIZE = (512 * 1024) - (63 * 1024) - (64 * 1024)
option ROM_SIZE = (512 * 1024)
#option CONFIG_ROM_SIZE = (512 * 1024) - (63 * 1024) - (64 * 1024)
option CONFIG_ROM_SIZE = (512 * 1024)
romimage "image"
option COREBOOT_EXTRA_VERSION = "-j7f24"
payload ../payload.elf
end
buildrom ./coreboot.rom ROM_SIZE "image"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "image"

12
targets/kontron/986lcd-m/Config-abuild.lb
View File

@@ -4,26 +4,26 @@ target VENDOR_MAINBOARD
mainboard VENDOR/MAINBOARD
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
option CONFIG_HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
__LOGLEVEL__
option ROM_SIZE=1024*1024
option CONFIG_ROM_SIZE=1024*1024
romimage "normal"
option USE_FALLBACK_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=0
option COREBOOT_EXTRA_VERSION=".0-normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option CONFIG_USE_FALLBACK_IMAGE=1
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
#pci_rom ../../../misc/kontron-pci8086,27a2.rom vendor_id=0x8086 device_id=0x27a2

8
targets/kontron/986lcd-m/Config.lb
View File

@@ -1,16 +1,16 @@
target kontron_986lcd_m
mainboard kontron/986lcd-m
## ROM_SIZE is the total number of bytes allocated for coreboot use
## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
## (normal AND fallback images and payloads).
option ROM_SIZE = 1024 * 1024
option CONFIG_ROM_SIZE = 1024 * 1024
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option CONFIG_USE_FALLBACK_IMAGE = 1
payload ../payload.elf
end
buildrom ./coreboot.rom ROM_SIZE "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
# Uncomment this and fix the path to your VGA BIOS blob (~/amipci_01.20 here) for on-board VGA support.
# See http://www.coreboot.org/Kontron_986LCD-M_mITX for details.

12
targets/lippert/frontrunner/Config.lb
View File

@@ -4,11 +4,11 @@
target frontrunner
mainboard lippert/frontrunner
option ROM_SIZE=256*1024
option CONFIG_ROM_SIZE=256*1024
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x16000
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x16000
option COREBOOT_EXTRA_VERSION=".0Normal"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
@@ -19,8 +19,8 @@ romimage "normal"
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x16000
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x16000
option COREBOOT_EXTRA_VERSION=".0Fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
@@ -30,4 +30,4 @@ romimage "fallback"
payload /tmp/filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

22
targets/lippert/roadrunner-lx/Config.lb
View File

@@ -35,28 +35,28 @@ option CONFIG_COMPRESSED_PAYLOAD_LZMA = 0
#option CONFIG_IDE = 1
#option CONFIG_FS_PAYLOAD = 1
#option CONFIG_FS_EXT2 = 1
#option AUTOBOOT_DELAY = 0
#option AUTOBOOT_CMDLINE = "hda1:/payload.elf"
#option CONFIG_AUTOBOOT_DELAY = 0
#option CONFIG_AUTOBOOT_CMDLINE = "hda1:/payload.elf"
# Leave 36k for VSA. Usually board is equipped with a 512 KB FWH (LPC) flash,
# however it can be replaced with a 1 MB chip.
option ROM_SIZE = (512 * 1024) - (36 * 1024)
#option ROM_SIZE = (1024 * 1024) - (36 * 1024)
option FALLBACK_SIZE = ROM_SIZE
option CONFIG_ROM_SIZE = (512 * 1024) - (36 * 1024)
#option CONFIG_ROM_SIZE = (1024 * 1024) - (36 * 1024)
option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
#option DEFAULT_CONSOLE_LOGLEVEL = 4
#option MAXIMUM_CONSOLE_LOGLEVEL = 4
#option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 4
#option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 4
# Saves space on ROM_IMAGE_SIZE, but decompression costs a second on boot.
# Saves space on CONFIG_ROM_IMAGE_SIZE, but decompression costs a second on boot.
option CONFIG_COMPRESS = 1
romimage "image"
option USE_FALLBACK_IMAGE = 1
option ROM_IMAGE_SIZE = 64 * 1024
option CONFIG_USE_FALLBACK_IMAGE = 1
option CONFIG_ROM_IMAGE_SIZE = 64 * 1024
option COREBOOT_EXTRA_VERSION = ".0"
payload ../payload.elf
# If getting payload from IDE
# payload /dev/null
end
buildrom ./coreboot.rom ROM_SIZE "image"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "image"

20
targets/lippert/spacerunner-lx/Config.lb
View File

@@ -36,27 +36,27 @@ option CONFIG_COMPRESSED_PAYLOAD_LZMA = 0
#option CONFIG_IDE = 1
#option CONFIG_FS_PAYLOAD = 1
#option CONFIG_FS_EXT2 = 1
#option AUTOBOOT_DELAY = 0
#option AUTOBOOT_CMDLINE = "hda1:/payload.elf"
#option CONFIG_AUTOBOOT_DELAY = 0
#option CONFIG_AUTOBOOT_CMDLINE = "hda1:/payload.elf"
# Leave 36k for VSA. Board is equipped with a 1 MB SPI flash, however, due to
# limitations of the IT8712F Super I/O, only the top 512 KB are directly mapped.
option ROM_SIZE = (512 * 1024) - (36 * 1024)
option FALLBACK_SIZE = ROM_SIZE
option CONFIG_ROM_SIZE = (512 * 1024) - (36 * 1024)
option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
#option DEFAULT_CONSOLE_LOGLEVEL = 4
#option MAXIMUM_CONSOLE_LOGLEVEL = 4
#option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 4
#option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 4
# Saves space on ROM_IMAGE_SIZE, but decompression costs a second on boot.
# Saves space on CONFIG_ROM_IMAGE_SIZE, but decompression costs a second on boot.
option CONFIG_COMPRESS = 1
romimage "image"
option USE_FALLBACK_IMAGE = 1
option ROM_IMAGE_SIZE = 64 * 1024
option CONFIG_USE_FALLBACK_IMAGE = 1
option CONFIG_ROM_IMAGE_SIZE = 64 * 1024
option COREBOOT_EXTRA_VERSION = ".0"
payload ../payload.elf
# If getting payload from IDE
# payload /dev/null
end
buildrom ./coreboot.rom ROM_SIZE "image"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "image"

16
targets/momentum/apache/Config.lb
View File

@@ -8,21 +8,21 @@ mainboard momentum/apache
# Apache Demo Board
romimage "normal"
## Base of ROM
option _ROMBASE=0xfff00000
option CONFIG_ROMBASE=0xfff00000
## Apache reset vector
option _RESET=_ROMBASE+0x100
option CONFIG_RESET=CONFIG_ROMBASE+0x100
## Exception vectors (other than reset vector)
option _EXCEPTION_VECTORS=_RESET+0x100
option CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100
## Start of coreboot in the boot rom
## = _RESET + exeception vector table size
option _ROMSTART=_RESET+0x3100
## = CONFIG_RESET + exeception vector table size
option CONFIG_ROMSTART=CONFIG_RESET+0x3100
## Coreboot C code runs at this location in RAM
option _RAMBASE=0x00100000
option _RAMSTART=0x00100000
option CONFIG_RAMBASE=0x00100000
option CONFIG_RAMSTART=0x00100000
end
buildrom ./coreboot.rom ROM_SIZE "normal"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal"

16
targets/motorola/sandpoint/Config.lb
View File

@@ -9,23 +9,23 @@ mainboard motorola/sandpointx3_altimus_mpc7410
# Sandpoint Demo Board
romimage "normal"
## Base of ROM
option _ROMBASE=0xfff00000
option CONFIG_ROMBASE=0xfff00000
## Sandpoint reset vector
option _RESET=_ROMBASE+0x100
option CONFIG_RESET=CONFIG_ROMBASE+0x100
## Exception vectors (other than reset vector)
option _EXCEPTION_VECTORS=_RESET+0x100
option CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100
## Start of coreboot in the boot rom
## = _RESET + exeception vector table size
option _ROMSTART=_RESET+0x3100
## = CONFIG_RESET + exeception vector table size
option CONFIG_ROMSTART=CONFIG_RESET+0x3100
## Coreboot C code runs at this location in RAM
option _RAMBASE=0x00100000
option _RAMSTART=0x00100000
option CONFIG_RAMBASE=0x00100000
option CONFIG_RAMSTART=0x00100000
option CONFIG_SANDPOINT_ALTIMUS=1
end
buildrom ./coreboot.rom ROM_SIZE "normal"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal"

70
targets/motorola/sandpoint/Config.lb.ide_stream
View File

@@ -6,32 +6,32 @@ loadoptions
target sandpoint
uses CROSS_COMPILE
uses HAVE_OPTION_TABLE
uses CONFIG_CROSS_COMPILE
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_SANDPOINT_ALTIMUS
uses CONFIG_COMPRESS
uses DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_USE_INIT
uses CONFIG_CHIP_CONFIGURE
uses NO_POST
uses CONFIG_NO_POST
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BASE
uses CONFIG_TTYS0_BASE
uses CONFIG_IDE_PAYLOAD
uses IDE_BOOT_DRIVE
uses IDE_SWAB IDE_OFFSET
uses ROM_SIZE
uses _RESET
uses _EXCEPTION_VECTORS
uses _ROMBASE
uses _ROMSTART
uses _RAMBASE
uses _RAMSTART
uses STACK_SIZE
uses HEAP_SIZE
uses CONFIG_IDE_BOOT_DRIVE
uses CONFIG_IDE_SWAB CONFIG_IDE_OFFSET
uses CONFIG_ROM_SIZE
uses CONFIG_RESET
uses CONFIG_EXCEPTION_VECTORS
uses CONFIG_ROMBASE
uses CONFIG_ROMSTART
uses CONFIG_RAMBASE
uses CONFIG_RAMSTART
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
## use a cross compiler
#option CROSS_COMPILE="powerpc-eabi-"
#option CROSS_COMPILE="ppc_74xx-"
#option CONFIG_CROSS_COMPILE="powerpc-eabi-"
#option CONFIG_CROSS_COMPILE="ppc_74xx-"
## Use stage 1 initialization code
option CONFIG_USE_INIT=1
@@ -43,48 +43,48 @@ option CONFIG_CHIP_CONFIGURE=1
option CONFIG_COMPRESS=0
## Turn off POST codes
option NO_POST=1
option CONFIG_NO_POST=1
## Enable serial console
option DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_CONSOLE_SERIAL8250=1
option TTYS0_BASE=0x3f8
option CONFIG_TTYS0_BASE=0x3f8
## Boot linux from IDE
option CONFIG_IDE_PAYLOAD=1
option IDE_BOOT_DRIVE=0
option IDE_SWAB=1
option IDE_OFFSET=0
option CONFIG_IDE_BOOT_DRIVE=0
option CONFIG_IDE_SWAB=1
option CONFIG_IDE_OFFSET=0
# ROM is 1Mb
option ROM_SIZE=1024*1024
option CONFIG_ROM_SIZE=1024*1024
# Set stack and heap sizes (stage 2)
option STACK_SIZE=0x10000
option HEAP_SIZE=0x10000
option CONFIG_STACK_SIZE=0x10000
option CONFIG_HEAP_SIZE=0x10000
# Sandpoint Demo Board
romimage "normal"
## Base of ROM
option _ROMBASE=0xfff00000
option CONFIG_ROMBASE=0xfff00000
## Sandpoint reset vector
option _RESET=_ROMBASE+0x100
option CONFIG_RESET=CONFIG_ROMBASE+0x100
## Exception vectors (other than reset vector)
option _EXCEPTION_VECTORS=_RESET+0x100
option CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100
## Start of coreboot in the boot rom
## = _RESET + exeception vector table size
option _ROMSTART=_RESET+0x3100
## = CONFIG_RESET + exeception vector table size
option CONFIG_ROMSTART=CONFIG_RESET+0x3100
## Coreboot C code runs at this location in RAM
option _RAMBASE=0x00100000
option _RAMSTART=0x00100000
option CONFIG_RAMBASE=0x00100000
option CONFIG_RAMSTART=0x00100000
option CONFIG_SANDPOINT_ALTIMUS=1
mainboard motorola/sandpoint
end
buildrom ./coreboot.rom ROM_SIZE "normal"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal"

18
targets/msi/ms6119/Config.lb
View File

@@ -21,29 +21,29 @@
target ms6119
mainboard msi/ms6119
option ROM_SIZE = 256 * 1024
option CONFIG_ROM_SIZE = 256 * 1024
option MAINBOARD_VENDOR = "MSI"
option MAINBOARD_PART_NUMBER = "MS-6119"
option CONFIG_MAINBOARD_VENDOR = "MSI"
option CONFIG_MAINBOARD_PART_NUMBER = "MS-6119"
option IRQ_SLOT_COUNT = 7
option CONFIG_IRQ_SLOT_COUNT = 7
option DEFAULT_CONSOLE_LOGLEVEL = 9
option MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_CONSOLE_VGA = 1
option CONFIG_PCI_ROM_RUN = 1
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 0
option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option CONFIG_USE_FALLBACK_IMAGE = 1
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

18
targets/msi/ms6147/Config.lb
View File

@@ -21,29 +21,29 @@
target ms6147
mainboard msi/ms6147
option ROM_SIZE = 256 * 1024
option CONFIG_ROM_SIZE = 256 * 1024
option MAINBOARD_VENDOR = "MSI"
option MAINBOARD_PART_NUMBER = "MS-6147"
option CONFIG_MAINBOARD_VENDOR = "MSI"
option CONFIG_MAINBOARD_PART_NUMBER = "MS-6147"
option IRQ_SLOT_COUNT = 8
option CONFIG_IRQ_SLOT_COUNT = 8
option DEFAULT_CONSOLE_LOGLEVEL = 9
option MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_CONSOLE_VGA = 1
option CONFIG_PCI_ROM_RUN = 1
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 0
option COREBOOT_EXTRA_VERSION = ".Normal"
payload ../payload.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option CONFIG_USE_FALLBACK_IMAGE = 1
option COREBOOT_EXTRA_VERSION = ".Fallback"
payload ../payload.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

18
targets/msi/ms6178/Config.lb
View File

@@ -21,32 +21,32 @@
target ms6178
mainboard msi/ms6178
option ROM_SIZE = 512 * 1024
option CONFIG_ROM_SIZE = 512 * 1024
option MAINBOARD_VENDOR = "MSI"
option MAINBOARD_PART_NUMBER = "MS-6178"
option CONFIG_MAINBOARD_VENDOR = "MSI"
option CONFIG_MAINBOARD_PART_NUMBER = "MS-6178"
option IRQ_SLOT_COUNT = 4
option CONFIG_IRQ_SLOT_COUNT = 4
option DEFAULT_CONSOLE_LOGLEVEL = 9
option MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_CONSOLE_VGA = 1
option CONFIG_PCI_ROM_RUN = 1
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 0
option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option CONFIG_USE_FALLBACK_IMAGE = 1
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
# pci_rom i810.vga vendor_id=0x8086 device_id=0x7120

26
targets/msi/ms7135/Config-abuild.lb
View File

@@ -4,33 +4,33 @@ target VENDOR_MAINBOARD
mainboard VENDOR/MAINBOARD
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
option CONFIG_HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
__LOGLEVEL__
romimage "normal"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
romimage "failover"
option USE_FAILOVER_IMAGE=1
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
option CONFIG_USE_FAILOVER_IMAGE=1
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"

34
targets/msi/ms7135/Config.lb
View File

@@ -23,39 +23,39 @@
target ms7135
mainboard msi/ms7135
option DEFAULT_CONSOLE_LOGLEVEL=8
option MAXIMUM_CONSOLE_LOGLEVEL=8
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
option HAVE_PIRQ_TABLE=1
option CONFIG_HAVE_PIRQ_TABLE=1
option CONFIG_CONSOLE_VGA=1
option CONFIG_PCI_ROM_RUN=1
romimage "normal"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x20000
option CONFIG_XIP_ROM_SIZE=0x20000
option COREBOOT_EXTRA_VERSION="_Normal"
payload /tmp/payload.elf
end
romimage "fallback"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
option CONFIG_USE_FAILOVER_IMAGE=0
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x20000
option CONFIG_XIP_ROM_SIZE=0x20000
option COREBOOT_EXTRA_VERSION="_Fallback"
payload /tmp/payload.elf
end
romimage "failover"
option USE_FAILOVER_IMAGE=1
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
option CONFIG_USE_FAILOVER_IMAGE=1
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
option COREBOOT_EXTRA_VERSION="_Failover"
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

32
targets/msi/ms7260/Config-abuild.lb
View File

@@ -22,37 +22,37 @@ target VENDOR_MAINBOARD
mainboard VENDOR/MAINBOARD
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
option CONFIG_HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
__LOGLEVEL__
romimage "normal"
option USE_FAILOVER_IMAGE = 0
option USE_FALLBACK_IMAGE = 0
option ROM_IMAGE_SIZE = 128 * 1024
option XIP_ROM_SIZE = 256 * 1024
option CONFIG_USE_FAILOVER_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 0
option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
option CONFIG_XIP_ROM_SIZE = 256 * 1024
option COREBOOT_EXTRA_VERSION = ".0Normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FAILOVER_IMAGE = 0
option USE_FALLBACK_IMAGE = 1
option ROM_IMAGE_SIZE = 128 * 1024
option XIP_ROM_SIZE = 256 * 1024
option CONFIG_USE_FAILOVER_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 1
option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
option CONFIG_XIP_ROM_SIZE = 256 * 1024
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload __PAYLOAD__
end
romimage "failover"
option USE_FAILOVER_IMAGE = 1
option USE_FALLBACK_IMAGE = 0
option ROM_IMAGE_SIZE = FAILOVER_SIZE
option XIP_ROM_SIZE = FAILOVER_SIZE
option CONFIG_USE_FAILOVER_IMAGE = 1
option CONFIG_USE_FALLBACK_IMAGE = 0
option CONFIG_ROM_IMAGE_SIZE = CONFIG_FAILOVER_SIZE
option CONFIG_XIP_ROM_SIZE = CONFIG_FAILOVER_SIZE
option COREBOOT_EXTRA_VERSION = ".0Failover"
end
# buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
# buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"

30
targets/msi/ms7260/Config.lb
View File

@@ -21,38 +21,38 @@
target ms7260
mainboard msi/ms7260
option ROM_SIZE = 512 * 1024
option CONFIG_ROM_SIZE = 512 * 1024
option CONFIG_COMPRESSED_PAYLOAD_NRV2B = 1 # NRV2B compression
# option CONFIG_COMPRESSED_PAYLOAD_LZMA = 1 # LZMA compression
romimage "normal"
option USE_FAILOVER_IMAGE = 0
option USE_FALLBACK_IMAGE = 0
option ROM_IMAGE_SIZE = 128 * 1024
option XIP_ROM_SIZE = 256 * 1024
option CONFIG_USE_FAILOVER_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 0
option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
option CONFIG_XIP_ROM_SIZE = 256 * 1024
option COREBOOT_EXTRA_VERSION = ".0Normal"
# payload /tmp/filo.elf
payload ../payload.elf
end
romimage "fallback"
option USE_FAILOVER_IMAGE = 0
option USE_FALLBACK_IMAGE = 1
option ROM_IMAGE_SIZE = 128 * 1024
option XIP_ROM_SIZE = 256 * 1024
option CONFIG_USE_FAILOVER_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 1
option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
option CONFIG_XIP_ROM_SIZE = 256 * 1024
option COREBOOT_EXTRA_VERSION = ".0Fallback"
# payload /tmp/filo.elf
payload ../payload.elf
end
romimage "failover"
option USE_FAILOVER_IMAGE = 1
option USE_FALLBACK_IMAGE = 0
option ROM_IMAGE_SIZE = FAILOVER_SIZE
option XIP_ROM_SIZE = FAILOVER_SIZE
option CONFIG_USE_FAILOVER_IMAGE = 1
option CONFIG_USE_FALLBACK_IMAGE = 0
option CONFIG_ROM_IMAGE_SIZE = CONFIG_FAILOVER_SIZE
option CONFIG_XIP_ROM_SIZE = CONFIG_FAILOVER_SIZE
option COREBOOT_EXTRA_VERSION = ".0Failover"
end
# buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
# buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"

14
targets/msi/ms9185/Config-abuild.lb
View File

@@ -4,23 +4,23 @@ target VENDOR_MAINBOARD
mainboard VENDOR/MAINBOARD
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
option CONFIG_HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
__LOGLEVEL__
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE = 128 * 1024
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
option COREBOOT_EXTRA_VERSION=".0-normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE = 128 * 1024
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

34
targets/msi/ms9185/Config.lb
View File

@@ -29,17 +29,17 @@ mainboard msi/ms9185
# ms9185
romimage "normal"
# 36k for ATI option rom
option ROM_SIZE = 512*1024-36*1024
# option ROM_SIZE = 524288
# option ROM_SIZE = 425984
option CONFIG_ROM_SIZE = 512*1024-36*1024
# option CONFIG_ROM_SIZE = 524288
# option CONFIG_ROM_SIZE = 425984
# 64K for Etherboot
# option ROM_SIZE = 458752
option USE_FALLBACK_IMAGE=0
# option ROM_IMAGE_SIZE=0x13800
# option ROM_IMAGE_SIZE=0x18800
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
# option CONFIG_ROM_SIZE = 458752
option CONFIG_USE_FALLBACK_IMAGE=0
# option CONFIG_ROM_IMAGE_SIZE=0x13800
# option CONFIG_ROM_IMAGE_SIZE=0x18800
option CONFIG_ROM_IMAGE_SIZE=0x20000
# option CONFIG_ROM_IMAGE_SIZE=0x15800
option CONFIG_XIP_ROM_SIZE=0x40000
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
@@ -62,12 +62,12 @@ romimage "normal"
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
# option ROM_IMAGE_SIZE=0x13800
# option ROM_IMAGE_SIZE=0x19800
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
option CONFIG_USE_FALLBACK_IMAGE=1
# option CONFIG_ROM_IMAGE_SIZE=0x13800
# option CONFIG_ROM_IMAGE_SIZE=0x19800
option CONFIG_ROM_IMAGE_SIZE=0x20000
# option CONFIG_ROM_IMAGE_SIZE=0x15800
option CONFIG_XIP_ROM_SIZE=0x40000
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
@@ -91,4 +91,4 @@ romimage "fallback"
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

14
targets/msi/ms9282/Config-abuild.lb
View File

@@ -4,23 +4,23 @@ target VENDOR_MAINBOARD
mainboard VENDOR/MAINBOARD
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
option CONFIG_HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
__LOGLEVEL__
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE = 128 * 1024
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
option COREBOOT_EXTRA_VERSION=".0-normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE = 128 * 1024
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

36
targets/msi/ms9282/Config.lb
View File

@@ -24,19 +24,19 @@ mainboard msi/ms9282
romimage "normal"
# 48K for SCSI FW
# option ROM_SIZE = 475136
option ROM_SIZE = 512*1024-36*1024
# option ROM_SIZE = 524288
# option CONFIG_ROM_SIZE = 475136
option CONFIG_ROM_SIZE = 512*1024-36*1024
# option CONFIG_ROM_SIZE = 524288
# 48K for SCSI FW and 48K for ATI ROM
# option ROM_SIZE = 425984
# option CONFIG_ROM_SIZE = 425984
# 64K for Etherboot
# option ROM_SIZE = 458752
option USE_FALLBACK_IMAGE=0
# option ROM_IMAGE_SIZE=0x13800
# option ROM_IMAGE_SIZE=0x18800
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
# option CONFIG_ROM_SIZE = 458752
option CONFIG_USE_FALLBACK_IMAGE=0
# option CONFIG_ROM_IMAGE_SIZE=0x13800
# option CONFIG_ROM_IMAGE_SIZE=0x18800
option CONFIG_ROM_IMAGE_SIZE=0x20000
# option CONFIG_ROM_IMAGE_SIZE=0x15800
option CONFIG_XIP_ROM_SIZE=0x40000
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
@@ -59,12 +59,12 @@ romimage "normal"
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
# option ROM_IMAGE_SIZE=0x13800
# option ROM_IMAGE_SIZE=0x19800
option ROM_IMAGE_SIZE=0x20000
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
option CONFIG_USE_FALLBACK_IMAGE=1
# option CONFIG_ROM_IMAGE_SIZE=0x13800
# option CONFIG_ROM_IMAGE_SIZE=0x19800
option CONFIG_ROM_IMAGE_SIZE=0x20000
# option CONFIG_ROM_IMAGE_SIZE=0x15800
option CONFIG_XIP_ROM_SIZE=0x40000
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
@@ -88,4 +88,4 @@ romimage "fallback"
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

18
targets/nec/powermate2000/Config.lb
View File

@@ -21,29 +21,29 @@
target powermate2000
mainboard nec/powermate2000
option ROM_SIZE = 512 * 1024
option CONFIG_ROM_SIZE = 512 * 1024
option MAINBOARD_VENDOR = "NEC"
option MAINBOARD_PART_NUMBER = "PowerMate 2000"
option CONFIG_MAINBOARD_VENDOR = "NEC"
option CONFIG_MAINBOARD_PART_NUMBER = "PowerMate 2000"
option IRQ_SLOT_COUNT = 5
option CONFIG_IRQ_SLOT_COUNT = 5
option DEFAULT_CONSOLE_LOGLEVEL = 9
option MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_CONSOLE_VGA = 1
option CONFIG_PCI_ROM_RUN = 1
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option CONFIG_USE_FALLBACK_IMAGE = 0
option COREBOOT_EXTRA_VERSION = ".0Normal"
payload ../payload.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option CONFIG_USE_FALLBACK_IMAGE = 1
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload ../payload.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

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