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This patch unifies the use of config options in v2 to all start with CONFIG_

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It's basically done with the following script and some manual fixup:

VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
	find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2009-06-30 15:17:49 +00:00
committed by Stefan Reinauer
parent 9702b6bf7e
commit 0867062412
863 changed files with 14632 additions and 14632 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
targets/motorola/sandpoint/Config.lb
View File

@@ -9,23 +9,23 @@ mainboard motorola/sandpointx3_altimus_mpc7410
# Sandpoint Demo Board
romimage "normal"
## Base of ROM
option _ROMBASE=0xfff00000
option CONFIG_ROMBASE=0xfff00000
## Sandpoint reset vector
option _RESET=_ROMBASE+0x100
option CONFIG_RESET=CONFIG_ROMBASE+0x100
## Exception vectors (other than reset vector)
option _EXCEPTION_VECTORS=_RESET+0x100
option CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100
## Start of coreboot in the boot rom
## = _RESET + exeception vector table size
option _ROMSTART=_RESET+0x3100
## = CONFIG_RESET + exeception vector table size
option CONFIG_ROMSTART=CONFIG_RESET+0x3100
## Coreboot C code runs at this location in RAM
option _RAMBASE=0x00100000
option _RAMSTART=0x00100000
option CONFIG_RAMBASE=0x00100000
option CONFIG_RAMSTART=0x00100000
option CONFIG_SANDPOINT_ALTIMUS=1
end
buildrom ./coreboot.rom ROM_SIZE "normal"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal"

70
targets/motorola/sandpoint/Config.lb.ide_stream
View File

@@ -6,32 +6,32 @@ loadoptions
target sandpoint
uses CROSS_COMPILE
uses HAVE_OPTION_TABLE
uses CONFIG_CROSS_COMPILE
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_SANDPOINT_ALTIMUS
uses CONFIG_COMPRESS
uses DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_USE_INIT
uses CONFIG_CHIP_CONFIGURE
uses NO_POST
uses CONFIG_NO_POST
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BASE
uses CONFIG_TTYS0_BASE
uses CONFIG_IDE_PAYLOAD
uses IDE_BOOT_DRIVE
uses IDE_SWAB IDE_OFFSET
uses ROM_SIZE
uses _RESET
uses _EXCEPTION_VECTORS
uses _ROMBASE
uses _ROMSTART
uses _RAMBASE
uses _RAMSTART
uses STACK_SIZE
uses HEAP_SIZE
uses CONFIG_IDE_BOOT_DRIVE
uses CONFIG_IDE_SWAB CONFIG_IDE_OFFSET
uses CONFIG_ROM_SIZE
uses CONFIG_RESET
uses CONFIG_EXCEPTION_VECTORS
uses CONFIG_ROMBASE
uses CONFIG_ROMSTART
uses CONFIG_RAMBASE
uses CONFIG_RAMSTART
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
## use a cross compiler
#option CROSS_COMPILE="powerpc-eabi-"
#option CROSS_COMPILE="ppc_74xx-"
#option CONFIG_CROSS_COMPILE="powerpc-eabi-"
#option CONFIG_CROSS_COMPILE="ppc_74xx-"
## Use stage 1 initialization code
option CONFIG_USE_INIT=1
@@ -43,48 +43,48 @@ option CONFIG_CHIP_CONFIGURE=1
option CONFIG_COMPRESS=0
## Turn off POST codes
option NO_POST=1
option CONFIG_NO_POST=1
## Enable serial console
option DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_CONSOLE_SERIAL8250=1
option TTYS0_BASE=0x3f8
option CONFIG_TTYS0_BASE=0x3f8
## Boot linux from IDE
option CONFIG_IDE_PAYLOAD=1
option IDE_BOOT_DRIVE=0
option IDE_SWAB=1
option IDE_OFFSET=0
option CONFIG_IDE_BOOT_DRIVE=0
option CONFIG_IDE_SWAB=1
option CONFIG_IDE_OFFSET=0
# ROM is 1Mb
option ROM_SIZE=1024*1024
option CONFIG_ROM_SIZE=1024*1024
# Set stack and heap sizes (stage 2)
option STACK_SIZE=0x10000
option HEAP_SIZE=0x10000
option CONFIG_STACK_SIZE=0x10000
option CONFIG_HEAP_SIZE=0x10000
# Sandpoint Demo Board
romimage "normal"
## Base of ROM
option _ROMBASE=0xfff00000
option CONFIG_ROMBASE=0xfff00000
## Sandpoint reset vector
option _RESET=_ROMBASE+0x100
option CONFIG_RESET=CONFIG_ROMBASE+0x100
## Exception vectors (other than reset vector)
option _EXCEPTION_VECTORS=_RESET+0x100
option CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100
## Start of coreboot in the boot rom
## = _RESET + exeception vector table size
option _ROMSTART=_RESET+0x3100
## = CONFIG_RESET + exeception vector table size
option CONFIG_ROMSTART=CONFIG_RESET+0x3100
## Coreboot C code runs at this location in RAM
option _RAMBASE=0x00100000
option _RAMSTART=0x00100000
option CONFIG_RAMBASE=0x00100000
option CONFIG_RAMSTART=0x00100000
option CONFIG_SANDPOINT_ALTIMUS=1
mainboard motorola/sandpoint
end
buildrom ./coreboot.rom ROM_SIZE "normal"
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal"