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This patch unifies the use of config options in v2 to all start with CONFIG_

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It's basically done with the following script and some manual fixup:

VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
	find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2009-06-30 15:17:49 +00:00
committed by Stefan Reinauer
parent 9702b6bf7e
commit 0867062412
863 changed files with 14632 additions and 14632 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
util/romcc/tests/hello_world.c
View File

@@ -9,31 +9,31 @@ unsigned char inb(unsigned short port)
}
/* Base Address */
#ifndef TTYS0_BASE
#define TTYS0_BASE 0x3f8
#ifndef CONFIG_TTYS0_BASE
#define CONFIG_TTYS0_BASE 0x3f8
#endif
#ifndef TTYS0_BAUD
#define TTYS0_BAUD 115200
#ifndef CONFIG_TTYS0_BAUD
#define CONFIG_TTYS0_BAUD 115200
#endif
#if ((115200%TTYS0_BAUD) != 0)
#if ((115200%CONFIG_TTYS0_BAUD) != 0)
#error Bad ttys0 baud rate
#endif
#if TTYS0_BAUD == 115200
#define TTYS0_DIV (1)
#if CONFIG_TTYS0_BAUD == 115200
#define CONFIG_TTYS0_DIV (1)
#else
#define TTYS0_DIV (115200/TTYS0_BAUD)
#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
#endif
/* Line Control Settings */
#ifndef TTYS0_LCS
#ifndef CONFIG_TTYS0_LCS
/* Set 8bit, 1 stop bit, no parity */
#define TTYS0_LCS 0x3
#define CONFIG_TTYS0_LCS 0x3
#endif
#define UART_LCS TTYS0_LCS
#define UART_LCS CONFIG_TTYS0_LCS
/* Data */
#define UART_RBR 0x00
@@ -55,7 +55,7 @@ unsigned char inb(unsigned short port)
int uart_can_tx_byte(void)
{
return inb(TTYS0_BASE + UART_LSR) & 0x20;
return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
}
void uart_wait_to_tx_byte(void)
@@ -66,14 +66,14 @@ void uart_wait_to_tx_byte(void)
void uart_wait_until_sent(void)
{
while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
static void uart_tx_byte(unsigned char data)
{
uart_wait_to_tx_byte();
outb(data, TTYS0_BASE + UART_TBR);
outb(data, CONFIG_TTYS0_BASE + UART_TBR);
/* Make certain the data clears the fifos */
uart_wait_until_sent();
}
@@ -82,14 +82,14 @@ static void uart_tx_byte(unsigned char data)
void uart_init(void)
{
/* disable interrupts */
outb(0x0, TTYS0_BASE + UART_IER);
outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
/* enable fifo's */
outb(0x01, TTYS0_BASE + UART_FCR);
outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR);
outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL);
outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM);
outb(UART_LCS, TTYS0_BASE + UART_LCR);
outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL);
outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM);
outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
}

40
util/romcc/tests/hello_world1.c
View File

@@ -9,31 +9,31 @@ unsigned char inb(unsigned short port)
}
/* Base Address */
#ifndef TTYS0_BASE
#define TTYS0_BASE 0x3f8
#ifndef CONFIG_TTYS0_BASE
#define CONFIG_TTYS0_BASE 0x3f8
#endif
#ifndef TTYS0_BAUD
#define TTYS0_BAUD 115200
#ifndef CONFIG_TTYS0_BAUD
#define CONFIG_TTYS0_BAUD 115200
#endif
#if ((115200%TTYS0_BAUD) != 0)
#if ((115200%CONFIG_TTYS0_BAUD) != 0)
#error Bad ttys0 baud rate
#endif
#if TTYS0_BAUD == 115200
#define TTYS0_DIV (1)
#if CONFIG_TTYS0_BAUD == 115200
#define CONFIG_TTYS0_DIV (1)
#else
#define TTYS0_DIV (115200/TTYS0_BAUD)
#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
#endif
/* Line Control Settings */
#ifndef TTYS0_LCS
#ifndef CONFIG_TTYS0_LCS
/* Set 8bit, 1 stop bit, no parity */
#define TTYS0_LCS 0x3
#define CONFIG_TTYS0_LCS 0x3
#endif
#define UART_LCS TTYS0_LCS
#define UART_LCS CONFIG_TTYS0_LCS
/* Data */
#define UART_RBR 0x00
@@ -55,7 +55,7 @@ unsigned char inb(unsigned short port)
int uart_can_tx_byte(void)
{
return inb(TTYS0_BASE + UART_LSR) & 0x20;
return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
}
void uart_wait_to_tx_byte(void)
@@ -66,14 +66,14 @@ void uart_wait_to_tx_byte(void)
void uart_wait_until_sent(void)
{
while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
static void uart_tx_byte(unsigned char data)
{
uart_wait_to_tx_byte();
outb(data, TTYS0_BASE + UART_TBR);
outb(data, CONFIG_TTYS0_BASE + UART_TBR);
/* Make certain the data clears the fifos */
uart_wait_until_sent();
}
@@ -82,14 +82,14 @@ static void uart_tx_byte(unsigned char data)
void uart_init(void)
{
/* disable interrupts */
outb(0x0, TTYS0_BASE + UART_IER);
outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
/* enable fifo's */
outb(0x01, TTYS0_BASE + UART_FCR);
outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR);
outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL);
outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM);
outb(UART_LCS, TTYS0_BASE + UART_LCR);
outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL);
outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM);
outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
}

40
util/romcc/tests/hello_world2.c
View File

@@ -9,31 +9,31 @@ unsigned char inb(unsigned short port)
}
/* Base Address */
#ifndef TTYS0_BASE
#define TTYS0_BASE 0x3f8
#ifndef CONFIG_TTYS0_BASE
#define CONFIG_TTYS0_BASE 0x3f8
#endif
#ifndef TTYS0_BAUD
#define TTYS0_BAUD 115200
#ifndef CONFIG_TTYS0_BAUD
#define CONFIG_TTYS0_BAUD 115200
#endif
#if ((115200%TTYS0_BAUD) != 0)
#if ((115200%CONFIG_TTYS0_BAUD) != 0)
#error Bad ttys0 baud rate
#endif
#if TTYS0_BAUD == 115200
#define TTYS0_DIV (1)
#if CONFIG_TTYS0_BAUD == 115200
#define CONFIG_TTYS0_DIV (1)
#else
#define TTYS0_DIV (115200/TTYS0_BAUD)
#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
#endif
/* Line Control Settings */
#ifndef TTYS0_LCS
#ifndef CONFIG_TTYS0_LCS
/* Set 8bit, 1 stop bit, no parity */
#define TTYS0_LCS 0x3
#define CONFIG_TTYS0_LCS 0x3
#endif
#define UART_LCS TTYS0_LCS
#define UART_LCS CONFIG_TTYS0_LCS
/* Data */
#define UART_RBR 0x00
@@ -55,7 +55,7 @@ unsigned char inb(unsigned short port)
int uart_can_tx_byte(void)
{
return inb(TTYS0_BASE + UART_LSR) & 0x20;
return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
}
void uart_wait_to_tx_byte(void)
@@ -66,14 +66,14 @@ void uart_wait_to_tx_byte(void)
void uart_wait_until_sent(void)
{
while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
static void uart_tx_byte(unsigned char data)
{
uart_wait_to_tx_byte();
outb(data, TTYS0_BASE + UART_TBR);
outb(data, CONFIG_TTYS0_BASE + UART_TBR);
/* Make certain the data clears the fifos */
uart_wait_until_sent();
}
@@ -82,14 +82,14 @@ static void uart_tx_byte(unsigned char data)
void uart_init(void)
{
/* disable interrupts */
outb(0x0, TTYS0_BASE + UART_IER);
outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
/* enable fifo's */
outb(0x01, TTYS0_BASE + UART_FCR);
outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR);
outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL);
outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM);
outb(UART_LCS, TTYS0_BASE + UART_LCR);
outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL);
outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM);
outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
}

36
util/romcc/tests/raminit_test.c
View File

@@ -83,27 +83,27 @@ static void pcibios_write_config_dword(
}
/* Base Address */
#ifndef TTYS0_BASE
#define TTYS0_BASE 0x3f8
#ifndef CONFIG_TTYS0_BASE
#define CONFIG_TTYS0_BASE 0x3f8
#endif
#ifndef TTYS0_BAUD
#define TTYS0_BAUD 115200
#ifndef CONFIG_TTYS0_BAUD
#define CONFIG_TTYS0_BAUD 115200
#endif
#if ((115200%TTYS0_BAUD) != 0)
#if ((115200%CONFIG_TTYS0_BAUD) != 0)
#error Bad ttys0 baud rate
#endif
#define TTYS0_DIV (115200/TTYS0_BAUD)
#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
/* Line Control Settings */
#ifndef TTYS0_LCS
#ifndef CONFIG_TTYS0_LCS
/* Set 8bit, 1 stop bit, no parity */
#define TTYS0_LCS 0x3
#define CONFIG_TTYS0_LCS 0x3
#endif
#define UART_LCS TTYS0_LCS
#define UART_LCS CONFIG_TTYS0_LCS
/* Data */
#define UART_RBR 0x00
@@ -125,7 +125,7 @@ static void pcibios_write_config_dword(
int uart_can_tx_byte(void)
{
return inb(TTYS0_BASE + UART_LSR) & 0x20;
return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
}
void uart_wait_to_tx_byte(void)
@@ -136,14 +136,14 @@ void uart_wait_to_tx_byte(void)
void uart_wait_until_sent(void)
{
while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
void uart_tx_byte(unsigned char data)
{
uart_wait_to_tx_byte();
outb(data, TTYS0_BASE + UART_TBR);
outb(data, CONFIG_TTYS0_BASE + UART_TBR);
/* Make certain the data clears the fifos */
uart_wait_until_sent();
}
@@ -151,14 +151,14 @@ void uart_tx_byte(unsigned char data)
void uart_init(void)
{
/* disable interrupts */
outb(0x0, TTYS0_BASE + UART_IER);
outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
/* enable fifo's */
outb(0x01, TTYS0_BASE + UART_FCR);
outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR);
outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL);
outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM);
outb(UART_LCS, TTYS0_BASE + UART_LCR);
outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL);
outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM);
outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
}
void __console_tx_char(unsigned char byte)

36
util/romcc/tests/raminit_test1.c
View File

@@ -83,27 +83,27 @@ static void pcibios_write_config_dword(
}
/* Base Address */
#ifndef TTYS0_BASE
#define TTYS0_BASE 0x3f8
#ifndef CONFIG_TTYS0_BASE
#define CONFIG_TTYS0_BASE 0x3f8
#endif
#ifndef TTYS0_BAUD
#define TTYS0_BAUD 115200
#ifndef CONFIG_TTYS0_BAUD
#define CONFIG_TTYS0_BAUD 115200
#endif
#if ((115200%TTYS0_BAUD) != 0)
#if ((115200%CONFIG_TTYS0_BAUD) != 0)
#error Bad ttys0 baud rate
#endif
#define TTYS0_DIV (115200/TTYS0_BAUD)
#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
/* Line Control Settings */
#ifndef TTYS0_LCS
#ifndef CONFIG_TTYS0_LCS
/* Set 8bit, 1 stop bit, no parity */
#define TTYS0_LCS 0x3
#define CONFIG_TTYS0_LCS 0x3
#endif
#define UART_LCS TTYS0_LCS
#define UART_LCS CONFIG_TTYS0_LCS
/* Data */
#define UART_RBR 0x00
@@ -125,7 +125,7 @@ static void pcibios_write_config_dword(
int uart_can_tx_byte(void)
{
return inb(TTYS0_BASE + UART_LSR) & 0x20;
return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
}
void uart_wait_to_tx_byte(void)
@@ -136,14 +136,14 @@ void uart_wait_to_tx_byte(void)
void uart_wait_until_sent(void)
{
while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
void uart_tx_byte(unsigned char data)
{
uart_wait_to_tx_byte();
outb(data, TTYS0_BASE + UART_TBR);
outb(data, CONFIG_TTYS0_BASE + UART_TBR);
/* Make certain the data clears the fifos */
uart_wait_until_sent();
}
@@ -151,14 +151,14 @@ void uart_tx_byte(unsigned char data)
void uart_init(void)
{
/* disable interrupts */
outb(0x0, TTYS0_BASE + UART_IER);
outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
/* enable fifo's */
outb(0x01, TTYS0_BASE + UART_FCR);
outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR);
outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL);
outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM);
outb(UART_LCS, TTYS0_BASE + UART_LCR);
outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL);
outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM);
outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
}
void __console_tx_char(unsigned char byte)

36
util/romcc/tests/raminit_test2.c
View File

@@ -83,27 +83,27 @@ static void pcibios_write_config_dword(
}
/* Base Address */
#ifndef TTYS0_BASE
#define TTYS0_BASE 0x3f8
#ifndef CONFIG_TTYS0_BASE
#define CONFIG_TTYS0_BASE 0x3f8
#endif
#ifndef TTYS0_BAUD
#define TTYS0_BAUD 115200
#ifndef CONFIG_TTYS0_BAUD
#define CONFIG_TTYS0_BAUD 115200
#endif
#if ((115200%TTYS0_BAUD) != 0)
#if ((115200%CONFIG_TTYS0_BAUD) != 0)
#error Bad ttys0 baud rate
#endif
#define TTYS0_DIV (115200/TTYS0_BAUD)
#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
/* Line Control Settings */
#ifndef TTYS0_LCS
#ifndef CONFIG_TTYS0_LCS
/* Set 8bit, 1 stop bit, no parity */
#define TTYS0_LCS 0x3
#define CONFIG_TTYS0_LCS 0x3
#endif
#define UART_LCS TTYS0_LCS
#define UART_LCS CONFIG_TTYS0_LCS
/* Data */
#define UART_RBR 0x00
@@ -125,7 +125,7 @@ static void pcibios_write_config_dword(
int uart_can_tx_byte(void)
{
return inb(TTYS0_BASE + UART_LSR) & 0x20;
return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
}
void uart_wait_to_tx_byte(void)
@@ -136,14 +136,14 @@ void uart_wait_to_tx_byte(void)
void uart_wait_until_sent(void)
{
while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
void uart_tx_byte(unsigned char data)
{
uart_wait_to_tx_byte();
outb(data, TTYS0_BASE + UART_TBR);
outb(data, CONFIG_TTYS0_BASE + UART_TBR);
/* Make certain the data clears the fifos */
uart_wait_until_sent();
}
@@ -151,14 +151,14 @@ void uart_tx_byte(unsigned char data)
void uart_init(void)
{
/* disable interrupts */
outb(0x0, TTYS0_BASE + UART_IER);
outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
/* enable fifo's */
outb(0x01, TTYS0_BASE + UART_FCR);
outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR);
outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL);
outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM);
outb(UART_LCS, TTYS0_BASE + UART_LCR);
outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL);
outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM);
outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
}
void __console_tx_char(unsigned char byte)

24
util/romcc/tests/simple_test.c
View File

@@ -25,27 +25,27 @@ static unsigned int config_cmd2(unsigned char bus, unsigned devfn, unsigned wher
}
/* Base Address */
#ifndef TTYS0_BASE
#define TTYS0_BASE 0x3f8
#ifndef CONFIG_TTYS0_BASE
#define CONFIG_TTYS0_BASE 0x3f8
#endif
#ifndef TTYS0_BAUD
#define TTYS0_BAUD 115200
#ifndef CONFIG_TTYS0_BAUD
#define CONFIG_TTYS0_BAUD 115200
#endif
#if ((115200%TTYS0_BAUD) != 0)
#if ((115200%CONFIG_TTYS0_BAUD) != 0)
#error Bad ttys0 baud rate
#endif
#define TTYS0_DIV (115200/TTYS0_BAUD)
#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
/* Line Control Settings */
#ifndef TTYS0_LCS
#ifndef CONFIG_TTYS0_LCS
/* Set 8bit, 1 stop bit, no parity */
#define TTYS0_LCS 0x3
#define CONFIG_TTYS0_LCS 0x3
#endif
#define UART_LCS TTYS0_LCS
#define UART_LCS CONFIG_TTYS0_LCS
/* Data */
#define UART_RBR 0x00
@@ -67,7 +67,7 @@ static unsigned int config_cmd2(unsigned char bus, unsigned devfn, unsigned wher
int uart_can_tx_byte(void)
{
return inb(TTYS0_BASE + UART_LSR) & 0x20;
return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
}
void uart_wait_to_tx_byte(void)
@@ -78,14 +78,14 @@ void uart_wait_to_tx_byte(void)
void uart_wait_until_sent(void)
{
while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
void uart_tx_byte(unsigned char data)
{
uart_wait_to_tx_byte();
outb(data, TTYS0_BASE + UART_TBR);
outb(data, CONFIG_TTYS0_BASE + UART_TBR);
/* Make certain the data clears the fifos */
uart_wait_until_sent();
}

24
util/romcc/tests/simple_test1.c
View File

@@ -25,27 +25,27 @@ static unsigned int config_cmd2(unsigned char bus, unsigned devfn, unsigned wher
}
/* Base Address */
#ifndef TTYS0_BASE
#define TTYS0_BASE 0x3f8
#ifndef CONFIG_TTYS0_BASE
#define CONFIG_TTYS0_BASE 0x3f8
#endif
#ifndef TTYS0_BAUD
#define TTYS0_BAUD 115200
#ifndef CONFIG_TTYS0_BAUD
#define CONFIG_TTYS0_BAUD 115200
#endif
#if ((115200%TTYS0_BAUD) != 0)
#if ((115200%CONFIG_TTYS0_BAUD) != 0)
#error Bad ttys0 baud rate
#endif
#define TTYS0_DIV (115200/TTYS0_BAUD)
#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
/* Line Control Settings */
#ifndef TTYS0_LCS
#ifndef CONFIG_TTYS0_LCS
/* Set 8bit, 1 stop bit, no parity */
#define TTYS0_LCS 0x3
#define CONFIG_TTYS0_LCS 0x3
#endif
#define UART_LCS TTYS0_LCS
#define UART_LCS CONFIG_TTYS0_LCS
/* Data */
#define UART_RBR 0x00
@@ -67,7 +67,7 @@ static unsigned int config_cmd2(unsigned char bus, unsigned devfn, unsigned wher
int uart_can_tx_byte(void)
{
return inb(TTYS0_BASE + UART_LSR) & 0x20;
return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
}
void uart_wait_to_tx_byte(void)
@@ -78,14 +78,14 @@ void uart_wait_to_tx_byte(void)
void uart_wait_until_sent(void)
{
while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
void uart_tx_byte(unsigned char data)
{
uart_wait_to_tx_byte();
outb(data, TTYS0_BASE + UART_TBR);
outb(data, CONFIG_TTYS0_BASE + UART_TBR);
/* Make certain the data clears the fifos */
uart_wait_until_sent();
}

36
util/romcc/tests/simple_test20.c
View File

@@ -33,27 +33,27 @@ static unsigned int pcibios_read_config_dword(
/* Base Address */
#ifndef TTYS0_BASE
#define TTYS0_BASE 0x3f8
#ifndef CONFIG_TTYS0_BASE
#define CONFIG_TTYS0_BASE 0x3f8
#endif
#ifndef TTYS0_BAUD
#define TTYS0_BAUD 115200
#ifndef CONFIG_TTYS0_BAUD
#define CONFIG_TTYS0_BAUD 115200
#endif
#if ((115200%TTYS0_BAUD) != 0)
#if ((115200%CONFIG_TTYS0_BAUD) != 0)
#error Bad ttys0 baud rate
#endif
#define TTYS0_DIV (115200/TTYS0_BAUD)
#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
/* Line Control Settings */
#ifndef TTYS0_LCS
#ifndef CONFIG_TTYS0_LCS
/* Set 8bit, 1 stop bit, no parity */
#define TTYS0_LCS 0x3
#define CONFIG_TTYS0_LCS 0x3
#endif
#define UART_LCS TTYS0_LCS
#define UART_LCS CONFIG_TTYS0_LCS
/* Data */
#define UART_RBR 0x00
@@ -75,7 +75,7 @@ static unsigned int pcibios_read_config_dword(
int uart_can_tx_byte(void)
{
return inb(TTYS0_BASE + UART_LSR) & 0x20;
return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
}
void uart_wait_to_tx_byte(void)
@@ -86,14 +86,14 @@ void uart_wait_to_tx_byte(void)
void uart_wait_until_sent(void)
{
while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
void uart_tx_byte(unsigned char data)
{
uart_wait_to_tx_byte();
outb(data, TTYS0_BASE + UART_TBR);
outb(data, CONFIG_TTYS0_BASE + UART_TBR);
/* Make certain the data clears the fifos */
uart_wait_until_sent();
}
@@ -101,14 +101,14 @@ void uart_tx_byte(unsigned char data)
void uart_init(void)
{
/* disable interrupts */
outb(0x0, TTYS0_BASE + UART_IER);
outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
/* enable fifo's */
outb(0x01, TTYS0_BASE + UART_FCR);
outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR);
outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL);
outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM);
outb(UART_LCS, TTYS0_BASE + UART_LCR);
outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL);
outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM);
outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
}
void __console_tx_char(unsigned char byte)

40
util/romcc/tests/simple_test27.c
View File

@@ -9,31 +9,31 @@ unsigned char inb(unsigned short port)
}
/* Base Address */
#ifndef TTYS0_BASE
#define TTYS0_BASE 0x3f8
#ifndef CONFIG_TTYS0_BASE
#define CONFIG_TTYS0_BASE 0x3f8
#endif
#ifndef TTYS0_BAUD
#define TTYS0_BAUD 115200
#ifndef CONFIG_TTYS0_BAUD
#define CONFIG_TTYS0_BAUD 115200
#endif
#if ((115200%TTYS0_BAUD) != 0)
#if ((115200%CONFIG_TTYS0_BAUD) != 0)
#error Bad ttys0 baud rate
#endif
#if TTYS0_BAUD == 115200
#define TTYS0_DIV (1)
#if CONFIG_TTYS0_BAUD == 115200
#define CONFIG_TTYS0_DIV (1)
#else
#define TTYS0_DIV (115200/TTYS0_BAUD)
#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
#endif
/* Line Control Settings */
#ifndef TTYS0_LCS
#ifndef CONFIG_TTYS0_LCS
/* Set 8bit, 1 stop bit, no parity */
#define TTYS0_LCS 0x3
#define CONFIG_TTYS0_LCS 0x3
#endif
#define UART_LCS TTYS0_LCS
#define UART_LCS CONFIG_TTYS0_LCS
/* Data */
#define UART_RBR 0x00
@@ -55,7 +55,7 @@ unsigned char inb(unsigned short port)
int uart_can_tx_byte(void)
{
return inb(TTYS0_BASE + UART_LSR) & 0x20;
return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
}
void uart_wait_to_tx_byte(void)
@@ -66,14 +66,14 @@ void uart_wait_to_tx_byte(void)
void uart_wait_until_sent(void)
{
while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
static void uart_tx_byte(unsigned char data)
{
uart_wait_to_tx_byte();
outb(data, TTYS0_BASE + UART_TBR);
outb(data, CONFIG_TTYS0_BASE + UART_TBR);
/* Make certain the data clears the fifos */
uart_wait_until_sent();
}
@@ -82,14 +82,14 @@ static void uart_tx_byte(unsigned char data)
void uart_init(void)
{
/* disable interrupts */
outb(0x0, TTYS0_BASE + UART_IER);
outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
/* enable fifo's */
outb(0x01, TTYS0_BASE + UART_FCR);
outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR);
outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL);
outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM);
outb(UART_LCS, TTYS0_BASE + UART_LCR);
outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL);
outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM);
outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
}

36
util/romcc/tests/simple_test4.c
View File

@@ -96,27 +96,27 @@ int log2(int value)
/* Base Address */
#ifndef TTYS0_BASE
#define TTYS0_BASE 0x3f8
#ifndef CONFIG_TTYS0_BASE
#define CONFIG_TTYS0_BASE 0x3f8
#endif
#ifndef TTYS0_BAUD
#define TTYS0_BAUD 115200
#ifndef CONFIG_TTYS0_BAUD
#define CONFIG_TTYS0_BAUD 115200
#endif
#if ((115200%TTYS0_BAUD) != 0)
#if ((115200%CONFIG_TTYS0_BAUD) != 0)
#error Bad ttys0 baud rate
#endif
#define TTYS0_DIV (115200/TTYS0_BAUD)
#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
/* Line Control Settings */
#ifndef TTYS0_LCS
#ifndef CONFIG_TTYS0_LCS
/* Set 8bit, 1 stop bit, no parity */
#define TTYS0_LCS 0x3
#define CONFIG_TTYS0_LCS 0x3
#endif
#define UART_LCS TTYS0_LCS
#define UART_LCS CONFIG_TTYS0_LCS
/* Data */
#define UART_RBR 0x00
@@ -138,7 +138,7 @@ int log2(int value)
int uart_can_tx_byte(void)
{
return inb(TTYS0_BASE + UART_LSR) & 0x20;
return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
}
void uart_wait_to_tx_byte(void)
@@ -149,14 +149,14 @@ void uart_wait_to_tx_byte(void)
void uart_wait_until_sent(void)
{
while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
void uart_tx_byte(unsigned char data)
{
uart_wait_to_tx_byte();
outb(data, TTYS0_BASE + UART_TBR);
outb(data, CONFIG_TTYS0_BASE + UART_TBR);
/* Make certain the data clears the fifos */
uart_wait_until_sent();
}
@@ -164,14 +164,14 @@ void uart_tx_byte(unsigned char data)
void uart_init(void)
{
/* disable interrupts */
outb(0x0, TTYS0_BASE + UART_IER);
outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
/* enable fifo's */
outb(0x01, TTYS0_BASE + UART_FCR);
outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR);
outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL);
outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM);
outb(UART_LCS, TTYS0_BASE + UART_LCR);
outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL);
outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM);
outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
}
void __console_tx_char(unsigned char byte)