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intel/skylake: Add kconfig option to skip Native SD Controller

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Skylake Core boot should have configurable option to skip
PCH based SD 3.0 Controller from customer/reference design.

Addition to that no unused or unnecessary should list under
device view.

BUG=chrome-os-partner:48190
BRANCH=None
TEST=Build & boot Kunimitsu and LARs.

Change-Id: Ie17fd6db01e0cabcdf605017509d809b54509a0d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 99ac17b723125822368539d0562aa35119e520fb
Original-Change-Id: I98a48f45ef442246227fd54ea021b53f824954c5
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315420
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12946
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Subrata Banik
2015-12-02 11:42:04 +05:30
committed by Patrick Georgi
parent 3fc42772bc
commit 086730b062
2 changed files with 8 additions and 0 deletions
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6
src/soc/intel/skylake/Kconfig
View File

@@ -79,6 +79,12 @@ config DCACHE_RAM_SIZE
The size of the cache-as-ram region required during bootblock The size of the cache-as-ram region required during bootblock
and/or romstage. and/or romstage.
config EXCLUDE_NATIVE_SD_INTERFACE
bool
default n
help
If you set this option to n, will not use native SD controller.
config HEAP_SIZE config HEAP_SIZE
hex hex
default 0x80000 default 0x80000

2
src/soc/intel/skylake/acpi/scs.asl
View File

@@ -70,6 +70,7 @@ Device (EMMC)
} }
} }
#if !IS_ENABLED(CONFIG_EXCLUDE_NATIVE_SD_INTERFACE)
Device (SDXC) Device (SDXC)
{ {
Name (_ADR, 0x001E0006) Name (_ADR, 0x001E0006)
@@ -123,3 +124,4 @@ Device (SDXC)
} }
} }
} }
#endif