soc/intel/*: Use SSDT to pass A4GB and A4GS

GNVS is more fragile as you need to keep struct elements in sync with
ASL code.

Change-Id: I2cd5e6b56e4a0dbbb11f4a0ac97e8f84d53b90ec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>

src/soc/intel/cannonlake/acpi.c

@@ -179,9 +179,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
 	/* Set USB2/USB3 wake enable bitmaps. */
 	gnvs->u2we = config->usb2_wake_enable_bitmap;
 	gnvs->u3we = config->usb3_wake_enable_bitmap;
-
-	/* Fill in Above 4GB MMIO resource */
-	sa_fill_gnvs(gnvs);
 }
 
 int soc_madt_sci_irq_polarity(int sci)

src/soc/intel/cannonlake/chip.c

@@ -10,6 +10,7 @@
 #include <intelblocks/irq.h>
 #include <intelblocks/itss.h>
 #include <intelblocks/pcie_rp.h>
+#include <intelblocks/systemagent.h>
 #include <intelblocks/xdci.h>
 #include <soc/intel/common/vbt.h>
 #include <soc/pci_devs.h>
@@ -176,6 +177,7 @@ static struct device_operations pci_domain_ops = {
 	.scan_bus         = &pci_domain_scan_bus,
 #if CONFIG(HAVE_ACPI_TABLES)
 	.acpi_name        = &soc_acpi_name,
+	.acpi_fill_ssdt   = ssdt_set_above_4g_pci,
 #endif
 };