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google/grunt: Override BayHub EMMC driving strength

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Careena EVT SanDisk EMMC sku has high fail rate of 0x5B reboot failure.
It'll need to increase 1.8V EMMC CLK/CMD, Data driving strength for
this issue.

CLK[6:4]
CMD,DATA[3:1]

original register value: 0x6B
enhanced: 0x7F

BUG=b:111964336
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I3db38ff12c566c258895c6643008a0472ca528bb
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/27816
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kevin Chiu
2018-08-03 18:52:18 +08:00
committed by Martin Roth
parent d87a9b8e67
commit 089b685761
3 changed files with 78 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
src/drivers/generic/bayhub/bh720.c
View File

@@ -21,28 +21,11 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include "chip.h"
#include "bh720.h"
enum {
BH720_PROTECT = 0xd0,
BH720_PROTECT_LOCK_OFF = 0,
BH720_PROTECT_LOCK_ON = BIT(0),
BH720_PROTECT_OFF = 0,
BH720_PROTECT_ON = BIT(31),
BH720_LINK_CTRL = 0x90,
BH720_LINK_CTRL_L0_ENABLE = BIT(0),
BH720_LINK_CTRL_L1_ENABLE = BIT(1),
BH720_LINK_CTRL_CLKREQ = BIT(8),
BH720_MISC2 = 0xf0,
BH720_MISC2_ASPM_DISABLE = BIT(0),
BH720_MISC2_APSM_CLKREQ_L1 = BIT(7),
BH720_MISC2_APSM_PHY_L1 = BIT(10),
BH720_MISC2_APSM_MORE = BIT(12),
BH720_RTD3_L1 = 0x3e0,
BH720_RTD3_L1_DISABLE_L1 = BIT(28),
};
__attribute__((weak)) void bh720_driving_strength(struct device *dev)
{
}
static void bh720_init(struct device *dev)
{
@@ -71,6 +54,8 @@ static void bh720_init(struct device *dev)
printk(BIOS_INFO, "BayHub BH720: Power-saving enabled (link_ctrl=%#x)\n",
pci_read_config32(dev, BH720_LINK_CTRL));
}
bh720_driving_strength(dev);
}
static struct pci_operations pci_ops = {

47
src/drivers/generic/bayhub/bh720.h Normal file
View File

@@ -0,0 +1,47 @@
/*
* Driver for BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge
*
* This file is part of the coreboot project.
*
* Copyright 2018 Google LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
enum {
BH720_PROTECT = 0xd0,
BH720_PROTECT_LOCK_OFF = 0,
BH720_PROTECT_LOCK_ON = BIT(0),
BH720_PROTECT_OFF = 0,
BH720_PROTECT_ON = BIT(31),
BH720_LINK_CTRL = 0x90,
BH720_LINK_CTRL_L0_ENABLE = BIT(0),
BH720_LINK_CTRL_L1_ENABLE = BIT(1),
BH720_LINK_CTRL_CLKREQ = BIT(8),
BH720_MISC2 = 0xf0,
BH720_MISC2_ASPM_DISABLE = BIT(0),
BH720_MISC2_APSM_CLKREQ_L1 = BIT(7),
BH720_MISC2_APSM_PHY_L1 = BIT(10),
BH720_MISC2_APSM_MORE = BIT(12),
BH720_MEM_RW_DATA = 0x200,
BH720_MEM_RW_ADR = 0x204,
BH720_MEM_ACCESS_EN = 0x208,
BH720_PCR = 0x304,
BH720_PCR_DATA_CMD_DRV_MAX = 7,
BH720_PCR_CLK_DRV_MAX = 7,
BH720_RTD3_L1 = 0x3e0,
BH720_RTD3_L1_DISABLE_L1 = BIT(28),
};
void bh720_driving_strength(struct device *dev);