soc/intel/alderlake: Update ME HFSTS register definition
Update Alder Lake CSME HFSTS registers definitions as per Intel doc #627331 revision 1.0.0, section 3.4.8. Follow up CLs will use the bit definitions for performing various checks. TEST=build and boot nivviks platform Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: I9aeee7a3b41ad59c03391207930a253ffff19ae5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69286 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Felix Held
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commit
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@@ -35,11 +35,9 @@ union me_hfsts3 {
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struct {
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u32 reserved_0: 4;
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u32 fw_sku: 3;
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u32 reserved_7: 2;
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u32 reserved_9: 2;
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u32 resered_11: 3;
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u32 resered_14: 16;
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u32 reserved_30: 2;
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u32 reserved_7_10: 4;
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u32 rpmc_status: 3;
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u32 resered_14_31: 18;
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} __packed fields;
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};
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#endif /* _ALDERLAKE_ME_H_ */
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@@ -23,7 +23,8 @@ union me_hfsts2 {
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uint32_t me_power_gate : 1;
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uint32_t ipu_needed : 1;
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uint32_t forced_safe_boot : 1;
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uint32_t rsvd1 : 2;
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uint32_t rsvd1 : 1;
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uint32_t cse_to_be_disabled : 1;
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uint32_t listener_change : 1;
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uint32_t status_data : 8;
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uint32_t current_pmevent : 4;
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@@ -58,10 +59,7 @@ union me_hfsts5 {
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uint32_t acm_done_sts : 1;
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uint32_t timeout_count : 7;
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uint32_t scrtm_indicator : 1;
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uint32_t inc_boot_guard_acm : 4;
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uint32_t inc_key_manifest : 4;
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uint32_t inc_boot_policy : 4;
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uint32_t rsvd0 : 2;
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uint32_t rsvd0 : 14;
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uint32_t start_enforcement : 1;
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} __packed fields;
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};
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@@ -78,9 +76,8 @@ union me_hfsts6 {
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uint32_t error_enforce_policy : 2;
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uint32_t measured_boot : 1;
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uint32_t verified_boot : 1;
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uint32_t boot_guard_acmsvn : 4;
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uint32_t kmsvn : 4;
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uint32_t bpmsvn : 4;
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uint32_t rsvd1 : 11;
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uint32_t manuf_lock : 1;
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uint32_t key_manifest_id : 4;
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uint32_t boot_policy_status : 1;
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uint32_t error : 1;
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