Kconfig: rename BOOT_MEDIA_SPI_BUS to BOOT_DEVICE_SPI_FLASH_BUS

Provide a default value of 0 in drivers/spi as there weren't
default values aside from specific mainboards and arch/x86.
Remove any default 0 values while noting to keep the option's
default to 0.

BUG=chrome-os-partner:56151

Change-Id: If9ef585e011a46b5cd152a03e41d545b36355a61
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16192
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>

src/mainboard/google/chell/Kconfig

@@ -32,10 +32,6 @@ config IRQ_SLOT_COUNT
 	int
 	default 18
 
-config BOOT_MEDIA_SPI_BUS
-	int
-	default 0
-
 config MAINBOARD_DIR
 	string
 	default "google/chell"

src/mainboard/google/cosmos/Kconfig

@@ -41,7 +41,7 @@ config MAINBOARD_VENDOR
 	string
 	default "Google"
 
-config BOOT_MEDIA_SPI_BUS
+config BOOT_DEVICE_SPI_FLASH_BUS
 	int
 	default 2
 

src/mainboard/google/foster/Kconfig

@@ -60,7 +60,7 @@ config FOSTER_BCT_CFG_EMMC
 
 endchoice
 
-config BOOT_MEDIA_SPI_BUS
+config BOOT_DEVICE_SPI_FLASH_BUS
 	int "SPI bus with boot media ROM"
 	range 1 7
 	depends on FOSTER_BCT_CFG_SPI

src/mainboard/google/glados/Kconfig

@@ -32,10 +32,6 @@ config IRQ_SLOT_COUNT
 	int
 	default 18
 
-config BOOT_MEDIA_SPI_BUS
-	int
-	default 0
-
 config MAINBOARD_DIR
 	string
 	default "google/glados"

src/mainboard/google/gru/Kconfig

@@ -67,7 +67,7 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
 	hex
 	default 5
 
-config BOOT_MEDIA_SPI_BUS
+config BOOT_DEVICE_SPI_FLASH_BUS
 	int
 	default 1
 

src/mainboard/google/gru/bootblock.c

@@ -63,7 +63,7 @@ void bootblock_mainboard_init(void)
 	/* Set pinmux and configure spi flashrom. */
 	write32(&rk3399_pmugrf->spi1_rxd, IOMUX_SPI1_RX);
 	write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
+	rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz);
 
 	/* Set pinmux and configure EC SPI. */
 	write32(&rk3399_grf->iomux_spi5, IOMUX_SPI5);

src/mainboard/google/lars/Kconfig

@@ -36,10 +36,6 @@ config IRQ_SLOT_COUNT
 	int
 	default 18
 
-config BOOT_MEDIA_SPI_BUS
-	int
-	default 0
-
 config MAINBOARD_DIR
 	string
 	default "google/lars"

src/mainboard/google/nyan/Kconfig

@@ -62,7 +62,7 @@ config NYAN_BCT_CFG_EMMC
 
 endchoice
 
-config BOOT_MEDIA_SPI_BUS
+config BOOT_DEVICE_SPI_FLASH_BUS
 	int "SPI bus with boot media ROM"
 	range 1 6
 	depends on NYAN_BCT_CFG_SPI

src/mainboard/google/nyan_big/Kconfig

@@ -63,7 +63,7 @@ config NYAN_BIG_BCT_CFG_EMMC
 
 endchoice
 
-config BOOT_MEDIA_SPI_BUS
+config BOOT_DEVICE_SPI_FLASH_BUS
 	int "SPI bus with boot media ROM"
 	range 1 6
 	depends on NYAN_BIG_BCT_CFG_SPI

src/mainboard/google/nyan_blaze/Kconfig

@@ -64,7 +64,7 @@ config NYAN_BLAZE_BCT_CFG_EMMC
 
 endchoice
 
-config BOOT_MEDIA_SPI_BUS
+config BOOT_DEVICE_SPI_FLASH_BUS
 	int "SPI bus with boot media ROM"
 	range 1 6
 	depends on NYAN_BLAZE_BCT_CFG_SPI

src/mainboard/google/oak/Kconfig

@@ -60,7 +60,7 @@ config DRIVER_TPM_I2C_ADDR
 	hex
 	default 0x20
 
-config BOOT_MEDIA_SPI_BUS
+config BOOT_DEVICE_SPI_FLASH_BUS
 	int
 	default 9
 

src/mainboard/google/purin/Kconfig

@@ -43,10 +43,6 @@ config MAINBOARD_VENDOR
 	string
 	default "Google"
 
-config BOOT_MEDIA_SPI_BUS
-	int
-	default 0
-
 config DRAM_SIZE_MB
 	int
 	default 256

src/mainboard/google/reef/Kconfig

@@ -12,10 +12,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select MAINBOARD_HAS_LPC_TPM
 	select SYSTEM_TYPE_LAPTOP
 
-config BOOT_MEDIA_SPI_BUS
-	int
-	default 0
-
 config CHROMEOS
 	select LID_SWITCH
 

src/mainboard/google/smaug/Kconfig

@@ -67,7 +67,7 @@ config SMAUG_BCT_CFG_EMMC
 
 endchoice
 
-config BOOT_MEDIA_SPI_BUS
+config BOOT_DEVICE_SPI_FLASH_BUS
 	int "SPI bus with boot media ROM"
 	range 1 7
 	depends on SMAUG_BCT_CFG_SPI

src/mainboard/google/urara/Kconfig

@@ -52,7 +52,7 @@ config CONSOLE_SERIAL_UART_ADDRESS
 	depends on DRIVERS_UART
 	default 0xB8101500
 
-config BOOT_MEDIA_SPI_BUS
+config BOOT_DEVICE_SPI_FLASH_BUS
 	int
 	default 1
 

src/mainboard/google/veyron/Kconfig

@@ -60,7 +60,7 @@ config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
 	int
 	default 100
 
-config BOOT_MEDIA_SPI_BUS
+config BOOT_DEVICE_SPI_FLASH_BUS
 	int
 	default 2
 

src/mainboard/google/veyron/bootblock.c

@@ -64,7 +64,7 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
+	rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz);
 
 	/* spi0 for chrome ec */
 	write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);

src/mainboard/google/veyron_brain/Kconfig

@@ -47,7 +47,7 @@ config MAINBOARD_VENDOR
 	string
 	default "Google"
 
-config BOOT_MEDIA_SPI_BUS
+config BOOT_DEVICE_SPI_FLASH_BUS
 	int
 	default 2
 

src/mainboard/google/veyron_brain/bootblock.c

@@ -66,7 +66,7 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
+	rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz);
 
 	setup_chromeos_gpios();
 }

src/mainboard/google/veyron_danger/Kconfig

@@ -48,7 +48,7 @@ config MAINBOARD_VENDOR
 	string
 	default "Google"
 
-config BOOT_MEDIA_SPI_BUS
+config BOOT_DEVICE_SPI_FLASH_BUS
 	int
 	default 2
 

src/mainboard/google/veyron_danger/bootblock.c

@@ -66,7 +66,7 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
+	rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz);
 
 	setup_chromeos_gpios();
 }

src/mainboard/google/veyron_emile/Kconfig

@@ -47,7 +47,7 @@ config MAINBOARD_VENDOR
 	string
 	default "Google"
 
-config BOOT_MEDIA_SPI_BUS
+config BOOT_DEVICE_SPI_FLASH_BUS
 	int
 	default 2
 

src/mainboard/google/veyron_emile/bootblock.c

@@ -66,7 +66,7 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
+	rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz);
 
 	setup_chromeos_gpios();
 }

src/mainboard/google/veyron_mickey/Kconfig

@@ -47,7 +47,7 @@ config MAINBOARD_VENDOR
 	string
 	default "Google"
 
-config BOOT_MEDIA_SPI_BUS
+config BOOT_DEVICE_SPI_FLASH_BUS
 	int
 	default 2
 

src/mainboard/google/veyron_mickey/bootblock.c

@@ -66,7 +66,7 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
+	rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz);
 
 	setup_chromeos_gpios();
 }

src/mainboard/google/veyron_rialto/Kconfig

@@ -47,7 +47,7 @@ config MAINBOARD_VENDOR
 	string
 	default "Google"
 
-config BOOT_MEDIA_SPI_BUS
+config BOOT_DEVICE_SPI_FLASH_BUS
 	int
 	default 2
 

src/mainboard/google/veyron_rialto/bootblock.c

@@ -68,7 +68,7 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
+	rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz);
 
 	setup_chromeos_gpios();
 }

src/mainboard/google/veyron_romy/Kconfig

@@ -47,7 +47,7 @@ config MAINBOARD_VENDOR
 	string
 	default "Google"
 
-config BOOT_MEDIA_SPI_BUS
+config BOOT_DEVICE_SPI_FLASH_BUS
 	int
 	default 2
 

src/mainboard/google/veyron_romy/bootblock.c

@@ -66,7 +66,7 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
+	rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz);
 
 	setup_chromeos_gpios();
 }