cpu/x86/lapic: Drop read/write_around aliases
Change-Id: Ia3935524e57885ca79586f1f4612020bb05956ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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		| @@ -128,7 +128,7 @@ static int lapic_start_cpu(unsigned long apicid) | ||||
| 		printk(BIOS_ERR, "ESR is 0x%x\n", lapic_read(LAPIC_ESR)); | ||||
| 		if (lapic_read(LAPIC_ESR)) { | ||||
| 			printk(BIOS_ERR, "Try to reset ESR\n"); | ||||
| 			lapic_write_around(LAPIC_ESR, 0); | ||||
| 			xapic_write_atomic(LAPIC_ESR, 0); | ||||
| 			printk(BIOS_ERR, "ESR is 0x%x\n", | ||||
| 				lapic_read(LAPIC_ESR)); | ||||
| 		} | ||||
| @@ -157,7 +157,7 @@ static int lapic_start_cpu(unsigned long apicid) | ||||
|  | ||||
| 	for (j = 1; j <= CONFIG_NUM_IPI_STARTS; j++) { | ||||
| 		printk(BIOS_SPEW, "Sending STARTUP #%d to %lu.\n", j, apicid); | ||||
| 		lapic_read_around(LAPIC_SPIV); | ||||
| 		lapic_read(LAPIC_SPIV); | ||||
| 		lapic_write(LAPIC_ESR, 0); | ||||
| 		lapic_read(LAPIC_ESR); | ||||
| 		printk(BIOS_SPEW, "After apic_write.\n"); | ||||
| @@ -185,7 +185,7 @@ static int lapic_start_cpu(unsigned long apicid) | ||||
| 		 * Due to the Pentium erratum 3AP. | ||||
| 		 */ | ||||
| 		if (maxlvt > 3) { | ||||
| 			lapic_read_around(LAPIC_SPIV); | ||||
| 			lapic_read(LAPIC_SPIV); | ||||
| 			lapic_write(LAPIC_ESR, 0); | ||||
| 		} | ||||
| 		accept_status = (lapic_read(LAPIC_ESR) & 0xEF); | ||||
|   | ||||
| @@ -40,9 +40,6 @@ static __always_inline int xapic_busy(void) | ||||
| 	return xapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; | ||||
| } | ||||
|  | ||||
| #define lapic_read_around(x) lapic_read(x) | ||||
| #define lapic_write_around(x, y) xapic_write_atomic((x), (y)) | ||||
|  | ||||
| static __always_inline uint32_t x2apic_read(unsigned int reg) | ||||
| { | ||||
| 	uint32_t value, index; | ||||
|   | ||||
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