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soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs

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Add Silicon upd settings for LPSS (GSPI/UART/I2C).

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Tan, Lean Sheng
2021-05-26 06:40:56 -07:00
committed by Patrick Georgi
parent cdb81500f1
commit 09133c78dd
3 changed files with 139 additions and 4 deletions
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17
src/soc/intel/elkhartlake/chip.h
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@@ -166,6 +166,14 @@ struct soc_intel_elkhartlake_config {
uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX];
uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX];
/*
* UARTn Default DMA/PIO Mode Enable(1)/Disable(0):
*/
uint8_t SerialIoUartDmaEnable[CONFIG_SOC_INTEL_UART_DEV_MAX];
/*
* GSPIn Default Chip Enable(1)/Disable(0):
*/
uint8_t SerialIoGSpiCsEnable[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
/*
* GSPIn Default Chip Select Mode:
* 0:Hardware Mode,
@@ -178,6 +186,15 @@ struct soc_intel_elkhartlake_config {
* 1: High
*/
uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
/*
* SerialIo I2C Pads Termination Config:
* 0x0:Hardware default,
* 0x1:None,
* 0x13:1kOhm weak pull-up,
* 0x15:5kOhm weak pull-up,
* 0x19:20kOhm weak pull-up
*/
uint8_t SerialIoI2cPadsTermination[CONFIG_SOC_INTEL_I2C_DEV_MAX];
/*
* TraceHubMode config