google/chell: copy glados to chell
Only change is renaming all occurrences of glados to chell, keeping capitalization. Change-Id: I8b1a3efd03d415f27c8872827f8687babbc539f7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/12150 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
Patrick Georgi
parent
4a6ac1e0e7
commit
09170f16a4
60
src/mainboard/google/chell/Kconfig
Normal file
60
src/mainboard/google/chell/Kconfig
Normal file
@ -0,0 +1,60 @@
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if BOARD_GOOGLE_CHELL
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select BOARD_ID_AUTO
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select BOARD_ROMSIZE_KB_16384
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select CACHE_ROM
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
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select EC_GOOGLE_CHROMEEC_LPC
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select EC_GOOGLE_CHROMEEC_MEC
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select EC_GOOGLE_CHROMEEC_PD
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select HAVE_SMI_HANDLER
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_LPC_TPM
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select MARK_GRAPHICS_MEM_WRCOMB
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select MMCONF_SUPPORT
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select MONOTONIC_TIMER_MSR
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select SOC_INTEL_SKYLAKE
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config CHROMEOS
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select CHROMEOS_RAMOOPS_DYNAMIC
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select CHROMEOS_VBNV_CMOS
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select EC_SOFTWARE_SYNC
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select LID_SWITCH
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select VBOOT_OPROM_MATTERS
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select VIRTUAL_DEV_SWITCH
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config IRQ_SLOT_COUNT
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int
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default 18
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config BOOT_MEDIA_SPI_BUS
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int
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default 0
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config MAINBOARD_DIR
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string
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default "google/chell"
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config MAINBOARD_PART_NUMBER
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string
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default "Chell"
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config MAX_CPUS
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int
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default 8
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config TPM_PIRQ
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hex
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default 0x18 # GPP_E0_IRQ
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x3
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endif
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2
src/mainboard/google/chell/Kconfig.name
Normal file
2
src/mainboard/google/chell/Kconfig.name
Normal file
@ -0,0 +1,2 @@
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config BOARD_GOOGLE_CHELL
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bool "Chell"
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36
src/mainboard/google/chell/Makefile.inc
Normal file
36
src/mainboard/google/chell/Makefile.inc
Normal file
@ -0,0 +1,36 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2015 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc.
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##
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subdirs-y += spd
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romstage-y += boardid.c
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romstage-y += pei_data.c
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verstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
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ramstage-y += boardid.c
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ramstage-y += mainboard.c
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ramstage-y += pei_data.c
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ramstage-y += ramstage.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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2
src/mainboard/google/chell/abuild.disabled
Normal file
2
src/mainboard/google/chell/abuild.disabled
Normal file
@ -0,0 +1,2 @@
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Successful builds for this board require the Skylake FSP binary and header files
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along with the Skylake microcode files from Intel.
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27
src/mainboard/google/chell/acpi/chromeos.asl
Normal file
27
src/mainboard/google/chell/acpi/chromeos.asl
Normal file
@ -0,0 +1,27 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include "../gpio.h"
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Name (OIPG, Package () {
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/* No physical recovery GPIO. */
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Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" },
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/* Firmware write protect GPIO. */
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Package () { 0x0003, 1, GPIO_PCH_WP, "INT344B:00" },
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})
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91
src/mainboard/google/chell/acpi/dptf.asl
Normal file
91
src/mainboard/google/chell/acpi/dptf.asl
Normal file
@ -0,0 +1,91 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Google Inc.
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* Copyright (C) 2015 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#define DPTF_CPU_PASSIVE 80
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#define DPTF_CPU_CRITICAL 90
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#define DPTF_CPU_ACTIVE_AC0 90
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#define DPTF_CPU_ACTIVE_AC1 80
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#define DPTF_CPU_ACTIVE_AC2 70
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#define DPTF_CPU_ACTIVE_AC3 60
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#define DPTF_CPU_ACTIVE_AC4 50
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#define DPTF_TSR0_SENSOR_ID 1
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#define DPTF_TSR0_SENSOR_NAME "Ambient"
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#define DPTF_TSR0_PASSIVE 55
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#define DPTF_TSR0_CRITICAL 70
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#define DPTF_TSR1_SENSOR_ID 2
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#define DPTF_TSR1_SENSOR_NAME "Charger"
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#define DPTF_TSR1_PASSIVE 55
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#define DPTF_TSR1_CRITICAL 70
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#define DPTF_TSR2_SENSOR_ID 3
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#define DPTF_TSR2_SENSOR_NAME "DRAM"
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#define DPTF_TSR2_PASSIVE 55
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#define DPTF_TSR2_CRITICAL 70
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#define DPTF_TSR3_SENSOR_ID 4
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#define DPTF_TSR3_SENSOR_NAME "WiFi"
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#define DPTF_TSR3_PASSIVE 55
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#define DPTF_TSR3_CRITICAL 70
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/* SKL-Y EC already has a custom charge profile based on temperature. */
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#undef DPTF_ENABLE_CHARGER
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Name (DTRT, Package () {
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/* CPU Throttle Effect on CPU */
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Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
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/* CPU Effect on Temp Sensor 0 */
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Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
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/* CPU Effect on Temp Sensor 1 */
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Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
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/* CPU Effect on Temp Sensor 2 */
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Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
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/* CPU Effect on Temp Sensor 3 */
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Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },
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})
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Name (MPPC, Package ()
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{
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0x2, /* Revision */
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Package () { /* Power Limit 1 */
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0, /* PowerLimitIndex, 0 for Power Limit 1 */
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1600, /* PowerLimitMinimum */
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6000, /* PowerLimitMaximum */
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1000, /* TimeWindowMinimum */
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1000, /* TimeWindowMaximum */
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200 /* StepSize */
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},
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Package () { /* Power Limit 2 */
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1, /* PowerLimitIndex, 1 for Power Limit 2 */
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8000, /* PowerLimitMinimum */
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8000, /* PowerLimitMaximum */
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1000, /* TimeWindowMinimum */
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1000, /* TimeWindowMaximum */
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1000 /* StepSize */
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}
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})
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/* Include DPTF */
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#include <soc/intel/skylake/acpi/dptf/dptf.asl>
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34
src/mainboard/google/chell/acpi/ec.asl
Normal file
34
src/mainboard/google/chell/acpi/ec.asl
Normal file
@ -0,0 +1,34 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Google Inc.
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*
|
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* This program is free software; you can redistribute it and/or modify
|
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; version 2 of the License.
|
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*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc.
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*/
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/* mainboard configuration */
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#include "../ec.h"
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#include "../gpio.h"
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/* Enable EC backed ALS device in ACPI */
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#define EC_ENABLE_ALS_DEVICE
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/* Enable EC backed Keyboard Backlight in ACPI */
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#define EC_ENABLE_KEYBOARD_BACKLIGHT
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/* Enable EC backed PD MCU device in ACPI */
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#define EC_ENABLE_PD_MCU_DEVICE
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/* ACPI code for EC functions */
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#include <ec/google/chromeec/acpi/ec.asl>
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251
src/mainboard/google/chell/acpi/mainboard.asl
Normal file
251
src/mainboard/google/chell/acpi/mainboard.asl
Normal file
@ -0,0 +1,251 @@
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/*
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* This file is part of the coreboot project.
|
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*
|
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* Copyright (C) 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
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*/
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|
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#include "../gpio.h"
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#define BOARD_TOUCHPAD_I2C_ADDR 0x15
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#define BOARD_TOUCHPAD_IRQ TOUCHPAD_INT_L
|
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|
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#define BOARD_TOUCHSCREEN_I2C_ADDR 0x10
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#define BOARD_TOUCHSCREEN_IRQ TOUCHSCREEN_INT_L
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#define BOARD_HP_MIC_CODEC_I2C_ADDR 0x1a
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#define BOARD_HP_MIC_CODEC_IRQ MIC_INT_L
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#define BOARD_LEFT_SPEAKER_AMP_I2C_ADDR 0x34
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#define BOARD_RIGHT_SPEAKER_AMP_I2C_ADDR 0x35
|
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|
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Scope (\_SB)
|
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{
|
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Device (LID0)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0D"))
|
||||
Method (_LID, 0)
|
||||
{
|
||||
Return (\_SB.PCI0.LPCB.EC0.LIDS)
|
||||
}
|
||||
|
||||
Name (_PRW, Package () { GPE_EC_WAKE, 5 })
|
||||
}
|
||||
|
||||
Device (PWRB)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0C"))
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* LPC Trusted Platform Module
|
||||
*/
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
#include <drivers/pc80/tpm/acpi/tpm.asl>
|
||||
}
|
||||
|
||||
/*
|
||||
* WLAN connected to Root Port 1
|
||||
*/
|
||||
Scope (\_SB.PCI0.RP01)
|
||||
{
|
||||
Device (WLAN)
|
||||
{
|
||||
Name (_ADR, 0x00000000)
|
||||
Name (_DDN, "Wireless LAN")
|
||||
Name (_PRW, Package () { GPE_WLAN_WAKE, 3 })
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_SB.PCI0.I2C0)
|
||||
{
|
||||
/* Touchscreen */
|
||||
Device (ELTS)
|
||||
{
|
||||
Name (_HID, "ELAN0001")
|
||||
Name (_DDN, "Elan Touchscreen")
|
||||
Name (_UID, 1)
|
||||
Name (_S0W, 4)
|
||||
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
I2cSerialBus (
|
||||
BOARD_TOUCHSCREEN_I2C_ADDR,
|
||||
ControllerInitiated,
|
||||
400000,
|
||||
AddressingMode7Bit,
|
||||
"\\_SB.PCI0.I2C0",
|
||||
)
|
||||
Interrupt (ResourceConsumer, Edge, ActiveLow)
|
||||
{
|
||||
BOARD_TOUCHSCREEN_IRQ
|
||||
}
|
||||
})
|
||||
|
||||
Method (_STA)
|
||||
{
|
||||
Return (0xF)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_SB.PCI0.I2C1)
|
||||
{
|
||||
/* Touchpad */
|
||||
Device (ELTP)
|
||||
{
|
||||
Name (_HID, "ELAN0000")
|
||||
Name (_DDN, "Elan Touchpad")
|
||||
Name (_UID, 1)
|
||||
Name (_S0W, 4)
|
||||
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
I2cSerialBus (
|
||||
BOARD_TOUCHPAD_I2C_ADDR,
|
||||
ControllerInitiated,
|
||||
400000,
|
||||
AddressingMode7Bit,
|
||||
"\\_SB.PCI0.I2C1",
|
||||
)
|
||||
Interrupt (ResourceConsumer, Edge, ActiveLow)
|
||||
{
|
||||
BOARD_TOUCHPAD_IRQ
|
||||
}
|
||||
})
|
||||
|
||||
Method (_STA)
|
||||
{
|
||||
Return (0xF)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_SB.PCI0.I2C4)
|
||||
{
|
||||
/* Headphone Codec */
|
||||
Device (HPMC)
|
||||
{
|
||||
Name (_HID, "10508825")
|
||||
Name (_DDN, "NAU88L25 Codec")
|
||||
Name (_UID, 1)
|
||||
|
||||
/*
|
||||
* Add DT style bindings with _DSD
|
||||
* Device property values are documented in kernel doc
|
||||
* Documentation/devicetree/bindings/sound/nau8825.txt
|
||||
*/
|
||||
Name (_DSD, Package () {
|
||||
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package () {
|
||||
/* Enable jack detection via JKDET pin */
|
||||
Package () {"nuvoton,jkdet-enable", 1},
|
||||
/*
|
||||
* JKDET pin is pulled up by R389 on board.
|
||||
* JKDET pin polarity = active low
|
||||
*/
|
||||
Package () {"nuvoton,jkdet-polarity", 1},
|
||||
/* VREF Impedance = 125 kOhm */
|
||||
Package () {"nuvoton,vref-impedance", 2},
|
||||
/* VDDA(1.8) * 1.53 = 2.754 */
|
||||
Package () {"nuvoton,micbias-voltage", 6},
|
||||
/*
|
||||
* Setup 4 buttons impedance according to
|
||||
* Android specification
|
||||
*/
|
||||
Package () {"nuvoton,sar-threshold-num", 4},
|
||||
Package () {"nuvoton,sar-threshold",
|
||||
Package () {0xc, 0x1e, 0x38, 0x60}},
|
||||
Package () {"nuvoton,sar-hysteresis", 1},
|
||||
/* VDDA for button impedance measurement */
|
||||
Package () {"nuvoton,sar-voltage", 0},
|
||||
/* 100ms short key press debounce */
|
||||
Package () {"nuvoton,short-key-debounce", 2},
|
||||
/* 2^(7+2) = 512 ms insert/eject debounce */
|
||||
Package () {"nuvoton,jack-insert-debounce", 7},
|
||||
Package () {"nuvoton,jack-eject-debounce", 7},
|
||||
}
|
||||
})
|
||||
|
||||
Name (_CRS, ResourceTemplate()
|
||||
{
|
||||
I2cSerialBus (
|
||||
BOARD_HP_MIC_CODEC_I2C_ADDR,
|
||||
ControllerInitiated,
|
||||
400000,
|
||||
AddressingMode7Bit,
|
||||
"\\_SB.PCI0.I2C4",
|
||||
)
|
||||
Interrupt (ResourceConsumer, Level, ActiveLow)
|
||||
{
|
||||
BOARD_HP_MIC_CODEC_IRQ
|
||||
}
|
||||
})
|
||||
|
||||
Method (_STA)
|
||||
{
|
||||
Return (0xF)
|
||||
}
|
||||
}
|
||||
|
||||
/* Left Speaker Amp */
|
||||
Device (SPKL)
|
||||
{
|
||||
Name (_HID, "INT343B")
|
||||
Name (_DDN, "SSM4567 Speaker Amp")
|
||||
Name (_UID, 0)
|
||||
|
||||
Name (_CRS, ResourceTemplate()
|
||||
{
|
||||
I2cSerialBus (
|
||||
BOARD_LEFT_SPEAKER_AMP_I2C_ADDR,
|
||||
ControllerInitiated,
|
||||
400000,
|
||||
AddressingMode7Bit,
|
||||
"\\_SB.PCI0.I2C4",
|
||||
)
|
||||
})
|
||||
|
||||
Method (_STA)
|
||||
{
|
||||
Return (0xF)
|
||||
}
|
||||
}
|
||||
|
||||
/* Right Speaker Amp */
|
||||
Device (SPKR)
|
||||
{
|
||||
Name (_HID, "INT343B")
|
||||
Name (_DDN, "SSM4567 Speaker Amp")
|
||||
Name (_UID, 1)
|
||||
|
||||
Name (_CRS, ResourceTemplate()
|
||||
{
|
||||
I2cSerialBus (
|
||||
BOARD_RIGHT_SPEAKER_AMP_I2C_ADDR,
|
||||
ControllerInitiated,
|
||||
400000,
|
||||
AddressingMode7Bit,
|
||||
"\\_SB.PCI0.I2C4",
|
||||
)
|
||||
})
|
||||
|
||||
Method (_STA)
|
||||
{
|
||||
Return (0xF)
|
||||
}
|
||||
}
|
||||
}
|
||||
28
src/mainboard/google/chell/acpi/superio.asl
Normal file
28
src/mainboard/google/chell/acpi/superio.asl
Normal file
@ -0,0 +1,28 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
/* mainboard configuration */
|
||||
#include "../ec.h"
|
||||
|
||||
#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
|
||||
#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
|
||||
#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
|
||||
|
||||
/* ACPI code for EC SuperIO functions */
|
||||
#include <ec/google/chromeec/acpi/superio.asl>
|
||||
19
src/mainboard/google/chell/acpi_tables.c
Normal file
19
src/mainboard/google/chell/acpi_tables.c
Normal file
@ -0,0 +1,19 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
32
src/mainboard/google/chell/boardid.c
Normal file
32
src/mainboard/google/chell/boardid.c
Normal file
@ -0,0 +1,32 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
#include <boardid.h>
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
|
||||
uint8_t board_id(void)
|
||||
{
|
||||
MAYBE_STATIC int id = -1;
|
||||
|
||||
if (id < 0)
|
||||
id = google_chromeec_get_board_version();
|
||||
|
||||
return id;
|
||||
}
|
||||
95
src/mainboard/google/chell/chromeos.c
Normal file
95
src/mainboard/google/chell/chromeos.c
Normal file
@ -0,0 +1,95 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <rules.h>
|
||||
#include <gpio.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <string.h>
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
|
||||
#include "gpio.h"
|
||||
#include "ec.h"
|
||||
|
||||
#if ENV_RAMSTAGE
|
||||
#include <boot/coreboot_tables.h>
|
||||
|
||||
void fill_lb_gpios(struct lb_gpios *gpios)
|
||||
{
|
||||
struct lb_gpio *start_gpio = gpios->gpios;
|
||||
struct lb_gpio *gpio = start_gpio;
|
||||
|
||||
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect",
|
||||
get_write_protect_state());
|
||||
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery",
|
||||
get_recovery_mode_switch());
|
||||
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer",
|
||||
get_developer_mode_switch());
|
||||
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid",
|
||||
get_lid_switch());
|
||||
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0);
|
||||
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done());
|
||||
fill_lb_gpio(gpio++, GPIO_EC_IN_RW, ACTIVE_HIGH, "EC in RW",
|
||||
gpio_get(GPIO_EC_IN_RW));
|
||||
|
||||
gpios->count = gpio - start_gpio;
|
||||
gpios->size = sizeof(*gpios) + (gpios->count * sizeof(*gpio));
|
||||
}
|
||||
#endif /* ENV_RAMSTAGE */
|
||||
|
||||
int get_lid_switch(void)
|
||||
{
|
||||
/* Read lid switch state from the EC. */
|
||||
return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN);
|
||||
}
|
||||
|
||||
int get_developer_mode_switch(void)
|
||||
{
|
||||
/* No physical developer mode switch. */
|
||||
return 0;
|
||||
}
|
||||
|
||||
int get_recovery_mode_switch(void)
|
||||
{
|
||||
/* Check for dedicated recovery switch first. */
|
||||
if (google_chromeec_get_switches() & EC_SWITCH_DEDICATED_RECOVERY)
|
||||
return 1;
|
||||
|
||||
/* Otherwise check if the EC has posted the keyboard recovery event. */
|
||||
return !!(google_chromeec_get_events_b() &
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
|
||||
}
|
||||
|
||||
int clear_recovery_mode_switch(void)
|
||||
{
|
||||
/* Clear keyboard recovery event. */
|
||||
return google_chromeec_clear_events_b(
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
|
||||
}
|
||||
|
||||
int get_write_protect_state(void)
|
||||
{
|
||||
/* Read PCH_WP GPIO. */
|
||||
return gpio_get(GPIO_PCH_WP);
|
||||
}
|
||||
140
src/mainboard/google/chell/cmos.layout
Normal file
140
src/mainboard/google/chell/cmos.layout
Normal file
@ -0,0 +1,140 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007-2008 coresystems GmbH
|
||||
## Copyright (C) 2015 Intel Corporation
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc.
|
||||
##
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register A
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register B
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register C
|
||||
#96 4 r 0 status_c_rsvd
|
||||
#100 1 r 0 uf_flag
|
||||
#101 1 r 0 af_flag
|
||||
#102 1 r 0 pf_flag
|
||||
#103 1 r 0 irqf_flag
|
||||
# -----------------------------------------------------------------
|
||||
# Status Register D
|
||||
#104 7 r 0 status_d_rsvd
|
||||
#111 1 r 0 valid_cmos_ram
|
||||
# -----------------------------------------------------------------
|
||||
# Diagnostic Status Register
|
||||
#112 8 r 0 diag_rsvd1
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
0 120 r 0 reserved_memory
|
||||
#120 264 r 0 unused
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
388 4 r 0 reboot_bits
|
||||
#390 2 r 0 unused?
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# coreboot config options: console
|
||||
392 3 e 5 baud_rate
|
||||
395 4 e 6 debug_level
|
||||
#399 1 r 0 unused
|
||||
|
||||
# coreboot config options: cpu
|
||||
400 1 e 2 hyper_threading
|
||||
#401 7 r 0 unused
|
||||
|
||||
# coreboot config options: southbridge
|
||||
408 1 e 1 nmi
|
||||
409 2 e 7 power_on_after_fail
|
||||
#411 5 r 0 unused
|
||||
|
||||
# coreboot config options: bootloader
|
||||
#Used by ChromeOS:
|
||||
416 128 r 0 vbnv
|
||||
#544 440 r 0 unused
|
||||
|
||||
# SandyBridge MRC Scrambler Seed values
|
||||
896 32 r 0 mrc_scrambler_seed
|
||||
928 32 r 0 mrc_scrambler_seed_s3
|
||||
|
||||
# coreboot config options: check sums
|
||||
984 16 h 0 check_sum
|
||||
#1000 24 r 0 amd_reserved
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 1 Emergency
|
||||
6 2 Alert
|
||||
6 3 Critical
|
||||
6 4 Error
|
||||
6 5 Warning
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Disable
|
||||
7 1 Enable
|
||||
7 2 Keep
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
checksum 392 415 984
|
||||
|
||||
|
||||
175
src/mainboard/google/chell/devicetree.cb
Normal file
175
src/mainboard/google/chell/devicetree.cb
Normal file
@ -0,0 +1,175 @@
|
||||
chip soc/intel/skylake
|
||||
|
||||
# Enable deep Sx states
|
||||
register "deep_s3_enable" = "1"
|
||||
register "deep_s5_enable" = "1"
|
||||
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
|
||||
|
||||
# GPE configuration
|
||||
# Note that GPE events called out in ASL code rely on this
|
||||
# route. i.e. If this route changes then the affected GPE
|
||||
# offset bits also need to be changed.
|
||||
register "gpe0_dw0" = "GPP_B"
|
||||
register "gpe0_dw1" = "GPP_D"
|
||||
register "gpe0_dw2" = "GPP_E"
|
||||
|
||||
# EC host command range is in 0x800-0x8ff
|
||||
register "gen1_dec" = "0x00fc0801"
|
||||
|
||||
# Enable DPTF
|
||||
register "dptf_enable" = "1"
|
||||
|
||||
# FSP Configuration
|
||||
register "ProbelessTrace" = "0"
|
||||
register "EnableLan" = "0"
|
||||
register "EnableSata" = "0"
|
||||
register "SataSalpSupport" = "0"
|
||||
register "SataMode" = "0"
|
||||
register "SataPortsEnable[0]" = "0"
|
||||
register "EnableAzalia" = "1"
|
||||
register "DspEnable" = "1"
|
||||
register "IoBufferOwnership" = "3"
|
||||
register "EnableTraceHub" = "0"
|
||||
register "XdciEnable" = "0"
|
||||
register "SsicPortEnable" = "0"
|
||||
register "SmbusEnable" = "1"
|
||||
register "Cio2Enable" = "0"
|
||||
register "ScsEmmcEnabled" = "1"
|
||||
register "ScsEmmcHs400Enabled" = "1"
|
||||
register "ScsSdCardEnabled" = "2"
|
||||
register "IshEnable" = "0"
|
||||
register "PttSwitch" = "0"
|
||||
register "InternalGfx" = "1"
|
||||
register "SkipExtGfxScan" = "1"
|
||||
register "Device4Enable" = "1"
|
||||
|
||||
# Enable Root port 1 and 5.
|
||||
register "PcieRpEnable[0]" = "1"
|
||||
register "PcieRpEnable[4]" = "1"
|
||||
# Enable CLKREQ#
|
||||
register "PcieRpClkReqSupport[0]" = "1"
|
||||
register "PcieRpClkReqSupport[4]" = "1"
|
||||
# RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2#
|
||||
register "PcieRpClkReqNumber[0]" = "1"
|
||||
register "PcieRpClkReqNumber[4]" = "2"
|
||||
|
||||
register "PortUsb20Enable[0]" = "1" # Type-C Port 1
|
||||
register "PortUsb20Enable[1]" = "1" # Type-C Port 2
|
||||
register "PortUsb20Enable[2]" = "1" # Bluetooth
|
||||
register "PortUsb20Enable[4]" = "1" # Type-A Port 1
|
||||
register "PortUsb20Enable[6]" = "1" # Camera
|
||||
register "PortUsb20Enable[8]" = "1" # Type-A Port 2
|
||||
|
||||
register "PortUsb30Enable[0]" = "1" # Type-C Port 1
|
||||
register "PortUsb30Enable[1]" = "1" # Type-C Port 2
|
||||
register "PortUsb30Enable[2]" = "1" # Type-A Port 1
|
||||
register "PortUsb30Enable[3]" = "1" # Type-A Port 2
|
||||
|
||||
# USB Per Port HS Preemphasis Bias
|
||||
register "Usb2AfePetxiset" = "{ 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, \
|
||||
0x07, 0x07, 0x07, 0x07, 0x07, 0x07, \
|
||||
0x07, 0x07, 0x07, 0x07 }"
|
||||
|
||||
# USB Per Port HS Transmitter Bias
|
||||
register "Usb2AfeTxiset" = "{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x05, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00 }"
|
||||
|
||||
# USB Per Port HS Transmitter Emphasis
|
||||
register "Usb2AfePredeemp" = "{ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, \
|
||||
0x02, 0x02, 0x02, 0x02, 0x03, 0x03, \
|
||||
0x03, 0x03, 0x03, 0x03 }"
|
||||
|
||||
# USB Per Port Half Bit Pre-emphasis
|
||||
register "Usb2AfePehalfbit" = "{ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, \
|
||||
0x01, 0x01, 0x01, 0x01, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00 }"
|
||||
|
||||
# Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
|
||||
register "Usb3HsioTxDeEmphEnable" = "{ 0x00, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x00 }"
|
||||
|
||||
# USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
|
||||
register "Usb3HsioTxDeEmph" = "{ 0x00, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x00 }"
|
||||
|
||||
# Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
|
||||
register "Usb3HsioTxDownscaleAmpEnable" = "{ 0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00 }"
|
||||
|
||||
# USB 3.0 TX Output Downscale Amplitude Adjustment
|
||||
register "Usb3HsioTxDownscaleAmp" = "{ 0x00, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x00 }"
|
||||
|
||||
# Must leave UART0 enabled or SD/eMMC will not work as PCI
|
||||
register "SerialIoDevMode" = "{ \
|
||||
[PchSerialIoIndexI2C0] = PchSerialIoPci, \
|
||||
[PchSerialIoIndexI2C1] = PchSerialIoPci, \
|
||||
[PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
|
||||
[PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
|
||||
[PchSerialIoIndexI2C4] = PchSerialIoPci, \
|
||||
[PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
|
||||
[PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
|
||||
[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
|
||||
[PchSerialIoIndexUart0] = PchSerialIoPci, \
|
||||
[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
|
||||
[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
|
||||
}"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
device pci 14.0 on end # USB xHCI
|
||||
device pci 14.1 off end # USB xDCI (OTG)
|
||||
device pci 14.2 on end # Thermal Subsystem
|
||||
device pci 15.0 on end # I2C #0
|
||||
device pci 15.1 on end # I2C #1
|
||||
device pci 15.2 off end # I2C #2
|
||||
device pci 15.3 off end # I2C #3
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT Redirection
|
||||
device pci 16.4 off end # Management Engine Interface 3
|
||||
device pci 17.0 off end # SATA
|
||||
device pci 19.0 on end # UART #2
|
||||
device pci 19.1 off end # I2C #5
|
||||
device pci 19.2 on end # I2C #4
|
||||
device pci 1c.0 on end # PCI Express Port 1
|
||||
device pci 1c.1 off end # PCI Express Port 2
|
||||
device pci 1c.2 off end # PCI Express Port 3
|
||||
device pci 1c.3 off end # PCI Express Port 4
|
||||
device pci 1c.4 on end # PCI Express Port 5
|
||||
device pci 1c.5 off end # PCI Express Port 6
|
||||
device pci 1c.6 off end # PCI Express Port 7
|
||||
device pci 1c.7 off end # PCI Express Port 8
|
||||
device pci 1d.0 off end # PCI Express Port 9
|
||||
device pci 1d.1 off end # PCI Express Port 10
|
||||
device pci 1d.2 off end # PCI Express Port 11
|
||||
device pci 1d.3 off end # PCI Express Port 12
|
||||
device pci 1e.0 on end # UART #0
|
||||
device pci 1e.1 off end # UART #1
|
||||
device pci 1e.2 off end # GSPI #0
|
||||
device pci 1e.3 off end # GSPI #1
|
||||
device pci 1e.4 on end # eMMC
|
||||
device pci 1e.5 off end # SDIO
|
||||
device pci 1e.6 on end # SDCard
|
||||
device pci 1f.0 on
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
chip ec/google/chromeec
|
||||
device pnp 0c09.0 on end
|
||||
end
|
||||
end # LPC Interface
|
||||
device pci 1f.2 on end # Power Management Controller
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
end
|
||||
end
|
||||
60
src/mainboard/google/chell/dsdt.asl
Normal file
60
src/mainboard/google/chell/dsdt.asl
Normal file
@ -0,0 +1,60 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x05, // DSDT revision: ACPI v5.0
|
||||
"COREv4", // OEM id
|
||||
"COREBOOT", // OEM table id
|
||||
0x20110725 // OEM revision
|
||||
)
|
||||
{
|
||||
// Some generic macros
|
||||
#include <soc/intel/skylake/acpi/platform.asl>
|
||||
|
||||
// global NVS and variables
|
||||
#include <soc/intel/skylake/acpi/globalnvs.asl>
|
||||
|
||||
// CPU
|
||||
#include <soc/intel/skylake/acpi/cpu.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <soc/intel/skylake/acpi/systemagent.asl>
|
||||
#include <soc/intel/skylake/acpi/pch.asl>
|
||||
}
|
||||
|
||||
// Dynamic Platform Thermal Framework
|
||||
#include "acpi/dptf.asl"
|
||||
}
|
||||
|
||||
// Chrome OS specific
|
||||
#include "acpi/chromeos.asl"
|
||||
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
|
||||
|
||||
// Chipset specific sleep states
|
||||
#include <soc/intel/skylake/acpi/sleepstates.asl>
|
||||
|
||||
// Mainboard specific
|
||||
#include "acpi/mainboard.asl"
|
||||
}
|
||||
50
src/mainboard/google/chell/ec.c
Normal file
50
src/mainboard/google/chell/ec.c
Normal file
@ -0,0 +1,50 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
#include <console/console.h>
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
#include "ec.h"
|
||||
|
||||
void mainboard_ec_init(void)
|
||||
{
|
||||
printk(BIOS_DEBUG, "mainboard: EC init\n");
|
||||
|
||||
if (acpi_is_wakeup_s3()) {
|
||||
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
|
||||
MAINBOARD_EC_S3_WAKE_EVENTS);
|
||||
|
||||
/* Disable SMI and wake events */
|
||||
google_chromeec_set_smi_mask(0);
|
||||
|
||||
/* Clear pending events */
|
||||
while (google_chromeec_get_event() != 0)
|
||||
;
|
||||
|
||||
/* Restore SCI event mask */
|
||||
google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
|
||||
} else {
|
||||
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
|
||||
MAINBOARD_EC_S5_WAKE_EVENTS);
|
||||
}
|
||||
|
||||
/* Clear wake event mask */
|
||||
google_chromeec_set_wake_mask(0);
|
||||
}
|
||||
65
src/mainboard/google/chell/ec.h
Normal file
65
src/mainboard/google/chell/ec.h
Normal file
@ -0,0 +1,65 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_EC_H
|
||||
#define MAINBOARD_EC_H
|
||||
|
||||
#include <ec/google/chromeec/ec_commands.h>
|
||||
|
||||
#define MAINBOARD_EC_SCI_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU))
|
||||
|
||||
#define MAINBOARD_EC_SMI_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
|
||||
|
||||
/* EC can wake from S5 with lid or power button */
|
||||
#define MAINBOARD_EC_S5_WAKE_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
|
||||
|
||||
/* EC can wake from S3 with lid or power button or key press */
|
||||
#define MAINBOARD_EC_S3_WAKE_EVENTS \
|
||||
(MAINBOARD_EC_S5_WAKE_EVENTS |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
|
||||
|
||||
/* Log EC wake events plus EC shutdown events */
|
||||
#define MAINBOARD_EC_LOG_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
|
||||
|
||||
#ifndef __ACPI__
|
||||
extern void mainboard_ec_init(void);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
51
src/mainboard/google/chell/fadt.c
Normal file
51
src/mainboard/google/chell/fadt.c
Normal file
@ -0,0 +1,51 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <soc/acpi.h>
|
||||
|
||||
void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
|
||||
{
|
||||
acpi_header_t *header = &(fadt->header);
|
||||
|
||||
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
|
||||
memcpy(header->signature, "FACP", 4);
|
||||
header->length = sizeof(acpi_fadt_t);
|
||||
header->revision = 5;
|
||||
memcpy(header->oem_id, OEM_ID, 6);
|
||||
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
|
||||
memcpy(header->asl_compiler_id, ASLC, 4);
|
||||
header->asl_compiler_revision = 1;
|
||||
|
||||
fadt->firmware_ctrl = (unsigned long) facs;
|
||||
fadt->dsdt = (unsigned long) dsdt;
|
||||
fadt->model = 1;
|
||||
fadt->preferred_pm_profile = PM_MOBILE;
|
||||
|
||||
fadt->x_firmware_ctl_l = (unsigned long)facs;
|
||||
fadt->x_firmware_ctl_h = 0;
|
||||
fadt->x_dsdt_l = (unsigned long)dsdt;
|
||||
fadt->x_dsdt_h = 0;
|
||||
|
||||
acpi_fill_in_fadt(fadt);
|
||||
|
||||
header->checksum = acpi_checksum((void *) fadt, header->length);
|
||||
}
|
||||
235
src/mainboard/google/chell/gpio.h
Normal file
235
src/mainboard/google/chell/gpio.h
Normal file
@ -0,0 +1,235 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* EC in RW */
|
||||
#define GPIO_EC_IN_RW GPP_C6
|
||||
|
||||
/* BIOS Flash Write Protect */
|
||||
#define GPIO_PCH_WP GPP_C23
|
||||
|
||||
/* Memory configuration board straps */
|
||||
#define GPIO_MEM_CONFIG_0 GPP_C12
|
||||
#define GPIO_MEM_CONFIG_1 GPP_C13
|
||||
#define GPIO_MEM_CONFIG_2 GPP_C14
|
||||
#define GPIO_MEM_CONFIG_3 GPP_C15
|
||||
|
||||
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
|
||||
#define GPE_EC_WAKE GPE0_LAN_WAK
|
||||
|
||||
/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */
|
||||
#define GPE_WLAN_WAKE GPE0_DW0_16
|
||||
|
||||
/* Input device interrupt configuration */
|
||||
#define TOUCHPAD_INT_L GPP_B3_IRQ
|
||||
#define TOUCHSCREEN_INT_L GPP_E7_IRQ
|
||||
#define MIC_INT_L GPP_F10_IRQ
|
||||
|
||||
/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */
|
||||
#define EC_SCI_GPI GPE0_DW2_16
|
||||
#define EC_SMI_GPI GPP_E15
|
||||
|
||||
#ifndef __ACPI__
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
|
||||
/* LAD0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
|
||||
/* LAD1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
|
||||
/* LAD2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
|
||||
/* LAD3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
|
||||
/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||
/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
/* PIRQA# */ /* GPP_A7 */
|
||||
/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||
/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
|
||||
/* CLKOUT_LPC1 */ /* GPP_A10 */
|
||||
/* PME# */ /* GPP_A11 */
|
||||
/* BM_BUSY# */ /* GPP_A12 */
|
||||
/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
|
||||
/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
|
||||
/* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
|
||||
/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
|
||||
/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
|
||||
/* ISH_GP0 */ /* GPP_A18 */
|
||||
/* ISH_GP1 */ /* GPP_A19 */
|
||||
/* ISH_GP2 */ /* GPP_A20 */
|
||||
/* ISH_GP3 */ /* GPP_A21 */
|
||||
/* ISH_GP4 */ /* GPP_A22 */
|
||||
/* ISH_GP5 */ /* GPP_A23 */
|
||||
/* CORE_VID0 */ /* GPP_B0 */
|
||||
/* CORE_VID1 */ /* GPP_B1 */
|
||||
/* VRALERT# */ /* GPP_B2 */
|
||||
/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), /* TRACKPAD */
|
||||
/* CPU_GP3 */ /* GPP_B4 */
|
||||
/* SRCCLKREQ0# */ /* GPP_B5 */
|
||||
/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN */
|
||||
/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
|
||||
/* SRCCLKREQ3# */ /* GPP_B8 */
|
||||
/* SRCCLKREQ4# */ /* GPP_B9 */
|
||||
/* SRCCLKREQ5# */ /* GPP_B10 */
|
||||
/* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
|
||||
/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
/* SPKR */ /* GPP_B14 */
|
||||
/* GSPI0_CS# */ /* GPP_B15 */
|
||||
/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */
|
||||
/* GSPI0_MISO */ /* GPP_B17 */
|
||||
/* GSPI0_MOSI */ /* GPP_B18 */
|
||||
/* GSPI1_CS# */ /* GPP_B19 */
|
||||
/* GSPI1_CLK */ /* GPP_B20 */
|
||||
/* GSPI1_MISO */ /* GPP_B21 */
|
||||
/* GSPI1_MOSI */ /* GPP_B22 */
|
||||
/* SM1ALERT# */ /* GPP_B23 */
|
||||
/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */
|
||||
/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */
|
||||
/* SMBALERT# */ /* GPP_C2 */
|
||||
/* SML0CLK */ /* GPP_C3 */
|
||||
/* SML0DATA */ /* GPP_C4 */
|
||||
/* SML0ALERT# */ /* GPP_C5 */
|
||||
/* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
|
||||
/* SM1DATA */ /* GPP_C7 */
|
||||
/* UART0_RXD */ /* GPP_C8 */
|
||||
/* UART0_TXD */ /* GPP_C9 */
|
||||
/* UART0_RTS# */ /* GPP_C10 */
|
||||
/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */
|
||||
/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
|
||||
/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
|
||||
/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */
|
||||
/* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */
|
||||
/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */
|
||||
/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */
|
||||
/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TRACKPAD */
|
||||
/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TRACKPAD */
|
||||
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
|
||||
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
|
||||
/* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */
|
||||
/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
|
||||
/* GPP_D0 */
|
||||
/* GPP_D1 */
|
||||
/* GPP_D2 */
|
||||
/* GPP_D3 */
|
||||
/* FASHTRIG */ /* GPP_D4 */
|
||||
/* ISH_I2C0_SDA */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */
|
||||
/* ISH_I2C0_SCL */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */
|
||||
/* ISH_I2C1_SDA */ /* GPP_D7 */
|
||||
/* ISH_I2C1_SCL */ /* GPP_D8 */
|
||||
/* GPP_D9 */
|
||||
PAD_CFG_GPO(GPP_D10, 1, DEEP), /* USBA_1_ILIM_SEL_L */
|
||||
PAD_CFG_GPO(GPP_D11, 1, DEEP), /* USBA_2_ILIM_SEL_L */
|
||||
PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */
|
||||
/* ISH_UART0_RXD */ /* GPP_D13 */
|
||||
/* ISH_UART0_TXD */ /* GPP_D14 */
|
||||
/* ISH_UART0_RTS# */ /* GPP_D15 */
|
||||
/* ISH_UART0_CTS# */ /* GPP_D16 */
|
||||
/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
|
||||
/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
|
||||
/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
|
||||
/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
|
||||
/* GPP_D21 */
|
||||
/* GPP_D22 */
|
||||
/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
|
||||
/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), /* TPM_PIRQ_L */
|
||||
/* SATAXPCIE1 */ /* GPP_E1 */
|
||||
/* SATAXPCIE2 */ /* GPP_E2 */
|
||||
/* CPU_GP0 */ /* GPP_E3 */
|
||||
/* SATA_DEVSLP0 */ /* GPP_E4 */
|
||||
/* SATA_DEVSLP1 */ /* GPP_E5 */
|
||||
/* SATA_DEVSLP2 */ /* GPP_E6 */
|
||||
/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), /* TOUCHSCREEN */
|
||||
/* SATALED# */ /* GPP_E8 */
|
||||
/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||
/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
|
||||
/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
|
||||
/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
|
||||
/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
|
||||
/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */
|
||||
/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */
|
||||
/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
|
||||
/* DDPB_CTRLCLK */ /* GPP_E18 */
|
||||
/* DDPB_CTRLDATA */ /* GPP_E19 */
|
||||
/* DDPC_CTRLCLK */ /* GPP_E20 */
|
||||
/* DDPC_CTRLDATA */ /* GPP_E21 */
|
||||
/* GPP_E22 */
|
||||
/* GPP_E23 */
|
||||
/*
|
||||
* The next 4 pads are for bit banging the amplifiers. They are connected
|
||||
* together with i2s0 signals. For default behavior of i2s make these
|
||||
* gpio inupts.
|
||||
*/
|
||||
/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP),
|
||||
/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP),
|
||||
/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP),
|
||||
/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP),
|
||||
/* I2C2_SDA */ /* GPP_F4 */
|
||||
/* I2C2_SCL */ /* GPP_F5 */
|
||||
/* I2C3_SDA */ /* GPP_F6 */
|
||||
/* I2C3_SCL */ /* GPP_F7 */
|
||||
/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* Amplifiers */
|
||||
/* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* Amplifiers */
|
||||
/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), /* MIC_INT_L */
|
||||
/* I2C5_SCL */ /* GPP_F11 */
|
||||
/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
|
||||
/* GPP_F23 */
|
||||
/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
|
||||
/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
|
||||
/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
|
||||
/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
|
||||
/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
|
||||
/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
|
||||
/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
|
||||
/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1),
|
||||
/* BATLOW# */ /* GPD0 */
|
||||
/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
|
||||
/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */
|
||||
/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
|
||||
/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
/* GPD7 */
|
||||
/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
/* SLP_WLAN# */ /* GPD9 */
|
||||
/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
|
||||
/* LANPHYC */ /* GPD11 */
|
||||
};
|
||||
|
||||
/* Early pad configuration in romstage. */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
|
||||
/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
42
src/mainboard/google/chell/mainboard.c
Normal file
42
src/mainboard/google/chell/mainboard.c
Normal file
@ -0,0 +1,42 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
#include <stdlib.h>
|
||||
#include "ec.h"
|
||||
|
||||
static void mainboard_init(device_t dev)
|
||||
{
|
||||
mainboard_ec_init();
|
||||
}
|
||||
|
||||
/*
|
||||
* mainboard_enable is executed as first thing after
|
||||
* enumerate_buses().
|
||||
*/
|
||||
static void mainboard_enable(device_t dev)
|
||||
{
|
||||
dev->ops->init = mainboard_init;
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
51
src/mainboard/google/chell/pei_data.c
Normal file
51
src/mainboard/google/chell/pei_data.c
Normal file
@ -0,0 +1,51 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <soc/pei_data.h>
|
||||
#include <soc/pei_wrapper.h>
|
||||
|
||||
void mainboard_fill_pei_data(struct pei_data *pei_data)
|
||||
{
|
||||
/* DQ byte map */
|
||||
const u8 dq_map[2][12] = {
|
||||
{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
|
||||
0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
|
||||
{ 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
|
||||
0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
|
||||
/* DQS CPU<>DRAM map */
|
||||
const u8 dqs_map[2][8] = {
|
||||
{ 0, 1, 3, 2, 4, 5, 6, 7 },
|
||||
{ 1, 0, 4, 5, 2, 3, 6, 7 } };
|
||||
|
||||
/* Rcomp resistor */
|
||||
const u16 RcompResistor[3] = { 200, 81, 162 };
|
||||
|
||||
/* Rcomp target */
|
||||
const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };
|
||||
|
||||
memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
|
||||
memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
|
||||
memcpy(pei_data->RcompResistor, RcompResistor,
|
||||
sizeof(RcompResistor));
|
||||
memcpy(pei_data->RcompTarget, RcompTarget,
|
||||
sizeof(RcompTarget));
|
||||
}
|
||||
29
src/mainboard/google/chell/ramstage.c
Normal file
29
src/mainboard/google/chell/ramstage.c
Normal file
@ -0,0 +1,29 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Intel Corporation
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
#include <soc/ramstage.h>
|
||||
#include "gpio.h"
|
||||
|
||||
void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
|
||||
{
|
||||
/* Configure pads prior to SiliconInit() in case there's any
|
||||
* dependencies during hardware initialization. */
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
78
src/mainboard/google/chell/romstage.c
Normal file
78
src/mainboard/google/chell/romstage.c
Normal file
@ -0,0 +1,78 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2010 coresystems GmbH
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
#include <cbfs.h>
|
||||
#include <console/console.h>
|
||||
#include <string.h>
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/pei_data.h>
|
||||
#include <soc/pei_wrapper.h>
|
||||
#include <soc/romstage.h>
|
||||
#include "gpio.h"
|
||||
#include "spd/spd.h"
|
||||
|
||||
static void early_config_gpio(void)
|
||||
{
|
||||
/* This is a hack for FSP because it does things in MemoryInit()
|
||||
* which it shouldn't be. We have to prepare certain gpios here
|
||||
* because of the brokenness in FSP. */
|
||||
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
|
||||
}
|
||||
|
||||
void mainboard_romstage_entry(struct romstage_params *params)
|
||||
{
|
||||
/* Ensure the EC and PD are in the right mode for recovery */
|
||||
google_chromeec_early_init();
|
||||
|
||||
early_config_gpio();
|
||||
|
||||
/* Fill out PEI DATA */
|
||||
mainboard_fill_pei_data(params->pei_data);
|
||||
mainboard_fill_spd_data(params->pei_data);
|
||||
/* Initliaze memory */
|
||||
romstage_common(params);
|
||||
}
|
||||
|
||||
void mainboard_memory_init_params(struct romstage_params *params,
|
||||
MEMORY_INIT_UPD *memory_params)
|
||||
{
|
||||
if (params->pei_data->spd_data[0][0][0] != 0) {
|
||||
memory_params->MemorySpdPtr00 =
|
||||
(UINT32)(params->pei_data->spd_data[0][0]);
|
||||
memory_params->MemorySpdPtr10 =
|
||||
(UINT32)(params->pei_data->spd_data[1][0]);
|
||||
}
|
||||
memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0],
|
||||
sizeof(params->pei_data->dq_map[0]));
|
||||
memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1],
|
||||
sizeof(params->pei_data->dq_map[1]));
|
||||
memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0],
|
||||
sizeof(params->pei_data->dqs_map[0]));
|
||||
memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1],
|
||||
sizeof(params->pei_data->dqs_map[1]));
|
||||
memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor,
|
||||
sizeof(params->pei_data->RcompResistor));
|
||||
memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget,
|
||||
sizeof(params->pei_data->RcompTarget));
|
||||
memory_params->MemorySpdDataLen = SPD_LEN;
|
||||
memory_params->DqPinsInterleaved = FALSE;
|
||||
}
|
||||
132
src/mainboard/google/chell/smihandler.c
Normal file
132
src/mainboard/google/chell/smihandler.c
Normal file
@ -0,0 +1,132 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <elog.h>
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/nvs.h>
|
||||
#include <soc/pm.h>
|
||||
#include <soc/smm.h>
|
||||
#include "ec.h"
|
||||
#include "gpio.h"
|
||||
|
||||
int mainboard_io_trap_handler(int smif)
|
||||
{
|
||||
switch (smif) {
|
||||
case 0x99:
|
||||
printk(BIOS_DEBUG, "Sample\n");
|
||||
smm_get_gnvs()->smif = 0;
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* On success, the IO Trap Handler returns 0
|
||||
* On failure, the IO Trap Handler returns a value != 0
|
||||
*
|
||||
* For now, we force the return value to 0 and log all traps to
|
||||
* see what's going on.
|
||||
*/
|
||||
return 1;
|
||||
}
|
||||
|
||||
static u8 mainboard_smi_ec(void)
|
||||
{
|
||||
u8 cmd = 0;
|
||||
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
|
||||
u32 pm1_cnt;
|
||||
cmd = google_chromeec_get_event();
|
||||
|
||||
/* Log this event */
|
||||
if (IS_ENABLED(CONFIG_ELOG_GSMI) && cmd)
|
||||
elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
|
||||
|
||||
switch (cmd) {
|
||||
case EC_HOST_EVENT_LID_CLOSED:
|
||||
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
|
||||
|
||||
/* Go to S5 */
|
||||
pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
|
||||
pm1_cnt |= (0xf << 10);
|
||||
outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
return cmd;
|
||||
}
|
||||
|
||||
void mainboard_smi_gpi_handler(const struct gpi_status *sts)
|
||||
{
|
||||
if (gpi_status_get(sts, EC_SMI_GPI)) {
|
||||
/* Process all pending events */
|
||||
while (mainboard_smi_ec() != 0)
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void mainboard_smi_sleep(u8 slp_typ)
|
||||
{
|
||||
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
|
||||
switch (slp_typ) {
|
||||
case 3:
|
||||
/* Enable wake events */
|
||||
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
|
||||
break;
|
||||
case 5:
|
||||
/* Enable wake events */
|
||||
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Disable SCI and SMI events */
|
||||
google_chromeec_set_smi_mask(0);
|
||||
google_chromeec_set_sci_mask(0);
|
||||
|
||||
/* Clear pending events that may trigger immediate wake */
|
||||
while (google_chromeec_get_event() != 0)
|
||||
;
|
||||
#endif
|
||||
}
|
||||
|
||||
int mainboard_smi_apmc(u8 apmc)
|
||||
{
|
||||
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
|
||||
switch (apmc) {
|
||||
case APM_CNT_ACPI_ENABLE:
|
||||
google_chromeec_set_smi_mask(0);
|
||||
/* Clear all pending events */
|
||||
while (google_chromeec_get_event() != 0)
|
||||
;
|
||||
google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
|
||||
break;
|
||||
case APM_CNT_ACPI_DISABLE:
|
||||
google_chromeec_set_sci_mask(0);
|
||||
/* Clear all pending events */
|
||||
while (google_chromeec_get_event() != 0)
|
||||
;
|
||||
google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
43
src/mainboard/google/chell/spd/Makefile.inc
Normal file
43
src/mainboard/google/chell/spd/Makefile.inc
Normal file
@ -0,0 +1,43 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2015 Google Inc.
|
||||
## Copyright (C) 2015 Intel Corporation
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc.
|
||||
##
|
||||
|
||||
romstage-y += spd.c
|
||||
|
||||
SPD_BIN = $(obj)/spd.bin
|
||||
|
||||
# SPD data by index. No method for board identification yet
|
||||
SPD_SOURCES = empty # 0b0000
|
||||
SPD_SOURCES += samsung_dimm_K4E6E304EE-EGCF # 0b0001
|
||||
SPD_SOURCES += hynix_dimm_H9CCNNN8JTBLAR # 0b0010
|
||||
SPD_SOURCES += hynix_dimm_H9CCNNNBLTALAR # 0b0011
|
||||
|
||||
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
|
||||
|
||||
# Include spd rom data
|
||||
$(SPD_BIN): $(SPD_DEPS)
|
||||
for f in $+; \
|
||||
do for c in $$(cat $$f | grep -v ^#); \
|
||||
do printf $$(printf '\%o' 0x$$c); \
|
||||
done; \
|
||||
done > $@
|
||||
|
||||
cbfs-files-y += spd.bin
|
||||
spd.bin-file := $(SPD_BIN)
|
||||
spd.bin-type := spd
|
||||
16
src/mainboard/google/chell/spd/empty.spd.hex
Normal file
16
src/mainboard/google/chell/spd/empty.spd.hex
Normal file
@ -0,0 +1,16 @@
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
@ -0,0 +1,16 @@
|
||||
91 20 F1 03 04 11 05 0B 03 11 01 08 09 00 50 05
|
||||
78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00
|
||||
00 80 ca fa 00 00 00 A8 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00
|
||||
48 39 43 43 4E 4E 4E 38 4A 54 42 4C 41 52 2D 4E
|
||||
54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
@ -0,0 +1,16 @@
|
||||
91 20 F1 03 04 12 05 0A 03 11 01 08 09 00 50 05
|
||||
78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00
|
||||
00 80 ca fa 00 00 00 A8 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00
|
||||
48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E
|
||||
54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
@ -0,0 +1,16 @@
|
||||
91 20 F1 03 04 12 05 0A 03 11 01 08 09 00 50 05
|
||||
78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00
|
||||
00 80 ca fa 00 00 00 A8 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00
|
||||
4B 34 45 36 45 33 30 34 45 44 2D 45 47 43 45 20
|
||||
20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
127
src/mainboard/google/chell/spd/spd.c
Normal file
127
src/mainboard/google/chell/spd/spd.c
Normal file
@ -0,0 +1,127 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
#include <arch/byteorder.h>
|
||||
#include <cbfs.h>
|
||||
#include <console/console.h>
|
||||
#include <gpio.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/pei_data.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "../gpio.h"
|
||||
#include "spd.h"
|
||||
|
||||
static void mainboard_print_spd_info(uint8_t spd[])
|
||||
{
|
||||
const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
|
||||
const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
|
||||
const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
|
||||
const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
|
||||
const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
|
||||
const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
|
||||
const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
|
||||
char spd_name[SPD_PART_LEN+1] = { 0 };
|
||||
|
||||
int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
|
||||
int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
|
||||
int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
|
||||
int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
|
||||
int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
|
||||
int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
|
||||
int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
|
||||
|
||||
/* Module type */
|
||||
printk(BIOS_INFO, "SPD: module type is ");
|
||||
switch (spd[SPD_DRAM_TYPE]) {
|
||||
case SPD_DRAM_DDR3:
|
||||
printk(BIOS_INFO, "DDR3\n");
|
||||
break;
|
||||
case SPD_DRAM_LPDDR3:
|
||||
printk(BIOS_INFO, "LPDDR3\n");
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Module Part Number */
|
||||
memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
|
||||
spd_name[SPD_PART_LEN] = 0;
|
||||
printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
|
||||
|
||||
printk(BIOS_INFO,
|
||||
"SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n",
|
||||
banks, ranks, rows, cols, capmb);
|
||||
printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
|
||||
devw, busw);
|
||||
|
||||
if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
|
||||
/* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
|
||||
printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
|
||||
capmb / 8 * busw / devw * ranks);
|
||||
}
|
||||
}
|
||||
|
||||
/* Copy SPD data for on-board memory */
|
||||
void mainboard_fill_spd_data(struct pei_data *pei_data)
|
||||
{
|
||||
char *spd_file;
|
||||
size_t spd_file_len;
|
||||
int spd_index;
|
||||
|
||||
gpio_t spd_gpios[] = {
|
||||
GPIO_MEM_CONFIG_0,
|
||||
GPIO_MEM_CONFIG_1,
|
||||
GPIO_MEM_CONFIG_2,
|
||||
GPIO_MEM_CONFIG_3,
|
||||
};
|
||||
|
||||
spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
|
||||
printk(BIOS_INFO, "SPD index %d\n", spd_index);
|
||||
|
||||
/* Load SPD data from CBFS */
|
||||
spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
|
||||
&spd_file_len);
|
||||
if (!spd_file)
|
||||
die("SPD data not found.");
|
||||
|
||||
/* make sure we have at least one SPD in the file. */
|
||||
if (spd_file_len < SPD_LEN)
|
||||
die("Missing SPD data.");
|
||||
|
||||
/* Make sure we did not overrun the buffer */
|
||||
if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
|
||||
printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n");
|
||||
spd_index = 1;
|
||||
}
|
||||
|
||||
/* Assume same memory in both channels */
|
||||
spd_index *= SPD_LEN;
|
||||
memcpy(pei_data->spd_data[0][0], spd_file + spd_index, SPD_LEN);
|
||||
memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN);
|
||||
|
||||
/* Make sure a valid SPD was found */
|
||||
if (pei_data->spd_data[0][0][0] == 0)
|
||||
die("Invalid SPD data.");
|
||||
|
||||
mainboard_print_spd_info(pei_data->spd_data[0][0]);
|
||||
}
|
||||
37
src/mainboard/google/chell/spd/spd.h
Normal file
37
src/mainboard/google/chell/spd/spd.h
Normal file
@ -0,0 +1,37 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_SPD_H
|
||||
#define MAINBOARD_SPD_H
|
||||
|
||||
#define SPD_LEN 256
|
||||
|
||||
#define SPD_DRAM_TYPE 2
|
||||
#define SPD_DRAM_DDR3 0x0b
|
||||
#define SPD_DRAM_LPDDR3 0xf1
|
||||
#define SPD_DENSITY_BANKS 4
|
||||
#define SPD_ADDRESSING 5
|
||||
#define SPD_ORGANIZATION 7
|
||||
#define SPD_BUS_DEV_WIDTH 8
|
||||
#define SPD_PART_OFF 128
|
||||
#define SPD_PART_LEN 18
|
||||
#define SPD_MANU_OFF 148
|
||||
|
||||
#endif
|
||||
Loading…
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Reference in New Issue
Block a user