sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/apollolake: Update memory HOB info save function

Browse Source 
SMBIOS memory HOB produced by glk FSP v52_27 has new structure
members, which are not available in current apl FSP. New FSP-m
header file in https://review.coreboot.org/#/c/20673/ lists new
SMBIOS structure members.

Break memory HOB save routine into different functions for glk
and apl to accomodate new changes.

Change-Id: I33c6e4f2842cebbb326b6a05436fa69e3836ffc6
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/20674
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ravi Sarawadi
2017-07-20 15:11:19 -07:00
committed by Aaron Durbin
parent ab94ba309e
commit 09195ac0f9
4 changed files with 182 additions and 64 deletions
Download Patch File Download Diff File Expand all files Collapse all files

64
src/soc/intel/apollolake/meminit.c
View File

@ -12,11 +12,9 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cbmem.h>
#include <console/console.h>
#include <fsp/util.h>
#include <memory_info.h>
#include <soc/intel/common/smbios.h>
#include <soc/meminit.h>
#include <stddef.h> /* required for FspmUpd.h */
#include <fsp/soc_binding.h>
@ -259,68 +257,6 @@ void meminit_lpddr4_by_sku(FSP_M_CONFIG *cfg,
cfg->PeriodicRetrainingDisable = sku->disable_periodic_retraining;
}
void save_lpddr4_dimm_info(const struct lpddr4_cfg *lp4cfg, size_t mem_sku)
{
int channel, dimm, dimm_max, index;
size_t hob_size;
const DIMM_INFO *src_dimm;
struct dimm_info *dest_dimm;
struct memory_info *mem_info;
const CHANNEL_INFO *channel_info;
const FSP_SMBIOS_MEMORY_INFO *memory_info_hob;
if (mem_sku >= lp4cfg->num_skus) {
printk(BIOS_ERR, "Too few LPDDR4 SKUs: 0x%zx/0x%zx\n",
mem_sku, lp4cfg->num_skus);
return;
}
memory_info_hob = fsp_find_smbios_memory_info(&hob_size);
/*
* Allocate CBMEM area for DIMM information used to populate SMBIOS
* table 17
*/
mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
if (mem_info == NULL) {
printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n");
return;
}
memset(mem_info, 0, sizeof(*mem_info));
/* Describe the first N DIMMs in the system */
index = 0;
dimm_max = ARRAY_SIZE(mem_info->dimm);
for (channel = 0; channel < memory_info_hob->ChannelCount; channel++) {
if (index >= dimm_max)
break;
channel_info = &memory_info_hob->ChannelInfo[channel];
for (dimm = 0; dimm < channel_info->DimmCount; dimm++) {
if (index >= dimm_max)
break;
src_dimm = &channel_info->DimmInfo[dimm];
dest_dimm = &mem_info->dimm[index];
if (!src_dimm->SizeInMb)
continue;
/* Populate the DIMM information */
dimm_info_fill(dest_dimm,
src_dimm->SizeInMb,
memory_info_hob->MemoryType,
memory_info_hob->MemoryFrequencyInMHz,
channel_info->ChannelId,
src_dimm->DimmId,
lp4cfg->skus[mem_sku].part_num,
strlen(lp4cfg->skus[mem_sku].part_num),
memory_info_hob->DataWidth);
index++;
}
}
mem_info->dimm_cnt = index;
printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
}
uint8_t fsp_memory_soc_version(void)
{
/* Bump this value when the memory configuration parameters change. */