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libpayload: Rework exception hook interface

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This patch makes some slight changes to the exception hook interface.
The old code provides a different handler hook for every exception
type... however, in practice all those hook functions often need to look
very similar, so this creates more boilerplate than it removes. The new
interface just allows for a single hook with the exception type passed
as an argument, and the consumer can signal whether the exception was
handled through the return value. (Right now this still only supports
one consumer, but it could easily be extended to walk through a list of
hooks if the need arises.)

Also move the excepton state from an argument to a global. This avoids a
lot of boilerplate since some consumers need to change the state from
many places, so they would have to pass the same pointer around many
times. It also removes the false suggestion that the exception state was
not global and you could have multiple copies of it (which the exception
core doesn't support for any architecture).

On the ARM side, the exception state is separated from the exception
stack for easier access. (This requires some assembly changes, and I
threw in a few comments and corrected the immediate sigils from '$' to
the official '#' while I'm there.) Since the exception state is now both
stored and loaded through an indirection pointer, this allows for some
very limited reentrance (you could point it to a different struct while
handling an exception, and while you still won't be able to return to
the outer-level exception from there, you could at least swap out the
pointer and return back to System Mode in one go).

BUG=chrome-os-partner:18390
TEST=Made sure normal exceptions still get dumped correctly on both
archs.

Original-Change-Id: I5d9a934fab7c14ccb2c9d7ee4b3465c825521fa2
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202562
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 97542110f0b385b9b8d89675866e65db8ca32aeb)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

*** Squashed to prevent build failures. ***

libpayload: align arm64 with new exception handling model

The exception handling was previously updated, however the
arm64 changes raced with hat one. Make the arm64 align with
the new model. Without these changes compilation will fail.

BUG=None
BRANCH=None
TEST=Can build libpayload for rush.

Original-Change-Id: I320b39a57b985d1f87446ea7757955664f8dba8f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/204402
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 0080df41b311ef20f9214b386fa4e38ee54aa1a1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I9a0bb3848cf5286f9f4bb08172a9f4a15278348e
Reviewed-on: http://review.coreboot.org/8117
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Julius Werner
2014-05-15 19:41:52 -07:00
committed by Marc Jones
parent 43e10301c0
commit 092cac58de
9 changed files with 179 additions and 185 deletions
Download Patch File Download Diff File Expand all files Collapse all files

56
payloads/libpayload/arch/arm/exception_asm.S
View File

@@ -43,72 +43,76 @@ exception_table:
b 8f
1:
mov sp, $0
mov sp, #0
b exception_common
/* Undefined Instruction (CAREFUL: the PC offset is specific to thumb mode!) */
2:
sub lr, lr, $2
mov sp, $1
sub lr, lr, #2
mov sp, #1
b exception_common
/* Software Interrupt (no PC offset necessary) */
3:
mov sp, $2
mov sp, #2
b exception_common
/* Prefetch Abort */
4:
sub lr, lr, $4
mov sp, $3
sub lr, lr, #4
mov sp, #3
b exception_common
/* Data Abort */
5:
sub lr, lr, $8
mov sp, $4
sub lr, lr, #8
mov sp, #4
b exception_common
/* (not used) */
6:
mov sp, $5
mov sp, #5
b exception_common
/* Interrupt */
7:
sub lr, lr, $4
mov sp, $6
sub lr, lr, #4
mov sp, #6
b exception_common
/* Fast Interrupt */
8:
sub lr, lr, $4
mov sp, $7
sub lr, lr, #4
mov sp, #7
b exception_common
exception_common:
str sp, exception_idx
ldr sp, exception_stack_end
push { lr }
stmfd sp, { sp, lr }^
sub sp, sp, $8
push { r0 - r12 }
ldr sp, exception_state_ptr
stmia sp!, { r0 - r12 } /* Save regs from bottom to top */
stmia sp, { sp, lr }^ /* Save banked SP/LR (no writeback) */
str lr, [sp, #(4 * 2)] /* Save PC to &regs[13] + 2 */
mrs r0, SPSR
push { r0 }
mov r0, sp
ldr r1, exception_idx
str r0, [sp, #(4 * 3)] /* Save SPSR to &regs[13] + 3 */
ldr sp, exception_stack_end /* Point SP to the stack for C code */
ldr r0, exception_idx
blx exception_dispatch
pop { r0 }
msr SPSR_cxsf, r0
pop { r0 - r12 }
add sp, sp, $8
ldmfd sp!, { pc }^
ldr sp, exception_state_ptr
ldr r0, [sp, #(4 * 16)] /* Load SPSR from &regs[0] + 16... */
msr SPSR_cxsf, r0 /* ...and get it out of the way */
ldmia sp!, { r0 - r12 } /* Restore regs from bottom to top */
ldmia sp, { sp, lr }^ /* Restore SP/LR to banked location */
add sp, sp, #8 /* Adjust SP (no writeback allowed) */
ldmia sp!, { pc }^ /* Do exception return (mode switch) */
.align 2
.global exception_stack_end
exception_stack_end:
.word 0
.global exception_state_ptr
exception_state_ptr:
.word 0
exception_idx:
.word 0