src/acpi to src/lib: Fix spelling errors

These issues were found and fixed by codespell, a useful tool for
finding spelling errors.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/x86/64bit/exit32.inc

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 /*
- * For droping from long mode to protected mode.
+ * For dropping from long mode to protected mode.
  *
  * For reference see "AMD64 ArchitectureProgrammer's Manual Volume 2",
  * Document 24593-Rev. 3.31-July 2019 Chapter 5.3
@@ -47,7 +47,7 @@ SetCodeSelector32:
 
 	# use iret to jump to a 32-bit offset in a new code segment
 	# iret will pop cs:rip, flags, then ss:rsp
-	mov	%ss, %ax	# need to push ss, but push ss instuction
+	mov	%ss, %ax	# need to push ss, but push ss instruction
 	push	%rax		# not valid in x64 mode, so use ax
 	push	%rdx		# the rsp to load
 	pushfq			# push rflags

src/cpu/x86/pae/pgtbl.c

@@ -104,7 +104,7 @@ void paging_disable_pae(void)
  * Use PAE to map a page and then memset it with the pattern specified.
  * In order to use PAE pagetables for virtual addressing are set up and reloaded
  * on a 2MiB boundary. After the function is done, virtual addressing mode is
- * disabled again. The PAT are set to all cachable, but MTRRs still apply.
+ * disabled again. The PAT are set to all cacheable, but MTRRs still apply.
  *
  * Requires a scratch memory for pagetables and a virtual address for
  * non identity mapped memory.
@@ -124,7 +124,7 @@ void paging_disable_pae(void)
  *                  Content at physical address isn't preserved.
  * @param length    The length of the memory segment to memset
  * @param dest      Physical memory address to memset
- * @param pat       The pattern to write to the pyhsical memory
+ * @param pat       The pattern to write to the physical memory
  * @return 0 on success, 1 on error
  */
 int memset_pae(uint64_t dest, unsigned char pat, uint64_t length, void *pgtbl,

src/cpu/x86/sipi_vector.S

@@ -57,7 +57,7 @@ _start:
 	movw	%cs, %ax
 	movw	%ax, %ds
 
-	/* The gdtaddr needs to be releative to the data segment in order
+	/* The gdtaddr needs to be relative to the data segment in order
 	 * to properly dereference it. The .text section comes first in an
 	 * rmodule so _start can be used as a proxy for the load address. */
 	movl	$(gdtaddr), %ebx