Fix build with CONFIG_DEBUG_RAM_SETUP on Intel 440BX, use printk().
It's a good thing to use printk() instead of print_*() anyway on 440BX (and other chipsets which have been converted to CAR). Build tested and boot-tested on ASUS P2B-LS. Signed-off-by: Keith Hui <buurin@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6206 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@@ -38,13 +38,14 @@ Macros and definitions.
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/* Debugging macros. */
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#if CONFIG_DEBUG_RAM_SETUP
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#define PRINT_DEBUG(x) print_debug(x)
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#define PRINT_DEBUG_HEX8(x) print_debug_hex8(x)
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#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
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#define PRINT_DEBUG_HEX32(x) print_debug_hex32(x)
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#include "lib/debug.c"
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#define PRINT_DEBUG(x...) printk(BIOS_DEBUG, x)
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#define PRINT_DEBUG_HEX8(x) PRINT_DEBUG("%02x", x)
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#define PRINT_DEBUG_HEX16(x) PRINT_DEBUG("%04x", x)
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#define PRINT_DEBUG_HEX32(x) PRINT_DEBUG("%08x", x)
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#define DUMPNORTH() dump_pci_device(NB)
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#else
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#define PRINT_DEBUG(x)
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#define PRINT_DEBUG(x...)
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#define PRINT_DEBUG_HEX8(x)
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#define PRINT_DEBUG_HEX16(x)
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#define PRINT_DEBUG_HEX32(x)
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@@ -621,11 +622,7 @@ static void spd_enable_refresh(void)
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continue;
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reg = (reg & 0xf8) | refresh_rate_map[(value & 0x7f)];
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PRINT_DEBUG(" Enabling refresh (DRAMC = 0x");
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PRINT_DEBUG_HEX8(reg);
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PRINT_DEBUG(") for DIMM ");
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PRINT_DEBUG_HEX8(i);
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PRINT_DEBUG("\n");
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PRINT_DEBUG(" Enabling refresh (DRAMC = 0x%02x) for DIMM %02x\n", reg, i);
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}
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pci_write_config8(NB, DRAMC, reg);
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@@ -662,8 +659,8 @@ void sdram_set_registers(void)
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}
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struct dimm_size {
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unsigned long side1;
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unsigned long side2;
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u32 side1;
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u32 side2;
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};
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static struct dimm_size spd_get_dimm_size(unsigned int device)
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@@ -718,15 +715,13 @@ static struct dimm_size spd_get_dimm_size(unsigned int device)
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* modules by setting them to a supported size.
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*/
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if(sz.side1 > 128) {
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PRINT_DEBUG("Side1 was 0x");
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PRINT_DEBUG_HEX16(sz.side1);
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PRINT_DEBUG(" but only 128MB will be used.\n");
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PRINT_DEBUG("Side1 was %dMB but only 128MB will be used.\n",
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sz.side1);
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sz.side1 = 128;
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if(sz.side2 > 128) {
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PRINT_DEBUG("Side2 was 0x");
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PRINT_DEBUG_HEX16(sz.side2);
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PRINT_DEBUG(" but only 128MB will be used.\n");
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PRINT_DEBUG("Side2 was %dMB but only 128MB will be used.\n",
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sz.side2);
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sz.side2 = 128;
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}
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}
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@@ -759,15 +754,12 @@ static void set_dram_row_attributes(void)
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if (value == SPD_MEMORY_TYPE_EDO
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|| value == SPD_MEMORY_TYPE_SDRAM) {
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PRINT_DEBUG("Found ");
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if (value == SPD_MEMORY_TYPE_EDO) {
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edosd |= 0x02;
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} else if (value == SPD_MEMORY_TYPE_SDRAM) {
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edosd |= 0x04;
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}
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PRINT_DEBUG("DIMM in slot ");
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PRINT_DEBUG_HEX8(i);
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PRINT_DEBUG("\n");
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PRINT_DEBUG("Found DIMM in slot %d\n", i);
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if (edosd == 0x06) {
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print_err("Mixing EDO/SDRAM unsupported!\n");
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@@ -925,21 +917,15 @@ static void set_dram_row_attributes(void)
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/* Set paging policy register. */
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pci_write_config8(NB, PGPOL + 1, bpr);
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PRINT_DEBUG("PGPOL[BPR] has been set to 0x");
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PRINT_DEBUG_HEX8(bpr);
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PRINT_DEBUG("\n");
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PRINT_DEBUG("PGPOL[BPR] has been set to 0x%02x\n", bpr);
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/* Set DRAM row page size register. */
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pci_write_config16(NB, RPS, rps);
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PRINT_DEBUG("RPS has been set to 0x");
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PRINT_DEBUG_HEX16(rps);
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PRINT_DEBUG("\n");
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PRINT_DEBUG("RPS has been set to 0x%04x\n", rps);
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/* ### ECC */
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pci_write_config8(NB, NBXCFG + 3, nbxecc);
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PRINT_DEBUG("NBXECC[31:24] has been set to 0x");
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PRINT_DEBUG_HEX8(nbxecc);
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PRINT_DEBUG("\n");
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PRINT_DEBUG("NBXECC[31:24] has been set to 0x%02x\n", nbxecc);
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/* Set DRAMC[4:3] to proper memory type (EDO/SDRAM).
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* TODO: Registered SDRAM support.
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@@ -956,9 +942,7 @@ static void set_dram_row_attributes(void)
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value = pci_read_config8(NB, DRAMC) & 0xe7;
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value |= edosd;
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pci_write_config8(NB, DRAMC, value);
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PRINT_DEBUG("DRAMC has been set to 0x");
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PRINT_DEBUG_HEX8(value);
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PRINT_DEBUG("\n");
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PRINT_DEBUG("DRAMC has been set to 0x%02x\n", value);
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}
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void sdram_set_spd_registers(void)
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