Intel i82830 boards & chips: Remove - using LATE_CBMEM_INIT
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: cpu/intel/socket_mFCBGA479 northbridge/intel/i82830 Mainboards: mainboard/rca/rm4100 mainboard/thomson/ip1000 Change-Id: I9574179516c30bb0d6a29741254293c2cc6f12e9 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Martin Roth
Martin Roth
@@ -1,30 +0,0 @@
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config NORTHBRIDGE_INTEL_I82830
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bool
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select NO_MMCONF_SUPPORT
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select HAVE_DEBUG_RAM_SETUP
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select LATE_CBMEM_INIT
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select UDELAY_IO
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choice
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prompt "Onboard graphics"
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default I830_VIDEO_MB_8MB
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depends on NORTHBRIDGE_INTEL_I82830
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config I830_VIDEO_MB_OFF
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bool "Disabled, 0KB"
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config I830_VIDEO_MB_512KB
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bool "Enabled, 512KB"
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config I830_VIDEO_MB_1MB
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bool "Enabled, 1MB"
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config I830_VIDEO_MB_8MB
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bool "Enabled, 8MB"
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endchoice
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config VIDEO_MB
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int
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default 0 if I830_VIDEO_MB_OFF
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default 512 if I830_VIDEO_MB_512KB
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default 1 if I830_VIDEO_MB_1MB
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default 8 if I830_VIDEO_MB_8MB
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depends on NORTHBRIDGE_INTEL_I82830
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@@ -1,8 +0,0 @@
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ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I82830),y)
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ramstage-y += northbridge.c
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ramstage-y += vga.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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endif
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@@ -1,52 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Joseph Smith <joe@smittys.pointclark.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef NORTHBRIDGE_INTEL_I82830_I82830_H
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#define NORTHBRIDGE_INTEL_I82830_I82830_H
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#define RRBAR 0x48 /* Register Range Base Address (0x00000000) */
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#define GCC0 0x50 /* GMCH Control #0 (0xa072) */
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#define GCC1 0x52 /* GMCH Control #1 (0x0000) */
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#define FDHC 0x58 /* Fixed DRAM Hole Control (0x00) */
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#define PAM0 0x59 /* Programmable Attribute Map #0 (0x00) */
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#define PAM1 0x5a /* Programmable Attribute Map #1 (0x00) */
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#define PAM2 0x5b /* Programmable Attribute Map #2 (0x00) */
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#define PAM3 0x5c /* Programmable Attribute Map #3 (0x00) */
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#define PAM4 0x5d /* Programmable Attribute Map #4 (0x00) */
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#define PAM5 0x5e /* Programmable Attribute Map #5 (0x00) */
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#define PAM6 0x5f /* Programmable Attribute Map #6 (0x00) */
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#define DRB 0x60 /* DRAM Row Boundary #0 (0x00) */
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#define DRB1 0x61 /* DRAM Row Boundary #1 (0x00) */
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#define DRB2 0x62 /* DRAM Row Boundary #2 (0x00) */
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#define DRB3 0x63 /* DRAM Row Boundary #3 (0x00) */
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#define DRA 0x70 /* DRAM Row Attribute #0 (0xff) */
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#define DRA1 0x71 /* DRAM Row Attribute #1 (0xff) */
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#define DRT 0x78 /* DRAM Timing (0x00000010) */
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#define DRC 0x7c /* DRAM Controller Mode #0 (0x00000000) */
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#define DRC1 0x7d /* DRAM Controller Mode #1 (0x00000000) */
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#define DRC2 0x7e /* DRAM Controller Mode #2 (0x00000000) */
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#define DRC3 0x7f /* DRAM Controller Mode #3 (0x00000000) */
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#define DTC 0x8c /* DRAM Throttling Control (0x00000000) */
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#define SMRAM 0x90 /* System Management RAM Control (0x02) */
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#define ESMRAMC 0x91 /* Extended System Management RAM Control Reg. (0x38) */
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#define ERRSTS 0x92 /* Error Status (0x0000) */
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#define ERRCMD 0x94 /* Error Command (0x0000) */
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#define BUFF_SC 0xec /* System Memory Buffer Strength Control (0x00000000) */
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#define APBASE 0x10 /* Aperture Base Configuration (0x00000008) */
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#define APSIZE 0xb4 /* Aperture Size (0x00) */
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#define ATTBASE 0xb8 /* Aperture Translation Table Base (0x00000000) */
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#endif /* NORTHBRIDGE_INTEL_I82830_I82830_H */
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@@ -1,26 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "i82830.h"
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#define NB_DEV PCI_DEV(0, 0, 0)
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static inline int memory_initialized(void)
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{
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u32 drc;
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drc = pci_read_config32(NB_DEV, DRC);
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return (drc & (1<<29));
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}
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@@ -1,130 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <arch/io.h>
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#include <stdint.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <cbmem.h>
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#include <cpu/cpu.h>
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#include <stdlib.h>
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#include <string.h>
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#include "i82830.h"
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static void northbridge_init(device_t dev)
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{
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printk(BIOS_SPEW, "Northbridge init\n");
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}
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static struct device_operations northbridge_operations = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = northbridge_init,
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.enable = 0,
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.ops_pci = 0,
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};
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static const struct pci_driver northbridge_driver __pci_driver = {
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.ops = &northbridge_operations,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x3575,
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};
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static void pci_domain_set_resources(device_t dev)
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{
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device_t mc_dev;
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int igd_memory = 0;
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uint64_t uma_memory_base = 0, uma_memory_size = 0;
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mc_dev = dev->link_list->children;
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if (!mc_dev)
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return;
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unsigned long tomk, tomk_stolen;
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int idx;
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if (CONFIG_VIDEO_MB == 512) {
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igd_memory = (CONFIG_VIDEO_MB);
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printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory >> 10);
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} else {
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igd_memory = (CONFIG_VIDEO_MB * 1024);
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printk(BIOS_DEBUG, "%dMB IGD UMA\n", igd_memory >> 10);
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}
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/* Get the value of the highest DRB. This tells the end of
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* the physical memory. The units are ticks of 32MB
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* i.e. 1 means 32MB.
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*/
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tomk = ((unsigned long)pci_read_config8(mc_dev, DRB + 3)) << 15;
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tomk_stolen = tomk - igd_memory;
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/* For reserving UMA memory in the memory map */
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uma_memory_base = tomk_stolen * 1024ULL;
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uma_memory_size = igd_memory * 1024ULL;
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printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk_stolen);
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/* Report the memory regions. */
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idx = 10;
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ram_resource(dev, idx++, 0, 640);
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ram_resource(dev, idx++, 768, tomk - 768);
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uma_resource(dev, idx++, uma_memory_base >> 10, uma_memory_size >> 10);
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assign_resources(dev->link_list);
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set_late_cbmem_top(tomk_stolen * 1024);
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}
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static struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.enable_resources = NULL,
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.init = NULL,
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.scan_bus = pci_domain_scan_bus,
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.ops_pci_bus = pci_bus_default_ops,
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};
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static void cpu_bus_init(device_t dev)
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{
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initialize_cpus(dev->link_list);
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}
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static struct device_operations cpu_bus_ops = {
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.read_resources = DEVICE_NOOP,
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.set_resources = DEVICE_NOOP,
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.enable_resources = DEVICE_NOOP,
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.init = cpu_bus_init,
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.scan_bus = 0,
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};
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static void enable_dev(struct device *dev)
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{
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struct device_path;
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/* Set the operations if it is a special bus type. */
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if (dev->path.type == DEVICE_PATH_DOMAIN) {
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dev->ops = &pci_domain_ops;
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} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
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dev->ops = &cpu_bus_ops;
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}
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}
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struct chip_operations northbridge_intel_i82830_ops = {
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CHIP_NAME("Intel 82830 Northbridge")
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.enable_dev = enable_dev,
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};
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@@ -1,508 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <spd.h>
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#include <delay.h>
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#include "lib/debug.c"
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#include "i82830.h"
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/*-----------------------------------------------------------------------------
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Macros and definitions.
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-----------------------------------------------------------------------------*/
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/* Debugging macros. */
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#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
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#define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x)
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#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
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#else
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#define PRINTK_DEBUG(x...)
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#define DUMPNORTH()
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#endif
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/* DRC[10:8] - Refresh Mode Select (RMS).
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* 0x0 for Refresh Disabled (Self Refresh)
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* 0x1 for Refresh interval 15.6 us for 133MHz
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* 0x2 for Refresh interval 7.8 us for 133MHz
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* 0x7 for Refresh interval 128 Clocks. (Fast Refresh Mode)
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*/
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#define RAM_COMMAND_REFRESH 0x1
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/* DRC[6:4] - SDRAM Mode Select (SMS). */
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#define RAM_COMMAND_SELF_REFRESH 0x0
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#define RAM_COMMAND_NOP 0x1
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#define RAM_COMMAND_PRECHARGE 0x2
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#define RAM_COMMAND_MRS 0x3
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#define RAM_COMMAND_CBR 0x6
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#define RAM_COMMAND_NORMAL 0x7
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/* DRC[29] - Initialization Complete (IC). */
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#define RAM_COMMAND_IC 0x1
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/*-----------------------------------------------------------------------------
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DIMM-initialization functions.
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-----------------------------------------------------------------------------*/
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static void do_ram_command(u32 command)
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{
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u32 reg32;
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/* Configure the RAM command. */
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reg32 = pci_read_config32(NORTHBRIDGE, DRC);
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/* Clear bits 29, 10-8, 6-4. */
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reg32 &= 0xdffff88f;
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reg32 |= command << 4;
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PRINTK_DEBUG(" Sending RAM command 0x%08x", reg32);
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pci_write_config32(NORTHBRIDGE, DRC, reg32);
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||||
}
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static void ram_read32(u8 dimm_start, u32 offset)
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{
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u32 reg32, base_addr = 32 * 1024 * 1024 * dimm_start;
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if (offset == 0x55aa55aa) {
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reg32 = read32((u32 *)base_addr);
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PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", base_addr, reg32);
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PRINTK_DEBUG(" Writing RAM at 0x%08x <= 0x%08x\n", base_addr, offset);
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write32((u32 *)base_addr, offset);
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reg32 = read32((u32 *)base_addr);
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PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", base_addr, reg32);
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} else {
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PRINTK_DEBUG(" to 0x%08x\n", base_addr + offset);
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read32((u32 *)(base_addr + offset));
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}
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}
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|
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static void initialize_dimm_rows(void)
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{
|
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int i, row;
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u8 dimm_start, dimm_end;
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unsigned device;
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|
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dimm_start = 0;
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|
||||
for (row = 0; row < (DIMM_SOCKETS * 2); row++) {
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||||
switch (row) {
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||||
case 0:
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||||
device = DIMM0;
|
||||
break;
|
||||
case 1:
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device = DIMM0;
|
||||
break;
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case 2:
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device = DIMM0 + 1;
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||||
break;
|
||||
case 3:
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device = DIMM0 + 1;
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||||
break;
|
||||
}
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|
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dimm_end = pci_read_config8(NORTHBRIDGE, DRB + row);
|
||||
|
||||
if (dimm_end > dimm_start) {
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||||
printk(BIOS_DEBUG, "Initializing SDRAM Row %u\n", row);
|
||||
|
||||
/* NOP command */
|
||||
PRINTK_DEBUG(" NOP\n");
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do_ram_command(RAM_COMMAND_NOP);
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ram_read32(dimm_start, 0);
|
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udelay(200);
|
||||
|
||||
/* Pre-charge all banks (at least 200 us after NOP) */
|
||||
PRINTK_DEBUG(" Pre-charging all banks\n");
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do_ram_command(RAM_COMMAND_PRECHARGE);
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ram_read32(dimm_start, 0);
|
||||
udelay(1);
|
||||
|
||||
/* 8 CBR refreshes (Auto Refresh) */
|
||||
PRINTK_DEBUG(" 8 CBR refreshes\n");
|
||||
for (i = 0; i < 8; i++) {
|
||||
do_ram_command(RAM_COMMAND_CBR);
|
||||
ram_read32(dimm_start, 0);
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
/* MRS command */
|
||||
/* TODO: Set offset 0x1d0 according to DRT values */
|
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PRINTK_DEBUG(" MRS\n");
|
||||
do_ram_command(RAM_COMMAND_MRS);
|
||||
ram_read32(dimm_start, 0x1d0);
|
||||
udelay(2);
|
||||
|
||||
/* Set GMCH-M Mode Select bits back to NORMAL operation mode */
|
||||
PRINTK_DEBUG(" Normal operation mode\n");
|
||||
do_ram_command(RAM_COMMAND_NORMAL);
|
||||
ram_read32(dimm_start, 0);
|
||||
udelay(1);
|
||||
|
||||
/* Perform a dummy memory read/write cycle */
|
||||
PRINTK_DEBUG(" Performing dummy read/write\n");
|
||||
ram_read32(dimm_start, 0x55aa55aa);
|
||||
udelay(1);
|
||||
}
|
||||
/* Set the start of the next DIMM. */
|
||||
dimm_start = dimm_end;
|
||||
}
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
DIMM-independent configuration functions.
|
||||
-----------------------------------------------------------------------------*/
|
||||
|
||||
struct dimm_size {
|
||||
unsigned int side1;
|
||||
unsigned int side2;
|
||||
};
|
||||
|
||||
static struct dimm_size spd_get_dimm_size(unsigned device)
|
||||
{
|
||||
struct dimm_size sz;
|
||||
int i, module_density, dimm_banks;
|
||||
sz.side1 = 0;
|
||||
module_density = spd_read_byte(device, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
|
||||
dimm_banks = spd_read_byte(device, SPD_NUM_DIMM_BANKS);
|
||||
|
||||
/* Find the size of side1. */
|
||||
/* Find the larger value. The larger value is always side1. */
|
||||
for (i = 512; i >= 0; i >>= 1) {
|
||||
if ((module_density & i) == i) {
|
||||
sz.side1 = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Set to 0 in case it's single sided. */
|
||||
sz.side2 = 0;
|
||||
|
||||
/* Test if it's a dual-sided DIMM. */
|
||||
if (dimm_banks > 1) {
|
||||
/* Test to see if there's a second value, if so it's asymmetrical. */
|
||||
if (module_density != i) {
|
||||
/* Find the second value, picking up where we left off. */
|
||||
/* i >>= 1 done initially to make sure we don't get the same value again. */
|
||||
for (i >>= 1; i >= 0; i >>= 1) {
|
||||
if (module_density == (sz.side1 | i)) {
|
||||
sz.side2 = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* If not, it's symmetrical */
|
||||
} else {
|
||||
sz.side2 = sz.side1;
|
||||
}
|
||||
}
|
||||
|
||||
/* SPD byte 31 is the memory size divided by 4 so we
|
||||
* need to multiply by 4 to get the total size.
|
||||
*/
|
||||
sz.side1 *= 4;
|
||||
sz.side2 *= 4;
|
||||
return sz;
|
||||
}
|
||||
|
||||
static void set_dram_row_boundaries(void)
|
||||
{
|
||||
int i, value, drb1, drb2;
|
||||
|
||||
for (i = 0; i < DIMM_SOCKETS; i++) {
|
||||
struct dimm_size sz;
|
||||
unsigned device;
|
||||
device = DIMM0 + i;
|
||||
drb1 = 0;
|
||||
drb2 = 0;
|
||||
|
||||
/* First check if a DIMM is actually present. */
|
||||
if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) {
|
||||
printk(BIOS_DEBUG, "Found DIMM in slot %u\n", i);
|
||||
sz = spd_get_dimm_size(device);
|
||||
printk(BIOS_DEBUG, " DIMM is %uMB on side 1\n", sz.side1);
|
||||
printk(BIOS_DEBUG, " DIMM is %uMB on side 2\n", sz.side2);
|
||||
|
||||
/* - Memory compatibility checks - */
|
||||
|
||||
/* Test for PC133 (i82830 only supports PC133) */
|
||||
/* PC133 SPD9 - cycle time is always 75 */
|
||||
if (spd_read_byte(device, SPD_MIN_CYCLE_TIME_AT_CAS_MAX) != 0x75) {
|
||||
printk(BIOS_ERR, "SPD9 DIMM Is Not PC133 Compatable\n");
|
||||
die("HALT\n");
|
||||
}
|
||||
/* PC133 SPD10 - access time is always 54 */
|
||||
if (spd_read_byte(device, SPD_ACCESS_TIME_FROM_CLOCK) != 0x54) {
|
||||
printk(BIOS_ERR, "SPD10 DIMM Is Not PC133 Compatable\n");
|
||||
die("HALT\n");
|
||||
}
|
||||
|
||||
/* The i82830 only supports a symmetrical dual-sided dimms
|
||||
* and can't handle DIMMs smaller than 32MB per
|
||||
* side or larger than 256MB per side.
|
||||
*/
|
||||
if ((sz.side2 != 0) && (sz.side1 != sz.side2)) {
|
||||
printk(BIOS_ERR, "This northbridge only supports\n");
|
||||
printk(BIOS_ERR, "symmetrical dual-sided DIMMs\n");
|
||||
printk(BIOS_ERR, "booting as a single-sided DIMM\n");
|
||||
sz.side2 = 0;
|
||||
}
|
||||
if ((sz.side1 < 32)) {
|
||||
printk(BIOS_ERR, "DIMMs smaller than 32MB per side\n");
|
||||
printk(BIOS_ERR, "are not supported on this northbridge\n");
|
||||
die("HALT\n");
|
||||
}
|
||||
|
||||
if ((sz.side1 > 256)) {
|
||||
printk(BIOS_ERR, "DIMMs larger than 256MB per side\n");
|
||||
printk(BIOS_ERR, "are not supported on this northbridge\n");
|
||||
die("HALT\n");
|
||||
}
|
||||
/* - End Memory compatibility checks - */
|
||||
|
||||
/* We need to divide size by 32 to set up the
|
||||
* DRB registers.
|
||||
*/
|
||||
if (sz.side1)
|
||||
drb1 = sz.side1 / 32;
|
||||
if (sz.side2)
|
||||
drb2 = sz.side2 / 32;
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "No DIMM found in slot %u\n", i);
|
||||
|
||||
/* If there's no DIMM in the slot, set value to 0. */
|
||||
drb1 = 0;
|
||||
drb2 = 0;
|
||||
}
|
||||
/* Set the value for DRAM Row Boundary Registers */
|
||||
if (i == 0) {
|
||||
pci_write_config8(NORTHBRIDGE, DRB, drb1);
|
||||
pci_write_config8(NORTHBRIDGE, DRB + 1, drb1 + drb2);
|
||||
PRINTK_DEBUG(" DRB 0x%02x has been set to 0x%02x\n", DRB, drb1);
|
||||
PRINTK_DEBUG(" DRB1 0x%02x has been set to 0x%02x\n", DRB + 1, drb1 + drb2);
|
||||
} else if (i == 1) {
|
||||
value = pci_read_config8(NORTHBRIDGE, DRB + 1);
|
||||
pci_write_config8(NORTHBRIDGE, DRB + 2, value + drb1);
|
||||
pci_write_config8(NORTHBRIDGE, DRB + 3, value + drb1 + drb2);
|
||||
PRINTK_DEBUG(" DRB2 0x%02x has been set to 0x%02x\n", DRB + 2, value + drb1);
|
||||
PRINTK_DEBUG(" DRB3 0x%02x has been set to 0x%02x\n", DRB + 3, value + drb1 + drb2);
|
||||
|
||||
/* We need to set the highest DRB value to 0x64 and 0x65.
|
||||
* These are supposed to be "Reserved" but memory will
|
||||
* not initialize properly if we don't.
|
||||
*/
|
||||
value = pci_read_config8(NORTHBRIDGE, DRB + 3);
|
||||
pci_write_config8(NORTHBRIDGE, DRB + 4, value);
|
||||
pci_write_config8(NORTHBRIDGE, DRB + 5, value);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void set_dram_row_attributes(void)
|
||||
{
|
||||
int i, dra, col, width, value;
|
||||
|
||||
for (i = 0; i < DIMM_SOCKETS; i++) {
|
||||
unsigned device;
|
||||
device = DIMM0 + i;
|
||||
|
||||
/* First check if a DIMM is actually present. */
|
||||
if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) {
|
||||
PRINTK_DEBUG("Found DIMM in slot %u\n", i);
|
||||
|
||||
dra = 0x00;
|
||||
|
||||
/* columns */
|
||||
col = spd_read_byte(device, SPD_NUM_COLUMNS);
|
||||
|
||||
/* data width */
|
||||
width = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB);
|
||||
|
||||
/* calculate page size in bits */
|
||||
value = ((1 << col) * width);
|
||||
|
||||
/* convert to Kilobytes */
|
||||
dra = ((value / 8) >> 10);
|
||||
|
||||
/* # of banks of DIMM (single or double sided) */
|
||||
value = spd_read_byte(device, SPD_NUM_DIMM_BANKS);
|
||||
|
||||
if (value == 1) {
|
||||
if (dra == 2) {
|
||||
dra = 0xF0; /* 2KB */
|
||||
} else if (dra == 4) {
|
||||
dra = 0xF1; /* 4KB */
|
||||
} else if (dra == 8) {
|
||||
dra = 0xF2; /* 8KB */
|
||||
} else if (dra == 16) {
|
||||
dra = 0xF3; /* 16KB */
|
||||
} else {
|
||||
printk(BIOS_ERR, "Page size not supported\n");
|
||||
die("HALT\n");
|
||||
}
|
||||
} else if (value == 2) {
|
||||
if (dra == 2) {
|
||||
dra = 0x00; /* 2KB */
|
||||
} else if (dra == 4) {
|
||||
dra = 0x11; /* 4KB */
|
||||
} else if (dra == 8) {
|
||||
dra = 0x22; /* 8KB */
|
||||
} else if (dra == 16) {
|
||||
dra = 0x33; /* 16KB */
|
||||
} else {
|
||||
printk(BIOS_ERR, "Page size not supported\n");
|
||||
die("HALT\n");
|
||||
}
|
||||
} else {
|
||||
printk(BIOS_ERR, "# of banks of DIMM not supported\n");
|
||||
die("HALT\n");
|
||||
}
|
||||
|
||||
} else {
|
||||
PRINTK_DEBUG("No DIMM found in slot %u\n", i);
|
||||
|
||||
/* If there's no DIMM in the slot, set dra value to 0xFF. */
|
||||
dra = 0xFF;
|
||||
}
|
||||
|
||||
/* Set the value for DRAM Row Attribute Registers */
|
||||
pci_write_config8(NORTHBRIDGE, DRA + i, dra);
|
||||
PRINTK_DEBUG(" DRA 0x%02x has been set to 0x%02x\n", DRA + i, dra);
|
||||
}
|
||||
}
|
||||
|
||||
static void set_dram_timing(void)
|
||||
{
|
||||
/* Set the value for DRAM Timing Register */
|
||||
/* TODO: Configure the value according to SPD values. */
|
||||
pci_write_config32(NORTHBRIDGE, DRT, 0x00000010);
|
||||
}
|
||||
|
||||
static void set_dram_buffer_strength(void)
|
||||
{
|
||||
/* TODO: This needs to be set according to the DRAM tech
|
||||
* (x8, x16, or x32). Argh, Intel provides no docs on this!
|
||||
* Currently, it needs to be pulled from the output of
|
||||
* lspci -xxx Rx92
|
||||
*/
|
||||
|
||||
/* Set the value for System Memory Buffer Strength Control Registers */
|
||||
pci_write_config32(NORTHBRIDGE, BUFF_SC, 0xFC9B491B);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
Public interface.
|
||||
-----------------------------------------------------------------------------*/
|
||||
|
||||
static void sdram_set_registers(void)
|
||||
{
|
||||
printk(BIOS_DEBUG, "Setting initial SDRAM registers....\n");
|
||||
|
||||
/* Calculate the value for DRT DRAM Timing Register */
|
||||
set_dram_timing();
|
||||
|
||||
/* Setup System Memory Buffer Strength Control Registers */
|
||||
set_dram_buffer_strength();
|
||||
|
||||
/* Setup DRAM Row Boundary Registers */
|
||||
set_dram_row_boundaries();
|
||||
|
||||
/* Setup DRAM Row Attribute Registers */
|
||||
set_dram_row_attributes();
|
||||
|
||||
printk(BIOS_DEBUG, "Initial SDRAM registers have been set.\n");
|
||||
}
|
||||
|
||||
static void northbridge_set_registers(void)
|
||||
{
|
||||
u16 value;
|
||||
int igd_memory = 0;
|
||||
|
||||
printk(BIOS_DEBUG, "Setting initial Northbridge registers....\n");
|
||||
|
||||
/* Set the value for Fixed DRAM Hole Control Register */
|
||||
pci_write_config8(NORTHBRIDGE, FDHC, 0x00);
|
||||
|
||||
/* Set the value for Programmable Attribute Map Registers
|
||||
* Ideally, this should be R/W for as many ranges as possible.
|
||||
*/
|
||||
pci_write_config8(NORTHBRIDGE, PAM0, 0x30);
|
||||
pci_write_config8(NORTHBRIDGE, PAM1, 0x33);
|
||||
pci_write_config8(NORTHBRIDGE, PAM2, 0x33);
|
||||
pci_write_config8(NORTHBRIDGE, PAM3, 0x33);
|
||||
pci_write_config8(NORTHBRIDGE, PAM4, 0x33);
|
||||
pci_write_config8(NORTHBRIDGE, PAM5, 0x33);
|
||||
pci_write_config8(NORTHBRIDGE, PAM6, 0x33);
|
||||
|
||||
/* Set the value for System Management RAM Control Register */
|
||||
pci_write_config8(NORTHBRIDGE, SMRAM, 0x02);
|
||||
|
||||
/* Set the value for GMCH Control Register #0 */
|
||||
pci_write_config16(NORTHBRIDGE, GCC0, 0xA072);
|
||||
|
||||
/* Set the value for Aperture Base Configuration Register */
|
||||
pci_write_config32(NORTHBRIDGE, APBASE, 0x00000008);
|
||||
|
||||
/* Set the value for GMCH Control Register #1 */
|
||||
switch (CONFIG_VIDEO_MB) {
|
||||
case 512: /* 512K of memory */
|
||||
igd_memory = 0x2;
|
||||
break;
|
||||
case 1: /* 1M of memory */
|
||||
igd_memory = 0x3;
|
||||
break;
|
||||
case 8: /* 8M of memory */
|
||||
igd_memory = 0x4;
|
||||
break;
|
||||
default: /* No memory */
|
||||
pci_write_config16(NORTHBRIDGE, GCC1, 0x0002);
|
||||
igd_memory = 0x0;
|
||||
}
|
||||
|
||||
value = pci_read_config16(NORTHBRIDGE, GCC1);
|
||||
value |= igd_memory << 4;
|
||||
value |= 1; // 64MB aperture
|
||||
pci_write_config16(NORTHBRIDGE, GCC1, value);
|
||||
|
||||
printk(BIOS_DEBUG, "Initial Northbridge registers have been set.\n");
|
||||
}
|
||||
|
||||
static void sdram_initialize(void)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
/* Setup Initial SDRAM Registers */
|
||||
sdram_set_registers();
|
||||
|
||||
/* Wait until power/voltages and clocks are stable (200us). */
|
||||
udelay(200);
|
||||
|
||||
/* Initialize each row of memory one at a time */
|
||||
initialize_dimm_rows();
|
||||
|
||||
/* Enable Refresh */
|
||||
PRINTK_DEBUG("Enabling Refresh\n");
|
||||
reg32 = pci_read_config32(NORTHBRIDGE, DRC);
|
||||
reg32 |= (RAM_COMMAND_REFRESH << 8);
|
||||
pci_write_config32(NORTHBRIDGE, DRC, reg32);
|
||||
|
||||
/* Set initialization complete */
|
||||
PRINTK_DEBUG("Setting initialization complete\n");
|
||||
reg32 = pci_read_config32(NORTHBRIDGE, DRC);
|
||||
reg32 |= (RAM_COMMAND_IC << 29);
|
||||
pci_write_config32(NORTHBRIDGE, DRC, reg32);
|
||||
|
||||
/* Setup Initial Northbridge Registers */
|
||||
northbridge_set_registers();
|
||||
|
||||
PRINTK_DEBUG("Northbridge following SDRAM init:\n");
|
||||
DUMPNORTH();
|
||||
}
|
||||
@@ -1,26 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef NORTHBRIDGE_INTEL_I82830_RAMINIT_H
|
||||
#define NORTHBRIDGE_INTEL_I82830_RAMINIT_H
|
||||
|
||||
/* 82830 Northbridge PCI device */
|
||||
#define NORTHBRIDGE PCI_DEV(0, 0, 0)
|
||||
|
||||
/* The 82830 supports max. 2 dual-sided SO-DIMMs. */
|
||||
#define DIMM_SOCKETS 2
|
||||
|
||||
#endif /* NORTHBRIDGE_INTEL_I82830_RAMINIT_H */
|
||||
@@ -1,387 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <compiler.h>
|
||||
#include <string.h>
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <device/pci_def.h>
|
||||
#include "i82830.h"
|
||||
|
||||
extern unsigned char *mbi;
|
||||
extern u32 mbi_len;
|
||||
|
||||
// #define DEBUG_SMI_I82830
|
||||
|
||||
/* If YABEL is enabled and it's not running at 0x00000000, we have to add some
|
||||
* offset to all our mbi object memory accesses
|
||||
*/
|
||||
#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && !CONFIG_YABEL_DIRECTHW
|
||||
#define OBJ_OFFSET CONFIG_YABEL_VIRTMEM_LOCATION
|
||||
#else
|
||||
#define OBJ_OFFSET 0x00000
|
||||
#endif
|
||||
|
||||
/* I830M */
|
||||
#define SMRAM 0x90
|
||||
#define D_OPEN (1 << 6)
|
||||
#define D_CLS (1 << 5)
|
||||
#define D_LCK (1 << 4)
|
||||
#define G_SMRANE (1 << 3)
|
||||
#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
|
||||
|
||||
|
||||
typedef struct {
|
||||
u32 mhid;
|
||||
u32 function;
|
||||
u32 retsts;
|
||||
u32 rfu;
|
||||
} __packed banner_id_t;
|
||||
|
||||
#define MSH_OK 0x0000
|
||||
#define MSH_OK_RESTART 0x0001
|
||||
#define MSH_FWH_ERR 0x00ff
|
||||
#define MSH_IF_BAD_ID 0x0100
|
||||
#define MSH_IF_BAD_FUNC 0x0101
|
||||
#define MSH_IF_MBI_CORRUPT 0x0102
|
||||
#define MSH_IF_BAD_HANDLE 0x0103
|
||||
#define MSH_ALRDY_ATCHED 0x0104
|
||||
#define MSH_NOT_ATCHED 0x0105
|
||||
#define MSH_IF 0x0106
|
||||
#define MSH_IF_INVADDR 0x0107
|
||||
#define MSH_IF_UKN_TYPE 0x0108
|
||||
#define MSH_IF_NOT_FOUND 0x0109
|
||||
#define MSH_IF_NO_KEY 0x010a
|
||||
#define MSH_IF_BUF_SIZE 0x010b
|
||||
#define MSH_IF_NOT_PENDING 0x010c
|
||||
|
||||
#ifdef DEBUG_SMI_I82830
|
||||
static void
|
||||
dump(u8 * addr, u32 len)
|
||||
{
|
||||
printk(BIOS_DEBUG, "\n%s(%p, %x):\n", __func__, addr, len);
|
||||
while (len) {
|
||||
unsigned int tmpCnt = len;
|
||||
unsigned char x;
|
||||
if (tmpCnt > 8)
|
||||
tmpCnt = 8;
|
||||
printk(BIOS_DEBUG, "\n%p: ", addr);
|
||||
// print hex
|
||||
while (tmpCnt--) {
|
||||
x = *addr++;
|
||||
printk(BIOS_DEBUG, "%02x ", x);
|
||||
}
|
||||
tmpCnt = len;
|
||||
if (tmpCnt > 8)
|
||||
tmpCnt = 8;
|
||||
len -= tmpCnt;
|
||||
//reset addr ptr to print ascii
|
||||
addr = addr - tmpCnt;
|
||||
// print ascii
|
||||
while (tmpCnt--) {
|
||||
x = *addr++;
|
||||
if ((x < 32) || (x >= 127)) {
|
||||
//non-printable char
|
||||
x = '.';
|
||||
}
|
||||
printk(BIOS_DEBUG, "%c", x);
|
||||
}
|
||||
}
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
banner_id_t banner;
|
||||
u16 versionmajor;
|
||||
u16 versionminor;
|
||||
u32 smicombuffersize;
|
||||
} __packed version_t;
|
||||
|
||||
typedef struct {
|
||||
u16 header_id;
|
||||
u16 attributes;
|
||||
u16 size;
|
||||
u8 name_len;
|
||||
u8 reserved;
|
||||
u32 type;
|
||||
u32 header_ext;
|
||||
u8 name[0];
|
||||
} __packed mbi_header_t;
|
||||
|
||||
typedef struct {
|
||||
banner_id_t banner;
|
||||
u64 handle;
|
||||
u32 objnum;
|
||||
mbi_header_t header;
|
||||
} __packed obj_header_t;
|
||||
|
||||
typedef struct {
|
||||
banner_id_t banner;
|
||||
u64 handle;
|
||||
u32 objnum;
|
||||
u32 start;
|
||||
u32 numbytes;
|
||||
u32 buflen;
|
||||
u32 buffer;
|
||||
} __packed get_object_t;
|
||||
|
||||
static void mbi_call(u8 subf, banner_id_t *banner_id)
|
||||
{
|
||||
#ifdef DEBUG_SMI_I82830
|
||||
printk(BIOS_DEBUG, "MBI\n");
|
||||
printk(BIOS_DEBUG, "|- sub function %x\n", subf);
|
||||
printk(BIOS_DEBUG, "|- banner id @ %x\n", (u32)banner_id);
|
||||
printk(BIOS_DEBUG, "| |- mhid %x\n", banner_id->mhid);
|
||||
printk(BIOS_DEBUG, "| |- function %x\n", banner_id->function);
|
||||
printk(BIOS_DEBUG, "| |- return status %x\n", banner_id->retsts);
|
||||
printk(BIOS_DEBUG, "| |- rfu %x\n", banner_id->rfu);
|
||||
#endif
|
||||
|
||||
switch(banner_id->function) {
|
||||
case 0x0001: {
|
||||
version_t *version;
|
||||
printk(BIOS_DEBUG, "|- MBI_QueryInterface\n");
|
||||
version = (version_t *)banner_id;
|
||||
version->banner.retsts = MSH_OK;
|
||||
version->versionmajor = 1;
|
||||
version->versionminor = 3;
|
||||
version->smicombuffersize = 0x1000;
|
||||
break;
|
||||
}
|
||||
case 0x0002:
|
||||
printk(BIOS_DEBUG, "|- MBI_Attach\n");
|
||||
printk(BIOS_DEBUG, "| |- Not Implemented!\n");
|
||||
break;
|
||||
case 0x0003:
|
||||
printk(BIOS_DEBUG, "|- MBI_Detach\n");
|
||||
printk(BIOS_DEBUG, "| |- Not Implemented!\n");
|
||||
break;
|
||||
case 0x0201: {
|
||||
obj_header_t *obj_header = (obj_header_t *)banner_id;
|
||||
mbi_header_t *mbi_header = NULL;
|
||||
printk(BIOS_DEBUG, "|- MBI_GetObjectHeader\n");
|
||||
printk(BIOS_DEBUG, "| |- objnum = %d\n", obj_header->objnum);
|
||||
|
||||
int i, count = 0;
|
||||
obj_header->banner.retsts = MSH_IF_NOT_FOUND;
|
||||
|
||||
for (i = 0; i < mbi_len;) {
|
||||
int len;
|
||||
|
||||
if (!(mbi[i] == 0xf0 && mbi [i+1] == 0xf6)) {
|
||||
i+=16;
|
||||
continue;
|
||||
}
|
||||
|
||||
mbi_header = (mbi_header_t *)&mbi[i];
|
||||
len = ALIGN((mbi_header->size * 16) + sizeof(mbi_header) + ALIGN(mbi_header->name_len, 16), 16);
|
||||
|
||||
if (obj_header->objnum == count) {
|
||||
#ifdef DEBUG_SMI_I82830
|
||||
if (mbi_header->name_len == 0xff) {
|
||||
printk(BIOS_DEBUG, "| |- corrupt.\n");
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
int headerlen = ALIGN(sizeof(mbi_header) + ALIGN(mbi_header->name_len, 16), 16);
|
||||
#ifdef DEBUG_SMI_I82830
|
||||
printk(BIOS_DEBUG, "| |- headerlen = %d\n", headerlen);
|
||||
#endif
|
||||
memcpy(&obj_header->header, mbi_header, headerlen);
|
||||
obj_header->banner.retsts = MSH_OK;
|
||||
printk(BIOS_DEBUG, "| |- MBI module '");
|
||||
int j;
|
||||
for (j = 0; j < mbi_header->name_len && mbi_header->name[j]; j++)
|
||||
printk(BIOS_DEBUG, "%c", mbi_header->name[j]);
|
||||
printk(BIOS_DEBUG, "' found.\n");
|
||||
#ifdef DEBUG_SMI_I82830
|
||||
dump((u8 *)banner_id, sizeof(obj_header_t) + ALIGN(mbi_header->name_len, 16));
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
i += len;
|
||||
count++;
|
||||
}
|
||||
if (obj_header->banner.retsts == MSH_IF_NOT_FOUND)
|
||||
printk(BIOS_DEBUG, "| |- MBI object #%d not found.\n", obj_header->objnum);
|
||||
break;
|
||||
}
|
||||
case 0x0203: {
|
||||
get_object_t *getobj = (get_object_t *)banner_id;
|
||||
mbi_header_t *mbi_header = NULL;
|
||||
printk(BIOS_DEBUG, "|- MBI_GetObject\n");
|
||||
#ifdef DEBUG_SMI_I82830
|
||||
printk(BIOS_DEBUG, "| |- handle = %016Lx\n", getobj->handle);
|
||||
#endif
|
||||
printk(BIOS_DEBUG, "| |- objnum = %d\n", getobj->objnum);
|
||||
printk(BIOS_DEBUG, "| |- start = %x\n", getobj->start);
|
||||
printk(BIOS_DEBUG, "| |- numbytes = %x\n", getobj->numbytes);
|
||||
printk(BIOS_DEBUG, "| |- buflen = %x\n", getobj->buflen);
|
||||
printk(BIOS_DEBUG, "| |- buffer = %x\n", getobj->buffer);
|
||||
|
||||
int i, count = 0;
|
||||
getobj->banner.retsts = MSH_IF_NOT_FOUND;
|
||||
|
||||
for (i = 0; i< mbi_len;) {
|
||||
int headerlen, objectlen;
|
||||
|
||||
if (!(mbi[i] == 0xf0 && mbi [i+1] == 0xf6)) {
|
||||
i+=16;
|
||||
continue;
|
||||
}
|
||||
|
||||
mbi_header = (mbi_header_t *)&mbi[i];
|
||||
headerlen = ALIGN(sizeof(mbi_header) + ALIGN(mbi_header->name_len, 16), 16);
|
||||
objectlen = ALIGN((mbi_header->size * 16), 16);
|
||||
|
||||
if (getobj->objnum == count) {
|
||||
printk(BIOS_DEBUG, "| |- len = %x\n", headerlen + objectlen);
|
||||
|
||||
memcpy((void *)(getobj->buffer + OBJ_OFFSET),
|
||||
((char *)mbi_header) + headerlen, (objectlen > getobj->buflen) ? getobj->buflen : objectlen);
|
||||
|
||||
getobj->banner.retsts = MSH_OK;
|
||||
#ifdef DEBUG_SMI_I82830
|
||||
dump((u8 *)banner_id, sizeof(*getobj));
|
||||
dump((u8 *)getobj->buffer + OBJ_OFFSET, objectlen);
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
i += (headerlen + objectlen);
|
||||
count++;
|
||||
}
|
||||
if (getobj->banner.retsts == MSH_IF_NOT_FOUND)
|
||||
printk(BIOS_DEBUG, "MBI module %d not found.\n", getobj->objnum);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
printk(BIOS_DEBUG, "|- function %x\n", banner_id->function);
|
||||
printk(BIOS_DEBUG, "| |- Unknown Function!\n");
|
||||
break;
|
||||
}
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
//dump(banner_id, 0x20);
|
||||
}
|
||||
|
||||
#define SMI_IFC_SUCCESS 1
|
||||
#define SMI_IFC_FAILURE_GENERIC 0
|
||||
#define SMI_IFC_FAILURE_INVALID 2
|
||||
#define SMI_IFC_FAILURE_CRITICAL 4
|
||||
#define SMI_IFC_FAILURE_NONCRITICAL 6
|
||||
|
||||
#define PC10 0x10
|
||||
#define PC11 0x11
|
||||
#define PC12 0x12
|
||||
#define PC13 0x13
|
||||
|
||||
static void smi_interface_call(void)
|
||||
{
|
||||
u8 *mmio = (u8 *)pci_read_config32(PCI_DEV(0, 0x02, 0), 0x14);
|
||||
// mmio &= 0xfff80000;
|
||||
// printk(BIOS_DEBUG, "mmio=%x\n", mmio);
|
||||
u16 swsmi = pci_read_config16(PCI_DEV(0, 0x02, 0), 0xe0);
|
||||
|
||||
if (!(swsmi & 1))
|
||||
return;
|
||||
|
||||
swsmi &= ~(1 << 0); // clear SMI toggle
|
||||
|
||||
switch ((swsmi>>1) & 0xf) {
|
||||
case 0:
|
||||
printk(BIOS_DEBUG, "Interface Function Presence Test.\n");
|
||||
swsmi = 0;
|
||||
swsmi &= ~(7 << 5); // Exit: Result
|
||||
swsmi |= (SMI_IFC_SUCCESS << 5);
|
||||
swsmi &= 0xff;
|
||||
swsmi |= (PC13 << 8);
|
||||
pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe0, swsmi);
|
||||
// write magic
|
||||
write32(mmio + 0x71428, 0x494e5443);
|
||||
return;
|
||||
case 4:
|
||||
printk(BIOS_DEBUG, "Get BIOS Data.\n");
|
||||
printk(BIOS_DEBUG, "swsmi=%04x\n", swsmi);
|
||||
break;
|
||||
case 5:
|
||||
printk(BIOS_DEBUG, "Call MBI Functions.\n");
|
||||
mbi_call(swsmi >> 8, (banner_id_t *)((read32(mmio + 0x71428) & 0x000fffff) + OBJ_OFFSET) );
|
||||
// swsmi = 0x0000;
|
||||
swsmi &= ~(7 << 5); // Exit: Result
|
||||
swsmi |= (SMI_IFC_SUCCESS << 5);
|
||||
pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe0, swsmi);
|
||||
return;
|
||||
case 6:
|
||||
printk(BIOS_DEBUG, "System BIOS Callbacks.\n");
|
||||
printk(BIOS_DEBUG, "swsmi=%04x\n", swsmi);
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_DEBUG, "Unknown SMI interface call %04x\n", swsmi);
|
||||
break;
|
||||
}
|
||||
|
||||
swsmi &= ~(7 << 5); // Exit: Result
|
||||
swsmi |= (SMI_IFC_FAILURE_CRITICAL << 7);
|
||||
pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe0, swsmi);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief read and clear ERRSTS
|
||||
* @return ERRSTS register
|
||||
*/
|
||||
static u16 reset_err_status(void)
|
||||
{
|
||||
u16 reg16;
|
||||
|
||||
reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), ERRSTS);
|
||||
/* set status bits are cleared by writing 1 to them */
|
||||
pci_write_config16(PCI_DEV(0, 0x00, 0), ERRSTS, reg16);
|
||||
|
||||
return reg16;
|
||||
}
|
||||
|
||||
static void dump_err_status(u32 errsts)
|
||||
{
|
||||
printk(BIOS_DEBUG, "ERRSTS: ");
|
||||
if (errsts & (1 << 12)) printk(BIOS_DEBUG, "MBI ");
|
||||
if (errsts & (1 << 9)) printk(BIOS_DEBUG, "LCKF ");
|
||||
if (errsts & (1 << 8)) printk(BIOS_DEBUG, "DTF ");
|
||||
if (errsts & (1 << 5)) printk(BIOS_DEBUG, "UNSC ");
|
||||
if (errsts & (1 << 4)) printk(BIOS_DEBUG, "OOGF ");
|
||||
if (errsts & (1 << 3)) printk(BIOS_DEBUG, "IAAF ");
|
||||
if (errsts & (1 << 2)) printk(BIOS_DEBUG, "ITTEF ");
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
}
|
||||
|
||||
void northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
|
||||
{
|
||||
u16 errsts;
|
||||
|
||||
/* We need to clear the SMI status registers, or we won't see what's
|
||||
* happening in the following calls.
|
||||
*/
|
||||
errsts = reset_err_status();
|
||||
if (errsts & (1 << 12)) {
|
||||
smi_interface_call();
|
||||
} else {
|
||||
if (errsts)
|
||||
dump_err_status(errsts);
|
||||
}
|
||||
|
||||
}
|
||||
@@ -1,87 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2009 Joseph Smith <joe@settoplinux.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <arch/io.h>
|
||||
#include <stdint.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <cbfs.h>
|
||||
#include <x86emu/x86emu.h>
|
||||
|
||||
static void vga_init(device_t dev)
|
||||
{
|
||||
printk(BIOS_INFO, "Starting Graphics Initialization\n");
|
||||
size_t mbi_len;
|
||||
void *mbi = cbfs_boot_map_with_leak("mbi.bin", CBFS_TYPE_MBI, &mbi_len);
|
||||
|
||||
if (mbi && mbi_len) {
|
||||
/* The GDT or coreboot table is going to live here. But
|
||||
* a long time after we relocated the GNVS, so this is
|
||||
* not troublesome.
|
||||
*/
|
||||
*(u32 *)0x500 = (u32)mbi;
|
||||
*(u32 *)0x504 = (u32)mbi_len;
|
||||
outb(0xeb, 0xb2);
|
||||
}
|
||||
|
||||
pci_dev_init(dev);
|
||||
printk(BIOS_INFO, "Graphics Initialization Complete\n");
|
||||
|
||||
/* Enable TV-Out */
|
||||
#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL)
|
||||
#define PIPE_A_CRT (1 << 0)
|
||||
#define PIPE_A_LFP (1 << 1)
|
||||
#define PIPE_A_TV (1 << 3)
|
||||
#define PIPE_B_CRT (1 << 8)
|
||||
#define PIPE_B_TV (1 << 10)
|
||||
printk(BIOS_DEBUG, "Enabling TV-Out\n");
|
||||
void runInt10(void);
|
||||
X86_AX = 0x5f64;
|
||||
X86_BX = 0x0001; // Set Display Device, force execution
|
||||
X86_CX = PIPE_A_CRT | PIPE_A_TV;
|
||||
// M.x86.R_CX = PIPE_B_TV;
|
||||
runInt10();
|
||||
switch (X86_AX) {
|
||||
case 0x005f:
|
||||
printk(BIOS_DEBUG, "... failed.\n");
|
||||
break;
|
||||
case 0x015f:
|
||||
printk(BIOS_DEBUG, "... ok.\n");
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_DEBUG, "... not supported.\n");
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static const struct device_operations vga_operations = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = vga_init,
|
||||
.scan_bus = 0,
|
||||
.enable = 0,
|
||||
.ops_pci = 0,
|
||||
};
|
||||
|
||||
static const struct pci_driver vga_driver __pci_driver = {
|
||||
.ops = &vga_operations,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x3577,
|
||||
};
|
||||
Reference in New Issue
Block a user