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VIA VT8237R cleanups (trivial).

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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3651 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
2008-10-12 14:40:23 +00:00
parent 2e5a9d952f
commit 0a20c41622
6 changed files with 207 additions and 182 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/southbridge/via/vt8237r/chip.h
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@@ -53,7 +53,7 @@ struct southbridge_via_vt8237r_config {
int ide0_enable:1; int ide0_enable:1;
int ide1_enable:1; int ide1_enable:1;
/* 1 = 80-pin cable */ /* 1 = 80-pin cable, 0 = 40-pin cable */
int ide0_80pin_cable:1; int ide0_80pin_cable:1;
int ide1_80pin_cable:1; int ide1_80pin_cable:1;
}; };

67
src/southbridge/via/vt8237r/vt8237_ctrl.c
View File

@@ -28,20 +28,17 @@
static void vt8237_cfg(struct device *dev) static void vt8237_cfg(struct device *dev)
{ {
u8 regm, regm2, regm3; u8 regm, regm2, regm3;
device_t devfun3; device_t devfun3;
devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8T890CE_3, 0); PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
if (!devfun3)
devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
if (!devfun3)
die("Unknown NB");
if (!devfun3) /* CPU to PCI Flow Control 1 & 2, just fill in recommended. */
devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
if (!devfun3)
die("Unknown NB");
/* CPU to PCI Flow Control 1 & 2, just fill in recommended */
pci_write_config8(dev, 0x70, 0xc2); pci_write_config8(dev, 0x70, 0xc2);
pci_write_config8(dev, 0x71, 0xc8); pci_write_config8(dev, 0x71, 0xc8);
@@ -54,7 +51,8 @@ static void vt8237_cfg(struct device *dev)
pci_write_config8(dev, 0x77, 0x48); pci_write_config8(dev, 0x77, 0x48);
pci_write_config8(dev, 0x78, 0x01); pci_write_config8(dev, 0x78, 0x01);
/* APIC on HT */ /* APIC on HT */
pci_write_config8(dev, 0x7c, 0x77); //maybe Enable LDT APIC Mode bit3 set to 1 /* Maybe Enable LDT APIC Mode bit3 set to 1 */
pci_write_config8(dev, 0x7c, 0x77);
/* WARNING: Need to copy some registers from NB (D0F3) to SB (D11F7). */ /* WARNING: Need to copy some registers from NB (D0F3) to SB (D11F7). */
@@ -89,28 +87,24 @@ static void vt8237_cfg(struct device *dev)
* NB V-Link Manual Driving Control - Data 0xb6 0x46 0x46 0x88 0x88 * NB V-Link Manual Driving Control - Data 0xb6 0x46 0x46 0x88 0x88
* NB V-Link Receiving Strobe Delay 0xb7 0x02 0x02 0x61 0x01 * NB V-Link Receiving Strobe Delay 0xb7 0x02 0x02 0x61 0x01
* NB V-Link Compensation Control bit4,0 (b5,b6) 0xb4 0x10 0x10 0x11 0x11 * NB V-Link Compensation Control bit4,0 (b5,b6) 0xb4 0x10 0x10 0x11 0x11
* SB V-Link Strobe Drive Control 0xb9 0x00 0xa5 0x98 0x98 * SB V-Link Strobe Drive Control 0xb9 0x00 0xa5 0x98 0x98
* SB V-Link Data drive Control???? 0xba 0x00 0xbb 0x77 0x77 * SB V-Link Data drive Control???? 0xba 0x00 0xbb 0x77 0x77
* SB V-Link Receive Strobe Delay???? 0xbb 0x04 0x11 0x11 0x11 * SB V-Link Receive Strobe Delay???? 0xbb 0x04 0x11 0x11 0x11
* SB V-Link Compensation Control bit0 (use b9) 0xb8 0x00 0x01 0x01 0x01 * SB V-Link Compensation Control bit0 (use b9) 0xb8 0x00 0x01 0x01 0x01
* V-Link CKG Control 0xb0 0x05 0x05 0x06 0x03 * V-Link CKG Control 0xb0 0x05 0x05 0x06 0x03
* V-Link CKG Control 0xb1 0x05 0x05 0x01 0x03 * V-Link CKG Control 0xb1 0x05 0x05 0x01 0x03
*/ */
static void vt8237s_vlink_init(struct device *dev) static void vt8237s_vlink_init(struct device *dev)
{ {
u8 reg; u8 reg;
device_t devfun7; device_t devfun7;
devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8T890CE_7, 0); PCI_DEVICE_ID_VIA_K8T890CE_7, 0);
if (!devfun7) if (!devfun7)
devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8M890CE_7, 0); PCI_DEVICE_ID_VIA_K8M890CE_7, 0);
/* No pairing NB was found. */
/* no pairing NB found */
if (!devfun7) if (!devfun7)
return; return;
@@ -132,40 +126,43 @@ static void vt8237s_vlink_init(struct device *dev)
pci_write_config8(dev, 0xba, 0x88); pci_write_config8(dev, 0xba, 0x88);
pci_write_config8(dev, 0xbb, 0x89); pci_write_config8(dev, 0xbb, 0x89);
reg = pci_read_config8(dev, 0xbd); reg = pci_read_config8(dev, 0xbd);
reg |= 0x3; reg |= 0x3;
pci_write_config8(dev, 0xbd, reg); pci_write_config8(dev, 0xbd, reg);
/* Program V-link 8X 8bit full duplex, parity disabled FIXME */ /* Program V-link 8X 8bit full duplex, parity disabled. FIXME. */
pci_write_config8(dev, 0x48, 0x13); pci_write_config8(dev, 0x48, 0x13);
} }
static void ctrl_enable(struct device *dev) { static void ctrl_enable(struct device *dev)
{
/* enable the 0:13 and 0:13.1 */ /* Enable the 0:13 and 0:13.1. */
/* FIXME */ /* FIXME */
pci_write_config8(dev, 0x4f, 0x43); pci_write_config8(dev, 0x4f, 0x43);
} }
extern void dump_south(device_t dev); extern void dump_south(device_t dev);
static void ctrl_init(struct device *dev) { static void ctrl_init(struct device *dev)
{
/*
* TODO: Fix some ordering issue for V-link set Rx77[6] and
* PCI1_Rx4F[0] should to 1.
* FIXME DO you need?
*/
/* TODO: Fix some ordering issue fo V-link set Rx77[6] and PCI1_Rx4F[0] /*
should to 1 FIXME DO you need?*/ * VT8237R specific configuration. Other SB are done in their own
* directories. TODO: Add A version.
/* VT8237R specific configuration other SB are done in their own directories */ */
/* add A version */
device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA, device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237S_LPC, 0); PCI_DEVICE_ID_VIA_VT8237S_LPC, 0);
if (devsb) { if (devsb) {
/* FIXME: Skip v-link setup for now */ /* FIXME: Skip v-link setup for now. */
// vt8237s_vlink_init(dev); // vt8237s_vlink_init(dev);
} }
/* configure PCI1 and copy mirror registers from D0F3 */ /* Configure PCI1 and copy mirror registers from D0F3. */
vt8237_cfg(dev); vt8237_cfg(dev);
dump_south(dev); dump_south(dev);
} }

3
src/southbridge/via/vt8237r/vt8237r.c
View File

@@ -63,9 +63,8 @@ void dump_south(device_t dev)
for (i = 0; i < 256; i += 16) { for (i = 0; i < 256; i += 16) {
printk_debug("%02x: ", i); printk_debug("%02x: ", i);
for (j = 0; j < 16; j++) { for (j = 0; j < 16; j++)
printk_debug("%02x ", pci_read_config8(dev, i + j)); printk_debug("%02x ", pci_read_config8(dev, i + j));
}
printk_debug("\n"); printk_debug("\n");
} }
} }

191
src/southbridge/via/vt8237r/vt8237r_early_smbus.c
View File

@@ -128,27 +128,27 @@ u8 smbus_read_byte(u8 dimm, u8 offset)
return val; return val;
} }
/** /**
* Enable the smbus on vt8237r-based systems * Enable the SMBus on VT8237R-based systems.
*/ */
void enable_smbus(void) void enable_smbus(void)
{ {
device_t dev; device_t dev;
/* Power management controller */ /* Power management controller */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID) { if (dev == PCI_DEV_INVALID) {
/* Power management controller */ /* Power management controller */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
if (dev == PCI_DEV_INVALID) if (dev == PCI_DEV_INVALID)
die("Power management controller not found\r\n"); die("Power management controller not found\r\n");
} }
/* 7 = SMBus Clock from RTC 32.768KHz /*
* 7 = SMBus Clock from RTC 32.768KHz
* 5 = Internal PLL reset from susp * 5 = Internal PLL reset from susp
*/ */
pci_write_config8(dev, VT8237R_POWER_WELL, 0xa0); pci_write_config8(dev, VT8237R_POWER_WELL, 0xa0);
@@ -201,7 +201,7 @@ void smbus_fixup(const struct mem_controller *ctrl)
* VT8237R has only been seen on DDR and DDR2 based systems, so far. * VT8237R has only been seen on DDR and DDR2 based systems, so far.
*/ */
for (i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) || for (i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) ||
(result > SPD_MEMORY_TYPE_SDRAM_DDR3))); i++) { (result > SPD_MEMORY_TYPE_SDRAM_DDR3))); i++) {
if (current_slot > ram_slots) if (current_slot > ram_slots)
current_slot = 0; current_slot = 0;
@@ -218,88 +218,100 @@ void smbus_fixup(const struct mem_controller *ctrl)
PRINT_DEBUG("Done\r\n"); PRINT_DEBUG("Done\r\n");
} }
/* fixme better separate the NB and SB, will done once it works */ /* FIXME: Better separate the NB and SB, will be done once it works. */
void vt8237_sb_enable_fid_vid(void) { void vt8237_sb_enable_fid_vid(void)
device_t dev; {
device_t devctl; device_t dev, devctl;
/* Power management controller */ /* Power management controller */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID) { if (dev == PCI_DEV_INVALID) {
/* Power management controller */ /* Power management controller */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
if (dev == PCI_DEV_INVALID) if (dev == PCI_DEV_INVALID)
return; return;
devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237_VLINK), 0); PCI_DEVICE_ID_VIA_VT8237_VLINK), 0);
if (devctl == PCI_DEV_INVALID) if (devctl == PCI_DEV_INVALID)
return; return;
/* TODO: Why is this an extra block? */
{ {
u8 tmp; u8 tmp;
tmp = pci_read_config8(devctl, 0xec); tmp = pci_read_config8(devctl, 0xec);
print_debug("EC is "); print_debug("EC is ");
print_debug_hex8(tmp); print_debug_hex8(tmp);
print_debug(" E5 is "); print_debug(" E5 is ");
tmp = pci_read_config8(dev, 0xe5); tmp = pci_read_config8(dev, 0xe5);
print_debug_hex8(tmp); print_debug_hex8(tmp);
} }
/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
/* Enable ACPI accessm RTC signal gated with PSON. */ /* Enable ACPI accessm RTC signal gated with PSON. */
pci_write_config8(dev, 0x81, 0x84); pci_write_config8(dev, 0x81, 0x84);
/* Allow SLP# signal to assert LDTSTOP_L.
/*
* Allow SLP# signal to assert LDTSTOP_L.
* Will work for C3 and for FID/VID change. * Will work for C3 and for FID/VID change.
*/ */
/* fixme */ /* FIXME */
outb(0xff, VT8237R_ACPI_IO_BASE + 0x50); //fixme maybe not needed outb(0xff, VT8237R_ACPI_IO_BASE + 0x50); /* Maybe unneeded? */
// outb(0x4, VT8237R_ACPI_IO_BASE + 0x50); /* Maybe unneeded? */
// outb(0x4, VT8237R_ACPI_IO_BASE + 0x50); //fixme maybe not needed /* It seems for AMD LDTSTP is connected not to SLP anymore. */
/* Enable 0: DPSLP# / DPRSTP# / VRDSLP */
/* it seems for AMD LDTSTP is connected not to SLP anymore */ /*
/* enable 0: DPSLP# / DPRSTP# / VRDSLP */ * Enable SATA LED, VR timer = 100us.
* Enable DPSLP# / DPRSTP# / VRDSLP - WARNING LDTSTP connetcs
/* Enable SATA LED, VR timer = 100us * to some of those pins! (and not to SLP as on R ver).
* Enable DPSLP# / DPRSTP# / VRDSLP - WARNING LDTSTP connetcs to some of those pins! (and not to SLP as on R ver)
*/ */
//fixme pci_write_config8(dev, 0xe5, 0x69); /* FIXME */
pci_write_config8(dev, 0xe5, 0x69);
/* REQ5 as PCI request input - should be together with INTE-INTH. /*
* Fast VR timer disable - need for LDTSTP signal * REQ5 as PCI request input - should be together with
*/ * INTE-INTH. Fast VR timer disable - need for LDTSTP signal.
*/
pci_write_config8(dev, 0xe4, 0xa5); pci_write_config8(dev, 0xe4, 0xa5);
/* reduce further the STPCLK/LDTSTP signal to 5us */ /* Reduce further the STPCLK/LDTSTP signal to 5us. */
pci_write_config8(dev, 0xec, 0x4); pci_write_config8(dev, 0xec, 0x4);
/* Host Bus Power Management Control, maybe not needed */
/* Host Bus Power Management Control, maybe not needed. */
pci_write_config8(dev, 0x8c, 0x5); pci_write_config8(dev, 0x8c, 0x5);
/* so the chip knows we are on AMD */ /* So the chip knows we are on AMD. */
pci_write_config8(devctl, 0x7c, 0x77); pci_write_config8(devctl, 0x7c, 0x77);
devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
0x2336), 0); 0x2336), 0);
if (devctl == PCI_DEV_INVALID) if (devctl == PCI_DEV_INVALID)
return; return;
/* Enable C2NOW delay to PSTATECTL VID / FID Change Delay to P-State Control */
/*
* Enable C2NOW delay to PSTATECTL VID / FID Change Delay
* to P-State Control.
*/
pci_write_config8(devctl, 0xa6, 0x83); pci_write_config8(devctl, 0xa6, 0x83);
//return; //FIXME fall through some revs have it old way // return; // FIXME: Fall through some revs have it old way.
} }
/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
/* Enable ACPI accessm RTC signal gated with PSON. */ /* Enable ACPI accessm RTC signal gated with PSON. */
pci_write_config8(dev, 0x81, 0x84); pci_write_config8(dev, 0x81, 0x84);
/* Allow SLP# signal to assert LDTSTOP_L.
/*
* Allow SLP# signal to assert LDTSTOP_L.
* Will work for C3 and for FID/VID change. * Will work for C3 and for FID/VID change.
*/ */
outb(0x1, VT8237R_ACPI_IO_BASE + 0x11); outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
@@ -312,97 +324,97 @@ void enable_rom_decode(void)
/* Power management controller */ /* Power management controller */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID) { if (dev == PCI_DEV_INVALID) {
/* Power management controller */ /* Power management controller */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
if (dev == PCI_DEV_INVALID) if (dev == PCI_DEV_INVALID)
return; return;
} }
/* ROM decode last 1MB FFC00000 - FFFFFFFF */ /* ROM decode last 1MB FFC00000 - FFFFFFFF. */
pci_write_config8(dev, 0x41, 0x7f); pci_write_config8(dev, 0x41, 0x7f);
} }
void vt8237_early_spi_init(void) { void vt8237_early_spi_init(void)
{
device_t dev; device_t dev;
volatile u16 *spireg; volatile u16 *spireg;
u32 tmp; u32 tmp;
/* Bus Control and Power Management */ /* Bus Control and Power Management */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
if (dev == PCI_DEV_INVALID) if (dev == PCI_DEV_INVALID)
die("SB not found\r\n"); die("SB not found\r\n");
/* put SPI base 20 d0 fe */ /* Put SPI base 20 d0 fe. */
tmp = pci_read_config32(dev, 0xbc); tmp = pci_read_config32(dev, 0xbc);
pci_write_config32(dev, 0xbc, (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000)); pci_write_config32(dev, 0xbc,
(VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000));
/* set SPI clock to 33MHz */ /* Set SPI clock to 33MHz. */
spireg = (u16 *) (VT8237S_SPI_MEM_BASE + 0x6c); spireg = (u16 *) (VT8237S_SPI_MEM_BASE + 0x6c);
(*spireg) &= 0xff00; (*spireg) &= 0xff00;
} }
/* offset 0x58 /*
* Offset 0x58:
* 31:20 reserved * 31:20 reserved
* 19:16 4 bit position in shadow EEPROM * 19:16 4 bit position in shadow EEPROM
* 15:0 data to write * 15:0 data to write
* *
* offset 0x5c * Offset 0x5c:
* 31:28 reserved * 31:28 reserved
* 27 ERDBG - enable read from 0x5c * 27 ERDBG - enable read from 0x5c
* 26 reserved * 26 reserved
* 25 SEELD * 25 SEELD
* 24 SEEPR - write 1 when done updating, wait until SEELD is set to 1, sticky * 24 SEEPR - write 1 when done updating, wait until SEELD is
* set to 1, sticky
* cleared by reset, if it is 1 writing is disabled * cleared by reset, if it is 1 writing is disabled
* 19:16 4 bit position in shadow EEPROM * 19:16 4 bit position in shadow EEPROM
* 15:0 data from shadow EEPROM * 15:0 data from shadow EEPROM
* *
* after PCIRESET SEELD and SEEPR must be 1 and 1 * After PCIRESET SEELD and SEEPR must be 1 and 1.
*/ */
/* 1 = needs PCI reset, 0 don't reset, network initialized */ /* 1 = needs PCI reset, 0 don't reset, network initialized. */
/* fixme maybe close the debug register after use? */ /* FIXME: Maybe close the debug register after use? */
#define LAN_TIMEOUT 0x7FFFFFFF #define LAN_TIMEOUT 0x7FFFFFFF
int vt8237_early_network_init(struct vt8237_network_rom *rom) { int vt8237_early_network_init(struct vt8237_network_rom *rom)
{
struct vt8237_network_rom n; struct vt8237_network_rom n;
int loops; int i, loops;
device_t dev; device_t dev;
u32 tmp; u32 tmp;
u8 status; u8 status;
u16 *rom_write; u16 *rom_write;
unsigned int checksum; unsigned int checksum;
int i;
/* Network adapter */ /* Network adapter */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_8233_7), 0); PCI_DEVICE_ID_VIA_8233_7), 0);
if (dev == PCI_DEV_INVALID) { if (dev == PCI_DEV_INVALID) {
print_err("Network is disabled, please enable\n"); print_err("Network is disabled, please enable\n");
return 0; return 0;
} }
tmp = pci_read_config32(dev, 0x5c); tmp = pci_read_config32(dev, 0x5c);
/* enable ERDBG */ tmp |= 0x08000000; /* Enable ERDBG. */
tmp |= 0x08000000;
pci_write_config32(dev, 0x5c, tmp); pci_write_config32(dev, 0x5c, tmp);
status = ((pci_read_config32(dev, 0x5c) >> 24) & 0x3); status = ((pci_read_config32(dev, 0x5c) >> 24) & 0x3);
if (status == 3) { /* Network controller OK, EEPROM loaded. */
/* network controller OK, EEPROM loaded */ if (status == 3)
return 0; return 0;
}
if (rom == NULL) { if (rom == NULL) {
print_err("No configuration data specified, using default MAC!\n"); print_err("No config data specified, using default MAC!\n");
n.mac_address[0] = 0x0; n.mac_address[0] = 0x0;
n.mac_address[1] = 0x0; n.mac_address[1] = 0x0;
n.mac_address[2] = 0xde; n.mac_address[2] = 0xde;
@@ -434,37 +446,38 @@ int vt8237_early_network_init(struct vt8237_network_rom *rom) {
rom_write = (u16 *) rom; rom_write = (u16 *) rom;
checksum = 0; checksum = 0;
/* write all data except checksum and second to last byte */ /* Write all data except checksum and second to last byte. */
tmp &= 0xff000000; /* leave reserved bits in */ tmp &= 0xff000000; /* Leave reserved bits in. */
for (i = 0; i < 15; i++) { for (i = 0; i < 15; i++) {
pci_write_config32(dev, 0x58, tmp | (i << 16) | rom_write[i]); pci_write_config32(dev, 0x58, tmp | (i << 16) | rom_write[i]);
/* lame code fixme */ /* Lame code FIXME */
checksum += rom_write[i] & 0xff; checksum += rom_write[i] & 0xff;
//checksum %= 256; /* checksum %= 256; */
checksum += (rom_write[i] >> 8) & 0xff; checksum += (rom_write[i] >> 8) & 0xff;
//checksum %= 256; /* checksum %= 256; */
} }
checksum += (rom_write[15] & 0xff); checksum += (rom_write[15] & 0xff);
checksum = ~(checksum & 0xff); checksum = ~(checksum & 0xff);
tmp |= (((checksum & 0xff) << 8) | rom_write[15]); tmp |= (((checksum & 0xff) << 8) | rom_write[15]);
/* write last byte and checksum */ /* Write last byte and checksum. */
pci_write_config32(dev, 0x58, (15 << 16) | tmp); pci_write_config32(dev, 0x58, (15 << 16) | tmp);
tmp = pci_read_config32(dev, 0x5c); tmp = pci_read_config32(dev, 0x5c);
pci_write_config32(dev, 0x5c, tmp | 0x01000000); /* toggle SEEPR */ pci_write_config32(dev, 0x5c, tmp | 0x01000000); /* Toggle SEEPR. */
/* Yes, this is a mess, but it's the easiest way to do it. */ /* Yes, this is a mess, but it's the easiest way to do it. */
while ( (((pci_read_config32(dev, 0x5c) >> 25) & 1) == 0) while ((((pci_read_config32(dev, 0x5c) >> 25) & 1) == 0)
&& (loops < LAN_TIMEOUT)) && (loops < LAN_TIMEOUT)) {
++loops; ++loops;
if (loops >= LAN_TIMEOUT) {
print_err("Timout - LAN controller did not accept configuration\n");
return 0;
} }
/* we are done, config will be used after PCIRST# */ if (loops >= LAN_TIMEOUT) {
print_err("Timeout - LAN controller didn't accept config\n");
return 0;
}
/* We are done, config will be used after PCIRST#. */
return 1; return 1;
} }

68
src/southbridge/via/vt8237r/vt8237r_lpc.c
View File

@@ -54,8 +54,8 @@ static struct ioapicreg {
} ioapic_table[] = { } ioapic_table[] = {
/* IO-APIC virtual wire mode configuration. */ /* IO-APIC virtual wire mode configuration. */
/* mask, trigger, polarity, destination, delivery, vector */ /* mask, trigger, polarity, destination, delivery, vector */
{0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | {0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST |
ExtINT, NONE}, ExtINT, NONE}, {
{1, DISABLED, NONE}, {1, DISABLED, NONE},
{2, DISABLED, NONE}, {2, DISABLED, NONE},
{3, DISABLED, NONE}, {3, DISABLED, NONE},
@@ -167,13 +167,15 @@ static void setup_pm(device_t dev)
/* GP Timer Control 1s */ /* GP Timer Control 1s */
pci_write_config8(dev, 0x93, 0x88); pci_write_config8(dev, 0x93, 0x88);
/* 7 = SMBus clock from RTC 32.768KHz /*
* 7 = SMBus clock from RTC 32.768KHz
* 5 = Internal PLL reset from susp * 5 = Internal PLL reset from susp
* 2 = GPO2 is GPIO * 2 = GPO2 is GPIO
*/ */
pci_write_config8(dev, 0x94, 0xa4); pci_write_config8(dev, 0x94, 0xa4);
/* 7 = stp to sust delay 1msec /*
* 7 = stp to sust delay 1msec
* 6 = SUSST# Deasserted Before PWRGD for STD * 6 = SUSST# Deasserted Before PWRGD for STD
* 4 = PWRGOOD reset on VT8237A/S * 4 = PWRGOOD reset on VT8237A/S
* 3 = GPO26/GPO27 is GPO * 3 = GPO26/GPO27 is GPO
@@ -216,14 +218,14 @@ static void setup_pm(device_t dev)
/* SCI is generated for RTC/pwrBtn/slpBtn. */ /* SCI is generated for RTC/pwrBtn/slpBtn. */
outw(0x001, VT8237R_ACPI_IO_BASE + 0x04); outw(0x001, VT8237R_ACPI_IO_BASE + 0x04);
} }
static void vt8237r_init(struct device *dev)
static void vt8237r_init(struct device *dev) { {
u8 enables; u8 enables;
/* Enable SATA LED, disable special CPU Frequency Change - /*
* Enable SATA LED, disable special CPU Frequency Change -
* GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs. * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
*/ */
pci_write_config8(dev, 0xe5, 0x9); pci_write_config8(dev, 0xe5, 0x9);
@@ -236,14 +238,18 @@ static void vt8237r_init(struct device *dev) {
enables |= 0x08; enables |= 0x08;
pci_write_config8(dev, 0x4f, enables); pci_write_config8(dev, 0x4f, enables);
/* Set Read Pass Write Control Enable (force A2 from APIC FSB to low). */ /*
* Set Read Pass Write Control Enable
* (force A2 from APIC FSB to low).
*/
pci_write_config8(dev, 0x48, 0x8c); pci_write_config8(dev, 0x48, 0x8c);
southbridge_init_common(dev); southbridge_init_common(dev);
/* FIXME: Intel needs more bit set for C2/C3. */ /* FIXME: Intel needs more bit set for C2/C3. */
/* Allow SLP# signal to assert LDTSTOP_L. /*
* Allow SLP# signal to assert LDTSTOP_L.
* Will work for C3 and for FID/VID change. * Will work for C3 and for FID/VID change.
*/ */
outb(0x1, VT8237R_ACPI_IO_BASE + 0x11); outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
@@ -253,39 +259,42 @@ static void vt8237s_init(struct device *dev)
{ {
u32 tmp; u32 tmp;
/* put SPI base VT8237S_SPI_MEM_BASE */ /* Put SPI base VT8237S_SPI_MEM_BASE. */
tmp = pci_read_config32(dev, 0xbc); tmp = pci_read_config32(dev, 0xbc);
pci_write_config32(dev, 0xbc, (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000)); pci_write_config32(dev, 0xbc,
(VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000));
/* Enable SATA LED, VR timer = 100us, VR timer should be fixed */
/* Enable SATA LED, VR timer = 100us, VR timer should be fixed. */
pci_write_config8(dev, 0xe5, 0x69); pci_write_config8(dev, 0xe5, 0x69);
/* REQ5 as PCI request input - should be together with INTE-INTH. /*
* Fast VR timer disable - need for LDTSTOP_L signal * REQ5 as PCI request input - should be together with INTE-INTH.
*/ * Fast VR timer disable - need for LDTSTOP_L signal.
*/
pci_write_config8(dev, 0xe4, 0xa5); pci_write_config8(dev, 0xe4, 0xa5);
/* reduce further the STPCLK/LDTSTP signal to 5us */ /* Reduce further the STPCLK/LDTSTP signal to 5us. */
pci_write_config8(dev, 0xec, 0x4); pci_write_config8(dev, 0xec, 0x4);
/* Host Bus Power Management Control, maybe not needed */ /* Host Bus Power Management Control, maybe not needed */
pci_write_config8(dev, 0x8c, 0x5); pci_write_config8(dev, 0x8c, 0x5);
/* Enable HPET at VT8237R_HPET_ADDR., does not work correctly on R */ /* Enable HPET at VT8237R_HPET_ADDR., does not work correctly on R. */
pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80)); pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80));
southbridge_init_common(dev); southbridge_init_common(dev);
/* FIXME: Intel needs more bit set for C2/C3. */ /* FIXME: Intel needs more bit set for C2/C3. */
/* Allow SLP# signal to assert LDTSTOP_L. /*
* Will work for C3 and for FID/VID change. FIXME FIXME, pre rev A2 * Allow SLP# signal to assert LDTSTOP_L.
* Will work for C3 and for FID/VID change. FIXME FIXME, pre rev A2.
*/ */
outb(0xff, VT8237R_ACPI_IO_BASE + 0x50); outb(0xff, VT8237R_ACPI_IO_BASE + 0x50);
dump_south(dev); dump_south(dev);
} }
static void vt8237_common_init(struct device *dev) static void vt8237_common_init(struct device *dev)
{ {
u8 enables, byte; u8 enables, byte;
@@ -315,7 +324,8 @@ static void vt8237_common_init(struct device *dev)
*/ */
pci_write_config8(dev, 0x41, 0x7f); pci_write_config8(dev, 0x41, 0x7f);
/* Set bit 6 of 0x40 (I/O recovery time). /*
* Set bit 6 of 0x40 (I/O recovery time).
* IMPORTANT FIX - EISA = ECLR reg at 0x4d0! Decoding must be on so * IMPORTANT FIX - EISA = ECLR reg at 0x4d0! Decoding must be on so
* that PCI interrupts can be properly marked as level triggered. * that PCI interrupts can be properly marked as level triggered.
*/ */
@@ -338,11 +348,12 @@ static void vt8237_common_init(struct device *dev)
pci_write_config8(dev, 0x59, 0x80); pci_write_config8(dev, 0x59, 0x80);
/* /*
* bit meaning * Bit | Meaning
* 3 Bypass APIC De-Assert Message (1=Enable) * -------------
* 1 possibly "INTE#, INTF#, INTG#, INTH# as PCI" * 3 | Bypass APIC De-Assert Message (1=Enable)
* bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch * 1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI"
* 0 Dynamic Clock Gating Main Switch (1=Enable) * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
* 0 | Dynamic Clock Gating Main Switch (1=Enable)
*/ */
pci_write_config8(dev, 0x5b, 0xb); pci_write_config8(dev, 0x5b, 0xb);
@@ -410,7 +421,6 @@ static const struct device_operations vt8237r_lpc_ops_s = {
.scan_bus = scan_static_bus, .scan_bus = scan_static_bus,
}; };
static const struct device_operations vt8237r_lpc_ops_r = { static const struct device_operations vt8237r_lpc_ops_r = {
.read_resources = vt8237r_read_resources, .read_resources = vt8237r_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,

22
src/southbridge/via/vt8237r/vt8237r_sata.c
View File

@@ -43,14 +43,19 @@ static void sata_i_init(struct device *dev)
return; return;
} }
static void sata_ii_init(struct device *dev) { static void sata_ii_init(struct device *dev)
{
u8 reg; u8 reg;
sata_i_init(dev); sata_i_init(dev);
/* analog black magic, you may or may not need to adjust 0x60-0x6f, depends on PCB */ /*
* Analog black magic, you may or may not need to adjust 0x60-0x6f,
* depends on PCB.
*/
/* Analog PHY - gen1 /*
* Analog PHY - gen1
* CDR bandwidth [6:5] = 3 * CDR bandwidth [6:5] = 3
* Squelch Window Select [4:3] = 1 * Squelch Window Select [4:3] = 1
* CDR Charge Pump [2:0] = 1 * CDR Charge Pump [2:0] = 1
@@ -58,18 +63,19 @@ static void sata_ii_init(struct device *dev) {
pci_write_config8(dev, 0x64, 0x49); pci_write_config8(dev, 0x64, 0x49);
/* adjust driver current source value to 9 */ /* Adjust driver current source value to 9. */
reg = pci_read_config8(dev, 0x65); reg = pci_read_config8(dev, 0x65);
reg &= 0xf0; reg &= 0xf0;
reg |= 0x9; reg |= 0x9;
pci_write_config8(dev, 0x65, reg); pci_write_config8(dev, 0x65, reg);
/* set all manual termination 50ohm bits [2:0] and enable [4] */ /* Set all manual termination 50ohm bits [2:0] and enable [4]. */
reg = pci_read_config8(dev, 0x6a); reg = pci_read_config8(dev, 0x6a);
reg |= 0xf; reg |= 0xf;
pci_write_config8(dev, 0x6a, reg); pci_write_config8(dev, 0x6a, reg);
/* Analog PHY - gen2 /*
* Analog PHY - gen2
* CDR bandwidth [5:4] = 2 * CDR bandwidth [5:4] = 2
* Pre / De-emphasis Level [7:6] controls bits [3:2], rest in 0x6e * Pre / De-emphasis Level [7:6] controls bits [3:2], rest in 0x6e
* CDR Charge Pump [2:0] = 1 * CDR Charge Pump [2:0] = 1
@@ -80,10 +86,10 @@ static void sata_ii_init(struct device *dev) {
reg |= 0x61; reg |= 0x61;
pci_write_config8(dev, 0x6f, reg); pci_write_config8(dev, 0x6f, reg);
/* check if staggered spinup is supported */ /* Check if staggered spinup is supported. */
reg = pci_read_config8(dev, 0x83); reg = pci_read_config8(dev, 0x83);
if ((reg & 0x8) == 0) { if ((reg & 0x8) == 0) {
/* start OOB sequence on both drives */ /* Start OOB sequence on both drives. */
reg |= 0x30; reg |= 0x30;
pci_write_config8(dev, 0x83, reg); pci_write_config8(dev, 0x83, reg);
} }